rt2x00: Restrict interface between rt2x00link and drivers
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt73usb.c
1 /*
2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt73usb
23         Abstract: rt73usb device specific routines.
24         Supported chipsets: rt2571W & rt2671.
25  */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/usb.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00usb.h"
37 #include "rt73usb.h"
38
39 /*
40  * Allow hardware encryption to be disabled.
41  */
42 static int modparam_nohwcrypt = 0;
43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
46 /*
47  * Register access.
48  * All access to the CSR registers will go through the methods
49  * rt2x00usb_register_read and rt2x00usb_register_write.
50  * BBP and RF register require indirect register access,
51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
52  * These indirect registers work with busy bits,
53  * and we will try maximal REGISTER_BUSY_COUNT times to access
54  * the register while taking a REGISTER_BUSY_DELAY us delay
55  * between each attampt. When the busy bit is still set at that time,
56  * the access attempt is considered to have failed,
57  * and we will print an error.
58  * The _lock versions must be used if you already hold the csr_mutex
59  */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61         rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
62 #define WAIT_FOR_RF(__dev, __reg) \
63         rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
64
65 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
66                               const unsigned int word, const u8 value)
67 {
68         u32 reg;
69
70         mutex_lock(&rt2x00dev->csr_mutex);
71
72         /*
73          * Wait until the BBP becomes available, afterwards we
74          * can safely write the new data into the register.
75          */
76         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
77                 reg = 0;
78                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
79                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
80                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
81                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
82
83                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
84         }
85
86         mutex_unlock(&rt2x00dev->csr_mutex);
87 }
88
89 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
90                              const unsigned int word, u8 *value)
91 {
92         u32 reg;
93
94         mutex_lock(&rt2x00dev->csr_mutex);
95
96         /*
97          * Wait until the BBP becomes available, afterwards we
98          * can safely write the read request into the register.
99          * After the data has been written, we wait until hardware
100          * returns the correct value, if at any time the register
101          * doesn't become available in time, reg will be 0xffffffff
102          * which means we return 0xff to the caller.
103          */
104         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
105                 reg = 0;
106                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
107                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
109
110                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
111
112                 WAIT_FOR_BBP(rt2x00dev, &reg);
113         }
114
115         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
116
117         mutex_unlock(&rt2x00dev->csr_mutex);
118 }
119
120 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
121                              const unsigned int word, const u32 value)
122 {
123         u32 reg;
124
125         if (!word)
126                 return;
127
128         mutex_lock(&rt2x00dev->csr_mutex);
129
130         /*
131          * Wait until the RF becomes available, afterwards we
132          * can safely write the new data into the register.
133          */
134         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
135                 reg = 0;
136                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
137                 /*
138                  * RF5225 and RF2527 contain 21 bits per RF register value,
139                  * all others contain 20 bits.
140                  */
141                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
142                                    20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
143                                          rt2x00_rf(&rt2x00dev->chip, RF2527)));
144                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
145                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
146
147                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
148                 rt2x00_rf_write(rt2x00dev, word, value);
149         }
150
151         mutex_unlock(&rt2x00dev->csr_mutex);
152 }
153
154 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
155 static const struct rt2x00debug rt73usb_rt2x00debug = {
156         .owner  = THIS_MODULE,
157         .csr    = {
158                 .read           = rt2x00usb_register_read,
159                 .write          = rt2x00usb_register_write,
160                 .flags          = RT2X00DEBUGFS_OFFSET,
161                 .word_base      = CSR_REG_BASE,
162                 .word_size      = sizeof(u32),
163                 .word_count     = CSR_REG_SIZE / sizeof(u32),
164         },
165         .eeprom = {
166                 .read           = rt2x00_eeprom_read,
167                 .write          = rt2x00_eeprom_write,
168                 .word_base      = EEPROM_BASE,
169                 .word_size      = sizeof(u16),
170                 .word_count     = EEPROM_SIZE / sizeof(u16),
171         },
172         .bbp    = {
173                 .read           = rt73usb_bbp_read,
174                 .write          = rt73usb_bbp_write,
175                 .word_base      = BBP_BASE,
176                 .word_size      = sizeof(u8),
177                 .word_count     = BBP_SIZE / sizeof(u8),
178         },
179         .rf     = {
180                 .read           = rt2x00_rf_read,
181                 .write          = rt73usb_rf_write,
182                 .word_base      = RF_BASE,
183                 .word_size      = sizeof(u32),
184                 .word_count     = RF_SIZE / sizeof(u32),
185         },
186 };
187 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
188
189 #ifdef CONFIG_RT2X00_LIB_LEDS
190 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
191                                    enum led_brightness brightness)
192 {
193         struct rt2x00_led *led =
194            container_of(led_cdev, struct rt2x00_led, led_dev);
195         unsigned int enabled = brightness != LED_OFF;
196         unsigned int a_mode =
197             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
198         unsigned int bg_mode =
199             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
200
201         if (led->type == LED_TYPE_RADIO) {
202                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
203                                    MCU_LEDCS_RADIO_STATUS, enabled);
204
205                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
206                                             0, led->rt2x00dev->led_mcu_reg,
207                                             REGISTER_TIMEOUT);
208         } else if (led->type == LED_TYPE_ASSOC) {
209                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
210                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
211                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
212                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
213
214                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
215                                             0, led->rt2x00dev->led_mcu_reg,
216                                             REGISTER_TIMEOUT);
217         } else if (led->type == LED_TYPE_QUALITY) {
218                 /*
219                  * The brightness is divided into 6 levels (0 - 5),
220                  * this means we need to convert the brightness
221                  * argument into the matching level within that range.
222                  */
223                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
224                                             brightness / (LED_FULL / 6),
225                                             led->rt2x00dev->led_mcu_reg,
226                                             REGISTER_TIMEOUT);
227         }
228 }
229
230 static int rt73usb_blink_set(struct led_classdev *led_cdev,
231                              unsigned long *delay_on,
232                              unsigned long *delay_off)
233 {
234         struct rt2x00_led *led =
235             container_of(led_cdev, struct rt2x00_led, led_dev);
236         u32 reg;
237
238         rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
239         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
240         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
241         rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
242
243         return 0;
244 }
245
246 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
247                              struct rt2x00_led *led,
248                              enum led_type type)
249 {
250         led->rt2x00dev = rt2x00dev;
251         led->type = type;
252         led->led_dev.brightness_set = rt73usb_brightness_set;
253         led->led_dev.blink_set = rt73usb_blink_set;
254         led->flags = LED_INITIALIZED;
255 }
256 #endif /* CONFIG_RT2X00_LIB_LEDS */
257
258 /*
259  * Configuration handlers.
260  */
261 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
262                                      struct rt2x00lib_crypto *crypto,
263                                      struct ieee80211_key_conf *key)
264 {
265         struct hw_key_entry key_entry;
266         struct rt2x00_field32 field;
267         int timeout;
268         u32 mask;
269         u32 reg;
270
271         if (crypto->cmd == SET_KEY) {
272                 /*
273                  * rt2x00lib can't determine the correct free
274                  * key_idx for shared keys. We have 1 register
275                  * with key valid bits. The goal is simple, read
276                  * the register, if that is full we have no slots
277                  * left.
278                  * Note that each BSS is allowed to have up to 4
279                  * shared keys, so put a mask over the allowed
280                  * entries.
281                  */
282                 mask = (0xf << crypto->bssidx);
283
284                 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
285                 reg &= mask;
286
287                 if (reg && reg == mask)
288                         return -ENOSPC;
289
290                 key->hw_key_idx += reg ? ffz(reg) : 0;
291
292                 /*
293                  * Upload key to hardware
294                  */
295                 memcpy(key_entry.key, crypto->key,
296                        sizeof(key_entry.key));
297                 memcpy(key_entry.tx_mic, crypto->tx_mic,
298                        sizeof(key_entry.tx_mic));
299                 memcpy(key_entry.rx_mic, crypto->rx_mic,
300                        sizeof(key_entry.rx_mic));
301
302                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
303                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
304                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
305                                                     USB_VENDOR_REQUEST_OUT, reg,
306                                                     &key_entry,
307                                                     sizeof(key_entry),
308                                                     timeout);
309
310                 /*
311                  * The cipher types are stored over 2 registers.
312                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
313                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
314                  * Using the correct defines correctly will cause overhead,
315                  * so just calculate the correct offset.
316                  */
317                 if (key->hw_key_idx < 8) {
318                         field.bit_offset = (3 * key->hw_key_idx);
319                         field.bit_mask = 0x7 << field.bit_offset;
320
321                         rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
322                         rt2x00_set_field32(&reg, field, crypto->cipher);
323                         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
324                 } else {
325                         field.bit_offset = (3 * (key->hw_key_idx - 8));
326                         field.bit_mask = 0x7 << field.bit_offset;
327
328                         rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
329                         rt2x00_set_field32(&reg, field, crypto->cipher);
330                         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
331                 }
332
333                 /*
334                  * The driver does not support the IV/EIV generation
335                  * in hardware. However it doesn't support the IV/EIV
336                  * inside the ieee80211 frame either, but requires it
337                  * to be provided seperately for the descriptor.
338                  * rt2x00lib will cut the IV/EIV data out of all frames
339                  * given to us by mac80211, but we must tell mac80211
340                  * to generate the IV/EIV data.
341                  */
342                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
343         }
344
345         /*
346          * SEC_CSR0 contains only single-bit fields to indicate
347          * a particular key is valid. Because using the FIELD32()
348          * defines directly will cause a lot of overhead we use
349          * a calculation to determine the correct bit directly.
350          */
351         mask = 1 << key->hw_key_idx;
352
353         rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
354         if (crypto->cmd == SET_KEY)
355                 reg |= mask;
356         else if (crypto->cmd == DISABLE_KEY)
357                 reg &= ~mask;
358         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
359
360         return 0;
361 }
362
363 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
364                                        struct rt2x00lib_crypto *crypto,
365                                        struct ieee80211_key_conf *key)
366 {
367         struct hw_pairwise_ta_entry addr_entry;
368         struct hw_key_entry key_entry;
369         int timeout;
370         u32 mask;
371         u32 reg;
372
373         if (crypto->cmd == SET_KEY) {
374                 /*
375                  * rt2x00lib can't determine the correct free
376                  * key_idx for pairwise keys. We have 2 registers
377                  * with key valid bits. The goal is simple, read
378                  * the first register, if that is full move to
379                  * the next register.
380                  * When both registers are full, we drop the key,
381                  * otherwise we use the first invalid entry.
382                  */
383                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
384                 if (reg && reg == ~0) {
385                         key->hw_key_idx = 32;
386                         rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
387                         if (reg && reg == ~0)
388                                 return -ENOSPC;
389                 }
390
391                 key->hw_key_idx += reg ? ffz(reg) : 0;
392
393                 /*
394                  * Upload key to hardware
395                  */
396                 memcpy(key_entry.key, crypto->key,
397                        sizeof(key_entry.key));
398                 memcpy(key_entry.tx_mic, crypto->tx_mic,
399                        sizeof(key_entry.tx_mic));
400                 memcpy(key_entry.rx_mic, crypto->rx_mic,
401                        sizeof(key_entry.rx_mic));
402
403                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
404                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
405                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
406                                                     USB_VENDOR_REQUEST_OUT, reg,
407                                                     &key_entry,
408                                                     sizeof(key_entry),
409                                                     timeout);
410
411                 /*
412                  * Send the address and cipher type to the hardware register.
413                  * This data fits within the CSR cache size, so we can use
414                  * rt2x00usb_register_multiwrite() directly.
415                  */
416                 memset(&addr_entry, 0, sizeof(addr_entry));
417                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
418                 addr_entry.cipher = crypto->cipher;
419
420                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
421                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
422                                             &addr_entry, sizeof(addr_entry));
423
424                 /*
425                  * Enable pairwise lookup table for given BSS idx,
426                  * without this received frames will not be decrypted
427                  * by the hardware.
428                  */
429                 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
430                 reg |= (1 << crypto->bssidx);
431                 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
432
433                 /*
434                  * The driver does not support the IV/EIV generation
435                  * in hardware. However it doesn't support the IV/EIV
436                  * inside the ieee80211 frame either, but requires it
437                  * to be provided seperately for the descriptor.
438                  * rt2x00lib will cut the IV/EIV data out of all frames
439                  * given to us by mac80211, but we must tell mac80211
440                  * to generate the IV/EIV data.
441                  */
442                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
443         }
444
445         /*
446          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
447          * a particular key is valid. Because using the FIELD32()
448          * defines directly will cause a lot of overhead we use
449          * a calculation to determine the correct bit directly.
450          */
451         if (key->hw_key_idx < 32) {
452                 mask = 1 << key->hw_key_idx;
453
454                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
455                 if (crypto->cmd == SET_KEY)
456                         reg |= mask;
457                 else if (crypto->cmd == DISABLE_KEY)
458                         reg &= ~mask;
459                 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
460         } else {
461                 mask = 1 << (key->hw_key_idx - 32);
462
463                 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
464                 if (crypto->cmd == SET_KEY)
465                         reg |= mask;
466                 else if (crypto->cmd == DISABLE_KEY)
467                         reg &= ~mask;
468                 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
469         }
470
471         return 0;
472 }
473
474 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
475                                   const unsigned int filter_flags)
476 {
477         u32 reg;
478
479         /*
480          * Start configuration steps.
481          * Note that the version error will always be dropped
482          * and broadcast frames will always be accepted since
483          * there is no filter for it at this time.
484          */
485         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
486         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
487                            !(filter_flags & FIF_FCSFAIL));
488         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
489                            !(filter_flags & FIF_PLCPFAIL));
490         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
491                            !(filter_flags & FIF_CONTROL));
492         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
493                            !(filter_flags & FIF_PROMISC_IN_BSS));
494         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
495                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
496                            !rt2x00dev->intf_ap_count);
497         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
498         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
499                            !(filter_flags & FIF_ALLMULTI));
500         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
501         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
502                            !(filter_flags & FIF_CONTROL));
503         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
504 }
505
506 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
507                                 struct rt2x00_intf *intf,
508                                 struct rt2x00intf_conf *conf,
509                                 const unsigned int flags)
510 {
511         unsigned int beacon_base;
512         u32 reg;
513
514         if (flags & CONFIG_UPDATE_TYPE) {
515                 /*
516                  * Clear current synchronisation setup.
517                  * For the Beacon base registers we only need to clear
518                  * the first byte since that byte contains the VALID and OWNER
519                  * bits which (when set to 0) will invalidate the entire beacon.
520                  */
521                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
522                 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
523
524                 /*
525                  * Enable synchronisation.
526                  */
527                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
528                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
529                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
530                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
531                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
532         }
533
534         if (flags & CONFIG_UPDATE_MAC) {
535                 reg = le32_to_cpu(conf->mac[1]);
536                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
537                 conf->mac[1] = cpu_to_le32(reg);
538
539                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
540                                             conf->mac, sizeof(conf->mac));
541         }
542
543         if (flags & CONFIG_UPDATE_BSSID) {
544                 reg = le32_to_cpu(conf->bssid[1]);
545                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
546                 conf->bssid[1] = cpu_to_le32(reg);
547
548                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
549                                             conf->bssid, sizeof(conf->bssid));
550         }
551 }
552
553 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
554                                struct rt2x00lib_erp *erp)
555 {
556         u32 reg;
557
558         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
559         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
560         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
561
562         rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
563         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
564                            !!erp->short_preamble);
565         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
566
567         rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
568
569         rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
570         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
571         rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
572
573         rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
574         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
575         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
576         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
577         rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
578 }
579
580 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
581                                       struct antenna_setup *ant)
582 {
583         u8 r3;
584         u8 r4;
585         u8 r77;
586         u8 temp;
587
588         rt73usb_bbp_read(rt2x00dev, 3, &r3);
589         rt73usb_bbp_read(rt2x00dev, 4, &r4);
590         rt73usb_bbp_read(rt2x00dev, 77, &r77);
591
592         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
593
594         /*
595          * Configure the RX antenna.
596          */
597         switch (ant->rx) {
598         case ANTENNA_HW_DIVERSITY:
599                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
600                 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
601                        && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
602                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
603                 break;
604         case ANTENNA_A:
605                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
606                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
607                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
608                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
609                 else
610                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
611                 break;
612         case ANTENNA_B:
613         default:
614                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
615                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
616                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
617                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
618                 else
619                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
620                 break;
621         }
622
623         rt73usb_bbp_write(rt2x00dev, 77, r77);
624         rt73usb_bbp_write(rt2x00dev, 3, r3);
625         rt73usb_bbp_write(rt2x00dev, 4, r4);
626 }
627
628 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
629                                       struct antenna_setup *ant)
630 {
631         u8 r3;
632         u8 r4;
633         u8 r77;
634
635         rt73usb_bbp_read(rt2x00dev, 3, &r3);
636         rt73usb_bbp_read(rt2x00dev, 4, &r4);
637         rt73usb_bbp_read(rt2x00dev, 77, &r77);
638
639         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
640         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
641                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
642
643         /*
644          * Configure the RX antenna.
645          */
646         switch (ant->rx) {
647         case ANTENNA_HW_DIVERSITY:
648                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
649                 break;
650         case ANTENNA_A:
651                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
652                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
653                 break;
654         case ANTENNA_B:
655         default:
656                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
657                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
658                 break;
659         }
660
661         rt73usb_bbp_write(rt2x00dev, 77, r77);
662         rt73usb_bbp_write(rt2x00dev, 3, r3);
663         rt73usb_bbp_write(rt2x00dev, 4, r4);
664 }
665
666 struct antenna_sel {
667         u8 word;
668         /*
669          * value[0] -> non-LNA
670          * value[1] -> LNA
671          */
672         u8 value[2];
673 };
674
675 static const struct antenna_sel antenna_sel_a[] = {
676         { 96,  { 0x58, 0x78 } },
677         { 104, { 0x38, 0x48 } },
678         { 75,  { 0xfe, 0x80 } },
679         { 86,  { 0xfe, 0x80 } },
680         { 88,  { 0xfe, 0x80 } },
681         { 35,  { 0x60, 0x60 } },
682         { 97,  { 0x58, 0x58 } },
683         { 98,  { 0x58, 0x58 } },
684 };
685
686 static const struct antenna_sel antenna_sel_bg[] = {
687         { 96,  { 0x48, 0x68 } },
688         { 104, { 0x2c, 0x3c } },
689         { 75,  { 0xfe, 0x80 } },
690         { 86,  { 0xfe, 0x80 } },
691         { 88,  { 0xfe, 0x80 } },
692         { 35,  { 0x50, 0x50 } },
693         { 97,  { 0x48, 0x48 } },
694         { 98,  { 0x48, 0x48 } },
695 };
696
697 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
698                                struct antenna_setup *ant)
699 {
700         const struct antenna_sel *sel;
701         unsigned int lna;
702         unsigned int i;
703         u32 reg;
704
705         /*
706          * We should never come here because rt2x00lib is supposed
707          * to catch this and send us the correct antenna explicitely.
708          */
709         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
710                ant->tx == ANTENNA_SW_DIVERSITY);
711
712         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
713                 sel = antenna_sel_a;
714                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
715         } else {
716                 sel = antenna_sel_bg;
717                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
718         }
719
720         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
721                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
722
723         rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
724
725         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
726                            (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
727         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
728                            (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
729
730         rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
731
732         if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
733             rt2x00_rf(&rt2x00dev->chip, RF5225))
734                 rt73usb_config_antenna_5x(rt2x00dev, ant);
735         else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
736                  rt2x00_rf(&rt2x00dev->chip, RF2527))
737                 rt73usb_config_antenna_2x(rt2x00dev, ant);
738 }
739
740 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
741                                     struct rt2x00lib_conf *libconf)
742 {
743         u16 eeprom;
744         short lna_gain = 0;
745
746         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
747                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
748                         lna_gain += 14;
749
750                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
751                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
752         } else {
753                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
754                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
755         }
756
757         rt2x00dev->lna_gain = lna_gain;
758 }
759
760 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
761                                    struct rf_channel *rf, const int txpower)
762 {
763         u8 r3;
764         u8 r94;
765         u8 smart;
766
767         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
768         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
769
770         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
771                   rt2x00_rf(&rt2x00dev->chip, RF2527));
772
773         rt73usb_bbp_read(rt2x00dev, 3, &r3);
774         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
775         rt73usb_bbp_write(rt2x00dev, 3, r3);
776
777         r94 = 6;
778         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
779                 r94 += txpower - MAX_TXPOWER;
780         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
781                 r94 += txpower;
782         rt73usb_bbp_write(rt2x00dev, 94, r94);
783
784         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
785         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
786         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
787         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
788
789         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
790         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
791         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
792         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
793
794         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
795         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
796         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
797         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
798
799         udelay(10);
800 }
801
802 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
803                                    const int txpower)
804 {
805         struct rf_channel rf;
806
807         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
808         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
809         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
810         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
811
812         rt73usb_config_channel(rt2x00dev, &rf, txpower);
813 }
814
815 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
816                                        struct rt2x00lib_conf *libconf)
817 {
818         u32 reg;
819
820         rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
821         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
822                            libconf->conf->long_frame_max_tx_count);
823         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
824                            libconf->conf->short_frame_max_tx_count);
825         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
826 }
827
828 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
829                                     struct rt2x00lib_conf *libconf)
830 {
831         u32 reg;
832
833         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
834         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
835         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
836
837         rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
838         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
839         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
840
841         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
842         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
843                            libconf->conf->beacon_int * 16);
844         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
845 }
846
847 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
848                                 struct rt2x00lib_conf *libconf)
849 {
850         enum dev_state state =
851             (libconf->conf->flags & IEEE80211_CONF_PS) ?
852                 STATE_SLEEP : STATE_AWAKE;
853         u32 reg;
854
855         if (state == STATE_SLEEP) {
856                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
857                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
858                                    libconf->conf->beacon_int - 10);
859                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
860                                    libconf->conf->listen_interval - 1);
861                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
862
863                 /* We must first disable autowake before it can be enabled */
864                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
865                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
866
867                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
868                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
869
870                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
871                                             USB_MODE_SLEEP, REGISTER_TIMEOUT);
872         } else {
873                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
874                                             USB_MODE_WAKEUP, REGISTER_TIMEOUT);
875
876                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
877                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
878                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
879                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
880                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
881                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
882         }
883 }
884
885 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
886                            struct rt2x00lib_conf *libconf,
887                            const unsigned int flags)
888 {
889         /* Always recalculate LNA gain before changing configuration */
890         rt73usb_config_lna_gain(rt2x00dev, libconf);
891
892         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
893                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
894                                        libconf->conf->power_level);
895         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
896             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
897                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
898         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
899                 rt73usb_config_retry_limit(rt2x00dev, libconf);
900         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
901                 rt73usb_config_duration(rt2x00dev, libconf);
902         if (flags & IEEE80211_CONF_CHANGE_PS)
903                 rt73usb_config_ps(rt2x00dev, libconf);
904 }
905
906 /*
907  * Link tuning
908  */
909 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
910                                struct link_qual *qual)
911 {
912         u32 reg;
913
914         /*
915          * Update FCS error count from register.
916          */
917         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
918         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
919
920         /*
921          * Update False CCA count from register.
922          */
923         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
924         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
925 }
926
927 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
928                                    struct link_qual *qual, u8 vgc_level)
929 {
930         if (qual->vgc_level != vgc_level) {
931                 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
932                 qual->vgc_level = vgc_level;
933                 qual->vgc_level_reg = vgc_level;
934         }
935 }
936
937 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
938                                 struct link_qual *qual)
939 {
940         rt73usb_set_vgc(rt2x00dev, qual, 0x20);
941 }
942
943 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
944                                struct link_qual *qual, const u32 count)
945 {
946         u8 up_bound;
947         u8 low_bound;
948
949         /*
950          * Determine r17 bounds.
951          */
952         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
953                 low_bound = 0x28;
954                 up_bound = 0x48;
955
956                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
957                         low_bound += 0x10;
958                         up_bound += 0x10;
959                 }
960         } else {
961                 if (qual->rssi > -82) {
962                         low_bound = 0x1c;
963                         up_bound = 0x40;
964                 } else if (qual->rssi > -84) {
965                         low_bound = 0x1c;
966                         up_bound = 0x20;
967                 } else {
968                         low_bound = 0x1c;
969                         up_bound = 0x1c;
970                 }
971
972                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
973                         low_bound += 0x14;
974                         up_bound += 0x10;
975                 }
976         }
977
978         /*
979          * If we are not associated, we should go straight to the
980          * dynamic CCA tuning.
981          */
982         if (!rt2x00dev->intf_associated)
983                 goto dynamic_cca_tune;
984
985         /*
986          * Special big-R17 for very short distance
987          */
988         if (qual->rssi > -35) {
989                 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
990                 return;
991         }
992
993         /*
994          * Special big-R17 for short distance
995          */
996         if (qual->rssi >= -58) {
997                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
998                 return;
999         }
1000
1001         /*
1002          * Special big-R17 for middle-short distance
1003          */
1004         if (qual->rssi >= -66) {
1005                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1006                 return;
1007         }
1008
1009         /*
1010          * Special mid-R17 for middle distance
1011          */
1012         if (qual->rssi >= -74) {
1013                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1014                 return;
1015         }
1016
1017         /*
1018          * Special case: Change up_bound based on the rssi.
1019          * Lower up_bound when rssi is weaker then -74 dBm.
1020          */
1021         up_bound -= 2 * (-74 - qual->rssi);
1022         if (low_bound > up_bound)
1023                 up_bound = low_bound;
1024
1025         if (qual->vgc_level > up_bound) {
1026                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
1027                 return;
1028         }
1029
1030 dynamic_cca_tune:
1031
1032         /*
1033          * r17 does not yet exceed upper limit, continue and base
1034          * the r17 tuning on the false CCA count.
1035          */
1036         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1037                 rt73usb_set_vgc(rt2x00dev, qual,
1038                                 min_t(u8, qual->vgc_level + 4, up_bound));
1039         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1040                 rt73usb_set_vgc(rt2x00dev, qual,
1041                                 max_t(u8, qual->vgc_level - 4, low_bound));
1042 }
1043
1044 /*
1045  * Firmware functions
1046  */
1047 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1048 {
1049         return FIRMWARE_RT2571;
1050 }
1051
1052 static u16 rt73usb_get_firmware_crc(const void *data, const size_t len)
1053 {
1054         u16 crc;
1055
1056         /*
1057          * Use the crc itu-t algorithm.
1058          * The last 2 bytes in the firmware array are the crc checksum itself,
1059          * this means that we should never pass those 2 bytes to the crc
1060          * algorithm.
1061          */
1062         crc = crc_itu_t(0, data, len - 2);
1063         crc = crc_itu_t_byte(crc, 0);
1064         crc = crc_itu_t_byte(crc, 0);
1065
1066         return crc;
1067 }
1068
1069 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1070                                  const size_t len)
1071 {
1072         unsigned int i;
1073         int status;
1074         u32 reg;
1075
1076         /*
1077          * Wait for stable hardware.
1078          */
1079         for (i = 0; i < 100; i++) {
1080                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1081                 if (reg)
1082                         break;
1083                 msleep(1);
1084         }
1085
1086         if (!reg) {
1087                 ERROR(rt2x00dev, "Unstable hardware.\n");
1088                 return -EBUSY;
1089         }
1090
1091         /*
1092          * Write firmware to device.
1093          */
1094         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1095                                             USB_VENDOR_REQUEST_OUT,
1096                                             FIRMWARE_IMAGE_BASE,
1097                                             data, len,
1098                                             REGISTER_TIMEOUT32(len));
1099
1100         /*
1101          * Send firmware request to device to load firmware,
1102          * we need to specify a long timeout time.
1103          */
1104         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1105                                              0, USB_MODE_FIRMWARE,
1106                                              REGISTER_TIMEOUT_FIRMWARE);
1107         if (status < 0) {
1108                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1109                 return status;
1110         }
1111
1112         return 0;
1113 }
1114
1115 /*
1116  * Initialization functions.
1117  */
1118 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1119 {
1120         u32 reg;
1121
1122         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1123         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1124         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1125         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1126         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1127
1128         rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1129         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1130         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1131         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1132         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1133         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1134         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1135         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1136         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1137         rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1138
1139         /*
1140          * CCK TXD BBP registers
1141          */
1142         rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1143         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1144         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1145         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1146         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1147         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1148         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1149         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1150         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1151         rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1152
1153         /*
1154          * OFDM TXD BBP registers
1155          */
1156         rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1157         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1158         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1159         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1160         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1161         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1162         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1163         rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1164
1165         rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1166         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1167         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1168         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1169         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1170         rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1171
1172         rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1173         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1174         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1175         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1176         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1177         rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1178
1179         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1180         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1181         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1182         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1183         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1184         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1185         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1186         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1187
1188         rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1189
1190         rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1191         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1192         rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1193
1194         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1195
1196         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1197                 return -EBUSY;
1198
1199         rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1200
1201         /*
1202          * Invalidate all Shared Keys (SEC_CSR0),
1203          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1204          */
1205         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1206         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1207         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1208
1209         reg = 0x000023b0;
1210         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1211             rt2x00_rf(&rt2x00dev->chip, RF2527))
1212                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1213         rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1214
1215         rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1216         rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1217         rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1218
1219         rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1220         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1221         rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1222
1223         /*
1224          * Clear all beacons
1225          * For the Beacon base registers we only need to clear
1226          * the first byte since that byte contains the VALID and OWNER
1227          * bits which (when set to 0) will invalidate the entire beacon.
1228          */
1229         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1230         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1231         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1232         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1233
1234         /*
1235          * We must clear the error counters.
1236          * These registers are cleared on read,
1237          * so we may pass a useless variable to store the value.
1238          */
1239         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1240         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1241         rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1242
1243         /*
1244          * Reset MAC and BBP registers.
1245          */
1246         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1247         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1248         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1249         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1250
1251         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1252         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1253         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1254         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1255
1256         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1257         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1258         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1259
1260         return 0;
1261 }
1262
1263 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1264 {
1265         unsigned int i;
1266         u8 value;
1267
1268         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1269                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1270                 if ((value != 0xff) && (value != 0x00))
1271                         return 0;
1272                 udelay(REGISTER_BUSY_DELAY);
1273         }
1274
1275         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1276         return -EACCES;
1277 }
1278
1279 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1280 {
1281         unsigned int i;
1282         u16 eeprom;
1283         u8 reg_id;
1284         u8 value;
1285
1286         if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1287                 return -EACCES;
1288
1289         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1290         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1291         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1292         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1293         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1294         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1295         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1296         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1297         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1298         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1299         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1300         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1301         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1302         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1303         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1304         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1305         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1306         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1307         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1308         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1309         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1310         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1311         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1312         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1313         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1314
1315         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1316                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1317
1318                 if (eeprom != 0xffff && eeprom != 0x0000) {
1319                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1320                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1321                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1322                 }
1323         }
1324
1325         return 0;
1326 }
1327
1328 /*
1329  * Device state switch handlers.
1330  */
1331 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1332                               enum dev_state state)
1333 {
1334         u32 reg;
1335
1336         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1337         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1338                            (state == STATE_RADIO_RX_OFF) ||
1339                            (state == STATE_RADIO_RX_OFF_LINK));
1340         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1341 }
1342
1343 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1344 {
1345         /*
1346          * Initialize all registers.
1347          */
1348         if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1349                      rt73usb_init_bbp(rt2x00dev)))
1350                 return -EIO;
1351
1352         return 0;
1353 }
1354
1355 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1356 {
1357         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1358
1359         /*
1360          * Disable synchronisation.
1361          */
1362         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1363
1364         rt2x00usb_disable_radio(rt2x00dev);
1365 }
1366
1367 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1368 {
1369         u32 reg;
1370         unsigned int i;
1371         char put_to_sleep;
1372
1373         put_to_sleep = (state != STATE_AWAKE);
1374
1375         rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1376         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1377         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1378         rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1379
1380         /*
1381          * Device is not guaranteed to be in the requested state yet.
1382          * We must wait until the register indicates that the
1383          * device has entered the correct state.
1384          */
1385         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1386                 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1387                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1388                 if (state == !put_to_sleep)
1389                         return 0;
1390                 msleep(10);
1391         }
1392
1393         return -EBUSY;
1394 }
1395
1396 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1397                                     enum dev_state state)
1398 {
1399         int retval = 0;
1400
1401         switch (state) {
1402         case STATE_RADIO_ON:
1403                 retval = rt73usb_enable_radio(rt2x00dev);
1404                 break;
1405         case STATE_RADIO_OFF:
1406                 rt73usb_disable_radio(rt2x00dev);
1407                 break;
1408         case STATE_RADIO_RX_ON:
1409         case STATE_RADIO_RX_ON_LINK:
1410         case STATE_RADIO_RX_OFF:
1411         case STATE_RADIO_RX_OFF_LINK:
1412                 rt73usb_toggle_rx(rt2x00dev, state);
1413                 break;
1414         case STATE_RADIO_IRQ_ON:
1415         case STATE_RADIO_IRQ_OFF:
1416                 /* No support, but no error either */
1417                 break;
1418         case STATE_DEEP_SLEEP:
1419         case STATE_SLEEP:
1420         case STATE_STANDBY:
1421         case STATE_AWAKE:
1422                 retval = rt73usb_set_state(rt2x00dev, state);
1423                 break;
1424         default:
1425                 retval = -ENOTSUPP;
1426                 break;
1427         }
1428
1429         if (unlikely(retval))
1430                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1431                       state, retval);
1432
1433         return retval;
1434 }
1435
1436 /*
1437  * TX descriptor initialization
1438  */
1439 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1440                                   struct sk_buff *skb,
1441                                   struct txentry_desc *txdesc)
1442 {
1443         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1444         __le32 *txd = skbdesc->desc;
1445         u32 word;
1446
1447         /*
1448          * Start writing the descriptor words.
1449          */
1450         rt2x00_desc_read(txd, 1, &word);
1451         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1452         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1453         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1454         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1455         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1456         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1457                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1458         rt2x00_desc_write(txd, 1, word);
1459
1460         rt2x00_desc_read(txd, 2, &word);
1461         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1462         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1463         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1464         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1465         rt2x00_desc_write(txd, 2, word);
1466
1467         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1468                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1469                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1470         }
1471
1472         rt2x00_desc_read(txd, 5, &word);
1473         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1474                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1475         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1476         rt2x00_desc_write(txd, 5, word);
1477
1478         rt2x00_desc_read(txd, 0, &word);
1479         rt2x00_set_field32(&word, TXD_W0_BURST,
1480                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1481         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1482         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1483                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1484         rt2x00_set_field32(&word, TXD_W0_ACK,
1485                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1486         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1487                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1488         rt2x00_set_field32(&word, TXD_W0_OFDM,
1489                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1490         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1491         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1492                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1493         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1494                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1495         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1496                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1497         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1498         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1499         rt2x00_set_field32(&word, TXD_W0_BURST2,
1500                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1501         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1502         rt2x00_desc_write(txd, 0, word);
1503 }
1504
1505 /*
1506  * TX data initialization
1507  */
1508 static void rt73usb_write_beacon(struct queue_entry *entry)
1509 {
1510         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1511         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1512         unsigned int beacon_base;
1513         u32 reg;
1514
1515         /*
1516          * Add the descriptor in front of the skb.
1517          */
1518         skb_push(entry->skb, entry->queue->desc_size);
1519         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1520         skbdesc->desc = entry->skb->data;
1521
1522         /*
1523          * Disable beaconing while we are reloading the beacon data,
1524          * otherwise we might be sending out invalid data.
1525          */
1526         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1527         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1528         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1529         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1530         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1531
1532         /*
1533          * Write entire beacon with descriptor to register.
1534          */
1535         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1536         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1537                                             USB_VENDOR_REQUEST_OUT, beacon_base,
1538                                             entry->skb->data, entry->skb->len,
1539                                             REGISTER_TIMEOUT32(entry->skb->len));
1540
1541         /*
1542          * Clean up the beacon skb.
1543          */
1544         dev_kfree_skb(entry->skb);
1545         entry->skb = NULL;
1546 }
1547
1548 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1549 {
1550         int length;
1551
1552         /*
1553          * The length _must_ be a multiple of 4,
1554          * but it must _not_ be a multiple of the USB packet size.
1555          */
1556         length = roundup(entry->skb->len, 4);
1557         length += (4 * !(length % entry->queue->usb_maxpacket));
1558
1559         return length;
1560 }
1561
1562 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1563                                   const enum data_queue_qid queue)
1564 {
1565         u32 reg;
1566
1567         if (queue != QID_BEACON) {
1568                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1569                 return;
1570         }
1571
1572         /*
1573          * For Wi-Fi faily generated beacons between participating stations.
1574          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1575          */
1576         rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1577
1578         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1579         if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1580                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1581                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1582                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1583                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1584         }
1585 }
1586
1587 /*
1588  * RX control handlers
1589  */
1590 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1591 {
1592         u8 offset = rt2x00dev->lna_gain;
1593         u8 lna;
1594
1595         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1596         switch (lna) {
1597         case 3:
1598                 offset += 90;
1599                 break;
1600         case 2:
1601                 offset += 74;
1602                 break;
1603         case 1:
1604                 offset += 64;
1605                 break;
1606         default:
1607                 return 0;
1608         }
1609
1610         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1611                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1612                         if (lna == 3 || lna == 2)
1613                                 offset += 10;
1614                 } else {
1615                         if (lna == 3)
1616                                 offset += 6;
1617                         else if (lna == 2)
1618                                 offset += 8;
1619                 }
1620         }
1621
1622         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1623 }
1624
1625 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1626                                 struct rxdone_entry_desc *rxdesc)
1627 {
1628         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1629         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1630         __le32 *rxd = (__le32 *)entry->skb->data;
1631         u32 word0;
1632         u32 word1;
1633
1634         /*
1635          * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1636          * frame data in rt2x00usb.
1637          */
1638         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1639         rxd = (__le32 *)skbdesc->desc;
1640
1641         /*
1642          * It is now safe to read the descriptor on all architectures.
1643          */
1644         rt2x00_desc_read(rxd, 0, &word0);
1645         rt2x00_desc_read(rxd, 1, &word1);
1646
1647         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1648                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1649
1650         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1651                 rxdesc->cipher =
1652                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1653                 rxdesc->cipher_status =
1654                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1655         }
1656
1657         if (rxdesc->cipher != CIPHER_NONE) {
1658                 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1659                 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
1660                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1661
1662                 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1663                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1664
1665                 /*
1666                  * Hardware has stripped IV/EIV data from 802.11 frame during
1667                  * decryption. It has provided the data seperately but rt2x00lib
1668                  * should decide if it should be reinserted.
1669                  */
1670                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1671
1672                 /*
1673                  * FIXME: Legacy driver indicates that the frame does
1674                  * contain the Michael Mic. Unfortunately, in rt2x00
1675                  * the MIC seems to be missing completely...
1676                  */
1677                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1678
1679                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1680                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1681                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1682                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1683         }
1684
1685         /*
1686          * Obtain the status about this packet.
1687          * When frame was received with an OFDM bitrate,
1688          * the signal is the PLCP value. If it was received with
1689          * a CCK bitrate the signal is the rate in 100kbit/s.
1690          */
1691         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1692         rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1693         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1694
1695         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1696                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1697         else
1698                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1699         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1700                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1701
1702         /*
1703          * Set skb pointers, and update frame information.
1704          */
1705         skb_pull(entry->skb, entry->queue->desc_size);
1706         skb_trim(entry->skb, rxdesc->size);
1707 }
1708
1709 /*
1710  * Device probe functions.
1711  */
1712 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1713 {
1714         u16 word;
1715         u8 *mac;
1716         s8 value;
1717
1718         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1719
1720         /*
1721          * Start validation of the data that has been read.
1722          */
1723         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1724         if (!is_valid_ether_addr(mac)) {
1725                 random_ether_addr(mac);
1726                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1727         }
1728
1729         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1730         if (word == 0xffff) {
1731                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1732                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1733                                    ANTENNA_B);
1734                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1735                                    ANTENNA_B);
1736                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1737                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1738                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1739                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1740                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1741                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1742         }
1743
1744         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1745         if (word == 0xffff) {
1746                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1747                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1748                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1749         }
1750
1751         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1752         if (word == 0xffff) {
1753                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1754                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1755                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1756                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1757                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1758                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1759                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1760                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1761                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1762                                    LED_MODE_DEFAULT);
1763                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1764                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1765         }
1766
1767         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1768         if (word == 0xffff) {
1769                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1770                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1771                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1772                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1773         }
1774
1775         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1776         if (word == 0xffff) {
1777                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1778                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1779                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1780                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1781         } else {
1782                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1783                 if (value < -10 || value > 10)
1784                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1785                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1786                 if (value < -10 || value > 10)
1787                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1788                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1789         }
1790
1791         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1792         if (word == 0xffff) {
1793                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1794                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1795                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1796                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1797         } else {
1798                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1799                 if (value < -10 || value > 10)
1800                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1801                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1802                 if (value < -10 || value > 10)
1803                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1804                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1805         }
1806
1807         return 0;
1808 }
1809
1810 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1811 {
1812         u32 reg;
1813         u16 value;
1814         u16 eeprom;
1815
1816         /*
1817          * Read EEPROM word for configuration.
1818          */
1819         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1820
1821         /*
1822          * Identify RF chipset.
1823          */
1824         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1825         rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1826         rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1827
1828         if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1829                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1830                 return -ENODEV;
1831         }
1832
1833         if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1834             !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1835             !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1836             !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1837                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1838                 return -ENODEV;
1839         }
1840
1841         /*
1842          * Identify default antenna configuration.
1843          */
1844         rt2x00dev->default_ant.tx =
1845             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1846         rt2x00dev->default_ant.rx =
1847             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1848
1849         /*
1850          * Read the Frame type.
1851          */
1852         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1853                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1854
1855         /*
1856          * Read frequency offset.
1857          */
1858         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1859         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1860
1861         /*
1862          * Read external LNA informations.
1863          */
1864         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1865
1866         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1867                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1868                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1869         }
1870
1871         /*
1872          * Store led settings, for correct led behaviour.
1873          */
1874 #ifdef CONFIG_RT2X00_LIB_LEDS
1875         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1876
1877         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1878         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1879         if (value == LED_MODE_SIGNAL_STRENGTH)
1880                 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1881                                  LED_TYPE_QUALITY);
1882
1883         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1884         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1885                            rt2x00_get_field16(eeprom,
1886                                               EEPROM_LED_POLARITY_GPIO_0));
1887         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1888                            rt2x00_get_field16(eeprom,
1889                                               EEPROM_LED_POLARITY_GPIO_1));
1890         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1891                            rt2x00_get_field16(eeprom,
1892                                               EEPROM_LED_POLARITY_GPIO_2));
1893         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1894                            rt2x00_get_field16(eeprom,
1895                                               EEPROM_LED_POLARITY_GPIO_3));
1896         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1897                            rt2x00_get_field16(eeprom,
1898                                               EEPROM_LED_POLARITY_GPIO_4));
1899         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1900                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1901         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1902                            rt2x00_get_field16(eeprom,
1903                                               EEPROM_LED_POLARITY_RDY_G));
1904         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1905                            rt2x00_get_field16(eeprom,
1906                                               EEPROM_LED_POLARITY_RDY_A));
1907 #endif /* CONFIG_RT2X00_LIB_LEDS */
1908
1909         return 0;
1910 }
1911
1912 /*
1913  * RF value list for RF2528
1914  * Supports: 2.4 GHz
1915  */
1916 static const struct rf_channel rf_vals_bg_2528[] = {
1917         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1918         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1919         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1920         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1921         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1922         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1923         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1924         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1925         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1926         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1927         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1928         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1929         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1930         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1931 };
1932
1933 /*
1934  * RF value list for RF5226
1935  * Supports: 2.4 GHz & 5.2 GHz
1936  */
1937 static const struct rf_channel rf_vals_5226[] = {
1938         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1939         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1940         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1941         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1942         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1943         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1944         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1945         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1946         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1947         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1948         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1949         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1950         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1951         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1952
1953         /* 802.11 UNI / HyperLan 2 */
1954         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1955         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1956         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1957         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1958         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1959         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1960         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1961         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1962
1963         /* 802.11 HyperLan 2 */
1964         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1965         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1966         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1967         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1968         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1969         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1970         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1971         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1972         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1973         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1974
1975         /* 802.11 UNII */
1976         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1977         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1978         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1979         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1980         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1981         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1982
1983         /* MMAC(Japan)J52 ch 34,38,42,46 */
1984         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1985         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1986         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1987         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1988 };
1989
1990 /*
1991  * RF value list for RF5225 & RF2527
1992  * Supports: 2.4 GHz & 5.2 GHz
1993  */
1994 static const struct rf_channel rf_vals_5225_2527[] = {
1995         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1996         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1997         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1998         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1999         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2000         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2001         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2002         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2003         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2004         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2005         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2006         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2007         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2008         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2009
2010         /* 802.11 UNI / HyperLan 2 */
2011         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2012         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2013         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2014         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2015         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2016         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2017         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2018         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2019
2020         /* 802.11 HyperLan 2 */
2021         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2022         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2023         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2024         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2025         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2026         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2027         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2028         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2029         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2030         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2031
2032         /* 802.11 UNII */
2033         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2034         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2035         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2036         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2037         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2038         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2039
2040         /* MMAC(Japan)J52 ch 34,38,42,46 */
2041         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2042         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2043         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2044         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2045 };
2046
2047
2048 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2049 {
2050         struct hw_mode_spec *spec = &rt2x00dev->spec;
2051         struct channel_info *info;
2052         char *tx_power;
2053         unsigned int i;
2054
2055         /*
2056          * Initialize all hw fields.
2057          */
2058         rt2x00dev->hw->flags =
2059             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2060             IEEE80211_HW_SIGNAL_DBM;
2061         rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
2062
2063         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2064         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2065                                 rt2x00_eeprom_addr(rt2x00dev,
2066                                                    EEPROM_MAC_ADDR_0));
2067
2068         /*
2069          * Initialize hw_mode information.
2070          */
2071         spec->supported_bands = SUPPORT_BAND_2GHZ;
2072         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2073
2074         if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2075                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2076                 spec->channels = rf_vals_bg_2528;
2077         } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
2078                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2079                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2080                 spec->channels = rf_vals_5226;
2081         } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2082                 spec->num_channels = 14;
2083                 spec->channels = rf_vals_5225_2527;
2084         } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
2085                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2086                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2087                 spec->channels = rf_vals_5225_2527;
2088         }
2089
2090         /*
2091          * Create channel information array
2092          */
2093         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2094         if (!info)
2095                 return -ENOMEM;
2096
2097         spec->channels_info = info;
2098
2099         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2100         for (i = 0; i < 14; i++)
2101                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2102
2103         if (spec->num_channels > 14) {
2104                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2105                 for (i = 14; i < spec->num_channels; i++)
2106                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2107         }
2108
2109         return 0;
2110 }
2111
2112 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2113 {
2114         int retval;
2115
2116         /*
2117          * Allocate eeprom data.
2118          */
2119         retval = rt73usb_validate_eeprom(rt2x00dev);
2120         if (retval)
2121                 return retval;
2122
2123         retval = rt73usb_init_eeprom(rt2x00dev);
2124         if (retval)
2125                 return retval;
2126
2127         /*
2128          * Initialize hw specifications.
2129          */
2130         retval = rt73usb_probe_hw_mode(rt2x00dev);
2131         if (retval)
2132                 return retval;
2133
2134         /*
2135          * This device requires firmware.
2136          */
2137         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2138         __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2139         if (!modparam_nohwcrypt)
2140                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2141
2142         /*
2143          * Set the rssi offset.
2144          */
2145         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2146
2147         return 0;
2148 }
2149
2150 /*
2151  * IEEE80211 stack callback functions.
2152  */
2153 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2154                            const struct ieee80211_tx_queue_params *params)
2155 {
2156         struct rt2x00_dev *rt2x00dev = hw->priv;
2157         struct data_queue *queue;
2158         struct rt2x00_field32 field;
2159         int retval;
2160         u32 reg;
2161
2162         /*
2163          * First pass the configuration through rt2x00lib, that will
2164          * update the queue settings and validate the input. After that
2165          * we are free to update the registers based on the value
2166          * in the queue parameter.
2167          */
2168         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2169         if (retval)
2170                 return retval;
2171
2172         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2173
2174         /* Update WMM TXOP register */
2175         if (queue_idx < 2) {
2176                 field.bit_offset = queue_idx * 16;
2177                 field.bit_mask = 0xffff << field.bit_offset;
2178
2179                 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2180                 rt2x00_set_field32(&reg, field, queue->txop);
2181                 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2182         } else if (queue_idx < 4) {
2183                 field.bit_offset = (queue_idx - 2) * 16;
2184                 field.bit_mask = 0xffff << field.bit_offset;
2185
2186                 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2187                 rt2x00_set_field32(&reg, field, queue->txop);
2188                 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2189         }
2190
2191         /* Update WMM registers */
2192         field.bit_offset = queue_idx * 4;
2193         field.bit_mask = 0xf << field.bit_offset;
2194
2195         rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2196         rt2x00_set_field32(&reg, field, queue->aifs);
2197         rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2198
2199         rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2200         rt2x00_set_field32(&reg, field, queue->cw_min);
2201         rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2202
2203         rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2204         rt2x00_set_field32(&reg, field, queue->cw_max);
2205         rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2206
2207         return 0;
2208 }
2209
2210 #if 0
2211 /*
2212  * Mac80211 demands get_tsf must be atomic.
2213  * This is not possible for rt73usb since all register access
2214  * functions require sleeping. Untill mac80211 no longer needs
2215  * get_tsf to be atomic, this function should be disabled.
2216  */
2217 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2218 {
2219         struct rt2x00_dev *rt2x00dev = hw->priv;
2220         u64 tsf;
2221         u32 reg;
2222
2223         rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2224         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2225         rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2226         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2227
2228         return tsf;
2229 }
2230 #else
2231 #define rt73usb_get_tsf NULL
2232 #endif
2233
2234 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2235         .tx                     = rt2x00mac_tx,
2236         .start                  = rt2x00mac_start,
2237         .stop                   = rt2x00mac_stop,
2238         .add_interface          = rt2x00mac_add_interface,
2239         .remove_interface       = rt2x00mac_remove_interface,
2240         .config                 = rt2x00mac_config,
2241         .config_interface       = rt2x00mac_config_interface,
2242         .configure_filter       = rt2x00mac_configure_filter,
2243         .set_key                = rt2x00mac_set_key,
2244         .get_stats              = rt2x00mac_get_stats,
2245         .bss_info_changed       = rt2x00mac_bss_info_changed,
2246         .conf_tx                = rt73usb_conf_tx,
2247         .get_tx_stats           = rt2x00mac_get_tx_stats,
2248         .get_tsf                = rt73usb_get_tsf,
2249 };
2250
2251 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2252         .probe_hw               = rt73usb_probe_hw,
2253         .get_firmware_name      = rt73usb_get_firmware_name,
2254         .get_firmware_crc       = rt73usb_get_firmware_crc,
2255         .load_firmware          = rt73usb_load_firmware,
2256         .initialize             = rt2x00usb_initialize,
2257         .uninitialize           = rt2x00usb_uninitialize,
2258         .clear_entry            = rt2x00usb_clear_entry,
2259         .set_device_state       = rt73usb_set_device_state,
2260         .link_stats             = rt73usb_link_stats,
2261         .reset_tuner            = rt73usb_reset_tuner,
2262         .link_tuner             = rt73usb_link_tuner,
2263         .write_tx_desc          = rt73usb_write_tx_desc,
2264         .write_tx_data          = rt2x00usb_write_tx_data,
2265         .write_beacon           = rt73usb_write_beacon,
2266         .get_tx_data_len        = rt73usb_get_tx_data_len,
2267         .kick_tx_queue          = rt73usb_kick_tx_queue,
2268         .fill_rxdone            = rt73usb_fill_rxdone,
2269         .config_shared_key      = rt73usb_config_shared_key,
2270         .config_pairwise_key    = rt73usb_config_pairwise_key,
2271         .config_filter          = rt73usb_config_filter,
2272         .config_intf            = rt73usb_config_intf,
2273         .config_erp             = rt73usb_config_erp,
2274         .config_ant             = rt73usb_config_ant,
2275         .config                 = rt73usb_config,
2276 };
2277
2278 static const struct data_queue_desc rt73usb_queue_rx = {
2279         .entry_num              = RX_ENTRIES,
2280         .data_size              = DATA_FRAME_SIZE,
2281         .desc_size              = RXD_DESC_SIZE,
2282         .priv_size              = sizeof(struct queue_entry_priv_usb),
2283 };
2284
2285 static const struct data_queue_desc rt73usb_queue_tx = {
2286         .entry_num              = TX_ENTRIES,
2287         .data_size              = DATA_FRAME_SIZE,
2288         .desc_size              = TXD_DESC_SIZE,
2289         .priv_size              = sizeof(struct queue_entry_priv_usb),
2290 };
2291
2292 static const struct data_queue_desc rt73usb_queue_bcn = {
2293         .entry_num              = 4 * BEACON_ENTRIES,
2294         .data_size              = MGMT_FRAME_SIZE,
2295         .desc_size              = TXINFO_SIZE,
2296         .priv_size              = sizeof(struct queue_entry_priv_usb),
2297 };
2298
2299 static const struct rt2x00_ops rt73usb_ops = {
2300         .name           = KBUILD_MODNAME,
2301         .max_sta_intf   = 1,
2302         .max_ap_intf    = 4,
2303         .eeprom_size    = EEPROM_SIZE,
2304         .rf_size        = RF_SIZE,
2305         .tx_queues      = NUM_TX_QUEUES,
2306         .rx             = &rt73usb_queue_rx,
2307         .tx             = &rt73usb_queue_tx,
2308         .bcn            = &rt73usb_queue_bcn,
2309         .lib            = &rt73usb_rt2x00_ops,
2310         .hw             = &rt73usb_mac80211_ops,
2311 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2312         .debugfs        = &rt73usb_rt2x00debug,
2313 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2314 };
2315
2316 /*
2317  * rt73usb module information.
2318  */
2319 static struct usb_device_id rt73usb_device_table[] = {
2320         /* AboCom */
2321         { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2322         /* Askey */
2323         { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2324         /* ASUS */
2325         { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2326         { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2327         /* Belkin */
2328         { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2329         { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2330         { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2331         { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2332         /* Billionton */
2333         { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2334         /* Buffalo */
2335         { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2336         /* CNet */
2337         { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2338         { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2339         /* Conceptronic */
2340         { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2341         /* Corega */
2342         { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2343         /* D-Link */
2344         { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2345         { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2346         { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2347         { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2348         /* Gemtek */
2349         { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2350         /* Gigabyte */
2351         { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2352         { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2353         /* Huawei-3Com */
2354         { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2355         /* Hercules */
2356         { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2357         { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2358         /* Linksys */
2359         { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2360         { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2361         { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
2362         /* MSI */
2363         { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2364         { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2365         { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2366         { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2367         /* Ralink */
2368         { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2369         { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2370         /* Qcom */
2371         { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2372         { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2373         { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2374         /* Senao */
2375         { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2376         /* Sitecom */
2377         { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2378         { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2379         /* Surecom */
2380         { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2381         /* Planex */
2382         { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2383         { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2384         { 0, }
2385 };
2386
2387 MODULE_AUTHOR(DRV_PROJECT);
2388 MODULE_VERSION(DRV_VERSION);
2389 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2390 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2391 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2392 MODULE_FIRMWARE(FIRMWARE_RT2571);
2393 MODULE_LICENSE("GPL");
2394
2395 static struct usb_driver rt73usb_driver = {
2396         .name           = KBUILD_MODNAME,
2397         .id_table       = rt73usb_device_table,
2398         .probe          = rt2x00usb_probe,
2399         .disconnect     = rt2x00usb_disconnect,
2400         .suspend        = rt2x00usb_suspend,
2401         .resume         = rt2x00usb_resume,
2402 };
2403
2404 static int __init rt73usb_init(void)
2405 {
2406         return usb_register(&rt73usb_driver);
2407 }
2408
2409 static void __exit rt73usb_exit(void)
2410 {
2411         usb_deregister(&rt73usb_driver);
2412 }
2413
2414 module_init(rt73usb_init);
2415 module_exit(rt73usb_exit);