rt2x00: Remove STATE_RADIO_IRQ_OFF_ISR and STATE_RADIO_IRQ_ON_ISR
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt73usb.c
1 /*
2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt73usb
23         Abstract: rt73usb device specific routines.
24         Supported chipsets: rt2571W & rt2671.
25  */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/usb.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00usb.h"
38 #include "rt73usb.h"
39
40 /*
41  * Allow hardware encryption to be disabled.
42  */
43 static int modparam_nohwcrypt;
44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46
47 /*
48  * Register access.
49  * All access to the CSR registers will go through the methods
50  * rt2x00usb_register_read and rt2x00usb_register_write.
51  * BBP and RF register require indirect register access,
52  * and use the CSR registers BBPCSR and RFCSR to achieve this.
53  * These indirect registers work with busy bits,
54  * and we will try maximal REGISTER_BUSY_COUNT times to access
55  * the register while taking a REGISTER_BUSY_DELAY us delay
56  * between each attampt. When the busy bit is still set at that time,
57  * the access attempt is considered to have failed,
58  * and we will print an error.
59  * The _lock versions must be used if you already hold the csr_mutex
60  */
61 #define WAIT_FOR_BBP(__dev, __reg) \
62         rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
63 #define WAIT_FOR_RF(__dev, __reg) \
64         rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
65
66 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
67                               const unsigned int word, const u8 value)
68 {
69         u32 reg;
70
71         mutex_lock(&rt2x00dev->csr_mutex);
72
73         /*
74          * Wait until the BBP becomes available, afterwards we
75          * can safely write the new data into the register.
76          */
77         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
78                 reg = 0;
79                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
80                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
81                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
82                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
83
84                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
85         }
86
87         mutex_unlock(&rt2x00dev->csr_mutex);
88 }
89
90 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
91                              const unsigned int word, u8 *value)
92 {
93         u32 reg;
94
95         mutex_lock(&rt2x00dev->csr_mutex);
96
97         /*
98          * Wait until the BBP becomes available, afterwards we
99          * can safely write the read request into the register.
100          * After the data has been written, we wait until hardware
101          * returns the correct value, if at any time the register
102          * doesn't become available in time, reg will be 0xffffffff
103          * which means we return 0xff to the caller.
104          */
105         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
106                 reg = 0;
107                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
108                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
109                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
110
111                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
112
113                 WAIT_FOR_BBP(rt2x00dev, &reg);
114         }
115
116         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
117
118         mutex_unlock(&rt2x00dev->csr_mutex);
119 }
120
121 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
122                              const unsigned int word, const u32 value)
123 {
124         u32 reg;
125
126         mutex_lock(&rt2x00dev->csr_mutex);
127
128         /*
129          * Wait until the RF becomes available, afterwards we
130          * can safely write the new data into the register.
131          */
132         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
133                 reg = 0;
134                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
135                 /*
136                  * RF5225 and RF2527 contain 21 bits per RF register value,
137                  * all others contain 20 bits.
138                  */
139                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
140                                    20 + (rt2x00_rf(rt2x00dev, RF5225) ||
141                                          rt2x00_rf(rt2x00dev, RF2527)));
142                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
143                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
144
145                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
146                 rt2x00_rf_write(rt2x00dev, word, value);
147         }
148
149         mutex_unlock(&rt2x00dev->csr_mutex);
150 }
151
152 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
153 static const struct rt2x00debug rt73usb_rt2x00debug = {
154         .owner  = THIS_MODULE,
155         .csr    = {
156                 .read           = rt2x00usb_register_read,
157                 .write          = rt2x00usb_register_write,
158                 .flags          = RT2X00DEBUGFS_OFFSET,
159                 .word_base      = CSR_REG_BASE,
160                 .word_size      = sizeof(u32),
161                 .word_count     = CSR_REG_SIZE / sizeof(u32),
162         },
163         .eeprom = {
164                 .read           = rt2x00_eeprom_read,
165                 .write          = rt2x00_eeprom_write,
166                 .word_base      = EEPROM_BASE,
167                 .word_size      = sizeof(u16),
168                 .word_count     = EEPROM_SIZE / sizeof(u16),
169         },
170         .bbp    = {
171                 .read           = rt73usb_bbp_read,
172                 .write          = rt73usb_bbp_write,
173                 .word_base      = BBP_BASE,
174                 .word_size      = sizeof(u8),
175                 .word_count     = BBP_SIZE / sizeof(u8),
176         },
177         .rf     = {
178                 .read           = rt2x00_rf_read,
179                 .write          = rt73usb_rf_write,
180                 .word_base      = RF_BASE,
181                 .word_size      = sizeof(u32),
182                 .word_count     = RF_SIZE / sizeof(u32),
183         },
184 };
185 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
186
187 static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
188 {
189         u32 reg;
190
191         rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
192         return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
193 }
194
195 #ifdef CONFIG_RT2X00_LIB_LEDS
196 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
197                                    enum led_brightness brightness)
198 {
199         struct rt2x00_led *led =
200            container_of(led_cdev, struct rt2x00_led, led_dev);
201         unsigned int enabled = brightness != LED_OFF;
202         unsigned int a_mode =
203             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
204         unsigned int bg_mode =
205             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
206
207         if (led->type == LED_TYPE_RADIO) {
208                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
209                                    MCU_LEDCS_RADIO_STATUS, enabled);
210
211                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
212                                             0, led->rt2x00dev->led_mcu_reg,
213                                             REGISTER_TIMEOUT);
214         } else if (led->type == LED_TYPE_ASSOC) {
215                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
216                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
217                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
218                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
219
220                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
221                                             0, led->rt2x00dev->led_mcu_reg,
222                                             REGISTER_TIMEOUT);
223         } else if (led->type == LED_TYPE_QUALITY) {
224                 /*
225                  * The brightness is divided into 6 levels (0 - 5),
226                  * this means we need to convert the brightness
227                  * argument into the matching level within that range.
228                  */
229                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
230                                             brightness / (LED_FULL / 6),
231                                             led->rt2x00dev->led_mcu_reg,
232                                             REGISTER_TIMEOUT);
233         }
234 }
235
236 static int rt73usb_blink_set(struct led_classdev *led_cdev,
237                              unsigned long *delay_on,
238                              unsigned long *delay_off)
239 {
240         struct rt2x00_led *led =
241             container_of(led_cdev, struct rt2x00_led, led_dev);
242         u32 reg;
243
244         rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
245         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
246         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
247         rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
248
249         return 0;
250 }
251
252 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
253                              struct rt2x00_led *led,
254                              enum led_type type)
255 {
256         led->rt2x00dev = rt2x00dev;
257         led->type = type;
258         led->led_dev.brightness_set = rt73usb_brightness_set;
259         led->led_dev.blink_set = rt73usb_blink_set;
260         led->flags = LED_INITIALIZED;
261 }
262 #endif /* CONFIG_RT2X00_LIB_LEDS */
263
264 /*
265  * Configuration handlers.
266  */
267 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
268                                      struct rt2x00lib_crypto *crypto,
269                                      struct ieee80211_key_conf *key)
270 {
271         struct hw_key_entry key_entry;
272         struct rt2x00_field32 field;
273         u32 mask;
274         u32 reg;
275
276         if (crypto->cmd == SET_KEY) {
277                 /*
278                  * rt2x00lib can't determine the correct free
279                  * key_idx for shared keys. We have 1 register
280                  * with key valid bits. The goal is simple, read
281                  * the register, if that is full we have no slots
282                  * left.
283                  * Note that each BSS is allowed to have up to 4
284                  * shared keys, so put a mask over the allowed
285                  * entries.
286                  */
287                 mask = (0xf << crypto->bssidx);
288
289                 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
290                 reg &= mask;
291
292                 if (reg && reg == mask)
293                         return -ENOSPC;
294
295                 key->hw_key_idx += reg ? ffz(reg) : 0;
296
297                 /*
298                  * Upload key to hardware
299                  */
300                 memcpy(key_entry.key, crypto->key,
301                        sizeof(key_entry.key));
302                 memcpy(key_entry.tx_mic, crypto->tx_mic,
303                        sizeof(key_entry.tx_mic));
304                 memcpy(key_entry.rx_mic, crypto->rx_mic,
305                        sizeof(key_entry.rx_mic));
306
307                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
308                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
309                                               &key_entry, sizeof(key_entry));
310
311                 /*
312                  * The cipher types are stored over 2 registers.
313                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
314                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
315                  * Using the correct defines correctly will cause overhead,
316                  * so just calculate the correct offset.
317                  */
318                 if (key->hw_key_idx < 8) {
319                         field.bit_offset = (3 * key->hw_key_idx);
320                         field.bit_mask = 0x7 << field.bit_offset;
321
322                         rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
323                         rt2x00_set_field32(&reg, field, crypto->cipher);
324                         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
325                 } else {
326                         field.bit_offset = (3 * (key->hw_key_idx - 8));
327                         field.bit_mask = 0x7 << field.bit_offset;
328
329                         rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
330                         rt2x00_set_field32(&reg, field, crypto->cipher);
331                         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
332                 }
333
334                 /*
335                  * The driver does not support the IV/EIV generation
336                  * in hardware. However it doesn't support the IV/EIV
337                  * inside the ieee80211 frame either, but requires it
338                  * to be provided separately for the descriptor.
339                  * rt2x00lib will cut the IV/EIV data out of all frames
340                  * given to us by mac80211, but we must tell mac80211
341                  * to generate the IV/EIV data.
342                  */
343                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
344         }
345
346         /*
347          * SEC_CSR0 contains only single-bit fields to indicate
348          * a particular key is valid. Because using the FIELD32()
349          * defines directly will cause a lot of overhead we use
350          * a calculation to determine the correct bit directly.
351          */
352         mask = 1 << key->hw_key_idx;
353
354         rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
355         if (crypto->cmd == SET_KEY)
356                 reg |= mask;
357         else if (crypto->cmd == DISABLE_KEY)
358                 reg &= ~mask;
359         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
360
361         return 0;
362 }
363
364 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
365                                        struct rt2x00lib_crypto *crypto,
366                                        struct ieee80211_key_conf *key)
367 {
368         struct hw_pairwise_ta_entry addr_entry;
369         struct hw_key_entry key_entry;
370         u32 mask;
371         u32 reg;
372
373         if (crypto->cmd == SET_KEY) {
374                 /*
375                  * rt2x00lib can't determine the correct free
376                  * key_idx for pairwise keys. We have 2 registers
377                  * with key valid bits. The goal is simple, read
378                  * the first register, if that is full move to
379                  * the next register.
380                  * When both registers are full, we drop the key,
381                  * otherwise we use the first invalid entry.
382                  */
383                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
384                 if (reg && reg == ~0) {
385                         key->hw_key_idx = 32;
386                         rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
387                         if (reg && reg == ~0)
388                                 return -ENOSPC;
389                 }
390
391                 key->hw_key_idx += reg ? ffz(reg) : 0;
392
393                 /*
394                  * Upload key to hardware
395                  */
396                 memcpy(key_entry.key, crypto->key,
397                        sizeof(key_entry.key));
398                 memcpy(key_entry.tx_mic, crypto->tx_mic,
399                        sizeof(key_entry.tx_mic));
400                 memcpy(key_entry.rx_mic, crypto->rx_mic,
401                        sizeof(key_entry.rx_mic));
402
403                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
404                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
405                                               &key_entry, sizeof(key_entry));
406
407                 /*
408                  * Send the address and cipher type to the hardware register.
409                  */
410                 memset(&addr_entry, 0, sizeof(addr_entry));
411                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
412                 addr_entry.cipher = crypto->cipher;
413
414                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
415                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
416                                             &addr_entry, sizeof(addr_entry));
417
418                 /*
419                  * Enable pairwise lookup table for given BSS idx,
420                  * without this received frames will not be decrypted
421                  * by the hardware.
422                  */
423                 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
424                 reg |= (1 << crypto->bssidx);
425                 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
426
427                 /*
428                  * The driver does not support the IV/EIV generation
429                  * in hardware. However it doesn't support the IV/EIV
430                  * inside the ieee80211 frame either, but requires it
431                  * to be provided separately for the descriptor.
432                  * rt2x00lib will cut the IV/EIV data out of all frames
433                  * given to us by mac80211, but we must tell mac80211
434                  * to generate the IV/EIV data.
435                  */
436                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
437         }
438
439         /*
440          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
441          * a particular key is valid. Because using the FIELD32()
442          * defines directly will cause a lot of overhead we use
443          * a calculation to determine the correct bit directly.
444          */
445         if (key->hw_key_idx < 32) {
446                 mask = 1 << key->hw_key_idx;
447
448                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
449                 if (crypto->cmd == SET_KEY)
450                         reg |= mask;
451                 else if (crypto->cmd == DISABLE_KEY)
452                         reg &= ~mask;
453                 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
454         } else {
455                 mask = 1 << (key->hw_key_idx - 32);
456
457                 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
458                 if (crypto->cmd == SET_KEY)
459                         reg |= mask;
460                 else if (crypto->cmd == DISABLE_KEY)
461                         reg &= ~mask;
462                 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
463         }
464
465         return 0;
466 }
467
468 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
469                                   const unsigned int filter_flags)
470 {
471         u32 reg;
472
473         /*
474          * Start configuration steps.
475          * Note that the version error will always be dropped
476          * and broadcast frames will always be accepted since
477          * there is no filter for it at this time.
478          */
479         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
480         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
481                            !(filter_flags & FIF_FCSFAIL));
482         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
483                            !(filter_flags & FIF_PLCPFAIL));
484         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
485                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
486         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
487                            !(filter_flags & FIF_PROMISC_IN_BSS));
488         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
489                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
490                            !rt2x00dev->intf_ap_count);
491         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
492         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
493                            !(filter_flags & FIF_ALLMULTI));
494         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
495         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
496                            !(filter_flags & FIF_CONTROL));
497         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
498 }
499
500 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
501                                 struct rt2x00_intf *intf,
502                                 struct rt2x00intf_conf *conf,
503                                 const unsigned int flags)
504 {
505         u32 reg;
506
507         if (flags & CONFIG_UPDATE_TYPE) {
508                 /*
509                  * Enable synchronisation.
510                  */
511                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
512                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
513                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
514         }
515
516         if (flags & CONFIG_UPDATE_MAC) {
517                 reg = le32_to_cpu(conf->mac[1]);
518                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
519                 conf->mac[1] = cpu_to_le32(reg);
520
521                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
522                                             conf->mac, sizeof(conf->mac));
523         }
524
525         if (flags & CONFIG_UPDATE_BSSID) {
526                 reg = le32_to_cpu(conf->bssid[1]);
527                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
528                 conf->bssid[1] = cpu_to_le32(reg);
529
530                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
531                                             conf->bssid, sizeof(conf->bssid));
532         }
533 }
534
535 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
536                                struct rt2x00lib_erp *erp,
537                                u32 changed)
538 {
539         u32 reg;
540
541         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
542         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
543         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
544         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
545
546         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
547                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
548                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
549                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
550                                    !!erp->short_preamble);
551                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
552         }
553
554         if (changed & BSS_CHANGED_BASIC_RATES)
555                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5,
556                                          erp->basic_rates);
557
558         if (changed & BSS_CHANGED_BEACON_INT) {
559                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
560                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
561                                    erp->beacon_int * 16);
562                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
563         }
564
565         if (changed & BSS_CHANGED_ERP_SLOT) {
566                 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
567                 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
568                 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
569
570                 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
571                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
572                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
573                 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
574                 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
575         }
576 }
577
578 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
579                                       struct antenna_setup *ant)
580 {
581         u8 r3;
582         u8 r4;
583         u8 r77;
584         u8 temp;
585
586         rt73usb_bbp_read(rt2x00dev, 3, &r3);
587         rt73usb_bbp_read(rt2x00dev, 4, &r4);
588         rt73usb_bbp_read(rt2x00dev, 77, &r77);
589
590         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
591
592         /*
593          * Configure the RX antenna.
594          */
595         switch (ant->rx) {
596         case ANTENNA_HW_DIVERSITY:
597                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
598                 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
599                        && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
600                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
601                 break;
602         case ANTENNA_A:
603                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
604                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
605                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
606                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
607                 else
608                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
609                 break;
610         case ANTENNA_B:
611         default:
612                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
613                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
614                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
615                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
616                 else
617                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
618                 break;
619         }
620
621         rt73usb_bbp_write(rt2x00dev, 77, r77);
622         rt73usb_bbp_write(rt2x00dev, 3, r3);
623         rt73usb_bbp_write(rt2x00dev, 4, r4);
624 }
625
626 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
627                                       struct antenna_setup *ant)
628 {
629         u8 r3;
630         u8 r4;
631         u8 r77;
632
633         rt73usb_bbp_read(rt2x00dev, 3, &r3);
634         rt73usb_bbp_read(rt2x00dev, 4, &r4);
635         rt73usb_bbp_read(rt2x00dev, 77, &r77);
636
637         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
638         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
639                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
640
641         /*
642          * Configure the RX antenna.
643          */
644         switch (ant->rx) {
645         case ANTENNA_HW_DIVERSITY:
646                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
647                 break;
648         case ANTENNA_A:
649                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
650                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
651                 break;
652         case ANTENNA_B:
653         default:
654                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
655                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
656                 break;
657         }
658
659         rt73usb_bbp_write(rt2x00dev, 77, r77);
660         rt73usb_bbp_write(rt2x00dev, 3, r3);
661         rt73usb_bbp_write(rt2x00dev, 4, r4);
662 }
663
664 struct antenna_sel {
665         u8 word;
666         /*
667          * value[0] -> non-LNA
668          * value[1] -> LNA
669          */
670         u8 value[2];
671 };
672
673 static const struct antenna_sel antenna_sel_a[] = {
674         { 96,  { 0x58, 0x78 } },
675         { 104, { 0x38, 0x48 } },
676         { 75,  { 0xfe, 0x80 } },
677         { 86,  { 0xfe, 0x80 } },
678         { 88,  { 0xfe, 0x80 } },
679         { 35,  { 0x60, 0x60 } },
680         { 97,  { 0x58, 0x58 } },
681         { 98,  { 0x58, 0x58 } },
682 };
683
684 static const struct antenna_sel antenna_sel_bg[] = {
685         { 96,  { 0x48, 0x68 } },
686         { 104, { 0x2c, 0x3c } },
687         { 75,  { 0xfe, 0x80 } },
688         { 86,  { 0xfe, 0x80 } },
689         { 88,  { 0xfe, 0x80 } },
690         { 35,  { 0x50, 0x50 } },
691         { 97,  { 0x48, 0x48 } },
692         { 98,  { 0x48, 0x48 } },
693 };
694
695 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
696                                struct antenna_setup *ant)
697 {
698         const struct antenna_sel *sel;
699         unsigned int lna;
700         unsigned int i;
701         u32 reg;
702
703         /*
704          * We should never come here because rt2x00lib is supposed
705          * to catch this and send us the correct antenna explicitely.
706          */
707         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
708                ant->tx == ANTENNA_SW_DIVERSITY);
709
710         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
711                 sel = antenna_sel_a;
712                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
713         } else {
714                 sel = antenna_sel_bg;
715                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
716         }
717
718         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
719                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
720
721         rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
722
723         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
724                            (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
725         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
726                            (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
727
728         rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
729
730         if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
731                 rt73usb_config_antenna_5x(rt2x00dev, ant);
732         else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
733                 rt73usb_config_antenna_2x(rt2x00dev, ant);
734 }
735
736 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
737                                     struct rt2x00lib_conf *libconf)
738 {
739         u16 eeprom;
740         short lna_gain = 0;
741
742         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
743                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
744                         lna_gain += 14;
745
746                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
747                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
748         } else {
749                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
750                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
751         }
752
753         rt2x00dev->lna_gain = lna_gain;
754 }
755
756 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
757                                    struct rf_channel *rf, const int txpower)
758 {
759         u8 r3;
760         u8 r94;
761         u8 smart;
762
763         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
764         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
765
766         smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
767
768         rt73usb_bbp_read(rt2x00dev, 3, &r3);
769         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
770         rt73usb_bbp_write(rt2x00dev, 3, r3);
771
772         r94 = 6;
773         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
774                 r94 += txpower - MAX_TXPOWER;
775         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
776                 r94 += txpower;
777         rt73usb_bbp_write(rt2x00dev, 94, r94);
778
779         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
780         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
781         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
782         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
783
784         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
785         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
786         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
787         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
788
789         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
790         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
791         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
792         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
793
794         udelay(10);
795 }
796
797 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
798                                    const int txpower)
799 {
800         struct rf_channel rf;
801
802         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
803         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
804         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
805         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
806
807         rt73usb_config_channel(rt2x00dev, &rf, txpower);
808 }
809
810 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
811                                        struct rt2x00lib_conf *libconf)
812 {
813         u32 reg;
814
815         rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
816         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
817         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
818         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
819         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
820                            libconf->conf->long_frame_max_tx_count);
821         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
822                            libconf->conf->short_frame_max_tx_count);
823         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
824 }
825
826 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
827                                 struct rt2x00lib_conf *libconf)
828 {
829         enum dev_state state =
830             (libconf->conf->flags & IEEE80211_CONF_PS) ?
831                 STATE_SLEEP : STATE_AWAKE;
832         u32 reg;
833
834         if (state == STATE_SLEEP) {
835                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
836                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
837                                    rt2x00dev->beacon_int - 10);
838                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
839                                    libconf->conf->listen_interval - 1);
840                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
841
842                 /* We must first disable autowake before it can be enabled */
843                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
844                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
845
846                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
847                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
848
849                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
850                                             USB_MODE_SLEEP, REGISTER_TIMEOUT);
851         } else {
852                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
853                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
854                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
855                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
856                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
857                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
858
859                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
860                                             USB_MODE_WAKEUP, REGISTER_TIMEOUT);
861         }
862 }
863
864 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
865                            struct rt2x00lib_conf *libconf,
866                            const unsigned int flags)
867 {
868         /* Always recalculate LNA gain before changing configuration */
869         rt73usb_config_lna_gain(rt2x00dev, libconf);
870
871         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
872                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
873                                        libconf->conf->power_level);
874         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
875             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
876                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
877         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
878                 rt73usb_config_retry_limit(rt2x00dev, libconf);
879         if (flags & IEEE80211_CONF_CHANGE_PS)
880                 rt73usb_config_ps(rt2x00dev, libconf);
881 }
882
883 /*
884  * Link tuning
885  */
886 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
887                                struct link_qual *qual)
888 {
889         u32 reg;
890
891         /*
892          * Update FCS error count from register.
893          */
894         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
895         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
896
897         /*
898          * Update False CCA count from register.
899          */
900         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
901         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
902 }
903
904 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
905                                    struct link_qual *qual, u8 vgc_level)
906 {
907         if (qual->vgc_level != vgc_level) {
908                 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
909                 qual->vgc_level = vgc_level;
910                 qual->vgc_level_reg = vgc_level;
911         }
912 }
913
914 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
915                                 struct link_qual *qual)
916 {
917         rt73usb_set_vgc(rt2x00dev, qual, 0x20);
918 }
919
920 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
921                                struct link_qual *qual, const u32 count)
922 {
923         u8 up_bound;
924         u8 low_bound;
925
926         /*
927          * Determine r17 bounds.
928          */
929         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
930                 low_bound = 0x28;
931                 up_bound = 0x48;
932
933                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
934                         low_bound += 0x10;
935                         up_bound += 0x10;
936                 }
937         } else {
938                 if (qual->rssi > -82) {
939                         low_bound = 0x1c;
940                         up_bound = 0x40;
941                 } else if (qual->rssi > -84) {
942                         low_bound = 0x1c;
943                         up_bound = 0x20;
944                 } else {
945                         low_bound = 0x1c;
946                         up_bound = 0x1c;
947                 }
948
949                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
950                         low_bound += 0x14;
951                         up_bound += 0x10;
952                 }
953         }
954
955         /*
956          * If we are not associated, we should go straight to the
957          * dynamic CCA tuning.
958          */
959         if (!rt2x00dev->intf_associated)
960                 goto dynamic_cca_tune;
961
962         /*
963          * Special big-R17 for very short distance
964          */
965         if (qual->rssi > -35) {
966                 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
967                 return;
968         }
969
970         /*
971          * Special big-R17 for short distance
972          */
973         if (qual->rssi >= -58) {
974                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
975                 return;
976         }
977
978         /*
979          * Special big-R17 for middle-short distance
980          */
981         if (qual->rssi >= -66) {
982                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
983                 return;
984         }
985
986         /*
987          * Special mid-R17 for middle distance
988          */
989         if (qual->rssi >= -74) {
990                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
991                 return;
992         }
993
994         /*
995          * Special case: Change up_bound based on the rssi.
996          * Lower up_bound when rssi is weaker then -74 dBm.
997          */
998         up_bound -= 2 * (-74 - qual->rssi);
999         if (low_bound > up_bound)
1000                 up_bound = low_bound;
1001
1002         if (qual->vgc_level > up_bound) {
1003                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
1004                 return;
1005         }
1006
1007 dynamic_cca_tune:
1008
1009         /*
1010          * r17 does not yet exceed upper limit, continue and base
1011          * the r17 tuning on the false CCA count.
1012          */
1013         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1014                 rt73usb_set_vgc(rt2x00dev, qual,
1015                                 min_t(u8, qual->vgc_level + 4, up_bound));
1016         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1017                 rt73usb_set_vgc(rt2x00dev, qual,
1018                                 max_t(u8, qual->vgc_level - 4, low_bound));
1019 }
1020
1021 /*
1022  * Queue handlers.
1023  */
1024 static void rt73usb_start_queue(struct data_queue *queue)
1025 {
1026         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1027         u32 reg;
1028
1029         switch (queue->qid) {
1030         case QID_RX:
1031                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1032                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1033                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1034                 break;
1035         case QID_BEACON:
1036                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1037                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1038                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1039                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1040                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1041                 break;
1042         default:
1043                 break;
1044         }
1045 }
1046
1047 static void rt73usb_stop_queue(struct data_queue *queue)
1048 {
1049         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1050         u32 reg;
1051
1052         switch (queue->qid) {
1053         case QID_RX:
1054                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1055                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1056                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1057                 break;
1058         case QID_BEACON:
1059                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1060                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1061                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1062                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1063                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1064                 break;
1065         default:
1066                 break;
1067         }
1068 }
1069
1070 /*
1071  * Firmware functions
1072  */
1073 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1074 {
1075         return FIRMWARE_RT2571;
1076 }
1077
1078 static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1079                                   const u8 *data, const size_t len)
1080 {
1081         u16 fw_crc;
1082         u16 crc;
1083
1084         /*
1085          * Only support 2kb firmware files.
1086          */
1087         if (len != 2048)
1088                 return FW_BAD_LENGTH;
1089
1090         /*
1091          * The last 2 bytes in the firmware array are the crc checksum itself,
1092          * this means that we should never pass those 2 bytes to the crc
1093          * algorithm.
1094          */
1095         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1096
1097         /*
1098          * Use the crc itu-t algorithm.
1099          */
1100         crc = crc_itu_t(0, data, len - 2);
1101         crc = crc_itu_t_byte(crc, 0);
1102         crc = crc_itu_t_byte(crc, 0);
1103
1104         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1105 }
1106
1107 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1108                                  const u8 *data, const size_t len)
1109 {
1110         unsigned int i;
1111         int status;
1112         u32 reg;
1113
1114         /*
1115          * Wait for stable hardware.
1116          */
1117         for (i = 0; i < 100; i++) {
1118                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1119                 if (reg)
1120                         break;
1121                 msleep(1);
1122         }
1123
1124         if (!reg) {
1125                 ERROR(rt2x00dev, "Unstable hardware.\n");
1126                 return -EBUSY;
1127         }
1128
1129         /*
1130          * Write firmware to device.
1131          */
1132         rt2x00usb_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, data, len);
1133
1134         /*
1135          * Send firmware request to device to load firmware,
1136          * we need to specify a long timeout time.
1137          */
1138         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1139                                              0, USB_MODE_FIRMWARE,
1140                                              REGISTER_TIMEOUT_FIRMWARE);
1141         if (status < 0) {
1142                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1143                 return status;
1144         }
1145
1146         return 0;
1147 }
1148
1149 /*
1150  * Initialization functions.
1151  */
1152 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1153 {
1154         u32 reg;
1155
1156         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1157         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1158         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1159         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1160         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1161
1162         rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1163         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1164         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1165         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1166         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1167         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1168         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1169         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1170         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1171         rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1172
1173         /*
1174          * CCK TXD BBP registers
1175          */
1176         rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1177         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1178         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1179         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1180         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1181         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1182         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1183         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1184         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1185         rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1186
1187         /*
1188          * OFDM TXD BBP registers
1189          */
1190         rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1191         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1192         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1193         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1194         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1195         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1196         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1197         rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1198
1199         rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1200         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1201         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1202         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1203         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1204         rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1205
1206         rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1207         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1208         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1209         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1210         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1211         rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1212
1213         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1214         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1215         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1216         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1217         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1218         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1219         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1220         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1221
1222         rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1223
1224         rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1225         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1226         rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1227
1228         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1229
1230         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1231                 return -EBUSY;
1232
1233         rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1234
1235         /*
1236          * Invalidate all Shared Keys (SEC_CSR0),
1237          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1238          */
1239         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1240         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1241         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1242
1243         reg = 0x000023b0;
1244         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
1245                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1246         rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1247
1248         rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1249         rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1250         rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1251
1252         rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1253         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1254         rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1255
1256         /*
1257          * Clear all beacons
1258          * For the Beacon base registers we only need to clear
1259          * the first byte since that byte contains the VALID and OWNER
1260          * bits which (when set to 0) will invalidate the entire beacon.
1261          */
1262         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1263         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1264         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1265         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1266
1267         /*
1268          * We must clear the error counters.
1269          * These registers are cleared on read,
1270          * so we may pass a useless variable to store the value.
1271          */
1272         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1273         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1274         rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1275
1276         /*
1277          * Reset MAC and BBP registers.
1278          */
1279         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1280         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1281         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1282         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1283
1284         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1285         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1286         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1287         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1288
1289         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1290         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1291         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1292
1293         return 0;
1294 }
1295
1296 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1297 {
1298         unsigned int i;
1299         u8 value;
1300
1301         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1302                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1303                 if ((value != 0xff) && (value != 0x00))
1304                         return 0;
1305                 udelay(REGISTER_BUSY_DELAY);
1306         }
1307
1308         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1309         return -EACCES;
1310 }
1311
1312 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1313 {
1314         unsigned int i;
1315         u16 eeprom;
1316         u8 reg_id;
1317         u8 value;
1318
1319         if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1320                 return -EACCES;
1321
1322         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1323         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1324         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1325         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1326         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1327         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1328         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1329         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1330         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1331         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1332         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1333         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1334         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1335         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1336         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1337         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1338         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1339         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1340         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1341         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1342         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1343         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1344         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1345         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1346         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1347
1348         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1349                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1350
1351                 if (eeprom != 0xffff && eeprom != 0x0000) {
1352                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1353                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1354                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1355                 }
1356         }
1357
1358         return 0;
1359 }
1360
1361 /*
1362  * Device state switch handlers.
1363  */
1364 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1365 {
1366         /*
1367          * Initialize all registers.
1368          */
1369         if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1370                      rt73usb_init_bbp(rt2x00dev)))
1371                 return -EIO;
1372
1373         return 0;
1374 }
1375
1376 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1377 {
1378         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1379
1380         /*
1381          * Disable synchronisation.
1382          */
1383         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1384
1385         rt2x00usb_disable_radio(rt2x00dev);
1386 }
1387
1388 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1389 {
1390         u32 reg, reg2;
1391         unsigned int i;
1392         char put_to_sleep;
1393
1394         put_to_sleep = (state != STATE_AWAKE);
1395
1396         rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1397         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1398         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1399         rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1400
1401         /*
1402          * Device is not guaranteed to be in the requested state yet.
1403          * We must wait until the register indicates that the
1404          * device has entered the correct state.
1405          */
1406         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1407                 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg2);
1408                 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1409                 if (state == !put_to_sleep)
1410                         return 0;
1411                 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1412                 msleep(10);
1413         }
1414
1415         return -EBUSY;
1416 }
1417
1418 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1419                                     enum dev_state state)
1420 {
1421         int retval = 0;
1422
1423         switch (state) {
1424         case STATE_RADIO_ON:
1425                 retval = rt73usb_enable_radio(rt2x00dev);
1426                 break;
1427         case STATE_RADIO_OFF:
1428                 rt73usb_disable_radio(rt2x00dev);
1429                 break;
1430         case STATE_RADIO_IRQ_ON:
1431         case STATE_RADIO_IRQ_OFF:
1432                 /* No support, but no error either */
1433                 break;
1434         case STATE_DEEP_SLEEP:
1435         case STATE_SLEEP:
1436         case STATE_STANDBY:
1437         case STATE_AWAKE:
1438                 retval = rt73usb_set_state(rt2x00dev, state);
1439                 break;
1440         default:
1441                 retval = -ENOTSUPP;
1442                 break;
1443         }
1444
1445         if (unlikely(retval))
1446                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1447                       state, retval);
1448
1449         return retval;
1450 }
1451
1452 /*
1453  * TX descriptor initialization
1454  */
1455 static void rt73usb_write_tx_desc(struct queue_entry *entry,
1456                                   struct txentry_desc *txdesc)
1457 {
1458         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1459         __le32 *txd = (__le32 *) entry->skb->data;
1460         u32 word;
1461
1462         /*
1463          * Start writing the descriptor words.
1464          */
1465         rt2x00_desc_read(txd, 0, &word);
1466         rt2x00_set_field32(&word, TXD_W0_BURST,
1467                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1468         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1469         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1470                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1471         rt2x00_set_field32(&word, TXD_W0_ACK,
1472                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1473         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1474                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1475         rt2x00_set_field32(&word, TXD_W0_OFDM,
1476                            (txdesc->rate_mode == RATE_MODE_OFDM));
1477         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1478         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1479                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1480         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1481                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1482         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1483                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1484         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1485         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1486         rt2x00_set_field32(&word, TXD_W0_BURST2,
1487                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1488         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1489         rt2x00_desc_write(txd, 0, word);
1490
1491         rt2x00_desc_read(txd, 1, &word);
1492         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1493         rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1494         rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1495         rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1496         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1497         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1498                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1499         rt2x00_desc_write(txd, 1, word);
1500
1501         rt2x00_desc_read(txd, 2, &word);
1502         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1503         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1504         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1505         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1506         rt2x00_desc_write(txd, 2, word);
1507
1508         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1509                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1510                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1511         }
1512
1513         rt2x00_desc_read(txd, 5, &word);
1514         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1515                            TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1516         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1517         rt2x00_desc_write(txd, 5, word);
1518
1519         /*
1520          * Register descriptor details in skb frame descriptor.
1521          */
1522         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1523         skbdesc->desc = txd;
1524         skbdesc->desc_len = TXD_DESC_SIZE;
1525 }
1526
1527 /*
1528  * TX data initialization
1529  */
1530 static void rt73usb_write_beacon(struct queue_entry *entry,
1531                                  struct txentry_desc *txdesc)
1532 {
1533         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1534         unsigned int beacon_base;
1535         unsigned int padding_len;
1536         u32 reg;
1537
1538         /*
1539          * Disable beaconing while we are reloading the beacon data,
1540          * otherwise we might be sending out invalid data.
1541          */
1542         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1543         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1544         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1545
1546         /*
1547          * Add space for the descriptor in front of the skb.
1548          */
1549         skb_push(entry->skb, TXD_DESC_SIZE);
1550         memset(entry->skb->data, 0, TXD_DESC_SIZE);
1551
1552         /*
1553          * Write the TX descriptor for the beacon.
1554          */
1555         rt73usb_write_tx_desc(entry, txdesc);
1556
1557         /*
1558          * Dump beacon to userspace through debugfs.
1559          */
1560         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1561
1562         /*
1563          * Write entire beacon with descriptor and padding to register.
1564          */
1565         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1566         skb_pad(entry->skb, padding_len);
1567         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1568         rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1569                                       entry->skb->len + padding_len);
1570
1571         /*
1572          * Enable beaconing again.
1573          *
1574          * For Wi-Fi faily generated beacons between participating stations.
1575          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1576          */
1577         rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1578
1579         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1580         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1581
1582         /*
1583          * Clean up the beacon skb.
1584          */
1585         dev_kfree_skb(entry->skb);
1586         entry->skb = NULL;
1587 }
1588
1589 static void rt73usb_clear_beacon(struct queue_entry *entry)
1590 {
1591         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1592         unsigned int beacon_base;
1593         u32 reg;
1594
1595         /*
1596          * Disable beaconing while we are reloading the beacon data,
1597          * otherwise we might be sending out invalid data.
1598          */
1599         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1600         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1601         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1602
1603         /*
1604          * Clear beacon.
1605          */
1606         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1607         rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
1608
1609         /*
1610          * Enable beaconing again.
1611          */
1612         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1613         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1614 }
1615
1616 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1617 {
1618         int length;
1619
1620         /*
1621          * The length _must_ be a multiple of 4,
1622          * but it must _not_ be a multiple of the USB packet size.
1623          */
1624         length = roundup(entry->skb->len, 4);
1625         length += (4 * !(length % entry->queue->usb_maxpacket));
1626
1627         return length;
1628 }
1629
1630 /*
1631  * RX control handlers
1632  */
1633 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1634 {
1635         u8 offset = rt2x00dev->lna_gain;
1636         u8 lna;
1637
1638         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1639         switch (lna) {
1640         case 3:
1641                 offset += 90;
1642                 break;
1643         case 2:
1644                 offset += 74;
1645                 break;
1646         case 1:
1647                 offset += 64;
1648                 break;
1649         default:
1650                 return 0;
1651         }
1652
1653         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1654                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1655                         if (lna == 3 || lna == 2)
1656                                 offset += 10;
1657                 } else {
1658                         if (lna == 3)
1659                                 offset += 6;
1660                         else if (lna == 2)
1661                                 offset += 8;
1662                 }
1663         }
1664
1665         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1666 }
1667
1668 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1669                                 struct rxdone_entry_desc *rxdesc)
1670 {
1671         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1672         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1673         __le32 *rxd = (__le32 *)entry->skb->data;
1674         u32 word0;
1675         u32 word1;
1676
1677         /*
1678          * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1679          * frame data in rt2x00usb.
1680          */
1681         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1682         rxd = (__le32 *)skbdesc->desc;
1683
1684         /*
1685          * It is now safe to read the descriptor on all architectures.
1686          */
1687         rt2x00_desc_read(rxd, 0, &word0);
1688         rt2x00_desc_read(rxd, 1, &word1);
1689
1690         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1691                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1692
1693         rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1694         rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1695
1696         if (rxdesc->cipher != CIPHER_NONE) {
1697                 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1698                 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
1699                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1700
1701                 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1702                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1703
1704                 /*
1705                  * Hardware has stripped IV/EIV data from 802.11 frame during
1706                  * decryption. It has provided the data separately but rt2x00lib
1707                  * should decide if it should be reinserted.
1708                  */
1709                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1710
1711                 /*
1712                  * FIXME: Legacy driver indicates that the frame does
1713                  * contain the Michael Mic. Unfortunately, in rt2x00
1714                  * the MIC seems to be missing completely...
1715                  */
1716                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1717
1718                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1719                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1720                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1721                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1722         }
1723
1724         /*
1725          * Obtain the status about this packet.
1726          * When frame was received with an OFDM bitrate,
1727          * the signal is the PLCP value. If it was received with
1728          * a CCK bitrate the signal is the rate in 100kbit/s.
1729          */
1730         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1731         rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1732         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1733
1734         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1735                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1736         else
1737                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1738         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1739                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1740
1741         /*
1742          * Set skb pointers, and update frame information.
1743          */
1744         skb_pull(entry->skb, entry->queue->desc_size);
1745         skb_trim(entry->skb, rxdesc->size);
1746 }
1747
1748 /*
1749  * Device probe functions.
1750  */
1751 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1752 {
1753         u16 word;
1754         u8 *mac;
1755         s8 value;
1756
1757         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1758
1759         /*
1760          * Start validation of the data that has been read.
1761          */
1762         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1763         if (!is_valid_ether_addr(mac)) {
1764                 random_ether_addr(mac);
1765                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1766         }
1767
1768         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1769         if (word == 0xffff) {
1770                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1771                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1772                                    ANTENNA_B);
1773                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1774                                    ANTENNA_B);
1775                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1776                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1777                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1778                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1779                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1780                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1781         }
1782
1783         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1784         if (word == 0xffff) {
1785                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1786                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1787                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1788         }
1789
1790         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1791         if (word == 0xffff) {
1792                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1793                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1794                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1795                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1796                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1797                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1798                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1799                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1800                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1801                                    LED_MODE_DEFAULT);
1802                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1803                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1804         }
1805
1806         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1807         if (word == 0xffff) {
1808                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1809                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1810                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1811                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1812         }
1813
1814         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1815         if (word == 0xffff) {
1816                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1817                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1818                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1819                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1820         } else {
1821                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1822                 if (value < -10 || value > 10)
1823                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1824                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1825                 if (value < -10 || value > 10)
1826                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1827                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1828         }
1829
1830         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1831         if (word == 0xffff) {
1832                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1833                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1834                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1835                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1836         } else {
1837                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1838                 if (value < -10 || value > 10)
1839                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1840                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1841                 if (value < -10 || value > 10)
1842                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1843                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1844         }
1845
1846         return 0;
1847 }
1848
1849 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1850 {
1851         u32 reg;
1852         u16 value;
1853         u16 eeprom;
1854
1855         /*
1856          * Read EEPROM word for configuration.
1857          */
1858         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1859
1860         /*
1861          * Identify RF chipset.
1862          */
1863         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1864         rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1865         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1866                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
1867
1868         if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
1869                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1870                 return -ENODEV;
1871         }
1872
1873         if (!rt2x00_rf(rt2x00dev, RF5226) &&
1874             !rt2x00_rf(rt2x00dev, RF2528) &&
1875             !rt2x00_rf(rt2x00dev, RF5225) &&
1876             !rt2x00_rf(rt2x00dev, RF2527)) {
1877                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1878                 return -ENODEV;
1879         }
1880
1881         /*
1882          * Identify default antenna configuration.
1883          */
1884         rt2x00dev->default_ant.tx =
1885             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1886         rt2x00dev->default_ant.rx =
1887             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1888
1889         /*
1890          * Read the Frame type.
1891          */
1892         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1893                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1894
1895         /*
1896          * Detect if this device has an hardware controlled radio.
1897          */
1898         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1899                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1900
1901         /*
1902          * Read frequency offset.
1903          */
1904         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1905         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1906
1907         /*
1908          * Read external LNA informations.
1909          */
1910         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1911
1912         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1913                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1914                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1915         }
1916
1917         /*
1918          * Store led settings, for correct led behaviour.
1919          */
1920 #ifdef CONFIG_RT2X00_LIB_LEDS
1921         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1922
1923         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1924         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1925         if (value == LED_MODE_SIGNAL_STRENGTH)
1926                 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1927                                  LED_TYPE_QUALITY);
1928
1929         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1930         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1931                            rt2x00_get_field16(eeprom,
1932                                               EEPROM_LED_POLARITY_GPIO_0));
1933         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1934                            rt2x00_get_field16(eeprom,
1935                                               EEPROM_LED_POLARITY_GPIO_1));
1936         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1937                            rt2x00_get_field16(eeprom,
1938                                               EEPROM_LED_POLARITY_GPIO_2));
1939         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1940                            rt2x00_get_field16(eeprom,
1941                                               EEPROM_LED_POLARITY_GPIO_3));
1942         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1943                            rt2x00_get_field16(eeprom,
1944                                               EEPROM_LED_POLARITY_GPIO_4));
1945         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1946                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1947         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1948                            rt2x00_get_field16(eeprom,
1949                                               EEPROM_LED_POLARITY_RDY_G));
1950         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1951                            rt2x00_get_field16(eeprom,
1952                                               EEPROM_LED_POLARITY_RDY_A));
1953 #endif /* CONFIG_RT2X00_LIB_LEDS */
1954
1955         return 0;
1956 }
1957
1958 /*
1959  * RF value list for RF2528
1960  * Supports: 2.4 GHz
1961  */
1962 static const struct rf_channel rf_vals_bg_2528[] = {
1963         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1964         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1965         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1966         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1967         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1968         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1969         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1970         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1971         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1972         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1973         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1974         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1975         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1976         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1977 };
1978
1979 /*
1980  * RF value list for RF5226
1981  * Supports: 2.4 GHz & 5.2 GHz
1982  */
1983 static const struct rf_channel rf_vals_5226[] = {
1984         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1985         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1986         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1987         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1988         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1989         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1990         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1991         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1992         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1993         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1994         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1995         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1996         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1997         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1998
1999         /* 802.11 UNI / HyperLan 2 */
2000         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
2001         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
2002         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
2003         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
2004         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
2005         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2006         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2007         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2008
2009         /* 802.11 HyperLan 2 */
2010         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2011         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2012         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2013         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2014         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2015         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2016         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2017         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2018         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2019         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2020
2021         /* 802.11 UNII */
2022         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2023         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2024         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2025         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2026         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2027         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2028
2029         /* MMAC(Japan)J52 ch 34,38,42,46 */
2030         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2031         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2032         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2033         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2034 };
2035
2036 /*
2037  * RF value list for RF5225 & RF2527
2038  * Supports: 2.4 GHz & 5.2 GHz
2039  */
2040 static const struct rf_channel rf_vals_5225_2527[] = {
2041         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2042         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2043         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2044         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2045         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2046         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2047         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2048         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2049         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2050         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2051         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2052         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2053         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2054         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2055
2056         /* 802.11 UNI / HyperLan 2 */
2057         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2058         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2059         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2060         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2061         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2062         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2063         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2064         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2065
2066         /* 802.11 HyperLan 2 */
2067         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2068         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2069         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2070         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2071         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2072         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2073         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2074         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2075         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2076         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2077
2078         /* 802.11 UNII */
2079         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2080         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2081         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2082         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2083         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2084         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2085
2086         /* MMAC(Japan)J52 ch 34,38,42,46 */
2087         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2088         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2089         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2090         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2091 };
2092
2093
2094 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2095 {
2096         struct hw_mode_spec *spec = &rt2x00dev->spec;
2097         struct channel_info *info;
2098         char *tx_power;
2099         unsigned int i;
2100
2101         /*
2102          * Initialize all hw fields.
2103          *
2104          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING unless we are
2105          * capable of sending the buffered frames out after the DTIM
2106          * transmission using rt2x00lib_beacondone. This will send out
2107          * multicast and broadcast traffic immediately instead of buffering it
2108          * infinitly and thus dropping it after some time.
2109          */
2110         rt2x00dev->hw->flags =
2111             IEEE80211_HW_SIGNAL_DBM |
2112             IEEE80211_HW_SUPPORTS_PS |
2113             IEEE80211_HW_PS_NULLFUNC_STACK;
2114
2115         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2116         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2117                                 rt2x00_eeprom_addr(rt2x00dev,
2118                                                    EEPROM_MAC_ADDR_0));
2119
2120         /*
2121          * Initialize hw_mode information.
2122          */
2123         spec->supported_bands = SUPPORT_BAND_2GHZ;
2124         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2125
2126         if (rt2x00_rf(rt2x00dev, RF2528)) {
2127                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2128                 spec->channels = rf_vals_bg_2528;
2129         } else if (rt2x00_rf(rt2x00dev, RF5226)) {
2130                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2131                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2132                 spec->channels = rf_vals_5226;
2133         } else if (rt2x00_rf(rt2x00dev, RF2527)) {
2134                 spec->num_channels = 14;
2135                 spec->channels = rf_vals_5225_2527;
2136         } else if (rt2x00_rf(rt2x00dev, RF5225)) {
2137                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2138                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2139                 spec->channels = rf_vals_5225_2527;
2140         }
2141
2142         /*
2143          * Create channel information array
2144          */
2145         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2146         if (!info)
2147                 return -ENOMEM;
2148
2149         spec->channels_info = info;
2150
2151         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2152         for (i = 0; i < 14; i++) {
2153                 info[i].max_power = MAX_TXPOWER;
2154                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2155         }
2156
2157         if (spec->num_channels > 14) {
2158                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2159                 for (i = 14; i < spec->num_channels; i++) {
2160                         info[i].max_power = MAX_TXPOWER;
2161                         info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2162                 }
2163         }
2164
2165         return 0;
2166 }
2167
2168 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2169 {
2170         int retval;
2171
2172         /*
2173          * Allocate eeprom data.
2174          */
2175         retval = rt73usb_validate_eeprom(rt2x00dev);
2176         if (retval)
2177                 return retval;
2178
2179         retval = rt73usb_init_eeprom(rt2x00dev);
2180         if (retval)
2181                 return retval;
2182
2183         /*
2184          * Initialize hw specifications.
2185          */
2186         retval = rt73usb_probe_hw_mode(rt2x00dev);
2187         if (retval)
2188                 return retval;
2189
2190         /*
2191          * This device has multiple filters for control frames,
2192          * but has no a separate filter for PS Poll frames.
2193          */
2194         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2195
2196         /*
2197          * This device requires firmware.
2198          */
2199         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2200         if (!modparam_nohwcrypt)
2201                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2202         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
2203         __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags);
2204
2205         /*
2206          * Set the rssi offset.
2207          */
2208         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2209
2210         return 0;
2211 }
2212
2213 /*
2214  * IEEE80211 stack callback functions.
2215  */
2216 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2217                            const struct ieee80211_tx_queue_params *params)
2218 {
2219         struct rt2x00_dev *rt2x00dev = hw->priv;
2220         struct data_queue *queue;
2221         struct rt2x00_field32 field;
2222         int retval;
2223         u32 reg;
2224         u32 offset;
2225
2226         /*
2227          * First pass the configuration through rt2x00lib, that will
2228          * update the queue settings and validate the input. After that
2229          * we are free to update the registers based on the value
2230          * in the queue parameter.
2231          */
2232         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2233         if (retval)
2234                 return retval;
2235
2236         /*
2237          * We only need to perform additional register initialization
2238          * for WMM queues/
2239          */
2240         if (queue_idx >= 4)
2241                 return 0;
2242
2243         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2244
2245         /* Update WMM TXOP register */
2246         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2247         field.bit_offset = (queue_idx & 1) * 16;
2248         field.bit_mask = 0xffff << field.bit_offset;
2249
2250         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2251         rt2x00_set_field32(&reg, field, queue->txop);
2252         rt2x00usb_register_write(rt2x00dev, offset, reg);
2253
2254         /* Update WMM registers */
2255         field.bit_offset = queue_idx * 4;
2256         field.bit_mask = 0xf << field.bit_offset;
2257
2258         rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2259         rt2x00_set_field32(&reg, field, queue->aifs);
2260         rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2261
2262         rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2263         rt2x00_set_field32(&reg, field, queue->cw_min);
2264         rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2265
2266         rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2267         rt2x00_set_field32(&reg, field, queue->cw_max);
2268         rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2269
2270         return 0;
2271 }
2272
2273 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2274 {
2275         struct rt2x00_dev *rt2x00dev = hw->priv;
2276         u64 tsf;
2277         u32 reg;
2278
2279         rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2280         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2281         rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2282         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2283
2284         return tsf;
2285 }
2286
2287 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2288         .tx                     = rt2x00mac_tx,
2289         .start                  = rt2x00mac_start,
2290         .stop                   = rt2x00mac_stop,
2291         .add_interface          = rt2x00mac_add_interface,
2292         .remove_interface       = rt2x00mac_remove_interface,
2293         .config                 = rt2x00mac_config,
2294         .configure_filter       = rt2x00mac_configure_filter,
2295         .set_tim                = rt2x00mac_set_tim,
2296         .set_key                = rt2x00mac_set_key,
2297         .sw_scan_start          = rt2x00mac_sw_scan_start,
2298         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2299         .get_stats              = rt2x00mac_get_stats,
2300         .bss_info_changed       = rt2x00mac_bss_info_changed,
2301         .conf_tx                = rt73usb_conf_tx,
2302         .get_tsf                = rt73usb_get_tsf,
2303         .rfkill_poll            = rt2x00mac_rfkill_poll,
2304         .flush                  = rt2x00mac_flush,
2305 };
2306
2307 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2308         .probe_hw               = rt73usb_probe_hw,
2309         .get_firmware_name      = rt73usb_get_firmware_name,
2310         .check_firmware         = rt73usb_check_firmware,
2311         .load_firmware          = rt73usb_load_firmware,
2312         .initialize             = rt2x00usb_initialize,
2313         .uninitialize           = rt2x00usb_uninitialize,
2314         .clear_entry            = rt2x00usb_clear_entry,
2315         .set_device_state       = rt73usb_set_device_state,
2316         .rfkill_poll            = rt73usb_rfkill_poll,
2317         .link_stats             = rt73usb_link_stats,
2318         .reset_tuner            = rt73usb_reset_tuner,
2319         .link_tuner             = rt73usb_link_tuner,
2320         .watchdog               = rt2x00usb_watchdog,
2321         .start_queue            = rt73usb_start_queue,
2322         .kick_queue             = rt2x00usb_kick_queue,
2323         .stop_queue             = rt73usb_stop_queue,
2324         .flush_queue            = rt2x00usb_flush_queue,
2325         .write_tx_desc          = rt73usb_write_tx_desc,
2326         .write_beacon           = rt73usb_write_beacon,
2327         .clear_beacon           = rt73usb_clear_beacon,
2328         .get_tx_data_len        = rt73usb_get_tx_data_len,
2329         .fill_rxdone            = rt73usb_fill_rxdone,
2330         .config_shared_key      = rt73usb_config_shared_key,
2331         .config_pairwise_key    = rt73usb_config_pairwise_key,
2332         .config_filter          = rt73usb_config_filter,
2333         .config_intf            = rt73usb_config_intf,
2334         .config_erp             = rt73usb_config_erp,
2335         .config_ant             = rt73usb_config_ant,
2336         .config                 = rt73usb_config,
2337 };
2338
2339 static const struct data_queue_desc rt73usb_queue_rx = {
2340         .entry_num              = 32,
2341         .data_size              = DATA_FRAME_SIZE,
2342         .desc_size              = RXD_DESC_SIZE,
2343         .priv_size              = sizeof(struct queue_entry_priv_usb),
2344 };
2345
2346 static const struct data_queue_desc rt73usb_queue_tx = {
2347         .entry_num              = 32,
2348         .data_size              = DATA_FRAME_SIZE,
2349         .desc_size              = TXD_DESC_SIZE,
2350         .priv_size              = sizeof(struct queue_entry_priv_usb),
2351 };
2352
2353 static const struct data_queue_desc rt73usb_queue_bcn = {
2354         .entry_num              = 4,
2355         .data_size              = MGMT_FRAME_SIZE,
2356         .desc_size              = TXINFO_SIZE,
2357         .priv_size              = sizeof(struct queue_entry_priv_usb),
2358 };
2359
2360 static const struct rt2x00_ops rt73usb_ops = {
2361         .name                   = KBUILD_MODNAME,
2362         .max_sta_intf           = 1,
2363         .max_ap_intf            = 4,
2364         .eeprom_size            = EEPROM_SIZE,
2365         .rf_size                = RF_SIZE,
2366         .tx_queues              = NUM_TX_QUEUES,
2367         .extra_tx_headroom      = TXD_DESC_SIZE,
2368         .rx                     = &rt73usb_queue_rx,
2369         .tx                     = &rt73usb_queue_tx,
2370         .bcn                    = &rt73usb_queue_bcn,
2371         .lib                    = &rt73usb_rt2x00_ops,
2372         .hw                     = &rt73usb_mac80211_ops,
2373 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2374         .debugfs                = &rt73usb_rt2x00debug,
2375 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2376 };
2377
2378 /*
2379  * rt73usb module information.
2380  */
2381 static struct usb_device_id rt73usb_device_table[] = {
2382         /* AboCom */
2383         { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2384         { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
2385         { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2386         { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2387         { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2388         /* AL */
2389         { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
2390         /* Amigo */
2391         { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2392         { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2393         /* AMIT  */
2394         { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
2395         /* Askey */
2396         { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2397         /* ASUS */
2398         { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2399         { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2400         /* Belkin */
2401         { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2402         { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2403         { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2404         { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2405         /* Billionton */
2406         { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2407         { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
2408         /* Buffalo */
2409         { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
2410         { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) },
2411         { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2412         { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2413         { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
2414         { USB_DEVICE(0x0411, 0x0137), USB_DEVICE_DATA(&rt73usb_ops) },
2415         /* CEIVA */
2416         { USB_DEVICE(0x178d, 0x02be), USB_DEVICE_DATA(&rt73usb_ops) },
2417         /* CNet */
2418         { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2419         { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2420         /* Conceptronic */
2421         { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2422         /* Corega */
2423         { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2424         /* D-Link */
2425         { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2426         { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2427         { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2428         { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2429         /* Edimax */
2430         { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2431         { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2432         /* EnGenius */
2433         { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
2434         /* Gemtek */
2435         { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2436         /* Gigabyte */
2437         { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2438         { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2439         /* Huawei-3Com */
2440         { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2441         /* Hercules */
2442         { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) },
2443         { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2444         { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2445         /* Linksys */
2446         { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2447         { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2448         { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
2449         /* MSI */
2450         { USB_DEVICE(0x0db0, 0x4600), USB_DEVICE_DATA(&rt73usb_ops) },
2451         { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2452         { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2453         { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2454         { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2455         /* Ovislink */
2456         { USB_DEVICE(0x1b75, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2457         /* Ralink */
2458         { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
2459         { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2460         { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2461         { USB_DEVICE(0x0812, 0x3101), USB_DEVICE_DATA(&rt73usb_ops) },
2462         /* Qcom */
2463         { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2464         { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2465         { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2466         /* Samsung */
2467         { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
2468         /* Senao */
2469         { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2470         /* Sitecom */
2471         { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2472         { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2473         { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
2474         { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2475         { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2476         /* Surecom */
2477         { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2478         /* Tilgin */
2479         { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
2480         /* Philips */
2481         { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
2482         /* Planex */
2483         { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2484         { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2485         /* WideTell */
2486         { USB_DEVICE(0x7167, 0x3840), USB_DEVICE_DATA(&rt73usb_ops) },
2487         /* Zcom */
2488         { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
2489         /* ZyXEL */
2490         { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
2491         { 0, }
2492 };
2493
2494 MODULE_AUTHOR(DRV_PROJECT);
2495 MODULE_VERSION(DRV_VERSION);
2496 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2497 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2498 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2499 MODULE_FIRMWARE(FIRMWARE_RT2571);
2500 MODULE_LICENSE("GPL");
2501
2502 static struct usb_driver rt73usb_driver = {
2503         .name           = KBUILD_MODNAME,
2504         .id_table       = rt73usb_device_table,
2505         .probe          = rt2x00usb_probe,
2506         .disconnect     = rt2x00usb_disconnect,
2507         .suspend        = rt2x00usb_suspend,
2508         .resume         = rt2x00usb_resume,
2509 };
2510
2511 static int __init rt73usb_init(void)
2512 {
2513         return usb_register(&rt73usb_driver);
2514 }
2515
2516 static void __exit rt73usb_exit(void)
2517 {
2518         usb_deregister(&rt73usb_driver);
2519 }
2520
2521 module_init(rt73usb_init);
2522 module_exit(rt73usb_exit);