1cbd9b4a3efc9c560784280e7c76f6160be00161
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt73usb.c
1 /*
2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt73usb
23         Abstract: rt73usb device specific routines.
24         Supported chipsets: rt2571W & rt2671.
25  */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/usb.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00usb.h"
37 #include "rt73usb.h"
38
39 /*
40  * Allow hardware encryption to be disabled.
41  */
42 static int modparam_nohwcrypt = 0;
43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
46 /*
47  * Register access.
48  * All access to the CSR registers will go through the methods
49  * rt2x00usb_register_read and rt2x00usb_register_write.
50  * BBP and RF register require indirect register access,
51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
52  * These indirect registers work with busy bits,
53  * and we will try maximal REGISTER_BUSY_COUNT times to access
54  * the register while taking a REGISTER_BUSY_DELAY us delay
55  * between each attampt. When the busy bit is still set at that time,
56  * the access attempt is considered to have failed,
57  * and we will print an error.
58  * The _lock versions must be used if you already hold the csr_mutex
59  */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61         rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
62 #define WAIT_FOR_RF(__dev, __reg) \
63         rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
64
65 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
66                               const unsigned int word, const u8 value)
67 {
68         u32 reg;
69
70         mutex_lock(&rt2x00dev->csr_mutex);
71
72         /*
73          * Wait until the BBP becomes available, afterwards we
74          * can safely write the new data into the register.
75          */
76         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
77                 reg = 0;
78                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
79                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
80                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
81                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
82
83                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
84         }
85
86         mutex_unlock(&rt2x00dev->csr_mutex);
87 }
88
89 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
90                              const unsigned int word, u8 *value)
91 {
92         u32 reg;
93
94         mutex_lock(&rt2x00dev->csr_mutex);
95
96         /*
97          * Wait until the BBP becomes available, afterwards we
98          * can safely write the read request into the register.
99          * After the data has been written, we wait until hardware
100          * returns the correct value, if at any time the register
101          * doesn't become available in time, reg will be 0xffffffff
102          * which means we return 0xff to the caller.
103          */
104         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
105                 reg = 0;
106                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
107                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
109
110                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
111
112                 WAIT_FOR_BBP(rt2x00dev, &reg);
113         }
114
115         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
116
117         mutex_unlock(&rt2x00dev->csr_mutex);
118 }
119
120 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
121                              const unsigned int word, const u32 value)
122 {
123         u32 reg;
124
125         mutex_lock(&rt2x00dev->csr_mutex);
126
127         /*
128          * Wait until the RF becomes available, afterwards we
129          * can safely write the new data into the register.
130          */
131         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
132                 reg = 0;
133                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
134                 /*
135                  * RF5225 and RF2527 contain 21 bits per RF register value,
136                  * all others contain 20 bits.
137                  */
138                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
139                                    20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
140                                          rt2x00_rf(&rt2x00dev->chip, RF2527)));
141                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
142                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
143
144                 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
145                 rt2x00_rf_write(rt2x00dev, word, value);
146         }
147
148         mutex_unlock(&rt2x00dev->csr_mutex);
149 }
150
151 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
152 static const struct rt2x00debug rt73usb_rt2x00debug = {
153         .owner  = THIS_MODULE,
154         .csr    = {
155                 .read           = rt2x00usb_register_read,
156                 .write          = rt2x00usb_register_write,
157                 .flags          = RT2X00DEBUGFS_OFFSET,
158                 .word_base      = CSR_REG_BASE,
159                 .word_size      = sizeof(u32),
160                 .word_count     = CSR_REG_SIZE / sizeof(u32),
161         },
162         .eeprom = {
163                 .read           = rt2x00_eeprom_read,
164                 .write          = rt2x00_eeprom_write,
165                 .word_base      = EEPROM_BASE,
166                 .word_size      = sizeof(u16),
167                 .word_count     = EEPROM_SIZE / sizeof(u16),
168         },
169         .bbp    = {
170                 .read           = rt73usb_bbp_read,
171                 .write          = rt73usb_bbp_write,
172                 .word_base      = BBP_BASE,
173                 .word_size      = sizeof(u8),
174                 .word_count     = BBP_SIZE / sizeof(u8),
175         },
176         .rf     = {
177                 .read           = rt2x00_rf_read,
178                 .write          = rt73usb_rf_write,
179                 .word_base      = RF_BASE,
180                 .word_size      = sizeof(u32),
181                 .word_count     = RF_SIZE / sizeof(u32),
182         },
183 };
184 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
185
186 static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
187 {
188         u32 reg;
189
190         rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
191         return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
192 }
193
194 #ifdef CONFIG_RT2X00_LIB_LEDS
195 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
196                                    enum led_brightness brightness)
197 {
198         struct rt2x00_led *led =
199            container_of(led_cdev, struct rt2x00_led, led_dev);
200         unsigned int enabled = brightness != LED_OFF;
201         unsigned int a_mode =
202             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
203         unsigned int bg_mode =
204             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
205
206         if (led->type == LED_TYPE_RADIO) {
207                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
208                                    MCU_LEDCS_RADIO_STATUS, enabled);
209
210                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
211                                             0, led->rt2x00dev->led_mcu_reg,
212                                             REGISTER_TIMEOUT);
213         } else if (led->type == LED_TYPE_ASSOC) {
214                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
215                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
216                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
217                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
218
219                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
220                                             0, led->rt2x00dev->led_mcu_reg,
221                                             REGISTER_TIMEOUT);
222         } else if (led->type == LED_TYPE_QUALITY) {
223                 /*
224                  * The brightness is divided into 6 levels (0 - 5),
225                  * this means we need to convert the brightness
226                  * argument into the matching level within that range.
227                  */
228                 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
229                                             brightness / (LED_FULL / 6),
230                                             led->rt2x00dev->led_mcu_reg,
231                                             REGISTER_TIMEOUT);
232         }
233 }
234
235 static int rt73usb_blink_set(struct led_classdev *led_cdev,
236                              unsigned long *delay_on,
237                              unsigned long *delay_off)
238 {
239         struct rt2x00_led *led =
240             container_of(led_cdev, struct rt2x00_led, led_dev);
241         u32 reg;
242
243         rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
244         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
245         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
246         rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
247
248         return 0;
249 }
250
251 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
252                              struct rt2x00_led *led,
253                              enum led_type type)
254 {
255         led->rt2x00dev = rt2x00dev;
256         led->type = type;
257         led->led_dev.brightness_set = rt73usb_brightness_set;
258         led->led_dev.blink_set = rt73usb_blink_set;
259         led->flags = LED_INITIALIZED;
260 }
261 #endif /* CONFIG_RT2X00_LIB_LEDS */
262
263 /*
264  * Configuration handlers.
265  */
266 static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
267                                      struct rt2x00lib_crypto *crypto,
268                                      struct ieee80211_key_conf *key)
269 {
270         struct hw_key_entry key_entry;
271         struct rt2x00_field32 field;
272         int timeout;
273         u32 mask;
274         u32 reg;
275
276         if (crypto->cmd == SET_KEY) {
277                 /*
278                  * rt2x00lib can't determine the correct free
279                  * key_idx for shared keys. We have 1 register
280                  * with key valid bits. The goal is simple, read
281                  * the register, if that is full we have no slots
282                  * left.
283                  * Note that each BSS is allowed to have up to 4
284                  * shared keys, so put a mask over the allowed
285                  * entries.
286                  */
287                 mask = (0xf << crypto->bssidx);
288
289                 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
290                 reg &= mask;
291
292                 if (reg && reg == mask)
293                         return -ENOSPC;
294
295                 key->hw_key_idx += reg ? ffz(reg) : 0;
296
297                 /*
298                  * Upload key to hardware
299                  */
300                 memcpy(key_entry.key, crypto->key,
301                        sizeof(key_entry.key));
302                 memcpy(key_entry.tx_mic, crypto->tx_mic,
303                        sizeof(key_entry.tx_mic));
304                 memcpy(key_entry.rx_mic, crypto->rx_mic,
305                        sizeof(key_entry.rx_mic));
306
307                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
308                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
309                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
310                                                     USB_VENDOR_REQUEST_OUT, reg,
311                                                     &key_entry,
312                                                     sizeof(key_entry),
313                                                     timeout);
314
315                 /*
316                  * The cipher types are stored over 2 registers.
317                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
318                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
319                  * Using the correct defines correctly will cause overhead,
320                  * so just calculate the correct offset.
321                  */
322                 if (key->hw_key_idx < 8) {
323                         field.bit_offset = (3 * key->hw_key_idx);
324                         field.bit_mask = 0x7 << field.bit_offset;
325
326                         rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
327                         rt2x00_set_field32(&reg, field, crypto->cipher);
328                         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
329                 } else {
330                         field.bit_offset = (3 * (key->hw_key_idx - 8));
331                         field.bit_mask = 0x7 << field.bit_offset;
332
333                         rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
334                         rt2x00_set_field32(&reg, field, crypto->cipher);
335                         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
336                 }
337
338                 /*
339                  * The driver does not support the IV/EIV generation
340                  * in hardware. However it doesn't support the IV/EIV
341                  * inside the ieee80211 frame either, but requires it
342                  * to be provided seperately for the descriptor.
343                  * rt2x00lib will cut the IV/EIV data out of all frames
344                  * given to us by mac80211, but we must tell mac80211
345                  * to generate the IV/EIV data.
346                  */
347                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
348         }
349
350         /*
351          * SEC_CSR0 contains only single-bit fields to indicate
352          * a particular key is valid. Because using the FIELD32()
353          * defines directly will cause a lot of overhead we use
354          * a calculation to determine the correct bit directly.
355          */
356         mask = 1 << key->hw_key_idx;
357
358         rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
359         if (crypto->cmd == SET_KEY)
360                 reg |= mask;
361         else if (crypto->cmd == DISABLE_KEY)
362                 reg &= ~mask;
363         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
364
365         return 0;
366 }
367
368 static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
369                                        struct rt2x00lib_crypto *crypto,
370                                        struct ieee80211_key_conf *key)
371 {
372         struct hw_pairwise_ta_entry addr_entry;
373         struct hw_key_entry key_entry;
374         int timeout;
375         u32 mask;
376         u32 reg;
377
378         if (crypto->cmd == SET_KEY) {
379                 /*
380                  * rt2x00lib can't determine the correct free
381                  * key_idx for pairwise keys. We have 2 registers
382                  * with key valid bits. The goal is simple, read
383                  * the first register, if that is full move to
384                  * the next register.
385                  * When both registers are full, we drop the key,
386                  * otherwise we use the first invalid entry.
387                  */
388                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
389                 if (reg && reg == ~0) {
390                         key->hw_key_idx = 32;
391                         rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
392                         if (reg && reg == ~0)
393                                 return -ENOSPC;
394                 }
395
396                 key->hw_key_idx += reg ? ffz(reg) : 0;
397
398                 /*
399                  * Upload key to hardware
400                  */
401                 memcpy(key_entry.key, crypto->key,
402                        sizeof(key_entry.key));
403                 memcpy(key_entry.tx_mic, crypto->tx_mic,
404                        sizeof(key_entry.tx_mic));
405                 memcpy(key_entry.rx_mic, crypto->rx_mic,
406                        sizeof(key_entry.rx_mic));
407
408                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
409                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
410                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
411                                                     USB_VENDOR_REQUEST_OUT, reg,
412                                                     &key_entry,
413                                                     sizeof(key_entry),
414                                                     timeout);
415
416                 /*
417                  * Send the address and cipher type to the hardware register.
418                  * This data fits within the CSR cache size, so we can use
419                  * rt2x00usb_register_multiwrite() directly.
420                  */
421                 memset(&addr_entry, 0, sizeof(addr_entry));
422                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
423                 addr_entry.cipher = crypto->cipher;
424
425                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
426                 rt2x00usb_register_multiwrite(rt2x00dev, reg,
427                                             &addr_entry, sizeof(addr_entry));
428
429                 /*
430                  * Enable pairwise lookup table for given BSS idx,
431                  * without this received frames will not be decrypted
432                  * by the hardware.
433                  */
434                 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
435                 reg |= (1 << crypto->bssidx);
436                 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
437
438                 /*
439                  * The driver does not support the IV/EIV generation
440                  * in hardware. However it doesn't support the IV/EIV
441                  * inside the ieee80211 frame either, but requires it
442                  * to be provided seperately for the descriptor.
443                  * rt2x00lib will cut the IV/EIV data out of all frames
444                  * given to us by mac80211, but we must tell mac80211
445                  * to generate the IV/EIV data.
446                  */
447                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
448         }
449
450         /*
451          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
452          * a particular key is valid. Because using the FIELD32()
453          * defines directly will cause a lot of overhead we use
454          * a calculation to determine the correct bit directly.
455          */
456         if (key->hw_key_idx < 32) {
457                 mask = 1 << key->hw_key_idx;
458
459                 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
460                 if (crypto->cmd == SET_KEY)
461                         reg |= mask;
462                 else if (crypto->cmd == DISABLE_KEY)
463                         reg &= ~mask;
464                 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
465         } else {
466                 mask = 1 << (key->hw_key_idx - 32);
467
468                 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
469                 if (crypto->cmd == SET_KEY)
470                         reg |= mask;
471                 else if (crypto->cmd == DISABLE_KEY)
472                         reg &= ~mask;
473                 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
474         }
475
476         return 0;
477 }
478
479 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
480                                   const unsigned int filter_flags)
481 {
482         u32 reg;
483
484         /*
485          * Start configuration steps.
486          * Note that the version error will always be dropped
487          * and broadcast frames will always be accepted since
488          * there is no filter for it at this time.
489          */
490         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
491         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
492                            !(filter_flags & FIF_FCSFAIL));
493         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
494                            !(filter_flags & FIF_PLCPFAIL));
495         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
496                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
497         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
498                            !(filter_flags & FIF_PROMISC_IN_BSS));
499         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
500                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
501                            !rt2x00dev->intf_ap_count);
502         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
503         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
504                            !(filter_flags & FIF_ALLMULTI));
505         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
506         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
507                            !(filter_flags & FIF_CONTROL));
508         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
509 }
510
511 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
512                                 struct rt2x00_intf *intf,
513                                 struct rt2x00intf_conf *conf,
514                                 const unsigned int flags)
515 {
516         unsigned int beacon_base;
517         u32 reg;
518
519         if (flags & CONFIG_UPDATE_TYPE) {
520                 /*
521                  * Clear current synchronisation setup.
522                  * For the Beacon base registers we only need to clear
523                  * the first byte since that byte contains the VALID and OWNER
524                  * bits which (when set to 0) will invalidate the entire beacon.
525                  */
526                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
527                 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
528
529                 /*
530                  * Enable synchronisation.
531                  */
532                 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
533                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
534                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
535                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
536                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
537         }
538
539         if (flags & CONFIG_UPDATE_MAC) {
540                 reg = le32_to_cpu(conf->mac[1]);
541                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
542                 conf->mac[1] = cpu_to_le32(reg);
543
544                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
545                                             conf->mac, sizeof(conf->mac));
546         }
547
548         if (flags & CONFIG_UPDATE_BSSID) {
549                 reg = le32_to_cpu(conf->bssid[1]);
550                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
551                 conf->bssid[1] = cpu_to_le32(reg);
552
553                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
554                                             conf->bssid, sizeof(conf->bssid));
555         }
556 }
557
558 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
559                                struct rt2x00lib_erp *erp)
560 {
561         u32 reg;
562
563         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
564         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
565         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
566         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
567
568         rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
569         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
570         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
571                            !!erp->short_preamble);
572         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
573
574         rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
575
576         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
577         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
578                            erp->beacon_int * 16);
579         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
580
581         rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
582         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
583         rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
584
585         rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
586         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
587         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
588         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
589         rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
590 }
591
592 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
593                                       struct antenna_setup *ant)
594 {
595         u8 r3;
596         u8 r4;
597         u8 r77;
598         u8 temp;
599
600         rt73usb_bbp_read(rt2x00dev, 3, &r3);
601         rt73usb_bbp_read(rt2x00dev, 4, &r4);
602         rt73usb_bbp_read(rt2x00dev, 77, &r77);
603
604         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
605
606         /*
607          * Configure the RX antenna.
608          */
609         switch (ant->rx) {
610         case ANTENNA_HW_DIVERSITY:
611                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
612                 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
613                        && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
614                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
615                 break;
616         case ANTENNA_A:
617                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
618                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
619                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
620                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
621                 else
622                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
623                 break;
624         case ANTENNA_B:
625         default:
626                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
627                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
628                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
629                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
630                 else
631                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
632                 break;
633         }
634
635         rt73usb_bbp_write(rt2x00dev, 77, r77);
636         rt73usb_bbp_write(rt2x00dev, 3, r3);
637         rt73usb_bbp_write(rt2x00dev, 4, r4);
638 }
639
640 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
641                                       struct antenna_setup *ant)
642 {
643         u8 r3;
644         u8 r4;
645         u8 r77;
646
647         rt73usb_bbp_read(rt2x00dev, 3, &r3);
648         rt73usb_bbp_read(rt2x00dev, 4, &r4);
649         rt73usb_bbp_read(rt2x00dev, 77, &r77);
650
651         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
652         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
653                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
654
655         /*
656          * Configure the RX antenna.
657          */
658         switch (ant->rx) {
659         case ANTENNA_HW_DIVERSITY:
660                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
661                 break;
662         case ANTENNA_A:
663                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
664                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
665                 break;
666         case ANTENNA_B:
667         default:
668                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
669                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
670                 break;
671         }
672
673         rt73usb_bbp_write(rt2x00dev, 77, r77);
674         rt73usb_bbp_write(rt2x00dev, 3, r3);
675         rt73usb_bbp_write(rt2x00dev, 4, r4);
676 }
677
678 struct antenna_sel {
679         u8 word;
680         /*
681          * value[0] -> non-LNA
682          * value[1] -> LNA
683          */
684         u8 value[2];
685 };
686
687 static const struct antenna_sel antenna_sel_a[] = {
688         { 96,  { 0x58, 0x78 } },
689         { 104, { 0x38, 0x48 } },
690         { 75,  { 0xfe, 0x80 } },
691         { 86,  { 0xfe, 0x80 } },
692         { 88,  { 0xfe, 0x80 } },
693         { 35,  { 0x60, 0x60 } },
694         { 97,  { 0x58, 0x58 } },
695         { 98,  { 0x58, 0x58 } },
696 };
697
698 static const struct antenna_sel antenna_sel_bg[] = {
699         { 96,  { 0x48, 0x68 } },
700         { 104, { 0x2c, 0x3c } },
701         { 75,  { 0xfe, 0x80 } },
702         { 86,  { 0xfe, 0x80 } },
703         { 88,  { 0xfe, 0x80 } },
704         { 35,  { 0x50, 0x50 } },
705         { 97,  { 0x48, 0x48 } },
706         { 98,  { 0x48, 0x48 } },
707 };
708
709 static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
710                                struct antenna_setup *ant)
711 {
712         const struct antenna_sel *sel;
713         unsigned int lna;
714         unsigned int i;
715         u32 reg;
716
717         /*
718          * We should never come here because rt2x00lib is supposed
719          * to catch this and send us the correct antenna explicitely.
720          */
721         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
722                ant->tx == ANTENNA_SW_DIVERSITY);
723
724         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
725                 sel = antenna_sel_a;
726                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
727         } else {
728                 sel = antenna_sel_bg;
729                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
730         }
731
732         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
733                 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
734
735         rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
736
737         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
738                            (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
739         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
740                            (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
741
742         rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
743
744         if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
745             rt2x00_rf(&rt2x00dev->chip, RF5225))
746                 rt73usb_config_antenna_5x(rt2x00dev, ant);
747         else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
748                  rt2x00_rf(&rt2x00dev->chip, RF2527))
749                 rt73usb_config_antenna_2x(rt2x00dev, ant);
750 }
751
752 static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
753                                     struct rt2x00lib_conf *libconf)
754 {
755         u16 eeprom;
756         short lna_gain = 0;
757
758         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
759                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
760                         lna_gain += 14;
761
762                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
763                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
764         } else {
765                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
766                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
767         }
768
769         rt2x00dev->lna_gain = lna_gain;
770 }
771
772 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
773                                    struct rf_channel *rf, const int txpower)
774 {
775         u8 r3;
776         u8 r94;
777         u8 smart;
778
779         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
780         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
781
782         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
783                   rt2x00_rf(&rt2x00dev->chip, RF2527));
784
785         rt73usb_bbp_read(rt2x00dev, 3, &r3);
786         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
787         rt73usb_bbp_write(rt2x00dev, 3, r3);
788
789         r94 = 6;
790         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
791                 r94 += txpower - MAX_TXPOWER;
792         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
793                 r94 += txpower;
794         rt73usb_bbp_write(rt2x00dev, 94, r94);
795
796         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
797         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
798         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
799         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
800
801         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
802         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
803         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
804         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
805
806         rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
807         rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
808         rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
809         rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
810
811         udelay(10);
812 }
813
814 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
815                                    const int txpower)
816 {
817         struct rf_channel rf;
818
819         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
820         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
821         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
822         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
823
824         rt73usb_config_channel(rt2x00dev, &rf, txpower);
825 }
826
827 static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
828                                        struct rt2x00lib_conf *libconf)
829 {
830         u32 reg;
831
832         rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
833         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
834                            libconf->conf->long_frame_max_tx_count);
835         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
836                            libconf->conf->short_frame_max_tx_count);
837         rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
838 }
839
840 static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
841                                 struct rt2x00lib_conf *libconf)
842 {
843         enum dev_state state =
844             (libconf->conf->flags & IEEE80211_CONF_PS) ?
845                 STATE_SLEEP : STATE_AWAKE;
846         u32 reg;
847
848         if (state == STATE_SLEEP) {
849                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
850                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
851                                    rt2x00dev->beacon_int - 10);
852                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
853                                    libconf->conf->listen_interval - 1);
854                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
855
856                 /* We must first disable autowake before it can be enabled */
857                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
858                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
859
860                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
861                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
862
863                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
864                                             USB_MODE_SLEEP, REGISTER_TIMEOUT);
865         } else {
866                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
867                                             USB_MODE_WAKEUP, REGISTER_TIMEOUT);
868
869                 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
870                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
871                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
872                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
873                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
874                 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
875         }
876 }
877
878 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
879                            struct rt2x00lib_conf *libconf,
880                            const unsigned int flags)
881 {
882         /* Always recalculate LNA gain before changing configuration */
883         rt73usb_config_lna_gain(rt2x00dev, libconf);
884
885         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
886                 rt73usb_config_channel(rt2x00dev, &libconf->rf,
887                                        libconf->conf->power_level);
888         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
889             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
890                 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
891         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
892                 rt73usb_config_retry_limit(rt2x00dev, libconf);
893         if (flags & IEEE80211_CONF_CHANGE_PS)
894                 rt73usb_config_ps(rt2x00dev, libconf);
895 }
896
897 /*
898  * Link tuning
899  */
900 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
901                                struct link_qual *qual)
902 {
903         u32 reg;
904
905         /*
906          * Update FCS error count from register.
907          */
908         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
909         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
910
911         /*
912          * Update False CCA count from register.
913          */
914         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
915         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
916 }
917
918 static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
919                                    struct link_qual *qual, u8 vgc_level)
920 {
921         if (qual->vgc_level != vgc_level) {
922                 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
923                 qual->vgc_level = vgc_level;
924                 qual->vgc_level_reg = vgc_level;
925         }
926 }
927
928 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
929                                 struct link_qual *qual)
930 {
931         rt73usb_set_vgc(rt2x00dev, qual, 0x20);
932 }
933
934 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
935                                struct link_qual *qual, const u32 count)
936 {
937         u8 up_bound;
938         u8 low_bound;
939
940         /*
941          * Determine r17 bounds.
942          */
943         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
944                 low_bound = 0x28;
945                 up_bound = 0x48;
946
947                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
948                         low_bound += 0x10;
949                         up_bound += 0x10;
950                 }
951         } else {
952                 if (qual->rssi > -82) {
953                         low_bound = 0x1c;
954                         up_bound = 0x40;
955                 } else if (qual->rssi > -84) {
956                         low_bound = 0x1c;
957                         up_bound = 0x20;
958                 } else {
959                         low_bound = 0x1c;
960                         up_bound = 0x1c;
961                 }
962
963                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
964                         low_bound += 0x14;
965                         up_bound += 0x10;
966                 }
967         }
968
969         /*
970          * If we are not associated, we should go straight to the
971          * dynamic CCA tuning.
972          */
973         if (!rt2x00dev->intf_associated)
974                 goto dynamic_cca_tune;
975
976         /*
977          * Special big-R17 for very short distance
978          */
979         if (qual->rssi > -35) {
980                 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
981                 return;
982         }
983
984         /*
985          * Special big-R17 for short distance
986          */
987         if (qual->rssi >= -58) {
988                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
989                 return;
990         }
991
992         /*
993          * Special big-R17 for middle-short distance
994          */
995         if (qual->rssi >= -66) {
996                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
997                 return;
998         }
999
1000         /*
1001          * Special mid-R17 for middle distance
1002          */
1003         if (qual->rssi >= -74) {
1004                 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1005                 return;
1006         }
1007
1008         /*
1009          * Special case: Change up_bound based on the rssi.
1010          * Lower up_bound when rssi is weaker then -74 dBm.
1011          */
1012         up_bound -= 2 * (-74 - qual->rssi);
1013         if (low_bound > up_bound)
1014                 up_bound = low_bound;
1015
1016         if (qual->vgc_level > up_bound) {
1017                 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
1018                 return;
1019         }
1020
1021 dynamic_cca_tune:
1022
1023         /*
1024          * r17 does not yet exceed upper limit, continue and base
1025          * the r17 tuning on the false CCA count.
1026          */
1027         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1028                 rt73usb_set_vgc(rt2x00dev, qual,
1029                                 min_t(u8, qual->vgc_level + 4, up_bound));
1030         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1031                 rt73usb_set_vgc(rt2x00dev, qual,
1032                                 max_t(u8, qual->vgc_level - 4, low_bound));
1033 }
1034
1035 /*
1036  * Firmware functions
1037  */
1038 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1039 {
1040         return FIRMWARE_RT2571;
1041 }
1042
1043 static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1044                                   const u8 *data, const size_t len)
1045 {
1046         u16 fw_crc;
1047         u16 crc;
1048
1049         /*
1050          * Only support 2kb firmware files.
1051          */
1052         if (len != 2048)
1053                 return FW_BAD_LENGTH;
1054
1055         /*
1056          * The last 2 bytes in the firmware array are the crc checksum itself,
1057          * this means that we should never pass those 2 bytes to the crc
1058          * algorithm.
1059          */
1060         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1061
1062         /*
1063          * Use the crc itu-t algorithm.
1064          */
1065         crc = crc_itu_t(0, data, len - 2);
1066         crc = crc_itu_t_byte(crc, 0);
1067         crc = crc_itu_t_byte(crc, 0);
1068
1069         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1070 }
1071
1072 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1073                                  const u8 *data, const size_t len)
1074 {
1075         unsigned int i;
1076         int status;
1077         u32 reg;
1078
1079         /*
1080          * Wait for stable hardware.
1081          */
1082         for (i = 0; i < 100; i++) {
1083                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1084                 if (reg)
1085                         break;
1086                 msleep(1);
1087         }
1088
1089         if (!reg) {
1090                 ERROR(rt2x00dev, "Unstable hardware.\n");
1091                 return -EBUSY;
1092         }
1093
1094         /*
1095          * Write firmware to device.
1096          */
1097         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1098                                             USB_VENDOR_REQUEST_OUT,
1099                                             FIRMWARE_IMAGE_BASE,
1100                                             data, len,
1101                                             REGISTER_TIMEOUT32(len));
1102
1103         /*
1104          * Send firmware request to device to load firmware,
1105          * we need to specify a long timeout time.
1106          */
1107         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1108                                              0, USB_MODE_FIRMWARE,
1109                                              REGISTER_TIMEOUT_FIRMWARE);
1110         if (status < 0) {
1111                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1112                 return status;
1113         }
1114
1115         return 0;
1116 }
1117
1118 /*
1119  * Initialization functions.
1120  */
1121 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1122 {
1123         u32 reg;
1124
1125         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1126         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1127         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1128         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1129         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1130
1131         rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1132         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1133         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1134         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1135         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1136         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1137         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1138         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1139         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1140         rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1141
1142         /*
1143          * CCK TXD BBP registers
1144          */
1145         rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1146         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1147         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1148         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1149         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1150         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1151         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1152         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1153         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1154         rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1155
1156         /*
1157          * OFDM TXD BBP registers
1158          */
1159         rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1160         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1161         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1162         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1163         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1164         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1165         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1166         rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1167
1168         rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1169         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1170         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1171         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1172         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1173         rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1174
1175         rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1176         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1177         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1178         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1179         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1180         rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1181
1182         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1183         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1184         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1185         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1186         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1187         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1188         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1189         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1190
1191         rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1192
1193         rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1194         rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1195         rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1196
1197         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1198
1199         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1200                 return -EBUSY;
1201
1202         rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1203
1204         /*
1205          * Invalidate all Shared Keys (SEC_CSR0),
1206          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1207          */
1208         rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1209         rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1210         rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1211
1212         reg = 0x000023b0;
1213         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1214             rt2x00_rf(&rt2x00dev->chip, RF2527))
1215                 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1216         rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1217
1218         rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1219         rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1220         rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1221
1222         rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1223         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1224         rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1225
1226         /*
1227          * Clear all beacons
1228          * For the Beacon base registers we only need to clear
1229          * the first byte since that byte contains the VALID and OWNER
1230          * bits which (when set to 0) will invalidate the entire beacon.
1231          */
1232         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1233         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1234         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1235         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1236
1237         /*
1238          * We must clear the error counters.
1239          * These registers are cleared on read,
1240          * so we may pass a useless variable to store the value.
1241          */
1242         rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1243         rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1244         rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1245
1246         /*
1247          * Reset MAC and BBP registers.
1248          */
1249         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1250         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1251         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1252         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1253
1254         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1255         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1256         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1257         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1258
1259         rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1260         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1261         rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1262
1263         return 0;
1264 }
1265
1266 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1267 {
1268         unsigned int i;
1269         u8 value;
1270
1271         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1272                 rt73usb_bbp_read(rt2x00dev, 0, &value);
1273                 if ((value != 0xff) && (value != 0x00))
1274                         return 0;
1275                 udelay(REGISTER_BUSY_DELAY);
1276         }
1277
1278         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1279         return -EACCES;
1280 }
1281
1282 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1283 {
1284         unsigned int i;
1285         u16 eeprom;
1286         u8 reg_id;
1287         u8 value;
1288
1289         if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1290                 return -EACCES;
1291
1292         rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1293         rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1294         rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1295         rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1296         rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1297         rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1298         rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1299         rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1300         rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1301         rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1302         rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1303         rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1304         rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1305         rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1306         rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1307         rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1308         rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1309         rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1310         rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1311         rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1312         rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1313         rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1314         rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1315         rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1316         rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1317
1318         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1319                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1320
1321                 if (eeprom != 0xffff && eeprom != 0x0000) {
1322                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1323                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1324                         rt73usb_bbp_write(rt2x00dev, reg_id, value);
1325                 }
1326         }
1327
1328         return 0;
1329 }
1330
1331 /*
1332  * Device state switch handlers.
1333  */
1334 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1335                               enum dev_state state)
1336 {
1337         u32 reg;
1338
1339         rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1340         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1341                            (state == STATE_RADIO_RX_OFF) ||
1342                            (state == STATE_RADIO_RX_OFF_LINK));
1343         rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1344 }
1345
1346 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1347 {
1348         /*
1349          * Initialize all registers.
1350          */
1351         if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1352                      rt73usb_init_bbp(rt2x00dev)))
1353                 return -EIO;
1354
1355         return 0;
1356 }
1357
1358 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1359 {
1360         rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1361
1362         /*
1363          * Disable synchronisation.
1364          */
1365         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1366
1367         rt2x00usb_disable_radio(rt2x00dev);
1368 }
1369
1370 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1371 {
1372         u32 reg;
1373         unsigned int i;
1374         char put_to_sleep;
1375
1376         put_to_sleep = (state != STATE_AWAKE);
1377
1378         rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1379         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1380         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1381         rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1382
1383         /*
1384          * Device is not guaranteed to be in the requested state yet.
1385          * We must wait until the register indicates that the
1386          * device has entered the correct state.
1387          */
1388         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1389                 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1390                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1391                 if (state == !put_to_sleep)
1392                         return 0;
1393                 msleep(10);
1394         }
1395
1396         return -EBUSY;
1397 }
1398
1399 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1400                                     enum dev_state state)
1401 {
1402         int retval = 0;
1403
1404         switch (state) {
1405         case STATE_RADIO_ON:
1406                 retval = rt73usb_enable_radio(rt2x00dev);
1407                 break;
1408         case STATE_RADIO_OFF:
1409                 rt73usb_disable_radio(rt2x00dev);
1410                 break;
1411         case STATE_RADIO_RX_ON:
1412         case STATE_RADIO_RX_ON_LINK:
1413         case STATE_RADIO_RX_OFF:
1414         case STATE_RADIO_RX_OFF_LINK:
1415                 rt73usb_toggle_rx(rt2x00dev, state);
1416                 break;
1417         case STATE_RADIO_IRQ_ON:
1418         case STATE_RADIO_IRQ_OFF:
1419                 /* No support, but no error either */
1420                 break;
1421         case STATE_DEEP_SLEEP:
1422         case STATE_SLEEP:
1423         case STATE_STANDBY:
1424         case STATE_AWAKE:
1425                 retval = rt73usb_set_state(rt2x00dev, state);
1426                 break;
1427         default:
1428                 retval = -ENOTSUPP;
1429                 break;
1430         }
1431
1432         if (unlikely(retval))
1433                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1434                       state, retval);
1435
1436         return retval;
1437 }
1438
1439 /*
1440  * TX descriptor initialization
1441  */
1442 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1443                                   struct sk_buff *skb,
1444                                   struct txentry_desc *txdesc)
1445 {
1446         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1447         __le32 *txd = skbdesc->desc;
1448         u32 word;
1449
1450         /*
1451          * Start writing the descriptor words.
1452          */
1453         rt2x00_desc_read(txd, 1, &word);
1454         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1455         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1456         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1457         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1458         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1459         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1460                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1461         rt2x00_desc_write(txd, 1, word);
1462
1463         rt2x00_desc_read(txd, 2, &word);
1464         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1465         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1466         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1467         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1468         rt2x00_desc_write(txd, 2, word);
1469
1470         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1471                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1472                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1473         }
1474
1475         rt2x00_desc_read(txd, 5, &word);
1476         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1477                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1478         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1479         rt2x00_desc_write(txd, 5, word);
1480
1481         rt2x00_desc_read(txd, 0, &word);
1482         rt2x00_set_field32(&word, TXD_W0_BURST,
1483                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1484         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1485         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1486                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1487         rt2x00_set_field32(&word, TXD_W0_ACK,
1488                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1489         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1490                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1491         rt2x00_set_field32(&word, TXD_W0_OFDM,
1492                            (txdesc->rate_mode == RATE_MODE_OFDM));
1493         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1494         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1495                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1496         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1497                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1498         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1499                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1500         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1501         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1502         rt2x00_set_field32(&word, TXD_W0_BURST2,
1503                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1504         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1505         rt2x00_desc_write(txd, 0, word);
1506 }
1507
1508 /*
1509  * TX data initialization
1510  */
1511 static void rt73usb_write_beacon(struct queue_entry *entry)
1512 {
1513         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1514         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1515         unsigned int beacon_base;
1516         u32 reg;
1517
1518         /*
1519          * Add the descriptor in front of the skb.
1520          */
1521         skb_push(entry->skb, entry->queue->desc_size);
1522         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1523         skbdesc->desc = entry->skb->data;
1524
1525         /*
1526          * Disable beaconing while we are reloading the beacon data,
1527          * otherwise we might be sending out invalid data.
1528          */
1529         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1530         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1531         rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1532
1533         /*
1534          * Write entire beacon with descriptor to register.
1535          */
1536         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1537         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1538                                             USB_VENDOR_REQUEST_OUT, beacon_base,
1539                                             entry->skb->data, entry->skb->len,
1540                                             REGISTER_TIMEOUT32(entry->skb->len));
1541
1542         /*
1543          * Clean up the beacon skb.
1544          */
1545         dev_kfree_skb(entry->skb);
1546         entry->skb = NULL;
1547 }
1548
1549 static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1550 {
1551         int length;
1552
1553         /*
1554          * The length _must_ be a multiple of 4,
1555          * but it must _not_ be a multiple of the USB packet size.
1556          */
1557         length = roundup(entry->skb->len, 4);
1558         length += (4 * !(length % entry->queue->usb_maxpacket));
1559
1560         return length;
1561 }
1562
1563 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1564                                   const enum data_queue_qid queue)
1565 {
1566         u32 reg;
1567
1568         if (queue != QID_BEACON) {
1569                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1570                 return;
1571         }
1572
1573         /*
1574          * For Wi-Fi faily generated beacons between participating stations.
1575          * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1576          */
1577         rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1578
1579         rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1580         if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1581                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1582                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1583                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1584                 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1585         }
1586 }
1587
1588 /*
1589  * RX control handlers
1590  */
1591 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1592 {
1593         u8 offset = rt2x00dev->lna_gain;
1594         u8 lna;
1595
1596         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1597         switch (lna) {
1598         case 3:
1599                 offset += 90;
1600                 break;
1601         case 2:
1602                 offset += 74;
1603                 break;
1604         case 1:
1605                 offset += 64;
1606                 break;
1607         default:
1608                 return 0;
1609         }
1610
1611         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1612                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1613                         if (lna == 3 || lna == 2)
1614                                 offset += 10;
1615                 } else {
1616                         if (lna == 3)
1617                                 offset += 6;
1618                         else if (lna == 2)
1619                                 offset += 8;
1620                 }
1621         }
1622
1623         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1624 }
1625
1626 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1627                                 struct rxdone_entry_desc *rxdesc)
1628 {
1629         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1630         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1631         __le32 *rxd = (__le32 *)entry->skb->data;
1632         u32 word0;
1633         u32 word1;
1634
1635         /*
1636          * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1637          * frame data in rt2x00usb.
1638          */
1639         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
1640         rxd = (__le32 *)skbdesc->desc;
1641
1642         /*
1643          * It is now safe to read the descriptor on all architectures.
1644          */
1645         rt2x00_desc_read(rxd, 0, &word0);
1646         rt2x00_desc_read(rxd, 1, &word1);
1647
1648         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1649                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1650
1651         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1652                 rxdesc->cipher =
1653                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1654                 rxdesc->cipher_status =
1655                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1656         }
1657
1658         if (rxdesc->cipher != CIPHER_NONE) {
1659                 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1660                 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
1661                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1662
1663                 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1664                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1665
1666                 /*
1667                  * Hardware has stripped IV/EIV data from 802.11 frame during
1668                  * decryption. It has provided the data seperately but rt2x00lib
1669                  * should decide if it should be reinserted.
1670                  */
1671                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1672
1673                 /*
1674                  * FIXME: Legacy driver indicates that the frame does
1675                  * contain the Michael Mic. Unfortunately, in rt2x00
1676                  * the MIC seems to be missing completely...
1677                  */
1678                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1679
1680                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1681                         rxdesc->flags |= RX_FLAG_DECRYPTED;
1682                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1683                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1684         }
1685
1686         /*
1687          * Obtain the status about this packet.
1688          * When frame was received with an OFDM bitrate,
1689          * the signal is the PLCP value. If it was received with
1690          * a CCK bitrate the signal is the rate in 100kbit/s.
1691          */
1692         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1693         rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
1694         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1695
1696         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1697                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1698         else
1699                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1700         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1701                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1702
1703         /*
1704          * Set skb pointers, and update frame information.
1705          */
1706         skb_pull(entry->skb, entry->queue->desc_size);
1707         skb_trim(entry->skb, rxdesc->size);
1708 }
1709
1710 /*
1711  * Device probe functions.
1712  */
1713 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1714 {
1715         u16 word;
1716         u8 *mac;
1717         s8 value;
1718
1719         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1720
1721         /*
1722          * Start validation of the data that has been read.
1723          */
1724         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1725         if (!is_valid_ether_addr(mac)) {
1726                 random_ether_addr(mac);
1727                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1728         }
1729
1730         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1731         if (word == 0xffff) {
1732                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1733                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1734                                    ANTENNA_B);
1735                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1736                                    ANTENNA_B);
1737                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1738                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1739                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1740                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1741                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1742                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1743         }
1744
1745         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1746         if (word == 0xffff) {
1747                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1748                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1749                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1750         }
1751
1752         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1753         if (word == 0xffff) {
1754                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1755                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1756                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1757                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1758                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1759                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1760                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1761                 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1762                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1763                                    LED_MODE_DEFAULT);
1764                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1765                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1766         }
1767
1768         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1769         if (word == 0xffff) {
1770                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1771                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1772                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1773                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1774         }
1775
1776         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1777         if (word == 0xffff) {
1778                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1779                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1780                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1781                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1782         } else {
1783                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1784                 if (value < -10 || value > 10)
1785                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1786                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1787                 if (value < -10 || value > 10)
1788                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1789                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1790         }
1791
1792         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1793         if (word == 0xffff) {
1794                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1795                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1796                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1797                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1798         } else {
1799                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1800                 if (value < -10 || value > 10)
1801                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1802                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1803                 if (value < -10 || value > 10)
1804                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1805                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1806         }
1807
1808         return 0;
1809 }
1810
1811 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1812 {
1813         u32 reg;
1814         u16 value;
1815         u16 eeprom;
1816
1817         /*
1818          * Read EEPROM word for configuration.
1819          */
1820         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1821
1822         /*
1823          * Identify RF chipset.
1824          */
1825         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1826         rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1827         rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1828
1829         if (!rt2x00_check_rev(&rt2x00dev->chip, 0x000ffff0, 0x25730) ||
1830             rt2x00_check_rev(&rt2x00dev->chip, 0x0000000f, 0)) {
1831                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1832                 return -ENODEV;
1833         }
1834
1835         if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1836             !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1837             !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1838             !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1839                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1840                 return -ENODEV;
1841         }
1842
1843         /*
1844          * Identify default antenna configuration.
1845          */
1846         rt2x00dev->default_ant.tx =
1847             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1848         rt2x00dev->default_ant.rx =
1849             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1850
1851         /*
1852          * Read the Frame type.
1853          */
1854         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1855                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1856
1857         /*
1858          * Detect if this device has an hardware controlled radio.
1859          */
1860         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1861                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1862
1863         /*
1864          * Read frequency offset.
1865          */
1866         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1867         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1868
1869         /*
1870          * Read external LNA informations.
1871          */
1872         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1873
1874         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1875                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1876                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1877         }
1878
1879         /*
1880          * Store led settings, for correct led behaviour.
1881          */
1882 #ifdef CONFIG_RT2X00_LIB_LEDS
1883         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1884
1885         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1886         rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1887         if (value == LED_MODE_SIGNAL_STRENGTH)
1888                 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1889                                  LED_TYPE_QUALITY);
1890
1891         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1892         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1893                            rt2x00_get_field16(eeprom,
1894                                               EEPROM_LED_POLARITY_GPIO_0));
1895         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1896                            rt2x00_get_field16(eeprom,
1897                                               EEPROM_LED_POLARITY_GPIO_1));
1898         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1899                            rt2x00_get_field16(eeprom,
1900                                               EEPROM_LED_POLARITY_GPIO_2));
1901         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1902                            rt2x00_get_field16(eeprom,
1903                                               EEPROM_LED_POLARITY_GPIO_3));
1904         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1905                            rt2x00_get_field16(eeprom,
1906                                               EEPROM_LED_POLARITY_GPIO_4));
1907         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1908                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1909         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1910                            rt2x00_get_field16(eeprom,
1911                                               EEPROM_LED_POLARITY_RDY_G));
1912         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1913                            rt2x00_get_field16(eeprom,
1914                                               EEPROM_LED_POLARITY_RDY_A));
1915 #endif /* CONFIG_RT2X00_LIB_LEDS */
1916
1917         return 0;
1918 }
1919
1920 /*
1921  * RF value list for RF2528
1922  * Supports: 2.4 GHz
1923  */
1924 static const struct rf_channel rf_vals_bg_2528[] = {
1925         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1926         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1927         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1928         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1929         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1930         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1931         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1932         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1933         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1934         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1935         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1936         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1937         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1938         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1939 };
1940
1941 /*
1942  * RF value list for RF5226
1943  * Supports: 2.4 GHz & 5.2 GHz
1944  */
1945 static const struct rf_channel rf_vals_5226[] = {
1946         { 1,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1947         { 2,  0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1948         { 3,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1949         { 4,  0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1950         { 5,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1951         { 6,  0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1952         { 7,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1953         { 8,  0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1954         { 9,  0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1955         { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1956         { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1957         { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1958         { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1959         { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1960
1961         /* 802.11 UNI / HyperLan 2 */
1962         { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1963         { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1964         { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1965         { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1966         { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1967         { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1968         { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1969         { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1970
1971         /* 802.11 HyperLan 2 */
1972         { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1973         { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1974         { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1975         { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1976         { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1977         { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1978         { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1979         { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1980         { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1981         { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1982
1983         /* 802.11 UNII */
1984         { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1985         { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1986         { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1987         { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1988         { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1989         { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1990
1991         /* MMAC(Japan)J52 ch 34,38,42,46 */
1992         { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1993         { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1994         { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1995         { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1996 };
1997
1998 /*
1999  * RF value list for RF5225 & RF2527
2000  * Supports: 2.4 GHz & 5.2 GHz
2001  */
2002 static const struct rf_channel rf_vals_5225_2527[] = {
2003         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2004         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2005         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2006         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2007         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2008         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2009         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2010         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2011         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2012         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2013         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2014         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2015         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2016         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2017
2018         /* 802.11 UNI / HyperLan 2 */
2019         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2020         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2021         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2022         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2023         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2024         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2025         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2026         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2027
2028         /* 802.11 HyperLan 2 */
2029         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2030         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2031         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2032         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2033         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2034         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2035         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2036         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2037         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2038         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2039
2040         /* 802.11 UNII */
2041         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2042         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2043         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2044         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2045         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2046         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2047
2048         /* MMAC(Japan)J52 ch 34,38,42,46 */
2049         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2050         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2051         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2052         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2053 };
2054
2055
2056 static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2057 {
2058         struct hw_mode_spec *spec = &rt2x00dev->spec;
2059         struct channel_info *info;
2060         char *tx_power;
2061         unsigned int i;
2062
2063         /*
2064          * Initialize all hw fields.
2065          */
2066         rt2x00dev->hw->flags =
2067             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2068             IEEE80211_HW_SIGNAL_DBM |
2069             IEEE80211_HW_SUPPORTS_PS |
2070             IEEE80211_HW_PS_NULLFUNC_STACK;
2071         rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
2072
2073         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2074         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2075                                 rt2x00_eeprom_addr(rt2x00dev,
2076                                                    EEPROM_MAC_ADDR_0));
2077
2078         /*
2079          * Initialize hw_mode information.
2080          */
2081         spec->supported_bands = SUPPORT_BAND_2GHZ;
2082         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2083
2084         if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2085                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2086                 spec->channels = rf_vals_bg_2528;
2087         } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
2088                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2089                 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2090                 spec->channels = rf_vals_5226;
2091         } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2092                 spec->num_channels = 14;
2093                 spec->channels = rf_vals_5225_2527;
2094         } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
2095                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2096                 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2097                 spec->channels = rf_vals_5225_2527;
2098         }
2099
2100         /*
2101          * Create channel information array
2102          */
2103         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2104         if (!info)
2105                 return -ENOMEM;
2106
2107         spec->channels_info = info;
2108
2109         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2110         for (i = 0; i < 14; i++)
2111                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2112
2113         if (spec->num_channels > 14) {
2114                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2115                 for (i = 14; i < spec->num_channels; i++)
2116                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2117         }
2118
2119         return 0;
2120 }
2121
2122 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2123 {
2124         int retval;
2125
2126         /*
2127          * Allocate eeprom data.
2128          */
2129         retval = rt73usb_validate_eeprom(rt2x00dev);
2130         if (retval)
2131                 return retval;
2132
2133         retval = rt73usb_init_eeprom(rt2x00dev);
2134         if (retval)
2135                 return retval;
2136
2137         /*
2138          * Initialize hw specifications.
2139          */
2140         retval = rt73usb_probe_hw_mode(rt2x00dev);
2141         if (retval)
2142                 return retval;
2143
2144         /*
2145          * This device has multiple filters for control frames,
2146          * but has no a separate filter for PS Poll frames.
2147          */
2148         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2149
2150         /*
2151          * This device requires firmware.
2152          */
2153         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2154         if (!modparam_nohwcrypt)
2155                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2156
2157         /*
2158          * Set the rssi offset.
2159          */
2160         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2161
2162         return 0;
2163 }
2164
2165 /*
2166  * IEEE80211 stack callback functions.
2167  */
2168 static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2169                            const struct ieee80211_tx_queue_params *params)
2170 {
2171         struct rt2x00_dev *rt2x00dev = hw->priv;
2172         struct data_queue *queue;
2173         struct rt2x00_field32 field;
2174         int retval;
2175         u32 reg;
2176         u32 offset;
2177
2178         /*
2179          * First pass the configuration through rt2x00lib, that will
2180          * update the queue settings and validate the input. After that
2181          * we are free to update the registers based on the value
2182          * in the queue parameter.
2183          */
2184         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2185         if (retval)
2186                 return retval;
2187
2188         /*
2189          * We only need to perform additional register initialization
2190          * for WMM queues/
2191          */
2192         if (queue_idx >= 4)
2193                 return 0;
2194
2195         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2196
2197         /* Update WMM TXOP register */
2198         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2199         field.bit_offset = (queue_idx & 1) * 16;
2200         field.bit_mask = 0xffff << field.bit_offset;
2201
2202         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2203         rt2x00_set_field32(&reg, field, queue->txop);
2204         rt2x00usb_register_write(rt2x00dev, offset, reg);
2205
2206         /* Update WMM registers */
2207         field.bit_offset = queue_idx * 4;
2208         field.bit_mask = 0xf << field.bit_offset;
2209
2210         rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2211         rt2x00_set_field32(&reg, field, queue->aifs);
2212         rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2213
2214         rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2215         rt2x00_set_field32(&reg, field, queue->cw_min);
2216         rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2217
2218         rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2219         rt2x00_set_field32(&reg, field, queue->cw_max);
2220         rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2221
2222         return 0;
2223 }
2224
2225 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2226 {
2227         struct rt2x00_dev *rt2x00dev = hw->priv;
2228         u64 tsf;
2229         u32 reg;
2230
2231         rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2232         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2233         rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2234         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2235
2236         return tsf;
2237 }
2238
2239 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2240         .tx                     = rt2x00mac_tx,
2241         .start                  = rt2x00mac_start,
2242         .stop                   = rt2x00mac_stop,
2243         .add_interface          = rt2x00mac_add_interface,
2244         .remove_interface       = rt2x00mac_remove_interface,
2245         .config                 = rt2x00mac_config,
2246         .configure_filter       = rt2x00mac_configure_filter,
2247         .set_tim                = rt2x00mac_set_tim,
2248         .set_key                = rt2x00mac_set_key,
2249         .get_stats              = rt2x00mac_get_stats,
2250         .bss_info_changed       = rt2x00mac_bss_info_changed,
2251         .conf_tx                = rt73usb_conf_tx,
2252         .get_tx_stats           = rt2x00mac_get_tx_stats,
2253         .get_tsf                = rt73usb_get_tsf,
2254         .rfkill_poll            = rt2x00mac_rfkill_poll,
2255 };
2256
2257 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2258         .probe_hw               = rt73usb_probe_hw,
2259         .get_firmware_name      = rt73usb_get_firmware_name,
2260         .check_firmware         = rt73usb_check_firmware,
2261         .load_firmware          = rt73usb_load_firmware,
2262         .initialize             = rt2x00usb_initialize,
2263         .uninitialize           = rt2x00usb_uninitialize,
2264         .clear_entry            = rt2x00usb_clear_entry,
2265         .set_device_state       = rt73usb_set_device_state,
2266         .rfkill_poll            = rt73usb_rfkill_poll,
2267         .link_stats             = rt73usb_link_stats,
2268         .reset_tuner            = rt73usb_reset_tuner,
2269         .link_tuner             = rt73usb_link_tuner,
2270         .write_tx_desc          = rt73usb_write_tx_desc,
2271         .write_tx_data          = rt2x00usb_write_tx_data,
2272         .write_beacon           = rt73usb_write_beacon,
2273         .get_tx_data_len        = rt73usb_get_tx_data_len,
2274         .kick_tx_queue          = rt73usb_kick_tx_queue,
2275         .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2276         .fill_rxdone            = rt73usb_fill_rxdone,
2277         .config_shared_key      = rt73usb_config_shared_key,
2278         .config_pairwise_key    = rt73usb_config_pairwise_key,
2279         .config_filter          = rt73usb_config_filter,
2280         .config_intf            = rt73usb_config_intf,
2281         .config_erp             = rt73usb_config_erp,
2282         .config_ant             = rt73usb_config_ant,
2283         .config                 = rt73usb_config,
2284 };
2285
2286 static const struct data_queue_desc rt73usb_queue_rx = {
2287         .entry_num              = RX_ENTRIES,
2288         .data_size              = DATA_FRAME_SIZE,
2289         .desc_size              = RXD_DESC_SIZE,
2290         .priv_size              = sizeof(struct queue_entry_priv_usb),
2291 };
2292
2293 static const struct data_queue_desc rt73usb_queue_tx = {
2294         .entry_num              = TX_ENTRIES,
2295         .data_size              = DATA_FRAME_SIZE,
2296         .desc_size              = TXD_DESC_SIZE,
2297         .priv_size              = sizeof(struct queue_entry_priv_usb),
2298 };
2299
2300 static const struct data_queue_desc rt73usb_queue_bcn = {
2301         .entry_num              = 4 * BEACON_ENTRIES,
2302         .data_size              = MGMT_FRAME_SIZE,
2303         .desc_size              = TXINFO_SIZE,
2304         .priv_size              = sizeof(struct queue_entry_priv_usb),
2305 };
2306
2307 static const struct rt2x00_ops rt73usb_ops = {
2308         .name           = KBUILD_MODNAME,
2309         .max_sta_intf   = 1,
2310         .max_ap_intf    = 4,
2311         .eeprom_size    = EEPROM_SIZE,
2312         .rf_size        = RF_SIZE,
2313         .tx_queues      = NUM_TX_QUEUES,
2314         .rx             = &rt73usb_queue_rx,
2315         .tx             = &rt73usb_queue_tx,
2316         .bcn            = &rt73usb_queue_bcn,
2317         .lib            = &rt73usb_rt2x00_ops,
2318         .hw             = &rt73usb_mac80211_ops,
2319 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2320         .debugfs        = &rt73usb_rt2x00debug,
2321 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2322 };
2323
2324 /*
2325  * rt73usb module information.
2326  */
2327 static struct usb_device_id rt73usb_device_table[] = {
2328         /* AboCom */
2329         { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2330         { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
2331         { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2332         { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2333         { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2334         /* AL */
2335         { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
2336         /* Amigo */
2337         { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2338         { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2339         /* AMIT  */
2340         { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
2341         /* Askey */
2342         { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2343         /* ASUS */
2344         { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2345         { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2346         /* Belkin */
2347         { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2348         { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2349         { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2350         { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2351         /* Billionton */
2352         { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2353         { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
2354         /* Buffalo */
2355         { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
2356         { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2357         { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2358         { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
2359         /* CNet */
2360         { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2361         { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2362         /* Conceptronic */
2363         { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2364         /* Corega */
2365         { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2366         /* D-Link */
2367         { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2368         { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2369         { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
2370         { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2371         /* Edimax */
2372         { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2373         { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2374         /* EnGenius */
2375         { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
2376         /* Gemtek */
2377         { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2378         /* Gigabyte */
2379         { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2380         { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2381         /* Huawei-3Com */
2382         { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2383         /* Hercules */
2384         { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2385         { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2386         /* Linksys */
2387         { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2388         { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2389         { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
2390         /* MSI */
2391         { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2392         { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2393         { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2394         { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2395         /* Ralink */
2396         { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
2397         { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2398         { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2399         /* Qcom */
2400         { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2401         { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2402         { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2403         /* Samsung */
2404         { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
2405         /* Senao */
2406         { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2407         /* Sitecom */
2408         { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2409         { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2410         { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
2411         { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2412         { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2413         /* Surecom */
2414         { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2415         /* Tilgin */
2416         { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
2417         /* Philips */
2418         { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
2419         /* Planex */
2420         { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2421         { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2422         /* Zcom */
2423         { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
2424         /* ZyXEL */
2425         { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
2426         { 0, }
2427 };
2428
2429 MODULE_AUTHOR(DRV_PROJECT);
2430 MODULE_VERSION(DRV_VERSION);
2431 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2432 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2433 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2434 MODULE_FIRMWARE(FIRMWARE_RT2571);
2435 MODULE_LICENSE("GPL");
2436
2437 static struct usb_driver rt73usb_driver = {
2438         .name           = KBUILD_MODNAME,
2439         .id_table       = rt73usb_device_table,
2440         .probe          = rt2x00usb_probe,
2441         .disconnect     = rt2x00usb_disconnect,
2442         .suspend        = rt2x00usb_suspend,
2443         .resume         = rt2x00usb_resume,
2444 };
2445
2446 static int __init rt73usb_init(void)
2447 {
2448         return usb_register(&rt73usb_driver);
2449 }
2450
2451 static void __exit rt73usb_exit(void)
2452 {
2453         usb_deregister(&rt73usb_driver);
2454 }
2455
2456 module_init(rt73usb_init);
2457 module_exit(rt73usb_exit);