Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt61pci.c
1 /*
2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt61pci
23         Abstract: rt61pci device specific routines.
24         Supported chipsets: RT2561, RT2561s, RT2661.
25  */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/eeprom_93cx6.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00pci.h"
38 #include "rt61pci.h"
39
40 /*
41  * Register access.
42  * BBP and RF register require indirect register access,
43  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
44  * These indirect registers work with busy bits,
45  * and we will try maximal REGISTER_BUSY_COUNT times to access
46  * the register while taking a REGISTER_BUSY_DELAY us delay
47  * between each attampt. When the busy bit is still set at that time,
48  * the access attempt is considered to have failed,
49  * and we will print an error.
50  */
51 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
52 {
53         u32 reg;
54         unsigned int i;
55
56         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
57                 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
58                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
59                         break;
60                 udelay(REGISTER_BUSY_DELAY);
61         }
62
63         return reg;
64 }
65
66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
67                               const unsigned int word, const u8 value)
68 {
69         u32 reg;
70
71         /*
72          * Wait until the BBP becomes ready.
73          */
74         reg = rt61pci_bbp_check(rt2x00dev);
75         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
76                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
77                 return;
78         }
79
80         /*
81          * Write the data into the BBP.
82          */
83         reg = 0;
84         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
85         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
86         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
87         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
88
89         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
90 }
91
92 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
93                              const unsigned int word, u8 *value)
94 {
95         u32 reg;
96
97         /*
98          * Wait until the BBP becomes ready.
99          */
100         reg = rt61pci_bbp_check(rt2x00dev);
101         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
102                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
103                 return;
104         }
105
106         /*
107          * Write the request into the BBP.
108          */
109         reg = 0;
110         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
111         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
112         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
113
114         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
115
116         /*
117          * Wait until the BBP becomes ready.
118          */
119         reg = rt61pci_bbp_check(rt2x00dev);
120         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
121                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
122                 *value = 0xff;
123                 return;
124         }
125
126         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
127 }
128
129 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
130                              const unsigned int word, const u32 value)
131 {
132         u32 reg;
133         unsigned int i;
134
135         if (!word)
136                 return;
137
138         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
139                 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
140                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
141                         goto rf_write;
142                 udelay(REGISTER_BUSY_DELAY);
143         }
144
145         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
146         return;
147
148 rf_write:
149         reg = 0;
150         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
151         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
152         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
153         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
154
155         rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
156         rt2x00_rf_write(rt2x00dev, word, value);
157 }
158
159 #ifdef CONFIG_RT61PCI_LEDS
160 /*
161  * This function is only called from rt61pci_led_brightness()
162  * make gcc happy by placing this function inside the
163  * same ifdef statement as the caller.
164  */
165 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
166                                 const u8 command, const u8 token,
167                                 const u8 arg0, const u8 arg1)
168 {
169         u32 reg;
170
171         rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
172
173         if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
174                 ERROR(rt2x00dev, "mcu request error. "
175                       "Request 0x%02x failed for token 0x%02x.\n",
176                       command, token);
177                 return;
178         }
179
180         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
181         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
182         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
183         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
184         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
185
186         rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
187         rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
188         rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
189         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
190 }
191 #endif /* CONFIG_RT61PCI_LEDS */
192
193 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
194 {
195         struct rt2x00_dev *rt2x00dev = eeprom->data;
196         u32 reg;
197
198         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
199
200         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
201         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
202         eeprom->reg_data_clock =
203             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
204         eeprom->reg_chip_select =
205             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
206 }
207
208 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
209 {
210         struct rt2x00_dev *rt2x00dev = eeprom->data;
211         u32 reg = 0;
212
213         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
214         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
215         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
216                            !!eeprom->reg_data_clock);
217         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
218                            !!eeprom->reg_chip_select);
219
220         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
221 }
222
223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
224 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
225
226 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
227                              const unsigned int word, u32 *data)
228 {
229         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
230 }
231
232 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
233                               const unsigned int word, u32 data)
234 {
235         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
236 }
237
238 static const struct rt2x00debug rt61pci_rt2x00debug = {
239         .owner  = THIS_MODULE,
240         .csr    = {
241                 .read           = rt61pci_read_csr,
242                 .write          = rt61pci_write_csr,
243                 .word_size      = sizeof(u32),
244                 .word_count     = CSR_REG_SIZE / sizeof(u32),
245         },
246         .eeprom = {
247                 .read           = rt2x00_eeprom_read,
248                 .write          = rt2x00_eeprom_write,
249                 .word_size      = sizeof(u16),
250                 .word_count     = EEPROM_SIZE / sizeof(u16),
251         },
252         .bbp    = {
253                 .read           = rt61pci_bbp_read,
254                 .write          = rt61pci_bbp_write,
255                 .word_size      = sizeof(u8),
256                 .word_count     = BBP_SIZE / sizeof(u8),
257         },
258         .rf     = {
259                 .read           = rt2x00_rf_read,
260                 .write          = rt61pci_rf_write,
261                 .word_size      = sizeof(u32),
262                 .word_count     = RF_SIZE / sizeof(u32),
263         },
264 };
265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267 #ifdef CONFIG_RT61PCI_RFKILL
268 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269 {
270         u32 reg;
271
272         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
273         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
274 }
275 #else
276 #define rt61pci_rfkill_poll     NULL
277 #endif /* CONFIG_RT61PCI_RFKILL */
278
279 #ifdef CONFIG_RT61PCI_LEDS
280 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
281                                    enum led_brightness brightness)
282 {
283         struct rt2x00_led *led =
284             container_of(led_cdev, struct rt2x00_led, led_dev);
285         unsigned int enabled = brightness != LED_OFF;
286         unsigned int a_mode =
287             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
288         unsigned int bg_mode =
289             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
290
291         if (led->type == LED_TYPE_RADIO) {
292                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
293                                    MCU_LEDCS_RADIO_STATUS, enabled);
294
295                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
296                                     (led->rt2x00dev->led_mcu_reg & 0xff),
297                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
298         } else if (led->type == LED_TYPE_ASSOC) {
299                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
300                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
301                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
302                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
303
304                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
305                                     (led->rt2x00dev->led_mcu_reg & 0xff),
306                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
307         } else if (led->type == LED_TYPE_QUALITY) {
308                 /*
309                  * The brightness is divided into 6 levels (0 - 5),
310                  * this means we need to convert the brightness
311                  * argument into the matching level within that range.
312                  */
313                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
314                                     brightness / (LED_FULL / 6), 0);
315         }
316 }
317
318 static int rt61pci_blink_set(struct led_classdev *led_cdev,
319                              unsigned long *delay_on,
320                              unsigned long *delay_off)
321 {
322         struct rt2x00_led *led =
323             container_of(led_cdev, struct rt2x00_led, led_dev);
324         u32 reg;
325
326         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
327         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
328         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
329         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
330
331         return 0;
332 }
333 #endif /* CONFIG_RT61PCI_LEDS */
334
335 /*
336  * Configuration handlers.
337  */
338 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
339                                   const unsigned int filter_flags)
340 {
341         u32 reg;
342
343         /*
344          * Start configuration steps.
345          * Note that the version error will always be dropped
346          * and broadcast frames will always be accepted since
347          * there is no filter for it at this time.
348          */
349         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
350         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
351                            !(filter_flags & FIF_FCSFAIL));
352         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
353                            !(filter_flags & FIF_PLCPFAIL));
354         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
355                            !(filter_flags & FIF_CONTROL));
356         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
357                            !(filter_flags & FIF_PROMISC_IN_BSS));
358         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
359                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
360                            !rt2x00dev->intf_ap_count);
361         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
362         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
363                            !(filter_flags & FIF_ALLMULTI));
364         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
365         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
366                            !(filter_flags & FIF_CONTROL));
367         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
368 }
369
370 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
371                                 struct rt2x00_intf *intf,
372                                 struct rt2x00intf_conf *conf,
373                                 const unsigned int flags)
374 {
375         unsigned int beacon_base;
376         u32 reg;
377
378         if (flags & CONFIG_UPDATE_TYPE) {
379                 /*
380                  * Clear current synchronisation setup.
381                  * For the Beacon base registers we only need to clear
382                  * the first byte since that byte contains the VALID and OWNER
383                  * bits which (when set to 0) will invalidate the entire beacon.
384                  */
385                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
386                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
387
388                 /*
389                  * Enable synchronisation.
390                  */
391                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
392                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
393                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
394                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
395                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
396         }
397
398         if (flags & CONFIG_UPDATE_MAC) {
399                 reg = le32_to_cpu(conf->mac[1]);
400                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
401                 conf->mac[1] = cpu_to_le32(reg);
402
403                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
404                                               conf->mac, sizeof(conf->mac));
405         }
406
407         if (flags & CONFIG_UPDATE_BSSID) {
408                 reg = le32_to_cpu(conf->bssid[1]);
409                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
410                 conf->bssid[1] = cpu_to_le32(reg);
411
412                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
413                                               conf->bssid, sizeof(conf->bssid));
414         }
415 }
416
417 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
418                                struct rt2x00lib_erp *erp)
419 {
420         u32 reg;
421
422         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
423         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
424         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
425
426         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
427         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
428                            !!erp->short_preamble);
429         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
430 }
431
432 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
433                                    const int basic_rate_mask)
434 {
435         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
436 }
437
438 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
439                                    struct rf_channel *rf, const int txpower)
440 {
441         u8 r3;
442         u8 r94;
443         u8 smart;
444
445         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
446         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
447
448         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
449                   rt2x00_rf(&rt2x00dev->chip, RF2527));
450
451         rt61pci_bbp_read(rt2x00dev, 3, &r3);
452         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
453         rt61pci_bbp_write(rt2x00dev, 3, r3);
454
455         r94 = 6;
456         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
457                 r94 += txpower - MAX_TXPOWER;
458         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
459                 r94 += txpower;
460         rt61pci_bbp_write(rt2x00dev, 94, r94);
461
462         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
463         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
464         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
465         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
466
467         udelay(200);
468
469         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
470         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
471         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
472         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
473
474         udelay(200);
475
476         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
477         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
478         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
479         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
480
481         msleep(1);
482 }
483
484 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
485                                    const int txpower)
486 {
487         struct rf_channel rf;
488
489         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
490         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
491         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
492         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
493
494         rt61pci_config_channel(rt2x00dev, &rf, txpower);
495 }
496
497 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
498                                       struct antenna_setup *ant)
499 {
500         u8 r3;
501         u8 r4;
502         u8 r77;
503
504         rt61pci_bbp_read(rt2x00dev, 3, &r3);
505         rt61pci_bbp_read(rt2x00dev, 4, &r4);
506         rt61pci_bbp_read(rt2x00dev, 77, &r77);
507
508         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
509                           rt2x00_rf(&rt2x00dev->chip, RF5325));
510
511         /*
512          * Configure the RX antenna.
513          */
514         switch (ant->rx) {
515         case ANTENNA_HW_DIVERSITY:
516                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
517                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
518                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
519                 break;
520         case ANTENNA_A:
521                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
522                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
523                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
524                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
525                 else
526                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
527                 break;
528         case ANTENNA_B:
529         default:
530                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
531                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
532                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
533                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
534                 else
535                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
536                 break;
537         }
538
539         rt61pci_bbp_write(rt2x00dev, 77, r77);
540         rt61pci_bbp_write(rt2x00dev, 3, r3);
541         rt61pci_bbp_write(rt2x00dev, 4, r4);
542 }
543
544 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
545                                       struct antenna_setup *ant)
546 {
547         u8 r3;
548         u8 r4;
549         u8 r77;
550
551         rt61pci_bbp_read(rt2x00dev, 3, &r3);
552         rt61pci_bbp_read(rt2x00dev, 4, &r4);
553         rt61pci_bbp_read(rt2x00dev, 77, &r77);
554
555         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
556                           rt2x00_rf(&rt2x00dev->chip, RF2529));
557         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
558                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
559
560         /*
561          * Configure the RX antenna.
562          */
563         switch (ant->rx) {
564         case ANTENNA_HW_DIVERSITY:
565                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
566                 break;
567         case ANTENNA_A:
568                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
569                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
570                 break;
571         case ANTENNA_B:
572         default:
573                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
574                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
575                 break;
576         }
577
578         rt61pci_bbp_write(rt2x00dev, 77, r77);
579         rt61pci_bbp_write(rt2x00dev, 3, r3);
580         rt61pci_bbp_write(rt2x00dev, 4, r4);
581 }
582
583 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
584                                            const int p1, const int p2)
585 {
586         u32 reg;
587
588         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
589
590         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
591         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
592
593         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
594         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
595
596         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
597 }
598
599 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
600                                         struct antenna_setup *ant)
601 {
602         u8 r3;
603         u8 r4;
604         u8 r77;
605
606         rt61pci_bbp_read(rt2x00dev, 3, &r3);
607         rt61pci_bbp_read(rt2x00dev, 4, &r4);
608         rt61pci_bbp_read(rt2x00dev, 77, &r77);
609
610         /*
611          * Configure the RX antenna.
612          */
613         switch (ant->rx) {
614         case ANTENNA_A:
615                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
616                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
617                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
618                 break;
619         case ANTENNA_HW_DIVERSITY:
620                 /*
621                  * FIXME: Antenna selection for the rf 2529 is very confusing
622                  * in the legacy driver. Just default to antenna B until the
623                  * legacy code can be properly translated into rt2x00 code.
624                  */
625         case ANTENNA_B:
626         default:
627                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
628                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
629                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
630                 break;
631         }
632
633         rt61pci_bbp_write(rt2x00dev, 77, r77);
634         rt61pci_bbp_write(rt2x00dev, 3, r3);
635         rt61pci_bbp_write(rt2x00dev, 4, r4);
636 }
637
638 struct antenna_sel {
639         u8 word;
640         /*
641          * value[0] -> non-LNA
642          * value[1] -> LNA
643          */
644         u8 value[2];
645 };
646
647 static const struct antenna_sel antenna_sel_a[] = {
648         { 96,  { 0x58, 0x78 } },
649         { 104, { 0x38, 0x48 } },
650         { 75,  { 0xfe, 0x80 } },
651         { 86,  { 0xfe, 0x80 } },
652         { 88,  { 0xfe, 0x80 } },
653         { 35,  { 0x60, 0x60 } },
654         { 97,  { 0x58, 0x58 } },
655         { 98,  { 0x58, 0x58 } },
656 };
657
658 static const struct antenna_sel antenna_sel_bg[] = {
659         { 96,  { 0x48, 0x68 } },
660         { 104, { 0x2c, 0x3c } },
661         { 75,  { 0xfe, 0x80 } },
662         { 86,  { 0xfe, 0x80 } },
663         { 88,  { 0xfe, 0x80 } },
664         { 35,  { 0x50, 0x50 } },
665         { 97,  { 0x48, 0x48 } },
666         { 98,  { 0x48, 0x48 } },
667 };
668
669 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
670                                    struct antenna_setup *ant)
671 {
672         const struct antenna_sel *sel;
673         unsigned int lna;
674         unsigned int i;
675         u32 reg;
676
677         /*
678          * We should never come here because rt2x00lib is supposed
679          * to catch this and send us the correct antenna explicitely.
680          */
681         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
682                ant->tx == ANTENNA_SW_DIVERSITY);
683
684         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
685                 sel = antenna_sel_a;
686                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
687         } else {
688                 sel = antenna_sel_bg;
689                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
690         }
691
692         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
693                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
694
695         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
696
697         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
698                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
699         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
700                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
701
702         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
703
704         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
705             rt2x00_rf(&rt2x00dev->chip, RF5325))
706                 rt61pci_config_antenna_5x(rt2x00dev, ant);
707         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
708                 rt61pci_config_antenna_2x(rt2x00dev, ant);
709         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
710                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
711                         rt61pci_config_antenna_2x(rt2x00dev, ant);
712                 else
713                         rt61pci_config_antenna_2529(rt2x00dev, ant);
714         }
715 }
716
717 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
718                                     struct rt2x00lib_conf *libconf)
719 {
720         u32 reg;
721
722         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
723         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
724         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
725
726         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
727         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
728         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
729         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
730         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
731
732         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
733         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
734         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
735
736         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
737         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
738         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
739
740         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
741         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
742                            libconf->conf->beacon_int * 16);
743         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
744 }
745
746 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
747                            struct rt2x00lib_conf *libconf,
748                            const unsigned int flags)
749 {
750         if (flags & CONFIG_UPDATE_PHYMODE)
751                 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
752         if (flags & CONFIG_UPDATE_CHANNEL)
753                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
754                                        libconf->conf->power_level);
755         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
756                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
757         if (flags & CONFIG_UPDATE_ANTENNA)
758                 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
759         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
760                 rt61pci_config_duration(rt2x00dev, libconf);
761 }
762
763 /*
764  * Link tuning
765  */
766 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
767                                struct link_qual *qual)
768 {
769         u32 reg;
770
771         /*
772          * Update FCS error count from register.
773          */
774         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
775         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
776
777         /*
778          * Update False CCA count from register.
779          */
780         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
781         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
782 }
783
784 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
785 {
786         rt61pci_bbp_write(rt2x00dev, 17, 0x20);
787         rt2x00dev->link.vgc_level = 0x20;
788 }
789
790 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
791 {
792         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
793         u8 r17;
794         u8 up_bound;
795         u8 low_bound;
796
797         rt61pci_bbp_read(rt2x00dev, 17, &r17);
798
799         /*
800          * Determine r17 bounds.
801          */
802         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
803                 low_bound = 0x28;
804                 up_bound = 0x48;
805                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
806                         low_bound += 0x10;
807                         up_bound += 0x10;
808                 }
809         } else {
810                 low_bound = 0x20;
811                 up_bound = 0x40;
812                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
813                         low_bound += 0x10;
814                         up_bound += 0x10;
815                 }
816         }
817
818         /*
819          * If we are not associated, we should go straight to the
820          * dynamic CCA tuning.
821          */
822         if (!rt2x00dev->intf_associated)
823                 goto dynamic_cca_tune;
824
825         /*
826          * Special big-R17 for very short distance
827          */
828         if (rssi >= -35) {
829                 if (r17 != 0x60)
830                         rt61pci_bbp_write(rt2x00dev, 17, 0x60);
831                 return;
832         }
833
834         /*
835          * Special big-R17 for short distance
836          */
837         if (rssi >= -58) {
838                 if (r17 != up_bound)
839                         rt61pci_bbp_write(rt2x00dev, 17, up_bound);
840                 return;
841         }
842
843         /*
844          * Special big-R17 for middle-short distance
845          */
846         if (rssi >= -66) {
847                 low_bound += 0x10;
848                 if (r17 != low_bound)
849                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
850                 return;
851         }
852
853         /*
854          * Special mid-R17 for middle distance
855          */
856         if (rssi >= -74) {
857                 low_bound += 0x08;
858                 if (r17 != low_bound)
859                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
860                 return;
861         }
862
863         /*
864          * Special case: Change up_bound based on the rssi.
865          * Lower up_bound when rssi is weaker then -74 dBm.
866          */
867         up_bound -= 2 * (-74 - rssi);
868         if (low_bound > up_bound)
869                 up_bound = low_bound;
870
871         if (r17 > up_bound) {
872                 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
873                 return;
874         }
875
876 dynamic_cca_tune:
877
878         /*
879          * r17 does not yet exceed upper limit, continue and base
880          * the r17 tuning on the false CCA count.
881          */
882         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
883                 if (++r17 > up_bound)
884                         r17 = up_bound;
885                 rt61pci_bbp_write(rt2x00dev, 17, r17);
886         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
887                 if (--r17 < low_bound)
888                         r17 = low_bound;
889                 rt61pci_bbp_write(rt2x00dev, 17, r17);
890         }
891 }
892
893 /*
894  * Firmware functions
895  */
896 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
897 {
898         char *fw_name;
899
900         switch (rt2x00dev->chip.rt) {
901         case RT2561:
902                 fw_name = FIRMWARE_RT2561;
903                 break;
904         case RT2561s:
905                 fw_name = FIRMWARE_RT2561s;
906                 break;
907         case RT2661:
908                 fw_name = FIRMWARE_RT2661;
909                 break;
910         default:
911                 fw_name = NULL;
912                 break;
913         }
914
915         return fw_name;
916 }
917
918 static u16 rt61pci_get_firmware_crc(void *data, const size_t len)
919 {
920         u16 crc;
921
922         /*
923          * Use the crc itu-t algorithm.
924          * The last 2 bytes in the firmware array are the crc checksum itself,
925          * this means that we should never pass those 2 bytes to the crc
926          * algorithm.
927          */
928         crc = crc_itu_t(0, data, len - 2);
929         crc = crc_itu_t_byte(crc, 0);
930         crc = crc_itu_t_byte(crc, 0);
931
932         return crc;
933 }
934
935 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
936                                  const size_t len)
937 {
938         int i;
939         u32 reg;
940
941         /*
942          * Wait for stable hardware.
943          */
944         for (i = 0; i < 100; i++) {
945                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
946                 if (reg)
947                         break;
948                 msleep(1);
949         }
950
951         if (!reg) {
952                 ERROR(rt2x00dev, "Unstable hardware.\n");
953                 return -EBUSY;
954         }
955
956         /*
957          * Prepare MCU and mailbox for firmware loading.
958          */
959         reg = 0;
960         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
961         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
962         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
963         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
964         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
965
966         /*
967          * Write firmware to device.
968          */
969         reg = 0;
970         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
971         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
972         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
973
974         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
975                                       data, len);
976
977         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
978         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
979
980         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
981         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
982
983         for (i = 0; i < 100; i++) {
984                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
985                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
986                         break;
987                 msleep(1);
988         }
989
990         if (i == 100) {
991                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
992                 return -EBUSY;
993         }
994
995         /*
996          * Reset MAC and BBP registers.
997          */
998         reg = 0;
999         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1000         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1001         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1002
1003         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1004         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1005         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1006         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1007
1008         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1009         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1010         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1011
1012         return 0;
1013 }
1014
1015 /*
1016  * Initialization functions.
1017  */
1018 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1019                                  struct queue_entry *entry)
1020 {
1021         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1022         u32 word;
1023
1024         rt2x00_desc_read(priv_rx->desc, 5, &word);
1025         rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1026                            priv_rx->data_dma);
1027         rt2x00_desc_write(priv_rx->desc, 5, word);
1028
1029         rt2x00_desc_read(priv_rx->desc, 0, &word);
1030         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1031         rt2x00_desc_write(priv_rx->desc, 0, word);
1032 }
1033
1034 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1035                                  struct queue_entry *entry)
1036 {
1037         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
1038         u32 word;
1039
1040         rt2x00_desc_read(priv_tx->desc, 1, &word);
1041         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1042         rt2x00_desc_write(priv_tx->desc, 1, word);
1043
1044         rt2x00_desc_read(priv_tx->desc, 5, &word);
1045         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1046         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
1047         rt2x00_desc_write(priv_tx->desc, 5, word);
1048
1049         rt2x00_desc_read(priv_tx->desc, 6, &word);
1050         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1051                            priv_tx->data_dma);
1052         rt2x00_desc_write(priv_tx->desc, 6, word);
1053
1054         rt2x00_desc_read(priv_tx->desc, 0, &word);
1055         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1056         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1057         rt2x00_desc_write(priv_tx->desc, 0, word);
1058 }
1059
1060 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1061 {
1062         struct queue_entry_priv_pci_rx *priv_rx;
1063         struct queue_entry_priv_pci_tx *priv_tx;
1064         u32 reg;
1065
1066         /*
1067          * Initialize registers.
1068          */
1069         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1070         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1071                            rt2x00dev->tx[0].limit);
1072         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1073                            rt2x00dev->tx[1].limit);
1074         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1075                            rt2x00dev->tx[2].limit);
1076         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1077                            rt2x00dev->tx[3].limit);
1078         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1079
1080         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1081         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1082                            rt2x00dev->tx[0].desc_size / 4);
1083         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1084
1085         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
1086         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1087         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1088                            priv_tx->desc_dma);
1089         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1090
1091         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
1092         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1093         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1094                            priv_tx->desc_dma);
1095         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1096
1097         priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
1098         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1099         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1100                            priv_tx->desc_dma);
1101         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1102
1103         priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
1104         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1105         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1106                            priv_tx->desc_dma);
1107         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1108
1109         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1110         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1111         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1112                            rt2x00dev->rx->desc_size / 4);
1113         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1114         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1115
1116         priv_rx = rt2x00dev->rx->entries[0].priv_data;
1117         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1118         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1119                            priv_rx->desc_dma);
1120         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1121
1122         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1123         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1124         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1125         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1126         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1127         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1128
1129         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1130         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1131         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1132         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1133         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1134         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1135
1136         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1137         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1138         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1139
1140         return 0;
1141 }
1142
1143 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1144 {
1145         u32 reg;
1146
1147         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1148         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1149         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1150         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1151         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1152
1153         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1154         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1155         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1156         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1157         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1158         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1159         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1160         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1161         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1162         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1163
1164         /*
1165          * CCK TXD BBP registers
1166          */
1167         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1168         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1169         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1170         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1171         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1172         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1173         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1174         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1175         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1176         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1177
1178         /*
1179          * OFDM TXD BBP registers
1180          */
1181         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1182         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1183         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1184         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1185         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1186         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1187         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1188         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1189
1190         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1191         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1192         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1193         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1194         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1195         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1196
1197         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1198         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1199         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1200         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1201         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1202         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1203
1204         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1205
1206         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1207
1208         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1209         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1210         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1211
1212         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1213
1214         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1215                 return -EBUSY;
1216
1217         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1218
1219         /*
1220          * Invalidate all Shared Keys (SEC_CSR0),
1221          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1222          */
1223         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1224         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1225         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1226
1227         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1228         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1229         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1230         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1231
1232         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1233
1234         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1235
1236         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1237
1238         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1239         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1240         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1241         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1242
1243         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1244         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1245         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1246         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1247
1248         /*
1249          * Clear all beacons
1250          * For the Beacon base registers we only need to clear
1251          * the first byte since that byte contains the VALID and OWNER
1252          * bits which (when set to 0) will invalidate the entire beacon.
1253          */
1254         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1255         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1256         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1257         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1258
1259         /*
1260          * We must clear the error counters.
1261          * These registers are cleared on read,
1262          * so we may pass a useless variable to store the value.
1263          */
1264         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1265         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1266         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1267
1268         /*
1269          * Reset MAC and BBP registers.
1270          */
1271         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1272         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1273         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1274         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1275
1276         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1277         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1278         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1279         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1280
1281         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1282         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1283         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1284
1285         return 0;
1286 }
1287
1288 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1289 {
1290         unsigned int i;
1291         u16 eeprom;
1292         u8 reg_id;
1293         u8 value;
1294
1295         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1296                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1297                 if ((value != 0xff) && (value != 0x00))
1298                         goto continue_csr_init;
1299                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1300                 udelay(REGISTER_BUSY_DELAY);
1301         }
1302
1303         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1304         return -EACCES;
1305
1306 continue_csr_init:
1307         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1308         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1309         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1310         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1311         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1312         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1313         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1314         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1315         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1316         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1317         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1318         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1319         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1320         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1321         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1322         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1323         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1324         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1325         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1326         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1327         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1328         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1329         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1330         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1331
1332         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1333                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1334
1335                 if (eeprom != 0xffff && eeprom != 0x0000) {
1336                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1337                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1338                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1339                 }
1340         }
1341
1342         return 0;
1343 }
1344
1345 /*
1346  * Device state switch handlers.
1347  */
1348 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1349                               enum dev_state state)
1350 {
1351         u32 reg;
1352
1353         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1354         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1355                            state == STATE_RADIO_RX_OFF);
1356         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1357 }
1358
1359 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1360                                enum dev_state state)
1361 {
1362         int mask = (state == STATE_RADIO_IRQ_OFF);
1363         u32 reg;
1364
1365         /*
1366          * When interrupts are being enabled, the interrupt registers
1367          * should clear the register to assure a clean state.
1368          */
1369         if (state == STATE_RADIO_IRQ_ON) {
1370                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1371                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1372
1373                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1374                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1375         }
1376
1377         /*
1378          * Only toggle the interrupts bits we are going to use.
1379          * Non-checked interrupt bits are disabled by default.
1380          */
1381         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1382         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1383         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1384         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1385         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1386         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1387
1388         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1389         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1390         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1391         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1392         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1393         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1394         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1395         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1396         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1397         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1398 }
1399
1400 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1401 {
1402         u32 reg;
1403
1404         /*
1405          * Initialize all registers.
1406          */
1407         if (rt61pci_init_queues(rt2x00dev) ||
1408             rt61pci_init_registers(rt2x00dev) ||
1409             rt61pci_init_bbp(rt2x00dev)) {
1410                 ERROR(rt2x00dev, "Register initialization failed.\n");
1411                 return -EIO;
1412         }
1413
1414         /*
1415          * Enable interrupts.
1416          */
1417         rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1418
1419         /*
1420          * Enable RX.
1421          */
1422         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1423         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1424         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1425
1426         return 0;
1427 }
1428
1429 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1430 {
1431         u32 reg;
1432
1433         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1434
1435         /*
1436          * Disable synchronisation.
1437          */
1438         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1439
1440         /*
1441          * Cancel RX and TX.
1442          */
1443         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1444         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1445         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1446         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1447         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1448         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1449
1450         /*
1451          * Disable interrupts.
1452          */
1453         rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1454 }
1455
1456 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1457 {
1458         u32 reg;
1459         unsigned int i;
1460         char put_to_sleep;
1461         char current_state;
1462
1463         put_to_sleep = (state != STATE_AWAKE);
1464
1465         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1466         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1467         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1468         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1469
1470         /*
1471          * Device is not guaranteed to be in the requested state yet.
1472          * We must wait until the register indicates that the
1473          * device has entered the correct state.
1474          */
1475         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1476                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1477                 current_state =
1478                     rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1479                 if (current_state == !put_to_sleep)
1480                         return 0;
1481                 msleep(10);
1482         }
1483
1484         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1485                "current device state %d.\n", !put_to_sleep, current_state);
1486
1487         return -EBUSY;
1488 }
1489
1490 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1491                                     enum dev_state state)
1492 {
1493         int retval = 0;
1494
1495         switch (state) {
1496         case STATE_RADIO_ON:
1497                 retval = rt61pci_enable_radio(rt2x00dev);
1498                 break;
1499         case STATE_RADIO_OFF:
1500                 rt61pci_disable_radio(rt2x00dev);
1501                 break;
1502         case STATE_RADIO_RX_ON:
1503         case STATE_RADIO_RX_ON_LINK:
1504                 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1505                 break;
1506         case STATE_RADIO_RX_OFF:
1507         case STATE_RADIO_RX_OFF_LINK:
1508                 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1509                 break;
1510         case STATE_DEEP_SLEEP:
1511         case STATE_SLEEP:
1512         case STATE_STANDBY:
1513         case STATE_AWAKE:
1514                 retval = rt61pci_set_state(rt2x00dev, state);
1515                 break;
1516         default:
1517                 retval = -ENOTSUPP;
1518                 break;
1519         }
1520
1521         return retval;
1522 }
1523
1524 /*
1525  * TX descriptor initialization
1526  */
1527 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1528                                     struct sk_buff *skb,
1529                                     struct txentry_desc *txdesc,
1530                                     struct ieee80211_tx_control *control)
1531 {
1532         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1533         __le32 *txd = skbdesc->desc;
1534         u32 word;
1535
1536         /*
1537          * Start writing the descriptor words.
1538          */
1539         rt2x00_desc_read(txd, 1, &word);
1540         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1541         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1542         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1543         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1544         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1545         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1546         rt2x00_desc_write(txd, 1, word);
1547
1548         rt2x00_desc_read(txd, 2, &word);
1549         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1550         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1551         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1552         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1553         rt2x00_desc_write(txd, 2, word);
1554
1555         rt2x00_desc_read(txd, 5, &word);
1556         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1557                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1558         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1559         rt2x00_desc_write(txd, 5, word);
1560
1561         if (skbdesc->desc_len > TXINFO_SIZE) {
1562                 rt2x00_desc_read(txd, 11, &word);
1563                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1564                 rt2x00_desc_write(txd, 11, word);
1565         }
1566
1567         rt2x00_desc_read(txd, 0, &word);
1568         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1569         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1570         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1571                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1572         rt2x00_set_field32(&word, TXD_W0_ACK,
1573                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1574         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1575                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1576         rt2x00_set_field32(&word, TXD_W0_OFDM,
1577                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1578         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1579         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1580                            !!(control->flags &
1581                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1582         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1583         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1584         rt2x00_set_field32(&word, TXD_W0_BURST,
1585                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1586         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1587         rt2x00_desc_write(txd, 0, word);
1588 }
1589
1590 /*
1591  * TX data initialization
1592  */
1593 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1594                                   const enum data_queue_qid queue)
1595 {
1596         u32 reg;
1597
1598         if (queue == QID_BEACON) {
1599                 /*
1600                  * For Wi-Fi faily generated beacons between participating
1601                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1602                  */
1603                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1604
1605                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1606                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1607                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1608                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1609                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1610                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1611                 }
1612                 return;
1613         }
1614
1615         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1616         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1617         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1618         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1619         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1620         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1621 }
1622
1623 /*
1624  * RX control handlers
1625  */
1626 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1627 {
1628         u16 eeprom;
1629         u8 offset;
1630         u8 lna;
1631
1632         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1633         switch (lna) {
1634         case 3:
1635                 offset = 90;
1636                 break;
1637         case 2:
1638                 offset = 74;
1639                 break;
1640         case 1:
1641                 offset = 64;
1642                 break;
1643         default:
1644                 return 0;
1645         }
1646
1647         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1648                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1649                         offset += 14;
1650
1651                 if (lna == 3 || lna == 2)
1652                         offset += 10;
1653
1654                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1655                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1656         } else {
1657                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1658                         offset += 14;
1659
1660                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1661                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1662         }
1663
1664         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1665 }
1666
1667 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1668                                 struct rxdone_entry_desc *rxdesc)
1669 {
1670         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1671         u32 word0;
1672         u32 word1;
1673
1674         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1675         rt2x00_desc_read(priv_rx->desc, 1, &word1);
1676
1677         rxdesc->flags = 0;
1678         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1679                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1680
1681         /*
1682          * Obtain the status about this packet.
1683          * When frame was received with an OFDM bitrate,
1684          * the signal is the PLCP value. If it was received with
1685          * a CCK bitrate the signal is the rate in 100kbit/s.
1686          */
1687         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1688         rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1689         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1690
1691         rxdesc->dev_flags = 0;
1692         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1693                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1694         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1695                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1696 }
1697
1698 /*
1699  * Interrupt functions.
1700  */
1701 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1702 {
1703         struct data_queue *queue;
1704         struct queue_entry *entry;
1705         struct queue_entry *entry_done;
1706         struct queue_entry_priv_pci_tx *priv_tx;
1707         struct txdone_entry_desc txdesc;
1708         u32 word;
1709         u32 reg;
1710         u32 old_reg;
1711         int type;
1712         int index;
1713
1714         /*
1715          * During each loop we will compare the freshly read
1716          * STA_CSR4 register value with the value read from
1717          * the previous loop. If the 2 values are equal then
1718          * we should stop processing because the chance it
1719          * quite big that the device has been unplugged and
1720          * we risk going into an endless loop.
1721          */
1722         old_reg = 0;
1723
1724         while (1) {
1725                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1726                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1727                         break;
1728
1729                 if (old_reg == reg)
1730                         break;
1731                 old_reg = reg;
1732
1733                 /*
1734                  * Skip this entry when it contains an invalid
1735                  * queue identication number.
1736                  */
1737                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1738                 queue = rt2x00queue_get_queue(rt2x00dev, type);
1739                 if (unlikely(!queue))
1740                         continue;
1741
1742                 /*
1743                  * Skip this entry when it contains an invalid
1744                  * index number.
1745                  */
1746                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1747                 if (unlikely(index >= queue->limit))
1748                         continue;
1749
1750                 entry = &queue->entries[index];
1751                 priv_tx = entry->priv_data;
1752                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1753
1754                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1755                     !rt2x00_get_field32(word, TXD_W0_VALID))
1756                         return;
1757
1758                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1759                 while (entry != entry_done) {
1760                         /* Catch up.
1761                          * Just report any entries we missed as failed.
1762                          */
1763                         WARNING(rt2x00dev,
1764                                 "TX status report missed for entry %d\n",
1765                                 entry_done->entry_idx);
1766
1767                         txdesc.status = TX_FAIL_OTHER;
1768                         txdesc.retry = 0;
1769
1770                         rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1771                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1772                 }
1773
1774                 /*
1775                  * Obtain the status about this packet.
1776                  */
1777                 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1778                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1779
1780                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1781         }
1782 }
1783
1784 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1785 {
1786         struct rt2x00_dev *rt2x00dev = dev_instance;
1787         u32 reg_mcu;
1788         u32 reg;
1789
1790         /*
1791          * Get the interrupt sources & saved to local variable.
1792          * Write register value back to clear pending interrupts.
1793          */
1794         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1795         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1796
1797         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1798         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1799
1800         if (!reg && !reg_mcu)
1801                 return IRQ_NONE;
1802
1803         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1804                 return IRQ_HANDLED;
1805
1806         /*
1807          * Handle interrupts, walk through all bits
1808          * and run the tasks, the bits are checked in order of
1809          * priority.
1810          */
1811
1812         /*
1813          * 1 - Rx ring done interrupt.
1814          */
1815         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1816                 rt2x00pci_rxdone(rt2x00dev);
1817
1818         /*
1819          * 2 - Tx ring done interrupt.
1820          */
1821         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1822                 rt61pci_txdone(rt2x00dev);
1823
1824         /*
1825          * 3 - Handle MCU command done.
1826          */
1827         if (reg_mcu)
1828                 rt2x00pci_register_write(rt2x00dev,
1829                                          M2H_CMD_DONE_CSR, 0xffffffff);
1830
1831         return IRQ_HANDLED;
1832 }
1833
1834 /*
1835  * Device probe functions.
1836  */
1837 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1838 {
1839         struct eeprom_93cx6 eeprom;
1840         u32 reg;
1841         u16 word;
1842         u8 *mac;
1843         s8 value;
1844
1845         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1846
1847         eeprom.data = rt2x00dev;
1848         eeprom.register_read = rt61pci_eepromregister_read;
1849         eeprom.register_write = rt61pci_eepromregister_write;
1850         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1851             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1852         eeprom.reg_data_in = 0;
1853         eeprom.reg_data_out = 0;
1854         eeprom.reg_data_clock = 0;
1855         eeprom.reg_chip_select = 0;
1856
1857         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1858                                EEPROM_SIZE / sizeof(u16));
1859
1860         /*
1861          * Start validation of the data that has been read.
1862          */
1863         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1864         if (!is_valid_ether_addr(mac)) {
1865                 DECLARE_MAC_BUF(macbuf);
1866
1867                 random_ether_addr(mac);
1868                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1869         }
1870
1871         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1872         if (word == 0xffff) {
1873                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1874                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1875                                    ANTENNA_B);
1876                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1877                                    ANTENNA_B);
1878                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1879                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1880                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1881                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1882                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1883                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1884         }
1885
1886         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1887         if (word == 0xffff) {
1888                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1889                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1890                 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1891                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1892                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1893                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1894                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1895                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1896         }
1897
1898         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1899         if (word == 0xffff) {
1900                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1901                                    LED_MODE_DEFAULT);
1902                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1903                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1904         }
1905
1906         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1907         if (word == 0xffff) {
1908                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1909                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1910                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1911                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1912         }
1913
1914         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1915         if (word == 0xffff) {
1916                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1917                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1918                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1919                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1920         } else {
1921                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1922                 if (value < -10 || value > 10)
1923                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1924                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1925                 if (value < -10 || value > 10)
1926                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1927                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1928         }
1929
1930         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1931         if (word == 0xffff) {
1932                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1933                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1934                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1935                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1936         } else {
1937                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1938                 if (value < -10 || value > 10)
1939                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1940                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1941                 if (value < -10 || value > 10)
1942                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1943                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1944         }
1945
1946         return 0;
1947 }
1948
1949 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1950 {
1951         u32 reg;
1952         u16 value;
1953         u16 eeprom;
1954         u16 device;
1955
1956         /*
1957          * Read EEPROM word for configuration.
1958          */
1959         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1960
1961         /*
1962          * Identify RF chipset.
1963          * To determine the RT chip we have to read the
1964          * PCI header of the device.
1965          */
1966         pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1967                              PCI_CONFIG_HEADER_DEVICE, &device);
1968         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1969         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1970         rt2x00_set_chip(rt2x00dev, device, value, reg);
1971
1972         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1973             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1974             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1975             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1976                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1977                 return -ENODEV;
1978         }
1979
1980         /*
1981          * Determine number of antenna's.
1982          */
1983         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1984                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1985
1986         /*
1987          * Identify default antenna configuration.
1988          */
1989         rt2x00dev->default_ant.tx =
1990             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1991         rt2x00dev->default_ant.rx =
1992             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1993
1994         /*
1995          * Read the Frame type.
1996          */
1997         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1998                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1999
2000         /*
2001          * Detect if this device has an hardware controlled radio.
2002          */
2003 #ifdef CONFIG_RT61PCI_RFKILL
2004         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2005                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2006 #endif /* CONFIG_RT61PCI_RFKILL */
2007
2008         /*
2009          * Read frequency offset and RF programming sequence.
2010          */
2011         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2012         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2013                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2014
2015         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2016
2017         /*
2018          * Read external LNA informations.
2019          */
2020         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2021
2022         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2023                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2024         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2025                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2026
2027         /*
2028          * When working with a RF2529 chip without double antenna
2029          * the antenna settings should be gathered from the NIC
2030          * eeprom word.
2031          */
2032         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2033             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2034                 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2035                 case 0:
2036                         rt2x00dev->default_ant.tx = ANTENNA_B;
2037                         rt2x00dev->default_ant.rx = ANTENNA_A;
2038                         break;
2039                 case 1:
2040                         rt2x00dev->default_ant.tx = ANTENNA_B;
2041                         rt2x00dev->default_ant.rx = ANTENNA_B;
2042                         break;
2043                 case 2:
2044                         rt2x00dev->default_ant.tx = ANTENNA_A;
2045                         rt2x00dev->default_ant.rx = ANTENNA_A;
2046                         break;
2047                 case 3:
2048                         rt2x00dev->default_ant.tx = ANTENNA_A;
2049                         rt2x00dev->default_ant.rx = ANTENNA_B;
2050                         break;
2051                 }
2052
2053                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2054                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2055                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2056                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2057         }
2058
2059         /*
2060          * Store led settings, for correct led behaviour.
2061          * If the eeprom value is invalid,
2062          * switch to default led mode.
2063          */
2064 #ifdef CONFIG_RT61PCI_LEDS
2065         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2066         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2067
2068         rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
2069         rt2x00dev->led_radio.type = LED_TYPE_RADIO;
2070         rt2x00dev->led_radio.led_dev.brightness_set =
2071             rt61pci_brightness_set;
2072         rt2x00dev->led_radio.led_dev.blink_set =
2073             rt61pci_blink_set;
2074         rt2x00dev->led_radio.flags = LED_INITIALIZED;
2075
2076         rt2x00dev->led_assoc.rt2x00dev = rt2x00dev;
2077         rt2x00dev->led_assoc.type = LED_TYPE_ASSOC;
2078         rt2x00dev->led_assoc.led_dev.brightness_set =
2079             rt61pci_brightness_set;
2080         rt2x00dev->led_assoc.led_dev.blink_set =
2081             rt61pci_blink_set;
2082         rt2x00dev->led_assoc.flags = LED_INITIALIZED;
2083
2084         if (value == LED_MODE_SIGNAL_STRENGTH) {
2085                 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
2086                 rt2x00dev->led_qual.type = LED_TYPE_QUALITY;
2087                 rt2x00dev->led_qual.led_dev.brightness_set =
2088                     rt61pci_brightness_set;
2089                 rt2x00dev->led_qual.led_dev.blink_set =
2090                     rt61pci_blink_set;
2091                 rt2x00dev->led_qual.flags = LED_INITIALIZED;
2092         }
2093
2094         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2095         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2096                            rt2x00_get_field16(eeprom,
2097                                               EEPROM_LED_POLARITY_GPIO_0));
2098         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2099                            rt2x00_get_field16(eeprom,
2100                                               EEPROM_LED_POLARITY_GPIO_1));
2101         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2102                            rt2x00_get_field16(eeprom,
2103                                               EEPROM_LED_POLARITY_GPIO_2));
2104         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2105                            rt2x00_get_field16(eeprom,
2106                                               EEPROM_LED_POLARITY_GPIO_3));
2107         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2108                            rt2x00_get_field16(eeprom,
2109                                               EEPROM_LED_POLARITY_GPIO_4));
2110         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2111                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2112         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2113                            rt2x00_get_field16(eeprom,
2114                                               EEPROM_LED_POLARITY_RDY_G));
2115         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2116                            rt2x00_get_field16(eeprom,
2117                                               EEPROM_LED_POLARITY_RDY_A));
2118 #endif /* CONFIG_RT61PCI_LEDS */
2119
2120         return 0;
2121 }
2122
2123 /*
2124  * RF value list for RF5225 & RF5325
2125  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2126  */
2127 static const struct rf_channel rf_vals_noseq[] = {
2128         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2129         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2130         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2131         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2132         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2133         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2134         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2135         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2136         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2137         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2138         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2139         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2140         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2141         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2142
2143         /* 802.11 UNI / HyperLan 2 */
2144         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2145         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2146         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2147         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2148         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2149         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2150         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2151         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2152
2153         /* 802.11 HyperLan 2 */
2154         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2155         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2156         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2157         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2158         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2159         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2160         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2161         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2162         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2163         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2164
2165         /* 802.11 UNII */
2166         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2167         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2168         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2169         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2170         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2171         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2172
2173         /* MMAC(Japan)J52 ch 34,38,42,46 */
2174         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2175         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2176         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2177         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2178 };
2179
2180 /*
2181  * RF value list for RF5225 & RF5325
2182  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2183  */
2184 static const struct rf_channel rf_vals_seq[] = {
2185         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2186         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2187         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2188         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2189         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2190         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2191         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2192         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2193         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2194         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2195         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2196         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2197         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2198         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2199
2200         /* 802.11 UNI / HyperLan 2 */
2201         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2202         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2203         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2204         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2205         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2206         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2207         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2208         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2209
2210         /* 802.11 HyperLan 2 */
2211         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2212         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2213         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2214         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2215         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2216         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2217         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2218         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2219         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2220         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2221
2222         /* 802.11 UNII */
2223         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2224         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2225         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2226         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2227         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2228         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2229
2230         /* MMAC(Japan)J52 ch 34,38,42,46 */
2231         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2232         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2233         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2234         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2235 };
2236
2237 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2238 {
2239         struct hw_mode_spec *spec = &rt2x00dev->spec;
2240         u8 *txpower;
2241         unsigned int i;
2242
2243         /*
2244          * Initialize all hw fields.
2245          */
2246         rt2x00dev->hw->flags =
2247             IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2248             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2249         rt2x00dev->hw->extra_tx_headroom = 0;
2250         rt2x00dev->hw->max_signal = MAX_SIGNAL;
2251         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2252         rt2x00dev->hw->queues = 4;
2253
2254         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2255         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2256                                 rt2x00_eeprom_addr(rt2x00dev,
2257                                                    EEPROM_MAC_ADDR_0));
2258
2259         /*
2260          * Convert tx_power array in eeprom.
2261          */
2262         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2263         for (i = 0; i < 14; i++)
2264                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2265
2266         /*
2267          * Initialize hw_mode information.
2268          */
2269         spec->supported_bands = SUPPORT_BAND_2GHZ;
2270         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2271         spec->tx_power_a = NULL;
2272         spec->tx_power_bg = txpower;
2273         spec->tx_power_default = DEFAULT_TXPOWER;
2274
2275         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2276                 spec->num_channels = 14;
2277                 spec->channels = rf_vals_noseq;
2278         } else {
2279                 spec->num_channels = 14;
2280                 spec->channels = rf_vals_seq;
2281         }
2282
2283         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2284             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2285                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2286                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2287
2288                 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2289                 for (i = 0; i < 14; i++)
2290                         txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2291
2292                 spec->tx_power_a = txpower;
2293         }
2294 }
2295
2296 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2297 {
2298         int retval;
2299
2300         /*
2301          * Allocate eeprom data.
2302          */
2303         retval = rt61pci_validate_eeprom(rt2x00dev);
2304         if (retval)
2305                 return retval;
2306
2307         retval = rt61pci_init_eeprom(rt2x00dev);
2308         if (retval)
2309                 return retval;
2310
2311         /*
2312          * Initialize hw specifications.
2313          */
2314         rt61pci_probe_hw_mode(rt2x00dev);
2315
2316         /*
2317          * This device requires firmware.
2318          */
2319         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2320
2321         /*
2322          * Set the rssi offset.
2323          */
2324         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2325
2326         return 0;
2327 }
2328
2329 /*
2330  * IEEE80211 stack callback functions.
2331  */
2332 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2333                                    u32 short_retry, u32 long_retry)
2334 {
2335         struct rt2x00_dev *rt2x00dev = hw->priv;
2336         u32 reg;
2337
2338         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2339         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2340         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2341         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2342
2343         return 0;
2344 }
2345
2346 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2347 {
2348         struct rt2x00_dev *rt2x00dev = hw->priv;
2349         u64 tsf;
2350         u32 reg;
2351
2352         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2353         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2354         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2355         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2356
2357         return tsf;
2358 }
2359
2360 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2361                           struct ieee80211_tx_control *control)
2362 {
2363         struct rt2x00_dev *rt2x00dev = hw->priv;
2364         struct rt2x00_intf *intf = vif_to_intf(control->vif);
2365         struct queue_entry_priv_pci_tx *priv_tx;
2366         struct skb_frame_desc *skbdesc;
2367         unsigned int beacon_base;
2368         u32 reg;
2369
2370         if (unlikely(!intf->beacon))
2371                 return -ENOBUFS;
2372
2373         priv_tx = intf->beacon->priv_data;
2374         memset(priv_tx->desc, 0, intf->beacon->queue->desc_size);
2375
2376         /*
2377          * Fill in skb descriptor
2378          */
2379         skbdesc = get_skb_frame_desc(skb);
2380         memset(skbdesc, 0, sizeof(*skbdesc));
2381         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2382         skbdesc->data = skb->data;
2383         skbdesc->data_len = skb->len;
2384         skbdesc->desc = priv_tx->desc;
2385         skbdesc->desc_len = intf->beacon->queue->desc_size;
2386         skbdesc->entry = intf->beacon;
2387
2388         /*
2389          * Disable beaconing while we are reloading the beacon data,
2390          * otherwise we might be sending out invalid data.
2391          */
2392         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2393         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2394         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2395         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2396         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2397
2398         /*
2399          * Write entire beacon with descriptor to register,
2400          * and kick the beacon generator.
2401          */
2402         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2403         beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2404         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2405                                       skbdesc->desc, skbdesc->desc_len);
2406         rt2x00pci_register_multiwrite(rt2x00dev,
2407                                       beacon_base + skbdesc->desc_len,
2408                                       skbdesc->data, skbdesc->data_len);
2409         rt61pci_kick_tx_queue(rt2x00dev, QID_BEACON);
2410
2411         return 0;
2412 }
2413
2414 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2415         .tx                     = rt2x00mac_tx,
2416         .start                  = rt2x00mac_start,
2417         .stop                   = rt2x00mac_stop,
2418         .add_interface          = rt2x00mac_add_interface,
2419         .remove_interface       = rt2x00mac_remove_interface,
2420         .config                 = rt2x00mac_config,
2421         .config_interface       = rt2x00mac_config_interface,
2422         .configure_filter       = rt2x00mac_configure_filter,
2423         .get_stats              = rt2x00mac_get_stats,
2424         .set_retry_limit        = rt61pci_set_retry_limit,
2425         .bss_info_changed       = rt2x00mac_bss_info_changed,
2426         .conf_tx                = rt2x00mac_conf_tx,
2427         .get_tx_stats           = rt2x00mac_get_tx_stats,
2428         .get_tsf                = rt61pci_get_tsf,
2429         .beacon_update          = rt61pci_beacon_update,
2430 };
2431
2432 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2433         .irq_handler            = rt61pci_interrupt,
2434         .probe_hw               = rt61pci_probe_hw,
2435         .get_firmware_name      = rt61pci_get_firmware_name,
2436         .get_firmware_crc       = rt61pci_get_firmware_crc,
2437         .load_firmware          = rt61pci_load_firmware,
2438         .initialize             = rt2x00pci_initialize,
2439         .uninitialize           = rt2x00pci_uninitialize,
2440         .init_rxentry           = rt61pci_init_rxentry,
2441         .init_txentry           = rt61pci_init_txentry,
2442         .set_device_state       = rt61pci_set_device_state,
2443         .rfkill_poll            = rt61pci_rfkill_poll,
2444         .link_stats             = rt61pci_link_stats,
2445         .reset_tuner            = rt61pci_reset_tuner,
2446         .link_tuner             = rt61pci_link_tuner,
2447         .write_tx_desc          = rt61pci_write_tx_desc,
2448         .write_tx_data          = rt2x00pci_write_tx_data,
2449         .kick_tx_queue          = rt61pci_kick_tx_queue,
2450         .fill_rxdone            = rt61pci_fill_rxdone,
2451         .config_filter          = rt61pci_config_filter,
2452         .config_intf            = rt61pci_config_intf,
2453         .config_erp             = rt61pci_config_erp,
2454         .config                 = rt61pci_config,
2455 };
2456
2457 static const struct data_queue_desc rt61pci_queue_rx = {
2458         .entry_num              = RX_ENTRIES,
2459         .data_size              = DATA_FRAME_SIZE,
2460         .desc_size              = RXD_DESC_SIZE,
2461         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
2462 };
2463
2464 static const struct data_queue_desc rt61pci_queue_tx = {
2465         .entry_num              = TX_ENTRIES,
2466         .data_size              = DATA_FRAME_SIZE,
2467         .desc_size              = TXD_DESC_SIZE,
2468         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
2469 };
2470
2471 static const struct data_queue_desc rt61pci_queue_bcn = {
2472         .entry_num              = 4 * BEACON_ENTRIES,
2473         .data_size              = 0, /* No DMA required for beacons */
2474         .desc_size              = TXINFO_SIZE,
2475         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
2476 };
2477
2478 static const struct rt2x00_ops rt61pci_ops = {
2479         .name           = KBUILD_MODNAME,
2480         .max_sta_intf   = 1,
2481         .max_ap_intf    = 4,
2482         .eeprom_size    = EEPROM_SIZE,
2483         .rf_size        = RF_SIZE,
2484         .rx             = &rt61pci_queue_rx,
2485         .tx             = &rt61pci_queue_tx,
2486         .bcn            = &rt61pci_queue_bcn,
2487         .lib            = &rt61pci_rt2x00_ops,
2488         .hw             = &rt61pci_mac80211_ops,
2489 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2490         .debugfs        = &rt61pci_rt2x00debug,
2491 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2492 };
2493
2494 /*
2495  * RT61pci module information.
2496  */
2497 static struct pci_device_id rt61pci_device_table[] = {
2498         /* RT2561s */
2499         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2500         /* RT2561 v2 */
2501         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2502         /* RT2661 */
2503         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2504         { 0, }
2505 };
2506
2507 MODULE_AUTHOR(DRV_PROJECT);
2508 MODULE_VERSION(DRV_VERSION);
2509 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2510 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2511                         "PCI & PCMCIA chipset based cards");
2512 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2513 MODULE_FIRMWARE(FIRMWARE_RT2561);
2514 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2515 MODULE_FIRMWARE(FIRMWARE_RT2661);
2516 MODULE_LICENSE("GPL");
2517
2518 static struct pci_driver rt61pci_driver = {
2519         .name           = KBUILD_MODNAME,
2520         .id_table       = rt61pci_device_table,
2521         .probe          = rt2x00pci_probe,
2522         .remove         = __devexit_p(rt2x00pci_remove),
2523         .suspend        = rt2x00pci_suspend,
2524         .resume         = rt2x00pci_resume,
2525 };
2526
2527 static int __init rt61pci_init(void)
2528 {
2529         return pci_register_driver(&rt61pci_driver);
2530 }
2531
2532 static void __exit rt61pci_exit(void)
2533 {
2534         pci_unregister_driver(&rt61pci_driver);
2535 }
2536
2537 module_init(rt61pci_init);
2538 module_exit(rt61pci_exit);