rt2x00: Introduce 3 queue commands in drivers (start, kick, stop).
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt61pci.c
1 /*
2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt61pci
23         Abstract: rt61pci device specific routines.
24         Supported chipsets: RT2561, RT2561s, RT2661.
25  */
26
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/slab.h>
34 #include <linux/pci.h>
35 #include <linux/eeprom_93cx6.h>
36
37 #include "rt2x00.h"
38 #include "rt2x00pci.h"
39 #include "rt61pci.h"
40
41 /*
42  * Allow hardware encryption to be disabled.
43  */
44 static int modparam_nohwcrypt = 0;
45 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
46 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
47
48 /*
49  * Register access.
50  * BBP and RF register require indirect register access,
51  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
52  * These indirect registers work with busy bits,
53  * and we will try maximal REGISTER_BUSY_COUNT times to access
54  * the register while taking a REGISTER_BUSY_DELAY us delay
55  * between each attempt. When the busy bit is still set at that time,
56  * the access attempt is considered to have failed,
57  * and we will print an error.
58  */
59 #define WAIT_FOR_BBP(__dev, __reg) \
60         rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
61 #define WAIT_FOR_RF(__dev, __reg) \
62         rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
63 #define WAIT_FOR_MCU(__dev, __reg) \
64         rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
65                                H2M_MAILBOX_CSR_OWNER, (__reg))
66
67 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68                               const unsigned int word, const u8 value)
69 {
70         u32 reg;
71
72         mutex_lock(&rt2x00dev->csr_mutex);
73
74         /*
75          * Wait until the BBP becomes available, afterwards we
76          * can safely write the new data into the register.
77          */
78         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
79                 reg = 0;
80                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
81                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
82                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
83                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
84
85                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
86         }
87
88         mutex_unlock(&rt2x00dev->csr_mutex);
89 }
90
91 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
92                              const unsigned int word, u8 *value)
93 {
94         u32 reg;
95
96         mutex_lock(&rt2x00dev->csr_mutex);
97
98         /*
99          * Wait until the BBP becomes available, afterwards we
100          * can safely write the read request into the register.
101          * After the data has been written, we wait until hardware
102          * returns the correct value, if at any time the register
103          * doesn't become available in time, reg will be 0xffffffff
104          * which means we return 0xff to the caller.
105          */
106         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
107                 reg = 0;
108                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
109                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
110                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
111
112                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
113
114                 WAIT_FOR_BBP(rt2x00dev, &reg);
115         }
116
117         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
118
119         mutex_unlock(&rt2x00dev->csr_mutex);
120 }
121
122 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
123                              const unsigned int word, const u32 value)
124 {
125         u32 reg;
126
127         mutex_lock(&rt2x00dev->csr_mutex);
128
129         /*
130          * Wait until the RF becomes available, afterwards we
131          * can safely write the new data into the register.
132          */
133         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
134                 reg = 0;
135                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
136                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
137                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
138                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
139
140                 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
141                 rt2x00_rf_write(rt2x00dev, word, value);
142         }
143
144         mutex_unlock(&rt2x00dev->csr_mutex);
145 }
146
147 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
148                                 const u8 command, const u8 token,
149                                 const u8 arg0, const u8 arg1)
150 {
151         u32 reg;
152
153         mutex_lock(&rt2x00dev->csr_mutex);
154
155         /*
156          * Wait until the MCU becomes available, afterwards we
157          * can safely write the new data into the register.
158          */
159         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
160                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
161                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
162                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
163                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
164                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
165
166                 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
167                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
168                 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
169                 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
170         }
171
172         mutex_unlock(&rt2x00dev->csr_mutex);
173
174 }
175
176 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
177 {
178         struct rt2x00_dev *rt2x00dev = eeprom->data;
179         u32 reg;
180
181         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
182
183         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
184         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
185         eeprom->reg_data_clock =
186             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
187         eeprom->reg_chip_select =
188             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
189 }
190
191 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
192 {
193         struct rt2x00_dev *rt2x00dev = eeprom->data;
194         u32 reg = 0;
195
196         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
197         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
198         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
199                            !!eeprom->reg_data_clock);
200         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
201                            !!eeprom->reg_chip_select);
202
203         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
204 }
205
206 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
207 static const struct rt2x00debug rt61pci_rt2x00debug = {
208         .owner  = THIS_MODULE,
209         .csr    = {
210                 .read           = rt2x00pci_register_read,
211                 .write          = rt2x00pci_register_write,
212                 .flags          = RT2X00DEBUGFS_OFFSET,
213                 .word_base      = CSR_REG_BASE,
214                 .word_size      = sizeof(u32),
215                 .word_count     = CSR_REG_SIZE / sizeof(u32),
216         },
217         .eeprom = {
218                 .read           = rt2x00_eeprom_read,
219                 .write          = rt2x00_eeprom_write,
220                 .word_base      = EEPROM_BASE,
221                 .word_size      = sizeof(u16),
222                 .word_count     = EEPROM_SIZE / sizeof(u16),
223         },
224         .bbp    = {
225                 .read           = rt61pci_bbp_read,
226                 .write          = rt61pci_bbp_write,
227                 .word_base      = BBP_BASE,
228                 .word_size      = sizeof(u8),
229                 .word_count     = BBP_SIZE / sizeof(u8),
230         },
231         .rf     = {
232                 .read           = rt2x00_rf_read,
233                 .write          = rt61pci_rf_write,
234                 .word_base      = RF_BASE,
235                 .word_size      = sizeof(u32),
236                 .word_count     = RF_SIZE / sizeof(u32),
237         },
238 };
239 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
240
241 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
242 {
243         u32 reg;
244
245         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
246         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
247 }
248
249 #ifdef CONFIG_RT2X00_LIB_LEDS
250 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
251                                    enum led_brightness brightness)
252 {
253         struct rt2x00_led *led =
254             container_of(led_cdev, struct rt2x00_led, led_dev);
255         unsigned int enabled = brightness != LED_OFF;
256         unsigned int a_mode =
257             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
258         unsigned int bg_mode =
259             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
260
261         if (led->type == LED_TYPE_RADIO) {
262                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
263                                    MCU_LEDCS_RADIO_STATUS, enabled);
264
265                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
266                                     (led->rt2x00dev->led_mcu_reg & 0xff),
267                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
268         } else if (led->type == LED_TYPE_ASSOC) {
269                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
270                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
271                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
272                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
273
274                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
275                                     (led->rt2x00dev->led_mcu_reg & 0xff),
276                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
277         } else if (led->type == LED_TYPE_QUALITY) {
278                 /*
279                  * The brightness is divided into 6 levels (0 - 5),
280                  * this means we need to convert the brightness
281                  * argument into the matching level within that range.
282                  */
283                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
284                                     brightness / (LED_FULL / 6), 0);
285         }
286 }
287
288 static int rt61pci_blink_set(struct led_classdev *led_cdev,
289                              unsigned long *delay_on,
290                              unsigned long *delay_off)
291 {
292         struct rt2x00_led *led =
293             container_of(led_cdev, struct rt2x00_led, led_dev);
294         u32 reg;
295
296         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
297         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
298         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
299         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
300
301         return 0;
302 }
303
304 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
305                              struct rt2x00_led *led,
306                              enum led_type type)
307 {
308         led->rt2x00dev = rt2x00dev;
309         led->type = type;
310         led->led_dev.brightness_set = rt61pci_brightness_set;
311         led->led_dev.blink_set = rt61pci_blink_set;
312         led->flags = LED_INITIALIZED;
313 }
314 #endif /* CONFIG_RT2X00_LIB_LEDS */
315
316 /*
317  * Configuration handlers.
318  */
319 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
320                                      struct rt2x00lib_crypto *crypto,
321                                      struct ieee80211_key_conf *key)
322 {
323         struct hw_key_entry key_entry;
324         struct rt2x00_field32 field;
325         u32 mask;
326         u32 reg;
327
328         if (crypto->cmd == SET_KEY) {
329                 /*
330                  * rt2x00lib can't determine the correct free
331                  * key_idx for shared keys. We have 1 register
332                  * with key valid bits. The goal is simple, read
333                  * the register, if that is full we have no slots
334                  * left.
335                  * Note that each BSS is allowed to have up to 4
336                  * shared keys, so put a mask over the allowed
337                  * entries.
338                  */
339                 mask = (0xf << crypto->bssidx);
340
341                 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
342                 reg &= mask;
343
344                 if (reg && reg == mask)
345                         return -ENOSPC;
346
347                 key->hw_key_idx += reg ? ffz(reg) : 0;
348
349                 /*
350                  * Upload key to hardware
351                  */
352                 memcpy(key_entry.key, crypto->key,
353                        sizeof(key_entry.key));
354                 memcpy(key_entry.tx_mic, crypto->tx_mic,
355                        sizeof(key_entry.tx_mic));
356                 memcpy(key_entry.rx_mic, crypto->rx_mic,
357                        sizeof(key_entry.rx_mic));
358
359                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
360                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
361                                               &key_entry, sizeof(key_entry));
362
363                 /*
364                  * The cipher types are stored over 2 registers.
365                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
366                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
367                  * Using the correct defines correctly will cause overhead,
368                  * so just calculate the correct offset.
369                  */
370                 if (key->hw_key_idx < 8) {
371                         field.bit_offset = (3 * key->hw_key_idx);
372                         field.bit_mask = 0x7 << field.bit_offset;
373
374                         rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
375                         rt2x00_set_field32(&reg, field, crypto->cipher);
376                         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
377                 } else {
378                         field.bit_offset = (3 * (key->hw_key_idx - 8));
379                         field.bit_mask = 0x7 << field.bit_offset;
380
381                         rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
382                         rt2x00_set_field32(&reg, field, crypto->cipher);
383                         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
384                 }
385
386                 /*
387                  * The driver does not support the IV/EIV generation
388                  * in hardware. However it doesn't support the IV/EIV
389                  * inside the ieee80211 frame either, but requires it
390                  * to be provided separately for the descriptor.
391                  * rt2x00lib will cut the IV/EIV data out of all frames
392                  * given to us by mac80211, but we must tell mac80211
393                  * to generate the IV/EIV data.
394                  */
395                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
396         }
397
398         /*
399          * SEC_CSR0 contains only single-bit fields to indicate
400          * a particular key is valid. Because using the FIELD32()
401          * defines directly will cause a lot of overhead, we use
402          * a calculation to determine the correct bit directly.
403          */
404         mask = 1 << key->hw_key_idx;
405
406         rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
407         if (crypto->cmd == SET_KEY)
408                 reg |= mask;
409         else if (crypto->cmd == DISABLE_KEY)
410                 reg &= ~mask;
411         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
412
413         return 0;
414 }
415
416 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
417                                        struct rt2x00lib_crypto *crypto,
418                                        struct ieee80211_key_conf *key)
419 {
420         struct hw_pairwise_ta_entry addr_entry;
421         struct hw_key_entry key_entry;
422         u32 mask;
423         u32 reg;
424
425         if (crypto->cmd == SET_KEY) {
426                 /*
427                  * rt2x00lib can't determine the correct free
428                  * key_idx for pairwise keys. We have 2 registers
429                  * with key valid bits. The goal is simple: read
430                  * the first register. If that is full, move to
431                  * the next register.
432                  * When both registers are full, we drop the key.
433                  * Otherwise, we use the first invalid entry.
434                  */
435                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
436                 if (reg && reg == ~0) {
437                         key->hw_key_idx = 32;
438                         rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
439                         if (reg && reg == ~0)
440                                 return -ENOSPC;
441                 }
442
443                 key->hw_key_idx += reg ? ffz(reg) : 0;
444
445                 /*
446                  * Upload key to hardware
447                  */
448                 memcpy(key_entry.key, crypto->key,
449                        sizeof(key_entry.key));
450                 memcpy(key_entry.tx_mic, crypto->tx_mic,
451                        sizeof(key_entry.tx_mic));
452                 memcpy(key_entry.rx_mic, crypto->rx_mic,
453                        sizeof(key_entry.rx_mic));
454
455                 memset(&addr_entry, 0, sizeof(addr_entry));
456                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
457                 addr_entry.cipher = crypto->cipher;
458
459                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
460                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
461                                               &key_entry, sizeof(key_entry));
462
463                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
464                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
465                                               &addr_entry, sizeof(addr_entry));
466
467                 /*
468                  * Enable pairwise lookup table for given BSS idx.
469                  * Without this, received frames will not be decrypted
470                  * by the hardware.
471                  */
472                 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
473                 reg |= (1 << crypto->bssidx);
474                 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
475
476                 /*
477                  * The driver does not support the IV/EIV generation
478                  * in hardware. However it doesn't support the IV/EIV
479                  * inside the ieee80211 frame either, but requires it
480                  * to be provided separately for the descriptor.
481                  * rt2x00lib will cut the IV/EIV data out of all frames
482                  * given to us by mac80211, but we must tell mac80211
483                  * to generate the IV/EIV data.
484                  */
485                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
486         }
487
488         /*
489          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
490          * a particular key is valid. Because using the FIELD32()
491          * defines directly will cause a lot of overhead, we use
492          * a calculation to determine the correct bit directly.
493          */
494         if (key->hw_key_idx < 32) {
495                 mask = 1 << key->hw_key_idx;
496
497                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
498                 if (crypto->cmd == SET_KEY)
499                         reg |= mask;
500                 else if (crypto->cmd == DISABLE_KEY)
501                         reg &= ~mask;
502                 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
503         } else {
504                 mask = 1 << (key->hw_key_idx - 32);
505
506                 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
507                 if (crypto->cmd == SET_KEY)
508                         reg |= mask;
509                 else if (crypto->cmd == DISABLE_KEY)
510                         reg &= ~mask;
511                 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
512         }
513
514         return 0;
515 }
516
517 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
518                                   const unsigned int filter_flags)
519 {
520         u32 reg;
521
522         /*
523          * Start configuration steps.
524          * Note that the version error will always be dropped
525          * and broadcast frames will always be accepted since
526          * there is no filter for it at this time.
527          */
528         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
529         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
530                            !(filter_flags & FIF_FCSFAIL));
531         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
532                            !(filter_flags & FIF_PLCPFAIL));
533         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
534                            !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
535         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
536                            !(filter_flags & FIF_PROMISC_IN_BSS));
537         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
538                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
539                            !rt2x00dev->intf_ap_count);
540         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
541         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
542                            !(filter_flags & FIF_ALLMULTI));
543         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
544         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
545                            !(filter_flags & FIF_CONTROL));
546         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
547 }
548
549 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
550                                 struct rt2x00_intf *intf,
551                                 struct rt2x00intf_conf *conf,
552                                 const unsigned int flags)
553 {
554         unsigned int beacon_base;
555         u32 reg;
556
557         if (flags & CONFIG_UPDATE_TYPE) {
558                 /*
559                  * Clear current synchronisation setup.
560                  * For the Beacon base registers, we only need to clear
561                  * the first byte since that byte contains the VALID and OWNER
562                  * bits which (when set to 0) will invalidate the entire beacon.
563                  */
564                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
565                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
566
567                 /*
568                  * Enable synchronisation.
569                  */
570                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
571                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
572                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
573                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
574                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
575         }
576
577         if (flags & CONFIG_UPDATE_MAC) {
578                 reg = le32_to_cpu(conf->mac[1]);
579                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
580                 conf->mac[1] = cpu_to_le32(reg);
581
582                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
583                                               conf->mac, sizeof(conf->mac));
584         }
585
586         if (flags & CONFIG_UPDATE_BSSID) {
587                 reg = le32_to_cpu(conf->bssid[1]);
588                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
589                 conf->bssid[1] = cpu_to_le32(reg);
590
591                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
592                                               conf->bssid, sizeof(conf->bssid));
593         }
594 }
595
596 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
597                                struct rt2x00lib_erp *erp,
598                                u32 changed)
599 {
600         u32 reg;
601
602         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
603         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
604         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
605         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
606
607         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
608                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
609                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
610                 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
611                                    !!erp->short_preamble);
612                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
613         }
614
615         if (changed & BSS_CHANGED_BASIC_RATES)
616                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5,
617                                          erp->basic_rates);
618
619         if (changed & BSS_CHANGED_BEACON_INT) {
620                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
621                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
622                                    erp->beacon_int * 16);
623                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
624         }
625
626         if (changed & BSS_CHANGED_ERP_SLOT) {
627                 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
628                 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
629                 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
630
631                 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
632                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
633                 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
634                 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
635                 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
636         }
637 }
638
639 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
640                                       struct antenna_setup *ant)
641 {
642         u8 r3;
643         u8 r4;
644         u8 r77;
645
646         rt61pci_bbp_read(rt2x00dev, 3, &r3);
647         rt61pci_bbp_read(rt2x00dev, 4, &r4);
648         rt61pci_bbp_read(rt2x00dev, 77, &r77);
649
650         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325));
651
652         /*
653          * Configure the RX antenna.
654          */
655         switch (ant->rx) {
656         case ANTENNA_HW_DIVERSITY:
657                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
658                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
659                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
660                 break;
661         case ANTENNA_A:
662                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
663                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
664                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
665                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
666                 else
667                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
668                 break;
669         case ANTENNA_B:
670         default:
671                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
672                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
673                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
674                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
675                 else
676                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
677                 break;
678         }
679
680         rt61pci_bbp_write(rt2x00dev, 77, r77);
681         rt61pci_bbp_write(rt2x00dev, 3, r3);
682         rt61pci_bbp_write(rt2x00dev, 4, r4);
683 }
684
685 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
686                                       struct antenna_setup *ant)
687 {
688         u8 r3;
689         u8 r4;
690         u8 r77;
691
692         rt61pci_bbp_read(rt2x00dev, 3, &r3);
693         rt61pci_bbp_read(rt2x00dev, 4, &r4);
694         rt61pci_bbp_read(rt2x00dev, 77, &r77);
695
696         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529));
697         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
698                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
699
700         /*
701          * Configure the RX antenna.
702          */
703         switch (ant->rx) {
704         case ANTENNA_HW_DIVERSITY:
705                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
706                 break;
707         case ANTENNA_A:
708                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
709                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
710                 break;
711         case ANTENNA_B:
712         default:
713                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
714                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
715                 break;
716         }
717
718         rt61pci_bbp_write(rt2x00dev, 77, r77);
719         rt61pci_bbp_write(rt2x00dev, 3, r3);
720         rt61pci_bbp_write(rt2x00dev, 4, r4);
721 }
722
723 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
724                                            const int p1, const int p2)
725 {
726         u32 reg;
727
728         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
729
730         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
731         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
732
733         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
734         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
735
736         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
737 }
738
739 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
740                                         struct antenna_setup *ant)
741 {
742         u8 r3;
743         u8 r4;
744         u8 r77;
745
746         rt61pci_bbp_read(rt2x00dev, 3, &r3);
747         rt61pci_bbp_read(rt2x00dev, 4, &r4);
748         rt61pci_bbp_read(rt2x00dev, 77, &r77);
749
750         /*
751          * Configure the RX antenna.
752          */
753         switch (ant->rx) {
754         case ANTENNA_A:
755                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
756                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
757                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
758                 break;
759         case ANTENNA_HW_DIVERSITY:
760                 /*
761                  * FIXME: Antenna selection for the rf 2529 is very confusing
762                  * in the legacy driver. Just default to antenna B until the
763                  * legacy code can be properly translated into rt2x00 code.
764                  */
765         case ANTENNA_B:
766         default:
767                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
768                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
769                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
770                 break;
771         }
772
773         rt61pci_bbp_write(rt2x00dev, 77, r77);
774         rt61pci_bbp_write(rt2x00dev, 3, r3);
775         rt61pci_bbp_write(rt2x00dev, 4, r4);
776 }
777
778 struct antenna_sel {
779         u8 word;
780         /*
781          * value[0] -> non-LNA
782          * value[1] -> LNA
783          */
784         u8 value[2];
785 };
786
787 static const struct antenna_sel antenna_sel_a[] = {
788         { 96,  { 0x58, 0x78 } },
789         { 104, { 0x38, 0x48 } },
790         { 75,  { 0xfe, 0x80 } },
791         { 86,  { 0xfe, 0x80 } },
792         { 88,  { 0xfe, 0x80 } },
793         { 35,  { 0x60, 0x60 } },
794         { 97,  { 0x58, 0x58 } },
795         { 98,  { 0x58, 0x58 } },
796 };
797
798 static const struct antenna_sel antenna_sel_bg[] = {
799         { 96,  { 0x48, 0x68 } },
800         { 104, { 0x2c, 0x3c } },
801         { 75,  { 0xfe, 0x80 } },
802         { 86,  { 0xfe, 0x80 } },
803         { 88,  { 0xfe, 0x80 } },
804         { 35,  { 0x50, 0x50 } },
805         { 97,  { 0x48, 0x48 } },
806         { 98,  { 0x48, 0x48 } },
807 };
808
809 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
810                                struct antenna_setup *ant)
811 {
812         const struct antenna_sel *sel;
813         unsigned int lna;
814         unsigned int i;
815         u32 reg;
816
817         /*
818          * We should never come here because rt2x00lib is supposed
819          * to catch this and send us the correct antenna explicitely.
820          */
821         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
822                ant->tx == ANTENNA_SW_DIVERSITY);
823
824         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
825                 sel = antenna_sel_a;
826                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
827         } else {
828                 sel = antenna_sel_bg;
829                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
830         }
831
832         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
833                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
834
835         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
836
837         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
838                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
839         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
840                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
841
842         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
843
844         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325))
845                 rt61pci_config_antenna_5x(rt2x00dev, ant);
846         else if (rt2x00_rf(rt2x00dev, RF2527))
847                 rt61pci_config_antenna_2x(rt2x00dev, ant);
848         else if (rt2x00_rf(rt2x00dev, RF2529)) {
849                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
850                         rt61pci_config_antenna_2x(rt2x00dev, ant);
851                 else
852                         rt61pci_config_antenna_2529(rt2x00dev, ant);
853         }
854 }
855
856 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
857                                     struct rt2x00lib_conf *libconf)
858 {
859         u16 eeprom;
860         short lna_gain = 0;
861
862         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
863                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
864                         lna_gain += 14;
865
866                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
867                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
868         } else {
869                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
870                         lna_gain += 14;
871
872                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
873                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
874         }
875
876         rt2x00dev->lna_gain = lna_gain;
877 }
878
879 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
880                                    struct rf_channel *rf, const int txpower)
881 {
882         u8 r3;
883         u8 r94;
884         u8 smart;
885
886         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
887         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
888
889         smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
890
891         rt61pci_bbp_read(rt2x00dev, 3, &r3);
892         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
893         rt61pci_bbp_write(rt2x00dev, 3, r3);
894
895         r94 = 6;
896         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
897                 r94 += txpower - MAX_TXPOWER;
898         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
899                 r94 += txpower;
900         rt61pci_bbp_write(rt2x00dev, 94, r94);
901
902         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
903         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
904         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
905         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
906
907         udelay(200);
908
909         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
910         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
911         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
912         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
913
914         udelay(200);
915
916         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
917         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
918         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
919         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
920
921         msleep(1);
922 }
923
924 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
925                                    const int txpower)
926 {
927         struct rf_channel rf;
928
929         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
930         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
931         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
932         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
933
934         rt61pci_config_channel(rt2x00dev, &rf, txpower);
935 }
936
937 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
938                                     struct rt2x00lib_conf *libconf)
939 {
940         u32 reg;
941
942         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
943         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1);
944         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_RATE_STEP, 0);
945         rt2x00_set_field32(&reg, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0);
946         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
947                            libconf->conf->long_frame_max_tx_count);
948         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
949                            libconf->conf->short_frame_max_tx_count);
950         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
951 }
952
953 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
954                                 struct rt2x00lib_conf *libconf)
955 {
956         enum dev_state state =
957             (libconf->conf->flags & IEEE80211_CONF_PS) ?
958                 STATE_SLEEP : STATE_AWAKE;
959         u32 reg;
960
961         if (state == STATE_SLEEP) {
962                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
963                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
964                                    rt2x00dev->beacon_int - 10);
965                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
966                                    libconf->conf->listen_interval - 1);
967                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
968
969                 /* We must first disable autowake before it can be enabled */
970                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
971                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
972
973                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
974                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
975
976                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
977                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
978                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
979
980                 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
981         } else {
982                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
983                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
984                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
985                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
986                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
987                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
988
989                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
990                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
991                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
992
993                 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
994         }
995 }
996
997 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
998                            struct rt2x00lib_conf *libconf,
999                            const unsigned int flags)
1000 {
1001         /* Always recalculate LNA gain before changing configuration */
1002         rt61pci_config_lna_gain(rt2x00dev, libconf);
1003
1004         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1005                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
1006                                        libconf->conf->power_level);
1007         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
1008             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
1009                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1010         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1011                 rt61pci_config_retry_limit(rt2x00dev, libconf);
1012         if (flags & IEEE80211_CONF_CHANGE_PS)
1013                 rt61pci_config_ps(rt2x00dev, libconf);
1014 }
1015
1016 /*
1017  * Link tuning
1018  */
1019 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1020                                struct link_qual *qual)
1021 {
1022         u32 reg;
1023
1024         /*
1025          * Update FCS error count from register.
1026          */
1027         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1028         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1029
1030         /*
1031          * Update False CCA count from register.
1032          */
1033         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1034         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1035 }
1036
1037 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1038                                    struct link_qual *qual, u8 vgc_level)
1039 {
1040         if (qual->vgc_level != vgc_level) {
1041                 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1042                 qual->vgc_level = vgc_level;
1043                 qual->vgc_level_reg = vgc_level;
1044         }
1045 }
1046
1047 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1048                                 struct link_qual *qual)
1049 {
1050         rt61pci_set_vgc(rt2x00dev, qual, 0x20);
1051 }
1052
1053 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1054                                struct link_qual *qual, const u32 count)
1055 {
1056         u8 up_bound;
1057         u8 low_bound;
1058
1059         /*
1060          * Determine r17 bounds.
1061          */
1062         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1063                 low_bound = 0x28;
1064                 up_bound = 0x48;
1065                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1066                         low_bound += 0x10;
1067                         up_bound += 0x10;
1068                 }
1069         } else {
1070                 low_bound = 0x20;
1071                 up_bound = 0x40;
1072                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1073                         low_bound += 0x10;
1074                         up_bound += 0x10;
1075                 }
1076         }
1077
1078         /*
1079          * If we are not associated, we should go straight to the
1080          * dynamic CCA tuning.
1081          */
1082         if (!rt2x00dev->intf_associated)
1083                 goto dynamic_cca_tune;
1084
1085         /*
1086          * Special big-R17 for very short distance
1087          */
1088         if (qual->rssi >= -35) {
1089                 rt61pci_set_vgc(rt2x00dev, qual, 0x60);
1090                 return;
1091         }
1092
1093         /*
1094          * Special big-R17 for short distance
1095          */
1096         if (qual->rssi >= -58) {
1097                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1098                 return;
1099         }
1100
1101         /*
1102          * Special big-R17 for middle-short distance
1103          */
1104         if (qual->rssi >= -66) {
1105                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10);
1106                 return;
1107         }
1108
1109         /*
1110          * Special mid-R17 for middle distance
1111          */
1112         if (qual->rssi >= -74) {
1113                 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08);
1114                 return;
1115         }
1116
1117         /*
1118          * Special case: Change up_bound based on the rssi.
1119          * Lower up_bound when rssi is weaker then -74 dBm.
1120          */
1121         up_bound -= 2 * (-74 - qual->rssi);
1122         if (low_bound > up_bound)
1123                 up_bound = low_bound;
1124
1125         if (qual->vgc_level > up_bound) {
1126                 rt61pci_set_vgc(rt2x00dev, qual, up_bound);
1127                 return;
1128         }
1129
1130 dynamic_cca_tune:
1131
1132         /*
1133          * r17 does not yet exceed upper limit, continue and base
1134          * the r17 tuning on the false CCA count.
1135          */
1136         if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1137                 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
1138         else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1139                 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
1140 }
1141
1142 /*
1143  * Queue handlers.
1144  */
1145 static void rt61pci_start_queue(struct data_queue *queue)
1146 {
1147         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1148         u32 reg;
1149
1150         switch (queue->qid) {
1151         case QID_RX:
1152                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1153                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1154                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1155                 break;
1156         case QID_BEACON:
1157                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1158                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1159                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1160                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1161                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1162                 break;
1163         default:
1164                 break;
1165         }
1166 }
1167
1168 static void rt61pci_kick_queue(struct data_queue *queue)
1169 {
1170         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1171         u32 reg;
1172
1173         switch (queue->qid) {
1174         case QID_AC_BE:
1175                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1176                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
1177                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1178                 break;
1179         case QID_AC_BK:
1180                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1181                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
1182                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1183                 break;
1184         case QID_AC_VI:
1185                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1186                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
1187                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1188                 break;
1189         case QID_AC_VO:
1190                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1191                 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
1192                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1193                 break;
1194         default:
1195                 break;
1196         }
1197 }
1198
1199 static void rt61pci_stop_queue(struct data_queue *queue)
1200 {
1201         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
1202         u32 reg;
1203
1204         switch (queue->qid) {
1205         case QID_AC_BE:
1206                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1207                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1208                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1209                 break;
1210         case QID_AC_BK:
1211                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1212                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1213                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1214                 break;
1215         case QID_AC_VI:
1216                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1217                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1218                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1219                 break;
1220         case QID_AC_VO:
1221                 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1222                 rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1223                 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1224                 break;
1225         case QID_RX:
1226                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1227                 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
1228                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1229                 break;
1230         case QID_BEACON:
1231                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1232                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1233                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1234                 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1235                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1236                 break;
1237         default:
1238                 break;
1239         }
1240 }
1241
1242 /*
1243  * Firmware functions
1244  */
1245 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1246 {
1247         u16 chip;
1248         char *fw_name;
1249
1250         pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip);
1251         switch (chip) {
1252         case RT2561_PCI_ID:
1253                 fw_name = FIRMWARE_RT2561;
1254                 break;
1255         case RT2561s_PCI_ID:
1256                 fw_name = FIRMWARE_RT2561s;
1257                 break;
1258         case RT2661_PCI_ID:
1259                 fw_name = FIRMWARE_RT2661;
1260                 break;
1261         default:
1262                 fw_name = NULL;
1263                 break;
1264         }
1265
1266         return fw_name;
1267 }
1268
1269 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1270                                   const u8 *data, const size_t len)
1271 {
1272         u16 fw_crc;
1273         u16 crc;
1274
1275         /*
1276          * Only support 8kb firmware files.
1277          */
1278         if (len != 8192)
1279                 return FW_BAD_LENGTH;
1280
1281         /*
1282          * The last 2 bytes in the firmware array are the crc checksum itself.
1283          * This means that we should never pass those 2 bytes to the crc
1284          * algorithm.
1285          */
1286         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1287
1288         /*
1289          * Use the crc itu-t algorithm.
1290          */
1291         crc = crc_itu_t(0, data, len - 2);
1292         crc = crc_itu_t_byte(crc, 0);
1293         crc = crc_itu_t_byte(crc, 0);
1294
1295         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1296 }
1297
1298 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1299                                  const u8 *data, const size_t len)
1300 {
1301         int i;
1302         u32 reg;
1303
1304         /*
1305          * Wait for stable hardware.
1306          */
1307         for (i = 0; i < 100; i++) {
1308                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1309                 if (reg)
1310                         break;
1311                 msleep(1);
1312         }
1313
1314         if (!reg) {
1315                 ERROR(rt2x00dev, "Unstable hardware.\n");
1316                 return -EBUSY;
1317         }
1318
1319         /*
1320          * Prepare MCU and mailbox for firmware loading.
1321          */
1322         reg = 0;
1323         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1324         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1325         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1326         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1327         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1328
1329         /*
1330          * Write firmware to device.
1331          */
1332         reg = 0;
1333         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1334         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1335         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1336
1337         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1338                                       data, len);
1339
1340         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1341         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1342
1343         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1344         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1345
1346         for (i = 0; i < 100; i++) {
1347                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1348                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1349                         break;
1350                 msleep(1);
1351         }
1352
1353         if (i == 100) {
1354                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1355                 return -EBUSY;
1356         }
1357
1358         /*
1359          * Hardware needs another millisecond before it is ready.
1360          */
1361         msleep(1);
1362
1363         /*
1364          * Reset MAC and BBP registers.
1365          */
1366         reg = 0;
1367         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1368         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1369         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1370
1371         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1372         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1373         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1374         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1375
1376         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1377         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1378         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1379
1380         return 0;
1381 }
1382
1383 /*
1384  * Initialization functions.
1385  */
1386 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1387 {
1388         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1389         u32 word;
1390
1391         if (entry->queue->qid == QID_RX) {
1392                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1393
1394                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1395         } else {
1396                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1397
1398                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1399                         rt2x00_get_field32(word, TXD_W0_VALID));
1400         }
1401 }
1402
1403 static void rt61pci_clear_entry(struct queue_entry *entry)
1404 {
1405         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1406         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1407         u32 word;
1408
1409         if (entry->queue->qid == QID_RX) {
1410                 rt2x00_desc_read(entry_priv->desc, 5, &word);
1411                 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1412                                    skbdesc->skb_dma);
1413                 rt2x00_desc_write(entry_priv->desc, 5, word);
1414
1415                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1416                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1417                 rt2x00_desc_write(entry_priv->desc, 0, word);
1418         } else {
1419                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1420                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1421                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1422                 rt2x00_desc_write(entry_priv->desc, 0, word);
1423         }
1424 }
1425
1426 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1427 {
1428         struct queue_entry_priv_pci *entry_priv;
1429         u32 reg;
1430
1431         /*
1432          * Initialize registers.
1433          */
1434         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1435         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1436                            rt2x00dev->tx[0].limit);
1437         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1438                            rt2x00dev->tx[1].limit);
1439         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1440                            rt2x00dev->tx[2].limit);
1441         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1442                            rt2x00dev->tx[3].limit);
1443         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1444
1445         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1446         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1447                            rt2x00dev->tx[0].desc_size / 4);
1448         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1449
1450         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1451         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1452         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1453                            entry_priv->desc_dma);
1454         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1455
1456         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1457         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1458         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1459                            entry_priv->desc_dma);
1460         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1461
1462         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1463         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1464         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1465                            entry_priv->desc_dma);
1466         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1467
1468         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1469         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1470         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1471                            entry_priv->desc_dma);
1472         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1473
1474         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1475         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1476         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1477                            rt2x00dev->rx->desc_size / 4);
1478         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1479         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1480
1481         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1482         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1483         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1484                            entry_priv->desc_dma);
1485         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1486
1487         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1488         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1489         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1490         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1491         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1492         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1493
1494         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1495         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1496         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1497         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1498         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1499         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1500
1501         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1502         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1503         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1504
1505         return 0;
1506 }
1507
1508 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1509 {
1510         u32 reg;
1511
1512         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1513         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1514         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1515         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1516         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1517
1518         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1519         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1520         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1521         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1522         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1523         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1524         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1525         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1526         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1527         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1528
1529         /*
1530          * CCK TXD BBP registers
1531          */
1532         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1533         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1534         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1535         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1536         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1537         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1538         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1539         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1540         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1541         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1542
1543         /*
1544          * OFDM TXD BBP registers
1545          */
1546         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1547         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1548         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1549         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1550         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1551         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1552         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1553         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1554
1555         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1556         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1557         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1558         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1559         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1560         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1561
1562         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1563         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1564         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1565         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1566         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1567         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1568
1569         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1570         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1571         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1572         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1573         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1574         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1575         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1576         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1577
1578         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1579
1580         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1581
1582         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1583         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1584         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1585
1586         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1587
1588         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1589                 return -EBUSY;
1590
1591         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1592
1593         /*
1594          * Invalidate all Shared Keys (SEC_CSR0),
1595          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1596          */
1597         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1598         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1599         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1600
1601         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1602         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1603         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1604         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1605
1606         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1607
1608         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1609
1610         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1611
1612         /*
1613          * Clear all beacons
1614          * For the Beacon base registers we only need to clear
1615          * the first byte since that byte contains the VALID and OWNER
1616          * bits which (when set to 0) will invalidate the entire beacon.
1617          */
1618         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1619         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1620         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1621         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1622
1623         /*
1624          * We must clear the error counters.
1625          * These registers are cleared on read,
1626          * so we may pass a useless variable to store the value.
1627          */
1628         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1629         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1630         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1631
1632         /*
1633          * Reset MAC and BBP registers.
1634          */
1635         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1636         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1637         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1638         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1639
1640         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1641         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1642         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1643         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1644
1645         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1646         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1647         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1648
1649         return 0;
1650 }
1651
1652 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1653 {
1654         unsigned int i;
1655         u8 value;
1656
1657         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1658                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1659                 if ((value != 0xff) && (value != 0x00))
1660                         return 0;
1661                 udelay(REGISTER_BUSY_DELAY);
1662         }
1663
1664         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1665         return -EACCES;
1666 }
1667
1668 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1669 {
1670         unsigned int i;
1671         u16 eeprom;
1672         u8 reg_id;
1673         u8 value;
1674
1675         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1676                 return -EACCES;
1677
1678         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1679         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1680         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1681         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1682         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1683         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1684         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1685         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1686         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1687         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1688         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1689         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1690         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1691         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1692         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1693         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1694         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1695         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1696         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1697         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1698         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1699         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1700         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1701         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1702
1703         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1704                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1705
1706                 if (eeprom != 0xffff && eeprom != 0x0000) {
1707                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1708                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1709                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1710                 }
1711         }
1712
1713         return 0;
1714 }
1715
1716 /*
1717  * Device state switch handlers.
1718  */
1719 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1720                                enum dev_state state)
1721 {
1722         int mask = (state == STATE_RADIO_IRQ_OFF) ||
1723                    (state == STATE_RADIO_IRQ_OFF_ISR);
1724         u32 reg;
1725
1726         /*
1727          * When interrupts are being enabled, the interrupt registers
1728          * should clear the register to assure a clean state.
1729          */
1730         if (state == STATE_RADIO_IRQ_ON) {
1731                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1732                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1733
1734                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1735                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1736         }
1737
1738         /*
1739          * Only toggle the interrupts bits we are going to use.
1740          * Non-checked interrupt bits are disabled by default.
1741          */
1742         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1743         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1744         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1745         rt2x00_set_field32(&reg, INT_MASK_CSR_BEACON_DONE, mask);
1746         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1747         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1748         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1749
1750         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1751         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1752         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1753         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1754         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1755         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1756         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1757         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1758         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1759         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
1760         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1761 }
1762
1763 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1764 {
1765         u32 reg;
1766
1767         /*
1768          * Initialize all registers.
1769          */
1770         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1771                      rt61pci_init_registers(rt2x00dev) ||
1772                      rt61pci_init_bbp(rt2x00dev)))
1773                 return -EIO;
1774
1775         /*
1776          * Enable RX.
1777          */
1778         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1779         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1780         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1781
1782         return 0;
1783 }
1784
1785 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1786 {
1787         /*
1788          * Disable power
1789          */
1790         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1791 }
1792
1793 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1794 {
1795         u32 reg, reg2;
1796         unsigned int i;
1797         char put_to_sleep;
1798
1799         put_to_sleep = (state != STATE_AWAKE);
1800
1801         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1802         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1803         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1804         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1805
1806         /*
1807          * Device is not guaranteed to be in the requested state yet.
1808          * We must wait until the register indicates that the
1809          * device has entered the correct state.
1810          */
1811         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1812                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg2);
1813                 state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE);
1814                 if (state == !put_to_sleep)
1815                         return 0;
1816                 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1817                 msleep(10);
1818         }
1819
1820         return -EBUSY;
1821 }
1822
1823 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1824                                     enum dev_state state)
1825 {
1826         int retval = 0;
1827
1828         switch (state) {
1829         case STATE_RADIO_ON:
1830                 retval = rt61pci_enable_radio(rt2x00dev);
1831                 break;
1832         case STATE_RADIO_OFF:
1833                 rt61pci_disable_radio(rt2x00dev);
1834                 break;
1835         case STATE_RADIO_RX_ON:
1836                 rt61pci_start_queue(rt2x00dev->rx);
1837                 break;
1838         case STATE_RADIO_RX_OFF:
1839                 rt61pci_stop_queue(rt2x00dev->rx);
1840                 break;
1841         case STATE_RADIO_IRQ_ON:
1842         case STATE_RADIO_IRQ_ON_ISR:
1843         case STATE_RADIO_IRQ_OFF:
1844         case STATE_RADIO_IRQ_OFF_ISR:
1845                 rt61pci_toggle_irq(rt2x00dev, state);
1846                 break;
1847         case STATE_DEEP_SLEEP:
1848         case STATE_SLEEP:
1849         case STATE_STANDBY:
1850         case STATE_AWAKE:
1851                 retval = rt61pci_set_state(rt2x00dev, state);
1852                 break;
1853         default:
1854                 retval = -ENOTSUPP;
1855                 break;
1856         }
1857
1858         if (unlikely(retval))
1859                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1860                       state, retval);
1861
1862         return retval;
1863 }
1864
1865 /*
1866  * TX descriptor initialization
1867  */
1868 static void rt61pci_write_tx_desc(struct queue_entry *entry,
1869                                   struct txentry_desc *txdesc)
1870 {
1871         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1872         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1873         __le32 *txd = entry_priv->desc;
1874         u32 word;
1875
1876         /*
1877          * Start writing the descriptor words.
1878          */
1879         rt2x00_desc_read(txd, 1, &word);
1880         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
1881         rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
1882         rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
1883         rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
1884         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1885         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1886                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1887         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1888         rt2x00_desc_write(txd, 1, word);
1889
1890         rt2x00_desc_read(txd, 2, &word);
1891         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1892         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1893         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1894         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1895         rt2x00_desc_write(txd, 2, word);
1896
1897         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1898                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1899                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1900         }
1901
1902         rt2x00_desc_read(txd, 5, &word);
1903         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1904         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1905                            skbdesc->entry->entry_idx);
1906         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1907                            TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power));
1908         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1909         rt2x00_desc_write(txd, 5, word);
1910
1911         if (entry->queue->qid != QID_BEACON) {
1912                 rt2x00_desc_read(txd, 6, &word);
1913                 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1914                                    skbdesc->skb_dma);
1915                 rt2x00_desc_write(txd, 6, word);
1916
1917                 rt2x00_desc_read(txd, 11, &word);
1918                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1919                                    txdesc->length);
1920                 rt2x00_desc_write(txd, 11, word);
1921         }
1922
1923         /*
1924          * Writing TXD word 0 must the last to prevent a race condition with
1925          * the device, whereby the device may take hold of the TXD before we
1926          * finished updating it.
1927          */
1928         rt2x00_desc_read(txd, 0, &word);
1929         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1930         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1931         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1932                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1933         rt2x00_set_field32(&word, TXD_W0_ACK,
1934                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1935         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1936                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1937         rt2x00_set_field32(&word, TXD_W0_OFDM,
1938                            (txdesc->rate_mode == RATE_MODE_OFDM));
1939         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1940         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1941                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1942         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1943                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1944         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1945                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1946         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1947         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1948         rt2x00_set_field32(&word, TXD_W0_BURST,
1949                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1950         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1951         rt2x00_desc_write(txd, 0, word);
1952
1953         /*
1954          * Register descriptor details in skb frame descriptor.
1955          */
1956         skbdesc->desc = txd;
1957         skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
1958                             TXD_DESC_SIZE;
1959 }
1960
1961 /*
1962  * TX data initialization
1963  */
1964 static void rt61pci_write_beacon(struct queue_entry *entry,
1965                                  struct txentry_desc *txdesc)
1966 {
1967         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1968         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1969         unsigned int beacon_base;
1970         u32 reg;
1971
1972         /*
1973          * Disable beaconing while we are reloading the beacon data,
1974          * otherwise we might be sending out invalid data.
1975          */
1976         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1977         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1978         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1979
1980         /*
1981          * Write the TX descriptor for the beacon.
1982          */
1983         rt61pci_write_tx_desc(entry, txdesc);
1984
1985         /*
1986          * Dump beacon to userspace through debugfs.
1987          */
1988         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1989
1990         /*
1991          * Write entire beacon with descriptor to register.
1992          */
1993         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1994         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1995                                       entry_priv->desc, TXINFO_SIZE);
1996         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
1997                                       entry->skb->data, entry->skb->len);
1998
1999         /*
2000          * Enable beaconing again.
2001          *
2002          * For Wi-Fi faily generated beacons between participating
2003          * stations. Set TBTT phase adaptive adjustment step to 8us.
2004          */
2005         rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
2006
2007         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
2008         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
2009         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2010         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2011
2012         /*
2013          * Clean up beacon skb.
2014          */
2015         dev_kfree_skb_any(entry->skb);
2016         entry->skb = NULL;
2017 }
2018
2019 /*
2020  * RX control handlers
2021  */
2022 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
2023 {
2024         u8 offset = rt2x00dev->lna_gain;
2025         u8 lna;
2026
2027         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
2028         switch (lna) {
2029         case 3:
2030                 offset += 90;
2031                 break;
2032         case 2:
2033                 offset += 74;
2034                 break;
2035         case 1:
2036                 offset += 64;
2037                 break;
2038         default:
2039                 return 0;
2040         }
2041
2042         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
2043                 if (lna == 3 || lna == 2)
2044                         offset += 10;
2045         }
2046
2047         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
2048 }
2049
2050 static void rt61pci_fill_rxdone(struct queue_entry *entry,
2051                                 struct rxdone_entry_desc *rxdesc)
2052 {
2053         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2054         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2055         u32 word0;
2056         u32 word1;
2057
2058         rt2x00_desc_read(entry_priv->desc, 0, &word0);
2059         rt2x00_desc_read(entry_priv->desc, 1, &word1);
2060
2061         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
2062                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2063
2064         rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
2065         rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
2066
2067         if (rxdesc->cipher != CIPHER_NONE) {
2068                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
2069                 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
2070                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
2071
2072                 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
2073                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
2074
2075                 /*
2076                  * Hardware has stripped IV/EIV data from 802.11 frame during
2077                  * decryption. It has provided the data separately but rt2x00lib
2078                  * should decide if it should be reinserted.
2079                  */
2080                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2081
2082                 /*
2083                  * FIXME: Legacy driver indicates that the frame does
2084                  * contain the Michael Mic. Unfortunately, in rt2x00
2085                  * the MIC seems to be missing completely...
2086                  */
2087                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2088
2089                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2090                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2091                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2092                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2093         }
2094
2095         /*
2096          * Obtain the status about this packet.
2097          * When frame was received with an OFDM bitrate,
2098          * the signal is the PLCP value. If it was received with
2099          * a CCK bitrate the signal is the rate in 100kbit/s.
2100          */
2101         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2102         rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2103         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2104
2105         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2106                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2107         else
2108                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2109         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2110                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2111 }
2112
2113 /*
2114  * Interrupt functions.
2115  */
2116 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2117 {
2118         struct data_queue *queue;
2119         struct queue_entry *entry;
2120         struct queue_entry *entry_done;
2121         struct queue_entry_priv_pci *entry_priv;
2122         struct txdone_entry_desc txdesc;
2123         u32 word;
2124         u32 reg;
2125         int type;
2126         int index;
2127         int i;
2128
2129         /*
2130          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
2131          * at most X times and also stop processing once the TX_STA_FIFO_VALID
2132          * flag is not set anymore.
2133          *
2134          * The legacy drivers use X=TX_RING_SIZE but state in a comment
2135          * that the TX_STA_FIFO stack has a size of 16. We stick to our
2136          * tx ring size for now.
2137          */
2138         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
2139                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2140                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2141                         break;
2142
2143                 /*
2144                  * Skip this entry when it contains an invalid
2145                  * queue identication number.
2146                  */
2147                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2148                 queue = rt2x00queue_get_queue(rt2x00dev, type);
2149                 if (unlikely(!queue))
2150                         continue;
2151
2152                 /*
2153                  * Skip this entry when it contains an invalid
2154                  * index number.
2155                  */
2156                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2157                 if (unlikely(index >= queue->limit))
2158                         continue;
2159
2160                 entry = &queue->entries[index];
2161                 entry_priv = entry->priv_data;
2162                 rt2x00_desc_read(entry_priv->desc, 0, &word);
2163
2164                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2165                     !rt2x00_get_field32(word, TXD_W0_VALID))
2166                         return;
2167
2168                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2169                 while (entry != entry_done) {
2170                         /* Catch up.
2171                          * Just report any entries we missed as failed.
2172                          */
2173                         WARNING(rt2x00dev,
2174                                 "TX status report missed for entry %d\n",
2175                                 entry_done->entry_idx);
2176
2177                         rt2x00lib_txdone_noinfo(entry_done, TXDONE_UNKNOWN);
2178                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2179                 }
2180
2181                 /*
2182                  * Obtain the status about this packet.
2183                  */
2184                 txdesc.flags = 0;
2185                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2186                 case 0: /* Success, maybe with retry */
2187                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2188                         break;
2189                 case 6: /* Failure, excessive retries */
2190                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2191                         /* Don't break, this is a failed frame! */
2192                 default: /* Failure */
2193                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2194                 }
2195                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2196
2197                 /*
2198                  * the frame was retried at least once
2199                  * -> hw used fallback rates
2200                  */
2201                 if (txdesc.retry)
2202                         __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2203
2204                 rt2x00lib_txdone(entry, &txdesc);
2205         }
2206 }
2207
2208 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2209 {
2210         struct ieee80211_conf conf = { .flags = 0 };
2211         struct rt2x00lib_conf libconf = { .conf = &conf };
2212
2213         rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2214 }
2215
2216 static irqreturn_t rt61pci_interrupt_thread(int irq, void *dev_instance)
2217 {
2218         struct rt2x00_dev *rt2x00dev = dev_instance;
2219         u32 reg = rt2x00dev->irqvalue[0];
2220         u32 reg_mcu = rt2x00dev->irqvalue[1];
2221
2222         /*
2223          * Handle interrupts, walk through all bits
2224          * and run the tasks, the bits are checked in order of
2225          * priority.
2226          */
2227
2228         /*
2229          * 1 - Rx ring done interrupt.
2230          */
2231         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2232                 rt2x00pci_rxdone(rt2x00dev);
2233
2234         /*
2235          * 2 - Tx ring done interrupt.
2236          */
2237         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2238                 rt61pci_txdone(rt2x00dev);
2239
2240         /*
2241          * 3 - Handle MCU command done.
2242          */
2243         if (reg_mcu)
2244                 rt2x00pci_register_write(rt2x00dev,
2245                                          M2H_CMD_DONE_CSR, 0xffffffff);
2246
2247         /*
2248          * 4 - MCU Autowakeup interrupt.
2249          */
2250         if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2251                 rt61pci_wakeup(rt2x00dev);
2252
2253         /*
2254          * 5 - Beacon done interrupt.
2255          */
2256         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2257                 rt2x00lib_beacondone(rt2x00dev);
2258
2259         /* Enable interrupts again. */
2260         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2261                                               STATE_RADIO_IRQ_ON_ISR);
2262         return IRQ_HANDLED;
2263 }
2264
2265
2266 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2267 {
2268         struct rt2x00_dev *rt2x00dev = dev_instance;
2269         u32 reg_mcu;
2270         u32 reg;
2271
2272         /*
2273          * Get the interrupt sources & saved to local variable.
2274          * Write register value back to clear pending interrupts.
2275          */
2276         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2277         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2278
2279         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2280         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2281
2282         if (!reg && !reg_mcu)
2283                 return IRQ_NONE;
2284
2285         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2286                 return IRQ_HANDLED;
2287
2288         /* Store irqvalues for use in the interrupt thread. */
2289         rt2x00dev->irqvalue[0] = reg;
2290         rt2x00dev->irqvalue[1] = reg_mcu;
2291
2292         /* Disable interrupts, will be enabled again in the interrupt thread. */
2293         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
2294                                               STATE_RADIO_IRQ_OFF_ISR);
2295         return IRQ_WAKE_THREAD;
2296 }
2297
2298 /*
2299  * Device probe functions.
2300  */
2301 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2302 {
2303         struct eeprom_93cx6 eeprom;
2304         u32 reg;
2305         u16 word;
2306         u8 *mac;
2307         s8 value;
2308
2309         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2310
2311         eeprom.data = rt2x00dev;
2312         eeprom.register_read = rt61pci_eepromregister_read;
2313         eeprom.register_write = rt61pci_eepromregister_write;
2314         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2315             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2316         eeprom.reg_data_in = 0;
2317         eeprom.reg_data_out = 0;
2318         eeprom.reg_data_clock = 0;
2319         eeprom.reg_chip_select = 0;
2320
2321         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2322                                EEPROM_SIZE / sizeof(u16));
2323
2324         /*
2325          * Start validation of the data that has been read.
2326          */
2327         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2328         if (!is_valid_ether_addr(mac)) {
2329                 random_ether_addr(mac);
2330                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2331         }
2332
2333         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2334         if (word == 0xffff) {
2335                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2336                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2337                                    ANTENNA_B);
2338                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2339                                    ANTENNA_B);
2340                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2341                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2342                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2343                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2344                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2345                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2346         }
2347
2348         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2349         if (word == 0xffff) {
2350                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2351                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2352                 rt2x00_set_field16(&word, EEPROM_NIC_RX_FIXED, 0);
2353                 rt2x00_set_field16(&word, EEPROM_NIC_TX_FIXED, 0);
2354                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2355                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2356                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2357                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2358                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2359         }
2360
2361         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2362         if (word == 0xffff) {
2363                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2364                                    LED_MODE_DEFAULT);
2365                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2366                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2367         }
2368
2369         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2370         if (word == 0xffff) {
2371                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2372                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2373                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2374                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2375         }
2376
2377         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2378         if (word == 0xffff) {
2379                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2380                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2381                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2382                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2383         } else {
2384                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2385                 if (value < -10 || value > 10)
2386                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2387                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2388                 if (value < -10 || value > 10)
2389                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2390                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2391         }
2392
2393         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2394         if (word == 0xffff) {
2395                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2396                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2397                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2398                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2399         } else {
2400                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2401                 if (value < -10 || value > 10)
2402                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2403                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2404                 if (value < -10 || value > 10)
2405                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2406                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2407         }
2408
2409         return 0;
2410 }
2411
2412 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2413 {
2414         u32 reg;
2415         u16 value;
2416         u16 eeprom;
2417
2418         /*
2419          * Read EEPROM word for configuration.
2420          */
2421         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2422
2423         /*
2424          * Identify RF chipset.
2425          */
2426         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2427         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2428         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2429                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2430
2431         if (!rt2x00_rf(rt2x00dev, RF5225) &&
2432             !rt2x00_rf(rt2x00dev, RF5325) &&
2433             !rt2x00_rf(rt2x00dev, RF2527) &&
2434             !rt2x00_rf(rt2x00dev, RF2529)) {
2435                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2436                 return -ENODEV;
2437         }
2438
2439         /*
2440          * Determine number of antennas.
2441          */
2442         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2443                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2444
2445         /*
2446          * Identify default antenna configuration.
2447          */
2448         rt2x00dev->default_ant.tx =
2449             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2450         rt2x00dev->default_ant.rx =
2451             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2452
2453         /*
2454          * Read the Frame type.
2455          */
2456         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2457                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2458
2459         /*
2460          * Detect if this device has a hardware controlled radio.
2461          */
2462         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2463                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2464
2465         /*
2466          * Read frequency offset and RF programming sequence.
2467          */
2468         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2469         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2470                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2471
2472         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2473
2474         /*
2475          * Read external LNA informations.
2476          */
2477         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2478
2479         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2480                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2481         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2482                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2483
2484         /*
2485          * When working with a RF2529 chip without double antenna,
2486          * the antenna settings should be gathered from the NIC
2487          * eeprom word.
2488          */
2489         if (rt2x00_rf(rt2x00dev, RF2529) &&
2490             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2491                 rt2x00dev->default_ant.rx =
2492                     ANTENNA_A + rt2x00_get_field16(eeprom, EEPROM_NIC_RX_FIXED);
2493                 rt2x00dev->default_ant.tx =
2494                     ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED);
2495
2496                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2497                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2498                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2499                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2500         }
2501
2502         /*
2503          * Store led settings, for correct led behaviour.
2504          * If the eeprom value is invalid,
2505          * switch to default led mode.
2506          */
2507 #ifdef CONFIG_RT2X00_LIB_LEDS
2508         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2509         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2510
2511         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2512         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2513         if (value == LED_MODE_SIGNAL_STRENGTH)
2514                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2515                                  LED_TYPE_QUALITY);
2516
2517         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2518         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2519                            rt2x00_get_field16(eeprom,
2520                                               EEPROM_LED_POLARITY_GPIO_0));
2521         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2522                            rt2x00_get_field16(eeprom,
2523                                               EEPROM_LED_POLARITY_GPIO_1));
2524         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2525                            rt2x00_get_field16(eeprom,
2526                                               EEPROM_LED_POLARITY_GPIO_2));
2527         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2528                            rt2x00_get_field16(eeprom,
2529                                               EEPROM_LED_POLARITY_GPIO_3));
2530         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2531                            rt2x00_get_field16(eeprom,
2532                                               EEPROM_LED_POLARITY_GPIO_4));
2533         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2534                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2535         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2536                            rt2x00_get_field16(eeprom,
2537                                               EEPROM_LED_POLARITY_RDY_G));
2538         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2539                            rt2x00_get_field16(eeprom,
2540                                               EEPROM_LED_POLARITY_RDY_A));
2541 #endif /* CONFIG_RT2X00_LIB_LEDS */
2542
2543         return 0;
2544 }
2545
2546 /*
2547  * RF value list for RF5225 & RF5325
2548  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2549  */
2550 static const struct rf_channel rf_vals_noseq[] = {
2551         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2552         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2553         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2554         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2555         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2556         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2557         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2558         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2559         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2560         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2561         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2562         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2563         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2564         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2565
2566         /* 802.11 UNI / HyperLan 2 */
2567         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2568         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2569         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2570         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2571         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2572         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2573         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2574         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2575
2576         /* 802.11 HyperLan 2 */
2577         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2578         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2579         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2580         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2581         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2582         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2583         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2584         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2585         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2586         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2587
2588         /* 802.11 UNII */
2589         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2590         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2591         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2592         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2593         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2594         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2595
2596         /* MMAC(Japan)J52 ch 34,38,42,46 */
2597         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2598         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2599         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2600         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2601 };
2602
2603 /*
2604  * RF value list for RF5225 & RF5325
2605  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2606  */
2607 static const struct rf_channel rf_vals_seq[] = {
2608         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2609         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2610         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2611         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2612         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2613         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2614         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2615         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2616         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2617         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2618         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2619         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2620         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2621         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2622
2623         /* 802.11 UNI / HyperLan 2 */
2624         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2625         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2626         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2627         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2628         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2629         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2630         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2631         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2632
2633         /* 802.11 HyperLan 2 */
2634         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2635         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2636         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2637         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2638         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2639         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2640         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2641         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2642         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2643         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2644
2645         /* 802.11 UNII */
2646         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2647         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2648         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2649         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2650         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2651         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2652
2653         /* MMAC(Japan)J52 ch 34,38,42,46 */
2654         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2655         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2656         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2657         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2658 };
2659
2660 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2661 {
2662         struct hw_mode_spec *spec = &rt2x00dev->spec;
2663         struct channel_info *info;
2664         char *tx_power;
2665         unsigned int i;
2666
2667         /*
2668          * Disable powersaving as default.
2669          */
2670         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2671
2672         /*
2673          * Initialize all hw fields.
2674          */
2675         rt2x00dev->hw->flags =
2676             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2677             IEEE80211_HW_SIGNAL_DBM |
2678             IEEE80211_HW_SUPPORTS_PS |
2679             IEEE80211_HW_PS_NULLFUNC_STACK;
2680
2681         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2682         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2683                                 rt2x00_eeprom_addr(rt2x00dev,
2684                                                    EEPROM_MAC_ADDR_0));
2685
2686         /*
2687          * As rt61 has a global fallback table we cannot specify
2688          * more then one tx rate per frame but since the hw will
2689          * try several rates (based on the fallback table) we should
2690          * initialize max_report_rates to the maximum number of rates
2691          * we are going to try. Otherwise mac80211 will truncate our
2692          * reported tx rates and the rc algortihm will end up with
2693          * incorrect data.
2694          */
2695         rt2x00dev->hw->max_rates = 1;
2696         rt2x00dev->hw->max_report_rates = 7;
2697         rt2x00dev->hw->max_rate_tries = 1;
2698
2699         /*
2700          * Initialize hw_mode information.
2701          */
2702         spec->supported_bands = SUPPORT_BAND_2GHZ;
2703         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2704
2705         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2706                 spec->num_channels = 14;
2707                 spec->channels = rf_vals_noseq;
2708         } else {
2709                 spec->num_channels = 14;
2710                 spec->channels = rf_vals_seq;
2711         }
2712
2713         if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) {
2714                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2715                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2716         }
2717
2718         /*
2719          * Create channel information array
2720          */
2721         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
2722         if (!info)
2723                 return -ENOMEM;
2724
2725         spec->channels_info = info;
2726
2727         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2728         for (i = 0; i < 14; i++) {
2729                 info[i].max_power = MAX_TXPOWER;
2730                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2731         }
2732
2733         if (spec->num_channels > 14) {
2734                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2735                 for (i = 14; i < spec->num_channels; i++) {
2736                         info[i].max_power = MAX_TXPOWER;
2737                         info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2738                 }
2739         }
2740
2741         return 0;
2742 }
2743
2744 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2745 {
2746         int retval;
2747
2748         /*
2749          * Disable power saving.
2750          */
2751         rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
2752
2753         /*
2754          * Allocate eeprom data.
2755          */
2756         retval = rt61pci_validate_eeprom(rt2x00dev);
2757         if (retval)
2758                 return retval;
2759
2760         retval = rt61pci_init_eeprom(rt2x00dev);
2761         if (retval)
2762                 return retval;
2763
2764         /*
2765          * Initialize hw specifications.
2766          */
2767         retval = rt61pci_probe_hw_mode(rt2x00dev);
2768         if (retval)
2769                 return retval;
2770
2771         /*
2772          * This device has multiple filters for control frames,
2773          * but has no a separate filter for PS Poll frames.
2774          */
2775         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2776
2777         /*
2778          * This device requires firmware and DMA mapped skbs.
2779          */
2780         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2781         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2782         if (!modparam_nohwcrypt)
2783                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2784         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
2785
2786         /*
2787          * Set the rssi offset.
2788          */
2789         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2790
2791         return 0;
2792 }
2793
2794 /*
2795  * IEEE80211 stack callback functions.
2796  */
2797 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2798                            const struct ieee80211_tx_queue_params *params)
2799 {
2800         struct rt2x00_dev *rt2x00dev = hw->priv;
2801         struct data_queue *queue;
2802         struct rt2x00_field32 field;
2803         int retval;
2804         u32 reg;
2805         u32 offset;
2806
2807         /*
2808          * First pass the configuration through rt2x00lib, that will
2809          * update the queue settings and validate the input. After that
2810          * we are free to update the registers based on the value
2811          * in the queue parameter.
2812          */
2813         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2814         if (retval)
2815                 return retval;
2816
2817         /*
2818          * We only need to perform additional register initialization
2819          * for WMM queues.
2820          */
2821         if (queue_idx >= 4)
2822                 return 0;
2823
2824         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2825
2826         /* Update WMM TXOP register */
2827         offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2828         field.bit_offset = (queue_idx & 1) * 16;
2829         field.bit_mask = 0xffff << field.bit_offset;
2830
2831         rt2x00pci_register_read(rt2x00dev, offset, &reg);
2832         rt2x00_set_field32(&reg, field, queue->txop);
2833         rt2x00pci_register_write(rt2x00dev, offset, reg);
2834
2835         /* Update WMM registers */
2836         field.bit_offset = queue_idx * 4;
2837         field.bit_mask = 0xf << field.bit_offset;
2838
2839         rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2840         rt2x00_set_field32(&reg, field, queue->aifs);
2841         rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2842
2843         rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2844         rt2x00_set_field32(&reg, field, queue->cw_min);
2845         rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2846
2847         rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2848         rt2x00_set_field32(&reg, field, queue->cw_max);
2849         rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2850
2851         return 0;
2852 }
2853
2854 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2855 {
2856         struct rt2x00_dev *rt2x00dev = hw->priv;
2857         u64 tsf;
2858         u32 reg;
2859
2860         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2861         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2862         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2863         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2864
2865         return tsf;
2866 }
2867
2868 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2869         .tx                     = rt2x00mac_tx,
2870         .start                  = rt2x00mac_start,
2871         .stop                   = rt2x00mac_stop,
2872         .add_interface          = rt2x00mac_add_interface,
2873         .remove_interface       = rt2x00mac_remove_interface,
2874         .config                 = rt2x00mac_config,
2875         .configure_filter       = rt2x00mac_configure_filter,
2876         .set_key                = rt2x00mac_set_key,
2877         .sw_scan_start          = rt2x00mac_sw_scan_start,
2878         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
2879         .get_stats              = rt2x00mac_get_stats,
2880         .bss_info_changed       = rt2x00mac_bss_info_changed,
2881         .conf_tx                = rt61pci_conf_tx,
2882         .get_tsf                = rt61pci_get_tsf,
2883         .rfkill_poll            = rt2x00mac_rfkill_poll,
2884         .flush                  = rt2x00mac_flush,
2885 };
2886
2887 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2888         .irq_handler            = rt61pci_interrupt,
2889         .irq_handler_thread     = rt61pci_interrupt_thread,
2890         .probe_hw               = rt61pci_probe_hw,
2891         .get_firmware_name      = rt61pci_get_firmware_name,
2892         .check_firmware         = rt61pci_check_firmware,
2893         .load_firmware          = rt61pci_load_firmware,
2894         .initialize             = rt2x00pci_initialize,
2895         .uninitialize           = rt2x00pci_uninitialize,
2896         .get_entry_state        = rt61pci_get_entry_state,
2897         .clear_entry            = rt61pci_clear_entry,
2898         .set_device_state       = rt61pci_set_device_state,
2899         .rfkill_poll            = rt61pci_rfkill_poll,
2900         .link_stats             = rt61pci_link_stats,
2901         .reset_tuner            = rt61pci_reset_tuner,
2902         .link_tuner             = rt61pci_link_tuner,
2903         .write_tx_desc          = rt61pci_write_tx_desc,
2904         .write_beacon           = rt61pci_write_beacon,
2905         .kick_tx_queue          = rt61pci_kick_queue,
2906         .kill_tx_queue          = rt61pci_stop_queue,
2907         .fill_rxdone            = rt61pci_fill_rxdone,
2908         .config_shared_key      = rt61pci_config_shared_key,
2909         .config_pairwise_key    = rt61pci_config_pairwise_key,
2910         .config_filter          = rt61pci_config_filter,
2911         .config_intf            = rt61pci_config_intf,
2912         .config_erp             = rt61pci_config_erp,
2913         .config_ant             = rt61pci_config_ant,
2914         .config                 = rt61pci_config,
2915 };
2916
2917 static const struct data_queue_desc rt61pci_queue_rx = {
2918         .entry_num              = 32,
2919         .data_size              = DATA_FRAME_SIZE,
2920         .desc_size              = RXD_DESC_SIZE,
2921         .priv_size              = sizeof(struct queue_entry_priv_pci),
2922 };
2923
2924 static const struct data_queue_desc rt61pci_queue_tx = {
2925         .entry_num              = 32,
2926         .data_size              = DATA_FRAME_SIZE,
2927         .desc_size              = TXD_DESC_SIZE,
2928         .priv_size              = sizeof(struct queue_entry_priv_pci),
2929 };
2930
2931 static const struct data_queue_desc rt61pci_queue_bcn = {
2932         .entry_num              = 4,
2933         .data_size              = 0, /* No DMA required for beacons */
2934         .desc_size              = TXINFO_SIZE,
2935         .priv_size              = sizeof(struct queue_entry_priv_pci),
2936 };
2937
2938 static const struct rt2x00_ops rt61pci_ops = {
2939         .name                   = KBUILD_MODNAME,
2940         .max_sta_intf           = 1,
2941         .max_ap_intf            = 4,
2942         .eeprom_size            = EEPROM_SIZE,
2943         .rf_size                = RF_SIZE,
2944         .tx_queues              = NUM_TX_QUEUES,
2945         .extra_tx_headroom      = 0,
2946         .rx                     = &rt61pci_queue_rx,
2947         .tx                     = &rt61pci_queue_tx,
2948         .bcn                    = &rt61pci_queue_bcn,
2949         .lib                    = &rt61pci_rt2x00_ops,
2950         .hw                     = &rt61pci_mac80211_ops,
2951 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2952         .debugfs                = &rt61pci_rt2x00debug,
2953 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2954 };
2955
2956 /*
2957  * RT61pci module information.
2958  */
2959 static DEFINE_PCI_DEVICE_TABLE(rt61pci_device_table) = {
2960         /* RT2561s */
2961         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2962         /* RT2561 v2 */
2963         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2964         /* RT2661 */
2965         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2966         { 0, }
2967 };
2968
2969 MODULE_AUTHOR(DRV_PROJECT);
2970 MODULE_VERSION(DRV_VERSION);
2971 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2972 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2973                         "PCI & PCMCIA chipset based cards");
2974 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2975 MODULE_FIRMWARE(FIRMWARE_RT2561);
2976 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2977 MODULE_FIRMWARE(FIRMWARE_RT2661);
2978 MODULE_LICENSE("GPL");
2979
2980 static struct pci_driver rt61pci_driver = {
2981         .name           = KBUILD_MODNAME,
2982         .id_table       = rt61pci_device_table,
2983         .probe          = rt2x00pci_probe,
2984         .remove         = __devexit_p(rt2x00pci_remove),
2985         .suspend        = rt2x00pci_suspend,
2986         .resume         = rt2x00pci_resume,
2987 };
2988
2989 static int __init rt61pci_init(void)
2990 {
2991         return pci_register_driver(&rt61pci_driver);
2992 }
2993
2994 static void __exit rt61pci_exit(void)
2995 {
2996         pci_unregister_driver(&rt61pci_driver);
2997 }
2998
2999 module_init(rt61pci_init);
3000 module_exit(rt61pci_exit);