bfc2fc5c1c222e5d24e46cde8fefc8f586178af6
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
1 /*
2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10         <http://rt2x00.serialmonkey.com>
11
12         This program is free software; you can redistribute it and/or modify
13         it under the terms of the GNU General Public License as published by
14         the Free Software Foundation; either version 2 of the License, or
15         (at your option) any later version.
16
17         This program is distributed in the hope that it will be useful,
18         but WITHOUT ANY WARRANTY; without even the implied warranty of
19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20         GNU General Public License for more details.
21
22         You should have received a copy of the GNU General Public License
23         along with this program; if not, write to the
24         Free Software Foundation, Inc.,
25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26  */
27
28 /*
29         Module: rt2800pci
30         Abstract: rt2800pci device specific routines.
31         Supported chipsets: RT2800E & RT2800ED.
32  */
33
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
42
43 #include "rt2x00.h"
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
47 #include "rt2800.h"
48 #include "rt2800pci.h"
49
50 /*
51  * Allow hardware encryption to be disabled.
52  */
53 static int modparam_nohwcrypt = 0;
54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58 {
59         unsigned int i;
60         u32 reg;
61
62         /*
63          * SOC devices don't support MCU requests.
64          */
65         if (rt2x00_is_soc(rt2x00dev))
66                 return;
67
68         for (i = 0; i < 200; i++) {
69                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
70
71                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75                         break;
76
77                 udelay(REGISTER_BUSY_DELAY);
78         }
79
80         if (i == 200)
81                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
83         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
85 }
86
87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89 {
90         void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
91
92         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
93
94         iounmap(base_addr);
95 }
96 #else
97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
98 {
99 }
100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
101
102 #ifdef CONFIG_PCI
103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
104 {
105         struct rt2x00_dev *rt2x00dev = eeprom->data;
106         u32 reg;
107
108         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
109
110         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112         eeprom->reg_data_clock =
113             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114         eeprom->reg_chip_select =
115             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
116 }
117
118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
119 {
120         struct rt2x00_dev *rt2x00dev = eeprom->data;
121         u32 reg = 0;
122
123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
126                            !!eeprom->reg_data_clock);
127         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
128                            !!eeprom->reg_chip_select);
129
130         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
131 }
132
133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
134 {
135         struct eeprom_93cx6 eeprom;
136         u32 reg;
137
138         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
139
140         eeprom.data = rt2x00dev;
141         eeprom.register_read = rt2800pci_eepromregister_read;
142         eeprom.register_write = rt2800pci_eepromregister_write;
143         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
144         {
145         case 0:
146                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
147                 break;
148         case 1:
149                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
150                 break;
151         default:
152                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
153                 break;
154         }
155         eeprom.reg_data_in = 0;
156         eeprom.reg_data_out = 0;
157         eeprom.reg_data_clock = 0;
158         eeprom.reg_chip_select = 0;
159
160         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161                                EEPROM_SIZE / sizeof(u16));
162 }
163
164 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
165 {
166         return rt2800_efuse_detect(rt2x00dev);
167 }
168
169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
170 {
171         rt2800_read_eeprom_efuse(rt2x00dev);
172 }
173 #else
174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
175 {
176 }
177
178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179 {
180         return 0;
181 }
182
183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
184 {
185 }
186 #endif /* CONFIG_PCI */
187
188 /*
189  * Queue handlers.
190  */
191 static void rt2800pci_start_queue(struct data_queue *queue)
192 {
193         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
194         u32 reg;
195
196         switch (queue->qid) {
197         case QID_RX:
198                 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
199                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
200                 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
201                 break;
202         case QID_BEACON:
203                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
204                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
205                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
206                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
207                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
208                 break;
209         default:
210                 break;
211         };
212 }
213
214 static void rt2800pci_kick_queue(struct data_queue *queue)
215 {
216         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
217         struct queue_entry *entry;
218
219         switch (queue->qid) {
220         case QID_AC_VO:
221         case QID_AC_VI:
222         case QID_AC_BE:
223         case QID_AC_BK:
224                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
225                 rt2800_register_write(rt2x00dev, TX_CTX_IDX(queue->qid), entry->entry_idx);
226                 break;
227         case QID_MGMT:
228                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
229                 rt2800_register_write(rt2x00dev, TX_CTX_IDX(5), entry->entry_idx);
230                 break;
231         default:
232                 break;
233         }
234 }
235
236 static void rt2800pci_stop_queue(struct data_queue *queue)
237 {
238         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
239         u32 reg;
240
241         switch (queue->qid) {
242         case QID_RX:
243                 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
244                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
245                 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
246                 break;
247         case QID_BEACON:
248                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
249                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
250                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
251                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
252                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
253                 break;
254         default:
255                 break;
256         }
257 }
258
259 /*
260  * Firmware functions
261  */
262 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
263 {
264         return FIRMWARE_RT2860;
265 }
266
267 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
268                                     const u8 *data, const size_t len)
269 {
270         u32 reg;
271
272         /*
273          * enable Host program ram write selection
274          */
275         reg = 0;
276         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
277         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
278
279         /*
280          * Write firmware to device.
281          */
282         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
283                                    data, len);
284
285         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
286         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
287
288         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
289         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
290
291         return 0;
292 }
293
294 /*
295  * Initialization functions.
296  */
297 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
298 {
299         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
300         u32 word;
301
302         if (entry->queue->qid == QID_RX) {
303                 rt2x00_desc_read(entry_priv->desc, 1, &word);
304
305                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
306         } else {
307                 rt2x00_desc_read(entry_priv->desc, 1, &word);
308
309                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
310         }
311 }
312
313 static void rt2800pci_clear_entry(struct queue_entry *entry)
314 {
315         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
316         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
317         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
318         u32 word;
319
320         if (entry->queue->qid == QID_RX) {
321                 rt2x00_desc_read(entry_priv->desc, 0, &word);
322                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
323                 rt2x00_desc_write(entry_priv->desc, 0, word);
324
325                 rt2x00_desc_read(entry_priv->desc, 1, &word);
326                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
327                 rt2x00_desc_write(entry_priv->desc, 1, word);
328
329                 /*
330                  * Set RX IDX in register to inform hardware that we have
331                  * handled this entry and it is available for reuse again.
332                  */
333                 rt2800_register_write(rt2x00dev, RX_CRX_IDX,
334                                       entry->entry_idx);
335         } else {
336                 rt2x00_desc_read(entry_priv->desc, 1, &word);
337                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
338                 rt2x00_desc_write(entry_priv->desc, 1, word);
339         }
340 }
341
342 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
343 {
344         struct queue_entry_priv_pci *entry_priv;
345         u32 reg;
346
347         /*
348          * Initialize registers.
349          */
350         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
351         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
352         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
353         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
354         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
355
356         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
357         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
358         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
359         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
360         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
361
362         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
363         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
364         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
365         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
366         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
367
368         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
369         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
370         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
371         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
372         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
373
374         entry_priv = rt2x00dev->rx->entries[0].priv_data;
375         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
376         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
377         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
378         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
379
380         /*
381          * Enable global DMA configuration
382          */
383         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
384         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
385         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
386         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
387         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
388
389         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
390
391         return 0;
392 }
393
394 /*
395  * Device state switch handlers.
396  */
397 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
398                                  enum dev_state state)
399 {
400         int mask = (state == STATE_RADIO_IRQ_ON) ||
401                    (state == STATE_RADIO_IRQ_ON_ISR);
402         u32 reg;
403
404         /*
405          * When interrupts are being enabled, the interrupt registers
406          * should clear the register to assure a clean state.
407          */
408         if (state == STATE_RADIO_IRQ_ON) {
409                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
410                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
411         }
412
413         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
414         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
415         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
416         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
417         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
418         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
419         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
420         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
421         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
422         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
423         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
424         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
425         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
426         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
427         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
428         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
429         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
430         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
431         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
432         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
433 }
434
435 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
436 {
437         u32 reg;
438
439         /*
440          * Reset DMA indexes
441          */
442         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
443         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
444         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
445         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
446         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
447         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
448         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
449         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
450         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
451
452         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
453         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
454
455         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
456
457         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
458         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
459         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
460         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
461
462         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
463
464         return 0;
465 }
466
467 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
468 {
469         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
470                      rt2800pci_init_queues(rt2x00dev)))
471                 return -EIO;
472
473         return rt2800_enable_radio(rt2x00dev);
474 }
475
476 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
477 {
478         if (rt2x00_is_soc(rt2x00dev)) {
479                 rt2800_disable_radio(rt2x00dev);
480                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
481                 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
482         }
483 }
484
485 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
486                                enum dev_state state)
487 {
488         if (state == STATE_AWAKE) {
489                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
490                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
491         } else if (state == STATE_SLEEP) {
492                 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, 0xffffffff);
493                 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, 0xffffffff);
494                 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
495         }
496
497         return 0;
498 }
499
500 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
501                                       enum dev_state state)
502 {
503         int retval = 0;
504
505         switch (state) {
506         case STATE_RADIO_ON:
507                 /*
508                  * Before the radio can be enabled, the device first has
509                  * to be woken up. After that it needs a bit of time
510                  * to be fully awake and then the radio can be enabled.
511                  */
512                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
513                 msleep(1);
514                 retval = rt2800pci_enable_radio(rt2x00dev);
515                 break;
516         case STATE_RADIO_OFF:
517                 /*
518                  * After the radio has been disabled, the device should
519                  * be put to sleep for powersaving.
520                  */
521                 rt2800pci_disable_radio(rt2x00dev);
522                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
523                 break;
524         case STATE_RADIO_IRQ_ON:
525         case STATE_RADIO_IRQ_ON_ISR:
526         case STATE_RADIO_IRQ_OFF:
527         case STATE_RADIO_IRQ_OFF_ISR:
528                 rt2800pci_toggle_irq(rt2x00dev, state);
529                 break;
530         case STATE_DEEP_SLEEP:
531         case STATE_SLEEP:
532         case STATE_STANDBY:
533         case STATE_AWAKE:
534                 retval = rt2800pci_set_state(rt2x00dev, state);
535                 break;
536         default:
537                 retval = -ENOTSUPP;
538                 break;
539         }
540
541         if (unlikely(retval))
542                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
543                       state, retval);
544
545         return retval;
546 }
547
548 /*
549  * TX descriptor initialization
550  */
551 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
552 {
553         return (__le32 *) entry->skb->data;
554 }
555
556 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
557                                     struct txentry_desc *txdesc)
558 {
559         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
560         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
561         __le32 *txd = entry_priv->desc;
562         u32 word;
563
564         /*
565          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
566          * must contains a TXWI structure + 802.11 header + padding + 802.11
567          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
568          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
569          * data. It means that LAST_SEC0 is always 0.
570          */
571
572         /*
573          * Initialize TX descriptor
574          */
575         rt2x00_desc_read(txd, 0, &word);
576         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
577         rt2x00_desc_write(txd, 0, word);
578
579         rt2x00_desc_read(txd, 1, &word);
580         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
581         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
582                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
583         rt2x00_set_field32(&word, TXD_W1_BURST,
584                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
585         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
586         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
587         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
588         rt2x00_desc_write(txd, 1, word);
589
590         rt2x00_desc_read(txd, 2, &word);
591         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
592                            skbdesc->skb_dma + TXWI_DESC_SIZE);
593         rt2x00_desc_write(txd, 2, word);
594
595         rt2x00_desc_read(txd, 3, &word);
596         rt2x00_set_field32(&word, TXD_W3_WIV,
597                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
598         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
599         rt2x00_desc_write(txd, 3, word);
600
601         /*
602          * Register descriptor details in skb frame descriptor.
603          */
604         skbdesc->desc = txd;
605         skbdesc->desc_len = TXD_DESC_SIZE;
606 }
607
608 /*
609  * RX control handlers
610  */
611 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
612                                   struct rxdone_entry_desc *rxdesc)
613 {
614         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
615         __le32 *rxd = entry_priv->desc;
616         u32 word;
617
618         rt2x00_desc_read(rxd, 3, &word);
619
620         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
621                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
622
623         /*
624          * Unfortunately we don't know the cipher type used during
625          * decryption. This prevents us from correct providing
626          * correct statistics through debugfs.
627          */
628         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
629
630         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
631                 /*
632                  * Hardware has stripped IV/EIV data from 802.11 frame during
633                  * decryption. Unfortunately the descriptor doesn't contain
634                  * any fields with the EIV/IV data either, so they can't
635                  * be restored by rt2x00lib.
636                  */
637                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
638
639                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
640                         rxdesc->flags |= RX_FLAG_DECRYPTED;
641                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
642                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
643         }
644
645         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
646                 rxdesc->dev_flags |= RXDONE_MY_BSS;
647
648         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
649                 rxdesc->dev_flags |= RXDONE_L2PAD;
650
651         /*
652          * Process the RXWI structure that is at the start of the buffer.
653          */
654         rt2800_process_rxwi(entry, rxdesc);
655 }
656
657 /*
658  * Interrupt functions.
659  */
660 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
661 {
662         struct ieee80211_conf conf = { .flags = 0 };
663         struct rt2x00lib_conf libconf = { .conf = &conf };
664
665         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
666 }
667
668 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
669 {
670         struct data_queue *queue;
671         struct queue_entry *entry;
672         u32 status;
673         u8 qid;
674
675         while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
676                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
677                 if (qid >= QID_RX) {
678                         /*
679                          * Unknown queue, this shouldn't happen. Just drop
680                          * this tx status.
681                          */
682                         WARNING(rt2x00dev, "Got TX status report with "
683                                            "unexpected pid %u, dropping\n", qid);
684                         break;
685                 }
686
687                 queue = rt2x00queue_get_queue(rt2x00dev, qid);
688                 if (unlikely(queue == NULL)) {
689                         /*
690                          * The queue is NULL, this shouldn't happen. Stop
691                          * processing here and drop the tx status
692                          */
693                         WARNING(rt2x00dev, "Got TX status for an unavailable "
694                                            "queue %u, dropping\n", qid);
695                         break;
696                 }
697
698                 if (rt2x00queue_empty(queue)) {
699                         /*
700                          * The queue is empty. Stop processing here
701                          * and drop the tx status.
702                          */
703                         WARNING(rt2x00dev, "Got TX status for an empty "
704                                            "queue %u, dropping\n", qid);
705                         break;
706                 }
707
708                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
709                 rt2800_txdone_entry(entry, status);
710         }
711 }
712
713 static void rt2800pci_txstatus_tasklet(unsigned long data)
714 {
715         rt2800pci_txdone((struct rt2x00_dev *)data);
716 }
717
718 static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
719 {
720         struct rt2x00_dev *rt2x00dev = dev_instance;
721         u32 reg = rt2x00dev->irqvalue[0];
722
723         /*
724          * 1 - Pre TBTT interrupt.
725          */
726         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
727                 rt2x00lib_pretbtt(rt2x00dev);
728
729         /*
730          * 2 - Beacondone interrupt.
731          */
732         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
733                 rt2x00lib_beacondone(rt2x00dev);
734
735         /*
736          * 3 - Rx ring done interrupt.
737          */
738         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
739                 rt2x00pci_rxdone(rt2x00dev);
740
741         /*
742          * 4 - Auto wakeup interrupt.
743          */
744         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
745                 rt2800pci_wakeup(rt2x00dev);
746
747         /* Enable interrupts again. */
748         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
749                                               STATE_RADIO_IRQ_ON_ISR);
750
751         return IRQ_HANDLED;
752 }
753
754 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
755 {
756         u32 status;
757         int i;
758
759         /*
760          * The TX_FIFO_STATUS interrupt needs special care. We should
761          * read TX_STA_FIFO but we should do it immediately as otherwise
762          * the register can overflow and we would lose status reports.
763          *
764          * Hence, read the TX_STA_FIFO register and copy all tx status
765          * reports into a kernel FIFO which is handled in the txstatus
766          * tasklet. We use a tasklet to process the tx status reports
767          * because we can schedule the tasklet multiple times (when the
768          * interrupt fires again during tx status processing).
769          *
770          * Furthermore we don't disable the TX_FIFO_STATUS
771          * interrupt here but leave it enabled so that the TX_STA_FIFO
772          * can also be read while the interrupt thread gets executed.
773          *
774          * Since we have only one producer and one consumer we don't
775          * need to lock the kfifo.
776          */
777         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
778                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
779
780                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
781                         break;
782
783                 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
784                         WARNING(rt2x00dev, "TX status FIFO overrun,"
785                                 "drop tx status report.\n");
786                         break;
787                 }
788         }
789
790         /* Schedule the tasklet for processing the tx status. */
791         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
792 }
793
794 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
795 {
796         struct rt2x00_dev *rt2x00dev = dev_instance;
797         u32 reg;
798         irqreturn_t ret = IRQ_HANDLED;
799
800         /* Read status and ACK all interrupts */
801         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
802         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
803
804         if (!reg)
805                 return IRQ_NONE;
806
807         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
808                 return IRQ_HANDLED;
809
810         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
811                 rt2800pci_txstatus_interrupt(rt2x00dev);
812
813         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT) ||
814             rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT) ||
815             rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE) ||
816             rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) {
817                 /*
818                  * All other interrupts are handled in the interrupt thread.
819                  * Store irqvalue for use in the interrupt thread.
820                  */
821                 rt2x00dev->irqvalue[0] = reg;
822
823                 /*
824                  * Disable interrupts, will be enabled again in the
825                  * interrupt thread.
826                 */
827                 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
828                                                       STATE_RADIO_IRQ_OFF_ISR);
829
830                 /*
831                  * Leave the TX_FIFO_STATUS interrupt enabled to not lose any
832                  * tx status reports.
833                  */
834                 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
835                 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
836                 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
837
838                 ret = IRQ_WAKE_THREAD;
839         }
840
841         return ret;
842 }
843
844 /*
845  * Device probe functions.
846  */
847 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
848 {
849         /*
850          * Read EEPROM into buffer
851          */
852         if (rt2x00_is_soc(rt2x00dev))
853                 rt2800pci_read_eeprom_soc(rt2x00dev);
854         else if (rt2800pci_efuse_detect(rt2x00dev))
855                 rt2800pci_read_eeprom_efuse(rt2x00dev);
856         else
857                 rt2800pci_read_eeprom_pci(rt2x00dev);
858
859         return rt2800_validate_eeprom(rt2x00dev);
860 }
861
862 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
863 {
864         int retval;
865
866         /*
867          * Allocate eeprom data.
868          */
869         retval = rt2800pci_validate_eeprom(rt2x00dev);
870         if (retval)
871                 return retval;
872
873         retval = rt2800_init_eeprom(rt2x00dev);
874         if (retval)
875                 return retval;
876
877         /*
878          * Initialize hw specifications.
879          */
880         retval = rt2800_probe_hw_mode(rt2x00dev);
881         if (retval)
882                 return retval;
883
884         /*
885          * This device has multiple filters for control frames
886          * and has a separate filter for PS Poll frames.
887          */
888         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
889         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
890
891         /*
892          * This device has a pre tbtt interrupt and thus fetches
893          * a new beacon directly prior to transmission.
894          */
895         __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
896
897         /*
898          * This device requires firmware.
899          */
900         if (!rt2x00_is_soc(rt2x00dev))
901                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
902         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
903         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
904         __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
905         __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
906         if (!modparam_nohwcrypt)
907                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
908         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
909
910         /*
911          * Set the rssi offset.
912          */
913         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
914
915         return 0;
916 }
917
918 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
919         .tx                     = rt2x00mac_tx,
920         .start                  = rt2x00mac_start,
921         .stop                   = rt2x00mac_stop,
922         .add_interface          = rt2x00mac_add_interface,
923         .remove_interface       = rt2x00mac_remove_interface,
924         .config                 = rt2x00mac_config,
925         .configure_filter       = rt2x00mac_configure_filter,
926         .set_key                = rt2x00mac_set_key,
927         .sw_scan_start          = rt2x00mac_sw_scan_start,
928         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
929         .get_stats              = rt2x00mac_get_stats,
930         .get_tkip_seq           = rt2800_get_tkip_seq,
931         .set_rts_threshold      = rt2800_set_rts_threshold,
932         .bss_info_changed       = rt2x00mac_bss_info_changed,
933         .conf_tx                = rt2800_conf_tx,
934         .get_tsf                = rt2800_get_tsf,
935         .rfkill_poll            = rt2x00mac_rfkill_poll,
936         .ampdu_action           = rt2800_ampdu_action,
937         .flush                  = rt2x00mac_flush,
938         .get_survey             = rt2800_get_survey,
939 };
940
941 static const struct rt2800_ops rt2800pci_rt2800_ops = {
942         .register_read          = rt2x00pci_register_read,
943         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
944         .register_write         = rt2x00pci_register_write,
945         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
946         .register_multiread     = rt2x00pci_register_multiread,
947         .register_multiwrite    = rt2x00pci_register_multiwrite,
948         .regbusy_read           = rt2x00pci_regbusy_read,
949         .drv_write_firmware     = rt2800pci_write_firmware,
950         .drv_init_registers     = rt2800pci_init_registers,
951         .drv_get_txwi           = rt2800pci_get_txwi,
952 };
953
954 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
955         .irq_handler            = rt2800pci_interrupt,
956         .irq_handler_thread     = rt2800pci_interrupt_thread,
957         .txstatus_tasklet       = rt2800pci_txstatus_tasklet,
958         .probe_hw               = rt2800pci_probe_hw,
959         .get_firmware_name      = rt2800pci_get_firmware_name,
960         .check_firmware         = rt2800_check_firmware,
961         .load_firmware          = rt2800_load_firmware,
962         .initialize             = rt2x00pci_initialize,
963         .uninitialize           = rt2x00pci_uninitialize,
964         .get_entry_state        = rt2800pci_get_entry_state,
965         .clear_entry            = rt2800pci_clear_entry,
966         .set_device_state       = rt2800pci_set_device_state,
967         .rfkill_poll            = rt2800_rfkill_poll,
968         .link_stats             = rt2800_link_stats,
969         .reset_tuner            = rt2800_reset_tuner,
970         .link_tuner             = rt2800_link_tuner,
971         .start_queue            = rt2800pci_start_queue,
972         .kick_queue             = rt2800pci_kick_queue,
973         .stop_queue             = rt2800pci_stop_queue,
974         .write_tx_desc          = rt2800pci_write_tx_desc,
975         .write_tx_data          = rt2800_write_tx_data,
976         .write_beacon           = rt2800_write_beacon,
977         .fill_rxdone            = rt2800pci_fill_rxdone,
978         .config_shared_key      = rt2800_config_shared_key,
979         .config_pairwise_key    = rt2800_config_pairwise_key,
980         .config_filter          = rt2800_config_filter,
981         .config_intf            = rt2800_config_intf,
982         .config_erp             = rt2800_config_erp,
983         .config_ant             = rt2800_config_ant,
984         .config                 = rt2800_config,
985 };
986
987 static const struct data_queue_desc rt2800pci_queue_rx = {
988         .entry_num              = 128,
989         .data_size              = AGGREGATION_SIZE,
990         .desc_size              = RXD_DESC_SIZE,
991         .priv_size              = sizeof(struct queue_entry_priv_pci),
992 };
993
994 static const struct data_queue_desc rt2800pci_queue_tx = {
995         .entry_num              = 64,
996         .data_size              = AGGREGATION_SIZE,
997         .desc_size              = TXD_DESC_SIZE,
998         .priv_size              = sizeof(struct queue_entry_priv_pci),
999 };
1000
1001 static const struct data_queue_desc rt2800pci_queue_bcn = {
1002         .entry_num              = 8,
1003         .data_size              = 0, /* No DMA required for beacons */
1004         .desc_size              = TXWI_DESC_SIZE,
1005         .priv_size              = sizeof(struct queue_entry_priv_pci),
1006 };
1007
1008 static const struct rt2x00_ops rt2800pci_ops = {
1009         .name                   = KBUILD_MODNAME,
1010         .max_sta_intf           = 1,
1011         .max_ap_intf            = 8,
1012         .eeprom_size            = EEPROM_SIZE,
1013         .rf_size                = RF_SIZE,
1014         .tx_queues              = NUM_TX_QUEUES,
1015         .extra_tx_headroom      = TXWI_DESC_SIZE,
1016         .rx                     = &rt2800pci_queue_rx,
1017         .tx                     = &rt2800pci_queue_tx,
1018         .bcn                    = &rt2800pci_queue_bcn,
1019         .lib                    = &rt2800pci_rt2x00_ops,
1020         .drv                    = &rt2800pci_rt2800_ops,
1021         .hw                     = &rt2800pci_mac80211_ops,
1022 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1023         .debugfs                = &rt2800_rt2x00debug,
1024 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1025 };
1026
1027 /*
1028  * RT2800pci module information.
1029  */
1030 #ifdef CONFIG_PCI
1031 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1032         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1033         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1034         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1035         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1036         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1037         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1038         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1039         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1040         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1041         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1042         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1043         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1044         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1045         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1046         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1047         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1048 #ifdef CONFIG_RT2800PCI_RT33XX
1049         { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1050 #endif
1051 #ifdef CONFIG_RT2800PCI_RT35XX
1052         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1053         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1054         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1055         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1056         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1057 #endif
1058         { 0, }
1059 };
1060 #endif /* CONFIG_PCI */
1061
1062 MODULE_AUTHOR(DRV_PROJECT);
1063 MODULE_VERSION(DRV_VERSION);
1064 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1065 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1066 #ifdef CONFIG_PCI
1067 MODULE_FIRMWARE(FIRMWARE_RT2860);
1068 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1069 #endif /* CONFIG_PCI */
1070 MODULE_LICENSE("GPL");
1071
1072 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1073 static int rt2800soc_probe(struct platform_device *pdev)
1074 {
1075         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1076 }
1077
1078 static struct platform_driver rt2800soc_driver = {
1079         .driver         = {
1080                 .name           = "rt2800_wmac",
1081                 .owner          = THIS_MODULE,
1082                 .mod_name       = KBUILD_MODNAME,
1083         },
1084         .probe          = rt2800soc_probe,
1085         .remove         = __devexit_p(rt2x00soc_remove),
1086         .suspend        = rt2x00soc_suspend,
1087         .resume         = rt2x00soc_resume,
1088 };
1089 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1090
1091 #ifdef CONFIG_PCI
1092 static struct pci_driver rt2800pci_driver = {
1093         .name           = KBUILD_MODNAME,
1094         .id_table       = rt2800pci_device_table,
1095         .probe          = rt2x00pci_probe,
1096         .remove         = __devexit_p(rt2x00pci_remove),
1097         .suspend        = rt2x00pci_suspend,
1098         .resume         = rt2x00pci_resume,
1099 };
1100 #endif /* CONFIG_PCI */
1101
1102 static int __init rt2800pci_init(void)
1103 {
1104         int ret = 0;
1105
1106 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1107         ret = platform_driver_register(&rt2800soc_driver);
1108         if (ret)
1109                 return ret;
1110 #endif
1111 #ifdef CONFIG_PCI
1112         ret = pci_register_driver(&rt2800pci_driver);
1113         if (ret) {
1114 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1115                 platform_driver_unregister(&rt2800soc_driver);
1116 #endif
1117                 return ret;
1118         }
1119 #endif
1120
1121         return ret;
1122 }
1123
1124 static void __exit rt2800pci_exit(void)
1125 {
1126 #ifdef CONFIG_PCI
1127         pci_unregister_driver(&rt2800pci_driver);
1128 #endif
1129 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1130         platform_driver_unregister(&rt2800soc_driver);
1131 #endif
1132 }
1133
1134 module_init(rt2800pci_init);
1135 module_exit(rt2800pci_exit);