rt2x00: Introduce 3 queue commands in drivers (start, kick, stop).
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
1 /*
2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10         <http://rt2x00.serialmonkey.com>
11
12         This program is free software; you can redistribute it and/or modify
13         it under the terms of the GNU General Public License as published by
14         the Free Software Foundation; either version 2 of the License, or
15         (at your option) any later version.
16
17         This program is distributed in the hope that it will be useful,
18         but WITHOUT ANY WARRANTY; without even the implied warranty of
19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20         GNU General Public License for more details.
21
22         You should have received a copy of the GNU General Public License
23         along with this program; if not, write to the
24         Free Software Foundation, Inc.,
25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26  */
27
28 /*
29         Module: rt2800pci
30         Abstract: rt2800pci device specific routines.
31         Supported chipsets: RT2800E & RT2800ED.
32  */
33
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
42
43 #include "rt2x00.h"
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
47 #include "rt2800.h"
48 #include "rt2800pci.h"
49
50 /*
51  * Allow hardware encryption to be disabled.
52  */
53 static int modparam_nohwcrypt = 0;
54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58 {
59         unsigned int i;
60         u32 reg;
61
62         /*
63          * SOC devices don't support MCU requests.
64          */
65         if (rt2x00_is_soc(rt2x00dev))
66                 return;
67
68         for (i = 0; i < 200; i++) {
69                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
70
71                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75                         break;
76
77                 udelay(REGISTER_BUSY_DELAY);
78         }
79
80         if (i == 200)
81                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
83         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
85 }
86
87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89 {
90         void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
91
92         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
93
94         iounmap(base_addr);
95 }
96 #else
97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
98 {
99 }
100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
101
102 #ifdef CONFIG_PCI
103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
104 {
105         struct rt2x00_dev *rt2x00dev = eeprom->data;
106         u32 reg;
107
108         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
109
110         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112         eeprom->reg_data_clock =
113             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114         eeprom->reg_chip_select =
115             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
116 }
117
118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
119 {
120         struct rt2x00_dev *rt2x00dev = eeprom->data;
121         u32 reg = 0;
122
123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
126                            !!eeprom->reg_data_clock);
127         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
128                            !!eeprom->reg_chip_select);
129
130         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
131 }
132
133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
134 {
135         struct eeprom_93cx6 eeprom;
136         u32 reg;
137
138         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
139
140         eeprom.data = rt2x00dev;
141         eeprom.register_read = rt2800pci_eepromregister_read;
142         eeprom.register_write = rt2800pci_eepromregister_write;
143         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
144         {
145         case 0:
146                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
147                 break;
148         case 1:
149                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
150                 break;
151         default:
152                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
153                 break;
154         }
155         eeprom.reg_data_in = 0;
156         eeprom.reg_data_out = 0;
157         eeprom.reg_data_clock = 0;
158         eeprom.reg_chip_select = 0;
159
160         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161                                EEPROM_SIZE / sizeof(u16));
162 }
163
164 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
165 {
166         return rt2800_efuse_detect(rt2x00dev);
167 }
168
169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
170 {
171         rt2800_read_eeprom_efuse(rt2x00dev);
172 }
173 #else
174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
175 {
176 }
177
178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179 {
180         return 0;
181 }
182
183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
184 {
185 }
186 #endif /* CONFIG_PCI */
187
188 /*
189  * Queue handlers.
190  */
191 static void rt2800pci_start_queue(struct data_queue *queue)
192 {
193         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
194         u32 reg;
195
196         switch (queue->qid) {
197         case QID_RX:
198                 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
199                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
200                 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
201                 break;
202         case QID_BEACON:
203                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
204                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
205                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
206                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
207                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
208                 break;
209         default:
210                 break;
211         };
212 }
213
214 static void rt2800pci_kick_queue(struct data_queue *queue)
215 {
216         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
217         struct queue_entry *entry;
218
219         switch (queue->qid) {
220         case QID_AC_BE:
221         case QID_AC_BK:
222         case QID_AC_VI:
223         case QID_AC_VO:
224                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
225                 rt2800_register_write(rt2x00dev, TX_CTX_IDX(queue->qid), entry->entry_idx);
226                 break;
227         case QID_MGMT:
228                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
229                 rt2800_register_write(rt2x00dev, TX_CTX_IDX(5), entry->entry_idx);
230                 break;
231         default:
232                 break;
233         }
234 }
235
236 static void rt2800pci_stop_queue(struct data_queue *queue)
237 {
238         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
239         u32 reg;
240
241         switch (queue->qid) {
242         case QID_RX:
243                 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
244                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
245                 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
246                 break;
247         case QID_BEACON:
248                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
249                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
250                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
251                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
252                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
253                 break;
254         default:
255                 break;
256         }
257 }
258
259 /*
260  * Firmware functions
261  */
262 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
263 {
264         return FIRMWARE_RT2860;
265 }
266
267 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
268                                     const u8 *data, const size_t len)
269 {
270         u32 reg;
271
272         /*
273          * enable Host program ram write selection
274          */
275         reg = 0;
276         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
277         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
278
279         /*
280          * Write firmware to device.
281          */
282         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
283                                    data, len);
284
285         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
286         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
287
288         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
289         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
290
291         return 0;
292 }
293
294 /*
295  * Initialization functions.
296  */
297 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
298 {
299         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
300         u32 word;
301
302         if (entry->queue->qid == QID_RX) {
303                 rt2x00_desc_read(entry_priv->desc, 1, &word);
304
305                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
306         } else {
307                 rt2x00_desc_read(entry_priv->desc, 1, &word);
308
309                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
310         }
311 }
312
313 static void rt2800pci_clear_entry(struct queue_entry *entry)
314 {
315         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
316         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
317         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
318         u32 word;
319
320         if (entry->queue->qid == QID_RX) {
321                 rt2x00_desc_read(entry_priv->desc, 0, &word);
322                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
323                 rt2x00_desc_write(entry_priv->desc, 0, word);
324
325                 rt2x00_desc_read(entry_priv->desc, 1, &word);
326                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
327                 rt2x00_desc_write(entry_priv->desc, 1, word);
328
329                 /*
330                  * Set RX IDX in register to inform hardware that we have
331                  * handled this entry and it is available for reuse again.
332                  */
333                 rt2800_register_write(rt2x00dev, RX_CRX_IDX,
334                                       entry->entry_idx);
335         } else {
336                 rt2x00_desc_read(entry_priv->desc, 1, &word);
337                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
338                 rt2x00_desc_write(entry_priv->desc, 1, word);
339         }
340 }
341
342 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
343 {
344         struct queue_entry_priv_pci *entry_priv;
345         u32 reg;
346
347         /*
348          * Initialize registers.
349          */
350         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
351         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
352         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
353         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
354         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
355
356         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
357         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
358         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
359         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
360         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
361
362         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
363         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
364         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
365         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
366         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
367
368         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
369         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
370         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
371         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
372         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
373
374         entry_priv = rt2x00dev->rx->entries[0].priv_data;
375         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
376         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
377         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
378         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
379
380         /*
381          * Enable global DMA configuration
382          */
383         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
384         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
385         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
386         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
387         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
388
389         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
390
391         return 0;
392 }
393
394 /*
395  * Device state switch handlers.
396  */
397 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
398                                  enum dev_state state)
399 {
400         int mask = (state == STATE_RADIO_IRQ_ON) ||
401                    (state == STATE_RADIO_IRQ_ON_ISR);
402         u32 reg;
403
404         /*
405          * When interrupts are being enabled, the interrupt registers
406          * should clear the register to assure a clean state.
407          */
408         if (state == STATE_RADIO_IRQ_ON) {
409                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
410                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
411         }
412
413         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
414         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
415         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
416         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
417         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
418         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
419         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
420         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
421         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
422         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
423         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
424         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
425         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
426         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
427         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
428         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
429         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
430         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
431         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
432         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
433 }
434
435 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
436 {
437         u32 reg;
438
439         /*
440          * Reset DMA indexes
441          */
442         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
443         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
444         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
445         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
446         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
447         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
448         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
449         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
450         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
451
452         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
453         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
454
455         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
456
457         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
458         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
459         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
460         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
461
462         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
463
464         return 0;
465 }
466
467 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
468 {
469         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
470                      rt2800pci_init_queues(rt2x00dev)))
471                 return -EIO;
472
473         return rt2800_enable_radio(rt2x00dev);
474 }
475
476 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
477 {
478         u32 reg;
479
480         rt2800_disable_radio(rt2x00dev);
481
482         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
483
484         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
485         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
486         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
487         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
488         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
489         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
490         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
491         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
492         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
493
494         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
495         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
496 }
497
498 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
499                                enum dev_state state)
500 {
501         /*
502          * Always put the device to sleep (even when we intend to wakeup!)
503          * if the device is booting and wasn't asleep it will return
504          * failure when attempting to wakeup.
505          */
506         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0xff, 2);
507
508         if (state == STATE_AWAKE) {
509                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
510                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
511         }
512
513         return 0;
514 }
515
516 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
517                                       enum dev_state state)
518 {
519         int retval = 0;
520
521         switch (state) {
522         case STATE_RADIO_ON:
523                 /*
524                  * Before the radio can be enabled, the device first has
525                  * to be woken up. After that it needs a bit of time
526                  * to be fully awake and then the radio can be enabled.
527                  */
528                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
529                 msleep(1);
530                 retval = rt2800pci_enable_radio(rt2x00dev);
531                 break;
532         case STATE_RADIO_OFF:
533                 /*
534                  * After the radio has been disabled, the device should
535                  * be put to sleep for powersaving.
536                  */
537                 rt2800pci_disable_radio(rt2x00dev);
538                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
539                 break;
540         case STATE_RADIO_RX_ON:
541                 rt2800pci_start_queue(rt2x00dev->rx);
542                 break;
543         case STATE_RADIO_RX_OFF:
544                 rt2800pci_stop_queue(rt2x00dev->rx);
545                 break;
546         case STATE_RADIO_IRQ_ON:
547         case STATE_RADIO_IRQ_ON_ISR:
548         case STATE_RADIO_IRQ_OFF:
549         case STATE_RADIO_IRQ_OFF_ISR:
550                 rt2800pci_toggle_irq(rt2x00dev, state);
551                 break;
552         case STATE_DEEP_SLEEP:
553         case STATE_SLEEP:
554         case STATE_STANDBY:
555         case STATE_AWAKE:
556                 retval = rt2800pci_set_state(rt2x00dev, state);
557                 break;
558         default:
559                 retval = -ENOTSUPP;
560                 break;
561         }
562
563         if (unlikely(retval))
564                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
565                       state, retval);
566
567         return retval;
568 }
569
570 /*
571  * TX descriptor initialization
572  */
573 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
574 {
575         return (__le32 *) entry->skb->data;
576 }
577
578 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
579                                     struct txentry_desc *txdesc)
580 {
581         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
582         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
583         __le32 *txd = entry_priv->desc;
584         u32 word;
585
586         /*
587          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
588          * must contains a TXWI structure + 802.11 header + padding + 802.11
589          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
590          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
591          * data. It means that LAST_SEC0 is always 0.
592          */
593
594         /*
595          * Initialize TX descriptor
596          */
597         rt2x00_desc_read(txd, 0, &word);
598         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
599         rt2x00_desc_write(txd, 0, word);
600
601         rt2x00_desc_read(txd, 1, &word);
602         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
603         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
604                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
605         rt2x00_set_field32(&word, TXD_W1_BURST,
606                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
607         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
608         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
609         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
610         rt2x00_desc_write(txd, 1, word);
611
612         rt2x00_desc_read(txd, 2, &word);
613         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
614                            skbdesc->skb_dma + TXWI_DESC_SIZE);
615         rt2x00_desc_write(txd, 2, word);
616
617         rt2x00_desc_read(txd, 3, &word);
618         rt2x00_set_field32(&word, TXD_W3_WIV,
619                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
620         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
621         rt2x00_desc_write(txd, 3, word);
622
623         /*
624          * Register descriptor details in skb frame descriptor.
625          */
626         skbdesc->desc = txd;
627         skbdesc->desc_len = TXD_DESC_SIZE;
628 }
629
630 /*
631  * RX control handlers
632  */
633 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
634                                   struct rxdone_entry_desc *rxdesc)
635 {
636         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
637         __le32 *rxd = entry_priv->desc;
638         u32 word;
639
640         rt2x00_desc_read(rxd, 3, &word);
641
642         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
643                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
644
645         /*
646          * Unfortunately we don't know the cipher type used during
647          * decryption. This prevents us from correct providing
648          * correct statistics through debugfs.
649          */
650         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
651
652         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
653                 /*
654                  * Hardware has stripped IV/EIV data from 802.11 frame during
655                  * decryption. Unfortunately the descriptor doesn't contain
656                  * any fields with the EIV/IV data either, so they can't
657                  * be restored by rt2x00lib.
658                  */
659                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
660
661                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
662                         rxdesc->flags |= RX_FLAG_DECRYPTED;
663                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
664                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
665         }
666
667         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
668                 rxdesc->dev_flags |= RXDONE_MY_BSS;
669
670         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
671                 rxdesc->dev_flags |= RXDONE_L2PAD;
672
673         /*
674          * Process the RXWI structure that is at the start of the buffer.
675          */
676         rt2800_process_rxwi(entry, rxdesc);
677 }
678
679 /*
680  * Interrupt functions.
681  */
682 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
683 {
684         struct ieee80211_conf conf = { .flags = 0 };
685         struct rt2x00lib_conf libconf = { .conf = &conf };
686
687         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
688 }
689
690 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
691 {
692         struct data_queue *queue;
693         struct queue_entry *entry;
694         u32 status;
695         u8 qid;
696
697         while (!kfifo_is_empty(&rt2x00dev->txstatus_fifo)) {
698                 /* Now remove the tx status from the FIFO */
699                 if (kfifo_out(&rt2x00dev->txstatus_fifo, &status,
700                               sizeof(status)) != sizeof(status)) {
701                         WARN_ON(1);
702                         break;
703                 }
704
705                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
706                 if (qid >= QID_RX) {
707                         /*
708                          * Unknown queue, this shouldn't happen. Just drop
709                          * this tx status.
710                          */
711                         WARNING(rt2x00dev, "Got TX status report with "
712                                            "unexpected pid %u, dropping\n", qid);
713                         break;
714                 }
715
716                 queue = rt2x00queue_get_queue(rt2x00dev, qid);
717                 if (unlikely(queue == NULL)) {
718                         /*
719                          * The queue is NULL, this shouldn't happen. Stop
720                          * processing here and drop the tx status
721                          */
722                         WARNING(rt2x00dev, "Got TX status for an unavailable "
723                                            "queue %u, dropping\n", qid);
724                         break;
725                 }
726
727                 if (rt2x00queue_empty(queue)) {
728                         /*
729                          * The queue is empty. Stop processing here
730                          * and drop the tx status.
731                          */
732                         WARNING(rt2x00dev, "Got TX status for an empty "
733                                            "queue %u, dropping\n", qid);
734                         break;
735                 }
736
737                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
738                 rt2800_txdone_entry(entry, status);
739         }
740 }
741
742 static void rt2800pci_txstatus_tasklet(unsigned long data)
743 {
744         rt2800pci_txdone((struct rt2x00_dev *)data);
745 }
746
747 static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
748 {
749         struct rt2x00_dev *rt2x00dev = dev_instance;
750         u32 reg = rt2x00dev->irqvalue[0];
751
752         /*
753          * 1 - Pre TBTT interrupt.
754          */
755         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
756                 rt2x00lib_pretbtt(rt2x00dev);
757
758         /*
759          * 2 - Beacondone interrupt.
760          */
761         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
762                 rt2x00lib_beacondone(rt2x00dev);
763
764         /*
765          * 3 - Rx ring done interrupt.
766          */
767         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
768                 rt2x00pci_rxdone(rt2x00dev);
769
770         /*
771          * 4 - Auto wakeup interrupt.
772          */
773         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
774                 rt2800pci_wakeup(rt2x00dev);
775
776         /* Enable interrupts again. */
777         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
778                                               STATE_RADIO_IRQ_ON_ISR);
779
780         return IRQ_HANDLED;
781 }
782
783 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
784 {
785         u32 status;
786         int i;
787
788         /*
789          * The TX_FIFO_STATUS interrupt needs special care. We should
790          * read TX_STA_FIFO but we should do it immediately as otherwise
791          * the register can overflow and we would lose status reports.
792          *
793          * Hence, read the TX_STA_FIFO register and copy all tx status
794          * reports into a kernel FIFO which is handled in the txstatus
795          * tasklet. We use a tasklet to process the tx status reports
796          * because we can schedule the tasklet multiple times (when the
797          * interrupt fires again during tx status processing).
798          *
799          * Furthermore we don't disable the TX_FIFO_STATUS
800          * interrupt here but leave it enabled so that the TX_STA_FIFO
801          * can also be read while the interrupt thread gets executed.
802          *
803          * Since we have only one producer and one consumer we don't
804          * need to lock the kfifo.
805          */
806         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
807                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
808
809                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
810                         break;
811
812                 if (kfifo_is_full(&rt2x00dev->txstatus_fifo)) {
813                         WARNING(rt2x00dev, "TX status FIFO overrun,"
814                                 " drop tx status report.\n");
815                         break;
816                 }
817
818                 if (kfifo_in(&rt2x00dev->txstatus_fifo, &status,
819                              sizeof(status)) != sizeof(status)) {
820                         WARNING(rt2x00dev, "TX status FIFO overrun,"
821                                 "drop tx status report.\n");
822                         break;
823                 }
824         }
825
826         /* Schedule the tasklet for processing the tx status. */
827         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
828 }
829
830 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
831 {
832         struct rt2x00_dev *rt2x00dev = dev_instance;
833         u32 reg;
834         irqreturn_t ret = IRQ_HANDLED;
835
836         /* Read status and ACK all interrupts */
837         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
838         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
839
840         if (!reg)
841                 return IRQ_NONE;
842
843         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
844                 return IRQ_HANDLED;
845
846         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
847                 rt2800pci_txstatus_interrupt(rt2x00dev);
848
849         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT) ||
850             rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT) ||
851             rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE) ||
852             rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) {
853                 /*
854                  * All other interrupts are handled in the interrupt thread.
855                  * Store irqvalue for use in the interrupt thread.
856                  */
857                 rt2x00dev->irqvalue[0] = reg;
858
859                 /*
860                  * Disable interrupts, will be enabled again in the
861                  * interrupt thread.
862                 */
863                 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
864                                                       STATE_RADIO_IRQ_OFF_ISR);
865
866                 /*
867                  * Leave the TX_FIFO_STATUS interrupt enabled to not lose any
868                  * tx status reports.
869                  */
870                 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
871                 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
872                 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
873
874                 ret = IRQ_WAKE_THREAD;
875         }
876
877         return ret;
878 }
879
880 /*
881  * Device probe functions.
882  */
883 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
884 {
885         /*
886          * Read EEPROM into buffer
887          */
888         if (rt2x00_is_soc(rt2x00dev))
889                 rt2800pci_read_eeprom_soc(rt2x00dev);
890         else if (rt2800pci_efuse_detect(rt2x00dev))
891                 rt2800pci_read_eeprom_efuse(rt2x00dev);
892         else
893                 rt2800pci_read_eeprom_pci(rt2x00dev);
894
895         return rt2800_validate_eeprom(rt2x00dev);
896 }
897
898 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
899 {
900         int retval;
901
902         /*
903          * Allocate eeprom data.
904          */
905         retval = rt2800pci_validate_eeprom(rt2x00dev);
906         if (retval)
907                 return retval;
908
909         retval = rt2800_init_eeprom(rt2x00dev);
910         if (retval)
911                 return retval;
912
913         /*
914          * Initialize hw specifications.
915          */
916         retval = rt2800_probe_hw_mode(rt2x00dev);
917         if (retval)
918                 return retval;
919
920         /*
921          * This device has multiple filters for control frames
922          * and has a separate filter for PS Poll frames.
923          */
924         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
925         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
926
927         /*
928          * This device has a pre tbtt interrupt and thus fetches
929          * a new beacon directly prior to transmission.
930          */
931         __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
932
933         /*
934          * This device requires firmware.
935          */
936         if (!rt2x00_is_soc(rt2x00dev))
937                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
938         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
939         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
940         __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
941         __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
942         if (!modparam_nohwcrypt)
943                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
944         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
945
946         /*
947          * Set the rssi offset.
948          */
949         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
950
951         return 0;
952 }
953
954 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
955         .tx                     = rt2x00mac_tx,
956         .start                  = rt2x00mac_start,
957         .stop                   = rt2x00mac_stop,
958         .add_interface          = rt2x00mac_add_interface,
959         .remove_interface       = rt2x00mac_remove_interface,
960         .config                 = rt2x00mac_config,
961         .configure_filter       = rt2x00mac_configure_filter,
962         .set_key                = rt2x00mac_set_key,
963         .sw_scan_start          = rt2x00mac_sw_scan_start,
964         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
965         .get_stats              = rt2x00mac_get_stats,
966         .get_tkip_seq           = rt2800_get_tkip_seq,
967         .set_rts_threshold      = rt2800_set_rts_threshold,
968         .bss_info_changed       = rt2x00mac_bss_info_changed,
969         .conf_tx                = rt2800_conf_tx,
970         .get_tsf                = rt2800_get_tsf,
971         .rfkill_poll            = rt2x00mac_rfkill_poll,
972         .ampdu_action           = rt2800_ampdu_action,
973         .flush                  = rt2x00mac_flush,
974         .get_survey             = rt2800_get_survey,
975 };
976
977 static const struct rt2800_ops rt2800pci_rt2800_ops = {
978         .register_read          = rt2x00pci_register_read,
979         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
980         .register_write         = rt2x00pci_register_write,
981         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
982         .register_multiread     = rt2x00pci_register_multiread,
983         .register_multiwrite    = rt2x00pci_register_multiwrite,
984         .regbusy_read           = rt2x00pci_regbusy_read,
985         .drv_write_firmware     = rt2800pci_write_firmware,
986         .drv_init_registers     = rt2800pci_init_registers,
987         .drv_get_txwi           = rt2800pci_get_txwi,
988 };
989
990 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
991         .irq_handler            = rt2800pci_interrupt,
992         .irq_handler_thread     = rt2800pci_interrupt_thread,
993         .txstatus_tasklet       = rt2800pci_txstatus_tasklet,
994         .probe_hw               = rt2800pci_probe_hw,
995         .get_firmware_name      = rt2800pci_get_firmware_name,
996         .check_firmware         = rt2800_check_firmware,
997         .load_firmware          = rt2800_load_firmware,
998         .initialize             = rt2x00pci_initialize,
999         .uninitialize           = rt2x00pci_uninitialize,
1000         .get_entry_state        = rt2800pci_get_entry_state,
1001         .clear_entry            = rt2800pci_clear_entry,
1002         .set_device_state       = rt2800pci_set_device_state,
1003         .rfkill_poll            = rt2800_rfkill_poll,
1004         .link_stats             = rt2800_link_stats,
1005         .reset_tuner            = rt2800_reset_tuner,
1006         .link_tuner             = rt2800_link_tuner,
1007         .write_tx_desc          = rt2800pci_write_tx_desc,
1008         .write_tx_data          = rt2800_write_tx_data,
1009         .write_beacon           = rt2800_write_beacon,
1010         .kick_tx_queue          = rt2800pci_kick_queue,
1011         .kill_tx_queue          = rt2800pci_stop_queue,
1012         .fill_rxdone            = rt2800pci_fill_rxdone,
1013         .config_shared_key      = rt2800_config_shared_key,
1014         .config_pairwise_key    = rt2800_config_pairwise_key,
1015         .config_filter          = rt2800_config_filter,
1016         .config_intf            = rt2800_config_intf,
1017         .config_erp             = rt2800_config_erp,
1018         .config_ant             = rt2800_config_ant,
1019         .config                 = rt2800_config,
1020 };
1021
1022 static const struct data_queue_desc rt2800pci_queue_rx = {
1023         .entry_num              = 128,
1024         .data_size              = AGGREGATION_SIZE,
1025         .desc_size              = RXD_DESC_SIZE,
1026         .priv_size              = sizeof(struct queue_entry_priv_pci),
1027 };
1028
1029 static const struct data_queue_desc rt2800pci_queue_tx = {
1030         .entry_num              = 64,
1031         .data_size              = AGGREGATION_SIZE,
1032         .desc_size              = TXD_DESC_SIZE,
1033         .priv_size              = sizeof(struct queue_entry_priv_pci),
1034 };
1035
1036 static const struct data_queue_desc rt2800pci_queue_bcn = {
1037         .entry_num              = 8,
1038         .data_size              = 0, /* No DMA required for beacons */
1039         .desc_size              = TXWI_DESC_SIZE,
1040         .priv_size              = sizeof(struct queue_entry_priv_pci),
1041 };
1042
1043 static const struct rt2x00_ops rt2800pci_ops = {
1044         .name                   = KBUILD_MODNAME,
1045         .max_sta_intf           = 1,
1046         .max_ap_intf            = 8,
1047         .eeprom_size            = EEPROM_SIZE,
1048         .rf_size                = RF_SIZE,
1049         .tx_queues              = NUM_TX_QUEUES,
1050         .extra_tx_headroom      = TXWI_DESC_SIZE,
1051         .rx                     = &rt2800pci_queue_rx,
1052         .tx                     = &rt2800pci_queue_tx,
1053         .bcn                    = &rt2800pci_queue_bcn,
1054         .lib                    = &rt2800pci_rt2x00_ops,
1055         .drv                    = &rt2800pci_rt2800_ops,
1056         .hw                     = &rt2800pci_mac80211_ops,
1057 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1058         .debugfs                = &rt2800_rt2x00debug,
1059 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1060 };
1061
1062 /*
1063  * RT2800pci module information.
1064  */
1065 #ifdef CONFIG_PCI
1066 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1067         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1068         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1069         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1070         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1071         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1072         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1073         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1074         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1075         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1076         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1077         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1078         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1079         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1080         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1081         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1082         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1083 #ifdef CONFIG_RT2800PCI_RT33XX
1084         { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1085 #endif
1086 #ifdef CONFIG_RT2800PCI_RT35XX
1087         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1088         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1089         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1090         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1091         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1092 #endif
1093         { 0, }
1094 };
1095 #endif /* CONFIG_PCI */
1096
1097 MODULE_AUTHOR(DRV_PROJECT);
1098 MODULE_VERSION(DRV_VERSION);
1099 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1100 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1101 #ifdef CONFIG_PCI
1102 MODULE_FIRMWARE(FIRMWARE_RT2860);
1103 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1104 #endif /* CONFIG_PCI */
1105 MODULE_LICENSE("GPL");
1106
1107 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1108 static int rt2800soc_probe(struct platform_device *pdev)
1109 {
1110         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1111 }
1112
1113 static struct platform_driver rt2800soc_driver = {
1114         .driver         = {
1115                 .name           = "rt2800_wmac",
1116                 .owner          = THIS_MODULE,
1117                 .mod_name       = KBUILD_MODNAME,
1118         },
1119         .probe          = rt2800soc_probe,
1120         .remove         = __devexit_p(rt2x00soc_remove),
1121         .suspend        = rt2x00soc_suspend,
1122         .resume         = rt2x00soc_resume,
1123 };
1124 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1125
1126 #ifdef CONFIG_PCI
1127 static struct pci_driver rt2800pci_driver = {
1128         .name           = KBUILD_MODNAME,
1129         .id_table       = rt2800pci_device_table,
1130         .probe          = rt2x00pci_probe,
1131         .remove         = __devexit_p(rt2x00pci_remove),
1132         .suspend        = rt2x00pci_suspend,
1133         .resume         = rt2x00pci_resume,
1134 };
1135 #endif /* CONFIG_PCI */
1136
1137 static int __init rt2800pci_init(void)
1138 {
1139         int ret = 0;
1140
1141 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1142         ret = platform_driver_register(&rt2800soc_driver);
1143         if (ret)
1144                 return ret;
1145 #endif
1146 #ifdef CONFIG_PCI
1147         ret = pci_register_driver(&rt2800pci_driver);
1148         if (ret) {
1149 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1150                 platform_driver_unregister(&rt2800soc_driver);
1151 #endif
1152                 return ret;
1153         }
1154 #endif
1155
1156         return ret;
1157 }
1158
1159 static void __exit rt2800pci_exit(void)
1160 {
1161 #ifdef CONFIG_PCI
1162         pci_unregister_driver(&rt2800pci_driver);
1163 #endif
1164 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1165         platform_driver_unregister(&rt2800soc_driver);
1166 #endif
1167 }
1168
1169 module_init(rt2800pci_init);
1170 module_exit(rt2800pci_exit);