rt2x00: Refactor beacon code to make use of start- and stop_queue
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
1 /*
2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10         <http://rt2x00.serialmonkey.com>
11
12         This program is free software; you can redistribute it and/or modify
13         it under the terms of the GNU General Public License as published by
14         the Free Software Foundation; either version 2 of the License, or
15         (at your option) any later version.
16
17         This program is distributed in the hope that it will be useful,
18         but WITHOUT ANY WARRANTY; without even the implied warranty of
19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20         GNU General Public License for more details.
21
22         You should have received a copy of the GNU General Public License
23         along with this program; if not, write to the
24         Free Software Foundation, Inc.,
25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26  */
27
28 /*
29         Module: rt2800pci
30         Abstract: rt2800pci device specific routines.
31         Supported chipsets: RT2800E & RT2800ED.
32  */
33
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
42
43 #include "rt2x00.h"
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
47 #include "rt2800.h"
48 #include "rt2800pci.h"
49
50 /*
51  * Allow hardware encryption to be disabled.
52  */
53 static int modparam_nohwcrypt = 0;
54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58 {
59         unsigned int i;
60         u32 reg;
61
62         /*
63          * SOC devices don't support MCU requests.
64          */
65         if (rt2x00_is_soc(rt2x00dev))
66                 return;
67
68         for (i = 0; i < 200; i++) {
69                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
70
71                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75                         break;
76
77                 udelay(REGISTER_BUSY_DELAY);
78         }
79
80         if (i == 200)
81                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
83         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
85 }
86
87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89 {
90         void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
91
92         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
93
94         iounmap(base_addr);
95 }
96 #else
97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
98 {
99 }
100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
101
102 #ifdef CONFIG_PCI
103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
104 {
105         struct rt2x00_dev *rt2x00dev = eeprom->data;
106         u32 reg;
107
108         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
109
110         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112         eeprom->reg_data_clock =
113             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114         eeprom->reg_chip_select =
115             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
116 }
117
118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
119 {
120         struct rt2x00_dev *rt2x00dev = eeprom->data;
121         u32 reg = 0;
122
123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
126                            !!eeprom->reg_data_clock);
127         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
128                            !!eeprom->reg_chip_select);
129
130         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
131 }
132
133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
134 {
135         struct eeprom_93cx6 eeprom;
136         u32 reg;
137
138         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
139
140         eeprom.data = rt2x00dev;
141         eeprom.register_read = rt2800pci_eepromregister_read;
142         eeprom.register_write = rt2800pci_eepromregister_write;
143         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
144         {
145         case 0:
146                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
147                 break;
148         case 1:
149                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
150                 break;
151         default:
152                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
153                 break;
154         }
155         eeprom.reg_data_in = 0;
156         eeprom.reg_data_out = 0;
157         eeprom.reg_data_clock = 0;
158         eeprom.reg_chip_select = 0;
159
160         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161                                EEPROM_SIZE / sizeof(u16));
162 }
163
164 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
165 {
166         return rt2800_efuse_detect(rt2x00dev);
167 }
168
169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
170 {
171         rt2800_read_eeprom_efuse(rt2x00dev);
172 }
173 #else
174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
175 {
176 }
177
178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179 {
180         return 0;
181 }
182
183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
184 {
185 }
186 #endif /* CONFIG_PCI */
187
188 /*
189  * Queue handlers.
190  */
191 static void rt2800pci_start_queue(struct data_queue *queue)
192 {
193         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
194         u32 reg;
195
196         switch (queue->qid) {
197         case QID_RX:
198                 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
199                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
200                 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
201                 break;
202         case QID_BEACON:
203                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
204                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
205                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
206                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
207                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
208
209                 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
210                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
211                 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
212                 break;
213         default:
214                 break;
215         };
216 }
217
218 static void rt2800pci_kick_queue(struct data_queue *queue)
219 {
220         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
221         struct queue_entry *entry;
222
223         switch (queue->qid) {
224         case QID_AC_VO:
225         case QID_AC_VI:
226         case QID_AC_BE:
227         case QID_AC_BK:
228                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
229                 rt2800_register_write(rt2x00dev, TX_CTX_IDX(queue->qid), entry->entry_idx);
230                 break;
231         case QID_MGMT:
232                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
233                 rt2800_register_write(rt2x00dev, TX_CTX_IDX(5), entry->entry_idx);
234                 break;
235         default:
236                 break;
237         }
238 }
239
240 static void rt2800pci_stop_queue(struct data_queue *queue)
241 {
242         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
243         u32 reg;
244
245         switch (queue->qid) {
246         case QID_RX:
247                 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
248                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
249                 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
250                 break;
251         case QID_BEACON:
252                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
253                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
254                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
255                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
256                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
257
258                 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
259                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
260                 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
261                 break;
262         default:
263                 break;
264         }
265 }
266
267 /*
268  * Firmware functions
269  */
270 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
271 {
272         return FIRMWARE_RT2860;
273 }
274
275 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
276                                     const u8 *data, const size_t len)
277 {
278         u32 reg;
279
280         /*
281          * enable Host program ram write selection
282          */
283         reg = 0;
284         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
285         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
286
287         /*
288          * Write firmware to device.
289          */
290         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
291                                    data, len);
292
293         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
294         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
295
296         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
297         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
298
299         return 0;
300 }
301
302 /*
303  * Initialization functions.
304  */
305 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
306 {
307         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
308         u32 word;
309
310         if (entry->queue->qid == QID_RX) {
311                 rt2x00_desc_read(entry_priv->desc, 1, &word);
312
313                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
314         } else {
315                 rt2x00_desc_read(entry_priv->desc, 1, &word);
316
317                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
318         }
319 }
320
321 static void rt2800pci_clear_entry(struct queue_entry *entry)
322 {
323         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
324         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
325         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
326         u32 word;
327
328         if (entry->queue->qid == QID_RX) {
329                 rt2x00_desc_read(entry_priv->desc, 0, &word);
330                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
331                 rt2x00_desc_write(entry_priv->desc, 0, word);
332
333                 rt2x00_desc_read(entry_priv->desc, 1, &word);
334                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
335                 rt2x00_desc_write(entry_priv->desc, 1, word);
336
337                 /*
338                  * Set RX IDX in register to inform hardware that we have
339                  * handled this entry and it is available for reuse again.
340                  */
341                 rt2800_register_write(rt2x00dev, RX_CRX_IDX,
342                                       entry->entry_idx);
343         } else {
344                 rt2x00_desc_read(entry_priv->desc, 1, &word);
345                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
346                 rt2x00_desc_write(entry_priv->desc, 1, word);
347         }
348 }
349
350 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
351 {
352         struct queue_entry_priv_pci *entry_priv;
353         u32 reg;
354
355         /*
356          * Initialize registers.
357          */
358         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
359         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
360         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
361         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
362         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
363
364         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
365         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
366         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
367         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
368         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
369
370         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
371         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
372         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
373         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
374         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
375
376         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
377         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
378         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
379         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
380         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
381
382         entry_priv = rt2x00dev->rx->entries[0].priv_data;
383         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
384         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
385         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
386         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
387
388         /*
389          * Enable global DMA configuration
390          */
391         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
392         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
393         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
394         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
395         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
396
397         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
398
399         return 0;
400 }
401
402 /*
403  * Device state switch handlers.
404  */
405 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
406                                  enum dev_state state)
407 {
408         int mask = (state == STATE_RADIO_IRQ_ON) ||
409                    (state == STATE_RADIO_IRQ_ON_ISR);
410         u32 reg;
411
412         /*
413          * When interrupts are being enabled, the interrupt registers
414          * should clear the register to assure a clean state.
415          */
416         if (state == STATE_RADIO_IRQ_ON) {
417                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
418                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
419         }
420
421         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
422         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
423         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
424         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
425         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
426         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
427         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
428         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
429         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
430         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
431         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
432         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
433         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
434         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
435         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
436         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
437         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
438         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
439         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
440         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
441 }
442
443 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
444 {
445         u32 reg;
446
447         /*
448          * Reset DMA indexes
449          */
450         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
451         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
452         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
453         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
454         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
455         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
456         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
457         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
458         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
459
460         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
461         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
462
463         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
464
465         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
466         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
467         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
468         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
469
470         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
471
472         return 0;
473 }
474
475 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
476 {
477         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
478                      rt2800pci_init_queues(rt2x00dev)))
479                 return -EIO;
480
481         return rt2800_enable_radio(rt2x00dev);
482 }
483
484 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
485 {
486         if (rt2x00_is_soc(rt2x00dev)) {
487                 rt2800_disable_radio(rt2x00dev);
488                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
489                 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
490         }
491 }
492
493 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
494                                enum dev_state state)
495 {
496         if (state == STATE_AWAKE) {
497                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
498                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
499         } else if (state == STATE_SLEEP) {
500                 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, 0xffffffff);
501                 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, 0xffffffff);
502                 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
503         }
504
505         return 0;
506 }
507
508 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
509                                       enum dev_state state)
510 {
511         int retval = 0;
512
513         switch (state) {
514         case STATE_RADIO_ON:
515                 /*
516                  * Before the radio can be enabled, the device first has
517                  * to be woken up. After that it needs a bit of time
518                  * to be fully awake and then the radio can be enabled.
519                  */
520                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
521                 msleep(1);
522                 retval = rt2800pci_enable_radio(rt2x00dev);
523                 break;
524         case STATE_RADIO_OFF:
525                 /*
526                  * After the radio has been disabled, the device should
527                  * be put to sleep for powersaving.
528                  */
529                 rt2800pci_disable_radio(rt2x00dev);
530                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
531                 break;
532         case STATE_RADIO_IRQ_ON:
533         case STATE_RADIO_IRQ_ON_ISR:
534         case STATE_RADIO_IRQ_OFF:
535         case STATE_RADIO_IRQ_OFF_ISR:
536                 rt2800pci_toggle_irq(rt2x00dev, state);
537                 break;
538         case STATE_DEEP_SLEEP:
539         case STATE_SLEEP:
540         case STATE_STANDBY:
541         case STATE_AWAKE:
542                 retval = rt2800pci_set_state(rt2x00dev, state);
543                 break;
544         default:
545                 retval = -ENOTSUPP;
546                 break;
547         }
548
549         if (unlikely(retval))
550                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
551                       state, retval);
552
553         return retval;
554 }
555
556 /*
557  * TX descriptor initialization
558  */
559 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
560 {
561         return (__le32 *) entry->skb->data;
562 }
563
564 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
565                                     struct txentry_desc *txdesc)
566 {
567         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
568         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
569         __le32 *txd = entry_priv->desc;
570         u32 word;
571
572         /*
573          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
574          * must contains a TXWI structure + 802.11 header + padding + 802.11
575          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
576          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
577          * data. It means that LAST_SEC0 is always 0.
578          */
579
580         /*
581          * Initialize TX descriptor
582          */
583         rt2x00_desc_read(txd, 0, &word);
584         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
585         rt2x00_desc_write(txd, 0, word);
586
587         rt2x00_desc_read(txd, 1, &word);
588         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
589         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
590                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
591         rt2x00_set_field32(&word, TXD_W1_BURST,
592                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
593         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
594         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
595         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
596         rt2x00_desc_write(txd, 1, word);
597
598         rt2x00_desc_read(txd, 2, &word);
599         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
600                            skbdesc->skb_dma + TXWI_DESC_SIZE);
601         rt2x00_desc_write(txd, 2, word);
602
603         rt2x00_desc_read(txd, 3, &word);
604         rt2x00_set_field32(&word, TXD_W3_WIV,
605                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
606         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
607         rt2x00_desc_write(txd, 3, word);
608
609         /*
610          * Register descriptor details in skb frame descriptor.
611          */
612         skbdesc->desc = txd;
613         skbdesc->desc_len = TXD_DESC_SIZE;
614 }
615
616 /*
617  * RX control handlers
618  */
619 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
620                                   struct rxdone_entry_desc *rxdesc)
621 {
622         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
623         __le32 *rxd = entry_priv->desc;
624         u32 word;
625
626         rt2x00_desc_read(rxd, 3, &word);
627
628         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
629                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
630
631         /*
632          * Unfortunately we don't know the cipher type used during
633          * decryption. This prevents us from correct providing
634          * correct statistics through debugfs.
635          */
636         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
637
638         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
639                 /*
640                  * Hardware has stripped IV/EIV data from 802.11 frame during
641                  * decryption. Unfortunately the descriptor doesn't contain
642                  * any fields with the EIV/IV data either, so they can't
643                  * be restored by rt2x00lib.
644                  */
645                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
646
647                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
648                         rxdesc->flags |= RX_FLAG_DECRYPTED;
649                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
650                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
651         }
652
653         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
654                 rxdesc->dev_flags |= RXDONE_MY_BSS;
655
656         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
657                 rxdesc->dev_flags |= RXDONE_L2PAD;
658
659         /*
660          * Process the RXWI structure that is at the start of the buffer.
661          */
662         rt2800_process_rxwi(entry, rxdesc);
663 }
664
665 /*
666  * Interrupt functions.
667  */
668 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
669 {
670         struct ieee80211_conf conf = { .flags = 0 };
671         struct rt2x00lib_conf libconf = { .conf = &conf };
672
673         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
674 }
675
676 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
677 {
678         struct data_queue *queue;
679         struct queue_entry *entry;
680         u32 status;
681         u8 qid;
682
683         while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
684                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
685                 if (qid >= QID_RX) {
686                         /*
687                          * Unknown queue, this shouldn't happen. Just drop
688                          * this tx status.
689                          */
690                         WARNING(rt2x00dev, "Got TX status report with "
691                                            "unexpected pid %u, dropping\n", qid);
692                         break;
693                 }
694
695                 queue = rt2x00queue_get_queue(rt2x00dev, qid);
696                 if (unlikely(queue == NULL)) {
697                         /*
698                          * The queue is NULL, this shouldn't happen. Stop
699                          * processing here and drop the tx status
700                          */
701                         WARNING(rt2x00dev, "Got TX status for an unavailable "
702                                            "queue %u, dropping\n", qid);
703                         break;
704                 }
705
706                 if (rt2x00queue_empty(queue)) {
707                         /*
708                          * The queue is empty. Stop processing here
709                          * and drop the tx status.
710                          */
711                         WARNING(rt2x00dev, "Got TX status for an empty "
712                                            "queue %u, dropping\n", qid);
713                         break;
714                 }
715
716                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
717                 rt2800_txdone_entry(entry, status);
718         }
719 }
720
721 static void rt2800pci_txstatus_tasklet(unsigned long data)
722 {
723         rt2800pci_txdone((struct rt2x00_dev *)data);
724 }
725
726 static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
727 {
728         struct rt2x00_dev *rt2x00dev = dev_instance;
729         u32 reg = rt2x00dev->irqvalue[0];
730
731         /*
732          * 1 - Pre TBTT interrupt.
733          */
734         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
735                 rt2x00lib_pretbtt(rt2x00dev);
736
737         /*
738          * 2 - Beacondone interrupt.
739          */
740         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
741                 rt2x00lib_beacondone(rt2x00dev);
742
743         /*
744          * 3 - Rx ring done interrupt.
745          */
746         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
747                 rt2x00pci_rxdone(rt2x00dev);
748
749         /*
750          * 4 - Auto wakeup interrupt.
751          */
752         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
753                 rt2800pci_wakeup(rt2x00dev);
754
755         /* Enable interrupts again. */
756         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
757                                               STATE_RADIO_IRQ_ON_ISR);
758
759         return IRQ_HANDLED;
760 }
761
762 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
763 {
764         u32 status;
765         int i;
766
767         /*
768          * The TX_FIFO_STATUS interrupt needs special care. We should
769          * read TX_STA_FIFO but we should do it immediately as otherwise
770          * the register can overflow and we would lose status reports.
771          *
772          * Hence, read the TX_STA_FIFO register and copy all tx status
773          * reports into a kernel FIFO which is handled in the txstatus
774          * tasklet. We use a tasklet to process the tx status reports
775          * because we can schedule the tasklet multiple times (when the
776          * interrupt fires again during tx status processing).
777          *
778          * Furthermore we don't disable the TX_FIFO_STATUS
779          * interrupt here but leave it enabled so that the TX_STA_FIFO
780          * can also be read while the interrupt thread gets executed.
781          *
782          * Since we have only one producer and one consumer we don't
783          * need to lock the kfifo.
784          */
785         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
786                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
787
788                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
789                         break;
790
791                 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
792                         WARNING(rt2x00dev, "TX status FIFO overrun,"
793                                 "drop tx status report.\n");
794                         break;
795                 }
796         }
797
798         /* Schedule the tasklet for processing the tx status. */
799         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
800 }
801
802 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
803 {
804         struct rt2x00_dev *rt2x00dev = dev_instance;
805         u32 reg;
806         irqreturn_t ret = IRQ_HANDLED;
807
808         /* Read status and ACK all interrupts */
809         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
810         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
811
812         if (!reg)
813                 return IRQ_NONE;
814
815         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
816                 return IRQ_HANDLED;
817
818         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
819                 rt2800pci_txstatus_interrupt(rt2x00dev);
820
821         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT) ||
822             rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT) ||
823             rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE) ||
824             rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) {
825                 /*
826                  * All other interrupts are handled in the interrupt thread.
827                  * Store irqvalue for use in the interrupt thread.
828                  */
829                 rt2x00dev->irqvalue[0] = reg;
830
831                 /*
832                  * Disable interrupts, will be enabled again in the
833                  * interrupt thread.
834                 */
835                 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
836                                                       STATE_RADIO_IRQ_OFF_ISR);
837
838                 /*
839                  * Leave the TX_FIFO_STATUS interrupt enabled to not lose any
840                  * tx status reports.
841                  */
842                 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
843                 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
844                 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
845
846                 ret = IRQ_WAKE_THREAD;
847         }
848
849         return ret;
850 }
851
852 /*
853  * Device probe functions.
854  */
855 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
856 {
857         /*
858          * Read EEPROM into buffer
859          */
860         if (rt2x00_is_soc(rt2x00dev))
861                 rt2800pci_read_eeprom_soc(rt2x00dev);
862         else if (rt2800pci_efuse_detect(rt2x00dev))
863                 rt2800pci_read_eeprom_efuse(rt2x00dev);
864         else
865                 rt2800pci_read_eeprom_pci(rt2x00dev);
866
867         return rt2800_validate_eeprom(rt2x00dev);
868 }
869
870 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
871 {
872         int retval;
873
874         /*
875          * Allocate eeprom data.
876          */
877         retval = rt2800pci_validate_eeprom(rt2x00dev);
878         if (retval)
879                 return retval;
880
881         retval = rt2800_init_eeprom(rt2x00dev);
882         if (retval)
883                 return retval;
884
885         /*
886          * Initialize hw specifications.
887          */
888         retval = rt2800_probe_hw_mode(rt2x00dev);
889         if (retval)
890                 return retval;
891
892         /*
893          * This device has multiple filters for control frames
894          * and has a separate filter for PS Poll frames.
895          */
896         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
897         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
898
899         /*
900          * This device has a pre tbtt interrupt and thus fetches
901          * a new beacon directly prior to transmission.
902          */
903         __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
904
905         /*
906          * This device requires firmware.
907          */
908         if (!rt2x00_is_soc(rt2x00dev))
909                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
910         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
911         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
912         __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
913         __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
914         if (!modparam_nohwcrypt)
915                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
916         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
917
918         /*
919          * Set the rssi offset.
920          */
921         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
922
923         return 0;
924 }
925
926 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
927         .tx                     = rt2x00mac_tx,
928         .start                  = rt2x00mac_start,
929         .stop                   = rt2x00mac_stop,
930         .add_interface          = rt2x00mac_add_interface,
931         .remove_interface       = rt2x00mac_remove_interface,
932         .config                 = rt2x00mac_config,
933         .configure_filter       = rt2x00mac_configure_filter,
934         .set_key                = rt2x00mac_set_key,
935         .sw_scan_start          = rt2x00mac_sw_scan_start,
936         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
937         .get_stats              = rt2x00mac_get_stats,
938         .get_tkip_seq           = rt2800_get_tkip_seq,
939         .set_rts_threshold      = rt2800_set_rts_threshold,
940         .bss_info_changed       = rt2x00mac_bss_info_changed,
941         .conf_tx                = rt2800_conf_tx,
942         .get_tsf                = rt2800_get_tsf,
943         .rfkill_poll            = rt2x00mac_rfkill_poll,
944         .ampdu_action           = rt2800_ampdu_action,
945         .flush                  = rt2x00mac_flush,
946         .get_survey             = rt2800_get_survey,
947 };
948
949 static const struct rt2800_ops rt2800pci_rt2800_ops = {
950         .register_read          = rt2x00pci_register_read,
951         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
952         .register_write         = rt2x00pci_register_write,
953         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
954         .register_multiread     = rt2x00pci_register_multiread,
955         .register_multiwrite    = rt2x00pci_register_multiwrite,
956         .regbusy_read           = rt2x00pci_regbusy_read,
957         .drv_write_firmware     = rt2800pci_write_firmware,
958         .drv_init_registers     = rt2800pci_init_registers,
959         .drv_get_txwi           = rt2800pci_get_txwi,
960 };
961
962 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
963         .irq_handler            = rt2800pci_interrupt,
964         .irq_handler_thread     = rt2800pci_interrupt_thread,
965         .txstatus_tasklet       = rt2800pci_txstatus_tasklet,
966         .probe_hw               = rt2800pci_probe_hw,
967         .get_firmware_name      = rt2800pci_get_firmware_name,
968         .check_firmware         = rt2800_check_firmware,
969         .load_firmware          = rt2800_load_firmware,
970         .initialize             = rt2x00pci_initialize,
971         .uninitialize           = rt2x00pci_uninitialize,
972         .get_entry_state        = rt2800pci_get_entry_state,
973         .clear_entry            = rt2800pci_clear_entry,
974         .set_device_state       = rt2800pci_set_device_state,
975         .rfkill_poll            = rt2800_rfkill_poll,
976         .link_stats             = rt2800_link_stats,
977         .reset_tuner            = rt2800_reset_tuner,
978         .link_tuner             = rt2800_link_tuner,
979         .start_queue            = rt2800pci_start_queue,
980         .kick_queue             = rt2800pci_kick_queue,
981         .stop_queue             = rt2800pci_stop_queue,
982         .write_tx_desc          = rt2800pci_write_tx_desc,
983         .write_tx_data          = rt2800_write_tx_data,
984         .write_beacon           = rt2800_write_beacon,
985         .clear_beacon           = rt2800_clear_beacon,
986         .fill_rxdone            = rt2800pci_fill_rxdone,
987         .config_shared_key      = rt2800_config_shared_key,
988         .config_pairwise_key    = rt2800_config_pairwise_key,
989         .config_filter          = rt2800_config_filter,
990         .config_intf            = rt2800_config_intf,
991         .config_erp             = rt2800_config_erp,
992         .config_ant             = rt2800_config_ant,
993         .config                 = rt2800_config,
994 };
995
996 static const struct data_queue_desc rt2800pci_queue_rx = {
997         .entry_num              = 128,
998         .data_size              = AGGREGATION_SIZE,
999         .desc_size              = RXD_DESC_SIZE,
1000         .priv_size              = sizeof(struct queue_entry_priv_pci),
1001 };
1002
1003 static const struct data_queue_desc rt2800pci_queue_tx = {
1004         .entry_num              = 64,
1005         .data_size              = AGGREGATION_SIZE,
1006         .desc_size              = TXD_DESC_SIZE,
1007         .priv_size              = sizeof(struct queue_entry_priv_pci),
1008 };
1009
1010 static const struct data_queue_desc rt2800pci_queue_bcn = {
1011         .entry_num              = 8,
1012         .data_size              = 0, /* No DMA required for beacons */
1013         .desc_size              = TXWI_DESC_SIZE,
1014         .priv_size              = sizeof(struct queue_entry_priv_pci),
1015 };
1016
1017 static const struct rt2x00_ops rt2800pci_ops = {
1018         .name                   = KBUILD_MODNAME,
1019         .max_sta_intf           = 1,
1020         .max_ap_intf            = 8,
1021         .eeprom_size            = EEPROM_SIZE,
1022         .rf_size                = RF_SIZE,
1023         .tx_queues              = NUM_TX_QUEUES,
1024         .extra_tx_headroom      = TXWI_DESC_SIZE,
1025         .rx                     = &rt2800pci_queue_rx,
1026         .tx                     = &rt2800pci_queue_tx,
1027         .bcn                    = &rt2800pci_queue_bcn,
1028         .lib                    = &rt2800pci_rt2x00_ops,
1029         .drv                    = &rt2800pci_rt2800_ops,
1030         .hw                     = &rt2800pci_mac80211_ops,
1031 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1032         .debugfs                = &rt2800_rt2x00debug,
1033 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1034 };
1035
1036 /*
1037  * RT2800pci module information.
1038  */
1039 #ifdef CONFIG_PCI
1040 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1041         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1042         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1043         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1044         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1045         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1046         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1047         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1048         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1049         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1050         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1051         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1052         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1053         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1054         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1055         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1056         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1057 #ifdef CONFIG_RT2800PCI_RT33XX
1058         { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1059 #endif
1060 #ifdef CONFIG_RT2800PCI_RT35XX
1061         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1062         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1063         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1064         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1065         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1066 #endif
1067         { 0, }
1068 };
1069 #endif /* CONFIG_PCI */
1070
1071 MODULE_AUTHOR(DRV_PROJECT);
1072 MODULE_VERSION(DRV_VERSION);
1073 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1074 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1075 #ifdef CONFIG_PCI
1076 MODULE_FIRMWARE(FIRMWARE_RT2860);
1077 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1078 #endif /* CONFIG_PCI */
1079 MODULE_LICENSE("GPL");
1080
1081 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1082 static int rt2800soc_probe(struct platform_device *pdev)
1083 {
1084         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1085 }
1086
1087 static struct platform_driver rt2800soc_driver = {
1088         .driver         = {
1089                 .name           = "rt2800_wmac",
1090                 .owner          = THIS_MODULE,
1091                 .mod_name       = KBUILD_MODNAME,
1092         },
1093         .probe          = rt2800soc_probe,
1094         .remove         = __devexit_p(rt2x00soc_remove),
1095         .suspend        = rt2x00soc_suspend,
1096         .resume         = rt2x00soc_resume,
1097 };
1098 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1099
1100 #ifdef CONFIG_PCI
1101 static struct pci_driver rt2800pci_driver = {
1102         .name           = KBUILD_MODNAME,
1103         .id_table       = rt2800pci_device_table,
1104         .probe          = rt2x00pci_probe,
1105         .remove         = __devexit_p(rt2x00pci_remove),
1106         .suspend        = rt2x00pci_suspend,
1107         .resume         = rt2x00pci_resume,
1108 };
1109 #endif /* CONFIG_PCI */
1110
1111 static int __init rt2800pci_init(void)
1112 {
1113         int ret = 0;
1114
1115 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1116         ret = platform_driver_register(&rt2800soc_driver);
1117         if (ret)
1118                 return ret;
1119 #endif
1120 #ifdef CONFIG_PCI
1121         ret = pci_register_driver(&rt2800pci_driver);
1122         if (ret) {
1123 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1124                 platform_driver_unregister(&rt2800soc_driver);
1125 #endif
1126                 return ret;
1127         }
1128 #endif
1129
1130         return ret;
1131 }
1132
1133 static void __exit rt2800pci_exit(void)
1134 {
1135 #ifdef CONFIG_PCI
1136         pci_unregister_driver(&rt2800pci_driver);
1137 #endif
1138 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1139         platform_driver_unregister(&rt2800soc_driver);
1140 #endif
1141 }
1142
1143 module_init(rt2800pci_init);
1144 module_exit(rt2800pci_exit);