49447222e40f5377002edc11c853ac7835e662ed
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800pci.c
1 /*
2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10         <http://rt2x00.serialmonkey.com>
11
12         This program is free software; you can redistribute it and/or modify
13         it under the terms of the GNU General Public License as published by
14         the Free Software Foundation; either version 2 of the License, or
15         (at your option) any later version.
16
17         This program is distributed in the hope that it will be useful,
18         but WITHOUT ANY WARRANTY; without even the implied warranty of
19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20         GNU General Public License for more details.
21
22         You should have received a copy of the GNU General Public License
23         along with this program; if not, write to the
24         Free Software Foundation, Inc.,
25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26  */
27
28 /*
29         Module: rt2800pci
30         Abstract: rt2800pci device specific routines.
31         Supported chipsets: RT2800E & RT2800ED.
32  */
33
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
42
43 #include "rt2x00.h"
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
47 #include "rt2800.h"
48 #include "rt2800pci.h"
49
50 /*
51  * Allow hardware encryption to be disabled.
52  */
53 static int modparam_nohwcrypt = 0;
54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56
57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
58 {
59         unsigned int i;
60         u32 reg;
61
62         /*
63          * SOC devices don't support MCU requests.
64          */
65         if (rt2x00_is_soc(rt2x00dev))
66                 return;
67
68         for (i = 0; i < 200; i++) {
69                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
70
71                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
75                         break;
76
77                 udelay(REGISTER_BUSY_DELAY);
78         }
79
80         if (i == 200)
81                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
82
83         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
85 }
86
87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
89 {
90         void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
91
92         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
93
94         iounmap(base_addr);
95 }
96 #else
97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
98 {
99 }
100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
101
102 #ifdef CONFIG_PCI
103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
104 {
105         struct rt2x00_dev *rt2x00dev = eeprom->data;
106         u32 reg;
107
108         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
109
110         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112         eeprom->reg_data_clock =
113             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114         eeprom->reg_chip_select =
115             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
116 }
117
118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
119 {
120         struct rt2x00_dev *rt2x00dev = eeprom->data;
121         u32 reg = 0;
122
123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
126                            !!eeprom->reg_data_clock);
127         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
128                            !!eeprom->reg_chip_select);
129
130         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
131 }
132
133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
134 {
135         struct eeprom_93cx6 eeprom;
136         u32 reg;
137
138         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
139
140         eeprom.data = rt2x00dev;
141         eeprom.register_read = rt2800pci_eepromregister_read;
142         eeprom.register_write = rt2800pci_eepromregister_write;
143         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
144         {
145         case 0:
146                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
147                 break;
148         case 1:
149                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
150                 break;
151         default:
152                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
153                 break;
154         }
155         eeprom.reg_data_in = 0;
156         eeprom.reg_data_out = 0;
157         eeprom.reg_data_clock = 0;
158         eeprom.reg_chip_select = 0;
159
160         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161                                EEPROM_SIZE / sizeof(u16));
162 }
163
164 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
165 {
166         return rt2800_efuse_detect(rt2x00dev);
167 }
168
169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
170 {
171         rt2800_read_eeprom_efuse(rt2x00dev);
172 }
173 #else
174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
175 {
176 }
177
178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
179 {
180         return 0;
181 }
182
183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
184 {
185 }
186 #endif /* CONFIG_PCI */
187
188 /*
189  * Firmware functions
190  */
191 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
192 {
193         return FIRMWARE_RT2860;
194 }
195
196 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
197                                     const u8 *data, const size_t len)
198 {
199         u32 reg;
200
201         /*
202          * enable Host program ram write selection
203          */
204         reg = 0;
205         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
206         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
207
208         /*
209          * Write firmware to device.
210          */
211         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
212                                    data, len);
213
214         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
215         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
216
217         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
218         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
219
220         return 0;
221 }
222
223 /*
224  * Initialization functions.
225  */
226 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
227 {
228         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
229         u32 word;
230
231         if (entry->queue->qid == QID_RX) {
232                 rt2x00_desc_read(entry_priv->desc, 1, &word);
233
234                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
235         } else {
236                 rt2x00_desc_read(entry_priv->desc, 1, &word);
237
238                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
239         }
240 }
241
242 static void rt2800pci_clear_entry(struct queue_entry *entry)
243 {
244         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
245         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
246         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
247         u32 word;
248
249         if (entry->queue->qid == QID_RX) {
250                 rt2x00_desc_read(entry_priv->desc, 0, &word);
251                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
252                 rt2x00_desc_write(entry_priv->desc, 0, word);
253
254                 rt2x00_desc_read(entry_priv->desc, 1, &word);
255                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
256                 rt2x00_desc_write(entry_priv->desc, 1, word);
257
258                 /*
259                  * Set RX IDX in register to inform hardware that we have
260                  * handled this entry and it is available for reuse again.
261                  */
262                 rt2800_register_write(rt2x00dev, RX_CRX_IDX,
263                                       entry->entry_idx);
264         } else {
265                 rt2x00_desc_read(entry_priv->desc, 1, &word);
266                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
267                 rt2x00_desc_write(entry_priv->desc, 1, word);
268         }
269 }
270
271 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
272 {
273         struct queue_entry_priv_pci *entry_priv;
274         u32 reg;
275
276         /*
277          * Initialize registers.
278          */
279         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
280         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
281         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
282         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
283         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
284
285         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
286         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
287         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
288         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
289         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
290
291         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
292         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
293         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
294         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
295         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
296
297         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
298         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
299         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
300         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
301         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
302
303         entry_priv = rt2x00dev->rx->entries[0].priv_data;
304         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
305         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
306         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
307         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
308
309         /*
310          * Enable global DMA configuration
311          */
312         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
313         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
314         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
315         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
316         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
317
318         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
319
320         return 0;
321 }
322
323 /*
324  * Device state switch handlers.
325  */
326 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
327                                 enum dev_state state)
328 {
329         u32 reg;
330
331         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
332         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
333                            (state == STATE_RADIO_RX_ON));
334         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
335 }
336
337 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
338                                  enum dev_state state)
339 {
340         int mask = (state == STATE_RADIO_IRQ_ON) ||
341                    (state == STATE_RADIO_IRQ_ON_ISR);
342         u32 reg;
343
344         /*
345          * When interrupts are being enabled, the interrupt registers
346          * should clear the register to assure a clean state.
347          */
348         if (state == STATE_RADIO_IRQ_ON) {
349                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
350                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
351         }
352
353         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
354         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
355         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
356         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
357         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
358         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
359         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
360         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
361         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
362         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
363         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
364         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
365         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
366         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
367         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
368         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
369         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
370         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
371         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
372         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
373 }
374
375 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
376 {
377         u32 reg;
378
379         /*
380          * Reset DMA indexes
381          */
382         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
383         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
384         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
385         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
386         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
387         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
388         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
389         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
390         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
391
392         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
393         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
394
395         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
396
397         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
398         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
399         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
400         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
401
402         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
403
404         return 0;
405 }
406
407 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
408 {
409         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
410                      rt2800pci_init_queues(rt2x00dev)))
411                 return -EIO;
412
413         return rt2800_enable_radio(rt2x00dev);
414 }
415
416 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
417 {
418         u32 reg;
419
420         rt2800_disable_radio(rt2x00dev);
421
422         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
423
424         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
425         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
426         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
427         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
428         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
429         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
430         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
431         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
432         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
433
434         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
435         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
436 }
437
438 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
439                                enum dev_state state)
440 {
441         /*
442          * Always put the device to sleep (even when we intend to wakeup!)
443          * if the device is booting and wasn't asleep it will return
444          * failure when attempting to wakeup.
445          */
446         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0xff, 2);
447
448         if (state == STATE_AWAKE) {
449                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
450                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
451         }
452
453         return 0;
454 }
455
456 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
457                                       enum dev_state state)
458 {
459         int retval = 0;
460
461         switch (state) {
462         case STATE_RADIO_ON:
463                 /*
464                  * Before the radio can be enabled, the device first has
465                  * to be woken up. After that it needs a bit of time
466                  * to be fully awake and then the radio can be enabled.
467                  */
468                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
469                 msleep(1);
470                 retval = rt2800pci_enable_radio(rt2x00dev);
471                 break;
472         case STATE_RADIO_OFF:
473                 /*
474                  * After the radio has been disabled, the device should
475                  * be put to sleep for powersaving.
476                  */
477                 rt2800pci_disable_radio(rt2x00dev);
478                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
479                 break;
480         case STATE_RADIO_RX_ON:
481         case STATE_RADIO_RX_OFF:
482                 rt2800pci_toggle_rx(rt2x00dev, state);
483                 break;
484         case STATE_RADIO_IRQ_ON:
485         case STATE_RADIO_IRQ_ON_ISR:
486         case STATE_RADIO_IRQ_OFF:
487         case STATE_RADIO_IRQ_OFF_ISR:
488                 rt2800pci_toggle_irq(rt2x00dev, state);
489                 break;
490         case STATE_DEEP_SLEEP:
491         case STATE_SLEEP:
492         case STATE_STANDBY:
493         case STATE_AWAKE:
494                 retval = rt2800pci_set_state(rt2x00dev, state);
495                 break;
496         default:
497                 retval = -ENOTSUPP;
498                 break;
499         }
500
501         if (unlikely(retval))
502                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
503                       state, retval);
504
505         return retval;
506 }
507
508 /*
509  * TX descriptor initialization
510  */
511 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
512 {
513         return (__le32 *) entry->skb->data;
514 }
515
516 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
517                                     struct txentry_desc *txdesc)
518 {
519         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
520         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
521         __le32 *txd = entry_priv->desc;
522         u32 word;
523
524         /*
525          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
526          * must contains a TXWI structure + 802.11 header + padding + 802.11
527          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
528          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
529          * data. It means that LAST_SEC0 is always 0.
530          */
531
532         /*
533          * Initialize TX descriptor
534          */
535         rt2x00_desc_read(txd, 0, &word);
536         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
537         rt2x00_desc_write(txd, 0, word);
538
539         rt2x00_desc_read(txd, 1, &word);
540         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
541         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
542                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
543         rt2x00_set_field32(&word, TXD_W1_BURST,
544                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
545         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
546         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
547         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
548         rt2x00_desc_write(txd, 1, word);
549
550         rt2x00_desc_read(txd, 2, &word);
551         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
552                            skbdesc->skb_dma + TXWI_DESC_SIZE);
553         rt2x00_desc_write(txd, 2, word);
554
555         rt2x00_desc_read(txd, 3, &word);
556         rt2x00_set_field32(&word, TXD_W3_WIV,
557                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
558         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
559         rt2x00_desc_write(txd, 3, word);
560
561         /*
562          * Register descriptor details in skb frame descriptor.
563          */
564         skbdesc->desc = txd;
565         skbdesc->desc_len = TXD_DESC_SIZE;
566 }
567
568 /*
569  * TX data initialization
570  */
571 static void rt2800pci_kick_tx_queue(struct data_queue *queue)
572 {
573         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
574         struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
575         unsigned int qidx;
576
577         if (queue->qid == QID_MGMT)
578                 qidx = 5;
579         else
580                 qidx = queue->qid;
581
582         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), entry->entry_idx);
583 }
584
585 static void rt2800pci_kill_tx_queue(struct data_queue *queue)
586 {
587         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
588         u32 reg;
589
590         if (queue->qid == QID_BEACON) {
591                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
592                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
593                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
594                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
595                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
596                 return;
597         }
598
599         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
600         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (queue->qid == QID_AC_BE));
601         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (queue->qid == QID_AC_BK));
602         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (queue->qid == QID_AC_VI));
603         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (queue->qid == QID_AC_VO));
604         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
605 }
606
607 /*
608  * RX control handlers
609  */
610 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
611                                   struct rxdone_entry_desc *rxdesc)
612 {
613         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
614         __le32 *rxd = entry_priv->desc;
615         u32 word;
616
617         rt2x00_desc_read(rxd, 3, &word);
618
619         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
620                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
621
622         /*
623          * Unfortunately we don't know the cipher type used during
624          * decryption. This prevents us from correct providing
625          * correct statistics through debugfs.
626          */
627         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
628
629         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
630                 /*
631                  * Hardware has stripped IV/EIV data from 802.11 frame during
632                  * decryption. Unfortunately the descriptor doesn't contain
633                  * any fields with the EIV/IV data either, so they can't
634                  * be restored by rt2x00lib.
635                  */
636                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
637
638                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
639                         rxdesc->flags |= RX_FLAG_DECRYPTED;
640                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
641                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
642         }
643
644         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
645                 rxdesc->dev_flags |= RXDONE_MY_BSS;
646
647         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
648                 rxdesc->dev_flags |= RXDONE_L2PAD;
649
650         /*
651          * Process the RXWI structure that is at the start of the buffer.
652          */
653         rt2800_process_rxwi(entry, rxdesc);
654 }
655
656 /*
657  * Interrupt functions.
658  */
659 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
660 {
661         struct ieee80211_conf conf = { .flags = 0 };
662         struct rt2x00lib_conf libconf = { .conf = &conf };
663
664         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
665 }
666
667 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
668 {
669         struct data_queue *queue;
670         struct queue_entry *entry;
671         u32 status;
672         u8 qid;
673
674         while (!kfifo_is_empty(&rt2x00dev->txstatus_fifo)) {
675                 /* Now remove the tx status from the FIFO */
676                 if (kfifo_out(&rt2x00dev->txstatus_fifo, &status,
677                               sizeof(status)) != sizeof(status)) {
678                         WARN_ON(1);
679                         break;
680                 }
681
682                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
683                 if (qid >= QID_RX) {
684                         /*
685                          * Unknown queue, this shouldn't happen. Just drop
686                          * this tx status.
687                          */
688                         WARNING(rt2x00dev, "Got TX status report with "
689                                            "unexpected pid %u, dropping\n", qid);
690                         break;
691                 }
692
693                 queue = rt2x00queue_get_queue(rt2x00dev, qid);
694                 if (unlikely(queue == NULL)) {
695                         /*
696                          * The queue is NULL, this shouldn't happen. Stop
697                          * processing here and drop the tx status
698                          */
699                         WARNING(rt2x00dev, "Got TX status for an unavailable "
700                                            "queue %u, dropping\n", qid);
701                         break;
702                 }
703
704                 if (rt2x00queue_empty(queue)) {
705                         /*
706                          * The queue is empty. Stop processing here
707                          * and drop the tx status.
708                          */
709                         WARNING(rt2x00dev, "Got TX status for an empty "
710                                            "queue %u, dropping\n", qid);
711                         break;
712                 }
713
714                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
715                 rt2800_txdone_entry(entry, status);
716         }
717 }
718
719 static void rt2800pci_txstatus_tasklet(unsigned long data)
720 {
721         rt2800pci_txdone((struct rt2x00_dev *)data);
722 }
723
724 static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
725 {
726         struct rt2x00_dev *rt2x00dev = dev_instance;
727         u32 reg = rt2x00dev->irqvalue[0];
728
729         /*
730          * 1 - Pre TBTT interrupt.
731          */
732         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
733                 rt2x00lib_pretbtt(rt2x00dev);
734
735         /*
736          * 2 - Beacondone interrupt.
737          */
738         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
739                 rt2x00lib_beacondone(rt2x00dev);
740
741         /*
742          * 3 - Rx ring done interrupt.
743          */
744         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
745                 rt2x00pci_rxdone(rt2x00dev);
746
747         /*
748          * 4 - Auto wakeup interrupt.
749          */
750         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
751                 rt2800pci_wakeup(rt2x00dev);
752
753         /* Enable interrupts again. */
754         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
755                                               STATE_RADIO_IRQ_ON_ISR);
756
757         return IRQ_HANDLED;
758 }
759
760 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
761 {
762         u32 status;
763         int i;
764
765         /*
766          * The TX_FIFO_STATUS interrupt needs special care. We should
767          * read TX_STA_FIFO but we should do it immediately as otherwise
768          * the register can overflow and we would lose status reports.
769          *
770          * Hence, read the TX_STA_FIFO register and copy all tx status
771          * reports into a kernel FIFO which is handled in the txstatus
772          * tasklet. We use a tasklet to process the tx status reports
773          * because we can schedule the tasklet multiple times (when the
774          * interrupt fires again during tx status processing).
775          *
776          * Furthermore we don't disable the TX_FIFO_STATUS
777          * interrupt here but leave it enabled so that the TX_STA_FIFO
778          * can also be read while the interrupt thread gets executed.
779          *
780          * Since we have only one producer and one consumer we don't
781          * need to lock the kfifo.
782          */
783         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
784                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
785
786                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
787                         break;
788
789                 if (kfifo_is_full(&rt2x00dev->txstatus_fifo)) {
790                         WARNING(rt2x00dev, "TX status FIFO overrun,"
791                                 " drop tx status report.\n");
792                         break;
793                 }
794
795                 if (kfifo_in(&rt2x00dev->txstatus_fifo, &status,
796                              sizeof(status)) != sizeof(status)) {
797                         WARNING(rt2x00dev, "TX status FIFO overrun,"
798                                 "drop tx status report.\n");
799                         break;
800                 }
801         }
802
803         /* Schedule the tasklet for processing the tx status. */
804         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
805 }
806
807 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
808 {
809         struct rt2x00_dev *rt2x00dev = dev_instance;
810         u32 reg;
811         irqreturn_t ret = IRQ_HANDLED;
812
813         /* Read status and ACK all interrupts */
814         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
815         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
816
817         if (!reg)
818                 return IRQ_NONE;
819
820         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
821                 return IRQ_HANDLED;
822
823         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
824                 rt2800pci_txstatus_interrupt(rt2x00dev);
825
826         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT) ||
827             rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT) ||
828             rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE) ||
829             rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) {
830                 /*
831                  * All other interrupts are handled in the interrupt thread.
832                  * Store irqvalue for use in the interrupt thread.
833                  */
834                 rt2x00dev->irqvalue[0] = reg;
835
836                 /*
837                  * Disable interrupts, will be enabled again in the
838                  * interrupt thread.
839                 */
840                 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
841                                                       STATE_RADIO_IRQ_OFF_ISR);
842
843                 /*
844                  * Leave the TX_FIFO_STATUS interrupt enabled to not lose any
845                  * tx status reports.
846                  */
847                 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
848                 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
849                 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
850
851                 ret = IRQ_WAKE_THREAD;
852         }
853
854         return ret;
855 }
856
857 /*
858  * Device probe functions.
859  */
860 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
861 {
862         /*
863          * Read EEPROM into buffer
864          */
865         if (rt2x00_is_soc(rt2x00dev))
866                 rt2800pci_read_eeprom_soc(rt2x00dev);
867         else if (rt2800pci_efuse_detect(rt2x00dev))
868                 rt2800pci_read_eeprom_efuse(rt2x00dev);
869         else
870                 rt2800pci_read_eeprom_pci(rt2x00dev);
871
872         return rt2800_validate_eeprom(rt2x00dev);
873 }
874
875 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
876 {
877         int retval;
878
879         /*
880          * Allocate eeprom data.
881          */
882         retval = rt2800pci_validate_eeprom(rt2x00dev);
883         if (retval)
884                 return retval;
885
886         retval = rt2800_init_eeprom(rt2x00dev);
887         if (retval)
888                 return retval;
889
890         /*
891          * Initialize hw specifications.
892          */
893         retval = rt2800_probe_hw_mode(rt2x00dev);
894         if (retval)
895                 return retval;
896
897         /*
898          * This device has multiple filters for control frames
899          * and has a separate filter for PS Poll frames.
900          */
901         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
902         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
903
904         /*
905          * This device has a pre tbtt interrupt and thus fetches
906          * a new beacon directly prior to transmission.
907          */
908         __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
909
910         /*
911          * This device requires firmware.
912          */
913         if (!rt2x00_is_soc(rt2x00dev))
914                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
915         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
916         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
917         __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
918         __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
919         if (!modparam_nohwcrypt)
920                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
921         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
922
923         /*
924          * Set the rssi offset.
925          */
926         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
927
928         return 0;
929 }
930
931 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
932         .tx                     = rt2x00mac_tx,
933         .start                  = rt2x00mac_start,
934         .stop                   = rt2x00mac_stop,
935         .add_interface          = rt2x00mac_add_interface,
936         .remove_interface       = rt2x00mac_remove_interface,
937         .config                 = rt2x00mac_config,
938         .configure_filter       = rt2x00mac_configure_filter,
939         .set_key                = rt2x00mac_set_key,
940         .sw_scan_start          = rt2x00mac_sw_scan_start,
941         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
942         .get_stats              = rt2x00mac_get_stats,
943         .get_tkip_seq           = rt2800_get_tkip_seq,
944         .set_rts_threshold      = rt2800_set_rts_threshold,
945         .bss_info_changed       = rt2x00mac_bss_info_changed,
946         .conf_tx                = rt2800_conf_tx,
947         .get_tsf                = rt2800_get_tsf,
948         .rfkill_poll            = rt2x00mac_rfkill_poll,
949         .ampdu_action           = rt2800_ampdu_action,
950         .flush                  = rt2x00mac_flush,
951         .get_survey             = rt2800_get_survey,
952 };
953
954 static const struct rt2800_ops rt2800pci_rt2800_ops = {
955         .register_read          = rt2x00pci_register_read,
956         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
957         .register_write         = rt2x00pci_register_write,
958         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
959         .register_multiread     = rt2x00pci_register_multiread,
960         .register_multiwrite    = rt2x00pci_register_multiwrite,
961         .regbusy_read           = rt2x00pci_regbusy_read,
962         .drv_write_firmware     = rt2800pci_write_firmware,
963         .drv_init_registers     = rt2800pci_init_registers,
964         .drv_get_txwi           = rt2800pci_get_txwi,
965 };
966
967 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
968         .irq_handler            = rt2800pci_interrupt,
969         .irq_handler_thread     = rt2800pci_interrupt_thread,
970         .txstatus_tasklet       = rt2800pci_txstatus_tasklet,
971         .probe_hw               = rt2800pci_probe_hw,
972         .get_firmware_name      = rt2800pci_get_firmware_name,
973         .check_firmware         = rt2800_check_firmware,
974         .load_firmware          = rt2800_load_firmware,
975         .initialize             = rt2x00pci_initialize,
976         .uninitialize           = rt2x00pci_uninitialize,
977         .get_entry_state        = rt2800pci_get_entry_state,
978         .clear_entry            = rt2800pci_clear_entry,
979         .set_device_state       = rt2800pci_set_device_state,
980         .rfkill_poll            = rt2800_rfkill_poll,
981         .link_stats             = rt2800_link_stats,
982         .reset_tuner            = rt2800_reset_tuner,
983         .link_tuner             = rt2800_link_tuner,
984         .write_tx_desc          = rt2800pci_write_tx_desc,
985         .write_tx_data          = rt2800_write_tx_data,
986         .write_beacon           = rt2800_write_beacon,
987         .kick_tx_queue          = rt2800pci_kick_tx_queue,
988         .kill_tx_queue          = rt2800pci_kill_tx_queue,
989         .fill_rxdone            = rt2800pci_fill_rxdone,
990         .config_shared_key      = rt2800_config_shared_key,
991         .config_pairwise_key    = rt2800_config_pairwise_key,
992         .config_filter          = rt2800_config_filter,
993         .config_intf            = rt2800_config_intf,
994         .config_erp             = rt2800_config_erp,
995         .config_ant             = rt2800_config_ant,
996         .config                 = rt2800_config,
997 };
998
999 static const struct data_queue_desc rt2800pci_queue_rx = {
1000         .entry_num              = 128,
1001         .data_size              = AGGREGATION_SIZE,
1002         .desc_size              = RXD_DESC_SIZE,
1003         .priv_size              = sizeof(struct queue_entry_priv_pci),
1004 };
1005
1006 static const struct data_queue_desc rt2800pci_queue_tx = {
1007         .entry_num              = 64,
1008         .data_size              = AGGREGATION_SIZE,
1009         .desc_size              = TXD_DESC_SIZE,
1010         .priv_size              = sizeof(struct queue_entry_priv_pci),
1011 };
1012
1013 static const struct data_queue_desc rt2800pci_queue_bcn = {
1014         .entry_num              = 8,
1015         .data_size              = 0, /* No DMA required for beacons */
1016         .desc_size              = TXWI_DESC_SIZE,
1017         .priv_size              = sizeof(struct queue_entry_priv_pci),
1018 };
1019
1020 static const struct rt2x00_ops rt2800pci_ops = {
1021         .name                   = KBUILD_MODNAME,
1022         .max_sta_intf           = 1,
1023         .max_ap_intf            = 8,
1024         .eeprom_size            = EEPROM_SIZE,
1025         .rf_size                = RF_SIZE,
1026         .tx_queues              = NUM_TX_QUEUES,
1027         .extra_tx_headroom      = TXWI_DESC_SIZE,
1028         .rx                     = &rt2800pci_queue_rx,
1029         .tx                     = &rt2800pci_queue_tx,
1030         .bcn                    = &rt2800pci_queue_bcn,
1031         .lib                    = &rt2800pci_rt2x00_ops,
1032         .drv                    = &rt2800pci_rt2800_ops,
1033         .hw                     = &rt2800pci_mac80211_ops,
1034 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1035         .debugfs                = &rt2800_rt2x00debug,
1036 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1037 };
1038
1039 /*
1040  * RT2800pci module information.
1041  */
1042 #ifdef CONFIG_PCI
1043 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1044         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1045         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
1046         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
1047         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
1048         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
1049         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
1050         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
1051         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
1052         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
1053         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
1054         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
1055         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
1056         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
1057         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
1058         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
1059         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
1060 #ifdef CONFIG_RT2800PCI_RT33XX
1061         { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1062 #endif
1063 #ifdef CONFIG_RT2800PCI_RT35XX
1064         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
1065         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1066         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1067         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1068         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1069 #endif
1070         { 0, }
1071 };
1072 #endif /* CONFIG_PCI */
1073
1074 MODULE_AUTHOR(DRV_PROJECT);
1075 MODULE_VERSION(DRV_VERSION);
1076 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1077 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1078 #ifdef CONFIG_PCI
1079 MODULE_FIRMWARE(FIRMWARE_RT2860);
1080 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1081 #endif /* CONFIG_PCI */
1082 MODULE_LICENSE("GPL");
1083
1084 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1085 static int rt2800soc_probe(struct platform_device *pdev)
1086 {
1087         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1088 }
1089
1090 static struct platform_driver rt2800soc_driver = {
1091         .driver         = {
1092                 .name           = "rt2800_wmac",
1093                 .owner          = THIS_MODULE,
1094                 .mod_name       = KBUILD_MODNAME,
1095         },
1096         .probe          = rt2800soc_probe,
1097         .remove         = __devexit_p(rt2x00soc_remove),
1098         .suspend        = rt2x00soc_suspend,
1099         .resume         = rt2x00soc_resume,
1100 };
1101 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1102
1103 #ifdef CONFIG_PCI
1104 static struct pci_driver rt2800pci_driver = {
1105         .name           = KBUILD_MODNAME,
1106         .id_table       = rt2800pci_device_table,
1107         .probe          = rt2x00pci_probe,
1108         .remove         = __devexit_p(rt2x00pci_remove),
1109         .suspend        = rt2x00pci_suspend,
1110         .resume         = rt2x00pci_resume,
1111 };
1112 #endif /* CONFIG_PCI */
1113
1114 static int __init rt2800pci_init(void)
1115 {
1116         int ret = 0;
1117
1118 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1119         ret = platform_driver_register(&rt2800soc_driver);
1120         if (ret)
1121                 return ret;
1122 #endif
1123 #ifdef CONFIG_PCI
1124         ret = pci_register_driver(&rt2800pci_driver);
1125         if (ret) {
1126 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1127                 platform_driver_unregister(&rt2800soc_driver);
1128 #endif
1129                 return ret;
1130         }
1131 #endif
1132
1133         return ret;
1134 }
1135
1136 static void __exit rt2800pci_exit(void)
1137 {
1138 #ifdef CONFIG_PCI
1139         pci_unregister_driver(&rt2800pci_driver);
1140 #endif
1141 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1142         platform_driver_unregister(&rt2800soc_driver);
1143 #endif
1144 }
1145
1146 module_init(rt2800pci_init);
1147 module_exit(rt2800pci_exit);