Fix common misspellings
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7         Based on the original rt2800pci.c and rt2800usb.c.
8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14           <http://rt2x00.serialmonkey.com>
15
16         This program is free software; you can redistribute it and/or modify
17         it under the terms of the GNU General Public License as published by
18         the Free Software Foundation; either version 2 of the License, or
19         (at your option) any later version.
20
21         This program is distributed in the hope that it will be useful,
22         but WITHOUT ANY WARRANTY; without even the implied warranty of
23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24         GNU General Public License for more details.
25
26         You should have received a copy of the GNU General Public License
27         along with this program; if not, write to the
28         Free Software Foundation, Inc.,
29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30  */
31
32 /*
33         Module: rt2800lib
34         Abstract: rt2800 generic device routines.
35  */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47  * Register access.
48  * All access to the CSR registers will go through the methods
49  * rt2800_register_read and rt2800_register_write.
50  * BBP and RF register require indirect register access,
51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
52  * These indirect registers work with busy bits,
53  * and we will try maximal REGISTER_BUSY_COUNT times to access
54  * the register while taking a REGISTER_BUSY_DELAY us delay
55  * between each attampt. When the busy bit is still set at that time,
56  * the access attempt is considered to have failed,
57  * and we will print an error.
58  * The _lock versions must be used if you already hold the csr_mutex
59  */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68                             H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72         /* check for rt2872 on SoC */
73         if (!rt2x00_is_soc(rt2x00dev) ||
74             !rt2x00_rt(rt2x00dev, RT2872))
75                 return false;
76
77         /* we know for sure that these rf chipsets are used on rt305x boards */
78         if (rt2x00_rf(rt2x00dev, RF3020) ||
79             rt2x00_rf(rt2x00dev, RF3021) ||
80             rt2x00_rf(rt2x00dev, RF3022))
81                 return true;
82
83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84         return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88                              const unsigned int word, const u8 value)
89 {
90         u32 reg;
91
92         mutex_lock(&rt2x00dev->csr_mutex);
93
94         /*
95          * Wait until the BBP becomes available, afterwards we
96          * can safely write the new data into the register.
97          */
98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99                 reg = 0;
100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107         }
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113                             const unsigned int word, u8 *value)
114 {
115         u32 reg;
116
117         mutex_lock(&rt2x00dev->csr_mutex);
118
119         /*
120          * Wait until the BBP becomes available, afterwards we
121          * can safely write the read request into the register.
122          * After the data has been written, we wait until hardware
123          * returns the correct value, if at any time the register
124          * doesn't become available in time, reg will be 0xffffffff
125          * which means we return 0xff to the caller.
126          */
127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128                 reg = 0;
129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136                 WAIT_FOR_BBP(rt2x00dev, &reg);
137         }
138
139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141         mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145                                const unsigned int word, const u8 value)
146 {
147         u32 reg;
148
149         mutex_lock(&rt2x00dev->csr_mutex);
150
151         /*
152          * Wait until the RFCSR becomes available, afterwards we
153          * can safely write the new data into the register.
154          */
155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156                 reg = 0;
157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163         }
164
165         mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169                               const unsigned int word, u8 *value)
170 {
171         u32 reg;
172
173         mutex_lock(&rt2x00dev->csr_mutex);
174
175         /*
176          * Wait until the RFCSR becomes available, afterwards we
177          * can safely write the read request into the register.
178          * After the data has been written, we wait until hardware
179          * returns the correct value, if at any time the register
180          * doesn't become available in time, reg will be 0xffffffff
181          * which means we return 0xff to the caller.
182          */
183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184                 reg = 0;
185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192         }
193
194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196         mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200                             const unsigned int word, const u32 value)
201 {
202         u32 reg;
203
204         mutex_lock(&rt2x00dev->csr_mutex);
205
206         /*
207          * Wait until the RF becomes available, afterwards we
208          * can safely write the new data into the register.
209          */
210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211                 reg = 0;
212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218                 rt2x00_rf_write(rt2x00dev, word, value);
219         }
220
221         mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225                         const u8 command, const u8 token,
226                         const u8 arg0, const u8 arg1)
227 {
228         u32 reg;
229
230         /*
231          * SOC devices don't support MCU requests.
232          */
233         if (rt2x00_is_soc(rt2x00dev))
234                 return;
235
236         mutex_lock(&rt2x00dev->csr_mutex);
237
238         /*
239          * Wait until the MCU becomes available, afterwards we
240          * can safely write the new data into the register.
241          */
242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249                 reg = 0;
250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252         }
253
254         mutex_unlock(&rt2x00dev->csr_mutex);
255 }
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
257
258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259 {
260         unsigned int i = 0;
261         u32 reg;
262
263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265                 if (reg && reg != ~0)
266                         return 0;
267                 msleep(1);
268         }
269
270         ERROR(rt2x00dev, "Unstable hardware.\n");
271         return -EBUSY;
272 }
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276 {
277         unsigned int i;
278         u32 reg;
279
280         /*
281          * Some devices are really slow to respond here. Wait a whole second
282          * before timing out.
283          */
284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288                         return 0;
289
290                 msleep(10);
291         }
292
293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294         return -EACCES;
295 }
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299 {
300         u16 fw_crc;
301         u16 crc;
302
303         /*
304          * The last 2 bytes in the firmware array are the crc checksum itself,
305          * this means that we should never pass those 2 bytes to the crc
306          * algorithm.
307          */
308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310         /*
311          * Use the crc ccitt algorithm.
312          * This will return the same value as the legacy driver which
313          * used bit ordering reversion on the both the firmware bytes
314          * before input input as well as on the final output.
315          * Obviously using crc ccitt directly is much more efficient.
316          */
317         crc = crc_ccitt(~0, data, len - 2);
318
319         /*
320          * There is a small difference between the crc-itu-t + bitrev and
321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
322          * will be swapped, use swab16 to convert the crc to the correct
323          * value.
324          */
325         crc = swab16(crc);
326
327         return fw_crc == crc;
328 }
329
330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331                           const u8 *data, const size_t len)
332 {
333         size_t offset = 0;
334         size_t fw_len;
335         bool multiple;
336
337         /*
338          * PCI(e) & SOC devices require firmware with a length
339          * of 8kb. USB devices require firmware files with a length
340          * of 4kb. Certain USB chipsets however require different firmware,
341          * which Ralink only provides attached to the original firmware
342          * file. Thus for USB devices, firmware files have a length
343          * which is a multiple of 4kb.
344          */
345         if (rt2x00_is_usb(rt2x00dev)) {
346                 fw_len = 4096;
347                 multiple = true;
348         } else {
349                 fw_len = 8192;
350                 multiple = true;
351         }
352
353         /*
354          * Validate the firmware length
355          */
356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
357                 return FW_BAD_LENGTH;
358
359         /*
360          * Check if the chipset requires one of the upper parts
361          * of the firmware.
362          */
363         if (rt2x00_is_usb(rt2x00dev) &&
364             !rt2x00_rt(rt2x00dev, RT2860) &&
365             !rt2x00_rt(rt2x00dev, RT2872) &&
366             !rt2x00_rt(rt2x00dev, RT3070) &&
367             ((len / fw_len) == 1))
368                 return FW_BAD_VERSION;
369
370         /*
371          * 8kb firmware files must be checked as if it were
372          * 2 separate firmware files.
373          */
374         while (offset < len) {
375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376                         return FW_BAD_CRC;
377
378                 offset += fw_len;
379         }
380
381         return FW_OK;
382 }
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386                          const u8 *data, const size_t len)
387 {
388         unsigned int i;
389         u32 reg;
390
391         /*
392          * If driver doesn't wake up firmware here,
393          * rt2800_load_firmware will hang forever when interface is up again.
394          */
395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
396
397         /*
398          * Wait for stable hardware.
399          */
400         if (rt2800_wait_csr_ready(rt2x00dev))
401                 return -EBUSY;
402
403         if (rt2x00_is_pci(rt2x00dev)) {
404                 if (rt2x00_rt(rt2x00dev, RT5390)) {
405                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
406                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
407                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
408                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
409                 }
410                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
411         }
412
413         /*
414          * Disable DMA, will be reenabled later when enabling
415          * the radio.
416          */
417         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
418         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
419         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
420         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
421         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
422         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
423         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
424
425         /*
426          * Write firmware to the device.
427          */
428         rt2800_drv_write_firmware(rt2x00dev, data, len);
429
430         /*
431          * Wait for device to stabilize.
432          */
433         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
434                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
435                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
436                         break;
437                 msleep(1);
438         }
439
440         if (i == REGISTER_BUSY_COUNT) {
441                 ERROR(rt2x00dev, "PBF system register not ready.\n");
442                 return -EBUSY;
443         }
444
445         /*
446          * Initialize firmware.
447          */
448         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
449         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
450         msleep(1);
451
452         return 0;
453 }
454 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
455
456 void rt2800_write_tx_data(struct queue_entry *entry,
457                           struct txentry_desc *txdesc)
458 {
459         __le32 *txwi = rt2800_drv_get_txwi(entry);
460         u32 word;
461
462         /*
463          * Initialize TX Info descriptor
464          */
465         rt2x00_desc_read(txwi, 0, &word);
466         rt2x00_set_field32(&word, TXWI_W0_FRAG,
467                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
468         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
469                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
470         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
471         rt2x00_set_field32(&word, TXWI_W0_TS,
472                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
473         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
474                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
475         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
476                            txdesc->u.ht.mpdu_density);
477         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
478         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
479         rt2x00_set_field32(&word, TXWI_W0_BW,
480                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
481         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
482                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
483         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
484         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
485         rt2x00_desc_write(txwi, 0, word);
486
487         rt2x00_desc_read(txwi, 1, &word);
488         rt2x00_set_field32(&word, TXWI_W1_ACK,
489                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
490         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
491                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
492         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
493         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
494                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
495                            txdesc->key_idx : 0xff);
496         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
497                            txdesc->length);
498         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
499         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
500         rt2x00_desc_write(txwi, 1, word);
501
502         /*
503          * Always write 0 to IV/EIV fields, hardware will insert the IV
504          * from the IVEIV register when TXD_W3_WIV is set to 0.
505          * When TXD_W3_WIV is set to 1 it will use the IV data
506          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
507          * crypto entry in the registers should be used to encrypt the frame.
508          */
509         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
510         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
511 }
512 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
513
514 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
515 {
516         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
517         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
518         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
519         u16 eeprom;
520         u8 offset0;
521         u8 offset1;
522         u8 offset2;
523
524         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
525                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
526                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
527                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
528                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
529                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
530         } else {
531                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
532                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
533                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
534                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
535                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
536         }
537
538         /*
539          * Convert the value from the descriptor into the RSSI value
540          * If the value in the descriptor is 0, it is considered invalid
541          * and the default (extremely low) rssi value is assumed
542          */
543         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
544         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
545         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
546
547         /*
548          * mac80211 only accepts a single RSSI value. Calculating the
549          * average doesn't deliver a fair answer either since -60:-60 would
550          * be considered equally good as -50:-70 while the second is the one
551          * which gives less energy...
552          */
553         rssi0 = max(rssi0, rssi1);
554         return max(rssi0, rssi2);
555 }
556
557 void rt2800_process_rxwi(struct queue_entry *entry,
558                          struct rxdone_entry_desc *rxdesc)
559 {
560         __le32 *rxwi = (__le32 *) entry->skb->data;
561         u32 word;
562
563         rt2x00_desc_read(rxwi, 0, &word);
564
565         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
566         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
567
568         rt2x00_desc_read(rxwi, 1, &word);
569
570         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
571                 rxdesc->flags |= RX_FLAG_SHORT_GI;
572
573         if (rt2x00_get_field32(word, RXWI_W1_BW))
574                 rxdesc->flags |= RX_FLAG_40MHZ;
575
576         /*
577          * Detect RX rate, always use MCS as signal type.
578          */
579         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
580         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
581         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
582
583         /*
584          * Mask of 0x8 bit to remove the short preamble flag.
585          */
586         if (rxdesc->rate_mode == RATE_MODE_CCK)
587                 rxdesc->signal &= ~0x8;
588
589         rt2x00_desc_read(rxwi, 2, &word);
590
591         /*
592          * Convert descriptor AGC value to RSSI value.
593          */
594         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
595
596         /*
597          * Remove RXWI descriptor from start of buffer.
598          */
599         skb_pull(entry->skb, RXWI_DESC_SIZE);
600 }
601 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
602
603 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
604 {
605         __le32 *txwi;
606         u32 word;
607         int wcid, ack, pid;
608         int tx_wcid, tx_ack, tx_pid;
609
610         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
611         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
612         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
613
614         /*
615          * This frames has returned with an IO error,
616          * so the status report is not intended for this
617          * frame.
618          */
619         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
620                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
621                 return false;
622         }
623
624         /*
625          * Validate if this TX status report is intended for
626          * this entry by comparing the WCID/ACK/PID fields.
627          */
628         txwi = rt2800_drv_get_txwi(entry);
629
630         rt2x00_desc_read(txwi, 1, &word);
631         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
632         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
633         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
634
635         if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
636                 WARNING(entry->queue->rt2x00dev,
637                         "TX status report missed for queue %d entry %d\n",
638                 entry->queue->qid, entry->entry_idx);
639                 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
640                 return false;
641         }
642
643         return true;
644 }
645
646 void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
647 {
648         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
649         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
650         struct txdone_entry_desc txdesc;
651         u32 word;
652         u16 mcs, real_mcs;
653         int aggr, ampdu;
654         __le32 *txwi;
655
656         /*
657          * Obtain the status about this packet.
658          */
659         txdesc.flags = 0;
660         txwi = rt2800_drv_get_txwi(entry);
661         rt2x00_desc_read(txwi, 0, &word);
662
663         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
664         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
665
666         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
667         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
668
669         /*
670          * If a frame was meant to be sent as a single non-aggregated MPDU
671          * but ended up in an aggregate the used tx rate doesn't correlate
672          * with the one specified in the TXWI as the whole aggregate is sent
673          * with the same rate.
674          *
675          * For example: two frames are sent to rt2x00, the first one sets
676          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
677          * and requests MCS15. If the hw aggregates both frames into one
678          * AMDPU the tx status for both frames will contain MCS7 although
679          * the frame was sent successfully.
680          *
681          * Hence, replace the requested rate with the real tx rate to not
682          * confuse the rate control algortihm by providing clearly wrong
683          * data.
684          */
685         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
686                 skbdesc->tx_rate_idx = real_mcs;
687                 mcs = real_mcs;
688         }
689
690         /*
691          * Ralink has a retry mechanism using a global fallback
692          * table. We setup this fallback table to try the immediate
693          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
694          * always contains the MCS used for the last transmission, be
695          * it successful or not.
696          */
697         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
698                 /*
699                  * Transmission succeeded. The number of retries is
700                  * mcs - real_mcs
701                  */
702                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
703                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
704         } else {
705                 /*
706                  * Transmission failed. The number of retries is
707                  * always 7 in this case (for a total number of 8
708                  * frames sent).
709                  */
710                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
711                 txdesc.retry = rt2x00dev->long_retry;
712         }
713
714         /*
715          * the frame was retried at least once
716          * -> hw used fallback rates
717          */
718         if (txdesc.retry)
719                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
720
721         rt2x00lib_txdone(entry, &txdesc);
722 }
723 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
724
725 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
726 {
727         struct data_queue *queue;
728         struct queue_entry *entry;
729         u32 reg;
730         u8 pid;
731         int i;
732
733         /*
734          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
735          * at most X times and also stop processing once the TX_STA_FIFO_VALID
736          * flag is not set anymore.
737          *
738          * The legacy drivers use X=TX_RING_SIZE but state in a comment
739          * that the TX_STA_FIFO stack has a size of 16. We stick to our
740          * tx ring size for now.
741          */
742         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
743                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
744                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
745                         break;
746
747                 /*
748                  * Skip this entry when it contains an invalid
749                  * queue identication number.
750                  */
751                 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
752                 if (pid >= QID_RX)
753                         continue;
754
755                 queue = rt2x00queue_get_tx_queue(rt2x00dev, pid);
756                 if (unlikely(!queue))
757                         continue;
758
759                 /*
760                  * Inside each queue, we process each entry in a chronological
761                  * order. We first check that the queue is not empty.
762                  */
763                 entry = NULL;
764                 while (!rt2x00queue_empty(queue)) {
765                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
766                         if (rt2800_txdone_entry_check(entry, reg))
767                                 break;
768                 }
769
770                 if (!entry || rt2x00queue_empty(queue))
771                         break;
772
773                 rt2800_txdone_entry(entry, reg);
774         }
775 }
776 EXPORT_SYMBOL_GPL(rt2800_txdone);
777
778 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
779 {
780         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
781         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
782         unsigned int beacon_base;
783         unsigned int padding_len;
784         u32 orig_reg, reg;
785
786         /*
787          * Disable beaconing while we are reloading the beacon data,
788          * otherwise we might be sending out invalid data.
789          */
790         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
791         orig_reg = reg;
792         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
793         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
794
795         /*
796          * Add space for the TXWI in front of the skb.
797          */
798         skb_push(entry->skb, TXWI_DESC_SIZE);
799         memset(entry->skb, 0, TXWI_DESC_SIZE);
800
801         /*
802          * Register descriptor details in skb frame descriptor.
803          */
804         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
805         skbdesc->desc = entry->skb->data;
806         skbdesc->desc_len = TXWI_DESC_SIZE;
807
808         /*
809          * Add the TXWI for the beacon to the skb.
810          */
811         rt2800_write_tx_data(entry, txdesc);
812
813         /*
814          * Dump beacon to userspace through debugfs.
815          */
816         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
817
818         /*
819          * Write entire beacon with TXWI and padding to register.
820          */
821         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
822         if (padding_len && skb_pad(entry->skb, padding_len)) {
823                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
824                 /* skb freed by skb_pad() on failure */
825                 entry->skb = NULL;
826                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
827                 return;
828         }
829
830         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
831         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
832                                    entry->skb->len + padding_len);
833
834         /*
835          * Enable beaconing again.
836          */
837         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
838         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
839
840         /*
841          * Clean up beacon skb.
842          */
843         dev_kfree_skb_any(entry->skb);
844         entry->skb = NULL;
845 }
846 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
847
848 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
849                                                 unsigned int beacon_base)
850 {
851         int i;
852
853         /*
854          * For the Beacon base registers we only need to clear
855          * the whole TXWI which (when set to 0) will invalidate
856          * the entire beacon.
857          */
858         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
859                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
860 }
861
862 void rt2800_clear_beacon(struct queue_entry *entry)
863 {
864         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
865         u32 reg;
866
867         /*
868          * Disable beaconing while we are reloading the beacon data,
869          * otherwise we might be sending out invalid data.
870          */
871         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
872         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
873         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
874
875         /*
876          * Clear beacon.
877          */
878         rt2800_clear_beacon_register(rt2x00dev,
879                                      HW_BEACON_OFFSET(entry->entry_idx));
880
881         /*
882          * Enabled beaconing again.
883          */
884         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
885         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
886 }
887 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
888
889 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
890 const struct rt2x00debug rt2800_rt2x00debug = {
891         .owner  = THIS_MODULE,
892         .csr    = {
893                 .read           = rt2800_register_read,
894                 .write          = rt2800_register_write,
895                 .flags          = RT2X00DEBUGFS_OFFSET,
896                 .word_base      = CSR_REG_BASE,
897                 .word_size      = sizeof(u32),
898                 .word_count     = CSR_REG_SIZE / sizeof(u32),
899         },
900         .eeprom = {
901                 .read           = rt2x00_eeprom_read,
902                 .write          = rt2x00_eeprom_write,
903                 .word_base      = EEPROM_BASE,
904                 .word_size      = sizeof(u16),
905                 .word_count     = EEPROM_SIZE / sizeof(u16),
906         },
907         .bbp    = {
908                 .read           = rt2800_bbp_read,
909                 .write          = rt2800_bbp_write,
910                 .word_base      = BBP_BASE,
911                 .word_size      = sizeof(u8),
912                 .word_count     = BBP_SIZE / sizeof(u8),
913         },
914         .rf     = {
915                 .read           = rt2x00_rf_read,
916                 .write          = rt2800_rf_write,
917                 .word_base      = RF_BASE,
918                 .word_size      = sizeof(u32),
919                 .word_count     = RF_SIZE / sizeof(u32),
920         },
921 };
922 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
923 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
924
925 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
926 {
927         u32 reg;
928
929         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
930         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
931 }
932 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
933
934 #ifdef CONFIG_RT2X00_LIB_LEDS
935 static void rt2800_brightness_set(struct led_classdev *led_cdev,
936                                   enum led_brightness brightness)
937 {
938         struct rt2x00_led *led =
939             container_of(led_cdev, struct rt2x00_led, led_dev);
940         unsigned int enabled = brightness != LED_OFF;
941         unsigned int bg_mode =
942             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
943         unsigned int polarity =
944                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
945                                    EEPROM_FREQ_LED_POLARITY);
946         unsigned int ledmode =
947                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
948                                    EEPROM_FREQ_LED_MODE);
949
950         if (led->type == LED_TYPE_RADIO) {
951                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
952                                       enabled ? 0x20 : 0);
953         } else if (led->type == LED_TYPE_ASSOC) {
954                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
955                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
956         } else if (led->type == LED_TYPE_QUALITY) {
957                 /*
958                  * The brightness is divided into 6 levels (0 - 5),
959                  * The specs tell us the following levels:
960                  *      0, 1 ,3, 7, 15, 31
961                  * to determine the level in a simple way we can simply
962                  * work with bitshifting:
963                  *      (1 << level) - 1
964                  */
965                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
966                                       (1 << brightness / (LED_FULL / 6)) - 1,
967                                       polarity);
968         }
969 }
970
971 static int rt2800_blink_set(struct led_classdev *led_cdev,
972                             unsigned long *delay_on, unsigned long *delay_off)
973 {
974         struct rt2x00_led *led =
975             container_of(led_cdev, struct rt2x00_led, led_dev);
976         u32 reg;
977
978         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
979         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
980         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
981         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
982
983         return 0;
984 }
985
986 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
987                      struct rt2x00_led *led, enum led_type type)
988 {
989         led->rt2x00dev = rt2x00dev;
990         led->type = type;
991         led->led_dev.brightness_set = rt2800_brightness_set;
992         led->led_dev.blink_set = rt2800_blink_set;
993         led->flags = LED_INITIALIZED;
994 }
995 #endif /* CONFIG_RT2X00_LIB_LEDS */
996
997 /*
998  * Configuration handlers.
999  */
1000 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
1001                                     struct rt2x00lib_crypto *crypto,
1002                                     struct ieee80211_key_conf *key)
1003 {
1004         struct mac_wcid_entry wcid_entry;
1005         struct mac_iveiv_entry iveiv_entry;
1006         u32 offset;
1007         u32 reg;
1008
1009         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1010
1011         if (crypto->cmd == SET_KEY) {
1012                 rt2800_register_read(rt2x00dev, offset, &reg);
1013                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1014                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1015                 /*
1016                  * Both the cipher as the BSS Idx numbers are split in a main
1017                  * value of 3 bits, and a extended field for adding one additional
1018                  * bit to the value.
1019                  */
1020                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1021                                    (crypto->cipher & 0x7));
1022                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1023                                    (crypto->cipher & 0x8) >> 3);
1024                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
1025                                    (crypto->bssidx & 0x7));
1026                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1027                                    (crypto->bssidx & 0x8) >> 3);
1028                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1029                 rt2800_register_write(rt2x00dev, offset, reg);
1030         } else {
1031                 rt2800_register_write(rt2x00dev, offset, 0);
1032         }
1033
1034         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1035
1036         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1037         if ((crypto->cipher == CIPHER_TKIP) ||
1038             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1039             (crypto->cipher == CIPHER_AES))
1040                 iveiv_entry.iv[3] |= 0x20;
1041         iveiv_entry.iv[3] |= key->keyidx << 6;
1042         rt2800_register_multiwrite(rt2x00dev, offset,
1043                                       &iveiv_entry, sizeof(iveiv_entry));
1044
1045         offset = MAC_WCID_ENTRY(key->hw_key_idx);
1046
1047         memset(&wcid_entry, 0, sizeof(wcid_entry));
1048         if (crypto->cmd == SET_KEY)
1049                 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
1050         rt2800_register_multiwrite(rt2x00dev, offset,
1051                                       &wcid_entry, sizeof(wcid_entry));
1052 }
1053
1054 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1055                              struct rt2x00lib_crypto *crypto,
1056                              struct ieee80211_key_conf *key)
1057 {
1058         struct hw_key_entry key_entry;
1059         struct rt2x00_field32 field;
1060         u32 offset;
1061         u32 reg;
1062
1063         if (crypto->cmd == SET_KEY) {
1064                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1065
1066                 memcpy(key_entry.key, crypto->key,
1067                        sizeof(key_entry.key));
1068                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1069                        sizeof(key_entry.tx_mic));
1070                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1071                        sizeof(key_entry.rx_mic));
1072
1073                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1074                 rt2800_register_multiwrite(rt2x00dev, offset,
1075                                               &key_entry, sizeof(key_entry));
1076         }
1077
1078         /*
1079          * The cipher types are stored over multiple registers
1080          * starting with SHARED_KEY_MODE_BASE each word will have
1081          * 32 bits and contains the cipher types for 2 bssidx each.
1082          * Using the correct defines correctly will cause overhead,
1083          * so just calculate the correct offset.
1084          */
1085         field.bit_offset = 4 * (key->hw_key_idx % 8);
1086         field.bit_mask = 0x7 << field.bit_offset;
1087
1088         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1089
1090         rt2800_register_read(rt2x00dev, offset, &reg);
1091         rt2x00_set_field32(&reg, field,
1092                            (crypto->cmd == SET_KEY) * crypto->cipher);
1093         rt2800_register_write(rt2x00dev, offset, reg);
1094
1095         /*
1096          * Update WCID information
1097          */
1098         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1099
1100         return 0;
1101 }
1102 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1103
1104 static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev)
1105 {
1106         int idx;
1107         u32 offset, reg;
1108
1109         /*
1110          * Search for the first free pairwise key entry and return the
1111          * corresponding index.
1112          *
1113          * Make sure the WCID starts _after_ the last possible shared key
1114          * entry (>32).
1115          *
1116          * Since parts of the pairwise key table might be shared with
1117          * the beacon frame buffers 6 & 7 we should only write into the
1118          * first 222 entries.
1119          */
1120         for (idx = 33; idx <= 222; idx++) {
1121                 offset = MAC_WCID_ATTR_ENTRY(idx);
1122                 rt2800_register_read(rt2x00dev, offset, &reg);
1123                 if (!reg)
1124                         return idx;
1125         }
1126         return -1;
1127 }
1128
1129 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1130                                struct rt2x00lib_crypto *crypto,
1131                                struct ieee80211_key_conf *key)
1132 {
1133         struct hw_key_entry key_entry;
1134         u32 offset;
1135         int idx;
1136
1137         if (crypto->cmd == SET_KEY) {
1138                 idx = rt2800_find_pairwise_keyslot(rt2x00dev);
1139                 if (idx < 0)
1140                         return -ENOSPC;
1141                 key->hw_key_idx = idx;
1142
1143                 memcpy(key_entry.key, crypto->key,
1144                        sizeof(key_entry.key));
1145                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1146                        sizeof(key_entry.tx_mic));
1147                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1148                        sizeof(key_entry.rx_mic));
1149
1150                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1151                 rt2800_register_multiwrite(rt2x00dev, offset,
1152                                               &key_entry, sizeof(key_entry));
1153         }
1154
1155         /*
1156          * Update WCID information
1157          */
1158         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1159
1160         return 0;
1161 }
1162 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1163
1164 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1165                           const unsigned int filter_flags)
1166 {
1167         u32 reg;
1168
1169         /*
1170          * Start configuration steps.
1171          * Note that the version error will always be dropped
1172          * and broadcast frames will always be accepted since
1173          * there is no filter for it at this time.
1174          */
1175         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1176         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1177                            !(filter_flags & FIF_FCSFAIL));
1178         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1179                            !(filter_flags & FIF_PLCPFAIL));
1180         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1181                            !(filter_flags & FIF_PROMISC_IN_BSS));
1182         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1183         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1184         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1185                            !(filter_flags & FIF_ALLMULTI));
1186         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1187         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1188         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1189                            !(filter_flags & FIF_CONTROL));
1190         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1191                            !(filter_flags & FIF_CONTROL));
1192         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1193                            !(filter_flags & FIF_CONTROL));
1194         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1195                            !(filter_flags & FIF_CONTROL));
1196         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1197                            !(filter_flags & FIF_CONTROL));
1198         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1199                            !(filter_flags & FIF_PSPOLL));
1200         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1201         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1202         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1203                            !(filter_flags & FIF_CONTROL));
1204         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1205 }
1206 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1207
1208 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1209                         struct rt2x00intf_conf *conf, const unsigned int flags)
1210 {
1211         u32 reg;
1212         bool update_bssid = false;
1213
1214         if (flags & CONFIG_UPDATE_TYPE) {
1215                 /*
1216                  * Enable synchronisation.
1217                  */
1218                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1219                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1220                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1221         }
1222
1223         if (flags & CONFIG_UPDATE_MAC) {
1224                 if (flags & CONFIG_UPDATE_TYPE &&
1225                     conf->sync == TSF_SYNC_AP_NONE) {
1226                         /*
1227                          * The BSSID register has to be set to our own mac
1228                          * address in AP mode.
1229                          */
1230                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1231                         update_bssid = true;
1232                 }
1233
1234                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1235                         reg = le32_to_cpu(conf->mac[1]);
1236                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1237                         conf->mac[1] = cpu_to_le32(reg);
1238                 }
1239
1240                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1241                                               conf->mac, sizeof(conf->mac));
1242         }
1243
1244         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1245                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1246                         reg = le32_to_cpu(conf->bssid[1]);
1247                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1248                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1249                         conf->bssid[1] = cpu_to_le32(reg);
1250                 }
1251
1252                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1253                                               conf->bssid, sizeof(conf->bssid));
1254         }
1255 }
1256 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1257
1258 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1259                                     struct rt2x00lib_erp *erp)
1260 {
1261         bool any_sta_nongf = !!(erp->ht_opmode &
1262                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1263         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1264         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1265         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1266         u32 reg;
1267
1268         /* default protection rate for HT20: OFDM 24M */
1269         mm20_rate = gf20_rate = 0x4004;
1270
1271         /* default protection rate for HT40: duplicate OFDM 24M */
1272         mm40_rate = gf40_rate = 0x4084;
1273
1274         switch (protection) {
1275         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1276                 /*
1277                  * All STAs in this BSS are HT20/40 but there might be
1278                  * STAs not supporting greenfield mode.
1279                  * => Disable protection for HT transmissions.
1280                  */
1281                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1282
1283                 break;
1284         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1285                 /*
1286                  * All STAs in this BSS are HT20 or HT20/40 but there
1287                  * might be STAs not supporting greenfield mode.
1288                  * => Protect all HT40 transmissions.
1289                  */
1290                 mm20_mode = gf20_mode = 0;
1291                 mm40_mode = gf40_mode = 2;
1292
1293                 break;
1294         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1295                 /*
1296                  * Nonmember protection:
1297                  * According to 802.11n we _should_ protect all
1298                  * HT transmissions (but we don't have to).
1299                  *
1300                  * But if cts_protection is enabled we _shall_ protect
1301                  * all HT transmissions using a CCK rate.
1302                  *
1303                  * And if any station is non GF we _shall_ protect
1304                  * GF transmissions.
1305                  *
1306                  * We decide to protect everything
1307                  * -> fall through to mixed mode.
1308                  */
1309         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1310                 /*
1311                  * Legacy STAs are present
1312                  * => Protect all HT transmissions.
1313                  */
1314                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1315
1316                 /*
1317                  * If erp protection is needed we have to protect HT
1318                  * transmissions with CCK 11M long preamble.
1319                  */
1320                 if (erp->cts_protection) {
1321                         /* don't duplicate RTS/CTS in CCK mode */
1322                         mm20_rate = mm40_rate = 0x0003;
1323                         gf20_rate = gf40_rate = 0x0003;
1324                 }
1325                 break;
1326         };
1327
1328         /* check for STAs not supporting greenfield mode */
1329         if (any_sta_nongf)
1330                 gf20_mode = gf40_mode = 2;
1331
1332         /* Update HT protection config */
1333         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1334         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1335         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1336         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1337
1338         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1339         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1340         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1341         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1342
1343         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1344         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1345         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1346         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1347
1348         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1349         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1350         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1351         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1352 }
1353
1354 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1355                        u32 changed)
1356 {
1357         u32 reg;
1358
1359         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1360                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1361                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1362                                    !!erp->short_preamble);
1363                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1364                                    !!erp->short_preamble);
1365                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1366         }
1367
1368         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1369                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1370                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1371                                    erp->cts_protection ? 2 : 0);
1372                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1373         }
1374
1375         if (changed & BSS_CHANGED_BASIC_RATES) {
1376                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1377                                          erp->basic_rates);
1378                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1379         }
1380
1381         if (changed & BSS_CHANGED_ERP_SLOT) {
1382                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1383                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1384                                    erp->slot_time);
1385                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1386
1387                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1388                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1389                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1390         }
1391
1392         if (changed & BSS_CHANGED_BEACON_INT) {
1393                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1394                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1395                                    erp->beacon_int * 16);
1396                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1397         }
1398
1399         if (changed & BSS_CHANGED_HT)
1400                 rt2800_config_ht_opmode(rt2x00dev, erp);
1401 }
1402 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1403
1404 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1405                                      enum antenna ant)
1406 {
1407         u32 reg;
1408         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1409         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1410
1411         if (rt2x00_is_pci(rt2x00dev)) {
1412                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1413                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1414                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1415         } else if (rt2x00_is_usb(rt2x00dev))
1416                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1417                                    eesk_pin, 0);
1418
1419         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1420         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1421         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1422         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1423 }
1424
1425 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1426 {
1427         u8 r1;
1428         u8 r3;
1429         u16 eeprom;
1430
1431         rt2800_bbp_read(rt2x00dev, 1, &r1);
1432         rt2800_bbp_read(rt2x00dev, 3, &r3);
1433
1434         /*
1435          * Configure the TX antenna.
1436          */
1437         switch (ant->tx_chain_num) {
1438         case 1:
1439                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1440                 break;
1441         case 2:
1442                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1443                 break;
1444         case 3:
1445                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1446                 break;
1447         }
1448
1449         /*
1450          * Configure the RX antenna.
1451          */
1452         switch (ant->rx_chain_num) {
1453         case 1:
1454                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1455                     rt2x00_rt(rt2x00dev, RT3090) ||
1456                     rt2x00_rt(rt2x00dev, RT3390)) {
1457                         rt2x00_eeprom_read(rt2x00dev,
1458                                            EEPROM_NIC_CONF1, &eeprom);
1459                         if (rt2x00_get_field16(eeprom,
1460                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1461                                 rt2800_set_ant_diversity(rt2x00dev,
1462                                                 rt2x00dev->default_ant.rx);
1463                 }
1464                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1465                 break;
1466         case 2:
1467                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1468                 break;
1469         case 3:
1470                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1471                 break;
1472         }
1473
1474         rt2800_bbp_write(rt2x00dev, 3, r3);
1475         rt2800_bbp_write(rt2x00dev, 1, r1);
1476 }
1477 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1478
1479 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1480                                    struct rt2x00lib_conf *libconf)
1481 {
1482         u16 eeprom;
1483         short lna_gain;
1484
1485         if (libconf->rf.channel <= 14) {
1486                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1487                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1488         } else if (libconf->rf.channel <= 64) {
1489                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1490                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1491         } else if (libconf->rf.channel <= 128) {
1492                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1493                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1494         } else {
1495                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1496                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1497         }
1498
1499         rt2x00dev->lna_gain = lna_gain;
1500 }
1501
1502 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1503                                          struct ieee80211_conf *conf,
1504                                          struct rf_channel *rf,
1505                                          struct channel_info *info)
1506 {
1507         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1508
1509         if (rt2x00dev->default_ant.tx_chain_num == 1)
1510                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1511
1512         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1513                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1514                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1515         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1516                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1517
1518         if (rf->channel > 14) {
1519                 /*
1520                  * When TX power is below 0, we should increase it by 7 to
1521                  * make it a positive value (Minimum value is -7).
1522                  * However this means that values between 0 and 7 have
1523                  * double meaning, and we should set a 7DBm boost flag.
1524                  */
1525                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1526                                    (info->default_power1 >= 0));
1527
1528                 if (info->default_power1 < 0)
1529                         info->default_power1 += 7;
1530
1531                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1532
1533                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1534                                    (info->default_power2 >= 0));
1535
1536                 if (info->default_power2 < 0)
1537                         info->default_power2 += 7;
1538
1539                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1540         } else {
1541                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1542                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1543         }
1544
1545         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1546
1547         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1548         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1549         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1550         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1551
1552         udelay(200);
1553
1554         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1555         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1556         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1557         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1558
1559         udelay(200);
1560
1561         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1562         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1563         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1564         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1565 }
1566
1567 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1568                                          struct ieee80211_conf *conf,
1569                                          struct rf_channel *rf,
1570                                          struct channel_info *info)
1571 {
1572         u8 rfcsr;
1573
1574         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1575         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1576
1577         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1578         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1579         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1580
1581         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1582         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1583         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1584
1585         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1586         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1587         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1588
1589         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1590         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1591         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1592
1593         rt2800_rfcsr_write(rt2x00dev, 24,
1594                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1595
1596         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1597         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1598         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1599 }
1600
1601
1602 #define RT5390_POWER_BOUND     0x27
1603 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1604
1605 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1606                                          struct ieee80211_conf *conf,
1607                                          struct rf_channel *rf,
1608                                          struct channel_info *info)
1609 {
1610         u8 rfcsr;
1611         u16 eeprom;
1612
1613         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1614         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1615         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1616         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1617         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1618
1619         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1620         if (info->default_power1 > RT5390_POWER_BOUND)
1621                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1622         else
1623                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1624         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1625
1626         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1627         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1628         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1629         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1630         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1631         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1632
1633         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1634         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1635                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1636                                   RT5390_FREQ_OFFSET_BOUND);
1637         else
1638                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1639         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1640
1641         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1642         if (rf->channel <= 14) {
1643                 int idx = rf->channel-1;
1644
1645                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
1646                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1647                                 /* r55/r59 value array of channel 1~14 */
1648                                 static const char r55_bt_rev[] = {0x83, 0x83,
1649                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1650                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1651                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1652                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1653                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1654
1655                                 rt2800_rfcsr_write(rt2x00dev, 55,
1656                                                    r55_bt_rev[idx]);
1657                                 rt2800_rfcsr_write(rt2x00dev, 59,
1658                                                    r59_bt_rev[idx]);
1659                         } else {
1660                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1661                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1662                                         0x88, 0x88, 0x86, 0x85, 0x84};
1663
1664                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1665                         }
1666                 } else {
1667                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1668                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1669                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1670                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1671                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1672                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1673                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1674
1675                                 rt2800_rfcsr_write(rt2x00dev, 55,
1676                                                    r55_nonbt_rev[idx]);
1677                                 rt2800_rfcsr_write(rt2x00dev, 59,
1678                                                    r59_nonbt_rev[idx]);
1679                         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1680                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1681                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1682                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1683
1684                                 rt2800_rfcsr_write(rt2x00dev, 59,
1685                                                    r59_non_bt[idx]);
1686                         }
1687                 }
1688         }
1689
1690         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1691         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1692         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1693         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1694
1695         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1696         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1697         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1698 }
1699
1700 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1701                                   struct ieee80211_conf *conf,
1702                                   struct rf_channel *rf,
1703                                   struct channel_info *info)
1704 {
1705         u32 reg;
1706         unsigned int tx_pin;
1707         u8 bbp;
1708
1709         if (rf->channel <= 14) {
1710                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1711                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1712         } else {
1713                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1714                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1715         }
1716
1717         if (rt2x00_rf(rt2x00dev, RF2020) ||
1718             rt2x00_rf(rt2x00dev, RF3020) ||
1719             rt2x00_rf(rt2x00dev, RF3021) ||
1720             rt2x00_rf(rt2x00dev, RF3022) ||
1721             rt2x00_rf(rt2x00dev, RF3052) ||
1722             rt2x00_rf(rt2x00dev, RF3320))
1723                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1724         else if (rt2x00_rf(rt2x00dev, RF5390))
1725                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1726         else
1727                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1728
1729         /*
1730          * Change BBP settings
1731          */
1732         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1733         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1734         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1735         rt2800_bbp_write(rt2x00dev, 86, 0);
1736
1737         if (rf->channel <= 14) {
1738                 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1739                         if (test_bit(CONFIG_EXTERNAL_LNA_BG,
1740                                      &rt2x00dev->flags)) {
1741                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1742                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1743                         } else {
1744                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1745                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1746                         }
1747                 }
1748         } else {
1749                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1750
1751                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1752                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1753                 else
1754                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1755         }
1756
1757         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1758         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1759         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1760         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1761         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1762
1763         tx_pin = 0;
1764
1765         /* Turn on unused PA or LNA when not using 1T or 1R */
1766         if (rt2x00dev->default_ant.tx_chain_num == 2) {
1767                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1768                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1769         }
1770
1771         /* Turn on unused PA or LNA when not using 1T or 1R */
1772         if (rt2x00dev->default_ant.rx_chain_num == 2) {
1773                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1774                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1775         }
1776
1777         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1778         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1779         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1780         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1781         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1782         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1783
1784         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1785
1786         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1787         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1788         rt2800_bbp_write(rt2x00dev, 4, bbp);
1789
1790         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1791         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1792         rt2800_bbp_write(rt2x00dev, 3, bbp);
1793
1794         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1795                 if (conf_is_ht40(conf)) {
1796                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1797                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1798                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1799                 } else {
1800                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1801                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1802                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1803                 }
1804         }
1805
1806         msleep(1);
1807
1808         /*
1809          * Clear channel statistic counters
1810          */
1811         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1812         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1813         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1814 }
1815
1816 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
1817                                       enum ieee80211_band band)
1818 {
1819         u16 eeprom;
1820         u8 comp_en;
1821         u8 comp_type;
1822         int comp_value;
1823
1824         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1825
1826         if (eeprom == 0xffff)
1827                 return 0;
1828
1829         if (band == IEEE80211_BAND_2GHZ) {
1830                 comp_en = rt2x00_get_field16(eeprom,
1831                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
1832                 if (comp_en) {
1833                         comp_type = rt2x00_get_field16(eeprom,
1834                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
1835                         comp_value = rt2x00_get_field16(eeprom,
1836                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
1837                         if (!comp_type)
1838                                 comp_value = -comp_value;
1839                 }
1840         } else {
1841                 comp_en = rt2x00_get_field16(eeprom,
1842                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
1843                 if (comp_en) {
1844                         comp_type = rt2x00_get_field16(eeprom,
1845                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
1846                         comp_value = rt2x00_get_field16(eeprom,
1847                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
1848                         if (!comp_type)
1849                                 comp_value = -comp_value;
1850                 }
1851         }
1852
1853         return comp_value;
1854 }
1855
1856 static u8 rt2800_compesate_txpower(struct rt2x00_dev *rt2x00dev,
1857                                      int is_rate_b,
1858                                      enum ieee80211_band band,
1859                                      int power_level,
1860                                      u8 txpower)
1861 {
1862         u32 reg;
1863         u16 eeprom;
1864         u8 criterion;
1865         u8 eirp_txpower;
1866         u8 eirp_txpower_criterion;
1867         u8 reg_limit;
1868         int bw_comp = 0;
1869
1870         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
1871                 return txpower;
1872
1873         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1874                 bw_comp = rt2800_get_txpower_bw_comp(rt2x00dev, band);
1875
1876         if (test_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags)) {
1877                 /*
1878                  * Check if eirp txpower exceed txpower_limit.
1879                  * We use OFDM 6M as criterion and its eirp txpower
1880                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
1881                  * .11b data rate need add additional 4dbm
1882                  * when calculating eirp txpower.
1883                  */
1884                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1885                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
1886
1887                 rt2x00_eeprom_read(rt2x00dev,
1888                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
1889
1890                 if (band == IEEE80211_BAND_2GHZ)
1891                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1892                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
1893                 else
1894                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1895                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
1896
1897                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
1898                                        (is_rate_b ? 4 : 0) + bw_comp;
1899
1900                 reg_limit = (eirp_txpower > power_level) ?
1901                                         (eirp_txpower - power_level) : 0;
1902         } else
1903                 reg_limit = 0;
1904
1905         return txpower + bw_comp - reg_limit;
1906 }
1907
1908 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1909                                   struct ieee80211_conf *conf)
1910 {
1911         u8 txpower;
1912         u16 eeprom;
1913         int i, is_rate_b;
1914         u32 reg;
1915         u8 r1;
1916         u32 offset;
1917         enum ieee80211_band band = conf->channel->band;
1918         int power_level = conf->power_level;
1919
1920         /*
1921          * set to normal bbp tx power control mode: +/- 0dBm
1922          */
1923         rt2800_bbp_read(rt2x00dev, 1, &r1);
1924         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
1925         rt2800_bbp_write(rt2x00dev, 1, r1);
1926         offset = TX_PWR_CFG_0;
1927
1928         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1929                 /* just to be safe */
1930                 if (offset > TX_PWR_CFG_4)
1931                         break;
1932
1933                 rt2800_register_read(rt2x00dev, offset, &reg);
1934
1935                 /* read the next four txpower values */
1936                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1937                                    &eeprom);
1938
1939                 is_rate_b = i ? 0 : 1;
1940                 /*
1941                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1942                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1943                  * TX_PWR_CFG_4: unknown
1944                  */
1945                 txpower = rt2x00_get_field16(eeprom,
1946                                              EEPROM_TXPOWER_BYRATE_RATE0);
1947                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1948                                              power_level, txpower);
1949                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
1950
1951                 /*
1952                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1953                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1954                  * TX_PWR_CFG_4: unknown
1955                  */
1956                 txpower = rt2x00_get_field16(eeprom,
1957                                              EEPROM_TXPOWER_BYRATE_RATE1);
1958                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1959                                              power_level, txpower);
1960                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
1961
1962                 /*
1963                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
1964                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
1965                  * TX_PWR_CFG_4: unknown
1966                  */
1967                 txpower = rt2x00_get_field16(eeprom,
1968                                              EEPROM_TXPOWER_BYRATE_RATE2);
1969                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1970                                              power_level, txpower);
1971                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
1972
1973                 /*
1974                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1975                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
1976                  * TX_PWR_CFG_4: unknown
1977                  */
1978                 txpower = rt2x00_get_field16(eeprom,
1979                                              EEPROM_TXPOWER_BYRATE_RATE3);
1980                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1981                                              power_level, txpower);
1982                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
1983
1984                 /* read the next four txpower values */
1985                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1986                                    &eeprom);
1987
1988                 is_rate_b = 0;
1989                 /*
1990                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1991                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1992                  * TX_PWR_CFG_4: unknown
1993                  */
1994                 txpower = rt2x00_get_field16(eeprom,
1995                                              EEPROM_TXPOWER_BYRATE_RATE0);
1996                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1997                                              power_level, txpower);
1998                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
1999
2000                 /*
2001                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2002                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2003                  * TX_PWR_CFG_4: unknown
2004                  */
2005                 txpower = rt2x00_get_field16(eeprom,
2006                                              EEPROM_TXPOWER_BYRATE_RATE1);
2007                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
2008                                              power_level, txpower);
2009                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2010
2011                 /*
2012                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2013                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2014                  * TX_PWR_CFG_4: unknown
2015                  */
2016                 txpower = rt2x00_get_field16(eeprom,
2017                                              EEPROM_TXPOWER_BYRATE_RATE2);
2018                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
2019                                              power_level, txpower);
2020                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2021
2022                 /*
2023                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2024                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2025                  * TX_PWR_CFG_4: unknown
2026                  */
2027                 txpower = rt2x00_get_field16(eeprom,
2028                                              EEPROM_TXPOWER_BYRATE_RATE3);
2029                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
2030                                              power_level, txpower);
2031                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2032
2033                 rt2800_register_write(rt2x00dev, offset, reg);
2034
2035                 /* next TX_PWR_CFG register */
2036                 offset += 4;
2037         }
2038 }
2039
2040 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2041                                       struct rt2x00lib_conf *libconf)
2042 {
2043         u32 reg;
2044
2045         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2046         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2047                            libconf->conf->short_frame_max_tx_count);
2048         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2049                            libconf->conf->long_frame_max_tx_count);
2050         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2051 }
2052
2053 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2054                              struct rt2x00lib_conf *libconf)
2055 {
2056         enum dev_state state =
2057             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2058                 STATE_SLEEP : STATE_AWAKE;
2059         u32 reg;
2060
2061         if (state == STATE_SLEEP) {
2062                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2063
2064                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2065                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2066                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2067                                    libconf->conf->listen_interval - 1);
2068                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2069                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2070
2071                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2072         } else {
2073                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2074                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2075                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2076                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2077                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2078
2079                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2080         }
2081 }
2082
2083 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2084                    struct rt2x00lib_conf *libconf,
2085                    const unsigned int flags)
2086 {
2087         /* Always recalculate LNA gain before changing configuration */
2088         rt2800_config_lna_gain(rt2x00dev, libconf);
2089
2090         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2091                 rt2800_config_channel(rt2x00dev, libconf->conf,
2092                                       &libconf->rf, &libconf->channel);
2093                 rt2800_config_txpower(rt2x00dev, libconf->conf);
2094         }
2095         if (flags & IEEE80211_CONF_CHANGE_POWER)
2096                 rt2800_config_txpower(rt2x00dev, libconf->conf);
2097         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2098                 rt2800_config_retry_limit(rt2x00dev, libconf);
2099         if (flags & IEEE80211_CONF_CHANGE_PS)
2100                 rt2800_config_ps(rt2x00dev, libconf);
2101 }
2102 EXPORT_SYMBOL_GPL(rt2800_config);
2103
2104 /*
2105  * Link tuning
2106  */
2107 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2108 {
2109         u32 reg;
2110
2111         /*
2112          * Update FCS error count from register.
2113          */
2114         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2115         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2116 }
2117 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2118
2119 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2120 {
2121         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2122                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2123                     rt2x00_rt(rt2x00dev, RT3071) ||
2124                     rt2x00_rt(rt2x00dev, RT3090) ||
2125                     rt2x00_rt(rt2x00dev, RT3390) ||
2126                     rt2x00_rt(rt2x00dev, RT5390))
2127                         return 0x1c + (2 * rt2x00dev->lna_gain);
2128                 else
2129                         return 0x2e + rt2x00dev->lna_gain;
2130         }
2131
2132         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2133                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2134         else
2135                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2136 }
2137
2138 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2139                                   struct link_qual *qual, u8 vgc_level)
2140 {
2141         if (qual->vgc_level != vgc_level) {
2142                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2143                 qual->vgc_level = vgc_level;
2144                 qual->vgc_level_reg = vgc_level;
2145         }
2146 }
2147
2148 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2149 {
2150         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2151 }
2152 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2153
2154 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2155                        const u32 count)
2156 {
2157         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2158                 return;
2159
2160         /*
2161          * When RSSI is better then -80 increase VGC level with 0x10
2162          */
2163         rt2800_set_vgc(rt2x00dev, qual,
2164                        rt2800_get_default_vgc(rt2x00dev) +
2165                        ((qual->rssi > -80) * 0x10));
2166 }
2167 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2168
2169 /*
2170  * Initialization functions.
2171  */
2172 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2173 {
2174         u32 reg;
2175         u16 eeprom;
2176         unsigned int i;
2177         int ret;
2178
2179         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2180         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2181         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2182         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2183         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2184         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2185         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2186
2187         ret = rt2800_drv_init_registers(rt2x00dev);
2188         if (ret)
2189                 return ret;
2190
2191         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2192         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2193         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2194         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2195         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2196         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2197
2198         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2199         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2200         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2201         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2202         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2203         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2204
2205         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2206         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2207
2208         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2209
2210         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2211         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2212         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2213         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2214         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2215         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2216         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2217         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2218
2219         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2220
2221         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2222         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2223         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2224         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2225
2226         if (rt2x00_rt(rt2x00dev, RT3071) ||
2227             rt2x00_rt(rt2x00dev, RT3090) ||
2228             rt2x00_rt(rt2x00dev, RT3390)) {
2229                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2230                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2231                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2232                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2233                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2234                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2235                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2236                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2237                                                       0x0000002c);
2238                         else
2239                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2240                                                       0x0000000f);
2241                 } else {
2242                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2243                 }
2244         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2245                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2246
2247                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2248                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2249                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2250                 } else {
2251                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2252                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2253                 }
2254         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2255                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2256                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2257                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
2258         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2259                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2260                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2261                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2262         } else {
2263                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2264                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2265         }
2266
2267         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2268         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2269         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2270         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2271         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2272         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2273         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2274         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2275         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2276         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2277
2278         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2279         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2280         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2281         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2282         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2283
2284         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2285         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2286         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2287             rt2x00_rt(rt2x00dev, RT2883) ||
2288             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2289                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2290         else
2291                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2292         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2293         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2294         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2295
2296         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2297         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2298         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2299         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2300         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2301         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2302         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2303         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2304         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2305
2306         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2307
2308         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2309         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2310         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2311         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2312         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2313         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2314         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2315         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2316
2317         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2318         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2319         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2320         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2321         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2322         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2323         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2324         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2325         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2326
2327         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2328         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2329         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2330         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2331         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2332         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2333         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2334         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2335         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2336         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2337         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2338         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2339
2340         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2341         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2342         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2343         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2344         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2345         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2346         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2347         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2348         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2349         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2350         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2351         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2352
2353         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2354         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2355         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2356         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2357         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2358         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2359         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2360         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2361         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2362         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2363         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2364         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2365
2366         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2367         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2368         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2369         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2370         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2371         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2372         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2373         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2374         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2375         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2376         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2377         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2378
2379         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2380         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2381         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2382         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2383         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2384         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2385         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2386         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2387         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2388         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2389         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2390         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2391
2392         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2393         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2394         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2395         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2396         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2397         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2398         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2399         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2400         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2401         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2402         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2403         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2404
2405         if (rt2x00_is_usb(rt2x00dev)) {
2406                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2407
2408                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2409                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2410                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2411                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2412                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2413                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2414                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2415                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2416                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2417                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2418                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2419         }
2420
2421         /*
2422          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2423          * although it is reserved.
2424          */
2425         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2426         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2427         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2428         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2429         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2430         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2431         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2432         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2433         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2434         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2435         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2436         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2437
2438         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2439
2440         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2441         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2442         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2443                            IEEE80211_MAX_RTS_THRESHOLD);
2444         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2445         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2446
2447         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2448
2449         /*
2450          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2451          * time should be set to 16. However, the original Ralink driver uses
2452          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2453          * connection problems with 11g + CTS protection. Hence, use the same
2454          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2455          */
2456         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2457         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2458         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2459         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2460         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2461         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2462         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2463
2464         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2465
2466         /*
2467          * ASIC will keep garbage value after boot, clear encryption keys.
2468          */
2469         for (i = 0; i < 4; i++)
2470                 rt2800_register_write(rt2x00dev,
2471                                          SHARED_KEY_MODE_ENTRY(i), 0);
2472
2473         for (i = 0; i < 256; i++) {
2474                 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2475                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2476                                               wcid, sizeof(wcid));
2477
2478                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0);
2479                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2480         }
2481
2482         /*
2483          * Clear all beacons
2484          */
2485         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2486         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2487         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2488         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2489         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2490         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2491         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2492         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2493
2494         if (rt2x00_is_usb(rt2x00dev)) {
2495                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2496                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2497                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2498         } else if (rt2x00_is_pcie(rt2x00dev)) {
2499                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2500                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2501                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2502         }
2503
2504         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2505         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2506         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2507         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2508         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2509         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2510         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2511         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2512         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2513         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2514
2515         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2516         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2517         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2518         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2519         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2520         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2521         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2522         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2523         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2524         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2525
2526         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2527         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2528         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2529         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2530         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2531         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2532         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2533         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2534         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2535         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2536
2537         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2538         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2539         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2540         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2541         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2542         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2543
2544         /*
2545          * Do not force the BA window size, we use the TXWI to set it
2546          */
2547         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2548         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2549         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2550         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2551
2552         /*
2553          * We must clear the error counters.
2554          * These registers are cleared on read,
2555          * so we may pass a useless variable to store the value.
2556          */
2557         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2558         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2559         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2560         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2561         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2562         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2563
2564         /*
2565          * Setup leadtime for pre tbtt interrupt to 6ms
2566          */
2567         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2568         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2569         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2570
2571         /*
2572          * Set up channel statistics timer
2573          */
2574         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2575         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2576         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2577         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2578         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2579         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2580         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2581
2582         return 0;
2583 }
2584
2585 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2586 {
2587         unsigned int i;
2588         u32 reg;
2589
2590         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2591                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2592                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2593                         return 0;
2594
2595                 udelay(REGISTER_BUSY_DELAY);
2596         }
2597
2598         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2599         return -EACCES;
2600 }
2601
2602 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2603 {
2604         unsigned int i;
2605         u8 value;
2606
2607         /*
2608          * BBP was enabled after firmware was loaded,
2609          * but we need to reactivate it now.
2610          */
2611         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2612         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2613         msleep(1);
2614
2615         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2616                 rt2800_bbp_read(rt2x00dev, 0, &value);
2617                 if ((value != 0xff) && (value != 0x00))
2618                         return 0;
2619                 udelay(REGISTER_BUSY_DELAY);
2620         }
2621
2622         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2623         return -EACCES;
2624 }
2625
2626 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2627 {
2628         unsigned int i;
2629         u16 eeprom;
2630         u8 reg_id;
2631         u8 value;
2632
2633         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2634                      rt2800_wait_bbp_ready(rt2x00dev)))
2635                 return -EACCES;
2636
2637         if (rt2x00_rt(rt2x00dev, RT5390)) {
2638                 rt2800_bbp_read(rt2x00dev, 4, &value);
2639                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2640                 rt2800_bbp_write(rt2x00dev, 4, value);
2641         }
2642
2643         if (rt2800_is_305x_soc(rt2x00dev) ||
2644             rt2x00_rt(rt2x00dev, RT5390))
2645                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2646
2647         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2648         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2649
2650         if (rt2x00_rt(rt2x00dev, RT5390))
2651                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2652
2653         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2654                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2655                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2656         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2657                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2658                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2659                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2660                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2661                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
2662         } else {
2663                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2664                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2665         }
2666
2667         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2668
2669         if (rt2x00_rt(rt2x00dev, RT3070) ||
2670             rt2x00_rt(rt2x00dev, RT3071) ||
2671             rt2x00_rt(rt2x00dev, RT3090) ||
2672             rt2x00_rt(rt2x00dev, RT3390) ||
2673             rt2x00_rt(rt2x00dev, RT5390)) {
2674                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2675                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2676                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2677         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2678                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2679                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2680         } else {
2681                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2682         }
2683
2684         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2685         if (rt2x00_rt(rt2x00dev, RT5390))
2686                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2687         else
2688                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2689
2690         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2691                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2692         else if (rt2x00_rt(rt2x00dev, RT5390))
2693                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2694         else
2695                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2696
2697         if (rt2x00_rt(rt2x00dev, RT5390))
2698                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2699         else
2700                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2701
2702         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2703
2704         if (rt2x00_rt(rt2x00dev, RT5390))
2705                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2706         else
2707                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2708
2709         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2710             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2711             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2712             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2713             rt2x00_rt(rt2x00dev, RT5390) ||
2714             rt2800_is_305x_soc(rt2x00dev))
2715                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2716         else
2717                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2718
2719         if (rt2x00_rt(rt2x00dev, RT5390))
2720                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
2721
2722         if (rt2800_is_305x_soc(rt2x00dev))
2723                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2724         else if (rt2x00_rt(rt2x00dev, RT5390))
2725                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
2726         else
2727                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2728
2729         if (rt2x00_rt(rt2x00dev, RT5390))
2730                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2731         else
2732                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2733
2734         if (rt2x00_rt(rt2x00dev, RT5390))
2735                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
2736
2737         if (rt2x00_rt(rt2x00dev, RT3071) ||
2738             rt2x00_rt(rt2x00dev, RT3090) ||
2739             rt2x00_rt(rt2x00dev, RT3390) ||
2740             rt2x00_rt(rt2x00dev, RT5390)) {
2741                 rt2800_bbp_read(rt2x00dev, 138, &value);
2742
2743                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2744                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2745                         value |= 0x20;
2746                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2747                         value &= ~0x02;
2748
2749                 rt2800_bbp_write(rt2x00dev, 138, value);
2750         }
2751
2752         if (rt2x00_rt(rt2x00dev, RT5390)) {
2753                 int ant, div_mode;
2754
2755                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2756                 div_mode = rt2x00_get_field16(eeprom,
2757                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
2758                 ant = (div_mode == 3) ? 1 : 0;
2759
2760                 /* check if this is a Bluetooth combo card */
2761                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2762                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
2763                         u32 reg;
2764
2765                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2766                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2767                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2768                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2769                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2770                         if (ant == 0)
2771                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2772                         else if (ant == 1)
2773                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2774                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2775                 }
2776
2777                 rt2800_bbp_read(rt2x00dev, 152, &value);
2778                 if (ant == 0)
2779                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2780                 else
2781                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2782                 rt2800_bbp_write(rt2x00dev, 152, value);
2783
2784                 /* Init frequency calibration */
2785                 rt2800_bbp_write(rt2x00dev, 142, 1);
2786                 rt2800_bbp_write(rt2x00dev, 143, 57);
2787         }
2788
2789         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2790                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2791
2792                 if (eeprom != 0xffff && eeprom != 0x0000) {
2793                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2794                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2795                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2796                 }
2797         }
2798
2799         return 0;
2800 }
2801
2802 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2803                                 bool bw40, u8 rfcsr24, u8 filter_target)
2804 {
2805         unsigned int i;
2806         u8 bbp;
2807         u8 rfcsr;
2808         u8 passband;
2809         u8 stopband;
2810         u8 overtuned = 0;
2811
2812         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2813
2814         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2815         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2816         rt2800_bbp_write(rt2x00dev, 4, bbp);
2817
2818         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2819         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2820         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2821
2822         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2823         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2824         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2825
2826         /*
2827          * Set power & frequency of passband test tone
2828          */
2829         rt2800_bbp_write(rt2x00dev, 24, 0);
2830
2831         for (i = 0; i < 100; i++) {
2832                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2833                 msleep(1);
2834
2835                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2836                 if (passband)
2837                         break;
2838         }
2839
2840         /*
2841          * Set power & frequency of stopband test tone
2842          */
2843         rt2800_bbp_write(rt2x00dev, 24, 0x06);
2844
2845         for (i = 0; i < 100; i++) {
2846                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2847                 msleep(1);
2848
2849                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2850
2851                 if ((passband - stopband) <= filter_target) {
2852                         rfcsr24++;
2853                         overtuned += ((passband - stopband) == filter_target);
2854                 } else
2855                         break;
2856
2857                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2858         }
2859
2860         rfcsr24 -= !!overtuned;
2861
2862         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2863         return rfcsr24;
2864 }
2865
2866 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2867 {
2868         u8 rfcsr;
2869         u8 bbp;
2870         u32 reg;
2871         u16 eeprom;
2872
2873         if (!rt2x00_rt(rt2x00dev, RT3070) &&
2874             !rt2x00_rt(rt2x00dev, RT3071) &&
2875             !rt2x00_rt(rt2x00dev, RT3090) &&
2876             !rt2x00_rt(rt2x00dev, RT3390) &&
2877             !rt2x00_rt(rt2x00dev, RT5390) &&
2878             !rt2800_is_305x_soc(rt2x00dev))
2879                 return 0;
2880
2881         /*
2882          * Init RF calibration.
2883          */
2884         if (rt2x00_rt(rt2x00dev, RT5390)) {
2885                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
2886                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
2887                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2888                 msleep(1);
2889                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
2890                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2891         } else {
2892                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2893                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2894                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2895                 msleep(1);
2896                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2897                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2898         }
2899
2900         if (rt2x00_rt(rt2x00dev, RT3070) ||
2901             rt2x00_rt(rt2x00dev, RT3071) ||
2902             rt2x00_rt(rt2x00dev, RT3090)) {
2903                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2904                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2905                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2906                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
2907                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2908                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2909                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2910                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2911                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2912                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2913                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2914                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2915                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2916                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2917                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2918                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2919                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2920                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2921                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2922         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2923                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2924                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2925                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2926                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2927                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2928                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2929                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2930                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2931                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2932                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2933                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2934                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2935                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2936                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2937                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2938                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2939                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2940                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2941                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2942                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2943                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2944                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2945                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2946                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2947                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2948                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2949                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2950                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2951                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2952                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2953                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2954                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2955         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2956                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2957                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2958                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2959                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2960                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2961                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2962                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2963                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2964                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2965                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2966                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2967                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2968                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2969                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2970                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2971                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2972                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2973                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2974                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2975                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2976                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2977                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2978                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2979                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2980                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2981                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2982                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2983                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2984                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2985                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2986                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2987                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2988                 return 0;
2989         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2990                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
2991                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
2992                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
2993                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
2994                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2995                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
2996                 else
2997                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
2998                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
2999                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3000                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3001                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3002                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3003                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3004                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3005                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3006                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3007                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3008
3009                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3010                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3011                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3012                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3013                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3014                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3015                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3016                 else
3017                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3018                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3019                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3020                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3021                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3022
3023                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3024                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3025                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3026                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3027                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3028                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3029                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3030                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3031                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3032                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3033
3034                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3035                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3036                 else
3037                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3038                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3039                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3040                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3041                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3042                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3043                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3044                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3045                 else
3046                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3047                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3048                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3049                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3050
3051                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3052                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3053                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3054                 else
3055                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3056                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3057                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3058                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3059                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3060                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3061                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3062
3063                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3064                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3065                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3066                 else
3067                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3068                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3069                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3070         }
3071
3072         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3073                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3074                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3075                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3076                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3077         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3078                    rt2x00_rt(rt2x00dev, RT3090)) {
3079                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3080
3081                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3082                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3083                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3084
3085                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3086                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3087                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3088                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3089                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3090                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3091                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3092                         else
3093                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3094                 }
3095                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3096
3097                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3098                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3099                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3100         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3101                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3102                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3103                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3104         }
3105
3106         /*
3107          * Set RX Filter calibration for 20MHz and 40MHz
3108          */
3109         if (rt2x00_rt(rt2x00dev, RT3070)) {
3110                 rt2x00dev->calibration[0] =
3111                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3112                 rt2x00dev->calibration[1] =
3113                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3114         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3115                    rt2x00_rt(rt2x00dev, RT3090) ||
3116                    rt2x00_rt(rt2x00dev, RT3390)) {
3117                 rt2x00dev->calibration[0] =
3118                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3119                 rt2x00dev->calibration[1] =
3120                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3121         }
3122
3123         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3124                 /*
3125                  * Set back to initial state
3126                  */
3127                 rt2800_bbp_write(rt2x00dev, 24, 0);
3128
3129                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3130                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3131                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3132
3133                 /*
3134                  * Set BBP back to BW20
3135                  */
3136                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3137                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3138                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3139         }
3140
3141         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3142             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3143             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3144             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3145                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3146
3147         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3148         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3149         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3150
3151         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3152                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3153                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3154                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3155                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3156                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3157                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3158                         if (!test_bit(CONFIG_EXTERNAL_LNA_BG,
3159                                       &rt2x00dev->flags))
3160                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3161                 }
3162                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3163                 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3164                         rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3165                                         rt2x00_get_field16(eeprom,
3166                                                 EEPROM_TXMIXER_GAIN_BG_VAL));
3167                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3168         }
3169
3170         if (rt2x00_rt(rt2x00dev, RT3090)) {
3171                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3172
3173                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3174                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3175                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3176                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3177                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3178                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3179
3180                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3181         }
3182
3183         if (rt2x00_rt(rt2x00dev, RT3071) ||
3184             rt2x00_rt(rt2x00dev, RT3090) ||
3185             rt2x00_rt(rt2x00dev, RT3390)) {
3186                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3187                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3188                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3189                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3190                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3191                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3192                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3193
3194                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3195                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3196                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3197
3198                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3199                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3200                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3201
3202                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3203                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3204                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3205         }
3206
3207         if (rt2x00_rt(rt2x00dev, RT3070)) {
3208                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3209                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3210                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3211                 else
3212                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3213                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3214                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3215                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3216                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3217         }
3218
3219         if (rt2x00_rt(rt2x00dev, RT5390)) {
3220                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3221                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3222                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3223
3224                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3225                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3226                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3227
3228                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3229                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3230                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3231         }
3232
3233         return 0;
3234 }
3235
3236 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3237 {
3238         u32 reg;
3239         u16 word;
3240
3241         /*
3242          * Initialize all registers.
3243          */
3244         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3245                      rt2800_init_registers(rt2x00dev) ||
3246                      rt2800_init_bbp(rt2x00dev) ||
3247                      rt2800_init_rfcsr(rt2x00dev)))
3248                 return -EIO;
3249
3250         /*
3251          * Send signal to firmware during boot time.
3252          */
3253         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3254
3255         if (rt2x00_is_usb(rt2x00dev) &&
3256             (rt2x00_rt(rt2x00dev, RT3070) ||
3257              rt2x00_rt(rt2x00dev, RT3071) ||
3258              rt2x00_rt(rt2x00dev, RT3572))) {
3259                 udelay(200);
3260                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3261                 udelay(10);
3262         }
3263
3264         /*
3265          * Enable RX.
3266          */
3267         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3268         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3269         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3270         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3271
3272         udelay(50);
3273
3274         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3275         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3276         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3277         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3278         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3279         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3280
3281         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3282         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3283         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3284         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3285
3286         /*
3287          * Initialize LED control
3288          */
3289         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3290         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3291                            word & 0xff, (word >> 8) & 0xff);
3292
3293         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3294         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3295                            word & 0xff, (word >> 8) & 0xff);
3296
3297         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3298         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3299                            word & 0xff, (word >> 8) & 0xff);
3300
3301         return 0;
3302 }
3303 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3304
3305 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3306 {
3307         u32 reg;
3308
3309         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3310         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3311         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3312         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3313
3314         /* Wait for DMA, ignore error */
3315         rt2800_wait_wpdma_ready(rt2x00dev);
3316
3317         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3318         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3319         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3320         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3321 }
3322 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3323
3324 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3325 {
3326         u32 reg;
3327
3328         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3329
3330         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3331 }
3332 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3333
3334 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3335 {
3336         u32 reg;
3337
3338         mutex_lock(&rt2x00dev->csr_mutex);
3339
3340         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3341         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3342         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3343         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3344         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3345
3346         /* Wait until the EEPROM has been loaded */
3347         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3348
3349         /* Apparently the data is read from end to start */
3350         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
3351                                         (u32 *)&rt2x00dev->eeprom[i]);
3352         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
3353                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
3354         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
3355                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
3356         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
3357                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
3358
3359         mutex_unlock(&rt2x00dev->csr_mutex);
3360 }
3361
3362 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3363 {
3364         unsigned int i;
3365
3366         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3367                 rt2800_efuse_read(rt2x00dev, i);
3368 }
3369 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3370
3371 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3372 {
3373         u16 word;
3374         u8 *mac;
3375         u8 default_lna_gain;
3376
3377         /*
3378          * Start validation of the data that has been read.
3379          */
3380         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3381         if (!is_valid_ether_addr(mac)) {
3382                 random_ether_addr(mac);
3383                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3384         }
3385
3386         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3387         if (word == 0xffff) {
3388                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3389                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3390                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3391                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3392                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3393         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3394                    rt2x00_rt(rt2x00dev, RT2872)) {
3395                 /*
3396                  * There is a max of 2 RX streams for RT28x0 series
3397                  */
3398                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3399                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3400                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3401         }
3402
3403         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3404         if (word == 0xffff) {
3405                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3406                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3407                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3408                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3409                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3410                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3411                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3412                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3413                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3414                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3415                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3416                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3417                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3418                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3419                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3420                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3421                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3422         }
3423
3424         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3425         if ((word & 0x00ff) == 0x00ff) {
3426                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3427                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3428                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3429         }
3430         if ((word & 0xff00) == 0xff00) {
3431                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3432                                    LED_MODE_TXRX_ACTIVITY);
3433                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3434                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3435                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3436                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3437                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3438                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3439         }
3440
3441         /*
3442          * During the LNA validation we are going to use
3443          * lna0 as correct value. Note that EEPROM_LNA
3444          * is never validated.
3445          */
3446         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3447         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3448
3449         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3450         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3451                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3452         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3453                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3454         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3455
3456         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3457         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3458                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3459         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3460             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3461                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3462                                    default_lna_gain);
3463         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3464
3465         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3466         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3467                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3468         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3469                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3470         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3471
3472         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3473         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3474                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3475         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3476             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3477                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3478                                    default_lna_gain);
3479         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3480
3481         return 0;
3482 }
3483 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3484
3485 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3486 {
3487         u32 reg;
3488         u16 value;
3489         u16 eeprom;
3490
3491         /*
3492          * Read EEPROM word for configuration.
3493          */
3494         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3495
3496         /*
3497          * Identify RF chipset by EEPROM value
3498          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3499          * RT53xx: defined in "EEPROM_CHIP_ID" field
3500          */
3501         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3502         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3503                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3504         else
3505                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3506
3507         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3508                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3509
3510         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3511             !rt2x00_rt(rt2x00dev, RT2872) &&
3512             !rt2x00_rt(rt2x00dev, RT2883) &&
3513             !rt2x00_rt(rt2x00dev, RT3070) &&
3514             !rt2x00_rt(rt2x00dev, RT3071) &&
3515             !rt2x00_rt(rt2x00dev, RT3090) &&
3516             !rt2x00_rt(rt2x00dev, RT3390) &&
3517             !rt2x00_rt(rt2x00dev, RT3572) &&
3518             !rt2x00_rt(rt2x00dev, RT5390)) {
3519                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3520                 return -ENODEV;
3521         }
3522
3523         if (!rt2x00_rf(rt2x00dev, RF2820) &&
3524             !rt2x00_rf(rt2x00dev, RF2850) &&
3525             !rt2x00_rf(rt2x00dev, RF2720) &&
3526             !rt2x00_rf(rt2x00dev, RF2750) &&
3527             !rt2x00_rf(rt2x00dev, RF3020) &&
3528             !rt2x00_rf(rt2x00dev, RF2020) &&
3529             !rt2x00_rf(rt2x00dev, RF3021) &&
3530             !rt2x00_rf(rt2x00dev, RF3022) &&
3531             !rt2x00_rf(rt2x00dev, RF3052) &&
3532             !rt2x00_rf(rt2x00dev, RF3320) &&
3533             !rt2x00_rf(rt2x00dev, RF5390)) {
3534                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3535                 return -ENODEV;
3536         }
3537
3538         /*
3539          * Identify default antenna configuration.
3540          */
3541         rt2x00dev->default_ant.tx_chain_num =
3542             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3543         rt2x00dev->default_ant.rx_chain_num =
3544             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3545
3546         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3547
3548         if (rt2x00_rt(rt2x00dev, RT3070) ||
3549             rt2x00_rt(rt2x00dev, RT3090) ||
3550             rt2x00_rt(rt2x00dev, RT3390)) {
3551                 value = rt2x00_get_field16(eeprom,
3552                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3553                 switch (value) {
3554                 case 0:
3555                 case 1:
3556                 case 2:
3557                         rt2x00dev->default_ant.tx = ANTENNA_A;
3558                         rt2x00dev->default_ant.rx = ANTENNA_A;
3559                         break;
3560                 case 3:
3561                         rt2x00dev->default_ant.tx = ANTENNA_A;
3562                         rt2x00dev->default_ant.rx = ANTENNA_B;
3563                         break;
3564                 }
3565         } else {
3566                 rt2x00dev->default_ant.tx = ANTENNA_A;
3567                 rt2x00dev->default_ant.rx = ANTENNA_A;
3568         }
3569
3570         /*
3571          * Read frequency offset and RF programming sequence.
3572          */
3573         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3574         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3575
3576         /*
3577          * Read external LNA informations.
3578          */
3579         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3580
3581         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
3582                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
3583         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3584                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3585
3586         /*
3587          * Detect if this device has an hardware controlled radio.
3588          */
3589         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3590                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3591
3592         /*
3593          * Store led settings, for correct led behaviour.
3594          */
3595 #ifdef CONFIG_RT2X00_LIB_LEDS
3596         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3597         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3598         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3599
3600         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3601 #endif /* CONFIG_RT2X00_LIB_LEDS */
3602
3603         /*
3604          * Check if support EIRP tx power limit feature.
3605          */
3606         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3607
3608         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3609                                         EIRP_MAX_TX_POWER_LIMIT)
3610                 __set_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags);
3611
3612         return 0;
3613 }
3614 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3615
3616 /*
3617  * RF value list for rt28xx
3618  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3619  */
3620 static const struct rf_channel rf_vals[] = {
3621         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3622         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3623         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3624         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3625         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3626         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3627         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3628         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3629         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3630         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3631         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3632         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3633         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3634         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3635
3636         /* 802.11 UNI / HyperLan 2 */
3637         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3638         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3639         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3640         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3641         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3642         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3643         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3644         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3645         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3646         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3647         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3648         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3649
3650         /* 802.11 HyperLan 2 */
3651         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3652         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3653         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3654         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3655         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3656         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3657         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3658         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3659         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3660         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3661         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3662         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3663         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3664         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3665         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3666         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3667
3668         /* 802.11 UNII */
3669         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3670         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3671         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3672         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3673         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3674         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3675         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3676         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3677         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3678         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3679         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3680
3681         /* 802.11 Japan */
3682         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3683         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3684         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3685         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3686         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3687         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3688         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3689 };
3690
3691 /*
3692  * RF value list for rt3xxx
3693  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3694  */
3695 static const struct rf_channel rf_vals_3x[] = {
3696         {1,  241, 2, 2 },
3697         {2,  241, 2, 7 },
3698         {3,  242, 2, 2 },
3699         {4,  242, 2, 7 },
3700         {5,  243, 2, 2 },
3701         {6,  243, 2, 7 },
3702         {7,  244, 2, 2 },
3703         {8,  244, 2, 7 },
3704         {9,  245, 2, 2 },
3705         {10, 245, 2, 7 },
3706         {11, 246, 2, 2 },
3707         {12, 246, 2, 7 },
3708         {13, 247, 2, 2 },
3709         {14, 248, 2, 4 },
3710
3711         /* 802.11 UNI / HyperLan 2 */
3712         {36, 0x56, 0, 4},
3713         {38, 0x56, 0, 6},
3714         {40, 0x56, 0, 8},
3715         {44, 0x57, 0, 0},
3716         {46, 0x57, 0, 2},
3717         {48, 0x57, 0, 4},
3718         {52, 0x57, 0, 8},
3719         {54, 0x57, 0, 10},
3720         {56, 0x58, 0, 0},
3721         {60, 0x58, 0, 4},
3722         {62, 0x58, 0, 6},
3723         {64, 0x58, 0, 8},
3724
3725         /* 802.11 HyperLan 2 */
3726         {100, 0x5b, 0, 8},
3727         {102, 0x5b, 0, 10},
3728         {104, 0x5c, 0, 0},
3729         {108, 0x5c, 0, 4},
3730         {110, 0x5c, 0, 6},
3731         {112, 0x5c, 0, 8},
3732         {116, 0x5d, 0, 0},
3733         {118, 0x5d, 0, 2},
3734         {120, 0x5d, 0, 4},
3735         {124, 0x5d, 0, 8},
3736         {126, 0x5d, 0, 10},
3737         {128, 0x5e, 0, 0},
3738         {132, 0x5e, 0, 4},
3739         {134, 0x5e, 0, 6},
3740         {136, 0x5e, 0, 8},
3741         {140, 0x5f, 0, 0},
3742
3743         /* 802.11 UNII */
3744         {149, 0x5f, 0, 9},
3745         {151, 0x5f, 0, 11},
3746         {153, 0x60, 0, 1},
3747         {157, 0x60, 0, 5},
3748         {159, 0x60, 0, 7},
3749         {161, 0x60, 0, 9},
3750         {165, 0x61, 0, 1},
3751         {167, 0x61, 0, 3},
3752         {169, 0x61, 0, 5},
3753         {171, 0x61, 0, 7},
3754         {173, 0x61, 0, 9},
3755 };
3756
3757 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3758 {
3759         struct hw_mode_spec *spec = &rt2x00dev->spec;
3760         struct channel_info *info;
3761         char *default_power1;
3762         char *default_power2;
3763         unsigned int i;
3764         u16 eeprom;
3765
3766         /*
3767          * Disable powersaving as default on PCI devices.
3768          */
3769         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3770                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3771
3772         /*
3773          * Initialize all hw fields.
3774          */
3775         rt2x00dev->hw->flags =
3776             IEEE80211_HW_SIGNAL_DBM |
3777             IEEE80211_HW_SUPPORTS_PS |
3778             IEEE80211_HW_PS_NULLFUNC_STACK |
3779             IEEE80211_HW_AMPDU_AGGREGATION;
3780         /*
3781          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3782          * unless we are capable of sending the buffered frames out after the
3783          * DTIM transmission using rt2x00lib_beacondone. This will send out
3784          * multicast and broadcast traffic immediately instead of buffering it
3785          * infinitly and thus dropping it after some time.
3786          */
3787         if (!rt2x00_is_usb(rt2x00dev))
3788                 rt2x00dev->hw->flags |=
3789                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
3790
3791         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3792         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3793                                 rt2x00_eeprom_addr(rt2x00dev,
3794                                                    EEPROM_MAC_ADDR_0));
3795
3796         /*
3797          * As rt2800 has a global fallback table we cannot specify
3798          * more then one tx rate per frame but since the hw will
3799          * try several rates (based on the fallback table) we should
3800          * initialize max_report_rates to the maximum number of rates
3801          * we are going to try. Otherwise mac80211 will truncate our
3802          * reported tx rates and the rc algortihm will end up with
3803          * incorrect data.
3804          */
3805         rt2x00dev->hw->max_rates = 1;
3806         rt2x00dev->hw->max_report_rates = 7;
3807         rt2x00dev->hw->max_rate_tries = 1;
3808
3809         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3810
3811         /*
3812          * Initialize hw_mode information.
3813          */
3814         spec->supported_bands = SUPPORT_BAND_2GHZ;
3815         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3816
3817         if (rt2x00_rf(rt2x00dev, RF2820) ||
3818             rt2x00_rf(rt2x00dev, RF2720)) {
3819                 spec->num_channels = 14;
3820                 spec->channels = rf_vals;
3821         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3822                    rt2x00_rf(rt2x00dev, RF2750)) {
3823                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3824                 spec->num_channels = ARRAY_SIZE(rf_vals);
3825                 spec->channels = rf_vals;
3826         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3827                    rt2x00_rf(rt2x00dev, RF2020) ||
3828                    rt2x00_rf(rt2x00dev, RF3021) ||
3829                    rt2x00_rf(rt2x00dev, RF3022) ||
3830                    rt2x00_rf(rt2x00dev, RF3320) ||
3831                    rt2x00_rf(rt2x00dev, RF5390)) {
3832                 spec->num_channels = 14;
3833                 spec->channels = rf_vals_3x;
3834         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3835                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3836                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3837                 spec->channels = rf_vals_3x;
3838         }
3839
3840         /*
3841          * Initialize HT information.
3842          */
3843         if (!rt2x00_rf(rt2x00dev, RF2020))
3844                 spec->ht.ht_supported = true;
3845         else
3846                 spec->ht.ht_supported = false;
3847
3848         spec->ht.cap =
3849             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3850             IEEE80211_HT_CAP_GRN_FLD |
3851             IEEE80211_HT_CAP_SGI_20 |
3852             IEEE80211_HT_CAP_SGI_40;
3853
3854         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
3855                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3856
3857         spec->ht.cap |=
3858             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
3859                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3860
3861         spec->ht.ampdu_factor = 3;
3862         spec->ht.ampdu_density = 4;
3863         spec->ht.mcs.tx_params =
3864             IEEE80211_HT_MCS_TX_DEFINED |
3865             IEEE80211_HT_MCS_TX_RX_DIFF |
3866             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
3867                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3868
3869         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
3870         case 3:
3871                 spec->ht.mcs.rx_mask[2] = 0xff;
3872         case 2:
3873                 spec->ht.mcs.rx_mask[1] = 0xff;
3874         case 1:
3875                 spec->ht.mcs.rx_mask[0] = 0xff;
3876                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3877                 break;
3878         }
3879
3880         /*
3881          * Create channel information array
3882          */
3883         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
3884         if (!info)
3885                 return -ENOMEM;
3886
3887         spec->channels_info = info;
3888
3889         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3890         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3891
3892         for (i = 0; i < 14; i++) {
3893                 info[i].default_power1 = default_power1[i];
3894                 info[i].default_power2 = default_power2[i];
3895         }
3896
3897         if (spec->num_channels > 14) {
3898                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3899                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3900
3901                 for (i = 14; i < spec->num_channels; i++) {
3902                         info[i].default_power1 = default_power1[i];
3903                         info[i].default_power2 = default_power2[i];
3904                 }
3905         }
3906
3907         return 0;
3908 }
3909 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3910
3911 /*
3912  * IEEE80211 stack callback functions.
3913  */
3914 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3915                          u16 *iv16)
3916 {
3917         struct rt2x00_dev *rt2x00dev = hw->priv;
3918         struct mac_iveiv_entry iveiv_entry;
3919         u32 offset;
3920
3921         offset = MAC_IVEIV_ENTRY(hw_key_idx);
3922         rt2800_register_multiread(rt2x00dev, offset,
3923                                       &iveiv_entry, sizeof(iveiv_entry));
3924
3925         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3926         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
3927 }
3928 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
3929
3930 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3931 {
3932         struct rt2x00_dev *rt2x00dev = hw->priv;
3933         u32 reg;
3934         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3935
3936         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3937         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3938         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3939
3940         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3941         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3942         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3943
3944         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3945         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3946         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3947
3948         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3949         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3950         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3951
3952         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3953         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3954         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3955
3956         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3957         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3958         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3959
3960         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3961         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3962         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3963
3964         return 0;
3965 }
3966 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
3967
3968 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3969                    const struct ieee80211_tx_queue_params *params)
3970 {
3971         struct rt2x00_dev *rt2x00dev = hw->priv;
3972         struct data_queue *queue;
3973         struct rt2x00_field32 field;
3974         int retval;
3975         u32 reg;
3976         u32 offset;
3977
3978         /*
3979          * First pass the configuration through rt2x00lib, that will
3980          * update the queue settings and validate the input. After that
3981          * we are free to update the registers based on the value
3982          * in the queue parameter.
3983          */
3984         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3985         if (retval)
3986                 return retval;
3987
3988         /*
3989          * We only need to perform additional register initialization
3990          * for WMM queues/
3991          */
3992         if (queue_idx >= 4)
3993                 return 0;
3994
3995         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
3996
3997         /* Update WMM TXOP register */
3998         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3999         field.bit_offset = (queue_idx & 1) * 16;
4000         field.bit_mask = 0xffff << field.bit_offset;
4001
4002         rt2800_register_read(rt2x00dev, offset, &reg);
4003         rt2x00_set_field32(&reg, field, queue->txop);
4004         rt2800_register_write(rt2x00dev, offset, reg);
4005
4006         /* Update WMM registers */
4007         field.bit_offset = queue_idx * 4;
4008         field.bit_mask = 0xf << field.bit_offset;
4009
4010         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4011         rt2x00_set_field32(&reg, field, queue->aifs);
4012         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4013
4014         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4015         rt2x00_set_field32(&reg, field, queue->cw_min);
4016         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4017
4018         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4019         rt2x00_set_field32(&reg, field, queue->cw_max);
4020         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4021
4022         /* Update EDCA registers */
4023         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4024
4025         rt2800_register_read(rt2x00dev, offset, &reg);
4026         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4027         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4028         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4029         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4030         rt2800_register_write(rt2x00dev, offset, reg);
4031
4032         return 0;
4033 }
4034 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4035
4036 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
4037 {
4038         struct rt2x00_dev *rt2x00dev = hw->priv;
4039         u64 tsf;
4040         u32 reg;
4041
4042         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4043         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4044         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4045         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4046
4047         return tsf;
4048 }
4049 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4050
4051 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4052                         enum ieee80211_ampdu_mlme_action action,
4053                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4054                         u8 buf_size)
4055 {
4056         int ret = 0;
4057
4058         switch (action) {
4059         case IEEE80211_AMPDU_RX_START:
4060         case IEEE80211_AMPDU_RX_STOP:
4061                 /*
4062                  * The hw itself takes care of setting up BlockAck mechanisms.
4063                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4064                  * agreement. Once that is done, the hw will BlockAck incoming
4065                  * AMPDUs without further setup.
4066                  */
4067                 break;
4068         case IEEE80211_AMPDU_TX_START:
4069                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4070                 break;
4071         case IEEE80211_AMPDU_TX_STOP:
4072                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4073                 break;
4074         case IEEE80211_AMPDU_TX_OPERATIONAL:
4075                 break;
4076         default:
4077                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4078         }
4079
4080         return ret;
4081 }
4082 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4083
4084 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4085                       struct survey_info *survey)
4086 {
4087         struct rt2x00_dev *rt2x00dev = hw->priv;
4088         struct ieee80211_conf *conf = &hw->conf;
4089         u32 idle, busy, busy_ext;
4090
4091         if (idx != 0)
4092                 return -ENOENT;
4093
4094         survey->channel = conf->channel;
4095
4096         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4097         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4098         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4099
4100         if (idle || busy) {
4101                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4102                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4103                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4104
4105                 survey->channel_time = (idle + busy) / 1000;
4106                 survey->channel_time_busy = busy / 1000;
4107                 survey->channel_time_ext_busy = busy_ext / 1000;
4108         }
4109
4110         return 0;
4111
4112 }
4113 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4114
4115 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4116 MODULE_VERSION(DRV_VERSION);
4117 MODULE_DESCRIPTION("Ralink RT2800 library");
4118 MODULE_LICENSE("GPL");