rt2x00: Split rt2x00dev->flags
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7         Based on the original rt2800pci.c and rt2800usb.c.
8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14           <http://rt2x00.serialmonkey.com>
15
16         This program is free software; you can redistribute it and/or modify
17         it under the terms of the GNU General Public License as published by
18         the Free Software Foundation; either version 2 of the License, or
19         (at your option) any later version.
20
21         This program is distributed in the hope that it will be useful,
22         but WITHOUT ANY WARRANTY; without even the implied warranty of
23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24         GNU General Public License for more details.
25
26         You should have received a copy of the GNU General Public License
27         along with this program; if not, write to the
28         Free Software Foundation, Inc.,
29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30  */
31
32 /*
33         Module: rt2800lib
34         Abstract: rt2800 generic device routines.
35  */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47  * Register access.
48  * All access to the CSR registers will go through the methods
49  * rt2800_register_read and rt2800_register_write.
50  * BBP and RF register require indirect register access,
51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
52  * These indirect registers work with busy bits,
53  * and we will try maximal REGISTER_BUSY_COUNT times to access
54  * the register while taking a REGISTER_BUSY_DELAY us delay
55  * between each attampt. When the busy bit is still set at that time,
56  * the access attempt is considered to have failed,
57  * and we will print an error.
58  * The _lock versions must be used if you already hold the csr_mutex
59  */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68                             H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72         /* check for rt2872 on SoC */
73         if (!rt2x00_is_soc(rt2x00dev) ||
74             !rt2x00_rt(rt2x00dev, RT2872))
75                 return false;
76
77         /* we know for sure that these rf chipsets are used on rt305x boards */
78         if (rt2x00_rf(rt2x00dev, RF3020) ||
79             rt2x00_rf(rt2x00dev, RF3021) ||
80             rt2x00_rf(rt2x00dev, RF3022))
81                 return true;
82
83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84         return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88                              const unsigned int word, const u8 value)
89 {
90         u32 reg;
91
92         mutex_lock(&rt2x00dev->csr_mutex);
93
94         /*
95          * Wait until the BBP becomes available, afterwards we
96          * can safely write the new data into the register.
97          */
98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99                 reg = 0;
100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107         }
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113                             const unsigned int word, u8 *value)
114 {
115         u32 reg;
116
117         mutex_lock(&rt2x00dev->csr_mutex);
118
119         /*
120          * Wait until the BBP becomes available, afterwards we
121          * can safely write the read request into the register.
122          * After the data has been written, we wait until hardware
123          * returns the correct value, if at any time the register
124          * doesn't become available in time, reg will be 0xffffffff
125          * which means we return 0xff to the caller.
126          */
127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128                 reg = 0;
129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136                 WAIT_FOR_BBP(rt2x00dev, &reg);
137         }
138
139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141         mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145                                const unsigned int word, const u8 value)
146 {
147         u32 reg;
148
149         mutex_lock(&rt2x00dev->csr_mutex);
150
151         /*
152          * Wait until the RFCSR becomes available, afterwards we
153          * can safely write the new data into the register.
154          */
155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156                 reg = 0;
157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163         }
164
165         mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169                               const unsigned int word, u8 *value)
170 {
171         u32 reg;
172
173         mutex_lock(&rt2x00dev->csr_mutex);
174
175         /*
176          * Wait until the RFCSR becomes available, afterwards we
177          * can safely write the read request into the register.
178          * After the data has been written, we wait until hardware
179          * returns the correct value, if at any time the register
180          * doesn't become available in time, reg will be 0xffffffff
181          * which means we return 0xff to the caller.
182          */
183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184                 reg = 0;
185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192         }
193
194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196         mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200                             const unsigned int word, const u32 value)
201 {
202         u32 reg;
203
204         mutex_lock(&rt2x00dev->csr_mutex);
205
206         /*
207          * Wait until the RF becomes available, afterwards we
208          * can safely write the new data into the register.
209          */
210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211                 reg = 0;
212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218                 rt2x00_rf_write(rt2x00dev, word, value);
219         }
220
221         mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225                         const u8 command, const u8 token,
226                         const u8 arg0, const u8 arg1)
227 {
228         u32 reg;
229
230         /*
231          * SOC devices don't support MCU requests.
232          */
233         if (rt2x00_is_soc(rt2x00dev))
234                 return;
235
236         mutex_lock(&rt2x00dev->csr_mutex);
237
238         /*
239          * Wait until the MCU becomes available, afterwards we
240          * can safely write the new data into the register.
241          */
242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249                 reg = 0;
250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252         }
253
254         mutex_unlock(&rt2x00dev->csr_mutex);
255 }
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
257
258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259 {
260         unsigned int i = 0;
261         u32 reg;
262
263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265                 if (reg && reg != ~0)
266                         return 0;
267                 msleep(1);
268         }
269
270         ERROR(rt2x00dev, "Unstable hardware.\n");
271         return -EBUSY;
272 }
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276 {
277         unsigned int i;
278         u32 reg;
279
280         /*
281          * Some devices are really slow to respond here. Wait a whole second
282          * before timing out.
283          */
284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288                         return 0;
289
290                 msleep(10);
291         }
292
293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294         return -EACCES;
295 }
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299 {
300         u16 fw_crc;
301         u16 crc;
302
303         /*
304          * The last 2 bytes in the firmware array are the crc checksum itself,
305          * this means that we should never pass those 2 bytes to the crc
306          * algorithm.
307          */
308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310         /*
311          * Use the crc ccitt algorithm.
312          * This will return the same value as the legacy driver which
313          * used bit ordering reversion on the both the firmware bytes
314          * before input input as well as on the final output.
315          * Obviously using crc ccitt directly is much more efficient.
316          */
317         crc = crc_ccitt(~0, data, len - 2);
318
319         /*
320          * There is a small difference between the crc-itu-t + bitrev and
321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
322          * will be swapped, use swab16 to convert the crc to the correct
323          * value.
324          */
325         crc = swab16(crc);
326
327         return fw_crc == crc;
328 }
329
330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331                           const u8 *data, const size_t len)
332 {
333         size_t offset = 0;
334         size_t fw_len;
335         bool multiple;
336
337         /*
338          * PCI(e) & SOC devices require firmware with a length
339          * of 8kb. USB devices require firmware files with a length
340          * of 4kb. Certain USB chipsets however require different firmware,
341          * which Ralink only provides attached to the original firmware
342          * file. Thus for USB devices, firmware files have a length
343          * which is a multiple of 4kb.
344          */
345         if (rt2x00_is_usb(rt2x00dev)) {
346                 fw_len = 4096;
347                 multiple = true;
348         } else {
349                 fw_len = 8192;
350                 multiple = true;
351         }
352
353         /*
354          * Validate the firmware length
355          */
356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
357                 return FW_BAD_LENGTH;
358
359         /*
360          * Check if the chipset requires one of the upper parts
361          * of the firmware.
362          */
363         if (rt2x00_is_usb(rt2x00dev) &&
364             !rt2x00_rt(rt2x00dev, RT2860) &&
365             !rt2x00_rt(rt2x00dev, RT2872) &&
366             !rt2x00_rt(rt2x00dev, RT3070) &&
367             ((len / fw_len) == 1))
368                 return FW_BAD_VERSION;
369
370         /*
371          * 8kb firmware files must be checked as if it were
372          * 2 separate firmware files.
373          */
374         while (offset < len) {
375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376                         return FW_BAD_CRC;
377
378                 offset += fw_len;
379         }
380
381         return FW_OK;
382 }
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386                          const u8 *data, const size_t len)
387 {
388         unsigned int i;
389         u32 reg;
390
391         /*
392          * If driver doesn't wake up firmware here,
393          * rt2800_load_firmware will hang forever when interface is up again.
394          */
395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
396
397         /*
398          * Wait for stable hardware.
399          */
400         if (rt2800_wait_csr_ready(rt2x00dev))
401                 return -EBUSY;
402
403         if (rt2x00_is_pci(rt2x00dev)) {
404                 if (rt2x00_rt(rt2x00dev, RT5390)) {
405                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
406                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
407                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
408                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
409                 }
410                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
411         }
412
413         /*
414          * Disable DMA, will be reenabled later when enabling
415          * the radio.
416          */
417         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
418         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
419         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
420         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
421         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
422         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
423         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
424
425         /*
426          * Write firmware to the device.
427          */
428         rt2800_drv_write_firmware(rt2x00dev, data, len);
429
430         /*
431          * Wait for device to stabilize.
432          */
433         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
434                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
435                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
436                         break;
437                 msleep(1);
438         }
439
440         if (i == REGISTER_BUSY_COUNT) {
441                 ERROR(rt2x00dev, "PBF system register not ready.\n");
442                 return -EBUSY;
443         }
444
445         /*
446          * Initialize firmware.
447          */
448         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
449         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
450         msleep(1);
451
452         return 0;
453 }
454 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
455
456 void rt2800_write_tx_data(struct queue_entry *entry,
457                           struct txentry_desc *txdesc)
458 {
459         __le32 *txwi = rt2800_drv_get_txwi(entry);
460         u32 word;
461
462         /*
463          * Initialize TX Info descriptor
464          */
465         rt2x00_desc_read(txwi, 0, &word);
466         rt2x00_set_field32(&word, TXWI_W0_FRAG,
467                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
468         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
469                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
470         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
471         rt2x00_set_field32(&word, TXWI_W0_TS,
472                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
473         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
474                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
475         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
476                            txdesc->u.ht.mpdu_density);
477         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
478         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
479         rt2x00_set_field32(&word, TXWI_W0_BW,
480                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
481         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
482                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
483         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
484         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
485         rt2x00_desc_write(txwi, 0, word);
486
487         rt2x00_desc_read(txwi, 1, &word);
488         rt2x00_set_field32(&word, TXWI_W1_ACK,
489                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
490         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
491                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
492         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
493         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
494                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
495                            txdesc->key_idx : 0xff);
496         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
497                            txdesc->length);
498         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
499         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
500         rt2x00_desc_write(txwi, 1, word);
501
502         /*
503          * Always write 0 to IV/EIV fields, hardware will insert the IV
504          * from the IVEIV register when TXD_W3_WIV is set to 0.
505          * When TXD_W3_WIV is set to 1 it will use the IV data
506          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
507          * crypto entry in the registers should be used to encrypt the frame.
508          */
509         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
510         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
511 }
512 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
513
514 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
515 {
516         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
517         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
518         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
519         u16 eeprom;
520         u8 offset0;
521         u8 offset1;
522         u8 offset2;
523
524         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
525                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
526                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
527                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
528                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
529                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
530         } else {
531                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
532                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
533                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
534                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
535                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
536         }
537
538         /*
539          * Convert the value from the descriptor into the RSSI value
540          * If the value in the descriptor is 0, it is considered invalid
541          * and the default (extremely low) rssi value is assumed
542          */
543         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
544         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
545         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
546
547         /*
548          * mac80211 only accepts a single RSSI value. Calculating the
549          * average doesn't deliver a fair answer either since -60:-60 would
550          * be considered equally good as -50:-70 while the second is the one
551          * which gives less energy...
552          */
553         rssi0 = max(rssi0, rssi1);
554         return max(rssi0, rssi2);
555 }
556
557 void rt2800_process_rxwi(struct queue_entry *entry,
558                          struct rxdone_entry_desc *rxdesc)
559 {
560         __le32 *rxwi = (__le32 *) entry->skb->data;
561         u32 word;
562
563         rt2x00_desc_read(rxwi, 0, &word);
564
565         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
566         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
567
568         rt2x00_desc_read(rxwi, 1, &word);
569
570         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
571                 rxdesc->flags |= RX_FLAG_SHORT_GI;
572
573         if (rt2x00_get_field32(word, RXWI_W1_BW))
574                 rxdesc->flags |= RX_FLAG_40MHZ;
575
576         /*
577          * Detect RX rate, always use MCS as signal type.
578          */
579         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
580         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
581         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
582
583         /*
584          * Mask of 0x8 bit to remove the short preamble flag.
585          */
586         if (rxdesc->rate_mode == RATE_MODE_CCK)
587                 rxdesc->signal &= ~0x8;
588
589         rt2x00_desc_read(rxwi, 2, &word);
590
591         /*
592          * Convert descriptor AGC value to RSSI value.
593          */
594         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
595
596         /*
597          * Remove RXWI descriptor from start of buffer.
598          */
599         skb_pull(entry->skb, RXWI_DESC_SIZE);
600 }
601 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
602
603 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
604 {
605         __le32 *txwi;
606         u32 word;
607         int wcid, ack, pid;
608         int tx_wcid, tx_ack, tx_pid;
609
610         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
611         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
612         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
613
614         /*
615          * This frames has returned with an IO error,
616          * so the status report is not intended for this
617          * frame.
618          */
619         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
620                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
621                 return false;
622         }
623
624         /*
625          * Validate if this TX status report is intended for
626          * this entry by comparing the WCID/ACK/PID fields.
627          */
628         txwi = rt2800_drv_get_txwi(entry);
629
630         rt2x00_desc_read(txwi, 1, &word);
631         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
632         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
633         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
634
635         if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
636                 WARNING(entry->queue->rt2x00dev,
637                         "TX status report missed for queue %d entry %d\n",
638                 entry->queue->qid, entry->entry_idx);
639                 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
640                 return false;
641         }
642
643         return true;
644 }
645
646 void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
647 {
648         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
649         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
650         struct txdone_entry_desc txdesc;
651         u32 word;
652         u16 mcs, real_mcs;
653         int aggr, ampdu;
654         __le32 *txwi;
655
656         /*
657          * Obtain the status about this packet.
658          */
659         txdesc.flags = 0;
660         txwi = rt2800_drv_get_txwi(entry);
661         rt2x00_desc_read(txwi, 0, &word);
662
663         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
664         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
665
666         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
667         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
668
669         /*
670          * If a frame was meant to be sent as a single non-aggregated MPDU
671          * but ended up in an aggregate the used tx rate doesn't correlate
672          * with the one specified in the TXWI as the whole aggregate is sent
673          * with the same rate.
674          *
675          * For example: two frames are sent to rt2x00, the first one sets
676          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
677          * and requests MCS15. If the hw aggregates both frames into one
678          * AMDPU the tx status for both frames will contain MCS7 although
679          * the frame was sent successfully.
680          *
681          * Hence, replace the requested rate with the real tx rate to not
682          * confuse the rate control algortihm by providing clearly wrong
683          * data.
684          */
685         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
686                 skbdesc->tx_rate_idx = real_mcs;
687                 mcs = real_mcs;
688         }
689
690         if (aggr == 1 || ampdu == 1)
691                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
692
693         /*
694          * Ralink has a retry mechanism using a global fallback
695          * table. We setup this fallback table to try the immediate
696          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
697          * always contains the MCS used for the last transmission, be
698          * it successful or not.
699          */
700         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
701                 /*
702                  * Transmission succeeded. The number of retries is
703                  * mcs - real_mcs
704                  */
705                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
706                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
707         } else {
708                 /*
709                  * Transmission failed. The number of retries is
710                  * always 7 in this case (for a total number of 8
711                  * frames sent).
712                  */
713                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
714                 txdesc.retry = rt2x00dev->long_retry;
715         }
716
717         /*
718          * the frame was retried at least once
719          * -> hw used fallback rates
720          */
721         if (txdesc.retry)
722                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
723
724         rt2x00lib_txdone(entry, &txdesc);
725 }
726 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
727
728 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
729 {
730         struct data_queue *queue;
731         struct queue_entry *entry;
732         u32 reg;
733         u8 pid;
734         int i;
735
736         /*
737          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
738          * at most X times and also stop processing once the TX_STA_FIFO_VALID
739          * flag is not set anymore.
740          *
741          * The legacy drivers use X=TX_RING_SIZE but state in a comment
742          * that the TX_STA_FIFO stack has a size of 16. We stick to our
743          * tx ring size for now.
744          */
745         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
746                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
747                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
748                         break;
749
750                 /*
751                  * Skip this entry when it contains an invalid
752                  * queue identication number.
753                  */
754                 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
755                 if (pid >= QID_RX)
756                         continue;
757
758                 queue = rt2x00queue_get_tx_queue(rt2x00dev, pid);
759                 if (unlikely(!queue))
760                         continue;
761
762                 /*
763                  * Inside each queue, we process each entry in a chronological
764                  * order. We first check that the queue is not empty.
765                  */
766                 entry = NULL;
767                 while (!rt2x00queue_empty(queue)) {
768                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
769                         if (rt2800_txdone_entry_check(entry, reg))
770                                 break;
771                 }
772
773                 if (!entry || rt2x00queue_empty(queue))
774                         break;
775
776                 rt2800_txdone_entry(entry, reg);
777         }
778 }
779 EXPORT_SYMBOL_GPL(rt2800_txdone);
780
781 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
782 {
783         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
784         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
785         unsigned int beacon_base;
786         unsigned int padding_len;
787         u32 orig_reg, reg;
788
789         /*
790          * Disable beaconing while we are reloading the beacon data,
791          * otherwise we might be sending out invalid data.
792          */
793         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
794         orig_reg = reg;
795         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
796         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
797
798         /*
799          * Add space for the TXWI in front of the skb.
800          */
801         skb_push(entry->skb, TXWI_DESC_SIZE);
802         memset(entry->skb, 0, TXWI_DESC_SIZE);
803
804         /*
805          * Register descriptor details in skb frame descriptor.
806          */
807         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
808         skbdesc->desc = entry->skb->data;
809         skbdesc->desc_len = TXWI_DESC_SIZE;
810
811         /*
812          * Add the TXWI for the beacon to the skb.
813          */
814         rt2800_write_tx_data(entry, txdesc);
815
816         /*
817          * Dump beacon to userspace through debugfs.
818          */
819         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
820
821         /*
822          * Write entire beacon with TXWI and padding to register.
823          */
824         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
825         if (padding_len && skb_pad(entry->skb, padding_len)) {
826                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
827                 /* skb freed by skb_pad() on failure */
828                 entry->skb = NULL;
829                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
830                 return;
831         }
832
833         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
834         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
835                                    entry->skb->len + padding_len);
836
837         /*
838          * Enable beaconing again.
839          */
840         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
841         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
842
843         /*
844          * Clean up beacon skb.
845          */
846         dev_kfree_skb_any(entry->skb);
847         entry->skb = NULL;
848 }
849 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
850
851 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
852                                                 unsigned int beacon_base)
853 {
854         int i;
855
856         /*
857          * For the Beacon base registers we only need to clear
858          * the whole TXWI which (when set to 0) will invalidate
859          * the entire beacon.
860          */
861         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
862                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
863 }
864
865 void rt2800_clear_beacon(struct queue_entry *entry)
866 {
867         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
868         u32 reg;
869
870         /*
871          * Disable beaconing while we are reloading the beacon data,
872          * otherwise we might be sending out invalid data.
873          */
874         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
875         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
876         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
877
878         /*
879          * Clear beacon.
880          */
881         rt2800_clear_beacon_register(rt2x00dev,
882                                      HW_BEACON_OFFSET(entry->entry_idx));
883
884         /*
885          * Enabled beaconing again.
886          */
887         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
888         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
889 }
890 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
891
892 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
893 const struct rt2x00debug rt2800_rt2x00debug = {
894         .owner  = THIS_MODULE,
895         .csr    = {
896                 .read           = rt2800_register_read,
897                 .write          = rt2800_register_write,
898                 .flags          = RT2X00DEBUGFS_OFFSET,
899                 .word_base      = CSR_REG_BASE,
900                 .word_size      = sizeof(u32),
901                 .word_count     = CSR_REG_SIZE / sizeof(u32),
902         },
903         .eeprom = {
904                 .read           = rt2x00_eeprom_read,
905                 .write          = rt2x00_eeprom_write,
906                 .word_base      = EEPROM_BASE,
907                 .word_size      = sizeof(u16),
908                 .word_count     = EEPROM_SIZE / sizeof(u16),
909         },
910         .bbp    = {
911                 .read           = rt2800_bbp_read,
912                 .write          = rt2800_bbp_write,
913                 .word_base      = BBP_BASE,
914                 .word_size      = sizeof(u8),
915                 .word_count     = BBP_SIZE / sizeof(u8),
916         },
917         .rf     = {
918                 .read           = rt2x00_rf_read,
919                 .write          = rt2800_rf_write,
920                 .word_base      = RF_BASE,
921                 .word_size      = sizeof(u32),
922                 .word_count     = RF_SIZE / sizeof(u32),
923         },
924 };
925 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
926 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
927
928 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
929 {
930         u32 reg;
931
932         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
933         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
934 }
935 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
936
937 #ifdef CONFIG_RT2X00_LIB_LEDS
938 static void rt2800_brightness_set(struct led_classdev *led_cdev,
939                                   enum led_brightness brightness)
940 {
941         struct rt2x00_led *led =
942             container_of(led_cdev, struct rt2x00_led, led_dev);
943         unsigned int enabled = brightness != LED_OFF;
944         unsigned int bg_mode =
945             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
946         unsigned int polarity =
947                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
948                                    EEPROM_FREQ_LED_POLARITY);
949         unsigned int ledmode =
950                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
951                                    EEPROM_FREQ_LED_MODE);
952         u32 reg;
953
954         /* Check for SoC (SOC devices don't support MCU requests) */
955         if (rt2x00_is_soc(led->rt2x00dev)) {
956                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
957
958                 /* Set LED Polarity */
959                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
960
961                 /* Set LED Mode */
962                 if (led->type == LED_TYPE_RADIO) {
963                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
964                                            enabled ? 3 : 0);
965                 } else if (led->type == LED_TYPE_ASSOC) {
966                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
967                                            enabled ? 3 : 0);
968                 } else if (led->type == LED_TYPE_QUALITY) {
969                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
970                                            enabled ? 3 : 0);
971                 }
972
973                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
974
975         } else {
976                 if (led->type == LED_TYPE_RADIO) {
977                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
978                                               enabled ? 0x20 : 0);
979                 } else if (led->type == LED_TYPE_ASSOC) {
980                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
981                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
982                 } else if (led->type == LED_TYPE_QUALITY) {
983                         /*
984                          * The brightness is divided into 6 levels (0 - 5),
985                          * The specs tell us the following levels:
986                          *      0, 1 ,3, 7, 15, 31
987                          * to determine the level in a simple way we can simply
988                          * work with bitshifting:
989                          *      (1 << level) - 1
990                          */
991                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
992                                               (1 << brightness / (LED_FULL / 6)) - 1,
993                                               polarity);
994                 }
995         }
996 }
997
998 static int rt2800_blink_set(struct led_classdev *led_cdev,
999                             unsigned long *delay_on, unsigned long *delay_off)
1000 {
1001         struct rt2x00_led *led =
1002             container_of(led_cdev, struct rt2x00_led, led_dev);
1003         u32 reg;
1004
1005         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1006         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
1007         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
1008         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1009
1010         return 0;
1011 }
1012
1013 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1014                      struct rt2x00_led *led, enum led_type type)
1015 {
1016         led->rt2x00dev = rt2x00dev;
1017         led->type = type;
1018         led->led_dev.brightness_set = rt2800_brightness_set;
1019         led->led_dev.blink_set = rt2800_blink_set;
1020         led->flags = LED_INITIALIZED;
1021 }
1022 #endif /* CONFIG_RT2X00_LIB_LEDS */
1023
1024 /*
1025  * Configuration handlers.
1026  */
1027 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
1028                                     struct rt2x00lib_crypto *crypto,
1029                                     struct ieee80211_key_conf *key)
1030 {
1031         struct mac_wcid_entry wcid_entry;
1032         struct mac_iveiv_entry iveiv_entry;
1033         u32 offset;
1034         u32 reg;
1035
1036         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1037
1038         if (crypto->cmd == SET_KEY) {
1039                 rt2800_register_read(rt2x00dev, offset, &reg);
1040                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1041                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1042                 /*
1043                  * Both the cipher as the BSS Idx numbers are split in a main
1044                  * value of 3 bits, and a extended field for adding one additional
1045                  * bit to the value.
1046                  */
1047                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1048                                    (crypto->cipher & 0x7));
1049                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1050                                    (crypto->cipher & 0x8) >> 3);
1051                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
1052                                    (crypto->bssidx & 0x7));
1053                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1054                                    (crypto->bssidx & 0x8) >> 3);
1055                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1056                 rt2800_register_write(rt2x00dev, offset, reg);
1057         } else {
1058                 rt2800_register_write(rt2x00dev, offset, 0);
1059         }
1060
1061         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1062
1063         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1064         if ((crypto->cipher == CIPHER_TKIP) ||
1065             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1066             (crypto->cipher == CIPHER_AES))
1067                 iveiv_entry.iv[3] |= 0x20;
1068         iveiv_entry.iv[3] |= key->keyidx << 6;
1069         rt2800_register_multiwrite(rt2x00dev, offset,
1070                                       &iveiv_entry, sizeof(iveiv_entry));
1071
1072         offset = MAC_WCID_ENTRY(key->hw_key_idx);
1073
1074         memset(&wcid_entry, 0, sizeof(wcid_entry));
1075         if (crypto->cmd == SET_KEY)
1076                 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
1077         rt2800_register_multiwrite(rt2x00dev, offset,
1078                                       &wcid_entry, sizeof(wcid_entry));
1079 }
1080
1081 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1082                              struct rt2x00lib_crypto *crypto,
1083                              struct ieee80211_key_conf *key)
1084 {
1085         struct hw_key_entry key_entry;
1086         struct rt2x00_field32 field;
1087         u32 offset;
1088         u32 reg;
1089
1090         if (crypto->cmd == SET_KEY) {
1091                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1092
1093                 memcpy(key_entry.key, crypto->key,
1094                        sizeof(key_entry.key));
1095                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1096                        sizeof(key_entry.tx_mic));
1097                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1098                        sizeof(key_entry.rx_mic));
1099
1100                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1101                 rt2800_register_multiwrite(rt2x00dev, offset,
1102                                               &key_entry, sizeof(key_entry));
1103         }
1104
1105         /*
1106          * The cipher types are stored over multiple registers
1107          * starting with SHARED_KEY_MODE_BASE each word will have
1108          * 32 bits and contains the cipher types for 2 bssidx each.
1109          * Using the correct defines correctly will cause overhead,
1110          * so just calculate the correct offset.
1111          */
1112         field.bit_offset = 4 * (key->hw_key_idx % 8);
1113         field.bit_mask = 0x7 << field.bit_offset;
1114
1115         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1116
1117         rt2800_register_read(rt2x00dev, offset, &reg);
1118         rt2x00_set_field32(&reg, field,
1119                            (crypto->cmd == SET_KEY) * crypto->cipher);
1120         rt2800_register_write(rt2x00dev, offset, reg);
1121
1122         /*
1123          * Update WCID information
1124          */
1125         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1126
1127         return 0;
1128 }
1129 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1130
1131 static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev)
1132 {
1133         int idx;
1134         u32 offset, reg;
1135
1136         /*
1137          * Search for the first free pairwise key entry and return the
1138          * corresponding index.
1139          *
1140          * Make sure the WCID starts _after_ the last possible shared key
1141          * entry (>32).
1142          *
1143          * Since parts of the pairwise key table might be shared with
1144          * the beacon frame buffers 6 & 7 we should only write into the
1145          * first 222 entries.
1146          */
1147         for (idx = 33; idx <= 222; idx++) {
1148                 offset = MAC_WCID_ATTR_ENTRY(idx);
1149                 rt2800_register_read(rt2x00dev, offset, &reg);
1150                 if (!reg)
1151                         return idx;
1152         }
1153         return -1;
1154 }
1155
1156 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1157                                struct rt2x00lib_crypto *crypto,
1158                                struct ieee80211_key_conf *key)
1159 {
1160         struct hw_key_entry key_entry;
1161         u32 offset;
1162         int idx;
1163
1164         if (crypto->cmd == SET_KEY) {
1165                 idx = rt2800_find_pairwise_keyslot(rt2x00dev);
1166                 if (idx < 0)
1167                         return -ENOSPC;
1168                 key->hw_key_idx = idx;
1169
1170                 memcpy(key_entry.key, crypto->key,
1171                        sizeof(key_entry.key));
1172                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1173                        sizeof(key_entry.tx_mic));
1174                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1175                        sizeof(key_entry.rx_mic));
1176
1177                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1178                 rt2800_register_multiwrite(rt2x00dev, offset,
1179                                               &key_entry, sizeof(key_entry));
1180         }
1181
1182         /*
1183          * Update WCID information
1184          */
1185         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1186
1187         return 0;
1188 }
1189 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1190
1191 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1192                           const unsigned int filter_flags)
1193 {
1194         u32 reg;
1195
1196         /*
1197          * Start configuration steps.
1198          * Note that the version error will always be dropped
1199          * and broadcast frames will always be accepted since
1200          * there is no filter for it at this time.
1201          */
1202         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1203         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1204                            !(filter_flags & FIF_FCSFAIL));
1205         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1206                            !(filter_flags & FIF_PLCPFAIL));
1207         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1208                            !(filter_flags & FIF_PROMISC_IN_BSS));
1209         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1210         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1211         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1212                            !(filter_flags & FIF_ALLMULTI));
1213         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1214         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1215         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1216                            !(filter_flags & FIF_CONTROL));
1217         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1218                            !(filter_flags & FIF_CONTROL));
1219         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1220                            !(filter_flags & FIF_CONTROL));
1221         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1222                            !(filter_flags & FIF_CONTROL));
1223         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1224                            !(filter_flags & FIF_CONTROL));
1225         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1226                            !(filter_flags & FIF_PSPOLL));
1227         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1228         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1229         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1230                            !(filter_flags & FIF_CONTROL));
1231         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1232 }
1233 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1234
1235 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1236                         struct rt2x00intf_conf *conf, const unsigned int flags)
1237 {
1238         u32 reg;
1239         bool update_bssid = false;
1240
1241         if (flags & CONFIG_UPDATE_TYPE) {
1242                 /*
1243                  * Enable synchronisation.
1244                  */
1245                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1246                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1247                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1248         }
1249
1250         if (flags & CONFIG_UPDATE_MAC) {
1251                 if (flags & CONFIG_UPDATE_TYPE &&
1252                     conf->sync == TSF_SYNC_AP_NONE) {
1253                         /*
1254                          * The BSSID register has to be set to our own mac
1255                          * address in AP mode.
1256                          */
1257                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1258                         update_bssid = true;
1259                 }
1260
1261                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1262                         reg = le32_to_cpu(conf->mac[1]);
1263                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1264                         conf->mac[1] = cpu_to_le32(reg);
1265                 }
1266
1267                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1268                                               conf->mac, sizeof(conf->mac));
1269         }
1270
1271         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1272                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1273                         reg = le32_to_cpu(conf->bssid[1]);
1274                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1275                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1276                         conf->bssid[1] = cpu_to_le32(reg);
1277                 }
1278
1279                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1280                                               conf->bssid, sizeof(conf->bssid));
1281         }
1282 }
1283 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1284
1285 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1286                                     struct rt2x00lib_erp *erp)
1287 {
1288         bool any_sta_nongf = !!(erp->ht_opmode &
1289                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1290         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1291         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1292         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1293         u32 reg;
1294
1295         /* default protection rate for HT20: OFDM 24M */
1296         mm20_rate = gf20_rate = 0x4004;
1297
1298         /* default protection rate for HT40: duplicate OFDM 24M */
1299         mm40_rate = gf40_rate = 0x4084;
1300
1301         switch (protection) {
1302         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1303                 /*
1304                  * All STAs in this BSS are HT20/40 but there might be
1305                  * STAs not supporting greenfield mode.
1306                  * => Disable protection for HT transmissions.
1307                  */
1308                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1309
1310                 break;
1311         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1312                 /*
1313                  * All STAs in this BSS are HT20 or HT20/40 but there
1314                  * might be STAs not supporting greenfield mode.
1315                  * => Protect all HT40 transmissions.
1316                  */
1317                 mm20_mode = gf20_mode = 0;
1318                 mm40_mode = gf40_mode = 2;
1319
1320                 break;
1321         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1322                 /*
1323                  * Nonmember protection:
1324                  * According to 802.11n we _should_ protect all
1325                  * HT transmissions (but we don't have to).
1326                  *
1327                  * But if cts_protection is enabled we _shall_ protect
1328                  * all HT transmissions using a CCK rate.
1329                  *
1330                  * And if any station is non GF we _shall_ protect
1331                  * GF transmissions.
1332                  *
1333                  * We decide to protect everything
1334                  * -> fall through to mixed mode.
1335                  */
1336         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1337                 /*
1338                  * Legacy STAs are present
1339                  * => Protect all HT transmissions.
1340                  */
1341                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1342
1343                 /*
1344                  * If erp protection is needed we have to protect HT
1345                  * transmissions with CCK 11M long preamble.
1346                  */
1347                 if (erp->cts_protection) {
1348                         /* don't duplicate RTS/CTS in CCK mode */
1349                         mm20_rate = mm40_rate = 0x0003;
1350                         gf20_rate = gf40_rate = 0x0003;
1351                 }
1352                 break;
1353         };
1354
1355         /* check for STAs not supporting greenfield mode */
1356         if (any_sta_nongf)
1357                 gf20_mode = gf40_mode = 2;
1358
1359         /* Update HT protection config */
1360         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1361         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1362         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1363         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1364
1365         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1366         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1367         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1368         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1369
1370         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1371         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1372         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1373         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1374
1375         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1376         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1377         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1378         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1379 }
1380
1381 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1382                        u32 changed)
1383 {
1384         u32 reg;
1385
1386         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1387                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1388                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1389                                    !!erp->short_preamble);
1390                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1391                                    !!erp->short_preamble);
1392                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1393         }
1394
1395         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1396                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1397                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1398                                    erp->cts_protection ? 2 : 0);
1399                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1400         }
1401
1402         if (changed & BSS_CHANGED_BASIC_RATES) {
1403                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1404                                          erp->basic_rates);
1405                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1406         }
1407
1408         if (changed & BSS_CHANGED_ERP_SLOT) {
1409                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1410                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1411                                    erp->slot_time);
1412                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1413
1414                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1415                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1416                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1417         }
1418
1419         if (changed & BSS_CHANGED_BEACON_INT) {
1420                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1421                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1422                                    erp->beacon_int * 16);
1423                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1424         }
1425
1426         if (changed & BSS_CHANGED_HT)
1427                 rt2800_config_ht_opmode(rt2x00dev, erp);
1428 }
1429 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1430
1431 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1432                                      enum antenna ant)
1433 {
1434         u32 reg;
1435         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1436         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1437
1438         if (rt2x00_is_pci(rt2x00dev)) {
1439                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1440                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1441                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1442         } else if (rt2x00_is_usb(rt2x00dev))
1443                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1444                                    eesk_pin, 0);
1445
1446         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1447         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1448         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1449         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1450 }
1451
1452 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1453 {
1454         u8 r1;
1455         u8 r3;
1456         u16 eeprom;
1457
1458         rt2800_bbp_read(rt2x00dev, 1, &r1);
1459         rt2800_bbp_read(rt2x00dev, 3, &r3);
1460
1461         /*
1462          * Configure the TX antenna.
1463          */
1464         switch (ant->tx_chain_num) {
1465         case 1:
1466                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1467                 break;
1468         case 2:
1469                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1470                 break;
1471         case 3:
1472                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1473                 break;
1474         }
1475
1476         /*
1477          * Configure the RX antenna.
1478          */
1479         switch (ant->rx_chain_num) {
1480         case 1:
1481                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1482                     rt2x00_rt(rt2x00dev, RT3090) ||
1483                     rt2x00_rt(rt2x00dev, RT3390)) {
1484                         rt2x00_eeprom_read(rt2x00dev,
1485                                            EEPROM_NIC_CONF1, &eeprom);
1486                         if (rt2x00_get_field16(eeprom,
1487                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1488                                 rt2800_set_ant_diversity(rt2x00dev,
1489                                                 rt2x00dev->default_ant.rx);
1490                 }
1491                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1492                 break;
1493         case 2:
1494                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1495                 break;
1496         case 3:
1497                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1498                 break;
1499         }
1500
1501         rt2800_bbp_write(rt2x00dev, 3, r3);
1502         rt2800_bbp_write(rt2x00dev, 1, r1);
1503 }
1504 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1505
1506 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1507                                    struct rt2x00lib_conf *libconf)
1508 {
1509         u16 eeprom;
1510         short lna_gain;
1511
1512         if (libconf->rf.channel <= 14) {
1513                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1514                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1515         } else if (libconf->rf.channel <= 64) {
1516                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1517                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1518         } else if (libconf->rf.channel <= 128) {
1519                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1520                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1521         } else {
1522                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1523                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1524         }
1525
1526         rt2x00dev->lna_gain = lna_gain;
1527 }
1528
1529 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1530                                          struct ieee80211_conf *conf,
1531                                          struct rf_channel *rf,
1532                                          struct channel_info *info)
1533 {
1534         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1535
1536         if (rt2x00dev->default_ant.tx_chain_num == 1)
1537                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1538
1539         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1540                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1541                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1542         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1543                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1544
1545         if (rf->channel > 14) {
1546                 /*
1547                  * When TX power is below 0, we should increase it by 7 to
1548                  * make it a positive value (Minumum value is -7).
1549                  * However this means that values between 0 and 7 have
1550                  * double meaning, and we should set a 7DBm boost flag.
1551                  */
1552                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1553                                    (info->default_power1 >= 0));
1554
1555                 if (info->default_power1 < 0)
1556                         info->default_power1 += 7;
1557
1558                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1559
1560                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1561                                    (info->default_power2 >= 0));
1562
1563                 if (info->default_power2 < 0)
1564                         info->default_power2 += 7;
1565
1566                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1567         } else {
1568                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1569                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1570         }
1571
1572         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1573
1574         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1575         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1576         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1577         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1578
1579         udelay(200);
1580
1581         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1582         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1583         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1584         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1585
1586         udelay(200);
1587
1588         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1589         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1590         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1591         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1592 }
1593
1594 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1595                                          struct ieee80211_conf *conf,
1596                                          struct rf_channel *rf,
1597                                          struct channel_info *info)
1598 {
1599         u8 rfcsr;
1600
1601         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1602         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1603
1604         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1605         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1606         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1607
1608         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1609         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1610         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1611
1612         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1613         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1614         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1615
1616         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1617         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1618         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1619
1620         rt2800_rfcsr_write(rt2x00dev, 24,
1621                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1622
1623         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1624         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1625         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1626 }
1627
1628
1629 #define RT5390_POWER_BOUND     0x27
1630 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1631
1632 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1633                                          struct ieee80211_conf *conf,
1634                                          struct rf_channel *rf,
1635                                          struct channel_info *info)
1636 {
1637         u8 rfcsr;
1638         u16 eeprom;
1639
1640         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1641         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1642         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1643         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1644         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1645
1646         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1647         if (info->default_power1 > RT5390_POWER_BOUND)
1648                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1649         else
1650                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1651         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1652
1653         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1654         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1655         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1656         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1657         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1658         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1659
1660         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1661         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1662                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1663                                   RT5390_FREQ_OFFSET_BOUND);
1664         else
1665                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1666         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1667
1668         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1669         if (rf->channel <= 14) {
1670                 int idx = rf->channel-1;
1671
1672                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
1673                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1674                                 /* r55/r59 value array of channel 1~14 */
1675                                 static const char r55_bt_rev[] = {0x83, 0x83,
1676                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1677                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1678                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1679                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1680                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1681
1682                                 rt2800_rfcsr_write(rt2x00dev, 55,
1683                                                    r55_bt_rev[idx]);
1684                                 rt2800_rfcsr_write(rt2x00dev, 59,
1685                                                    r59_bt_rev[idx]);
1686                         } else {
1687                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1688                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1689                                         0x88, 0x88, 0x86, 0x85, 0x84};
1690
1691                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1692                         }
1693                 } else {
1694                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1695                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1696                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1697                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1698                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1699                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1700                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1701
1702                                 rt2800_rfcsr_write(rt2x00dev, 55,
1703                                                    r55_nonbt_rev[idx]);
1704                                 rt2800_rfcsr_write(rt2x00dev, 59,
1705                                                    r59_nonbt_rev[idx]);
1706                         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1707                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1708                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1709                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1710
1711                                 rt2800_rfcsr_write(rt2x00dev, 59,
1712                                                    r59_non_bt[idx]);
1713                         }
1714                 }
1715         }
1716
1717         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1718         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1719         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1720         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1721
1722         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1723         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1724         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1725 }
1726
1727 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1728                                   struct ieee80211_conf *conf,
1729                                   struct rf_channel *rf,
1730                                   struct channel_info *info)
1731 {
1732         u32 reg;
1733         unsigned int tx_pin;
1734         u8 bbp;
1735
1736         if (rf->channel <= 14) {
1737                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1738                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1739         } else {
1740                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1741                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1742         }
1743
1744         if (rt2x00_rf(rt2x00dev, RF2020) ||
1745             rt2x00_rf(rt2x00dev, RF3020) ||
1746             rt2x00_rf(rt2x00dev, RF3021) ||
1747             rt2x00_rf(rt2x00dev, RF3022) ||
1748             rt2x00_rf(rt2x00dev, RF3052) ||
1749             rt2x00_rf(rt2x00dev, RF3320))
1750                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1751         else if (rt2x00_rf(rt2x00dev, RF5390))
1752                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1753         else
1754                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1755
1756         /*
1757          * Change BBP settings
1758          */
1759         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1760         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1761         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1762         rt2800_bbp_write(rt2x00dev, 86, 0);
1763
1764         if (rf->channel <= 14) {
1765                 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1766                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
1767                                      &rt2x00dev->cap_flags)) {
1768                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1769                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1770                         } else {
1771                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1772                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1773                         }
1774                 }
1775         } else {
1776                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1777
1778                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
1779                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1780                 else
1781                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1782         }
1783
1784         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1785         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1786         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1787         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1788         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1789
1790         tx_pin = 0;
1791
1792         /* Turn on unused PA or LNA when not using 1T or 1R */
1793         if (rt2x00dev->default_ant.tx_chain_num == 2) {
1794                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1795                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1796         }
1797
1798         /* Turn on unused PA or LNA when not using 1T or 1R */
1799         if (rt2x00dev->default_ant.rx_chain_num == 2) {
1800                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1801                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1802         }
1803
1804         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1805         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1806         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1807         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1808         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1809         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1810
1811         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1812
1813         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1814         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1815         rt2800_bbp_write(rt2x00dev, 4, bbp);
1816
1817         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1818         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1819         rt2800_bbp_write(rt2x00dev, 3, bbp);
1820
1821         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1822                 if (conf_is_ht40(conf)) {
1823                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1824                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1825                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1826                 } else {
1827                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1828                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1829                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1830                 }
1831         }
1832
1833         msleep(1);
1834
1835         /*
1836          * Clear channel statistic counters
1837          */
1838         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1839         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1840         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1841 }
1842
1843 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
1844 {
1845         u8 tssi_bounds[9];
1846         u8 current_tssi;
1847         u16 eeprom;
1848         u8 step;
1849         int i;
1850
1851         /*
1852          * Read TSSI boundaries for temperature compensation from
1853          * the EEPROM.
1854          *
1855          * Array idx               0    1    2    3    4    5    6    7    8
1856          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
1857          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
1858          */
1859         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1860                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
1861                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1862                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
1863                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1864                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
1865
1866                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
1867                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1868                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
1869                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1870                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
1871
1872                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
1873                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1874                                         EEPROM_TSSI_BOUND_BG3_REF);
1875                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1876                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
1877
1878                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
1879                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1880                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
1881                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1882                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
1883
1884                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
1885                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1886                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
1887
1888                 step = rt2x00_get_field16(eeprom,
1889                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
1890         } else {
1891                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
1892                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1893                                         EEPROM_TSSI_BOUND_A1_MINUS4);
1894                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1895                                         EEPROM_TSSI_BOUND_A1_MINUS3);
1896
1897                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
1898                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1899                                         EEPROM_TSSI_BOUND_A2_MINUS2);
1900                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1901                                         EEPROM_TSSI_BOUND_A2_MINUS1);
1902
1903                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
1904                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1905                                         EEPROM_TSSI_BOUND_A3_REF);
1906                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1907                                         EEPROM_TSSI_BOUND_A3_PLUS1);
1908
1909                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
1910                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1911                                         EEPROM_TSSI_BOUND_A4_PLUS2);
1912                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1913                                         EEPROM_TSSI_BOUND_A4_PLUS3);
1914
1915                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
1916                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1917                                         EEPROM_TSSI_BOUND_A5_PLUS4);
1918
1919                 step = rt2x00_get_field16(eeprom,
1920                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
1921         }
1922
1923         /*
1924          * Check if temperature compensation is supported.
1925          */
1926         if (tssi_bounds[4] == 0xff)
1927                 return 0;
1928
1929         /*
1930          * Read current TSSI (BBP 49).
1931          */
1932         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
1933
1934         /*
1935          * Compare TSSI value (BBP49) with the compensation boundaries
1936          * from the EEPROM and increase or decrease tx power.
1937          */
1938         for (i = 0; i <= 3; i++) {
1939                 if (current_tssi > tssi_bounds[i])
1940                         break;
1941         }
1942
1943         if (i == 4) {
1944                 for (i = 8; i >= 5; i--) {
1945                         if (current_tssi < tssi_bounds[i])
1946                                 break;
1947                 }
1948         }
1949
1950         return (i - 4) * step;
1951 }
1952
1953 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
1954                                       enum ieee80211_band band)
1955 {
1956         u16 eeprom;
1957         u8 comp_en;
1958         u8 comp_type;
1959         int comp_value = 0;
1960
1961         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1962
1963         /*
1964          * HT40 compensation not required.
1965          */
1966         if (eeprom == 0xffff ||
1967             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1968                 return 0;
1969
1970         if (band == IEEE80211_BAND_2GHZ) {
1971                 comp_en = rt2x00_get_field16(eeprom,
1972                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
1973                 if (comp_en) {
1974                         comp_type = rt2x00_get_field16(eeprom,
1975                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
1976                         comp_value = rt2x00_get_field16(eeprom,
1977                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
1978                         if (!comp_type)
1979                                 comp_value = -comp_value;
1980                 }
1981         } else {
1982                 comp_en = rt2x00_get_field16(eeprom,
1983                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
1984                 if (comp_en) {
1985                         comp_type = rt2x00_get_field16(eeprom,
1986                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
1987                         comp_value = rt2x00_get_field16(eeprom,
1988                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
1989                         if (!comp_type)
1990                                 comp_value = -comp_value;
1991                 }
1992         }
1993
1994         return comp_value;
1995 }
1996
1997 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
1998                                    enum ieee80211_band band, int power_level,
1999                                    u8 txpower, int delta)
2000 {
2001         u32 reg;
2002         u16 eeprom;
2003         u8 criterion;
2004         u8 eirp_txpower;
2005         u8 eirp_txpower_criterion;
2006         u8 reg_limit;
2007
2008         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2009                 return txpower;
2010
2011         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2012                 /*
2013                  * Check if eirp txpower exceed txpower_limit.
2014                  * We use OFDM 6M as criterion and its eirp txpower
2015                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2016                  * .11b data rate need add additional 4dbm
2017                  * when calculating eirp txpower.
2018                  */
2019                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2020                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2021
2022                 rt2x00_eeprom_read(rt2x00dev,
2023                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2024
2025                 if (band == IEEE80211_BAND_2GHZ)
2026                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2027                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2028                 else
2029                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2030                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2031
2032                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2033                                (is_rate_b ? 4 : 0) + delta;
2034
2035                 reg_limit = (eirp_txpower > power_level) ?
2036                                         (eirp_txpower - power_level) : 0;
2037         } else
2038                 reg_limit = 0;
2039
2040         return txpower + delta - reg_limit;
2041 }
2042
2043 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2044                                   enum ieee80211_band band,
2045                                   int power_level)
2046 {
2047         u8 txpower;
2048         u16 eeprom;
2049         int i, is_rate_b;
2050         u32 reg;
2051         u8 r1;
2052         u32 offset;
2053         int delta;
2054
2055         /*
2056          * Calculate HT40 compensation delta
2057          */
2058         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2059
2060         /*
2061          * calculate temperature compensation delta
2062          */
2063         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2064
2065         /*
2066          * set to normal bbp tx power control mode: +/- 0dBm
2067          */
2068         rt2800_bbp_read(rt2x00dev, 1, &r1);
2069         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2070         rt2800_bbp_write(rt2x00dev, 1, r1);
2071         offset = TX_PWR_CFG_0;
2072
2073         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2074                 /* just to be safe */
2075                 if (offset > TX_PWR_CFG_4)
2076                         break;
2077
2078                 rt2800_register_read(rt2x00dev, offset, &reg);
2079
2080                 /* read the next four txpower values */
2081                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2082                                    &eeprom);
2083
2084                 is_rate_b = i ? 0 : 1;
2085                 /*
2086                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2087                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2088                  * TX_PWR_CFG_4: unknown
2089                  */
2090                 txpower = rt2x00_get_field16(eeprom,
2091                                              EEPROM_TXPOWER_BYRATE_RATE0);
2092                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2093                                              power_level, txpower, delta);
2094                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2095
2096                 /*
2097                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2098                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2099                  * TX_PWR_CFG_4: unknown
2100                  */
2101                 txpower = rt2x00_get_field16(eeprom,
2102                                              EEPROM_TXPOWER_BYRATE_RATE1);
2103                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2104                                              power_level, txpower, delta);
2105                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2106
2107                 /*
2108                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2109                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2110                  * TX_PWR_CFG_4: unknown
2111                  */
2112                 txpower = rt2x00_get_field16(eeprom,
2113                                              EEPROM_TXPOWER_BYRATE_RATE2);
2114                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2115                                              power_level, txpower, delta);
2116                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2117
2118                 /*
2119                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2120                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2121                  * TX_PWR_CFG_4: unknown
2122                  */
2123                 txpower = rt2x00_get_field16(eeprom,
2124                                              EEPROM_TXPOWER_BYRATE_RATE3);
2125                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2126                                              power_level, txpower, delta);
2127                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2128
2129                 /* read the next four txpower values */
2130                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2131                                    &eeprom);
2132
2133                 is_rate_b = 0;
2134                 /*
2135                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2136                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2137                  * TX_PWR_CFG_4: unknown
2138                  */
2139                 txpower = rt2x00_get_field16(eeprom,
2140                                              EEPROM_TXPOWER_BYRATE_RATE0);
2141                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2142                                              power_level, txpower, delta);
2143                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2144
2145                 /*
2146                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2147                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2148                  * TX_PWR_CFG_4: unknown
2149                  */
2150                 txpower = rt2x00_get_field16(eeprom,
2151                                              EEPROM_TXPOWER_BYRATE_RATE1);
2152                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2153                                              power_level, txpower, delta);
2154                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2155
2156                 /*
2157                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2158                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2159                  * TX_PWR_CFG_4: unknown
2160                  */
2161                 txpower = rt2x00_get_field16(eeprom,
2162                                              EEPROM_TXPOWER_BYRATE_RATE2);
2163                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2164                                              power_level, txpower, delta);
2165                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2166
2167                 /*
2168                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2169                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2170                  * TX_PWR_CFG_4: unknown
2171                  */
2172                 txpower = rt2x00_get_field16(eeprom,
2173                                              EEPROM_TXPOWER_BYRATE_RATE3);
2174                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2175                                              power_level, txpower, delta);
2176                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2177
2178                 rt2800_register_write(rt2x00dev, offset, reg);
2179
2180                 /* next TX_PWR_CFG register */
2181                 offset += 4;
2182         }
2183 }
2184
2185 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2186 {
2187         rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2188                               rt2x00dev->tx_power);
2189 }
2190 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2191
2192 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2193                                       struct rt2x00lib_conf *libconf)
2194 {
2195         u32 reg;
2196
2197         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2198         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2199                            libconf->conf->short_frame_max_tx_count);
2200         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2201                            libconf->conf->long_frame_max_tx_count);
2202         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2203 }
2204
2205 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2206                              struct rt2x00lib_conf *libconf)
2207 {
2208         enum dev_state state =
2209             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2210                 STATE_SLEEP : STATE_AWAKE;
2211         u32 reg;
2212
2213         if (state == STATE_SLEEP) {
2214                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2215
2216                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2217                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2218                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2219                                    libconf->conf->listen_interval - 1);
2220                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2221                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2222
2223                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2224         } else {
2225                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2226                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2227                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2228                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2229                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2230
2231                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2232         }
2233 }
2234
2235 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2236                    struct rt2x00lib_conf *libconf,
2237                    const unsigned int flags)
2238 {
2239         /* Always recalculate LNA gain before changing configuration */
2240         rt2800_config_lna_gain(rt2x00dev, libconf);
2241
2242         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2243                 rt2800_config_channel(rt2x00dev, libconf->conf,
2244                                       &libconf->rf, &libconf->channel);
2245                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2246                                       libconf->conf->power_level);
2247         }
2248         if (flags & IEEE80211_CONF_CHANGE_POWER)
2249                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2250                                       libconf->conf->power_level);
2251         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2252                 rt2800_config_retry_limit(rt2x00dev, libconf);
2253         if (flags & IEEE80211_CONF_CHANGE_PS)
2254                 rt2800_config_ps(rt2x00dev, libconf);
2255 }
2256 EXPORT_SYMBOL_GPL(rt2800_config);
2257
2258 /*
2259  * Link tuning
2260  */
2261 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2262 {
2263         u32 reg;
2264
2265         /*
2266          * Update FCS error count from register.
2267          */
2268         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2269         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2270 }
2271 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2272
2273 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2274 {
2275         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2276                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2277                     rt2x00_rt(rt2x00dev, RT3071) ||
2278                     rt2x00_rt(rt2x00dev, RT3090) ||
2279                     rt2x00_rt(rt2x00dev, RT3390) ||
2280                     rt2x00_rt(rt2x00dev, RT5390))
2281                         return 0x1c + (2 * rt2x00dev->lna_gain);
2282                 else
2283                         return 0x2e + rt2x00dev->lna_gain;
2284         }
2285
2286         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2287                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2288         else
2289                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2290 }
2291
2292 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2293                                   struct link_qual *qual, u8 vgc_level)
2294 {
2295         if (qual->vgc_level != vgc_level) {
2296                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2297                 qual->vgc_level = vgc_level;
2298                 qual->vgc_level_reg = vgc_level;
2299         }
2300 }
2301
2302 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2303 {
2304         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2305 }
2306 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2307
2308 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2309                        const u32 count)
2310 {
2311         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2312                 return;
2313
2314         /*
2315          * When RSSI is better then -80 increase VGC level with 0x10
2316          */
2317         rt2800_set_vgc(rt2x00dev, qual,
2318                        rt2800_get_default_vgc(rt2x00dev) +
2319                        ((qual->rssi > -80) * 0x10));
2320 }
2321 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2322
2323 /*
2324  * Initialization functions.
2325  */
2326 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2327 {
2328         u32 reg;
2329         u16 eeprom;
2330         unsigned int i;
2331         int ret;
2332
2333         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2334         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2335         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2336         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2337         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2338         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2339         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2340
2341         ret = rt2800_drv_init_registers(rt2x00dev);
2342         if (ret)
2343                 return ret;
2344
2345         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2346         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2347         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2348         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2349         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2350         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2351
2352         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2353         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2354         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2355         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2356         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2357         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2358
2359         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2360         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2361
2362         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2363
2364         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2365         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2366         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2367         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2368         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2369         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2370         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2371         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2372
2373         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2374
2375         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2376         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2377         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2378         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2379
2380         if (rt2x00_rt(rt2x00dev, RT3071) ||
2381             rt2x00_rt(rt2x00dev, RT3090) ||
2382             rt2x00_rt(rt2x00dev, RT3390)) {
2383                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2384                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2385                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2386                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2387                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2388                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2389                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2390                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2391                                                       0x0000002c);
2392                         else
2393                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2394                                                       0x0000000f);
2395                 } else {
2396                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2397                 }
2398         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2399                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2400
2401                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2402                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2403                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2404                 } else {
2405                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2406                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2407                 }
2408         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2409                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2410                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2411                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
2412         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2413                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2414                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2415                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2416         } else {
2417                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2418                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2419         }
2420
2421         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2422         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2423         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2424         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2425         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2426         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2427         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2428         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2429         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2430         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2431
2432         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2433         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2434         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2435         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2436         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2437
2438         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2439         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2440         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2441             rt2x00_rt(rt2x00dev, RT2883) ||
2442             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2443                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2444         else
2445                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2446         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2447         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2448         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2449
2450         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2451         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2452         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2453         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2454         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2455         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2456         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2457         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2458         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2459
2460         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2461
2462         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2463         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2464         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2465         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2466         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2467         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2468         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2469         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2470
2471         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2472         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2473         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2474         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2475         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2476         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2477         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2478         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2479         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2480
2481         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2482         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2483         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2484         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2485         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2486         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2487         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2488         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2489         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2490         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2491         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2492         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2493
2494         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2495         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2496         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2497         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2498         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2499         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2500         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2501         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2502         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2503         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2504         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2505         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2506
2507         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2508         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2509         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2510         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2511         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2512         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2513         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2514         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2515         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2516         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2517         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2518         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2519
2520         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2521         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2522         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2523         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2524         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2525         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2526         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2527         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2528         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2529         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2530         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2531         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2532
2533         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2534         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2535         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2536         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2537         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2538         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2539         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2540         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2541         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2542         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2543         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2544         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2545
2546         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2547         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2548         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2549         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2550         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2551         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2552         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2553         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2554         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2555         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2556         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2557         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2558
2559         if (rt2x00_is_usb(rt2x00dev)) {
2560                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2561
2562                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2563                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2564                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2565                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2566                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2567                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2568                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2569                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2570                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2571                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2572                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2573         }
2574
2575         /*
2576          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2577          * although it is reserved.
2578          */
2579         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2580         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2581         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2582         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2583         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2584         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2585         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2586         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2587         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2588         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2589         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2590         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2591
2592         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2593
2594         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2595         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2596         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2597                            IEEE80211_MAX_RTS_THRESHOLD);
2598         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2599         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2600
2601         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2602
2603         /*
2604          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2605          * time should be set to 16. However, the original Ralink driver uses
2606          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2607          * connection problems with 11g + CTS protection. Hence, use the same
2608          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2609          */
2610         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2611         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2612         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2613         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2614         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2615         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2616         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2617
2618         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2619
2620         /*
2621          * ASIC will keep garbage value after boot, clear encryption keys.
2622          */
2623         for (i = 0; i < 4; i++)
2624                 rt2800_register_write(rt2x00dev,
2625                                          SHARED_KEY_MODE_ENTRY(i), 0);
2626
2627         for (i = 0; i < 256; i++) {
2628                 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2629                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2630                                               wcid, sizeof(wcid));
2631
2632                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0);
2633                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2634         }
2635
2636         /*
2637          * Clear all beacons
2638          */
2639         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2640         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2641         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2642         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2643         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2644         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2645         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2646         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2647
2648         if (rt2x00_is_usb(rt2x00dev)) {
2649                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2650                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2651                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2652         } else if (rt2x00_is_pcie(rt2x00dev)) {
2653                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2654                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2655                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2656         }
2657
2658         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2659         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2660         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2661         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2662         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2663         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2664         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2665         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2666         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2667         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2668
2669         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2670         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2671         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2672         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2673         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2674         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2675         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2676         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2677         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2678         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2679
2680         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2681         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2682         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2683         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2684         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2685         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2686         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2687         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2688         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2689         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2690
2691         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2692         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2693         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2694         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2695         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2696         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2697
2698         /*
2699          * Do not force the BA window size, we use the TXWI to set it
2700          */
2701         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2702         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2703         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2704         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2705
2706         /*
2707          * We must clear the error counters.
2708          * These registers are cleared on read,
2709          * so we may pass a useless variable to store the value.
2710          */
2711         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2712         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2713         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2714         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2715         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2716         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2717
2718         /*
2719          * Setup leadtime for pre tbtt interrupt to 6ms
2720          */
2721         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2722         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2723         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2724
2725         /*
2726          * Set up channel statistics timer
2727          */
2728         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2729         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2730         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2731         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2732         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2733         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2734         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2735
2736         return 0;
2737 }
2738
2739 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2740 {
2741         unsigned int i;
2742         u32 reg;
2743
2744         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2745                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2746                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2747                         return 0;
2748
2749                 udelay(REGISTER_BUSY_DELAY);
2750         }
2751
2752         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2753         return -EACCES;
2754 }
2755
2756 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2757 {
2758         unsigned int i;
2759         u8 value;
2760
2761         /*
2762          * BBP was enabled after firmware was loaded,
2763          * but we need to reactivate it now.
2764          */
2765         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2766         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2767         msleep(1);
2768
2769         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2770                 rt2800_bbp_read(rt2x00dev, 0, &value);
2771                 if ((value != 0xff) && (value != 0x00))
2772                         return 0;
2773                 udelay(REGISTER_BUSY_DELAY);
2774         }
2775
2776         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2777         return -EACCES;
2778 }
2779
2780 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2781 {
2782         unsigned int i;
2783         u16 eeprom;
2784         u8 reg_id;
2785         u8 value;
2786
2787         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2788                      rt2800_wait_bbp_ready(rt2x00dev)))
2789                 return -EACCES;
2790
2791         if (rt2x00_rt(rt2x00dev, RT5390)) {
2792                 rt2800_bbp_read(rt2x00dev, 4, &value);
2793                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2794                 rt2800_bbp_write(rt2x00dev, 4, value);
2795         }
2796
2797         if (rt2800_is_305x_soc(rt2x00dev) ||
2798             rt2x00_rt(rt2x00dev, RT5390))
2799                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2800
2801         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2802         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2803
2804         if (rt2x00_rt(rt2x00dev, RT5390))
2805                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2806
2807         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2808                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2809                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2810         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2811                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2812                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2813                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2814                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2815                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
2816         } else {
2817                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2818                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2819         }
2820
2821         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2822
2823         if (rt2x00_rt(rt2x00dev, RT3070) ||
2824             rt2x00_rt(rt2x00dev, RT3071) ||
2825             rt2x00_rt(rt2x00dev, RT3090) ||
2826             rt2x00_rt(rt2x00dev, RT3390) ||
2827             rt2x00_rt(rt2x00dev, RT5390)) {
2828                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2829                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2830                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2831         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2832                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2833                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2834         } else {
2835                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2836         }
2837
2838         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2839         if (rt2x00_rt(rt2x00dev, RT5390))
2840                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2841         else
2842                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2843
2844         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2845                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2846         else if (rt2x00_rt(rt2x00dev, RT5390))
2847                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2848         else
2849                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2850
2851         if (rt2x00_rt(rt2x00dev, RT5390))
2852                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2853         else
2854                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2855
2856         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2857
2858         if (rt2x00_rt(rt2x00dev, RT5390))
2859                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2860         else
2861                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2862
2863         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2864             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2865             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2866             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2867             rt2x00_rt(rt2x00dev, RT5390) ||
2868             rt2800_is_305x_soc(rt2x00dev))
2869                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2870         else
2871                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2872
2873         if (rt2x00_rt(rt2x00dev, RT5390))
2874                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
2875
2876         if (rt2800_is_305x_soc(rt2x00dev))
2877                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2878         else if (rt2x00_rt(rt2x00dev, RT5390))
2879                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
2880         else
2881                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2882
2883         if (rt2x00_rt(rt2x00dev, RT5390))
2884                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2885         else
2886                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2887
2888         if (rt2x00_rt(rt2x00dev, RT5390))
2889                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
2890
2891         if (rt2x00_rt(rt2x00dev, RT3071) ||
2892             rt2x00_rt(rt2x00dev, RT3090) ||
2893             rt2x00_rt(rt2x00dev, RT3390) ||
2894             rt2x00_rt(rt2x00dev, RT5390)) {
2895                 rt2800_bbp_read(rt2x00dev, 138, &value);
2896
2897                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2898                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2899                         value |= 0x20;
2900                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2901                         value &= ~0x02;
2902
2903                 rt2800_bbp_write(rt2x00dev, 138, value);
2904         }
2905
2906         if (rt2x00_rt(rt2x00dev, RT5390)) {
2907                 int ant, div_mode;
2908
2909                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2910                 div_mode = rt2x00_get_field16(eeprom,
2911                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
2912                 ant = (div_mode == 3) ? 1 : 0;
2913
2914                 /* check if this is a Bluetooth combo card */
2915                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2916                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
2917                         u32 reg;
2918
2919                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2920                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2921                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2922                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2923                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2924                         if (ant == 0)
2925                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2926                         else if (ant == 1)
2927                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2928                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2929                 }
2930
2931                 rt2800_bbp_read(rt2x00dev, 152, &value);
2932                 if (ant == 0)
2933                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2934                 else
2935                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2936                 rt2800_bbp_write(rt2x00dev, 152, value);
2937
2938                 /* Init frequency calibration */
2939                 rt2800_bbp_write(rt2x00dev, 142, 1);
2940                 rt2800_bbp_write(rt2x00dev, 143, 57);
2941         }
2942
2943         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2944                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2945
2946                 if (eeprom != 0xffff && eeprom != 0x0000) {
2947                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2948                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2949                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2950                 }
2951         }
2952
2953         return 0;
2954 }
2955
2956 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2957                                 bool bw40, u8 rfcsr24, u8 filter_target)
2958 {
2959         unsigned int i;
2960         u8 bbp;
2961         u8 rfcsr;
2962         u8 passband;
2963         u8 stopband;
2964         u8 overtuned = 0;
2965
2966         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2967
2968         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2969         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2970         rt2800_bbp_write(rt2x00dev, 4, bbp);
2971
2972         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2973         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2974         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2975
2976         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2977         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2978         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2979
2980         /*
2981          * Set power & frequency of passband test tone
2982          */
2983         rt2800_bbp_write(rt2x00dev, 24, 0);
2984
2985         for (i = 0; i < 100; i++) {
2986                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2987                 msleep(1);
2988
2989                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2990                 if (passband)
2991                         break;
2992         }
2993
2994         /*
2995          * Set power & frequency of stopband test tone
2996          */
2997         rt2800_bbp_write(rt2x00dev, 24, 0x06);
2998
2999         for (i = 0; i < 100; i++) {
3000                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3001                 msleep(1);
3002
3003                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3004
3005                 if ((passband - stopband) <= filter_target) {
3006                         rfcsr24++;
3007                         overtuned += ((passband - stopband) == filter_target);
3008                 } else
3009                         break;
3010
3011                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3012         }
3013
3014         rfcsr24 -= !!overtuned;
3015
3016         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3017         return rfcsr24;
3018 }
3019
3020 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3021 {
3022         u8 rfcsr;
3023         u8 bbp;
3024         u32 reg;
3025         u16 eeprom;
3026
3027         if (!rt2x00_rt(rt2x00dev, RT3070) &&
3028             !rt2x00_rt(rt2x00dev, RT3071) &&
3029             !rt2x00_rt(rt2x00dev, RT3090) &&
3030             !rt2x00_rt(rt2x00dev, RT3390) &&
3031             !rt2x00_rt(rt2x00dev, RT5390) &&
3032             !rt2800_is_305x_soc(rt2x00dev))
3033                 return 0;
3034
3035         /*
3036          * Init RF calibration.
3037          */
3038         if (rt2x00_rt(rt2x00dev, RT5390)) {
3039                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3040                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3041                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3042                 msleep(1);
3043                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3044                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3045         } else {
3046                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3047                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3048                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3049                 msleep(1);
3050                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3051                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3052         }
3053
3054         if (rt2x00_rt(rt2x00dev, RT3070) ||
3055             rt2x00_rt(rt2x00dev, RT3071) ||
3056             rt2x00_rt(rt2x00dev, RT3090)) {
3057                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3058                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3059                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3060                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3061                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3062                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3063                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3064                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3065                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3066                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3067                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3068                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3069                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3070                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3071                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3072                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3073                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3074                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3075                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3076         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3077                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3078                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3079                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3080                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3081                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3082                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3083                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3084                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3085                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3086                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3087                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3088                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3089                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3090                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3091                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3092                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3093                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3094                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3095                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3096                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3097                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3098                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3099                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3100                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3101                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3102                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3103                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3104                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3105                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3106                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3107                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3108                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3109         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3110                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3111                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3112                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3113                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3114                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3115                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3116                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3117                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3118                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3119                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3120                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3121                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3122                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3123                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3124                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3125                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3126                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3127                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3128                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3129                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3130                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3131                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3132                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3133                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3134                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3135                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3136                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3137                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3138                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3139                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3140                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3141                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3142                 return 0;
3143         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3144                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3145                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3146                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3147                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3148                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3149                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3150                 else
3151                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3152                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3153                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3154                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3155                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3156                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3157                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3158                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3159                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3160                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3161                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3162
3163                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3164                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3165                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3166                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3167                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3168                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3169                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3170                 else
3171                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3172                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3173                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3174                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3175                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3176
3177                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3178                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3179                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3180                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3181                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3182                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3183                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3184                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3185                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3186                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3187
3188                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3189                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3190                 else
3191                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3192                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3193                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3194                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3195                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3196                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3197                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3198                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3199                 else
3200                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3201                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3202                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3203                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3204
3205                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3206                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3207                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3208                 else
3209                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3210                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3211                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3212                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3213                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3214                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3215                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3216
3217                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3218                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3219                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3220                 else
3221                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3222                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3223                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3224         }
3225
3226         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3227                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3228                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3229                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3230                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3231         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3232                    rt2x00_rt(rt2x00dev, RT3090)) {
3233                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3234
3235                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3236                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3237                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3238
3239                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3240                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3241                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3242                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3243                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3244                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3245                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3246                         else
3247                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3248                 }
3249                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3250
3251                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3252                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3253                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3254         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3255                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3256                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3257                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3258         }
3259
3260         /*
3261          * Set RX Filter calibration for 20MHz and 40MHz
3262          */
3263         if (rt2x00_rt(rt2x00dev, RT3070)) {
3264                 rt2x00dev->calibration[0] =
3265                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3266                 rt2x00dev->calibration[1] =
3267                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3268         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3269                    rt2x00_rt(rt2x00dev, RT3090) ||
3270                    rt2x00_rt(rt2x00dev, RT3390)) {
3271                 rt2x00dev->calibration[0] =
3272                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3273                 rt2x00dev->calibration[1] =
3274                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3275         }
3276
3277         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3278                 /*
3279                  * Set back to initial state
3280                  */
3281                 rt2800_bbp_write(rt2x00dev, 24, 0);
3282
3283                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3284                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3285                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3286
3287                 /*
3288                  * Set BBP back to BW20
3289                  */
3290                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3291                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3292                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3293         }
3294
3295         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3296             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3297             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3298             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3299                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3300
3301         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3302         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3303         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3304
3305         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3306                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3307                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3308                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3309                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3310                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3311                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3312                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3313                                       &rt2x00dev->cap_flags))
3314                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3315                 }
3316                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3317                 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3318                         rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3319                                         rt2x00_get_field16(eeprom,
3320                                                 EEPROM_TXMIXER_GAIN_BG_VAL));
3321                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3322         }
3323
3324         if (rt2x00_rt(rt2x00dev, RT3090)) {
3325                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3326
3327                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3328                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3329                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3330                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3331                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3332                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3333
3334                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3335         }
3336
3337         if (rt2x00_rt(rt2x00dev, RT3071) ||
3338             rt2x00_rt(rt2x00dev, RT3090) ||
3339             rt2x00_rt(rt2x00dev, RT3390)) {
3340                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3341                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3342                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3343                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3344                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3345                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3346                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3347
3348                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3349                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3350                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3351
3352                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3353                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3354                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3355
3356                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3357                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3358                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3359         }
3360
3361         if (rt2x00_rt(rt2x00dev, RT3070)) {
3362                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3363                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3364                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3365                 else
3366                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3367                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3368                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3369                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3370                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3371         }
3372
3373         if (rt2x00_rt(rt2x00dev, RT5390)) {
3374                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3375                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3376                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3377
3378                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3379                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3380                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3381
3382                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3383                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3384                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3385         }
3386
3387         return 0;
3388 }
3389
3390 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3391 {
3392         u32 reg;
3393         u16 word;
3394
3395         /*
3396          * Initialize all registers.
3397          */
3398         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3399                      rt2800_init_registers(rt2x00dev) ||
3400                      rt2800_init_bbp(rt2x00dev) ||
3401                      rt2800_init_rfcsr(rt2x00dev)))
3402                 return -EIO;
3403
3404         /*
3405          * Send signal to firmware during boot time.
3406          */
3407         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3408
3409         if (rt2x00_is_usb(rt2x00dev) &&
3410             (rt2x00_rt(rt2x00dev, RT3070) ||
3411              rt2x00_rt(rt2x00dev, RT3071) ||
3412              rt2x00_rt(rt2x00dev, RT3572))) {
3413                 udelay(200);
3414                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3415                 udelay(10);
3416         }
3417
3418         /*
3419          * Enable RX.
3420          */
3421         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3422         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3423         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3424         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3425
3426         udelay(50);
3427
3428         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3429         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3430         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3431         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3432         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3433         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3434
3435         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3436         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3437         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3438         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3439
3440         /*
3441          * Initialize LED control
3442          */
3443         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3444         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3445                            word & 0xff, (word >> 8) & 0xff);
3446
3447         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3448         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3449                            word & 0xff, (word >> 8) & 0xff);
3450
3451         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3452         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3453                            word & 0xff, (word >> 8) & 0xff);
3454
3455         return 0;
3456 }
3457 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3458
3459 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3460 {
3461         u32 reg;
3462
3463         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3464         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3465         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3466         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3467
3468         /* Wait for DMA, ignore error */
3469         rt2800_wait_wpdma_ready(rt2x00dev);
3470
3471         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3472         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3473         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3474         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3475 }
3476 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3477
3478 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3479 {
3480         u32 reg;
3481
3482         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3483
3484         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3485 }
3486 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3487
3488 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3489 {
3490         u32 reg;
3491
3492         mutex_lock(&rt2x00dev->csr_mutex);
3493
3494         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3495         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3496         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3497         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3498         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3499
3500         /* Wait until the EEPROM has been loaded */
3501         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3502
3503         /* Apparently the data is read from end to start */
3504         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
3505                                         (u32 *)&rt2x00dev->eeprom[i]);
3506         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
3507                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
3508         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
3509                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
3510         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
3511                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
3512
3513         mutex_unlock(&rt2x00dev->csr_mutex);
3514 }
3515
3516 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3517 {
3518         unsigned int i;
3519
3520         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3521                 rt2800_efuse_read(rt2x00dev, i);
3522 }
3523 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3524
3525 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3526 {
3527         u16 word;
3528         u8 *mac;
3529         u8 default_lna_gain;
3530
3531         /*
3532          * Start validation of the data that has been read.
3533          */
3534         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3535         if (!is_valid_ether_addr(mac)) {
3536                 random_ether_addr(mac);
3537                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3538         }
3539
3540         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3541         if (word == 0xffff) {
3542                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3543                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3544                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3545                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3546                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3547         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3548                    rt2x00_rt(rt2x00dev, RT2872)) {
3549                 /*
3550                  * There is a max of 2 RX streams for RT28x0 series
3551                  */
3552                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3553                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3554                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3555         }
3556
3557         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3558         if (word == 0xffff) {
3559                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3560                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3561                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3562                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3563                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3564                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3565                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3566                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3567                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3568                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3569                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3570                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3571                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3572                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3573                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3574                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3575                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3576         }
3577
3578         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3579         if ((word & 0x00ff) == 0x00ff) {
3580                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3581                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3582                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3583         }
3584         if ((word & 0xff00) == 0xff00) {
3585                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3586                                    LED_MODE_TXRX_ACTIVITY);
3587                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3588                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3589                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3590                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3591                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3592                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3593         }
3594
3595         /*
3596          * During the LNA validation we are going to use
3597          * lna0 as correct value. Note that EEPROM_LNA
3598          * is never validated.
3599          */
3600         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3601         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3602
3603         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3604         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3605                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3606         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3607                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3608         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3609
3610         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3611         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3612                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3613         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3614             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3615                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3616                                    default_lna_gain);
3617         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3618
3619         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3620         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3621                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3622         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3623                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3624         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3625
3626         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3627         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3628                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3629         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3630             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3631                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3632                                    default_lna_gain);
3633         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3634
3635         return 0;
3636 }
3637 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3638
3639 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3640 {
3641         u32 reg;
3642         u16 value;
3643         u16 eeprom;
3644
3645         /*
3646          * Read EEPROM word for configuration.
3647          */
3648         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3649
3650         /*
3651          * Identify RF chipset by EEPROM value
3652          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3653          * RT53xx: defined in "EEPROM_CHIP_ID" field
3654          */
3655         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3656         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3657                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3658         else
3659                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3660
3661         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3662                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3663
3664         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3665             !rt2x00_rt(rt2x00dev, RT2872) &&
3666             !rt2x00_rt(rt2x00dev, RT2883) &&
3667             !rt2x00_rt(rt2x00dev, RT3070) &&
3668             !rt2x00_rt(rt2x00dev, RT3071) &&
3669             !rt2x00_rt(rt2x00dev, RT3090) &&
3670             !rt2x00_rt(rt2x00dev, RT3390) &&
3671             !rt2x00_rt(rt2x00dev, RT3572) &&
3672             !rt2x00_rt(rt2x00dev, RT5390)) {
3673                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3674                 return -ENODEV;
3675         }
3676
3677         if (!rt2x00_rf(rt2x00dev, RF2820) &&
3678             !rt2x00_rf(rt2x00dev, RF2850) &&
3679             !rt2x00_rf(rt2x00dev, RF2720) &&
3680             !rt2x00_rf(rt2x00dev, RF2750) &&
3681             !rt2x00_rf(rt2x00dev, RF3020) &&
3682             !rt2x00_rf(rt2x00dev, RF2020) &&
3683             !rt2x00_rf(rt2x00dev, RF3021) &&
3684             !rt2x00_rf(rt2x00dev, RF3022) &&
3685             !rt2x00_rf(rt2x00dev, RF3052) &&
3686             !rt2x00_rf(rt2x00dev, RF3320) &&
3687             !rt2x00_rf(rt2x00dev, RF5390)) {
3688                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3689                 return -ENODEV;
3690         }
3691
3692         /*
3693          * Identify default antenna configuration.
3694          */
3695         rt2x00dev->default_ant.tx_chain_num =
3696             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3697         rt2x00dev->default_ant.rx_chain_num =
3698             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3699
3700         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3701
3702         if (rt2x00_rt(rt2x00dev, RT3070) ||
3703             rt2x00_rt(rt2x00dev, RT3090) ||
3704             rt2x00_rt(rt2x00dev, RT3390)) {
3705                 value = rt2x00_get_field16(eeprom,
3706                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3707                 switch (value) {
3708                 case 0:
3709                 case 1:
3710                 case 2:
3711                         rt2x00dev->default_ant.tx = ANTENNA_A;
3712                         rt2x00dev->default_ant.rx = ANTENNA_A;
3713                         break;
3714                 case 3:
3715                         rt2x00dev->default_ant.tx = ANTENNA_A;
3716                         rt2x00dev->default_ant.rx = ANTENNA_B;
3717                         break;
3718                 }
3719         } else {
3720                 rt2x00dev->default_ant.tx = ANTENNA_A;
3721                 rt2x00dev->default_ant.rx = ANTENNA_A;
3722         }
3723
3724         /*
3725          * Read frequency offset and RF programming sequence.
3726          */
3727         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3728         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3729
3730         /*
3731          * Read external LNA informations.
3732          */
3733         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3734
3735         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
3736                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
3737         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3738                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
3739
3740         /*
3741          * Detect if this device has an hardware controlled radio.
3742          */
3743         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3744                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
3745
3746         /*
3747          * Store led settings, for correct led behaviour.
3748          */
3749 #ifdef CONFIG_RT2X00_LIB_LEDS
3750         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3751         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3752         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3753
3754         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3755 #endif /* CONFIG_RT2X00_LIB_LEDS */
3756
3757         /*
3758          * Check if support EIRP tx power limit feature.
3759          */
3760         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3761
3762         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3763                                         EIRP_MAX_TX_POWER_LIMIT)
3764                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
3765
3766         return 0;
3767 }
3768 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3769
3770 /*
3771  * RF value list for rt28xx
3772  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3773  */
3774 static const struct rf_channel rf_vals[] = {
3775         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3776         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3777         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3778         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3779         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3780         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3781         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3782         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3783         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3784         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3785         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3786         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3787         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3788         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3789
3790         /* 802.11 UNI / HyperLan 2 */
3791         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3792         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3793         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3794         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3795         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3796         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3797         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3798         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3799         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3800         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3801         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3802         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3803
3804         /* 802.11 HyperLan 2 */
3805         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3806         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3807         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3808         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3809         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3810         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3811         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3812         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3813         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3814         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3815         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3816         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3817         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3818         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3819         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3820         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3821
3822         /* 802.11 UNII */
3823         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3824         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3825         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3826         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3827         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3828         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3829         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3830         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3831         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3832         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3833         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3834
3835         /* 802.11 Japan */
3836         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3837         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3838         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3839         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3840         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3841         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3842         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3843 };
3844
3845 /*
3846  * RF value list for rt3xxx
3847  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3848  */
3849 static const struct rf_channel rf_vals_3x[] = {
3850         {1,  241, 2, 2 },
3851         {2,  241, 2, 7 },
3852         {3,  242, 2, 2 },
3853         {4,  242, 2, 7 },
3854         {5,  243, 2, 2 },
3855         {6,  243, 2, 7 },
3856         {7,  244, 2, 2 },
3857         {8,  244, 2, 7 },
3858         {9,  245, 2, 2 },
3859         {10, 245, 2, 7 },
3860         {11, 246, 2, 2 },
3861         {12, 246, 2, 7 },
3862         {13, 247, 2, 2 },
3863         {14, 248, 2, 4 },
3864
3865         /* 802.11 UNI / HyperLan 2 */
3866         {36, 0x56, 0, 4},
3867         {38, 0x56, 0, 6},
3868         {40, 0x56, 0, 8},
3869         {44, 0x57, 0, 0},
3870         {46, 0x57, 0, 2},
3871         {48, 0x57, 0, 4},
3872         {52, 0x57, 0, 8},
3873         {54, 0x57, 0, 10},
3874         {56, 0x58, 0, 0},
3875         {60, 0x58, 0, 4},
3876         {62, 0x58, 0, 6},
3877         {64, 0x58, 0, 8},
3878
3879         /* 802.11 HyperLan 2 */
3880         {100, 0x5b, 0, 8},
3881         {102, 0x5b, 0, 10},
3882         {104, 0x5c, 0, 0},
3883         {108, 0x5c, 0, 4},
3884         {110, 0x5c, 0, 6},
3885         {112, 0x5c, 0, 8},
3886         {116, 0x5d, 0, 0},
3887         {118, 0x5d, 0, 2},
3888         {120, 0x5d, 0, 4},
3889         {124, 0x5d, 0, 8},
3890         {126, 0x5d, 0, 10},
3891         {128, 0x5e, 0, 0},
3892         {132, 0x5e, 0, 4},
3893         {134, 0x5e, 0, 6},
3894         {136, 0x5e, 0, 8},
3895         {140, 0x5f, 0, 0},
3896
3897         /* 802.11 UNII */
3898         {149, 0x5f, 0, 9},
3899         {151, 0x5f, 0, 11},
3900         {153, 0x60, 0, 1},
3901         {157, 0x60, 0, 5},
3902         {159, 0x60, 0, 7},
3903         {161, 0x60, 0, 9},
3904         {165, 0x61, 0, 1},
3905         {167, 0x61, 0, 3},
3906         {169, 0x61, 0, 5},
3907         {171, 0x61, 0, 7},
3908         {173, 0x61, 0, 9},
3909 };
3910
3911 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3912 {
3913         struct hw_mode_spec *spec = &rt2x00dev->spec;
3914         struct channel_info *info;
3915         char *default_power1;
3916         char *default_power2;
3917         unsigned int i;
3918         u16 eeprom;
3919
3920         /*
3921          * Disable powersaving as default on PCI devices.
3922          */
3923         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3924                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3925
3926         /*
3927          * Initialize all hw fields.
3928          */
3929         rt2x00dev->hw->flags =
3930             IEEE80211_HW_SIGNAL_DBM |
3931             IEEE80211_HW_SUPPORTS_PS |
3932             IEEE80211_HW_PS_NULLFUNC_STACK |
3933             IEEE80211_HW_AMPDU_AGGREGATION;
3934         /*
3935          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3936          * unless we are capable of sending the buffered frames out after the
3937          * DTIM transmission using rt2x00lib_beacondone. This will send out
3938          * multicast and broadcast traffic immediately instead of buffering it
3939          * infinitly and thus dropping it after some time.
3940          */
3941         if (!rt2x00_is_usb(rt2x00dev))
3942                 rt2x00dev->hw->flags |=
3943                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
3944
3945         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3946         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3947                                 rt2x00_eeprom_addr(rt2x00dev,
3948                                                    EEPROM_MAC_ADDR_0));
3949
3950         /*
3951          * As rt2800 has a global fallback table we cannot specify
3952          * more then one tx rate per frame but since the hw will
3953          * try several rates (based on the fallback table) we should
3954          * initialize max_report_rates to the maximum number of rates
3955          * we are going to try. Otherwise mac80211 will truncate our
3956          * reported tx rates and the rc algortihm will end up with
3957          * incorrect data.
3958          */
3959         rt2x00dev->hw->max_rates = 1;
3960         rt2x00dev->hw->max_report_rates = 7;
3961         rt2x00dev->hw->max_rate_tries = 1;
3962
3963         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3964
3965         /*
3966          * Initialize hw_mode information.
3967          */
3968         spec->supported_bands = SUPPORT_BAND_2GHZ;
3969         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3970
3971         if (rt2x00_rf(rt2x00dev, RF2820) ||
3972             rt2x00_rf(rt2x00dev, RF2720)) {
3973                 spec->num_channels = 14;
3974                 spec->channels = rf_vals;
3975         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3976                    rt2x00_rf(rt2x00dev, RF2750)) {
3977                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3978                 spec->num_channels = ARRAY_SIZE(rf_vals);
3979                 spec->channels = rf_vals;
3980         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3981                    rt2x00_rf(rt2x00dev, RF2020) ||
3982                    rt2x00_rf(rt2x00dev, RF3021) ||
3983                    rt2x00_rf(rt2x00dev, RF3022) ||
3984                    rt2x00_rf(rt2x00dev, RF3320) ||
3985                    rt2x00_rf(rt2x00dev, RF5390)) {
3986                 spec->num_channels = 14;
3987                 spec->channels = rf_vals_3x;
3988         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3989                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3990                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3991                 spec->channels = rf_vals_3x;
3992         }
3993
3994         /*
3995          * Initialize HT information.
3996          */
3997         if (!rt2x00_rf(rt2x00dev, RF2020))
3998                 spec->ht.ht_supported = true;
3999         else
4000                 spec->ht.ht_supported = false;
4001
4002         spec->ht.cap =
4003             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4004             IEEE80211_HT_CAP_GRN_FLD |
4005             IEEE80211_HT_CAP_SGI_20 |
4006             IEEE80211_HT_CAP_SGI_40;
4007
4008         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4009                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4010
4011         spec->ht.cap |=
4012             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4013                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4014
4015         spec->ht.ampdu_factor = 3;
4016         spec->ht.ampdu_density = 4;
4017         spec->ht.mcs.tx_params =
4018             IEEE80211_HT_MCS_TX_DEFINED |
4019             IEEE80211_HT_MCS_TX_RX_DIFF |
4020             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4021                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4022
4023         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4024         case 3:
4025                 spec->ht.mcs.rx_mask[2] = 0xff;
4026         case 2:
4027                 spec->ht.mcs.rx_mask[1] = 0xff;
4028         case 1:
4029                 spec->ht.mcs.rx_mask[0] = 0xff;
4030                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4031                 break;
4032         }
4033
4034         /*
4035          * Create channel information array
4036          */
4037         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4038         if (!info)
4039                 return -ENOMEM;
4040
4041         spec->channels_info = info;
4042
4043         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4044         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4045
4046         for (i = 0; i < 14; i++) {
4047                 info[i].default_power1 = default_power1[i];
4048                 info[i].default_power2 = default_power2[i];
4049         }
4050
4051         if (spec->num_channels > 14) {
4052                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4053                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4054
4055                 for (i = 14; i < spec->num_channels; i++) {
4056                         info[i].default_power1 = default_power1[i];
4057                         info[i].default_power2 = default_power2[i];
4058                 }
4059         }
4060
4061         return 0;
4062 }
4063 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4064
4065 /*
4066  * IEEE80211 stack callback functions.
4067  */
4068 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4069                          u16 *iv16)
4070 {
4071         struct rt2x00_dev *rt2x00dev = hw->priv;
4072         struct mac_iveiv_entry iveiv_entry;
4073         u32 offset;
4074
4075         offset = MAC_IVEIV_ENTRY(hw_key_idx);
4076         rt2800_register_multiread(rt2x00dev, offset,
4077                                       &iveiv_entry, sizeof(iveiv_entry));
4078
4079         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4080         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4081 }
4082 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4083
4084 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4085 {
4086         struct rt2x00_dev *rt2x00dev = hw->priv;
4087         u32 reg;
4088         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4089
4090         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4091         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4092         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4093
4094         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4095         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4096         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4097
4098         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4099         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4100         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4101
4102         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4103         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4104         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4105
4106         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4107         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4108         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4109
4110         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4111         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4112         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4113
4114         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4115         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4116         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4117
4118         return 0;
4119 }
4120 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4121
4122 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
4123                    const struct ieee80211_tx_queue_params *params)
4124 {
4125         struct rt2x00_dev *rt2x00dev = hw->priv;
4126         struct data_queue *queue;
4127         struct rt2x00_field32 field;
4128         int retval;
4129         u32 reg;
4130         u32 offset;
4131
4132         /*
4133          * First pass the configuration through rt2x00lib, that will
4134          * update the queue settings and validate the input. After that
4135          * we are free to update the registers based on the value
4136          * in the queue parameter.
4137          */
4138         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
4139         if (retval)
4140                 return retval;
4141
4142         /*
4143          * We only need to perform additional register initialization
4144          * for WMM queues/
4145          */
4146         if (queue_idx >= 4)
4147                 return 0;
4148
4149         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4150
4151         /* Update WMM TXOP register */
4152         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4153         field.bit_offset = (queue_idx & 1) * 16;
4154         field.bit_mask = 0xffff << field.bit_offset;
4155
4156         rt2800_register_read(rt2x00dev, offset, &reg);
4157         rt2x00_set_field32(&reg, field, queue->txop);
4158         rt2800_register_write(rt2x00dev, offset, reg);
4159
4160         /* Update WMM registers */
4161         field.bit_offset = queue_idx * 4;
4162         field.bit_mask = 0xf << field.bit_offset;
4163
4164         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4165         rt2x00_set_field32(&reg, field, queue->aifs);
4166         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4167
4168         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4169         rt2x00_set_field32(&reg, field, queue->cw_min);
4170         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4171
4172         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4173         rt2x00_set_field32(&reg, field, queue->cw_max);
4174         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4175
4176         /* Update EDCA registers */
4177         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4178
4179         rt2800_register_read(rt2x00dev, offset, &reg);
4180         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4181         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4182         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4183         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4184         rt2800_register_write(rt2x00dev, offset, reg);
4185
4186         return 0;
4187 }
4188 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4189
4190 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
4191 {
4192         struct rt2x00_dev *rt2x00dev = hw->priv;
4193         u64 tsf;
4194         u32 reg;
4195
4196         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4197         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4198         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4199         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4200
4201         return tsf;
4202 }
4203 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4204
4205 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4206                         enum ieee80211_ampdu_mlme_action action,
4207                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4208                         u8 buf_size)
4209 {
4210         int ret = 0;
4211
4212         switch (action) {
4213         case IEEE80211_AMPDU_RX_START:
4214         case IEEE80211_AMPDU_RX_STOP:
4215                 /*
4216                  * The hw itself takes care of setting up BlockAck mechanisms.
4217                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4218                  * agreement. Once that is done, the hw will BlockAck incoming
4219                  * AMPDUs without further setup.
4220                  */
4221                 break;
4222         case IEEE80211_AMPDU_TX_START:
4223                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4224                 break;
4225         case IEEE80211_AMPDU_TX_STOP:
4226                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4227                 break;
4228         case IEEE80211_AMPDU_TX_OPERATIONAL:
4229                 break;
4230         default:
4231                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4232         }
4233
4234         return ret;
4235 }
4236 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4237
4238 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4239                       struct survey_info *survey)
4240 {
4241         struct rt2x00_dev *rt2x00dev = hw->priv;
4242         struct ieee80211_conf *conf = &hw->conf;
4243         u32 idle, busy, busy_ext;
4244
4245         if (idx != 0)
4246                 return -ENOENT;
4247
4248         survey->channel = conf->channel;
4249
4250         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4251         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4252         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4253
4254         if (idle || busy) {
4255                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4256                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4257                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4258
4259                 survey->channel_time = (idle + busy) / 1000;
4260                 survey->channel_time_busy = busy / 1000;
4261                 survey->channel_time_ext_busy = busy_ext / 1000;
4262         }
4263
4264         return 0;
4265
4266 }
4267 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4268
4269 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4270 MODULE_VERSION(DRV_VERSION);
4271 MODULE_DESCRIPTION("Ralink RT2800 library");
4272 MODULE_LICENSE("GPL");