ad90c86810d777447d039555bbca8785d94a04cc
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7         Based on the original rt2800pci.c and rt2800usb.c.
8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14           <http://rt2x00.serialmonkey.com>
15
16         This program is free software; you can redistribute it and/or modify
17         it under the terms of the GNU General Public License as published by
18         the Free Software Foundation; either version 2 of the License, or
19         (at your option) any later version.
20
21         This program is distributed in the hope that it will be useful,
22         but WITHOUT ANY WARRANTY; without even the implied warranty of
23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24         GNU General Public License for more details.
25
26         You should have received a copy of the GNU General Public License
27         along with this program; if not, write to the
28         Free Software Foundation, Inc.,
29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30  */
31
32 /*
33         Module: rt2800lib
34         Abstract: rt2800 generic device routines.
35  */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47  * Register access.
48  * All access to the CSR registers will go through the methods
49  * rt2800_register_read and rt2800_register_write.
50  * BBP and RF register require indirect register access,
51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
52  * These indirect registers work with busy bits,
53  * and we will try maximal REGISTER_BUSY_COUNT times to access
54  * the register while taking a REGISTER_BUSY_DELAY us delay
55  * between each attampt. When the busy bit is still set at that time,
56  * the access attempt is considered to have failed,
57  * and we will print an error.
58  * The _lock versions must be used if you already hold the csr_mutex
59  */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68                             H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72         /* check for rt2872 on SoC */
73         if (!rt2x00_is_soc(rt2x00dev) ||
74             !rt2x00_rt(rt2x00dev, RT2872))
75                 return false;
76
77         /* we know for sure that these rf chipsets are used on rt305x boards */
78         if (rt2x00_rf(rt2x00dev, RF3020) ||
79             rt2x00_rf(rt2x00dev, RF3021) ||
80             rt2x00_rf(rt2x00dev, RF3022))
81                 return true;
82
83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84         return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88                              const unsigned int word, const u8 value)
89 {
90         u32 reg;
91
92         mutex_lock(&rt2x00dev->csr_mutex);
93
94         /*
95          * Wait until the BBP becomes available, afterwards we
96          * can safely write the new data into the register.
97          */
98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99                 reg = 0;
100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107         }
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113                             const unsigned int word, u8 *value)
114 {
115         u32 reg;
116
117         mutex_lock(&rt2x00dev->csr_mutex);
118
119         /*
120          * Wait until the BBP becomes available, afterwards we
121          * can safely write the read request into the register.
122          * After the data has been written, we wait until hardware
123          * returns the correct value, if at any time the register
124          * doesn't become available in time, reg will be 0xffffffff
125          * which means we return 0xff to the caller.
126          */
127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128                 reg = 0;
129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136                 WAIT_FOR_BBP(rt2x00dev, &reg);
137         }
138
139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141         mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145                                const unsigned int word, const u8 value)
146 {
147         u32 reg;
148
149         mutex_lock(&rt2x00dev->csr_mutex);
150
151         /*
152          * Wait until the RFCSR becomes available, afterwards we
153          * can safely write the new data into the register.
154          */
155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156                 reg = 0;
157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163         }
164
165         mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169                               const unsigned int word, u8 *value)
170 {
171         u32 reg;
172
173         mutex_lock(&rt2x00dev->csr_mutex);
174
175         /*
176          * Wait until the RFCSR becomes available, afterwards we
177          * can safely write the read request into the register.
178          * After the data has been written, we wait until hardware
179          * returns the correct value, if at any time the register
180          * doesn't become available in time, reg will be 0xffffffff
181          * which means we return 0xff to the caller.
182          */
183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184                 reg = 0;
185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192         }
193
194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196         mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200                             const unsigned int word, const u32 value)
201 {
202         u32 reg;
203
204         mutex_lock(&rt2x00dev->csr_mutex);
205
206         /*
207          * Wait until the RF becomes available, afterwards we
208          * can safely write the new data into the register.
209          */
210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211                 reg = 0;
212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218                 rt2x00_rf_write(rt2x00dev, word, value);
219         }
220
221         mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225                         const u8 command, const u8 token,
226                         const u8 arg0, const u8 arg1)
227 {
228         u32 reg;
229
230         /*
231          * SOC devices don't support MCU requests.
232          */
233         if (rt2x00_is_soc(rt2x00dev))
234                 return;
235
236         mutex_lock(&rt2x00dev->csr_mutex);
237
238         /*
239          * Wait until the MCU becomes available, afterwards we
240          * can safely write the new data into the register.
241          */
242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249                 reg = 0;
250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252         }
253
254         mutex_unlock(&rt2x00dev->csr_mutex);
255 }
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
257
258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259 {
260         unsigned int i = 0;
261         u32 reg;
262
263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265                 if (reg && reg != ~0)
266                         return 0;
267                 msleep(1);
268         }
269
270         ERROR(rt2x00dev, "Unstable hardware.\n");
271         return -EBUSY;
272 }
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276 {
277         unsigned int i;
278         u32 reg;
279
280         /*
281          * Some devices are really slow to respond here. Wait a whole second
282          * before timing out.
283          */
284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288                         return 0;
289
290                 msleep(10);
291         }
292
293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294         return -EACCES;
295 }
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299 {
300         u16 fw_crc;
301         u16 crc;
302
303         /*
304          * The last 2 bytes in the firmware array are the crc checksum itself,
305          * this means that we should never pass those 2 bytes to the crc
306          * algorithm.
307          */
308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310         /*
311          * Use the crc ccitt algorithm.
312          * This will return the same value as the legacy driver which
313          * used bit ordering reversion on the both the firmware bytes
314          * before input input as well as on the final output.
315          * Obviously using crc ccitt directly is much more efficient.
316          */
317         crc = crc_ccitt(~0, data, len - 2);
318
319         /*
320          * There is a small difference between the crc-itu-t + bitrev and
321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
322          * will be swapped, use swab16 to convert the crc to the correct
323          * value.
324          */
325         crc = swab16(crc);
326
327         return fw_crc == crc;
328 }
329
330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331                           const u8 *data, const size_t len)
332 {
333         size_t offset = 0;
334         size_t fw_len;
335         bool multiple;
336
337         /*
338          * PCI(e) & SOC devices require firmware with a length
339          * of 8kb. USB devices require firmware files with a length
340          * of 4kb. Certain USB chipsets however require different firmware,
341          * which Ralink only provides attached to the original firmware
342          * file. Thus for USB devices, firmware files have a length
343          * which is a multiple of 4kb.
344          */
345         if (rt2x00_is_usb(rt2x00dev)) {
346                 fw_len = 4096;
347                 multiple = true;
348         } else {
349                 fw_len = 8192;
350                 multiple = true;
351         }
352
353         /*
354          * Validate the firmware length
355          */
356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
357                 return FW_BAD_LENGTH;
358
359         /*
360          * Check if the chipset requires one of the upper parts
361          * of the firmware.
362          */
363         if (rt2x00_is_usb(rt2x00dev) &&
364             !rt2x00_rt(rt2x00dev, RT2860) &&
365             !rt2x00_rt(rt2x00dev, RT2872) &&
366             !rt2x00_rt(rt2x00dev, RT3070) &&
367             ((len / fw_len) == 1))
368                 return FW_BAD_VERSION;
369
370         /*
371          * 8kb firmware files must be checked as if it were
372          * 2 separate firmware files.
373          */
374         while (offset < len) {
375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376                         return FW_BAD_CRC;
377
378                 offset += fw_len;
379         }
380
381         return FW_OK;
382 }
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386                          const u8 *data, const size_t len)
387 {
388         unsigned int i;
389         u32 reg;
390
391         /*
392          * If driver doesn't wake up firmware here,
393          * rt2800_load_firmware will hang forever when interface is up again.
394          */
395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
396
397         /*
398          * Wait for stable hardware.
399          */
400         if (rt2800_wait_csr_ready(rt2x00dev))
401                 return -EBUSY;
402
403         if (rt2x00_is_pci(rt2x00dev)) {
404                 if (rt2x00_rt(rt2x00dev, RT5390)) {
405                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
406                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
407                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
408                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
409                 }
410                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
411         }
412
413         /*
414          * Disable DMA, will be reenabled later when enabling
415          * the radio.
416          */
417         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
418         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
419         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
420         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
421         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
422         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
423         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
424
425         /*
426          * Write firmware to the device.
427          */
428         rt2800_drv_write_firmware(rt2x00dev, data, len);
429
430         /*
431          * Wait for device to stabilize.
432          */
433         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
434                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
435                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
436                         break;
437                 msleep(1);
438         }
439
440         if (i == REGISTER_BUSY_COUNT) {
441                 ERROR(rt2x00dev, "PBF system register not ready.\n");
442                 return -EBUSY;
443         }
444
445         /*
446          * Initialize firmware.
447          */
448         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
449         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
450         msleep(1);
451
452         return 0;
453 }
454 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
455
456 void rt2800_write_tx_data(struct queue_entry *entry,
457                           struct txentry_desc *txdesc)
458 {
459         __le32 *txwi = rt2800_drv_get_txwi(entry);
460         u32 word;
461
462         /*
463          * Initialize TX Info descriptor
464          */
465         rt2x00_desc_read(txwi, 0, &word);
466         rt2x00_set_field32(&word, TXWI_W0_FRAG,
467                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
468         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
469                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
470         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
471         rt2x00_set_field32(&word, TXWI_W0_TS,
472                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
473         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
474                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
475         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
476         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
477         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
478         rt2x00_set_field32(&word, TXWI_W0_BW,
479                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
480         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
481                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
482         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
483         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
484         rt2x00_desc_write(txwi, 0, word);
485
486         rt2x00_desc_read(txwi, 1, &word);
487         rt2x00_set_field32(&word, TXWI_W1_ACK,
488                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
489         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
490                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
491         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
492         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
493                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
494                            txdesc->key_idx : 0xff);
495         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
496                            txdesc->length);
497         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
498         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
499         rt2x00_desc_write(txwi, 1, word);
500
501         /*
502          * Always write 0 to IV/EIV fields, hardware will insert the IV
503          * from the IVEIV register when TXD_W3_WIV is set to 0.
504          * When TXD_W3_WIV is set to 1 it will use the IV data
505          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
506          * crypto entry in the registers should be used to encrypt the frame.
507          */
508         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
509         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
510 }
511 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
512
513 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
514 {
515         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
516         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
517         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
518         u16 eeprom;
519         u8 offset0;
520         u8 offset1;
521         u8 offset2;
522
523         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
524                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
525                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
526                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
527                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
528                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
529         } else {
530                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
531                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
532                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
533                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
534                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
535         }
536
537         /*
538          * Convert the value from the descriptor into the RSSI value
539          * If the value in the descriptor is 0, it is considered invalid
540          * and the default (extremely low) rssi value is assumed
541          */
542         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
543         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
544         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
545
546         /*
547          * mac80211 only accepts a single RSSI value. Calculating the
548          * average doesn't deliver a fair answer either since -60:-60 would
549          * be considered equally good as -50:-70 while the second is the one
550          * which gives less energy...
551          */
552         rssi0 = max(rssi0, rssi1);
553         return max(rssi0, rssi2);
554 }
555
556 void rt2800_process_rxwi(struct queue_entry *entry,
557                          struct rxdone_entry_desc *rxdesc)
558 {
559         __le32 *rxwi = (__le32 *) entry->skb->data;
560         u32 word;
561
562         rt2x00_desc_read(rxwi, 0, &word);
563
564         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
565         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
566
567         rt2x00_desc_read(rxwi, 1, &word);
568
569         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
570                 rxdesc->flags |= RX_FLAG_SHORT_GI;
571
572         if (rt2x00_get_field32(word, RXWI_W1_BW))
573                 rxdesc->flags |= RX_FLAG_40MHZ;
574
575         /*
576          * Detect RX rate, always use MCS as signal type.
577          */
578         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
579         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
580         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
581
582         /*
583          * Mask of 0x8 bit to remove the short preamble flag.
584          */
585         if (rxdesc->rate_mode == RATE_MODE_CCK)
586                 rxdesc->signal &= ~0x8;
587
588         rt2x00_desc_read(rxwi, 2, &word);
589
590         /*
591          * Convert descriptor AGC value to RSSI value.
592          */
593         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
594
595         /*
596          * Remove RXWI descriptor from start of buffer.
597          */
598         skb_pull(entry->skb, RXWI_DESC_SIZE);
599 }
600 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
601
602 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
603 {
604         __le32 *txwi;
605         u32 word;
606         int wcid, ack, pid;
607         int tx_wcid, tx_ack, tx_pid;
608
609         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
610         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
611         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
612
613         /*
614          * This frames has returned with an IO error,
615          * so the status report is not intended for this
616          * frame.
617          */
618         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
619                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
620                 return false;
621         }
622
623         /*
624          * Validate if this TX status report is intended for
625          * this entry by comparing the WCID/ACK/PID fields.
626          */
627         txwi = rt2800_drv_get_txwi(entry);
628
629         rt2x00_desc_read(txwi, 1, &word);
630         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
631         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
632         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
633
634         if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
635                 WARNING(entry->queue->rt2x00dev,
636                         "TX status report missed for queue %d entry %d\n",
637                 entry->queue->qid, entry->entry_idx);
638                 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
639                 return false;
640         }
641
642         return true;
643 }
644
645 void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
646 {
647         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
648         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
649         struct txdone_entry_desc txdesc;
650         u32 word;
651         u16 mcs, real_mcs;
652         int aggr, ampdu;
653         __le32 *txwi;
654
655         /*
656          * Obtain the status about this packet.
657          */
658         txdesc.flags = 0;
659         txwi = rt2800_drv_get_txwi(entry);
660         rt2x00_desc_read(txwi, 0, &word);
661
662         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
663         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
664
665         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
666         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
667
668         /*
669          * If a frame was meant to be sent as a single non-aggregated MPDU
670          * but ended up in an aggregate the used tx rate doesn't correlate
671          * with the one specified in the TXWI as the whole aggregate is sent
672          * with the same rate.
673          *
674          * For example: two frames are sent to rt2x00, the first one sets
675          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
676          * and requests MCS15. If the hw aggregates both frames into one
677          * AMDPU the tx status for both frames will contain MCS7 although
678          * the frame was sent successfully.
679          *
680          * Hence, replace the requested rate with the real tx rate to not
681          * confuse the rate control algortihm by providing clearly wrong
682          * data.
683          */
684         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
685                 skbdesc->tx_rate_idx = real_mcs;
686                 mcs = real_mcs;
687         }
688
689         /*
690          * Ralink has a retry mechanism using a global fallback
691          * table. We setup this fallback table to try the immediate
692          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
693          * always contains the MCS used for the last transmission, be
694          * it successful or not.
695          */
696         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
697                 /*
698                  * Transmission succeeded. The number of retries is
699                  * mcs - real_mcs
700                  */
701                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
702                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
703         } else {
704                 /*
705                  * Transmission failed. The number of retries is
706                  * always 7 in this case (for a total number of 8
707                  * frames sent).
708                  */
709                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
710                 txdesc.retry = rt2x00dev->long_retry;
711         }
712
713         /*
714          * the frame was retried at least once
715          * -> hw used fallback rates
716          */
717         if (txdesc.retry)
718                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
719
720         rt2x00lib_txdone(entry, &txdesc);
721 }
722 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
723
724 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
725 {
726         struct data_queue *queue;
727         struct queue_entry *entry;
728         u32 reg;
729         u8 pid;
730         int i;
731
732         /*
733          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
734          * at most X times and also stop processing once the TX_STA_FIFO_VALID
735          * flag is not set anymore.
736          *
737          * The legacy drivers use X=TX_RING_SIZE but state in a comment
738          * that the TX_STA_FIFO stack has a size of 16. We stick to our
739          * tx ring size for now.
740          */
741         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
742                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
743                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
744                         break;
745
746                 /*
747                  * Skip this entry when it contains an invalid
748                  * queue identication number.
749                  */
750                 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
751                 if (pid >= QID_RX)
752                         continue;
753
754                 queue = rt2x00queue_get_tx_queue(rt2x00dev, pid);
755                 if (unlikely(!queue))
756                         continue;
757
758                 /*
759                  * Inside each queue, we process each entry in a chronological
760                  * order. We first check that the queue is not empty.
761                  */
762                 entry = NULL;
763                 while (!rt2x00queue_empty(queue)) {
764                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
765                         if (rt2800_txdone_entry_check(entry, reg))
766                                 break;
767                 }
768
769                 if (!entry || rt2x00queue_empty(queue))
770                         break;
771
772                 rt2800_txdone_entry(entry, reg);
773         }
774 }
775 EXPORT_SYMBOL_GPL(rt2800_txdone);
776
777 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
778 {
779         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
780         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
781         unsigned int beacon_base;
782         unsigned int padding_len;
783         u32 orig_reg, reg;
784
785         /*
786          * Disable beaconing while we are reloading the beacon data,
787          * otherwise we might be sending out invalid data.
788          */
789         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
790         orig_reg = reg;
791         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
792         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
793
794         /*
795          * Add space for the TXWI in front of the skb.
796          */
797         skb_push(entry->skb, TXWI_DESC_SIZE);
798         memset(entry->skb, 0, TXWI_DESC_SIZE);
799
800         /*
801          * Register descriptor details in skb frame descriptor.
802          */
803         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
804         skbdesc->desc = entry->skb->data;
805         skbdesc->desc_len = TXWI_DESC_SIZE;
806
807         /*
808          * Add the TXWI for the beacon to the skb.
809          */
810         rt2800_write_tx_data(entry, txdesc);
811
812         /*
813          * Dump beacon to userspace through debugfs.
814          */
815         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
816
817         /*
818          * Write entire beacon with TXWI and padding to register.
819          */
820         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
821         if (padding_len && skb_pad(entry->skb, padding_len)) {
822                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
823                 /* skb freed by skb_pad() on failure */
824                 entry->skb = NULL;
825                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
826                 return;
827         }
828
829         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
830         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
831                                    entry->skb->len + padding_len);
832
833         /*
834          * Enable beaconing again.
835          */
836         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
837         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
838
839         /*
840          * Clean up beacon skb.
841          */
842         dev_kfree_skb_any(entry->skb);
843         entry->skb = NULL;
844 }
845 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
846
847 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
848                                                 unsigned int beacon_base)
849 {
850         int i;
851
852         /*
853          * For the Beacon base registers we only need to clear
854          * the whole TXWI which (when set to 0) will invalidate
855          * the entire beacon.
856          */
857         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
858                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
859 }
860
861 void rt2800_clear_beacon(struct queue_entry *entry)
862 {
863         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
864         u32 reg;
865
866         /*
867          * Disable beaconing while we are reloading the beacon data,
868          * otherwise we might be sending out invalid data.
869          */
870         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
871         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
872         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
873
874         /*
875          * Clear beacon.
876          */
877         rt2800_clear_beacon_register(rt2x00dev,
878                                      HW_BEACON_OFFSET(entry->entry_idx));
879
880         /*
881          * Enabled beaconing again.
882          */
883         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
884         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
885 }
886 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
887
888 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
889 const struct rt2x00debug rt2800_rt2x00debug = {
890         .owner  = THIS_MODULE,
891         .csr    = {
892                 .read           = rt2800_register_read,
893                 .write          = rt2800_register_write,
894                 .flags          = RT2X00DEBUGFS_OFFSET,
895                 .word_base      = CSR_REG_BASE,
896                 .word_size      = sizeof(u32),
897                 .word_count     = CSR_REG_SIZE / sizeof(u32),
898         },
899         .eeprom = {
900                 .read           = rt2x00_eeprom_read,
901                 .write          = rt2x00_eeprom_write,
902                 .word_base      = EEPROM_BASE,
903                 .word_size      = sizeof(u16),
904                 .word_count     = EEPROM_SIZE / sizeof(u16),
905         },
906         .bbp    = {
907                 .read           = rt2800_bbp_read,
908                 .write          = rt2800_bbp_write,
909                 .word_base      = BBP_BASE,
910                 .word_size      = sizeof(u8),
911                 .word_count     = BBP_SIZE / sizeof(u8),
912         },
913         .rf     = {
914                 .read           = rt2x00_rf_read,
915                 .write          = rt2800_rf_write,
916                 .word_base      = RF_BASE,
917                 .word_size      = sizeof(u32),
918                 .word_count     = RF_SIZE / sizeof(u32),
919         },
920 };
921 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
922 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
923
924 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
925 {
926         u32 reg;
927
928         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
929         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
930 }
931 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
932
933 #ifdef CONFIG_RT2X00_LIB_LEDS
934 static void rt2800_brightness_set(struct led_classdev *led_cdev,
935                                   enum led_brightness brightness)
936 {
937         struct rt2x00_led *led =
938             container_of(led_cdev, struct rt2x00_led, led_dev);
939         unsigned int enabled = brightness != LED_OFF;
940         unsigned int bg_mode =
941             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
942         unsigned int polarity =
943                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
944                                    EEPROM_FREQ_LED_POLARITY);
945         unsigned int ledmode =
946                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
947                                    EEPROM_FREQ_LED_MODE);
948
949         if (led->type == LED_TYPE_RADIO) {
950                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
951                                       enabled ? 0x20 : 0);
952         } else if (led->type == LED_TYPE_ASSOC) {
953                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
954                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
955         } else if (led->type == LED_TYPE_QUALITY) {
956                 /*
957                  * The brightness is divided into 6 levels (0 - 5),
958                  * The specs tell us the following levels:
959                  *      0, 1 ,3, 7, 15, 31
960                  * to determine the level in a simple way we can simply
961                  * work with bitshifting:
962                  *      (1 << level) - 1
963                  */
964                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
965                                       (1 << brightness / (LED_FULL / 6)) - 1,
966                                       polarity);
967         }
968 }
969
970 static int rt2800_blink_set(struct led_classdev *led_cdev,
971                             unsigned long *delay_on, unsigned long *delay_off)
972 {
973         struct rt2x00_led *led =
974             container_of(led_cdev, struct rt2x00_led, led_dev);
975         u32 reg;
976
977         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
978         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
979         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
980         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
981
982         return 0;
983 }
984
985 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
986                      struct rt2x00_led *led, enum led_type type)
987 {
988         led->rt2x00dev = rt2x00dev;
989         led->type = type;
990         led->led_dev.brightness_set = rt2800_brightness_set;
991         led->led_dev.blink_set = rt2800_blink_set;
992         led->flags = LED_INITIALIZED;
993 }
994 #endif /* CONFIG_RT2X00_LIB_LEDS */
995
996 /*
997  * Configuration handlers.
998  */
999 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
1000                                     struct rt2x00lib_crypto *crypto,
1001                                     struct ieee80211_key_conf *key)
1002 {
1003         struct mac_wcid_entry wcid_entry;
1004         struct mac_iveiv_entry iveiv_entry;
1005         u32 offset;
1006         u32 reg;
1007
1008         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1009
1010         if (crypto->cmd == SET_KEY) {
1011                 rt2800_register_read(rt2x00dev, offset, &reg);
1012                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1013                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1014                 /*
1015                  * Both the cipher as the BSS Idx numbers are split in a main
1016                  * value of 3 bits, and a extended field for adding one additional
1017                  * bit to the value.
1018                  */
1019                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1020                                    (crypto->cipher & 0x7));
1021                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1022                                    (crypto->cipher & 0x8) >> 3);
1023                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
1024                                    (crypto->bssidx & 0x7));
1025                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1026                                    (crypto->bssidx & 0x8) >> 3);
1027                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1028                 rt2800_register_write(rt2x00dev, offset, reg);
1029         } else {
1030                 rt2800_register_write(rt2x00dev, offset, 0);
1031         }
1032
1033         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1034
1035         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1036         if ((crypto->cipher == CIPHER_TKIP) ||
1037             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1038             (crypto->cipher == CIPHER_AES))
1039                 iveiv_entry.iv[3] |= 0x20;
1040         iveiv_entry.iv[3] |= key->keyidx << 6;
1041         rt2800_register_multiwrite(rt2x00dev, offset,
1042                                       &iveiv_entry, sizeof(iveiv_entry));
1043
1044         offset = MAC_WCID_ENTRY(key->hw_key_idx);
1045
1046         memset(&wcid_entry, 0, sizeof(wcid_entry));
1047         if (crypto->cmd == SET_KEY)
1048                 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
1049         rt2800_register_multiwrite(rt2x00dev, offset,
1050                                       &wcid_entry, sizeof(wcid_entry));
1051 }
1052
1053 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1054                              struct rt2x00lib_crypto *crypto,
1055                              struct ieee80211_key_conf *key)
1056 {
1057         struct hw_key_entry key_entry;
1058         struct rt2x00_field32 field;
1059         u32 offset;
1060         u32 reg;
1061
1062         if (crypto->cmd == SET_KEY) {
1063                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1064
1065                 memcpy(key_entry.key, crypto->key,
1066                        sizeof(key_entry.key));
1067                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1068                        sizeof(key_entry.tx_mic));
1069                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1070                        sizeof(key_entry.rx_mic));
1071
1072                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1073                 rt2800_register_multiwrite(rt2x00dev, offset,
1074                                               &key_entry, sizeof(key_entry));
1075         }
1076
1077         /*
1078          * The cipher types are stored over multiple registers
1079          * starting with SHARED_KEY_MODE_BASE each word will have
1080          * 32 bits and contains the cipher types for 2 bssidx each.
1081          * Using the correct defines correctly will cause overhead,
1082          * so just calculate the correct offset.
1083          */
1084         field.bit_offset = 4 * (key->hw_key_idx % 8);
1085         field.bit_mask = 0x7 << field.bit_offset;
1086
1087         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1088
1089         rt2800_register_read(rt2x00dev, offset, &reg);
1090         rt2x00_set_field32(&reg, field,
1091                            (crypto->cmd == SET_KEY) * crypto->cipher);
1092         rt2800_register_write(rt2x00dev, offset, reg);
1093
1094         /*
1095          * Update WCID information
1096          */
1097         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1098
1099         return 0;
1100 }
1101 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1102
1103 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1104                                struct rt2x00lib_crypto *crypto,
1105                                struct ieee80211_key_conf *key)
1106 {
1107         struct hw_key_entry key_entry;
1108         u32 offset;
1109
1110         if (crypto->cmd == SET_KEY) {
1111                 /*
1112                  * 1 pairwise key is possible per AID, this means that the AID
1113                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
1114                  * last possible shared key entry.
1115                  *
1116                  * Since parts of the pairwise key table might be shared with
1117                  * the beacon frame buffers 6 & 7 we should only write into the
1118                  * first 222 entries.
1119                  */
1120                 if (crypto->aid > (222 - 32))
1121                         return -ENOSPC;
1122
1123                 key->hw_key_idx = 32 + crypto->aid;
1124
1125                 memcpy(key_entry.key, crypto->key,
1126                        sizeof(key_entry.key));
1127                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1128                        sizeof(key_entry.tx_mic));
1129                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1130                        sizeof(key_entry.rx_mic));
1131
1132                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1133                 rt2800_register_multiwrite(rt2x00dev, offset,
1134                                               &key_entry, sizeof(key_entry));
1135         }
1136
1137         /*
1138          * Update WCID information
1139          */
1140         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1141
1142         return 0;
1143 }
1144 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1145
1146 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1147                           const unsigned int filter_flags)
1148 {
1149         u32 reg;
1150
1151         /*
1152          * Start configuration steps.
1153          * Note that the version error will always be dropped
1154          * and broadcast frames will always be accepted since
1155          * there is no filter for it at this time.
1156          */
1157         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1158         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1159                            !(filter_flags & FIF_FCSFAIL));
1160         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1161                            !(filter_flags & FIF_PLCPFAIL));
1162         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1163                            !(filter_flags & FIF_PROMISC_IN_BSS));
1164         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1165         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1166         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1167                            !(filter_flags & FIF_ALLMULTI));
1168         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1169         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1170         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1171                            !(filter_flags & FIF_CONTROL));
1172         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1173                            !(filter_flags & FIF_CONTROL));
1174         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1175                            !(filter_flags & FIF_CONTROL));
1176         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1177                            !(filter_flags & FIF_CONTROL));
1178         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1179                            !(filter_flags & FIF_CONTROL));
1180         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1181                            !(filter_flags & FIF_PSPOLL));
1182         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1183         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1184         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1185                            !(filter_flags & FIF_CONTROL));
1186         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1187 }
1188 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1189
1190 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1191                         struct rt2x00intf_conf *conf, const unsigned int flags)
1192 {
1193         u32 reg;
1194         bool update_bssid = false;
1195
1196         if (flags & CONFIG_UPDATE_TYPE) {
1197                 /*
1198                  * Enable synchronisation.
1199                  */
1200                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1201                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1202                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1203         }
1204
1205         if (flags & CONFIG_UPDATE_MAC) {
1206                 if (flags & CONFIG_UPDATE_TYPE &&
1207                     conf->sync == TSF_SYNC_AP_NONE) {
1208                         /*
1209                          * The BSSID register has to be set to our own mac
1210                          * address in AP mode.
1211                          */
1212                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1213                         update_bssid = true;
1214                 }
1215
1216                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1217                         reg = le32_to_cpu(conf->mac[1]);
1218                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1219                         conf->mac[1] = cpu_to_le32(reg);
1220                 }
1221
1222                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1223                                               conf->mac, sizeof(conf->mac));
1224         }
1225
1226         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1227                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1228                         reg = le32_to_cpu(conf->bssid[1]);
1229                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1230                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1231                         conf->bssid[1] = cpu_to_le32(reg);
1232                 }
1233
1234                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1235                                               conf->bssid, sizeof(conf->bssid));
1236         }
1237 }
1238 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1239
1240 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1241                                     struct rt2x00lib_erp *erp)
1242 {
1243         bool any_sta_nongf = !!(erp->ht_opmode &
1244                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1245         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1246         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1247         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1248         u32 reg;
1249
1250         /* default protection rate for HT20: OFDM 24M */
1251         mm20_rate = gf20_rate = 0x4004;
1252
1253         /* default protection rate for HT40: duplicate OFDM 24M */
1254         mm40_rate = gf40_rate = 0x4084;
1255
1256         switch (protection) {
1257         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1258                 /*
1259                  * All STAs in this BSS are HT20/40 but there might be
1260                  * STAs not supporting greenfield mode.
1261                  * => Disable protection for HT transmissions.
1262                  */
1263                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1264
1265                 break;
1266         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1267                 /*
1268                  * All STAs in this BSS are HT20 or HT20/40 but there
1269                  * might be STAs not supporting greenfield mode.
1270                  * => Protect all HT40 transmissions.
1271                  */
1272                 mm20_mode = gf20_mode = 0;
1273                 mm40_mode = gf40_mode = 2;
1274
1275                 break;
1276         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1277                 /*
1278                  * Nonmember protection:
1279                  * According to 802.11n we _should_ protect all
1280                  * HT transmissions (but we don't have to).
1281                  *
1282                  * But if cts_protection is enabled we _shall_ protect
1283                  * all HT transmissions using a CCK rate.
1284                  *
1285                  * And if any station is non GF we _shall_ protect
1286                  * GF transmissions.
1287                  *
1288                  * We decide to protect everything
1289                  * -> fall through to mixed mode.
1290                  */
1291         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1292                 /*
1293                  * Legacy STAs are present
1294                  * => Protect all HT transmissions.
1295                  */
1296                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1297
1298                 /*
1299                  * If erp protection is needed we have to protect HT
1300                  * transmissions with CCK 11M long preamble.
1301                  */
1302                 if (erp->cts_protection) {
1303                         /* don't duplicate RTS/CTS in CCK mode */
1304                         mm20_rate = mm40_rate = 0x0003;
1305                         gf20_rate = gf40_rate = 0x0003;
1306                 }
1307                 break;
1308         };
1309
1310         /* check for STAs not supporting greenfield mode */
1311         if (any_sta_nongf)
1312                 gf20_mode = gf40_mode = 2;
1313
1314         /* Update HT protection config */
1315         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1316         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1317         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1318         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1319
1320         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1321         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1322         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1323         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1324
1325         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1326         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1327         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1328         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1329
1330         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1331         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1332         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1333         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1334 }
1335
1336 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1337                        u32 changed)
1338 {
1339         u32 reg;
1340
1341         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1342                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1343                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1344                                    !!erp->short_preamble);
1345                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1346                                    !!erp->short_preamble);
1347                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1348         }
1349
1350         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1351                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1352                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1353                                    erp->cts_protection ? 2 : 0);
1354                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1355         }
1356
1357         if (changed & BSS_CHANGED_BASIC_RATES) {
1358                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1359                                          erp->basic_rates);
1360                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1361         }
1362
1363         if (changed & BSS_CHANGED_ERP_SLOT) {
1364                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1365                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1366                                    erp->slot_time);
1367                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1368
1369                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1370                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1371                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1372         }
1373
1374         if (changed & BSS_CHANGED_BEACON_INT) {
1375                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1376                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1377                                    erp->beacon_int * 16);
1378                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1379         }
1380
1381         if (changed & BSS_CHANGED_HT)
1382                 rt2800_config_ht_opmode(rt2x00dev, erp);
1383 }
1384 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1385
1386 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1387                                      enum antenna ant)
1388 {
1389         u32 reg;
1390         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1391         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1392
1393         if (rt2x00_is_pci(rt2x00dev)) {
1394                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1395                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1396                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1397         } else if (rt2x00_is_usb(rt2x00dev))
1398                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1399                                    eesk_pin, 0);
1400
1401         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1402         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1403         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1404         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1405 }
1406
1407 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1408 {
1409         u8 r1;
1410         u8 r3;
1411         u16 eeprom;
1412
1413         rt2800_bbp_read(rt2x00dev, 1, &r1);
1414         rt2800_bbp_read(rt2x00dev, 3, &r3);
1415
1416         /*
1417          * Configure the TX antenna.
1418          */
1419         switch (ant->tx_chain_num) {
1420         case 1:
1421                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1422                 break;
1423         case 2:
1424                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1425                 break;
1426         case 3:
1427                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1428                 break;
1429         }
1430
1431         /*
1432          * Configure the RX antenna.
1433          */
1434         switch (ant->rx_chain_num) {
1435         case 1:
1436                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1437                     rt2x00_rt(rt2x00dev, RT3090) ||
1438                     rt2x00_rt(rt2x00dev, RT3390)) {
1439                         rt2x00_eeprom_read(rt2x00dev,
1440                                            EEPROM_NIC_CONF1, &eeprom);
1441                         if (rt2x00_get_field16(eeprom,
1442                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1443                                 rt2800_set_ant_diversity(rt2x00dev,
1444                                                 rt2x00dev->default_ant.rx);
1445                 }
1446                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1447                 break;
1448         case 2:
1449                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1450                 break;
1451         case 3:
1452                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1453                 break;
1454         }
1455
1456         rt2800_bbp_write(rt2x00dev, 3, r3);
1457         rt2800_bbp_write(rt2x00dev, 1, r1);
1458 }
1459 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1460
1461 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1462                                    struct rt2x00lib_conf *libconf)
1463 {
1464         u16 eeprom;
1465         short lna_gain;
1466
1467         if (libconf->rf.channel <= 14) {
1468                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1469                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1470         } else if (libconf->rf.channel <= 64) {
1471                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1472                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1473         } else if (libconf->rf.channel <= 128) {
1474                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1475                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1476         } else {
1477                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1478                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1479         }
1480
1481         rt2x00dev->lna_gain = lna_gain;
1482 }
1483
1484 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1485                                          struct ieee80211_conf *conf,
1486                                          struct rf_channel *rf,
1487                                          struct channel_info *info)
1488 {
1489         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1490
1491         if (rt2x00dev->default_ant.tx_chain_num == 1)
1492                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1493
1494         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1495                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1496                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1497         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1498                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1499
1500         if (rf->channel > 14) {
1501                 /*
1502                  * When TX power is below 0, we should increase it by 7 to
1503                  * make it a positive value (Minumum value is -7).
1504                  * However this means that values between 0 and 7 have
1505                  * double meaning, and we should set a 7DBm boost flag.
1506                  */
1507                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1508                                    (info->default_power1 >= 0));
1509
1510                 if (info->default_power1 < 0)
1511                         info->default_power1 += 7;
1512
1513                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1514
1515                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1516                                    (info->default_power2 >= 0));
1517
1518                 if (info->default_power2 < 0)
1519                         info->default_power2 += 7;
1520
1521                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1522         } else {
1523                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1524                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1525         }
1526
1527         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1528
1529         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1530         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1531         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1532         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1533
1534         udelay(200);
1535
1536         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1537         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1538         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1539         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1540
1541         udelay(200);
1542
1543         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1544         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1545         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1546         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1547 }
1548
1549 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1550                                          struct ieee80211_conf *conf,
1551                                          struct rf_channel *rf,
1552                                          struct channel_info *info)
1553 {
1554         u8 rfcsr;
1555
1556         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1557         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1558
1559         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1560         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1561         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1562
1563         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1564         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1565         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1566
1567         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1568         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1569         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1570
1571         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1572         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1573         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1574
1575         rt2800_rfcsr_write(rt2x00dev, 24,
1576                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1577
1578         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1579         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1580         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1581 }
1582
1583
1584 #define RT5390_POWER_BOUND     0x27
1585 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1586
1587 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1588                                          struct ieee80211_conf *conf,
1589                                          struct rf_channel *rf,
1590                                          struct channel_info *info)
1591 {
1592         u8 rfcsr;
1593         u16 eeprom;
1594
1595         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1596         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1597         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1598         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1599         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1600
1601         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1602         if (info->default_power1 > RT5390_POWER_BOUND)
1603                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1604         else
1605                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1606         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1607
1608         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1609         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1610         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1611         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1612         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1613         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1614
1615         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1616         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1617                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1618                                   RT5390_FREQ_OFFSET_BOUND);
1619         else
1620                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1621         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1622
1623         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1624         if (rf->channel <= 14) {
1625                 int idx = rf->channel-1;
1626
1627                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
1628                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1629                                 /* r55/r59 value array of channel 1~14 */
1630                                 static const char r55_bt_rev[] = {0x83, 0x83,
1631                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1632                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1633                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1634                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1635                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1636
1637                                 rt2800_rfcsr_write(rt2x00dev, 55,
1638                                                    r55_bt_rev[idx]);
1639                                 rt2800_rfcsr_write(rt2x00dev, 59,
1640                                                    r59_bt_rev[idx]);
1641                         } else {
1642                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1643                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1644                                         0x88, 0x88, 0x86, 0x85, 0x84};
1645
1646                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1647                         }
1648                 } else {
1649                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1650                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1651                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1652                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1653                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1654                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1655                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1656
1657                                 rt2800_rfcsr_write(rt2x00dev, 55,
1658                                                    r55_nonbt_rev[idx]);
1659                                 rt2800_rfcsr_write(rt2x00dev, 59,
1660                                                    r59_nonbt_rev[idx]);
1661                         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1662                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1663                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1664                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1665
1666                                 rt2800_rfcsr_write(rt2x00dev, 59,
1667                                                    r59_non_bt[idx]);
1668                         }
1669                 }
1670         }
1671
1672         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1673         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1674         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1675         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1676
1677         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1678         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1679         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1680 }
1681
1682 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1683                                   struct ieee80211_conf *conf,
1684                                   struct rf_channel *rf,
1685                                   struct channel_info *info)
1686 {
1687         u32 reg;
1688         unsigned int tx_pin;
1689         u8 bbp;
1690
1691         if (rf->channel <= 14) {
1692                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1693                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1694         } else {
1695                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1696                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1697         }
1698
1699         if (rt2x00_rf(rt2x00dev, RF2020) ||
1700             rt2x00_rf(rt2x00dev, RF3020) ||
1701             rt2x00_rf(rt2x00dev, RF3021) ||
1702             rt2x00_rf(rt2x00dev, RF3022) ||
1703             rt2x00_rf(rt2x00dev, RF3052) ||
1704             rt2x00_rf(rt2x00dev, RF3320))
1705                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1706         else if (rt2x00_rf(rt2x00dev, RF5390))
1707                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1708         else
1709                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1710
1711         /*
1712          * Change BBP settings
1713          */
1714         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1715         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1716         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1717         rt2800_bbp_write(rt2x00dev, 86, 0);
1718
1719         if (rf->channel <= 14) {
1720                 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1721                         if (test_bit(CONFIG_EXTERNAL_LNA_BG,
1722                                      &rt2x00dev->flags)) {
1723                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1724                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1725                         } else {
1726                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1727                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1728                         }
1729                 }
1730         } else {
1731                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1732
1733                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1734                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1735                 else
1736                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1737         }
1738
1739         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1740         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1741         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1742         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1743         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1744
1745         tx_pin = 0;
1746
1747         /* Turn on unused PA or LNA when not using 1T or 1R */
1748         if (rt2x00dev->default_ant.tx_chain_num == 2) {
1749                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1750                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1751         }
1752
1753         /* Turn on unused PA or LNA when not using 1T or 1R */
1754         if (rt2x00dev->default_ant.rx_chain_num == 2) {
1755                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1756                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1757         }
1758
1759         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1760         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1761         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1762         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1763         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1764         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1765
1766         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1767
1768         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1769         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1770         rt2800_bbp_write(rt2x00dev, 4, bbp);
1771
1772         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1773         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1774         rt2800_bbp_write(rt2x00dev, 3, bbp);
1775
1776         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1777                 if (conf_is_ht40(conf)) {
1778                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1779                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1780                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1781                 } else {
1782                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1783                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1784                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1785                 }
1786         }
1787
1788         msleep(1);
1789
1790         /*
1791          * Clear channel statistic counters
1792          */
1793         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1794         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1795         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1796 }
1797
1798 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
1799                                       enum ieee80211_band band)
1800 {
1801         u16 eeprom;
1802         u8 comp_en;
1803         u8 comp_type;
1804         int comp_value;
1805
1806         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1807
1808         if (eeprom == 0xffff)
1809                 return 0;
1810
1811         if (band == IEEE80211_BAND_2GHZ) {
1812                 comp_en = rt2x00_get_field16(eeprom,
1813                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
1814                 if (comp_en) {
1815                         comp_type = rt2x00_get_field16(eeprom,
1816                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
1817                         comp_value = rt2x00_get_field16(eeprom,
1818                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
1819                         if (!comp_type)
1820                                 comp_value = -comp_value;
1821                 }
1822         } else {
1823                 comp_en = rt2x00_get_field16(eeprom,
1824                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
1825                 if (comp_en) {
1826                         comp_type = rt2x00_get_field16(eeprom,
1827                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
1828                         comp_value = rt2x00_get_field16(eeprom,
1829                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
1830                         if (!comp_type)
1831                                 comp_value = -comp_value;
1832                 }
1833         }
1834
1835         return comp_value;
1836 }
1837
1838 static u8 rt2800_compesate_txpower(struct rt2x00_dev *rt2x00dev,
1839                                      int is_rate_b,
1840                                      enum ieee80211_band band,
1841                                      int power_level,
1842                                      u8 txpower)
1843 {
1844         u32 reg;
1845         u16 eeprom;
1846         u8 criterion;
1847         u8 eirp_txpower;
1848         u8 eirp_txpower_criterion;
1849         u8 reg_limit;
1850         int bw_comp = 0;
1851
1852         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
1853                 return txpower;
1854
1855         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1856                 bw_comp = rt2800_get_txpower_bw_comp(rt2x00dev, band);
1857
1858         if (test_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags)) {
1859                 /*
1860                  * Check if eirp txpower exceed txpower_limit.
1861                  * We use OFDM 6M as criterion and its eirp txpower
1862                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
1863                  * .11b data rate need add additional 4dbm
1864                  * when calculating eirp txpower.
1865                  */
1866                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1867                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
1868
1869                 rt2x00_eeprom_read(rt2x00dev,
1870                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
1871
1872                 if (band == IEEE80211_BAND_2GHZ)
1873                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1874                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
1875                 else
1876                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1877                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
1878
1879                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
1880                                        (is_rate_b ? 4 : 0) + bw_comp;
1881
1882                 reg_limit = (eirp_txpower > power_level) ?
1883                                         (eirp_txpower - power_level) : 0;
1884         } else
1885                 reg_limit = 0;
1886
1887         return txpower + bw_comp - reg_limit;
1888 }
1889
1890 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1891                                   struct ieee80211_conf *conf)
1892 {
1893         u8 txpower;
1894         u16 eeprom;
1895         int i, is_rate_b;
1896         u32 reg;
1897         u8 r1;
1898         u32 offset;
1899         enum ieee80211_band band = conf->channel->band;
1900         int power_level = conf->power_level;
1901
1902         /*
1903          * set to normal bbp tx power control mode: +/- 0dBm
1904          */
1905         rt2800_bbp_read(rt2x00dev, 1, &r1);
1906         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
1907         rt2800_bbp_write(rt2x00dev, 1, r1);
1908         offset = TX_PWR_CFG_0;
1909
1910         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1911                 /* just to be safe */
1912                 if (offset > TX_PWR_CFG_4)
1913                         break;
1914
1915                 rt2800_register_read(rt2x00dev, offset, &reg);
1916
1917                 /* read the next four txpower values */
1918                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1919                                    &eeprom);
1920
1921                 is_rate_b = i ? 0 : 1;
1922                 /*
1923                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1924                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1925                  * TX_PWR_CFG_4: unknown
1926                  */
1927                 txpower = rt2x00_get_field16(eeprom,
1928                                              EEPROM_TXPOWER_BYRATE_RATE0);
1929                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1930                                              power_level, txpower);
1931                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
1932
1933                 /*
1934                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1935                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1936                  * TX_PWR_CFG_4: unknown
1937                  */
1938                 txpower = rt2x00_get_field16(eeprom,
1939                                              EEPROM_TXPOWER_BYRATE_RATE1);
1940                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1941                                              power_level, txpower);
1942                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
1943
1944                 /*
1945                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
1946                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
1947                  * TX_PWR_CFG_4: unknown
1948                  */
1949                 txpower = rt2x00_get_field16(eeprom,
1950                                              EEPROM_TXPOWER_BYRATE_RATE2);
1951                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1952                                              power_level, txpower);
1953                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
1954
1955                 /*
1956                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1957                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
1958                  * TX_PWR_CFG_4: unknown
1959                  */
1960                 txpower = rt2x00_get_field16(eeprom,
1961                                              EEPROM_TXPOWER_BYRATE_RATE3);
1962                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1963                                              power_level, txpower);
1964                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
1965
1966                 /* read the next four txpower values */
1967                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1968                                    &eeprom);
1969
1970                 is_rate_b = 0;
1971                 /*
1972                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1973                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1974                  * TX_PWR_CFG_4: unknown
1975                  */
1976                 txpower = rt2x00_get_field16(eeprom,
1977                                              EEPROM_TXPOWER_BYRATE_RATE0);
1978                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1979                                              power_level, txpower);
1980                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
1981
1982                 /*
1983                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1984                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1985                  * TX_PWR_CFG_4: unknown
1986                  */
1987                 txpower = rt2x00_get_field16(eeprom,
1988                                              EEPROM_TXPOWER_BYRATE_RATE1);
1989                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1990                                              power_level, txpower);
1991                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
1992
1993                 /*
1994                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1995                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1996                  * TX_PWR_CFG_4: unknown
1997                  */
1998                 txpower = rt2x00_get_field16(eeprom,
1999                                              EEPROM_TXPOWER_BYRATE_RATE2);
2000                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
2001                                              power_level, txpower);
2002                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2003
2004                 /*
2005                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2006                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2007                  * TX_PWR_CFG_4: unknown
2008                  */
2009                 txpower = rt2x00_get_field16(eeprom,
2010                                              EEPROM_TXPOWER_BYRATE_RATE3);
2011                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
2012                                              power_level, txpower);
2013                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2014
2015                 rt2800_register_write(rt2x00dev, offset, reg);
2016
2017                 /* next TX_PWR_CFG register */
2018                 offset += 4;
2019         }
2020 }
2021
2022 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2023                                       struct rt2x00lib_conf *libconf)
2024 {
2025         u32 reg;
2026
2027         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2028         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2029                            libconf->conf->short_frame_max_tx_count);
2030         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2031                            libconf->conf->long_frame_max_tx_count);
2032         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2033 }
2034
2035 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2036                              struct rt2x00lib_conf *libconf)
2037 {
2038         enum dev_state state =
2039             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2040                 STATE_SLEEP : STATE_AWAKE;
2041         u32 reg;
2042
2043         if (state == STATE_SLEEP) {
2044                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2045
2046                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2047                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2048                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2049                                    libconf->conf->listen_interval - 1);
2050                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2051                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2052
2053                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2054         } else {
2055                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2056                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2057                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2058                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2059                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2060
2061                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2062         }
2063 }
2064
2065 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2066                    struct rt2x00lib_conf *libconf,
2067                    const unsigned int flags)
2068 {
2069         /* Always recalculate LNA gain before changing configuration */
2070         rt2800_config_lna_gain(rt2x00dev, libconf);
2071
2072         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2073                 rt2800_config_channel(rt2x00dev, libconf->conf,
2074                                       &libconf->rf, &libconf->channel);
2075                 rt2800_config_txpower(rt2x00dev, libconf->conf);
2076         }
2077         if (flags & IEEE80211_CONF_CHANGE_POWER)
2078                 rt2800_config_txpower(rt2x00dev, libconf->conf);
2079         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2080                 rt2800_config_retry_limit(rt2x00dev, libconf);
2081         if (flags & IEEE80211_CONF_CHANGE_PS)
2082                 rt2800_config_ps(rt2x00dev, libconf);
2083 }
2084 EXPORT_SYMBOL_GPL(rt2800_config);
2085
2086 /*
2087  * Link tuning
2088  */
2089 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2090 {
2091         u32 reg;
2092
2093         /*
2094          * Update FCS error count from register.
2095          */
2096         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2097         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2098 }
2099 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2100
2101 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2102 {
2103         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2104                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2105                     rt2x00_rt(rt2x00dev, RT3071) ||
2106                     rt2x00_rt(rt2x00dev, RT3090) ||
2107                     rt2x00_rt(rt2x00dev, RT3390) ||
2108                     rt2x00_rt(rt2x00dev, RT5390))
2109                         return 0x1c + (2 * rt2x00dev->lna_gain);
2110                 else
2111                         return 0x2e + rt2x00dev->lna_gain;
2112         }
2113
2114         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2115                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2116         else
2117                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2118 }
2119
2120 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2121                                   struct link_qual *qual, u8 vgc_level)
2122 {
2123         if (qual->vgc_level != vgc_level) {
2124                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2125                 qual->vgc_level = vgc_level;
2126                 qual->vgc_level_reg = vgc_level;
2127         }
2128 }
2129
2130 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2131 {
2132         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2133 }
2134 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2135
2136 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2137                        const u32 count)
2138 {
2139         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2140                 return;
2141
2142         /*
2143          * When RSSI is better then -80 increase VGC level with 0x10
2144          */
2145         rt2800_set_vgc(rt2x00dev, qual,
2146                        rt2800_get_default_vgc(rt2x00dev) +
2147                        ((qual->rssi > -80) * 0x10));
2148 }
2149 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2150
2151 /*
2152  * Initialization functions.
2153  */
2154 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2155 {
2156         u32 reg;
2157         u16 eeprom;
2158         unsigned int i;
2159         int ret;
2160
2161         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2162         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2163         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2164         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2165         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2166         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2167         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2168
2169         ret = rt2800_drv_init_registers(rt2x00dev);
2170         if (ret)
2171                 return ret;
2172
2173         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2174         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2175         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2176         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2177         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2178         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2179
2180         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2181         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2182         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2183         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2184         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2185         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2186
2187         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2188         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2189
2190         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2191
2192         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2193         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2194         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2195         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2196         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2197         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2198         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2199         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2200
2201         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2202
2203         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2204         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2205         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2206         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2207
2208         if (rt2x00_rt(rt2x00dev, RT3071) ||
2209             rt2x00_rt(rt2x00dev, RT3090) ||
2210             rt2x00_rt(rt2x00dev, RT3390)) {
2211                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2212                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2213                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2214                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2215                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2216                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2217                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2218                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2219                                                       0x0000002c);
2220                         else
2221                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2222                                                       0x0000000f);
2223                 } else {
2224                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2225                 }
2226         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2227                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2228
2229                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2230                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2231                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2232                 } else {
2233                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2234                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2235                 }
2236         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2237                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2238                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2239                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
2240         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2241                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2242                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2243                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2244         } else {
2245                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2246                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2247         }
2248
2249         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2250         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2251         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2252         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2253         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2254         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2255         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2256         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2257         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2258         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2259
2260         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2261         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2262         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2263         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2264         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2265
2266         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2267         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2268         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2269             rt2x00_rt(rt2x00dev, RT2883) ||
2270             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2271                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2272         else
2273                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2274         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2275         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2276         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2277
2278         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2279         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2280         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2281         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2282         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2283         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2284         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2285         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2286         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2287
2288         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2289
2290         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2291         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2292         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2293         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2294         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2295         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2296         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2297         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2298
2299         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2300         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2301         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2302         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2303         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2304         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2305         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2306         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2307         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2308
2309         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2310         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2311         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2312         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2313         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2314         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2315         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2316         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2317         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2318         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2319         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2320         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2321
2322         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2323         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2324         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2325         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2326         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2327         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2328         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2329         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2330         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2331         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2332         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2333         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2334
2335         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2336         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2337         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2338         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2339         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2340         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2341         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2342         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2343         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2344         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2345         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2346         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2347
2348         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2349         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2350         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2351         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2352         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2353         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2354         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2355         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2356         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2357         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2358         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2359         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2360
2361         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2362         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2363         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2364         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2365         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2366         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2367         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2368         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2369         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2370         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2371         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2372         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2373
2374         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2375         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2376         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2377         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2378         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2379         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2380         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2381         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2382         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2383         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2384         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2385         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2386
2387         if (rt2x00_is_usb(rt2x00dev)) {
2388                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2389
2390                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2391                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2392                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2393                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2394                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2395                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2396                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2397                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2398                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2399                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2400                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2401         }
2402
2403         /*
2404          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2405          * although it is reserved.
2406          */
2407         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2408         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2409         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2410         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2411         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2412         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2413         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2414         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2415         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2416         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2417         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2418         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2419
2420         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2421
2422         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2423         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2424         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2425                            IEEE80211_MAX_RTS_THRESHOLD);
2426         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2427         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2428
2429         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2430
2431         /*
2432          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2433          * time should be set to 16. However, the original Ralink driver uses
2434          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2435          * connection problems with 11g + CTS protection. Hence, use the same
2436          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2437          */
2438         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2439         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2440         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2441         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2442         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2443         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2444         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2445
2446         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2447
2448         /*
2449          * ASIC will keep garbage value after boot, clear encryption keys.
2450          */
2451         for (i = 0; i < 4; i++)
2452                 rt2800_register_write(rt2x00dev,
2453                                          SHARED_KEY_MODE_ENTRY(i), 0);
2454
2455         for (i = 0; i < 256; i++) {
2456                 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2457                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2458                                               wcid, sizeof(wcid));
2459
2460                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2461                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2462         }
2463
2464         /*
2465          * Clear all beacons
2466          */
2467         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2468         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2469         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2470         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2471         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2472         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2473         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2474         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2475
2476         if (rt2x00_is_usb(rt2x00dev)) {
2477                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2478                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2479                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2480         } else if (rt2x00_is_pcie(rt2x00dev)) {
2481                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2482                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2483                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2484         }
2485
2486         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2487         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2488         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2489         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2490         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2491         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2492         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2493         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2494         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2495         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2496
2497         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2498         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2499         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2500         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2501         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2502         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2503         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2504         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2505         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2506         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2507
2508         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2509         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2510         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2511         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2512         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2513         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2514         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2515         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2516         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2517         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2518
2519         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2520         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2521         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2522         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2523         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2524         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2525
2526         /*
2527          * Do not force the BA window size, we use the TXWI to set it
2528          */
2529         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2530         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2531         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2532         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2533
2534         /*
2535          * We must clear the error counters.
2536          * These registers are cleared on read,
2537          * so we may pass a useless variable to store the value.
2538          */
2539         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2540         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2541         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2542         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2543         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2544         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2545
2546         /*
2547          * Setup leadtime for pre tbtt interrupt to 6ms
2548          */
2549         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2550         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2551         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2552
2553         /*
2554          * Set up channel statistics timer
2555          */
2556         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2557         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2558         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2559         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2560         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2561         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2562         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2563
2564         return 0;
2565 }
2566
2567 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2568 {
2569         unsigned int i;
2570         u32 reg;
2571
2572         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2573                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2574                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2575                         return 0;
2576
2577                 udelay(REGISTER_BUSY_DELAY);
2578         }
2579
2580         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2581         return -EACCES;
2582 }
2583
2584 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2585 {
2586         unsigned int i;
2587         u8 value;
2588
2589         /*
2590          * BBP was enabled after firmware was loaded,
2591          * but we need to reactivate it now.
2592          */
2593         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2594         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2595         msleep(1);
2596
2597         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2598                 rt2800_bbp_read(rt2x00dev, 0, &value);
2599                 if ((value != 0xff) && (value != 0x00))
2600                         return 0;
2601                 udelay(REGISTER_BUSY_DELAY);
2602         }
2603
2604         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2605         return -EACCES;
2606 }
2607
2608 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2609 {
2610         unsigned int i;
2611         u16 eeprom;
2612         u8 reg_id;
2613         u8 value;
2614
2615         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2616                      rt2800_wait_bbp_ready(rt2x00dev)))
2617                 return -EACCES;
2618
2619         if (rt2x00_rt(rt2x00dev, RT5390)) {
2620                 rt2800_bbp_read(rt2x00dev, 4, &value);
2621                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2622                 rt2800_bbp_write(rt2x00dev, 4, value);
2623         }
2624
2625         if (rt2800_is_305x_soc(rt2x00dev) ||
2626             rt2x00_rt(rt2x00dev, RT5390))
2627                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2628
2629         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2630         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2631
2632         if (rt2x00_rt(rt2x00dev, RT5390))
2633                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2634
2635         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2636                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2637                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2638         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2639                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2640                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2641                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2642                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2643                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
2644         } else {
2645                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2646                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2647         }
2648
2649         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2650
2651         if (rt2x00_rt(rt2x00dev, RT3070) ||
2652             rt2x00_rt(rt2x00dev, RT3071) ||
2653             rt2x00_rt(rt2x00dev, RT3090) ||
2654             rt2x00_rt(rt2x00dev, RT3390) ||
2655             rt2x00_rt(rt2x00dev, RT5390)) {
2656                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2657                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2658                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2659         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2660                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2661                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2662         } else {
2663                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2664         }
2665
2666         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2667         if (rt2x00_rt(rt2x00dev, RT5390))
2668                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2669         else
2670                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2671
2672         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2673                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2674         else if (rt2x00_rt(rt2x00dev, RT5390))
2675                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2676         else
2677                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2678
2679         if (rt2x00_rt(rt2x00dev, RT5390))
2680                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2681         else
2682                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2683
2684         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2685
2686         if (rt2x00_rt(rt2x00dev, RT5390))
2687                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2688         else
2689                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2690
2691         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2692             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2693             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2694             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2695             rt2x00_rt(rt2x00dev, RT5390) ||
2696             rt2800_is_305x_soc(rt2x00dev))
2697                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2698         else
2699                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2700
2701         if (rt2x00_rt(rt2x00dev, RT5390))
2702                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
2703
2704         if (rt2800_is_305x_soc(rt2x00dev))
2705                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2706         else if (rt2x00_rt(rt2x00dev, RT5390))
2707                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
2708         else
2709                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2710
2711         if (rt2x00_rt(rt2x00dev, RT5390))
2712                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2713         else
2714                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2715
2716         if (rt2x00_rt(rt2x00dev, RT5390))
2717                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
2718
2719         if (rt2x00_rt(rt2x00dev, RT3071) ||
2720             rt2x00_rt(rt2x00dev, RT3090) ||
2721             rt2x00_rt(rt2x00dev, RT3390) ||
2722             rt2x00_rt(rt2x00dev, RT5390)) {
2723                 rt2800_bbp_read(rt2x00dev, 138, &value);
2724
2725                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2726                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2727                         value |= 0x20;
2728                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2729                         value &= ~0x02;
2730
2731                 rt2800_bbp_write(rt2x00dev, 138, value);
2732         }
2733
2734         if (rt2x00_rt(rt2x00dev, RT5390)) {
2735                 int ant, div_mode;
2736
2737                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2738                 div_mode = rt2x00_get_field16(eeprom,
2739                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
2740                 ant = (div_mode == 3) ? 1 : 0;
2741
2742                 /* check if this is a Bluetooth combo card */
2743                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2744                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
2745                         u32 reg;
2746
2747                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2748                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2749                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2750                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2751                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2752                         if (ant == 0)
2753                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2754                         else if (ant == 1)
2755                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2756                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2757                 }
2758
2759                 rt2800_bbp_read(rt2x00dev, 152, &value);
2760                 if (ant == 0)
2761                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2762                 else
2763                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2764                 rt2800_bbp_write(rt2x00dev, 152, value);
2765
2766                 /* Init frequency calibration */
2767                 rt2800_bbp_write(rt2x00dev, 142, 1);
2768                 rt2800_bbp_write(rt2x00dev, 143, 57);
2769         }
2770
2771         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2772                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2773
2774                 if (eeprom != 0xffff && eeprom != 0x0000) {
2775                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2776                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2777                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2778                 }
2779         }
2780
2781         return 0;
2782 }
2783
2784 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2785                                 bool bw40, u8 rfcsr24, u8 filter_target)
2786 {
2787         unsigned int i;
2788         u8 bbp;
2789         u8 rfcsr;
2790         u8 passband;
2791         u8 stopband;
2792         u8 overtuned = 0;
2793
2794         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2795
2796         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2797         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2798         rt2800_bbp_write(rt2x00dev, 4, bbp);
2799
2800         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2801         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2802         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2803
2804         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2805         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2806         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2807
2808         /*
2809          * Set power & frequency of passband test tone
2810          */
2811         rt2800_bbp_write(rt2x00dev, 24, 0);
2812
2813         for (i = 0; i < 100; i++) {
2814                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2815                 msleep(1);
2816
2817                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2818                 if (passband)
2819                         break;
2820         }
2821
2822         /*
2823          * Set power & frequency of stopband test tone
2824          */
2825         rt2800_bbp_write(rt2x00dev, 24, 0x06);
2826
2827         for (i = 0; i < 100; i++) {
2828                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2829                 msleep(1);
2830
2831                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2832
2833                 if ((passband - stopband) <= filter_target) {
2834                         rfcsr24++;
2835                         overtuned += ((passband - stopband) == filter_target);
2836                 } else
2837                         break;
2838
2839                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2840         }
2841
2842         rfcsr24 -= !!overtuned;
2843
2844         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2845         return rfcsr24;
2846 }
2847
2848 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2849 {
2850         u8 rfcsr;
2851         u8 bbp;
2852         u32 reg;
2853         u16 eeprom;
2854
2855         if (!rt2x00_rt(rt2x00dev, RT3070) &&
2856             !rt2x00_rt(rt2x00dev, RT3071) &&
2857             !rt2x00_rt(rt2x00dev, RT3090) &&
2858             !rt2x00_rt(rt2x00dev, RT3390) &&
2859             !rt2x00_rt(rt2x00dev, RT5390) &&
2860             !rt2800_is_305x_soc(rt2x00dev))
2861                 return 0;
2862
2863         /*
2864          * Init RF calibration.
2865          */
2866         if (rt2x00_rt(rt2x00dev, RT5390)) {
2867                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
2868                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
2869                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2870                 msleep(1);
2871                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
2872                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2873         } else {
2874                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2875                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2876                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2877                 msleep(1);
2878                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2879                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2880         }
2881
2882         if (rt2x00_rt(rt2x00dev, RT3070) ||
2883             rt2x00_rt(rt2x00dev, RT3071) ||
2884             rt2x00_rt(rt2x00dev, RT3090)) {
2885                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2886                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2887                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2888                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
2889                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2890                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2891                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2892                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2893                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2894                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2895                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2896                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2897                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2898                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2899                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2900                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2901                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2902                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2903                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2904         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2905                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2906                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2907                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2908                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2909                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2910                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2911                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2912                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2913                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2914                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2915                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2916                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2917                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2918                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2919                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2920                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2921                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2922                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2923                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2924                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2925                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2926                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2927                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2928                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2929                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2930                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2931                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2932                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2933                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2934                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2935                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2936                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2937         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2938                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2939                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2940                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2941                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2942                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2943                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2944                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2945                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2946                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2947                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2948                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2949                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2950                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2951                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2952                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2953                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2954                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2955                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2956                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2957                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2958                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2959                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2960                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2961                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2962                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2963                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2964                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2965                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2966                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2967                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2968                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2969                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2970                 return 0;
2971         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2972                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
2973                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
2974                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
2975                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
2976                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2977                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
2978                 else
2979                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
2980                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
2981                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
2982                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
2983                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
2984                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
2985                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
2986                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
2987                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
2988                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
2989                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
2990
2991                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
2992                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
2993                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
2994                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
2995                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
2996                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2997                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2998                 else
2999                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3000                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3001                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3002                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3003                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3004
3005                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3006                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3007                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3008                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3009                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3010                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3011                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3012                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3013                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3014                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3015
3016                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3017                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3018                 else
3019                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3020                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3021                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3022                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3023                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3024                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3025                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3026                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3027                 else
3028                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3029                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3030                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3031                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3032
3033                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3034                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3035                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3036                 else
3037                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3038                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3039                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3040                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3041                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3042                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3043                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3044
3045                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3046                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3047                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3048                 else
3049                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3050                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3051                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3052         }
3053
3054         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3055                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3056                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3057                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3058                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3059         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3060                    rt2x00_rt(rt2x00dev, RT3090)) {
3061                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3062
3063                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3064                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3065                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3066
3067                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3068                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3069                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3070                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3071                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3072                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3073                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3074                         else
3075                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3076                 }
3077                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3078
3079                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3080                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3081                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3082         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3083                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3084                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3085                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3086         }
3087
3088         /*
3089          * Set RX Filter calibration for 20MHz and 40MHz
3090          */
3091         if (rt2x00_rt(rt2x00dev, RT3070)) {
3092                 rt2x00dev->calibration[0] =
3093                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3094                 rt2x00dev->calibration[1] =
3095                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3096         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3097                    rt2x00_rt(rt2x00dev, RT3090) ||
3098                    rt2x00_rt(rt2x00dev, RT3390)) {
3099                 rt2x00dev->calibration[0] =
3100                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3101                 rt2x00dev->calibration[1] =
3102                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3103         }
3104
3105         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3106                 /*
3107                  * Set back to initial state
3108                  */
3109                 rt2800_bbp_write(rt2x00dev, 24, 0);
3110
3111                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3112                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3113                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3114
3115                 /*
3116                  * Set BBP back to BW20
3117                  */
3118                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3119                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3120                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3121         }
3122
3123         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3124             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3125             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3126             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3127                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3128
3129         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3130         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3131         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3132
3133         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3134                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3135                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3136                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3137                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3138                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3139                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3140                         if (!test_bit(CONFIG_EXTERNAL_LNA_BG,
3141                                       &rt2x00dev->flags))
3142                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3143                 }
3144                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3145                 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3146                         rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3147                                         rt2x00_get_field16(eeprom,
3148                                                 EEPROM_TXMIXER_GAIN_BG_VAL));
3149                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3150         }
3151
3152         if (rt2x00_rt(rt2x00dev, RT3090)) {
3153                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3154
3155                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3156                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3157                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3158                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3159                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3160                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3161
3162                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3163         }
3164
3165         if (rt2x00_rt(rt2x00dev, RT3071) ||
3166             rt2x00_rt(rt2x00dev, RT3090) ||
3167             rt2x00_rt(rt2x00dev, RT3390)) {
3168                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3169                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3170                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3171                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3172                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3173                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3174                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3175
3176                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3177                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3178                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3179
3180                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3181                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3182                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3183
3184                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3185                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3186                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3187         }
3188
3189         if (rt2x00_rt(rt2x00dev, RT3070)) {
3190                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3191                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3192                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3193                 else
3194                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3195                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3196                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3197                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3198                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3199         }
3200
3201         if (rt2x00_rt(rt2x00dev, RT5390)) {
3202                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3203                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3204                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3205
3206                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3207                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3208                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3209
3210                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3211                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3212                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3213         }
3214
3215         return 0;
3216 }
3217
3218 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3219 {
3220         u32 reg;
3221         u16 word;
3222
3223         /*
3224          * Initialize all registers.
3225          */
3226         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3227                      rt2800_init_registers(rt2x00dev) ||
3228                      rt2800_init_bbp(rt2x00dev) ||
3229                      rt2800_init_rfcsr(rt2x00dev)))
3230                 return -EIO;
3231
3232         /*
3233          * Send signal to firmware during boot time.
3234          */
3235         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3236
3237         if (rt2x00_is_usb(rt2x00dev) &&
3238             (rt2x00_rt(rt2x00dev, RT3070) ||
3239              rt2x00_rt(rt2x00dev, RT3071) ||
3240              rt2x00_rt(rt2x00dev, RT3572))) {
3241                 udelay(200);
3242                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3243                 udelay(10);
3244         }
3245
3246         /*
3247          * Enable RX.
3248          */
3249         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3250         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3251         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3252         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3253
3254         udelay(50);
3255
3256         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3257         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3258         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3259         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3260         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3261         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3262
3263         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3264         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3265         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3266         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3267
3268         /*
3269          * Initialize LED control
3270          */
3271         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3272         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3273                            word & 0xff, (word >> 8) & 0xff);
3274
3275         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3276         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3277                            word & 0xff, (word >> 8) & 0xff);
3278
3279         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3280         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3281                            word & 0xff, (word >> 8) & 0xff);
3282
3283         return 0;
3284 }
3285 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3286
3287 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3288 {
3289         u32 reg;
3290
3291         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3292         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3293         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3294         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3295
3296         /* Wait for DMA, ignore error */
3297         rt2800_wait_wpdma_ready(rt2x00dev);
3298
3299         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3300         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3301         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3302         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3303 }
3304 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3305
3306 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3307 {
3308         u32 reg;
3309
3310         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3311
3312         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3313 }
3314 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3315
3316 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3317 {
3318         u32 reg;
3319
3320         mutex_lock(&rt2x00dev->csr_mutex);
3321
3322         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3323         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3324         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3325         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3326         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3327
3328         /* Wait until the EEPROM has been loaded */
3329         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3330
3331         /* Apparently the data is read from end to start */
3332         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
3333                                         (u32 *)&rt2x00dev->eeprom[i]);
3334         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
3335                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
3336         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
3337                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
3338         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
3339                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
3340
3341         mutex_unlock(&rt2x00dev->csr_mutex);
3342 }
3343
3344 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3345 {
3346         unsigned int i;
3347
3348         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3349                 rt2800_efuse_read(rt2x00dev, i);
3350 }
3351 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3352
3353 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3354 {
3355         u16 word;
3356         u8 *mac;
3357         u8 default_lna_gain;
3358
3359         /*
3360          * Start validation of the data that has been read.
3361          */
3362         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3363         if (!is_valid_ether_addr(mac)) {
3364                 random_ether_addr(mac);
3365                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3366         }
3367
3368         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3369         if (word == 0xffff) {
3370                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3371                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3372                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3373                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3374                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3375         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3376                    rt2x00_rt(rt2x00dev, RT2872)) {
3377                 /*
3378                  * There is a max of 2 RX streams for RT28x0 series
3379                  */
3380                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3381                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3382                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3383         }
3384
3385         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3386         if (word == 0xffff) {
3387                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3388                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3389                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3390                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3391                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3392                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3393                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3394                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3395                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3396                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3397                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3398                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3399                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3400                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3401                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3402                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3403                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3404         }
3405
3406         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3407         if ((word & 0x00ff) == 0x00ff) {
3408                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3409                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3410                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3411         }
3412         if ((word & 0xff00) == 0xff00) {
3413                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3414                                    LED_MODE_TXRX_ACTIVITY);
3415                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3416                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3417                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3418                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3419                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3420                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3421         }
3422
3423         /*
3424          * During the LNA validation we are going to use
3425          * lna0 as correct value. Note that EEPROM_LNA
3426          * is never validated.
3427          */
3428         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3429         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3430
3431         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3432         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3433                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3434         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3435                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3436         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3437
3438         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3439         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3440                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3441         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3442             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3443                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3444                                    default_lna_gain);
3445         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3446
3447         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3448         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3449                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3450         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3451                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3452         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3453
3454         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3455         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3456                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3457         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3458             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3459                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3460                                    default_lna_gain);
3461         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3462
3463         return 0;
3464 }
3465 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3466
3467 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3468 {
3469         u32 reg;
3470         u16 value;
3471         u16 eeprom;
3472
3473         /*
3474          * Read EEPROM word for configuration.
3475          */
3476         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3477
3478         /*
3479          * Identify RF chipset by EEPROM value
3480          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3481          * RT53xx: defined in "EEPROM_CHIP_ID" field
3482          */
3483         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3484         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3485                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3486         else
3487                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3488
3489         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3490                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3491
3492         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3493             !rt2x00_rt(rt2x00dev, RT2872) &&
3494             !rt2x00_rt(rt2x00dev, RT2883) &&
3495             !rt2x00_rt(rt2x00dev, RT3070) &&
3496             !rt2x00_rt(rt2x00dev, RT3071) &&
3497             !rt2x00_rt(rt2x00dev, RT3090) &&
3498             !rt2x00_rt(rt2x00dev, RT3390) &&
3499             !rt2x00_rt(rt2x00dev, RT3572) &&
3500             !rt2x00_rt(rt2x00dev, RT5390)) {
3501                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3502                 return -ENODEV;
3503         }
3504
3505         if (!rt2x00_rf(rt2x00dev, RF2820) &&
3506             !rt2x00_rf(rt2x00dev, RF2850) &&
3507             !rt2x00_rf(rt2x00dev, RF2720) &&
3508             !rt2x00_rf(rt2x00dev, RF2750) &&
3509             !rt2x00_rf(rt2x00dev, RF3020) &&
3510             !rt2x00_rf(rt2x00dev, RF2020) &&
3511             !rt2x00_rf(rt2x00dev, RF3021) &&
3512             !rt2x00_rf(rt2x00dev, RF3022) &&
3513             !rt2x00_rf(rt2x00dev, RF3052) &&
3514             !rt2x00_rf(rt2x00dev, RF3320) &&
3515             !rt2x00_rf(rt2x00dev, RF5390)) {
3516                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3517                 return -ENODEV;
3518         }
3519
3520         /*
3521          * Identify default antenna configuration.
3522          */
3523         rt2x00dev->default_ant.tx_chain_num =
3524             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3525         rt2x00dev->default_ant.rx_chain_num =
3526             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3527
3528         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3529
3530         if (rt2x00_rt(rt2x00dev, RT3070) ||
3531             rt2x00_rt(rt2x00dev, RT3090) ||
3532             rt2x00_rt(rt2x00dev, RT3390)) {
3533                 value = rt2x00_get_field16(eeprom,
3534                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3535                 switch (value) {
3536                 case 0:
3537                 case 1:
3538                 case 2:
3539                         rt2x00dev->default_ant.tx = ANTENNA_A;
3540                         rt2x00dev->default_ant.rx = ANTENNA_A;
3541                         break;
3542                 case 3:
3543                         rt2x00dev->default_ant.tx = ANTENNA_A;
3544                         rt2x00dev->default_ant.rx = ANTENNA_B;
3545                         break;
3546                 }
3547         } else {
3548                 rt2x00dev->default_ant.tx = ANTENNA_A;
3549                 rt2x00dev->default_ant.rx = ANTENNA_A;
3550         }
3551
3552         /*
3553          * Read frequency offset and RF programming sequence.
3554          */
3555         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3556         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3557
3558         /*
3559          * Read external LNA informations.
3560          */
3561         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3562
3563         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
3564                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
3565         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3566                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3567
3568         /*
3569          * Detect if this device has an hardware controlled radio.
3570          */
3571         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3572                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3573
3574         /*
3575          * Store led settings, for correct led behaviour.
3576          */
3577 #ifdef CONFIG_RT2X00_LIB_LEDS
3578         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3579         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3580         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3581
3582         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3583 #endif /* CONFIG_RT2X00_LIB_LEDS */
3584
3585         /*
3586          * Check if support EIRP tx power limit feature.
3587          */
3588         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3589
3590         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3591                                         EIRP_MAX_TX_POWER_LIMIT)
3592                 __set_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags);
3593
3594         return 0;
3595 }
3596 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3597
3598 /*
3599  * RF value list for rt28xx
3600  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3601  */
3602 static const struct rf_channel rf_vals[] = {
3603         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3604         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3605         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3606         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3607         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3608         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3609         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3610         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3611         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3612         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3613         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3614         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3615         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3616         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3617
3618         /* 802.11 UNI / HyperLan 2 */
3619         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3620         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3621         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3622         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3623         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3624         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3625         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3626         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3627         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3628         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3629         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3630         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3631
3632         /* 802.11 HyperLan 2 */
3633         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3634         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3635         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3636         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3637         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3638         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3639         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3640         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3641         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3642         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3643         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3644         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3645         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3646         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3647         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3648         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3649
3650         /* 802.11 UNII */
3651         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3652         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3653         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3654         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3655         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3656         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3657         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3658         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3659         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3660         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3661         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3662
3663         /* 802.11 Japan */
3664         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3665         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3666         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3667         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3668         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3669         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3670         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3671 };
3672
3673 /*
3674  * RF value list for rt3xxx
3675  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3676  */
3677 static const struct rf_channel rf_vals_3x[] = {
3678         {1,  241, 2, 2 },
3679         {2,  241, 2, 7 },
3680         {3,  242, 2, 2 },
3681         {4,  242, 2, 7 },
3682         {5,  243, 2, 2 },
3683         {6,  243, 2, 7 },
3684         {7,  244, 2, 2 },
3685         {8,  244, 2, 7 },
3686         {9,  245, 2, 2 },
3687         {10, 245, 2, 7 },
3688         {11, 246, 2, 2 },
3689         {12, 246, 2, 7 },
3690         {13, 247, 2, 2 },
3691         {14, 248, 2, 4 },
3692
3693         /* 802.11 UNI / HyperLan 2 */
3694         {36, 0x56, 0, 4},
3695         {38, 0x56, 0, 6},
3696         {40, 0x56, 0, 8},
3697         {44, 0x57, 0, 0},
3698         {46, 0x57, 0, 2},
3699         {48, 0x57, 0, 4},
3700         {52, 0x57, 0, 8},
3701         {54, 0x57, 0, 10},
3702         {56, 0x58, 0, 0},
3703         {60, 0x58, 0, 4},
3704         {62, 0x58, 0, 6},
3705         {64, 0x58, 0, 8},
3706
3707         /* 802.11 HyperLan 2 */
3708         {100, 0x5b, 0, 8},
3709         {102, 0x5b, 0, 10},
3710         {104, 0x5c, 0, 0},
3711         {108, 0x5c, 0, 4},
3712         {110, 0x5c, 0, 6},
3713         {112, 0x5c, 0, 8},
3714         {116, 0x5d, 0, 0},
3715         {118, 0x5d, 0, 2},
3716         {120, 0x5d, 0, 4},
3717         {124, 0x5d, 0, 8},
3718         {126, 0x5d, 0, 10},
3719         {128, 0x5e, 0, 0},
3720         {132, 0x5e, 0, 4},
3721         {134, 0x5e, 0, 6},
3722         {136, 0x5e, 0, 8},
3723         {140, 0x5f, 0, 0},
3724
3725         /* 802.11 UNII */
3726         {149, 0x5f, 0, 9},
3727         {151, 0x5f, 0, 11},
3728         {153, 0x60, 0, 1},
3729         {157, 0x60, 0, 5},
3730         {159, 0x60, 0, 7},
3731         {161, 0x60, 0, 9},
3732         {165, 0x61, 0, 1},
3733         {167, 0x61, 0, 3},
3734         {169, 0x61, 0, 5},
3735         {171, 0x61, 0, 7},
3736         {173, 0x61, 0, 9},
3737 };
3738
3739 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3740 {
3741         struct hw_mode_spec *spec = &rt2x00dev->spec;
3742         struct channel_info *info;
3743         char *default_power1;
3744         char *default_power2;
3745         unsigned int i;
3746         u16 eeprom;
3747
3748         /*
3749          * Disable powersaving as default on PCI devices.
3750          */
3751         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3752                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3753
3754         /*
3755          * Initialize all hw fields.
3756          */
3757         rt2x00dev->hw->flags =
3758             IEEE80211_HW_SIGNAL_DBM |
3759             IEEE80211_HW_SUPPORTS_PS |
3760             IEEE80211_HW_PS_NULLFUNC_STACK |
3761             IEEE80211_HW_AMPDU_AGGREGATION;
3762         /*
3763          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3764          * unless we are capable of sending the buffered frames out after the
3765          * DTIM transmission using rt2x00lib_beacondone. This will send out
3766          * multicast and broadcast traffic immediately instead of buffering it
3767          * infinitly and thus dropping it after some time.
3768          */
3769         if (!rt2x00_is_usb(rt2x00dev))
3770                 rt2x00dev->hw->flags |=
3771                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
3772
3773         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3774         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3775                                 rt2x00_eeprom_addr(rt2x00dev,
3776                                                    EEPROM_MAC_ADDR_0));
3777
3778         /*
3779          * As rt2800 has a global fallback table we cannot specify
3780          * more then one tx rate per frame but since the hw will
3781          * try several rates (based on the fallback table) we should
3782          * initialize max_report_rates to the maximum number of rates
3783          * we are going to try. Otherwise mac80211 will truncate our
3784          * reported tx rates and the rc algortihm will end up with
3785          * incorrect data.
3786          */
3787         rt2x00dev->hw->max_rates = 1;
3788         rt2x00dev->hw->max_report_rates = 7;
3789         rt2x00dev->hw->max_rate_tries = 1;
3790
3791         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3792
3793         /*
3794          * Initialize hw_mode information.
3795          */
3796         spec->supported_bands = SUPPORT_BAND_2GHZ;
3797         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3798
3799         if (rt2x00_rf(rt2x00dev, RF2820) ||
3800             rt2x00_rf(rt2x00dev, RF2720)) {
3801                 spec->num_channels = 14;
3802                 spec->channels = rf_vals;
3803         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3804                    rt2x00_rf(rt2x00dev, RF2750)) {
3805                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3806                 spec->num_channels = ARRAY_SIZE(rf_vals);
3807                 spec->channels = rf_vals;
3808         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3809                    rt2x00_rf(rt2x00dev, RF2020) ||
3810                    rt2x00_rf(rt2x00dev, RF3021) ||
3811                    rt2x00_rf(rt2x00dev, RF3022) ||
3812                    rt2x00_rf(rt2x00dev, RF3320) ||
3813                    rt2x00_rf(rt2x00dev, RF5390)) {
3814                 spec->num_channels = 14;
3815                 spec->channels = rf_vals_3x;
3816         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3817                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3818                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3819                 spec->channels = rf_vals_3x;
3820         }
3821
3822         /*
3823          * Initialize HT information.
3824          */
3825         if (!rt2x00_rf(rt2x00dev, RF2020))
3826                 spec->ht.ht_supported = true;
3827         else
3828                 spec->ht.ht_supported = false;
3829
3830         spec->ht.cap =
3831             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3832             IEEE80211_HT_CAP_GRN_FLD |
3833             IEEE80211_HT_CAP_SGI_20 |
3834             IEEE80211_HT_CAP_SGI_40;
3835
3836         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
3837                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3838
3839         spec->ht.cap |=
3840             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
3841                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3842
3843         spec->ht.ampdu_factor = 3;
3844         spec->ht.ampdu_density = 4;
3845         spec->ht.mcs.tx_params =
3846             IEEE80211_HT_MCS_TX_DEFINED |
3847             IEEE80211_HT_MCS_TX_RX_DIFF |
3848             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
3849                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3850
3851         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
3852         case 3:
3853                 spec->ht.mcs.rx_mask[2] = 0xff;
3854         case 2:
3855                 spec->ht.mcs.rx_mask[1] = 0xff;
3856         case 1:
3857                 spec->ht.mcs.rx_mask[0] = 0xff;
3858                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3859                 break;
3860         }
3861
3862         /*
3863          * Create channel information array
3864          */
3865         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
3866         if (!info)
3867                 return -ENOMEM;
3868
3869         spec->channels_info = info;
3870
3871         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3872         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3873
3874         for (i = 0; i < 14; i++) {
3875                 info[i].default_power1 = default_power1[i];
3876                 info[i].default_power2 = default_power2[i];
3877         }
3878
3879         if (spec->num_channels > 14) {
3880                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3881                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3882
3883                 for (i = 14; i < spec->num_channels; i++) {
3884                         info[i].default_power1 = default_power1[i];
3885                         info[i].default_power2 = default_power2[i];
3886                 }
3887         }
3888
3889         return 0;
3890 }
3891 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3892
3893 /*
3894  * IEEE80211 stack callback functions.
3895  */
3896 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3897                          u16 *iv16)
3898 {
3899         struct rt2x00_dev *rt2x00dev = hw->priv;
3900         struct mac_iveiv_entry iveiv_entry;
3901         u32 offset;
3902
3903         offset = MAC_IVEIV_ENTRY(hw_key_idx);
3904         rt2800_register_multiread(rt2x00dev, offset,
3905                                       &iveiv_entry, sizeof(iveiv_entry));
3906
3907         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3908         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
3909 }
3910 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
3911
3912 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3913 {
3914         struct rt2x00_dev *rt2x00dev = hw->priv;
3915         u32 reg;
3916         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3917
3918         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3919         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3920         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3921
3922         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3923         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3924         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3925
3926         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3927         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3928         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3929
3930         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3931         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3932         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3933
3934         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3935         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3936         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3937
3938         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3939         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3940         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3941
3942         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3943         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3944         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3945
3946         return 0;
3947 }
3948 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
3949
3950 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3951                    const struct ieee80211_tx_queue_params *params)
3952 {
3953         struct rt2x00_dev *rt2x00dev = hw->priv;
3954         struct data_queue *queue;
3955         struct rt2x00_field32 field;
3956         int retval;
3957         u32 reg;
3958         u32 offset;
3959
3960         /*
3961          * First pass the configuration through rt2x00lib, that will
3962          * update the queue settings and validate the input. After that
3963          * we are free to update the registers based on the value
3964          * in the queue parameter.
3965          */
3966         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3967         if (retval)
3968                 return retval;
3969
3970         /*
3971          * We only need to perform additional register initialization
3972          * for WMM queues/
3973          */
3974         if (queue_idx >= 4)
3975                 return 0;
3976
3977         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
3978
3979         /* Update WMM TXOP register */
3980         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3981         field.bit_offset = (queue_idx & 1) * 16;
3982         field.bit_mask = 0xffff << field.bit_offset;
3983
3984         rt2800_register_read(rt2x00dev, offset, &reg);
3985         rt2x00_set_field32(&reg, field, queue->txop);
3986         rt2800_register_write(rt2x00dev, offset, reg);
3987
3988         /* Update WMM registers */
3989         field.bit_offset = queue_idx * 4;
3990         field.bit_mask = 0xf << field.bit_offset;
3991
3992         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3993         rt2x00_set_field32(&reg, field, queue->aifs);
3994         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3995
3996         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3997         rt2x00_set_field32(&reg, field, queue->cw_min);
3998         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3999
4000         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4001         rt2x00_set_field32(&reg, field, queue->cw_max);
4002         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4003
4004         /* Update EDCA registers */
4005         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4006
4007         rt2800_register_read(rt2x00dev, offset, &reg);
4008         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4009         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4010         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4011         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4012         rt2800_register_write(rt2x00dev, offset, reg);
4013
4014         return 0;
4015 }
4016 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4017
4018 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
4019 {
4020         struct rt2x00_dev *rt2x00dev = hw->priv;
4021         u64 tsf;
4022         u32 reg;
4023
4024         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4025         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4026         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4027         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4028
4029         return tsf;
4030 }
4031 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4032
4033 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4034                         enum ieee80211_ampdu_mlme_action action,
4035                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4036                         u8 buf_size)
4037 {
4038         int ret = 0;
4039
4040         switch (action) {
4041         case IEEE80211_AMPDU_RX_START:
4042         case IEEE80211_AMPDU_RX_STOP:
4043                 /*
4044                  * The hw itself takes care of setting up BlockAck mechanisms.
4045                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4046                  * agreement. Once that is done, the hw will BlockAck incoming
4047                  * AMPDUs without further setup.
4048                  */
4049                 break;
4050         case IEEE80211_AMPDU_TX_START:
4051                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4052                 break;
4053         case IEEE80211_AMPDU_TX_STOP:
4054                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4055                 break;
4056         case IEEE80211_AMPDU_TX_OPERATIONAL:
4057                 break;
4058         default:
4059                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4060         }
4061
4062         return ret;
4063 }
4064 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4065
4066 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4067                       struct survey_info *survey)
4068 {
4069         struct rt2x00_dev *rt2x00dev = hw->priv;
4070         struct ieee80211_conf *conf = &hw->conf;
4071         u32 idle, busy, busy_ext;
4072
4073         if (idx != 0)
4074                 return -ENOENT;
4075
4076         survey->channel = conf->channel;
4077
4078         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4079         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4080         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4081
4082         if (idle || busy) {
4083                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4084                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4085                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4086
4087                 survey->channel_time = (idle + busy) / 1000;
4088                 survey->channel_time_busy = busy / 1000;
4089                 survey->channel_time_ext_busy = busy_ext / 1000;
4090         }
4091
4092         return 0;
4093
4094 }
4095 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4096
4097 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4098 MODULE_VERSION(DRV_VERSION);
4099 MODULE_DESCRIPTION("Ralink RT2800 library");
4100 MODULE_LICENSE("GPL");