rt2x00: Optimize TX descriptor handling
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7         Based on the original rt2800pci.c and rt2800usb.c.
8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14           <http://rt2x00.serialmonkey.com>
15
16         This program is free software; you can redistribute it and/or modify
17         it under the terms of the GNU General Public License as published by
18         the Free Software Foundation; either version 2 of the License, or
19         (at your option) any later version.
20
21         This program is distributed in the hope that it will be useful,
22         but WITHOUT ANY WARRANTY; without even the implied warranty of
23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24         GNU General Public License for more details.
25
26         You should have received a copy of the GNU General Public License
27         along with this program; if not, write to the
28         Free Software Foundation, Inc.,
29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30  */
31
32 /*
33         Module: rt2800lib
34         Abstract: rt2800 generic device routines.
35  */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47  * Register access.
48  * All access to the CSR registers will go through the methods
49  * rt2800_register_read and rt2800_register_write.
50  * BBP and RF register require indirect register access,
51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
52  * These indirect registers work with busy bits,
53  * and we will try maximal REGISTER_BUSY_COUNT times to access
54  * the register while taking a REGISTER_BUSY_DELAY us delay
55  * between each attampt. When the busy bit is still set at that time,
56  * the access attempt is considered to have failed,
57  * and we will print an error.
58  * The _lock versions must be used if you already hold the csr_mutex
59  */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68                             H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72         /* check for rt2872 on SoC */
73         if (!rt2x00_is_soc(rt2x00dev) ||
74             !rt2x00_rt(rt2x00dev, RT2872))
75                 return false;
76
77         /* we know for sure that these rf chipsets are used on rt305x boards */
78         if (rt2x00_rf(rt2x00dev, RF3020) ||
79             rt2x00_rf(rt2x00dev, RF3021) ||
80             rt2x00_rf(rt2x00dev, RF3022))
81                 return true;
82
83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84         return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88                              const unsigned int word, const u8 value)
89 {
90         u32 reg;
91
92         mutex_lock(&rt2x00dev->csr_mutex);
93
94         /*
95          * Wait until the BBP becomes available, afterwards we
96          * can safely write the new data into the register.
97          */
98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99                 reg = 0;
100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107         }
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113                             const unsigned int word, u8 *value)
114 {
115         u32 reg;
116
117         mutex_lock(&rt2x00dev->csr_mutex);
118
119         /*
120          * Wait until the BBP becomes available, afterwards we
121          * can safely write the read request into the register.
122          * After the data has been written, we wait until hardware
123          * returns the correct value, if at any time the register
124          * doesn't become available in time, reg will be 0xffffffff
125          * which means we return 0xff to the caller.
126          */
127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128                 reg = 0;
129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136                 WAIT_FOR_BBP(rt2x00dev, &reg);
137         }
138
139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141         mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145                                const unsigned int word, const u8 value)
146 {
147         u32 reg;
148
149         mutex_lock(&rt2x00dev->csr_mutex);
150
151         /*
152          * Wait until the RFCSR becomes available, afterwards we
153          * can safely write the new data into the register.
154          */
155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156                 reg = 0;
157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163         }
164
165         mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169                               const unsigned int word, u8 *value)
170 {
171         u32 reg;
172
173         mutex_lock(&rt2x00dev->csr_mutex);
174
175         /*
176          * Wait until the RFCSR becomes available, afterwards we
177          * can safely write the read request into the register.
178          * After the data has been written, we wait until hardware
179          * returns the correct value, if at any time the register
180          * doesn't become available in time, reg will be 0xffffffff
181          * which means we return 0xff to the caller.
182          */
183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184                 reg = 0;
185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192         }
193
194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196         mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200                             const unsigned int word, const u32 value)
201 {
202         u32 reg;
203
204         mutex_lock(&rt2x00dev->csr_mutex);
205
206         /*
207          * Wait until the RF becomes available, afterwards we
208          * can safely write the new data into the register.
209          */
210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211                 reg = 0;
212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218                 rt2x00_rf_write(rt2x00dev, word, value);
219         }
220
221         mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225                         const u8 command, const u8 token,
226                         const u8 arg0, const u8 arg1)
227 {
228         u32 reg;
229
230         /*
231          * SOC devices don't support MCU requests.
232          */
233         if (rt2x00_is_soc(rt2x00dev))
234                 return;
235
236         mutex_lock(&rt2x00dev->csr_mutex);
237
238         /*
239          * Wait until the MCU becomes available, afterwards we
240          * can safely write the new data into the register.
241          */
242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249                 reg = 0;
250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252         }
253
254         mutex_unlock(&rt2x00dev->csr_mutex);
255 }
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
257
258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259 {
260         unsigned int i = 0;
261         u32 reg;
262
263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265                 if (reg && reg != ~0)
266                         return 0;
267                 msleep(1);
268         }
269
270         ERROR(rt2x00dev, "Unstable hardware.\n");
271         return -EBUSY;
272 }
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276 {
277         unsigned int i;
278         u32 reg;
279
280         /*
281          * Some devices are really slow to respond here. Wait a whole second
282          * before timing out.
283          */
284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288                         return 0;
289
290                 msleep(10);
291         }
292
293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294         return -EACCES;
295 }
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299 {
300         u16 fw_crc;
301         u16 crc;
302
303         /*
304          * The last 2 bytes in the firmware array are the crc checksum itself,
305          * this means that we should never pass those 2 bytes to the crc
306          * algorithm.
307          */
308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310         /*
311          * Use the crc ccitt algorithm.
312          * This will return the same value as the legacy driver which
313          * used bit ordering reversion on the both the firmware bytes
314          * before input input as well as on the final output.
315          * Obviously using crc ccitt directly is much more efficient.
316          */
317         crc = crc_ccitt(~0, data, len - 2);
318
319         /*
320          * There is a small difference between the crc-itu-t + bitrev and
321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
322          * will be swapped, use swab16 to convert the crc to the correct
323          * value.
324          */
325         crc = swab16(crc);
326
327         return fw_crc == crc;
328 }
329
330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331                           const u8 *data, const size_t len)
332 {
333         size_t offset = 0;
334         size_t fw_len;
335         bool multiple;
336
337         /*
338          * PCI(e) & SOC devices require firmware with a length
339          * of 8kb. USB devices require firmware files with a length
340          * of 4kb. Certain USB chipsets however require different firmware,
341          * which Ralink only provides attached to the original firmware
342          * file. Thus for USB devices, firmware files have a length
343          * which is a multiple of 4kb.
344          */
345         if (rt2x00_is_usb(rt2x00dev)) {
346                 fw_len = 4096;
347                 multiple = true;
348         } else {
349                 fw_len = 8192;
350                 multiple = true;
351         }
352
353         /*
354          * Validate the firmware length
355          */
356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
357                 return FW_BAD_LENGTH;
358
359         /*
360          * Check if the chipset requires one of the upper parts
361          * of the firmware.
362          */
363         if (rt2x00_is_usb(rt2x00dev) &&
364             !rt2x00_rt(rt2x00dev, RT2860) &&
365             !rt2x00_rt(rt2x00dev, RT2872) &&
366             !rt2x00_rt(rt2x00dev, RT3070) &&
367             ((len / fw_len) == 1))
368                 return FW_BAD_VERSION;
369
370         /*
371          * 8kb firmware files must be checked as if it were
372          * 2 separate firmware files.
373          */
374         while (offset < len) {
375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376                         return FW_BAD_CRC;
377
378                 offset += fw_len;
379         }
380
381         return FW_OK;
382 }
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386                          const u8 *data, const size_t len)
387 {
388         unsigned int i;
389         u32 reg;
390
391         /*
392          * If driver doesn't wake up firmware here,
393          * rt2800_load_firmware will hang forever when interface is up again.
394          */
395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
396
397         /*
398          * Wait for stable hardware.
399          */
400         if (rt2800_wait_csr_ready(rt2x00dev))
401                 return -EBUSY;
402
403         if (rt2x00_is_pci(rt2x00dev)) {
404                 if (rt2x00_rt(rt2x00dev, RT5390)) {
405                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
406                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
407                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
408                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
409                 }
410                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
411         }
412
413         /*
414          * Disable DMA, will be reenabled later when enabling
415          * the radio.
416          */
417         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
418         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
419         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
420         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
421         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
422         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
423         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
424
425         /*
426          * Write firmware to the device.
427          */
428         rt2800_drv_write_firmware(rt2x00dev, data, len);
429
430         /*
431          * Wait for device to stabilize.
432          */
433         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
434                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
435                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
436                         break;
437                 msleep(1);
438         }
439
440         if (i == REGISTER_BUSY_COUNT) {
441                 ERROR(rt2x00dev, "PBF system register not ready.\n");
442                 return -EBUSY;
443         }
444
445         /*
446          * Initialize firmware.
447          */
448         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
449         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
450         msleep(1);
451
452         return 0;
453 }
454 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
455
456 void rt2800_write_tx_data(struct queue_entry *entry,
457                           struct txentry_desc *txdesc)
458 {
459         __le32 *txwi = rt2800_drv_get_txwi(entry);
460         u32 word;
461
462         /*
463          * Initialize TX Info descriptor
464          */
465         rt2x00_desc_read(txwi, 0, &word);
466         rt2x00_set_field32(&word, TXWI_W0_FRAG,
467                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
468         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
469                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
470         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
471         rt2x00_set_field32(&word, TXWI_W0_TS,
472                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
473         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
474                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
475         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
476                            txdesc->u.ht.mpdu_density);
477         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
478         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
479         rt2x00_set_field32(&word, TXWI_W0_BW,
480                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
481         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
482                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
483         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
484         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
485         rt2x00_desc_write(txwi, 0, word);
486
487         rt2x00_desc_read(txwi, 1, &word);
488         rt2x00_set_field32(&word, TXWI_W1_ACK,
489                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
490         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
491                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
492         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
493         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
494                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
495                            txdesc->key_idx : 0xff);
496         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
497                            txdesc->length);
498         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
499         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
500         rt2x00_desc_write(txwi, 1, word);
501
502         /*
503          * Always write 0 to IV/EIV fields, hardware will insert the IV
504          * from the IVEIV register when TXD_W3_WIV is set to 0.
505          * When TXD_W3_WIV is set to 1 it will use the IV data
506          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
507          * crypto entry in the registers should be used to encrypt the frame.
508          */
509         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
510         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
511 }
512 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
513
514 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
515 {
516         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
517         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
518         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
519         u16 eeprom;
520         u8 offset0;
521         u8 offset1;
522         u8 offset2;
523
524         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
525                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
526                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
527                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
528                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
529                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
530         } else {
531                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
532                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
533                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
534                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
535                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
536         }
537
538         /*
539          * Convert the value from the descriptor into the RSSI value
540          * If the value in the descriptor is 0, it is considered invalid
541          * and the default (extremely low) rssi value is assumed
542          */
543         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
544         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
545         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
546
547         /*
548          * mac80211 only accepts a single RSSI value. Calculating the
549          * average doesn't deliver a fair answer either since -60:-60 would
550          * be considered equally good as -50:-70 while the second is the one
551          * which gives less energy...
552          */
553         rssi0 = max(rssi0, rssi1);
554         return max(rssi0, rssi2);
555 }
556
557 void rt2800_process_rxwi(struct queue_entry *entry,
558                          struct rxdone_entry_desc *rxdesc)
559 {
560         __le32 *rxwi = (__le32 *) entry->skb->data;
561         u32 word;
562
563         rt2x00_desc_read(rxwi, 0, &word);
564
565         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
566         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
567
568         rt2x00_desc_read(rxwi, 1, &word);
569
570         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
571                 rxdesc->flags |= RX_FLAG_SHORT_GI;
572
573         if (rt2x00_get_field32(word, RXWI_W1_BW))
574                 rxdesc->flags |= RX_FLAG_40MHZ;
575
576         /*
577          * Detect RX rate, always use MCS as signal type.
578          */
579         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
580         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
581         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
582
583         /*
584          * Mask of 0x8 bit to remove the short preamble flag.
585          */
586         if (rxdesc->rate_mode == RATE_MODE_CCK)
587                 rxdesc->signal &= ~0x8;
588
589         rt2x00_desc_read(rxwi, 2, &word);
590
591         /*
592          * Convert descriptor AGC value to RSSI value.
593          */
594         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
595
596         /*
597          * Remove RXWI descriptor from start of buffer.
598          */
599         skb_pull(entry->skb, RXWI_DESC_SIZE);
600 }
601 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
602
603 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
604 {
605         __le32 *txwi;
606         u32 word;
607         int wcid, ack, pid;
608         int tx_wcid, tx_ack, tx_pid;
609
610         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
611         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
612         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
613
614         /*
615          * This frames has returned with an IO error,
616          * so the status report is not intended for this
617          * frame.
618          */
619         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
620                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
621                 return false;
622         }
623
624         /*
625          * Validate if this TX status report is intended for
626          * this entry by comparing the WCID/ACK/PID fields.
627          */
628         txwi = rt2800_drv_get_txwi(entry);
629
630         rt2x00_desc_read(txwi, 1, &word);
631         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
632         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
633         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
634
635         if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
636                 WARNING(entry->queue->rt2x00dev,
637                         "TX status report missed for queue %d entry %d\n",
638                 entry->queue->qid, entry->entry_idx);
639                 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
640                 return false;
641         }
642
643         return true;
644 }
645
646 void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
647 {
648         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
649         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
650         struct txdone_entry_desc txdesc;
651         u32 word;
652         u16 mcs, real_mcs;
653         int aggr, ampdu;
654         __le32 *txwi;
655
656         /*
657          * Obtain the status about this packet.
658          */
659         txdesc.flags = 0;
660         txwi = rt2800_drv_get_txwi(entry);
661         rt2x00_desc_read(txwi, 0, &word);
662
663         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
664         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
665
666         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
667         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
668
669         /*
670          * If a frame was meant to be sent as a single non-aggregated MPDU
671          * but ended up in an aggregate the used tx rate doesn't correlate
672          * with the one specified in the TXWI as the whole aggregate is sent
673          * with the same rate.
674          *
675          * For example: two frames are sent to rt2x00, the first one sets
676          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
677          * and requests MCS15. If the hw aggregates both frames into one
678          * AMDPU the tx status for both frames will contain MCS7 although
679          * the frame was sent successfully.
680          *
681          * Hence, replace the requested rate with the real tx rate to not
682          * confuse the rate control algortihm by providing clearly wrong
683          * data.
684          */
685         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
686                 skbdesc->tx_rate_idx = real_mcs;
687                 mcs = real_mcs;
688         }
689
690         /*
691          * Ralink has a retry mechanism using a global fallback
692          * table. We setup this fallback table to try the immediate
693          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
694          * always contains the MCS used for the last transmission, be
695          * it successful or not.
696          */
697         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
698                 /*
699                  * Transmission succeeded. The number of retries is
700                  * mcs - real_mcs
701                  */
702                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
703                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
704         } else {
705                 /*
706                  * Transmission failed. The number of retries is
707                  * always 7 in this case (for a total number of 8
708                  * frames sent).
709                  */
710                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
711                 txdesc.retry = rt2x00dev->long_retry;
712         }
713
714         /*
715          * the frame was retried at least once
716          * -> hw used fallback rates
717          */
718         if (txdesc.retry)
719                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
720
721         rt2x00lib_txdone(entry, &txdesc);
722 }
723 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
724
725 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
726 {
727         struct data_queue *queue;
728         struct queue_entry *entry;
729         u32 reg;
730         u8 pid;
731         int i;
732
733         /*
734          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
735          * at most X times and also stop processing once the TX_STA_FIFO_VALID
736          * flag is not set anymore.
737          *
738          * The legacy drivers use X=TX_RING_SIZE but state in a comment
739          * that the TX_STA_FIFO stack has a size of 16. We stick to our
740          * tx ring size for now.
741          */
742         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
743                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
744                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
745                         break;
746
747                 /*
748                  * Skip this entry when it contains an invalid
749                  * queue identication number.
750                  */
751                 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
752                 if (pid >= QID_RX)
753                         continue;
754
755                 queue = rt2x00queue_get_tx_queue(rt2x00dev, pid);
756                 if (unlikely(!queue))
757                         continue;
758
759                 /*
760                  * Inside each queue, we process each entry in a chronological
761                  * order. We first check that the queue is not empty.
762                  */
763                 entry = NULL;
764                 while (!rt2x00queue_empty(queue)) {
765                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
766                         if (rt2800_txdone_entry_check(entry, reg))
767                                 break;
768                 }
769
770                 if (!entry || rt2x00queue_empty(queue))
771                         break;
772
773                 rt2800_txdone_entry(entry, reg);
774         }
775 }
776 EXPORT_SYMBOL_GPL(rt2800_txdone);
777
778 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
779 {
780         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
781         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
782         unsigned int beacon_base;
783         unsigned int padding_len;
784         u32 orig_reg, reg;
785
786         /*
787          * Disable beaconing while we are reloading the beacon data,
788          * otherwise we might be sending out invalid data.
789          */
790         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
791         orig_reg = reg;
792         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
793         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
794
795         /*
796          * Add space for the TXWI in front of the skb.
797          */
798         skb_push(entry->skb, TXWI_DESC_SIZE);
799         memset(entry->skb, 0, TXWI_DESC_SIZE);
800
801         /*
802          * Register descriptor details in skb frame descriptor.
803          */
804         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
805         skbdesc->desc = entry->skb->data;
806         skbdesc->desc_len = TXWI_DESC_SIZE;
807
808         /*
809          * Add the TXWI for the beacon to the skb.
810          */
811         rt2800_write_tx_data(entry, txdesc);
812
813         /*
814          * Dump beacon to userspace through debugfs.
815          */
816         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
817
818         /*
819          * Write entire beacon with TXWI and padding to register.
820          */
821         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
822         if (padding_len && skb_pad(entry->skb, padding_len)) {
823                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
824                 /* skb freed by skb_pad() on failure */
825                 entry->skb = NULL;
826                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
827                 return;
828         }
829
830         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
831         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
832                                    entry->skb->len + padding_len);
833
834         /*
835          * Enable beaconing again.
836          */
837         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
838         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
839
840         /*
841          * Clean up beacon skb.
842          */
843         dev_kfree_skb_any(entry->skb);
844         entry->skb = NULL;
845 }
846 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
847
848 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
849                                                 unsigned int beacon_base)
850 {
851         int i;
852
853         /*
854          * For the Beacon base registers we only need to clear
855          * the whole TXWI which (when set to 0) will invalidate
856          * the entire beacon.
857          */
858         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
859                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
860 }
861
862 void rt2800_clear_beacon(struct queue_entry *entry)
863 {
864         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
865         u32 reg;
866
867         /*
868          * Disable beaconing while we are reloading the beacon data,
869          * otherwise we might be sending out invalid data.
870          */
871         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
872         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
873         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
874
875         /*
876          * Clear beacon.
877          */
878         rt2800_clear_beacon_register(rt2x00dev,
879                                      HW_BEACON_OFFSET(entry->entry_idx));
880
881         /*
882          * Enabled beaconing again.
883          */
884         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
885         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
886 }
887 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
888
889 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
890 const struct rt2x00debug rt2800_rt2x00debug = {
891         .owner  = THIS_MODULE,
892         .csr    = {
893                 .read           = rt2800_register_read,
894                 .write          = rt2800_register_write,
895                 .flags          = RT2X00DEBUGFS_OFFSET,
896                 .word_base      = CSR_REG_BASE,
897                 .word_size      = sizeof(u32),
898                 .word_count     = CSR_REG_SIZE / sizeof(u32),
899         },
900         .eeprom = {
901                 .read           = rt2x00_eeprom_read,
902                 .write          = rt2x00_eeprom_write,
903                 .word_base      = EEPROM_BASE,
904                 .word_size      = sizeof(u16),
905                 .word_count     = EEPROM_SIZE / sizeof(u16),
906         },
907         .bbp    = {
908                 .read           = rt2800_bbp_read,
909                 .write          = rt2800_bbp_write,
910                 .word_base      = BBP_BASE,
911                 .word_size      = sizeof(u8),
912                 .word_count     = BBP_SIZE / sizeof(u8),
913         },
914         .rf     = {
915                 .read           = rt2x00_rf_read,
916                 .write          = rt2800_rf_write,
917                 .word_base      = RF_BASE,
918                 .word_size      = sizeof(u32),
919                 .word_count     = RF_SIZE / sizeof(u32),
920         },
921 };
922 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
923 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
924
925 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
926 {
927         u32 reg;
928
929         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
930         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
931 }
932 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
933
934 #ifdef CONFIG_RT2X00_LIB_LEDS
935 static void rt2800_brightness_set(struct led_classdev *led_cdev,
936                                   enum led_brightness brightness)
937 {
938         struct rt2x00_led *led =
939             container_of(led_cdev, struct rt2x00_led, led_dev);
940         unsigned int enabled = brightness != LED_OFF;
941         unsigned int bg_mode =
942             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
943         unsigned int polarity =
944                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
945                                    EEPROM_FREQ_LED_POLARITY);
946         unsigned int ledmode =
947                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
948                                    EEPROM_FREQ_LED_MODE);
949
950         if (led->type == LED_TYPE_RADIO) {
951                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
952                                       enabled ? 0x20 : 0);
953         } else if (led->type == LED_TYPE_ASSOC) {
954                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
955                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
956         } else if (led->type == LED_TYPE_QUALITY) {
957                 /*
958                  * The brightness is divided into 6 levels (0 - 5),
959                  * The specs tell us the following levels:
960                  *      0, 1 ,3, 7, 15, 31
961                  * to determine the level in a simple way we can simply
962                  * work with bitshifting:
963                  *      (1 << level) - 1
964                  */
965                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
966                                       (1 << brightness / (LED_FULL / 6)) - 1,
967                                       polarity);
968         }
969 }
970
971 static int rt2800_blink_set(struct led_classdev *led_cdev,
972                             unsigned long *delay_on, unsigned long *delay_off)
973 {
974         struct rt2x00_led *led =
975             container_of(led_cdev, struct rt2x00_led, led_dev);
976         u32 reg;
977
978         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
979         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
980         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
981         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
982
983         return 0;
984 }
985
986 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
987                      struct rt2x00_led *led, enum led_type type)
988 {
989         led->rt2x00dev = rt2x00dev;
990         led->type = type;
991         led->led_dev.brightness_set = rt2800_brightness_set;
992         led->led_dev.blink_set = rt2800_blink_set;
993         led->flags = LED_INITIALIZED;
994 }
995 #endif /* CONFIG_RT2X00_LIB_LEDS */
996
997 /*
998  * Configuration handlers.
999  */
1000 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
1001                                     struct rt2x00lib_crypto *crypto,
1002                                     struct ieee80211_key_conf *key)
1003 {
1004         struct mac_wcid_entry wcid_entry;
1005         struct mac_iveiv_entry iveiv_entry;
1006         u32 offset;
1007         u32 reg;
1008
1009         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1010
1011         if (crypto->cmd == SET_KEY) {
1012                 rt2800_register_read(rt2x00dev, offset, &reg);
1013                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1014                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1015                 /*
1016                  * Both the cipher as the BSS Idx numbers are split in a main
1017                  * value of 3 bits, and a extended field for adding one additional
1018                  * bit to the value.
1019                  */
1020                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1021                                    (crypto->cipher & 0x7));
1022                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1023                                    (crypto->cipher & 0x8) >> 3);
1024                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
1025                                    (crypto->bssidx & 0x7));
1026                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1027                                    (crypto->bssidx & 0x8) >> 3);
1028                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1029                 rt2800_register_write(rt2x00dev, offset, reg);
1030         } else {
1031                 rt2800_register_write(rt2x00dev, offset, 0);
1032         }
1033
1034         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1035
1036         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1037         if ((crypto->cipher == CIPHER_TKIP) ||
1038             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1039             (crypto->cipher == CIPHER_AES))
1040                 iveiv_entry.iv[3] |= 0x20;
1041         iveiv_entry.iv[3] |= key->keyidx << 6;
1042         rt2800_register_multiwrite(rt2x00dev, offset,
1043                                       &iveiv_entry, sizeof(iveiv_entry));
1044
1045         offset = MAC_WCID_ENTRY(key->hw_key_idx);
1046
1047         memset(&wcid_entry, 0, sizeof(wcid_entry));
1048         if (crypto->cmd == SET_KEY)
1049                 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
1050         rt2800_register_multiwrite(rt2x00dev, offset,
1051                                       &wcid_entry, sizeof(wcid_entry));
1052 }
1053
1054 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1055                              struct rt2x00lib_crypto *crypto,
1056                              struct ieee80211_key_conf *key)
1057 {
1058         struct hw_key_entry key_entry;
1059         struct rt2x00_field32 field;
1060         u32 offset;
1061         u32 reg;
1062
1063         if (crypto->cmd == SET_KEY) {
1064                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1065
1066                 memcpy(key_entry.key, crypto->key,
1067                        sizeof(key_entry.key));
1068                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1069                        sizeof(key_entry.tx_mic));
1070                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1071                        sizeof(key_entry.rx_mic));
1072
1073                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1074                 rt2800_register_multiwrite(rt2x00dev, offset,
1075                                               &key_entry, sizeof(key_entry));
1076         }
1077
1078         /*
1079          * The cipher types are stored over multiple registers
1080          * starting with SHARED_KEY_MODE_BASE each word will have
1081          * 32 bits and contains the cipher types for 2 bssidx each.
1082          * Using the correct defines correctly will cause overhead,
1083          * so just calculate the correct offset.
1084          */
1085         field.bit_offset = 4 * (key->hw_key_idx % 8);
1086         field.bit_mask = 0x7 << field.bit_offset;
1087
1088         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1089
1090         rt2800_register_read(rt2x00dev, offset, &reg);
1091         rt2x00_set_field32(&reg, field,
1092                            (crypto->cmd == SET_KEY) * crypto->cipher);
1093         rt2800_register_write(rt2x00dev, offset, reg);
1094
1095         /*
1096          * Update WCID information
1097          */
1098         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1099
1100         return 0;
1101 }
1102 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1103
1104 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1105                                struct rt2x00lib_crypto *crypto,
1106                                struct ieee80211_key_conf *key)
1107 {
1108         struct hw_key_entry key_entry;
1109         u32 offset;
1110
1111         if (crypto->cmd == SET_KEY) {
1112                 /*
1113                  * 1 pairwise key is possible per AID, this means that the AID
1114                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
1115                  * last possible shared key entry.
1116                  *
1117                  * Since parts of the pairwise key table might be shared with
1118                  * the beacon frame buffers 6 & 7 we should only write into the
1119                  * first 222 entries.
1120                  */
1121                 if (crypto->aid > (222 - 32))
1122                         return -ENOSPC;
1123
1124                 key->hw_key_idx = 32 + crypto->aid;
1125
1126                 memcpy(key_entry.key, crypto->key,
1127                        sizeof(key_entry.key));
1128                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1129                        sizeof(key_entry.tx_mic));
1130                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1131                        sizeof(key_entry.rx_mic));
1132
1133                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1134                 rt2800_register_multiwrite(rt2x00dev, offset,
1135                                               &key_entry, sizeof(key_entry));
1136         }
1137
1138         /*
1139          * Update WCID information
1140          */
1141         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1142
1143         return 0;
1144 }
1145 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1146
1147 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1148                           const unsigned int filter_flags)
1149 {
1150         u32 reg;
1151
1152         /*
1153          * Start configuration steps.
1154          * Note that the version error will always be dropped
1155          * and broadcast frames will always be accepted since
1156          * there is no filter for it at this time.
1157          */
1158         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1159         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1160                            !(filter_flags & FIF_FCSFAIL));
1161         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1162                            !(filter_flags & FIF_PLCPFAIL));
1163         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1164                            !(filter_flags & FIF_PROMISC_IN_BSS));
1165         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1166         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1167         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1168                            !(filter_flags & FIF_ALLMULTI));
1169         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1170         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1171         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1172                            !(filter_flags & FIF_CONTROL));
1173         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1174                            !(filter_flags & FIF_CONTROL));
1175         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1176                            !(filter_flags & FIF_CONTROL));
1177         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1178                            !(filter_flags & FIF_CONTROL));
1179         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1180                            !(filter_flags & FIF_CONTROL));
1181         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1182                            !(filter_flags & FIF_PSPOLL));
1183         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1184         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1185         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1186                            !(filter_flags & FIF_CONTROL));
1187         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1188 }
1189 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1190
1191 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1192                         struct rt2x00intf_conf *conf, const unsigned int flags)
1193 {
1194         u32 reg;
1195         bool update_bssid = false;
1196
1197         if (flags & CONFIG_UPDATE_TYPE) {
1198                 /*
1199                  * Enable synchronisation.
1200                  */
1201                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1202                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1203                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1204         }
1205
1206         if (flags & CONFIG_UPDATE_MAC) {
1207                 if (flags & CONFIG_UPDATE_TYPE &&
1208                     conf->sync == TSF_SYNC_AP_NONE) {
1209                         /*
1210                          * The BSSID register has to be set to our own mac
1211                          * address in AP mode.
1212                          */
1213                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1214                         update_bssid = true;
1215                 }
1216
1217                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1218                         reg = le32_to_cpu(conf->mac[1]);
1219                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1220                         conf->mac[1] = cpu_to_le32(reg);
1221                 }
1222
1223                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1224                                               conf->mac, sizeof(conf->mac));
1225         }
1226
1227         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1228                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1229                         reg = le32_to_cpu(conf->bssid[1]);
1230                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1231                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1232                         conf->bssid[1] = cpu_to_le32(reg);
1233                 }
1234
1235                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1236                                               conf->bssid, sizeof(conf->bssid));
1237         }
1238 }
1239 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1240
1241 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1242                                     struct rt2x00lib_erp *erp)
1243 {
1244         bool any_sta_nongf = !!(erp->ht_opmode &
1245                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1246         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1247         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1248         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1249         u32 reg;
1250
1251         /* default protection rate for HT20: OFDM 24M */
1252         mm20_rate = gf20_rate = 0x4004;
1253
1254         /* default protection rate for HT40: duplicate OFDM 24M */
1255         mm40_rate = gf40_rate = 0x4084;
1256
1257         switch (protection) {
1258         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1259                 /*
1260                  * All STAs in this BSS are HT20/40 but there might be
1261                  * STAs not supporting greenfield mode.
1262                  * => Disable protection for HT transmissions.
1263                  */
1264                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1265
1266                 break;
1267         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1268                 /*
1269                  * All STAs in this BSS are HT20 or HT20/40 but there
1270                  * might be STAs not supporting greenfield mode.
1271                  * => Protect all HT40 transmissions.
1272                  */
1273                 mm20_mode = gf20_mode = 0;
1274                 mm40_mode = gf40_mode = 2;
1275
1276                 break;
1277         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1278                 /*
1279                  * Nonmember protection:
1280                  * According to 802.11n we _should_ protect all
1281                  * HT transmissions (but we don't have to).
1282                  *
1283                  * But if cts_protection is enabled we _shall_ protect
1284                  * all HT transmissions using a CCK rate.
1285                  *
1286                  * And if any station is non GF we _shall_ protect
1287                  * GF transmissions.
1288                  *
1289                  * We decide to protect everything
1290                  * -> fall through to mixed mode.
1291                  */
1292         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1293                 /*
1294                  * Legacy STAs are present
1295                  * => Protect all HT transmissions.
1296                  */
1297                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1298
1299                 /*
1300                  * If erp protection is needed we have to protect HT
1301                  * transmissions with CCK 11M long preamble.
1302                  */
1303                 if (erp->cts_protection) {
1304                         /* don't duplicate RTS/CTS in CCK mode */
1305                         mm20_rate = mm40_rate = 0x0003;
1306                         gf20_rate = gf40_rate = 0x0003;
1307                 }
1308                 break;
1309         };
1310
1311         /* check for STAs not supporting greenfield mode */
1312         if (any_sta_nongf)
1313                 gf20_mode = gf40_mode = 2;
1314
1315         /* Update HT protection config */
1316         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1317         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1318         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1319         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1320
1321         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1322         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1323         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1324         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1325
1326         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1327         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1328         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1329         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1330
1331         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1332         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1333         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1334         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1335 }
1336
1337 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1338                        u32 changed)
1339 {
1340         u32 reg;
1341
1342         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1343                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1344                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1345                                    !!erp->short_preamble);
1346                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1347                                    !!erp->short_preamble);
1348                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1349         }
1350
1351         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1352                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1353                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1354                                    erp->cts_protection ? 2 : 0);
1355                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1356         }
1357
1358         if (changed & BSS_CHANGED_BASIC_RATES) {
1359                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1360                                          erp->basic_rates);
1361                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1362         }
1363
1364         if (changed & BSS_CHANGED_ERP_SLOT) {
1365                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1366                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1367                                    erp->slot_time);
1368                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1369
1370                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1371                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1372                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1373         }
1374
1375         if (changed & BSS_CHANGED_BEACON_INT) {
1376                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1377                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1378                                    erp->beacon_int * 16);
1379                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1380         }
1381
1382         if (changed & BSS_CHANGED_HT)
1383                 rt2800_config_ht_opmode(rt2x00dev, erp);
1384 }
1385 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1386
1387 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1388                                      enum antenna ant)
1389 {
1390         u32 reg;
1391         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1392         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1393
1394         if (rt2x00_is_pci(rt2x00dev)) {
1395                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1396                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1397                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1398         } else if (rt2x00_is_usb(rt2x00dev))
1399                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1400                                    eesk_pin, 0);
1401
1402         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1403         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1404         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1405         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1406 }
1407
1408 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1409 {
1410         u8 r1;
1411         u8 r3;
1412         u16 eeprom;
1413
1414         rt2800_bbp_read(rt2x00dev, 1, &r1);
1415         rt2800_bbp_read(rt2x00dev, 3, &r3);
1416
1417         /*
1418          * Configure the TX antenna.
1419          */
1420         switch (ant->tx_chain_num) {
1421         case 1:
1422                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1423                 break;
1424         case 2:
1425                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1426                 break;
1427         case 3:
1428                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1429                 break;
1430         }
1431
1432         /*
1433          * Configure the RX antenna.
1434          */
1435         switch (ant->rx_chain_num) {
1436         case 1:
1437                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1438                     rt2x00_rt(rt2x00dev, RT3090) ||
1439                     rt2x00_rt(rt2x00dev, RT3390)) {
1440                         rt2x00_eeprom_read(rt2x00dev,
1441                                            EEPROM_NIC_CONF1, &eeprom);
1442                         if (rt2x00_get_field16(eeprom,
1443                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1444                                 rt2800_set_ant_diversity(rt2x00dev,
1445                                                 rt2x00dev->default_ant.rx);
1446                 }
1447                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1448                 break;
1449         case 2:
1450                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1451                 break;
1452         case 3:
1453                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1454                 break;
1455         }
1456
1457         rt2800_bbp_write(rt2x00dev, 3, r3);
1458         rt2800_bbp_write(rt2x00dev, 1, r1);
1459 }
1460 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1461
1462 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1463                                    struct rt2x00lib_conf *libconf)
1464 {
1465         u16 eeprom;
1466         short lna_gain;
1467
1468         if (libconf->rf.channel <= 14) {
1469                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1470                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1471         } else if (libconf->rf.channel <= 64) {
1472                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1473                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1474         } else if (libconf->rf.channel <= 128) {
1475                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1476                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1477         } else {
1478                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1479                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1480         }
1481
1482         rt2x00dev->lna_gain = lna_gain;
1483 }
1484
1485 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1486                                          struct ieee80211_conf *conf,
1487                                          struct rf_channel *rf,
1488                                          struct channel_info *info)
1489 {
1490         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1491
1492         if (rt2x00dev->default_ant.tx_chain_num == 1)
1493                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1494
1495         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1496                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1497                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1498         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1499                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1500
1501         if (rf->channel > 14) {
1502                 /*
1503                  * When TX power is below 0, we should increase it by 7 to
1504                  * make it a positive value (Minumum value is -7).
1505                  * However this means that values between 0 and 7 have
1506                  * double meaning, and we should set a 7DBm boost flag.
1507                  */
1508                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1509                                    (info->default_power1 >= 0));
1510
1511                 if (info->default_power1 < 0)
1512                         info->default_power1 += 7;
1513
1514                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1515
1516                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1517                                    (info->default_power2 >= 0));
1518
1519                 if (info->default_power2 < 0)
1520                         info->default_power2 += 7;
1521
1522                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1523         } else {
1524                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1525                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1526         }
1527
1528         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1529
1530         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1531         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1532         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1533         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1534
1535         udelay(200);
1536
1537         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1538         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1539         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1540         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1541
1542         udelay(200);
1543
1544         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1545         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1546         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1547         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1548 }
1549
1550 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1551                                          struct ieee80211_conf *conf,
1552                                          struct rf_channel *rf,
1553                                          struct channel_info *info)
1554 {
1555         u8 rfcsr;
1556
1557         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1558         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1559
1560         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1561         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1562         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1563
1564         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1565         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1566         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1567
1568         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1569         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1570         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1571
1572         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1573         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1574         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1575
1576         rt2800_rfcsr_write(rt2x00dev, 24,
1577                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1578
1579         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1580         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1581         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1582 }
1583
1584
1585 #define RT5390_POWER_BOUND     0x27
1586 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1587
1588 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1589                                          struct ieee80211_conf *conf,
1590                                          struct rf_channel *rf,
1591                                          struct channel_info *info)
1592 {
1593         u8 rfcsr;
1594         u16 eeprom;
1595
1596         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1597         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1598         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1599         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1600         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1601
1602         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1603         if (info->default_power1 > RT5390_POWER_BOUND)
1604                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1605         else
1606                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1607         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1608
1609         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1610         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1611         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1612         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1613         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1614         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1615
1616         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1617         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1618                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1619                                   RT5390_FREQ_OFFSET_BOUND);
1620         else
1621                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1622         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1623
1624         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1625         if (rf->channel <= 14) {
1626                 int idx = rf->channel-1;
1627
1628                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
1629                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1630                                 /* r55/r59 value array of channel 1~14 */
1631                                 static const char r55_bt_rev[] = {0x83, 0x83,
1632                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1633                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1634                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1635                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1636                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1637
1638                                 rt2800_rfcsr_write(rt2x00dev, 55,
1639                                                    r55_bt_rev[idx]);
1640                                 rt2800_rfcsr_write(rt2x00dev, 59,
1641                                                    r59_bt_rev[idx]);
1642                         } else {
1643                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1644                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1645                                         0x88, 0x88, 0x86, 0x85, 0x84};
1646
1647                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1648                         }
1649                 } else {
1650                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1651                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1652                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1653                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1654                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1655                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1656                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1657
1658                                 rt2800_rfcsr_write(rt2x00dev, 55,
1659                                                    r55_nonbt_rev[idx]);
1660                                 rt2800_rfcsr_write(rt2x00dev, 59,
1661                                                    r59_nonbt_rev[idx]);
1662                         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1663                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1664                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1665                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1666
1667                                 rt2800_rfcsr_write(rt2x00dev, 59,
1668                                                    r59_non_bt[idx]);
1669                         }
1670                 }
1671         }
1672
1673         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1674         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1675         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1676         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1677
1678         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1679         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1680         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1681 }
1682
1683 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1684                                   struct ieee80211_conf *conf,
1685                                   struct rf_channel *rf,
1686                                   struct channel_info *info)
1687 {
1688         u32 reg;
1689         unsigned int tx_pin;
1690         u8 bbp;
1691
1692         if (rf->channel <= 14) {
1693                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1694                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1695         } else {
1696                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1697                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1698         }
1699
1700         if (rt2x00_rf(rt2x00dev, RF2020) ||
1701             rt2x00_rf(rt2x00dev, RF3020) ||
1702             rt2x00_rf(rt2x00dev, RF3021) ||
1703             rt2x00_rf(rt2x00dev, RF3022) ||
1704             rt2x00_rf(rt2x00dev, RF3052) ||
1705             rt2x00_rf(rt2x00dev, RF3320))
1706                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1707         else if (rt2x00_rf(rt2x00dev, RF5390))
1708                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1709         else
1710                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1711
1712         /*
1713          * Change BBP settings
1714          */
1715         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1716         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1717         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1718         rt2800_bbp_write(rt2x00dev, 86, 0);
1719
1720         if (rf->channel <= 14) {
1721                 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1722                         if (test_bit(CONFIG_EXTERNAL_LNA_BG,
1723                                      &rt2x00dev->flags)) {
1724                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1725                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1726                         } else {
1727                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1728                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1729                         }
1730                 }
1731         } else {
1732                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1733
1734                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1735                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1736                 else
1737                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1738         }
1739
1740         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1741         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1742         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1743         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1744         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1745
1746         tx_pin = 0;
1747
1748         /* Turn on unused PA or LNA when not using 1T or 1R */
1749         if (rt2x00dev->default_ant.tx_chain_num == 2) {
1750                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1751                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1752         }
1753
1754         /* Turn on unused PA or LNA when not using 1T or 1R */
1755         if (rt2x00dev->default_ant.rx_chain_num == 2) {
1756                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1757                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1758         }
1759
1760         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1761         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1762         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1763         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1764         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1765         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1766
1767         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1768
1769         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1770         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1771         rt2800_bbp_write(rt2x00dev, 4, bbp);
1772
1773         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1774         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1775         rt2800_bbp_write(rt2x00dev, 3, bbp);
1776
1777         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1778                 if (conf_is_ht40(conf)) {
1779                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1780                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1781                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1782                 } else {
1783                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1784                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1785                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1786                 }
1787         }
1788
1789         msleep(1);
1790
1791         /*
1792          * Clear channel statistic counters
1793          */
1794         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1795         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1796         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1797 }
1798
1799 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
1800                                       enum ieee80211_band band)
1801 {
1802         u16 eeprom;
1803         u8 comp_en;
1804         u8 comp_type;
1805         int comp_value;
1806
1807         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1808
1809         if (eeprom == 0xffff)
1810                 return 0;
1811
1812         if (band == IEEE80211_BAND_2GHZ) {
1813                 comp_en = rt2x00_get_field16(eeprom,
1814                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
1815                 if (comp_en) {
1816                         comp_type = rt2x00_get_field16(eeprom,
1817                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
1818                         comp_value = rt2x00_get_field16(eeprom,
1819                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
1820                         if (!comp_type)
1821                                 comp_value = -comp_value;
1822                 }
1823         } else {
1824                 comp_en = rt2x00_get_field16(eeprom,
1825                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
1826                 if (comp_en) {
1827                         comp_type = rt2x00_get_field16(eeprom,
1828                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
1829                         comp_value = rt2x00_get_field16(eeprom,
1830                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
1831                         if (!comp_type)
1832                                 comp_value = -comp_value;
1833                 }
1834         }
1835
1836         return comp_value;
1837 }
1838
1839 static u8 rt2800_compesate_txpower(struct rt2x00_dev *rt2x00dev,
1840                                      int is_rate_b,
1841                                      enum ieee80211_band band,
1842                                      int power_level,
1843                                      u8 txpower)
1844 {
1845         u32 reg;
1846         u16 eeprom;
1847         u8 criterion;
1848         u8 eirp_txpower;
1849         u8 eirp_txpower_criterion;
1850         u8 reg_limit;
1851         int bw_comp = 0;
1852
1853         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
1854                 return txpower;
1855
1856         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1857                 bw_comp = rt2800_get_txpower_bw_comp(rt2x00dev, band);
1858
1859         if (test_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags)) {
1860                 /*
1861                  * Check if eirp txpower exceed txpower_limit.
1862                  * We use OFDM 6M as criterion and its eirp txpower
1863                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
1864                  * .11b data rate need add additional 4dbm
1865                  * when calculating eirp txpower.
1866                  */
1867                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1868                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
1869
1870                 rt2x00_eeprom_read(rt2x00dev,
1871                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
1872
1873                 if (band == IEEE80211_BAND_2GHZ)
1874                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1875                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
1876                 else
1877                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1878                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
1879
1880                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
1881                                        (is_rate_b ? 4 : 0) + bw_comp;
1882
1883                 reg_limit = (eirp_txpower > power_level) ?
1884                                         (eirp_txpower - power_level) : 0;
1885         } else
1886                 reg_limit = 0;
1887
1888         return txpower + bw_comp - reg_limit;
1889 }
1890
1891 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1892                                   struct ieee80211_conf *conf)
1893 {
1894         u8 txpower;
1895         u16 eeprom;
1896         int i, is_rate_b;
1897         u32 reg;
1898         u8 r1;
1899         u32 offset;
1900         enum ieee80211_band band = conf->channel->band;
1901         int power_level = conf->power_level;
1902
1903         /*
1904          * set to normal bbp tx power control mode: +/- 0dBm
1905          */
1906         rt2800_bbp_read(rt2x00dev, 1, &r1);
1907         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
1908         rt2800_bbp_write(rt2x00dev, 1, r1);
1909         offset = TX_PWR_CFG_0;
1910
1911         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1912                 /* just to be safe */
1913                 if (offset > TX_PWR_CFG_4)
1914                         break;
1915
1916                 rt2800_register_read(rt2x00dev, offset, &reg);
1917
1918                 /* read the next four txpower values */
1919                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1920                                    &eeprom);
1921
1922                 is_rate_b = i ? 0 : 1;
1923                 /*
1924                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1925                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1926                  * TX_PWR_CFG_4: unknown
1927                  */
1928                 txpower = rt2x00_get_field16(eeprom,
1929                                              EEPROM_TXPOWER_BYRATE_RATE0);
1930                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1931                                              power_level, txpower);
1932                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
1933
1934                 /*
1935                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1936                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1937                  * TX_PWR_CFG_4: unknown
1938                  */
1939                 txpower = rt2x00_get_field16(eeprom,
1940                                              EEPROM_TXPOWER_BYRATE_RATE1);
1941                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1942                                              power_level, txpower);
1943                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
1944
1945                 /*
1946                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
1947                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
1948                  * TX_PWR_CFG_4: unknown
1949                  */
1950                 txpower = rt2x00_get_field16(eeprom,
1951                                              EEPROM_TXPOWER_BYRATE_RATE2);
1952                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1953                                              power_level, txpower);
1954                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
1955
1956                 /*
1957                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1958                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
1959                  * TX_PWR_CFG_4: unknown
1960                  */
1961                 txpower = rt2x00_get_field16(eeprom,
1962                                              EEPROM_TXPOWER_BYRATE_RATE3);
1963                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1964                                              power_level, txpower);
1965                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
1966
1967                 /* read the next four txpower values */
1968                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1969                                    &eeprom);
1970
1971                 is_rate_b = 0;
1972                 /*
1973                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1974                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1975                  * TX_PWR_CFG_4: unknown
1976                  */
1977                 txpower = rt2x00_get_field16(eeprom,
1978                                              EEPROM_TXPOWER_BYRATE_RATE0);
1979                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1980                                              power_level, txpower);
1981                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
1982
1983                 /*
1984                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1985                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1986                  * TX_PWR_CFG_4: unknown
1987                  */
1988                 txpower = rt2x00_get_field16(eeprom,
1989                                              EEPROM_TXPOWER_BYRATE_RATE1);
1990                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1991                                              power_level, txpower);
1992                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
1993
1994                 /*
1995                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1996                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1997                  * TX_PWR_CFG_4: unknown
1998                  */
1999                 txpower = rt2x00_get_field16(eeprom,
2000                                              EEPROM_TXPOWER_BYRATE_RATE2);
2001                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
2002                                              power_level, txpower);
2003                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2004
2005                 /*
2006                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2007                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2008                  * TX_PWR_CFG_4: unknown
2009                  */
2010                 txpower = rt2x00_get_field16(eeprom,
2011                                              EEPROM_TXPOWER_BYRATE_RATE3);
2012                 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
2013                                              power_level, txpower);
2014                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2015
2016                 rt2800_register_write(rt2x00dev, offset, reg);
2017
2018                 /* next TX_PWR_CFG register */
2019                 offset += 4;
2020         }
2021 }
2022
2023 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2024                                       struct rt2x00lib_conf *libconf)
2025 {
2026         u32 reg;
2027
2028         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2029         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2030                            libconf->conf->short_frame_max_tx_count);
2031         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2032                            libconf->conf->long_frame_max_tx_count);
2033         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2034 }
2035
2036 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2037                              struct rt2x00lib_conf *libconf)
2038 {
2039         enum dev_state state =
2040             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2041                 STATE_SLEEP : STATE_AWAKE;
2042         u32 reg;
2043
2044         if (state == STATE_SLEEP) {
2045                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2046
2047                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2048                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2049                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2050                                    libconf->conf->listen_interval - 1);
2051                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2052                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2053
2054                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2055         } else {
2056                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2057                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2058                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2059                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2060                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2061
2062                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2063         }
2064 }
2065
2066 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2067                    struct rt2x00lib_conf *libconf,
2068                    const unsigned int flags)
2069 {
2070         /* Always recalculate LNA gain before changing configuration */
2071         rt2800_config_lna_gain(rt2x00dev, libconf);
2072
2073         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2074                 rt2800_config_channel(rt2x00dev, libconf->conf,
2075                                       &libconf->rf, &libconf->channel);
2076                 rt2800_config_txpower(rt2x00dev, libconf->conf);
2077         }
2078         if (flags & IEEE80211_CONF_CHANGE_POWER)
2079                 rt2800_config_txpower(rt2x00dev, libconf->conf);
2080         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2081                 rt2800_config_retry_limit(rt2x00dev, libconf);
2082         if (flags & IEEE80211_CONF_CHANGE_PS)
2083                 rt2800_config_ps(rt2x00dev, libconf);
2084 }
2085 EXPORT_SYMBOL_GPL(rt2800_config);
2086
2087 /*
2088  * Link tuning
2089  */
2090 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2091 {
2092         u32 reg;
2093
2094         /*
2095          * Update FCS error count from register.
2096          */
2097         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2098         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2099 }
2100 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2101
2102 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2103 {
2104         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2105                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2106                     rt2x00_rt(rt2x00dev, RT3071) ||
2107                     rt2x00_rt(rt2x00dev, RT3090) ||
2108                     rt2x00_rt(rt2x00dev, RT3390) ||
2109                     rt2x00_rt(rt2x00dev, RT5390))
2110                         return 0x1c + (2 * rt2x00dev->lna_gain);
2111                 else
2112                         return 0x2e + rt2x00dev->lna_gain;
2113         }
2114
2115         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2116                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2117         else
2118                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2119 }
2120
2121 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2122                                   struct link_qual *qual, u8 vgc_level)
2123 {
2124         if (qual->vgc_level != vgc_level) {
2125                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2126                 qual->vgc_level = vgc_level;
2127                 qual->vgc_level_reg = vgc_level;
2128         }
2129 }
2130
2131 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2132 {
2133         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2134 }
2135 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2136
2137 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2138                        const u32 count)
2139 {
2140         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2141                 return;
2142
2143         /*
2144          * When RSSI is better then -80 increase VGC level with 0x10
2145          */
2146         rt2800_set_vgc(rt2x00dev, qual,
2147                        rt2800_get_default_vgc(rt2x00dev) +
2148                        ((qual->rssi > -80) * 0x10));
2149 }
2150 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2151
2152 /*
2153  * Initialization functions.
2154  */
2155 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2156 {
2157         u32 reg;
2158         u16 eeprom;
2159         unsigned int i;
2160         int ret;
2161
2162         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2163         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2164         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2165         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2166         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2167         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2168         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2169
2170         ret = rt2800_drv_init_registers(rt2x00dev);
2171         if (ret)
2172                 return ret;
2173
2174         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2175         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2176         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2177         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2178         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2179         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2180
2181         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2182         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2183         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2184         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2185         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2186         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2187
2188         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2189         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2190
2191         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2192
2193         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2194         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2195         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2196         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2197         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2198         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2199         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2200         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2201
2202         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2203
2204         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2205         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2206         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2207         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2208
2209         if (rt2x00_rt(rt2x00dev, RT3071) ||
2210             rt2x00_rt(rt2x00dev, RT3090) ||
2211             rt2x00_rt(rt2x00dev, RT3390)) {
2212                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2213                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2214                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2215                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2216                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2217                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2218                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2219                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2220                                                       0x0000002c);
2221                         else
2222                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2223                                                       0x0000000f);
2224                 } else {
2225                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2226                 }
2227         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2228                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2229
2230                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2231                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2232                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2233                 } else {
2234                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2235                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2236                 }
2237         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2238                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2239                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2240                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
2241         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2242                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2243                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2244                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2245         } else {
2246                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2247                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2248         }
2249
2250         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2251         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2252         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2253         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2254         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2255         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2256         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2257         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2258         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2259         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2260
2261         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2262         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2263         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2264         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2265         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2266
2267         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2268         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2269         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2270             rt2x00_rt(rt2x00dev, RT2883) ||
2271             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2272                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2273         else
2274                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2275         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2276         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2277         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2278
2279         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2280         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2281         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2282         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2283         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2284         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2285         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2286         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2287         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2288
2289         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2290
2291         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2292         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2293         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2294         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2295         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2296         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2297         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2298         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2299
2300         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2301         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2302         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2303         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2304         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2305         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2306         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2307         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2308         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2309
2310         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2311         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2312         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2313         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2314         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2315         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2316         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2317         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2318         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2319         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2320         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2321         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2322
2323         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2324         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2325         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2326         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2327         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2328         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2329         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2330         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2331         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2332         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2333         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2334         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2335
2336         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2337         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2338         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2339         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2340         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2341         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2342         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2343         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2344         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2345         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2346         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2347         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2348
2349         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2350         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2351         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2352         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2353         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2354         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2355         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2356         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2357         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2358         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2359         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2360         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2361
2362         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2363         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2364         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2365         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2366         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2367         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2368         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2369         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2370         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2371         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2372         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2373         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2374
2375         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2376         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2377         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2378         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2379         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2380         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2381         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2382         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2383         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2384         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2385         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2386         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2387
2388         if (rt2x00_is_usb(rt2x00dev)) {
2389                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2390
2391                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2392                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2393                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2394                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2395                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2396                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2397                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2398                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2399                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2400                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2401                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2402         }
2403
2404         /*
2405          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2406          * although it is reserved.
2407          */
2408         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2409         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2410         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2411         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2412         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2413         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2414         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2415         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2416         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2417         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2418         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2419         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2420
2421         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2422
2423         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2424         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2425         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2426                            IEEE80211_MAX_RTS_THRESHOLD);
2427         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2428         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2429
2430         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2431
2432         /*
2433          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2434          * time should be set to 16. However, the original Ralink driver uses
2435          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2436          * connection problems with 11g + CTS protection. Hence, use the same
2437          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2438          */
2439         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2440         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2441         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2442         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2443         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2444         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2445         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2446
2447         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2448
2449         /*
2450          * ASIC will keep garbage value after boot, clear encryption keys.
2451          */
2452         for (i = 0; i < 4; i++)
2453                 rt2800_register_write(rt2x00dev,
2454                                          SHARED_KEY_MODE_ENTRY(i), 0);
2455
2456         for (i = 0; i < 256; i++) {
2457                 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2458                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2459                                               wcid, sizeof(wcid));
2460
2461                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2462                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2463         }
2464
2465         /*
2466          * Clear all beacons
2467          */
2468         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2469         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2470         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2471         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2472         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2473         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2474         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2475         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2476
2477         if (rt2x00_is_usb(rt2x00dev)) {
2478                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2479                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2480                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2481         } else if (rt2x00_is_pcie(rt2x00dev)) {
2482                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2483                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2484                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2485         }
2486
2487         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2488         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2489         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2490         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2491         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2492         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2493         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2494         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2495         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2496         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2497
2498         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2499         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2500         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2501         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2502         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2503         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2504         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2505         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2506         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2507         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2508
2509         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2510         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2511         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2512         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2513         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2514         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2515         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2516         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2517         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2518         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2519
2520         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2521         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2522         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2523         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2524         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2525         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2526
2527         /*
2528          * Do not force the BA window size, we use the TXWI to set it
2529          */
2530         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2531         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2532         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2533         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2534
2535         /*
2536          * We must clear the error counters.
2537          * These registers are cleared on read,
2538          * so we may pass a useless variable to store the value.
2539          */
2540         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2541         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2542         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2543         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2544         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2545         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2546
2547         /*
2548          * Setup leadtime for pre tbtt interrupt to 6ms
2549          */
2550         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2551         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2552         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2553
2554         /*
2555          * Set up channel statistics timer
2556          */
2557         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2558         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2559         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2560         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2561         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2562         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2563         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2564
2565         return 0;
2566 }
2567
2568 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2569 {
2570         unsigned int i;
2571         u32 reg;
2572
2573         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2574                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2575                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2576                         return 0;
2577
2578                 udelay(REGISTER_BUSY_DELAY);
2579         }
2580
2581         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2582         return -EACCES;
2583 }
2584
2585 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2586 {
2587         unsigned int i;
2588         u8 value;
2589
2590         /*
2591          * BBP was enabled after firmware was loaded,
2592          * but we need to reactivate it now.
2593          */
2594         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2595         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2596         msleep(1);
2597
2598         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2599                 rt2800_bbp_read(rt2x00dev, 0, &value);
2600                 if ((value != 0xff) && (value != 0x00))
2601                         return 0;
2602                 udelay(REGISTER_BUSY_DELAY);
2603         }
2604
2605         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2606         return -EACCES;
2607 }
2608
2609 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2610 {
2611         unsigned int i;
2612         u16 eeprom;
2613         u8 reg_id;
2614         u8 value;
2615
2616         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2617                      rt2800_wait_bbp_ready(rt2x00dev)))
2618                 return -EACCES;
2619
2620         if (rt2x00_rt(rt2x00dev, RT5390)) {
2621                 rt2800_bbp_read(rt2x00dev, 4, &value);
2622                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2623                 rt2800_bbp_write(rt2x00dev, 4, value);
2624         }
2625
2626         if (rt2800_is_305x_soc(rt2x00dev) ||
2627             rt2x00_rt(rt2x00dev, RT5390))
2628                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2629
2630         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2631         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2632
2633         if (rt2x00_rt(rt2x00dev, RT5390))
2634                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2635
2636         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2637                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2638                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2639         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2640                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2641                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2642                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2643                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2644                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
2645         } else {
2646                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2647                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2648         }
2649
2650         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2651
2652         if (rt2x00_rt(rt2x00dev, RT3070) ||
2653             rt2x00_rt(rt2x00dev, RT3071) ||
2654             rt2x00_rt(rt2x00dev, RT3090) ||
2655             rt2x00_rt(rt2x00dev, RT3390) ||
2656             rt2x00_rt(rt2x00dev, RT5390)) {
2657                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2658                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2659                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2660         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2661                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2662                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2663         } else {
2664                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2665         }
2666
2667         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2668         if (rt2x00_rt(rt2x00dev, RT5390))
2669                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2670         else
2671                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2672
2673         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2674                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2675         else if (rt2x00_rt(rt2x00dev, RT5390))
2676                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2677         else
2678                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2679
2680         if (rt2x00_rt(rt2x00dev, RT5390))
2681                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2682         else
2683                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2684
2685         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2686
2687         if (rt2x00_rt(rt2x00dev, RT5390))
2688                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2689         else
2690                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2691
2692         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2693             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2694             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2695             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2696             rt2x00_rt(rt2x00dev, RT5390) ||
2697             rt2800_is_305x_soc(rt2x00dev))
2698                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2699         else
2700                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2701
2702         if (rt2x00_rt(rt2x00dev, RT5390))
2703                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
2704
2705         if (rt2800_is_305x_soc(rt2x00dev))
2706                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2707         else if (rt2x00_rt(rt2x00dev, RT5390))
2708                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
2709         else
2710                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2711
2712         if (rt2x00_rt(rt2x00dev, RT5390))
2713                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2714         else
2715                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2716
2717         if (rt2x00_rt(rt2x00dev, RT5390))
2718                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
2719
2720         if (rt2x00_rt(rt2x00dev, RT3071) ||
2721             rt2x00_rt(rt2x00dev, RT3090) ||
2722             rt2x00_rt(rt2x00dev, RT3390) ||
2723             rt2x00_rt(rt2x00dev, RT5390)) {
2724                 rt2800_bbp_read(rt2x00dev, 138, &value);
2725
2726                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2727                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2728                         value |= 0x20;
2729                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2730                         value &= ~0x02;
2731
2732                 rt2800_bbp_write(rt2x00dev, 138, value);
2733         }
2734
2735         if (rt2x00_rt(rt2x00dev, RT5390)) {
2736                 int ant, div_mode;
2737
2738                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2739                 div_mode = rt2x00_get_field16(eeprom,
2740                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
2741                 ant = (div_mode == 3) ? 1 : 0;
2742
2743                 /* check if this is a Bluetooth combo card */
2744                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2745                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
2746                         u32 reg;
2747
2748                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2749                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2750                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2751                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2752                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2753                         if (ant == 0)
2754                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2755                         else if (ant == 1)
2756                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2757                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2758                 }
2759
2760                 rt2800_bbp_read(rt2x00dev, 152, &value);
2761                 if (ant == 0)
2762                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2763                 else
2764                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2765                 rt2800_bbp_write(rt2x00dev, 152, value);
2766
2767                 /* Init frequency calibration */
2768                 rt2800_bbp_write(rt2x00dev, 142, 1);
2769                 rt2800_bbp_write(rt2x00dev, 143, 57);
2770         }
2771
2772         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2773                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2774
2775                 if (eeprom != 0xffff && eeprom != 0x0000) {
2776                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2777                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2778                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2779                 }
2780         }
2781
2782         return 0;
2783 }
2784
2785 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2786                                 bool bw40, u8 rfcsr24, u8 filter_target)
2787 {
2788         unsigned int i;
2789         u8 bbp;
2790         u8 rfcsr;
2791         u8 passband;
2792         u8 stopband;
2793         u8 overtuned = 0;
2794
2795         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2796
2797         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2798         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2799         rt2800_bbp_write(rt2x00dev, 4, bbp);
2800
2801         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2802         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2803         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2804
2805         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2806         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2807         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2808
2809         /*
2810          * Set power & frequency of passband test tone
2811          */
2812         rt2800_bbp_write(rt2x00dev, 24, 0);
2813
2814         for (i = 0; i < 100; i++) {
2815                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2816                 msleep(1);
2817
2818                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2819                 if (passband)
2820                         break;
2821         }
2822
2823         /*
2824          * Set power & frequency of stopband test tone
2825          */
2826         rt2800_bbp_write(rt2x00dev, 24, 0x06);
2827
2828         for (i = 0; i < 100; i++) {
2829                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2830                 msleep(1);
2831
2832                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2833
2834                 if ((passband - stopband) <= filter_target) {
2835                         rfcsr24++;
2836                         overtuned += ((passband - stopband) == filter_target);
2837                 } else
2838                         break;
2839
2840                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2841         }
2842
2843         rfcsr24 -= !!overtuned;
2844
2845         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2846         return rfcsr24;
2847 }
2848
2849 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2850 {
2851         u8 rfcsr;
2852         u8 bbp;
2853         u32 reg;
2854         u16 eeprom;
2855
2856         if (!rt2x00_rt(rt2x00dev, RT3070) &&
2857             !rt2x00_rt(rt2x00dev, RT3071) &&
2858             !rt2x00_rt(rt2x00dev, RT3090) &&
2859             !rt2x00_rt(rt2x00dev, RT3390) &&
2860             !rt2x00_rt(rt2x00dev, RT5390) &&
2861             !rt2800_is_305x_soc(rt2x00dev))
2862                 return 0;
2863
2864         /*
2865          * Init RF calibration.
2866          */
2867         if (rt2x00_rt(rt2x00dev, RT5390)) {
2868                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
2869                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
2870                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2871                 msleep(1);
2872                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
2873                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2874         } else {
2875                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2876                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2877                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2878                 msleep(1);
2879                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2880                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2881         }
2882
2883         if (rt2x00_rt(rt2x00dev, RT3070) ||
2884             rt2x00_rt(rt2x00dev, RT3071) ||
2885             rt2x00_rt(rt2x00dev, RT3090)) {
2886                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2887                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2888                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2889                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
2890                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2891                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2892                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2893                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2894                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2895                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2896                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2897                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2898                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2899                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2900                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2901                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2902                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2903                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2904                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2905         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2906                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2907                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2908                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2909                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2910                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2911                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2912                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2913                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2914                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2915                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2916                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2917                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2918                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2919                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2920                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2921                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2922                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2923                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2924                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2925                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2926                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2927                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2928                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2929                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2930                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2931                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2932                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2933                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2934                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2935                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2936                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2937                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2938         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2939                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2940                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2941                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2942                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2943                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2944                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2945                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2946                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2947                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2948                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2949                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2950                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2951                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2952                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2953                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2954                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2955                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2956                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2957                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2958                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2959                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2960                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2961                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2962                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2963                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2964                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2965                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2966                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2967                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2968                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2969                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2970                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2971                 return 0;
2972         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2973                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
2974                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
2975                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
2976                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
2977                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2978                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
2979                 else
2980                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
2981                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
2982                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
2983                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
2984                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
2985                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
2986                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
2987                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
2988                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
2989                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
2990                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
2991
2992                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
2993                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
2994                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
2995                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
2996                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
2997                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2998                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2999                 else
3000                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3001                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3002                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3003                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3004                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3005
3006                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3007                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3008                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3009                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3010                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3011                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3012                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3013                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3014                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3015                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3016
3017                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3018                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3019                 else
3020                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3021                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3022                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3023                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3024                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3025                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3026                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3027                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3028                 else
3029                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3030                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3031                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3032                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3033
3034                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3035                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3036                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3037                 else
3038                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3039                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3040                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3041                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3042                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3043                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3044                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3045
3046                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3047                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3048                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3049                 else
3050                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3051                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3052                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3053         }
3054
3055         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3056                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3057                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3058                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3059                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3060         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3061                    rt2x00_rt(rt2x00dev, RT3090)) {
3062                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3063
3064                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3065                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3066                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3067
3068                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3069                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3070                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3071                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3072                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3073                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3074                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3075                         else
3076                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3077                 }
3078                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3079
3080                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3081                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3082                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3083         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3084                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3085                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3086                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3087         }
3088
3089         /*
3090          * Set RX Filter calibration for 20MHz and 40MHz
3091          */
3092         if (rt2x00_rt(rt2x00dev, RT3070)) {
3093                 rt2x00dev->calibration[0] =
3094                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3095                 rt2x00dev->calibration[1] =
3096                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3097         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3098                    rt2x00_rt(rt2x00dev, RT3090) ||
3099                    rt2x00_rt(rt2x00dev, RT3390)) {
3100                 rt2x00dev->calibration[0] =
3101                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3102                 rt2x00dev->calibration[1] =
3103                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3104         }
3105
3106         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3107                 /*
3108                  * Set back to initial state
3109                  */
3110                 rt2800_bbp_write(rt2x00dev, 24, 0);
3111
3112                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3113                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3114                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3115
3116                 /*
3117                  * Set BBP back to BW20
3118                  */
3119                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3120                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3121                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3122         }
3123
3124         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3125             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3126             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3127             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3128                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3129
3130         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3131         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3132         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3133
3134         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3135                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3136                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3137                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3138                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3139                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3140                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3141                         if (!test_bit(CONFIG_EXTERNAL_LNA_BG,
3142                                       &rt2x00dev->flags))
3143                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3144                 }
3145                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3146                 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3147                         rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3148                                         rt2x00_get_field16(eeprom,
3149                                                 EEPROM_TXMIXER_GAIN_BG_VAL));
3150                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3151         }
3152
3153         if (rt2x00_rt(rt2x00dev, RT3090)) {
3154                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3155
3156                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3157                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3158                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3159                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3160                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3161                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3162
3163                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3164         }
3165
3166         if (rt2x00_rt(rt2x00dev, RT3071) ||
3167             rt2x00_rt(rt2x00dev, RT3090) ||
3168             rt2x00_rt(rt2x00dev, RT3390)) {
3169                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3170                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3171                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3172                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3173                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3174                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3175                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3176
3177                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3178                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3179                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3180
3181                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3182                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3183                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3184
3185                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3186                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3187                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3188         }
3189
3190         if (rt2x00_rt(rt2x00dev, RT3070)) {
3191                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3192                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3193                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3194                 else
3195                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3196                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3197                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3198                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3199                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3200         }
3201
3202         if (rt2x00_rt(rt2x00dev, RT5390)) {
3203                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3204                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3205                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3206
3207                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3208                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3209                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3210
3211                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3212                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3213                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3214         }
3215
3216         return 0;
3217 }
3218
3219 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3220 {
3221         u32 reg;
3222         u16 word;
3223
3224         /*
3225          * Initialize all registers.
3226          */
3227         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3228                      rt2800_init_registers(rt2x00dev) ||
3229                      rt2800_init_bbp(rt2x00dev) ||
3230                      rt2800_init_rfcsr(rt2x00dev)))
3231                 return -EIO;
3232
3233         /*
3234          * Send signal to firmware during boot time.
3235          */
3236         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3237
3238         if (rt2x00_is_usb(rt2x00dev) &&
3239             (rt2x00_rt(rt2x00dev, RT3070) ||
3240              rt2x00_rt(rt2x00dev, RT3071) ||
3241              rt2x00_rt(rt2x00dev, RT3572))) {
3242                 udelay(200);
3243                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3244                 udelay(10);
3245         }
3246
3247         /*
3248          * Enable RX.
3249          */
3250         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3251         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3252         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3253         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3254
3255         udelay(50);
3256
3257         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3258         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3259         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3260         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3261         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3262         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3263
3264         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3265         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3266         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3267         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3268
3269         /*
3270          * Initialize LED control
3271          */
3272         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3273         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3274                            word & 0xff, (word >> 8) & 0xff);
3275
3276         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3277         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3278                            word & 0xff, (word >> 8) & 0xff);
3279
3280         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3281         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3282                            word & 0xff, (word >> 8) & 0xff);
3283
3284         return 0;
3285 }
3286 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3287
3288 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3289 {
3290         u32 reg;
3291
3292         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3293         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3294         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3295         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3296
3297         /* Wait for DMA, ignore error */
3298         rt2800_wait_wpdma_ready(rt2x00dev);
3299
3300         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3301         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3302         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3303         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3304 }
3305 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3306
3307 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3308 {
3309         u32 reg;
3310
3311         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3312
3313         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3314 }
3315 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3316
3317 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3318 {
3319         u32 reg;
3320
3321         mutex_lock(&rt2x00dev->csr_mutex);
3322
3323         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3324         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3325         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3326         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3327         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3328
3329         /* Wait until the EEPROM has been loaded */
3330         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3331
3332         /* Apparently the data is read from end to start */
3333         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
3334                                         (u32 *)&rt2x00dev->eeprom[i]);
3335         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
3336                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
3337         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
3338                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
3339         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
3340                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
3341
3342         mutex_unlock(&rt2x00dev->csr_mutex);
3343 }
3344
3345 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3346 {
3347         unsigned int i;
3348
3349         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3350                 rt2800_efuse_read(rt2x00dev, i);
3351 }
3352 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3353
3354 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3355 {
3356         u16 word;
3357         u8 *mac;
3358         u8 default_lna_gain;
3359
3360         /*
3361          * Start validation of the data that has been read.
3362          */
3363         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3364         if (!is_valid_ether_addr(mac)) {
3365                 random_ether_addr(mac);
3366                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3367         }
3368
3369         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3370         if (word == 0xffff) {
3371                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3372                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3373                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3374                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3375                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3376         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3377                    rt2x00_rt(rt2x00dev, RT2872)) {
3378                 /*
3379                  * There is a max of 2 RX streams for RT28x0 series
3380                  */
3381                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3382                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3383                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3384         }
3385
3386         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3387         if (word == 0xffff) {
3388                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3389                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3390                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3391                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3392                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3393                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3394                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3395                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3396                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3397                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3398                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3399                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3400                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3401                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3402                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3403                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3404                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3405         }
3406
3407         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3408         if ((word & 0x00ff) == 0x00ff) {
3409                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3410                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3411                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3412         }
3413         if ((word & 0xff00) == 0xff00) {
3414                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3415                                    LED_MODE_TXRX_ACTIVITY);
3416                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3417                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3418                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3419                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3420                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3421                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3422         }
3423
3424         /*
3425          * During the LNA validation we are going to use
3426          * lna0 as correct value. Note that EEPROM_LNA
3427          * is never validated.
3428          */
3429         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3430         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3431
3432         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3433         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3434                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3435         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3436                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3437         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3438
3439         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3440         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3441                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3442         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3443             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3444                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3445                                    default_lna_gain);
3446         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3447
3448         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3449         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3450                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3451         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3452                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3453         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3454
3455         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3456         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3457                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3458         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3459             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3460                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3461                                    default_lna_gain);
3462         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3463
3464         return 0;
3465 }
3466 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3467
3468 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3469 {
3470         u32 reg;
3471         u16 value;
3472         u16 eeprom;
3473
3474         /*
3475          * Read EEPROM word for configuration.
3476          */
3477         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3478
3479         /*
3480          * Identify RF chipset by EEPROM value
3481          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3482          * RT53xx: defined in "EEPROM_CHIP_ID" field
3483          */
3484         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3485         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3486                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3487         else
3488                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3489
3490         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3491                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3492
3493         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3494             !rt2x00_rt(rt2x00dev, RT2872) &&
3495             !rt2x00_rt(rt2x00dev, RT2883) &&
3496             !rt2x00_rt(rt2x00dev, RT3070) &&
3497             !rt2x00_rt(rt2x00dev, RT3071) &&
3498             !rt2x00_rt(rt2x00dev, RT3090) &&
3499             !rt2x00_rt(rt2x00dev, RT3390) &&
3500             !rt2x00_rt(rt2x00dev, RT3572) &&
3501             !rt2x00_rt(rt2x00dev, RT5390)) {
3502                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3503                 return -ENODEV;
3504         }
3505
3506         if (!rt2x00_rf(rt2x00dev, RF2820) &&
3507             !rt2x00_rf(rt2x00dev, RF2850) &&
3508             !rt2x00_rf(rt2x00dev, RF2720) &&
3509             !rt2x00_rf(rt2x00dev, RF2750) &&
3510             !rt2x00_rf(rt2x00dev, RF3020) &&
3511             !rt2x00_rf(rt2x00dev, RF2020) &&
3512             !rt2x00_rf(rt2x00dev, RF3021) &&
3513             !rt2x00_rf(rt2x00dev, RF3022) &&
3514             !rt2x00_rf(rt2x00dev, RF3052) &&
3515             !rt2x00_rf(rt2x00dev, RF3320) &&
3516             !rt2x00_rf(rt2x00dev, RF5390)) {
3517                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3518                 return -ENODEV;
3519         }
3520
3521         /*
3522          * Identify default antenna configuration.
3523          */
3524         rt2x00dev->default_ant.tx_chain_num =
3525             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3526         rt2x00dev->default_ant.rx_chain_num =
3527             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3528
3529         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3530
3531         if (rt2x00_rt(rt2x00dev, RT3070) ||
3532             rt2x00_rt(rt2x00dev, RT3090) ||
3533             rt2x00_rt(rt2x00dev, RT3390)) {
3534                 value = rt2x00_get_field16(eeprom,
3535                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3536                 switch (value) {
3537                 case 0:
3538                 case 1:
3539                 case 2:
3540                         rt2x00dev->default_ant.tx = ANTENNA_A;
3541                         rt2x00dev->default_ant.rx = ANTENNA_A;
3542                         break;
3543                 case 3:
3544                         rt2x00dev->default_ant.tx = ANTENNA_A;
3545                         rt2x00dev->default_ant.rx = ANTENNA_B;
3546                         break;
3547                 }
3548         } else {
3549                 rt2x00dev->default_ant.tx = ANTENNA_A;
3550                 rt2x00dev->default_ant.rx = ANTENNA_A;
3551         }
3552
3553         /*
3554          * Read frequency offset and RF programming sequence.
3555          */
3556         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3557         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3558
3559         /*
3560          * Read external LNA informations.
3561          */
3562         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3563
3564         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
3565                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
3566         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3567                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3568
3569         /*
3570          * Detect if this device has an hardware controlled radio.
3571          */
3572         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3573                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3574
3575         /*
3576          * Store led settings, for correct led behaviour.
3577          */
3578 #ifdef CONFIG_RT2X00_LIB_LEDS
3579         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3580         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3581         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3582
3583         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3584 #endif /* CONFIG_RT2X00_LIB_LEDS */
3585
3586         /*
3587          * Check if support EIRP tx power limit feature.
3588          */
3589         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3590
3591         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3592                                         EIRP_MAX_TX_POWER_LIMIT)
3593                 __set_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags);
3594
3595         return 0;
3596 }
3597 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3598
3599 /*
3600  * RF value list for rt28xx
3601  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3602  */
3603 static const struct rf_channel rf_vals[] = {
3604         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3605         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3606         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3607         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3608         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3609         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3610         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3611         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3612         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3613         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3614         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3615         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3616         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3617         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3618
3619         /* 802.11 UNI / HyperLan 2 */
3620         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3621         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3622         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3623         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3624         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3625         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3626         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3627         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3628         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3629         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3630         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3631         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3632
3633         /* 802.11 HyperLan 2 */
3634         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3635         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3636         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3637         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3638         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3639         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3640         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3641         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3642         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3643         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3644         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3645         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3646         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3647         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3648         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3649         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3650
3651         /* 802.11 UNII */
3652         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3653         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3654         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3655         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3656         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3657         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3658         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3659         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3660         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3661         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3662         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3663
3664         /* 802.11 Japan */
3665         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3666         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3667         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3668         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3669         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3670         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3671         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3672 };
3673
3674 /*
3675  * RF value list for rt3xxx
3676  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3677  */
3678 static const struct rf_channel rf_vals_3x[] = {
3679         {1,  241, 2, 2 },
3680         {2,  241, 2, 7 },
3681         {3,  242, 2, 2 },
3682         {4,  242, 2, 7 },
3683         {5,  243, 2, 2 },
3684         {6,  243, 2, 7 },
3685         {7,  244, 2, 2 },
3686         {8,  244, 2, 7 },
3687         {9,  245, 2, 2 },
3688         {10, 245, 2, 7 },
3689         {11, 246, 2, 2 },
3690         {12, 246, 2, 7 },
3691         {13, 247, 2, 2 },
3692         {14, 248, 2, 4 },
3693
3694         /* 802.11 UNI / HyperLan 2 */
3695         {36, 0x56, 0, 4},
3696         {38, 0x56, 0, 6},
3697         {40, 0x56, 0, 8},
3698         {44, 0x57, 0, 0},
3699         {46, 0x57, 0, 2},
3700         {48, 0x57, 0, 4},
3701         {52, 0x57, 0, 8},
3702         {54, 0x57, 0, 10},
3703         {56, 0x58, 0, 0},
3704         {60, 0x58, 0, 4},
3705         {62, 0x58, 0, 6},
3706         {64, 0x58, 0, 8},
3707
3708         /* 802.11 HyperLan 2 */
3709         {100, 0x5b, 0, 8},
3710         {102, 0x5b, 0, 10},
3711         {104, 0x5c, 0, 0},
3712         {108, 0x5c, 0, 4},
3713         {110, 0x5c, 0, 6},
3714         {112, 0x5c, 0, 8},
3715         {116, 0x5d, 0, 0},
3716         {118, 0x5d, 0, 2},
3717         {120, 0x5d, 0, 4},
3718         {124, 0x5d, 0, 8},
3719         {126, 0x5d, 0, 10},
3720         {128, 0x5e, 0, 0},
3721         {132, 0x5e, 0, 4},
3722         {134, 0x5e, 0, 6},
3723         {136, 0x5e, 0, 8},
3724         {140, 0x5f, 0, 0},
3725
3726         /* 802.11 UNII */
3727         {149, 0x5f, 0, 9},
3728         {151, 0x5f, 0, 11},
3729         {153, 0x60, 0, 1},
3730         {157, 0x60, 0, 5},
3731         {159, 0x60, 0, 7},
3732         {161, 0x60, 0, 9},
3733         {165, 0x61, 0, 1},
3734         {167, 0x61, 0, 3},
3735         {169, 0x61, 0, 5},
3736         {171, 0x61, 0, 7},
3737         {173, 0x61, 0, 9},
3738 };
3739
3740 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3741 {
3742         struct hw_mode_spec *spec = &rt2x00dev->spec;
3743         struct channel_info *info;
3744         char *default_power1;
3745         char *default_power2;
3746         unsigned int i;
3747         u16 eeprom;
3748
3749         /*
3750          * Disable powersaving as default on PCI devices.
3751          */
3752         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3753                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3754
3755         /*
3756          * Initialize all hw fields.
3757          */
3758         rt2x00dev->hw->flags =
3759             IEEE80211_HW_SIGNAL_DBM |
3760             IEEE80211_HW_SUPPORTS_PS |
3761             IEEE80211_HW_PS_NULLFUNC_STACK |
3762             IEEE80211_HW_AMPDU_AGGREGATION;
3763         /*
3764          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3765          * unless we are capable of sending the buffered frames out after the
3766          * DTIM transmission using rt2x00lib_beacondone. This will send out
3767          * multicast and broadcast traffic immediately instead of buffering it
3768          * infinitly and thus dropping it after some time.
3769          */
3770         if (!rt2x00_is_usb(rt2x00dev))
3771                 rt2x00dev->hw->flags |=
3772                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
3773
3774         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3775         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3776                                 rt2x00_eeprom_addr(rt2x00dev,
3777                                                    EEPROM_MAC_ADDR_0));
3778
3779         /*
3780          * As rt2800 has a global fallback table we cannot specify
3781          * more then one tx rate per frame but since the hw will
3782          * try several rates (based on the fallback table) we should
3783          * initialize max_report_rates to the maximum number of rates
3784          * we are going to try. Otherwise mac80211 will truncate our
3785          * reported tx rates and the rc algortihm will end up with
3786          * incorrect data.
3787          */
3788         rt2x00dev->hw->max_rates = 1;
3789         rt2x00dev->hw->max_report_rates = 7;
3790         rt2x00dev->hw->max_rate_tries = 1;
3791
3792         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3793
3794         /*
3795          * Initialize hw_mode information.
3796          */
3797         spec->supported_bands = SUPPORT_BAND_2GHZ;
3798         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3799
3800         if (rt2x00_rf(rt2x00dev, RF2820) ||
3801             rt2x00_rf(rt2x00dev, RF2720)) {
3802                 spec->num_channels = 14;
3803                 spec->channels = rf_vals;
3804         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3805                    rt2x00_rf(rt2x00dev, RF2750)) {
3806                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3807                 spec->num_channels = ARRAY_SIZE(rf_vals);
3808                 spec->channels = rf_vals;
3809         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3810                    rt2x00_rf(rt2x00dev, RF2020) ||
3811                    rt2x00_rf(rt2x00dev, RF3021) ||
3812                    rt2x00_rf(rt2x00dev, RF3022) ||
3813                    rt2x00_rf(rt2x00dev, RF3320) ||
3814                    rt2x00_rf(rt2x00dev, RF5390)) {
3815                 spec->num_channels = 14;
3816                 spec->channels = rf_vals_3x;
3817         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3818                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3819                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3820                 spec->channels = rf_vals_3x;
3821         }
3822
3823         /*
3824          * Initialize HT information.
3825          */
3826         if (!rt2x00_rf(rt2x00dev, RF2020))
3827                 spec->ht.ht_supported = true;
3828         else
3829                 spec->ht.ht_supported = false;
3830
3831         spec->ht.cap =
3832             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3833             IEEE80211_HT_CAP_GRN_FLD |
3834             IEEE80211_HT_CAP_SGI_20 |
3835             IEEE80211_HT_CAP_SGI_40;
3836
3837         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
3838                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3839
3840         spec->ht.cap |=
3841             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
3842                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3843
3844         spec->ht.ampdu_factor = 3;
3845         spec->ht.ampdu_density = 4;
3846         spec->ht.mcs.tx_params =
3847             IEEE80211_HT_MCS_TX_DEFINED |
3848             IEEE80211_HT_MCS_TX_RX_DIFF |
3849             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
3850                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3851
3852         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
3853         case 3:
3854                 spec->ht.mcs.rx_mask[2] = 0xff;
3855         case 2:
3856                 spec->ht.mcs.rx_mask[1] = 0xff;
3857         case 1:
3858                 spec->ht.mcs.rx_mask[0] = 0xff;
3859                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3860                 break;
3861         }
3862
3863         /*
3864          * Create channel information array
3865          */
3866         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
3867         if (!info)
3868                 return -ENOMEM;
3869
3870         spec->channels_info = info;
3871
3872         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3873         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3874
3875         for (i = 0; i < 14; i++) {
3876                 info[i].default_power1 = default_power1[i];
3877                 info[i].default_power2 = default_power2[i];
3878         }
3879
3880         if (spec->num_channels > 14) {
3881                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3882                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3883
3884                 for (i = 14; i < spec->num_channels; i++) {
3885                         info[i].default_power1 = default_power1[i];
3886                         info[i].default_power2 = default_power2[i];
3887                 }
3888         }
3889
3890         return 0;
3891 }
3892 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3893
3894 /*
3895  * IEEE80211 stack callback functions.
3896  */
3897 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3898                          u16 *iv16)
3899 {
3900         struct rt2x00_dev *rt2x00dev = hw->priv;
3901         struct mac_iveiv_entry iveiv_entry;
3902         u32 offset;
3903
3904         offset = MAC_IVEIV_ENTRY(hw_key_idx);
3905         rt2800_register_multiread(rt2x00dev, offset,
3906                                       &iveiv_entry, sizeof(iveiv_entry));
3907
3908         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3909         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
3910 }
3911 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
3912
3913 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3914 {
3915         struct rt2x00_dev *rt2x00dev = hw->priv;
3916         u32 reg;
3917         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3918
3919         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3920         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3921         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3922
3923         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3924         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3925         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3926
3927         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3928         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3929         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3930
3931         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3932         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3933         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3934
3935         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3936         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3937         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3938
3939         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3940         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3941         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3942
3943         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3944         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3945         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3946
3947         return 0;
3948 }
3949 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
3950
3951 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3952                    const struct ieee80211_tx_queue_params *params)
3953 {
3954         struct rt2x00_dev *rt2x00dev = hw->priv;
3955         struct data_queue *queue;
3956         struct rt2x00_field32 field;
3957         int retval;
3958         u32 reg;
3959         u32 offset;
3960
3961         /*
3962          * First pass the configuration through rt2x00lib, that will
3963          * update the queue settings and validate the input. After that
3964          * we are free to update the registers based on the value
3965          * in the queue parameter.
3966          */
3967         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3968         if (retval)
3969                 return retval;
3970
3971         /*
3972          * We only need to perform additional register initialization
3973          * for WMM queues/
3974          */
3975         if (queue_idx >= 4)
3976                 return 0;
3977
3978         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
3979
3980         /* Update WMM TXOP register */
3981         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3982         field.bit_offset = (queue_idx & 1) * 16;
3983         field.bit_mask = 0xffff << field.bit_offset;
3984
3985         rt2800_register_read(rt2x00dev, offset, &reg);
3986         rt2x00_set_field32(&reg, field, queue->txop);
3987         rt2800_register_write(rt2x00dev, offset, reg);
3988
3989         /* Update WMM registers */
3990         field.bit_offset = queue_idx * 4;
3991         field.bit_mask = 0xf << field.bit_offset;
3992
3993         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3994         rt2x00_set_field32(&reg, field, queue->aifs);
3995         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3996
3997         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3998         rt2x00_set_field32(&reg, field, queue->cw_min);
3999         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4000
4001         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4002         rt2x00_set_field32(&reg, field, queue->cw_max);
4003         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4004
4005         /* Update EDCA registers */
4006         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4007
4008         rt2800_register_read(rt2x00dev, offset, &reg);
4009         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4010         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4011         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4012         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4013         rt2800_register_write(rt2x00dev, offset, reg);
4014
4015         return 0;
4016 }
4017 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4018
4019 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
4020 {
4021         struct rt2x00_dev *rt2x00dev = hw->priv;
4022         u64 tsf;
4023         u32 reg;
4024
4025         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4026         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4027         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4028         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4029
4030         return tsf;
4031 }
4032 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4033
4034 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4035                         enum ieee80211_ampdu_mlme_action action,
4036                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4037                         u8 buf_size)
4038 {
4039         int ret = 0;
4040
4041         switch (action) {
4042         case IEEE80211_AMPDU_RX_START:
4043         case IEEE80211_AMPDU_RX_STOP:
4044                 /*
4045                  * The hw itself takes care of setting up BlockAck mechanisms.
4046                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4047                  * agreement. Once that is done, the hw will BlockAck incoming
4048                  * AMPDUs without further setup.
4049                  */
4050                 break;
4051         case IEEE80211_AMPDU_TX_START:
4052                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4053                 break;
4054         case IEEE80211_AMPDU_TX_STOP:
4055                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4056                 break;
4057         case IEEE80211_AMPDU_TX_OPERATIONAL:
4058                 break;
4059         default:
4060                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4061         }
4062
4063         return ret;
4064 }
4065 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4066
4067 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4068                       struct survey_info *survey)
4069 {
4070         struct rt2x00_dev *rt2x00dev = hw->priv;
4071         struct ieee80211_conf *conf = &hw->conf;
4072         u32 idle, busy, busy_ext;
4073
4074         if (idx != 0)
4075                 return -ENOENT;
4076
4077         survey->channel = conf->channel;
4078
4079         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4080         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4081         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4082
4083         if (idle || busy) {
4084                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4085                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4086                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4087
4088                 survey->channel_time = (idle + busy) / 1000;
4089                 survey->channel_time_busy = busy / 1000;
4090                 survey->channel_time_ext_busy = busy_ext / 1000;
4091         }
4092
4093         return 0;
4094
4095 }
4096 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4097
4098 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4099 MODULE_VERSION(DRV_VERSION);
4100 MODULE_DESCRIPTION("Ralink RT2800 library");
4101 MODULE_LICENSE("GPL");