rt2x00: Refactor beacon code to make use of start- and stop_queue
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7         Based on the original rt2800pci.c and rt2800usb.c.
8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14           <http://rt2x00.serialmonkey.com>
15
16         This program is free software; you can redistribute it and/or modify
17         it under the terms of the GNU General Public License as published by
18         the Free Software Foundation; either version 2 of the License, or
19         (at your option) any later version.
20
21         This program is distributed in the hope that it will be useful,
22         but WITHOUT ANY WARRANTY; without even the implied warranty of
23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24         GNU General Public License for more details.
25
26         You should have received a copy of the GNU General Public License
27         along with this program; if not, write to the
28         Free Software Foundation, Inc.,
29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30  */
31
32 /*
33         Module: rt2800lib
34         Abstract: rt2800 generic device routines.
35  */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47  * Register access.
48  * All access to the CSR registers will go through the methods
49  * rt2800_register_read and rt2800_register_write.
50  * BBP and RF register require indirect register access,
51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
52  * These indirect registers work with busy bits,
53  * and we will try maximal REGISTER_BUSY_COUNT times to access
54  * the register while taking a REGISTER_BUSY_DELAY us delay
55  * between each attampt. When the busy bit is still set at that time,
56  * the access attempt is considered to have failed,
57  * and we will print an error.
58  * The _lock versions must be used if you already hold the csr_mutex
59  */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68                             H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72         /* check for rt2872 on SoC */
73         if (!rt2x00_is_soc(rt2x00dev) ||
74             !rt2x00_rt(rt2x00dev, RT2872))
75                 return false;
76
77         /* we know for sure that these rf chipsets are used on rt305x boards */
78         if (rt2x00_rf(rt2x00dev, RF3020) ||
79             rt2x00_rf(rt2x00dev, RF3021) ||
80             rt2x00_rf(rt2x00dev, RF3022))
81                 return true;
82
83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84         return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88                              const unsigned int word, const u8 value)
89 {
90         u32 reg;
91
92         mutex_lock(&rt2x00dev->csr_mutex);
93
94         /*
95          * Wait until the BBP becomes available, afterwards we
96          * can safely write the new data into the register.
97          */
98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99                 reg = 0;
100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107         }
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113                             const unsigned int word, u8 *value)
114 {
115         u32 reg;
116
117         mutex_lock(&rt2x00dev->csr_mutex);
118
119         /*
120          * Wait until the BBP becomes available, afterwards we
121          * can safely write the read request into the register.
122          * After the data has been written, we wait until hardware
123          * returns the correct value, if at any time the register
124          * doesn't become available in time, reg will be 0xffffffff
125          * which means we return 0xff to the caller.
126          */
127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128                 reg = 0;
129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136                 WAIT_FOR_BBP(rt2x00dev, &reg);
137         }
138
139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141         mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145                                const unsigned int word, const u8 value)
146 {
147         u32 reg;
148
149         mutex_lock(&rt2x00dev->csr_mutex);
150
151         /*
152          * Wait until the RFCSR becomes available, afterwards we
153          * can safely write the new data into the register.
154          */
155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156                 reg = 0;
157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163         }
164
165         mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169                               const unsigned int word, u8 *value)
170 {
171         u32 reg;
172
173         mutex_lock(&rt2x00dev->csr_mutex);
174
175         /*
176          * Wait until the RFCSR becomes available, afterwards we
177          * can safely write the read request into the register.
178          * After the data has been written, we wait until hardware
179          * returns the correct value, if at any time the register
180          * doesn't become available in time, reg will be 0xffffffff
181          * which means we return 0xff to the caller.
182          */
183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184                 reg = 0;
185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192         }
193
194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196         mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200                             const unsigned int word, const u32 value)
201 {
202         u32 reg;
203
204         mutex_lock(&rt2x00dev->csr_mutex);
205
206         /*
207          * Wait until the RF becomes available, afterwards we
208          * can safely write the new data into the register.
209          */
210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211                 reg = 0;
212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218                 rt2x00_rf_write(rt2x00dev, word, value);
219         }
220
221         mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225                         const u8 command, const u8 token,
226                         const u8 arg0, const u8 arg1)
227 {
228         u32 reg;
229
230         /*
231          * SOC devices don't support MCU requests.
232          */
233         if (rt2x00_is_soc(rt2x00dev))
234                 return;
235
236         mutex_lock(&rt2x00dev->csr_mutex);
237
238         /*
239          * Wait until the MCU becomes available, afterwards we
240          * can safely write the new data into the register.
241          */
242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249                 reg = 0;
250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252         }
253
254         mutex_unlock(&rt2x00dev->csr_mutex);
255 }
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
257
258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259 {
260         unsigned int i = 0;
261         u32 reg;
262
263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265                 if (reg && reg != ~0)
266                         return 0;
267                 msleep(1);
268         }
269
270         ERROR(rt2x00dev, "Unstable hardware.\n");
271         return -EBUSY;
272 }
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276 {
277         unsigned int i;
278         u32 reg;
279
280         /*
281          * Some devices are really slow to respond here. Wait a whole second
282          * before timing out.
283          */
284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288                         return 0;
289
290                 msleep(10);
291         }
292
293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294         return -EACCES;
295 }
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299 {
300         u16 fw_crc;
301         u16 crc;
302
303         /*
304          * The last 2 bytes in the firmware array are the crc checksum itself,
305          * this means that we should never pass those 2 bytes to the crc
306          * algorithm.
307          */
308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310         /*
311          * Use the crc ccitt algorithm.
312          * This will return the same value as the legacy driver which
313          * used bit ordering reversion on the both the firmware bytes
314          * before input input as well as on the final output.
315          * Obviously using crc ccitt directly is much more efficient.
316          */
317         crc = crc_ccitt(~0, data, len - 2);
318
319         /*
320          * There is a small difference between the crc-itu-t + bitrev and
321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
322          * will be swapped, use swab16 to convert the crc to the correct
323          * value.
324          */
325         crc = swab16(crc);
326
327         return fw_crc == crc;
328 }
329
330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331                           const u8 *data, const size_t len)
332 {
333         size_t offset = 0;
334         size_t fw_len;
335         bool multiple;
336
337         /*
338          * PCI(e) & SOC devices require firmware with a length
339          * of 8kb. USB devices require firmware files with a length
340          * of 4kb. Certain USB chipsets however require different firmware,
341          * which Ralink only provides attached to the original firmware
342          * file. Thus for USB devices, firmware files have a length
343          * which is a multiple of 4kb.
344          */
345         if (rt2x00_is_usb(rt2x00dev)) {
346                 fw_len = 4096;
347                 multiple = true;
348         } else {
349                 fw_len = 8192;
350                 multiple = true;
351         }
352
353         /*
354          * Validate the firmware length
355          */
356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
357                 return FW_BAD_LENGTH;
358
359         /*
360          * Check if the chipset requires one of the upper parts
361          * of the firmware.
362          */
363         if (rt2x00_is_usb(rt2x00dev) &&
364             !rt2x00_rt(rt2x00dev, RT2860) &&
365             !rt2x00_rt(rt2x00dev, RT2872) &&
366             !rt2x00_rt(rt2x00dev, RT3070) &&
367             ((len / fw_len) == 1))
368                 return FW_BAD_VERSION;
369
370         /*
371          * 8kb firmware files must be checked as if it were
372          * 2 separate firmware files.
373          */
374         while (offset < len) {
375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376                         return FW_BAD_CRC;
377
378                 offset += fw_len;
379         }
380
381         return FW_OK;
382 }
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386                          const u8 *data, const size_t len)
387 {
388         unsigned int i;
389         u32 reg;
390
391         /*
392          * If driver doesn't wake up firmware here,
393          * rt2800_load_firmware will hang forever when interface is up again.
394          */
395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
396
397         /*
398          * Wait for stable hardware.
399          */
400         if (rt2800_wait_csr_ready(rt2x00dev))
401                 return -EBUSY;
402
403         if (rt2x00_is_pci(rt2x00dev))
404                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
405
406         /*
407          * Disable DMA, will be reenabled later when enabling
408          * the radio.
409          */
410         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
411         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
412         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
413         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
414         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
415         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
416         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
417
418         /*
419          * Write firmware to the device.
420          */
421         rt2800_drv_write_firmware(rt2x00dev, data, len);
422
423         /*
424          * Wait for device to stabilize.
425          */
426         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
427                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
428                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
429                         break;
430                 msleep(1);
431         }
432
433         if (i == REGISTER_BUSY_COUNT) {
434                 ERROR(rt2x00dev, "PBF system register not ready.\n");
435                 return -EBUSY;
436         }
437
438         /*
439          * Initialize firmware.
440          */
441         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
442         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
443         msleep(1);
444
445         return 0;
446 }
447 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
448
449 void rt2800_write_tx_data(struct queue_entry *entry,
450                           struct txentry_desc *txdesc)
451 {
452         __le32 *txwi = rt2800_drv_get_txwi(entry);
453         u32 word;
454
455         /*
456          * Initialize TX Info descriptor
457          */
458         rt2x00_desc_read(txwi, 0, &word);
459         rt2x00_set_field32(&word, TXWI_W0_FRAG,
460                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
461         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
462                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
463         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
464         rt2x00_set_field32(&word, TXWI_W0_TS,
465                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
466         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
467                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
468         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
469         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
470         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
471         rt2x00_set_field32(&word, TXWI_W0_BW,
472                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
473         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
474                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
475         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
476         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
477         rt2x00_desc_write(txwi, 0, word);
478
479         rt2x00_desc_read(txwi, 1, &word);
480         rt2x00_set_field32(&word, TXWI_W1_ACK,
481                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
482         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
483                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
484         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
485         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
486                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
487                            txdesc->key_idx : 0xff);
488         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
489                            txdesc->length);
490         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
491         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
492         rt2x00_desc_write(txwi, 1, word);
493
494         /*
495          * Always write 0 to IV/EIV fields, hardware will insert the IV
496          * from the IVEIV register when TXD_W3_WIV is set to 0.
497          * When TXD_W3_WIV is set to 1 it will use the IV data
498          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
499          * crypto entry in the registers should be used to encrypt the frame.
500          */
501         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
502         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
503 }
504 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
505
506 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
507 {
508         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
509         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
510         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
511         u16 eeprom;
512         u8 offset0;
513         u8 offset1;
514         u8 offset2;
515
516         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
517                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
518                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
519                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
520                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
521                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
522         } else {
523                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
524                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
525                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
526                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
527                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
528         }
529
530         /*
531          * Convert the value from the descriptor into the RSSI value
532          * If the value in the descriptor is 0, it is considered invalid
533          * and the default (extremely low) rssi value is assumed
534          */
535         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
536         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
537         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
538
539         /*
540          * mac80211 only accepts a single RSSI value. Calculating the
541          * average doesn't deliver a fair answer either since -60:-60 would
542          * be considered equally good as -50:-70 while the second is the one
543          * which gives less energy...
544          */
545         rssi0 = max(rssi0, rssi1);
546         return max(rssi0, rssi2);
547 }
548
549 void rt2800_process_rxwi(struct queue_entry *entry,
550                          struct rxdone_entry_desc *rxdesc)
551 {
552         __le32 *rxwi = (__le32 *) entry->skb->data;
553         u32 word;
554
555         rt2x00_desc_read(rxwi, 0, &word);
556
557         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
558         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
559
560         rt2x00_desc_read(rxwi, 1, &word);
561
562         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
563                 rxdesc->flags |= RX_FLAG_SHORT_GI;
564
565         if (rt2x00_get_field32(word, RXWI_W1_BW))
566                 rxdesc->flags |= RX_FLAG_40MHZ;
567
568         /*
569          * Detect RX rate, always use MCS as signal type.
570          */
571         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
572         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
573         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
574
575         /*
576          * Mask of 0x8 bit to remove the short preamble flag.
577          */
578         if (rxdesc->rate_mode == RATE_MODE_CCK)
579                 rxdesc->signal &= ~0x8;
580
581         rt2x00_desc_read(rxwi, 2, &word);
582
583         /*
584          * Convert descriptor AGC value to RSSI value.
585          */
586         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
587
588         /*
589          * Remove RXWI descriptor from start of buffer.
590          */
591         skb_pull(entry->skb, RXWI_DESC_SIZE);
592 }
593 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
594
595 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
596 {
597         __le32 *txwi;
598         u32 word;
599         int wcid, ack, pid;
600         int tx_wcid, tx_ack, tx_pid;
601
602         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
603         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
604         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
605
606         /*
607          * This frames has returned with an IO error,
608          * so the status report is not intended for this
609          * frame.
610          */
611         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
612                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
613                 return false;
614         }
615
616         /*
617          * Validate if this TX status report is intended for
618          * this entry by comparing the WCID/ACK/PID fields.
619          */
620         txwi = rt2800_drv_get_txwi(entry);
621
622         rt2x00_desc_read(txwi, 1, &word);
623         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
624         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
625         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
626
627         if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
628                 WARNING(entry->queue->rt2x00dev,
629                         "TX status report missed for queue %d entry %d\n",
630                 entry->queue->qid, entry->entry_idx);
631                 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
632                 return false;
633         }
634
635         return true;
636 }
637
638 void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
639 {
640         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
641         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
642         struct txdone_entry_desc txdesc;
643         u32 word;
644         u16 mcs, real_mcs;
645         int aggr, ampdu;
646         __le32 *txwi;
647
648         /*
649          * Obtain the status about this packet.
650          */
651         txdesc.flags = 0;
652         txwi = rt2800_drv_get_txwi(entry);
653         rt2x00_desc_read(txwi, 0, &word);
654
655         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
656         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
657
658         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
659         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
660
661         /*
662          * If a frame was meant to be sent as a single non-aggregated MPDU
663          * but ended up in an aggregate the used tx rate doesn't correlate
664          * with the one specified in the TXWI as the whole aggregate is sent
665          * with the same rate.
666          *
667          * For example: two frames are sent to rt2x00, the first one sets
668          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
669          * and requests MCS15. If the hw aggregates both frames into one
670          * AMDPU the tx status for both frames will contain MCS7 although
671          * the frame was sent successfully.
672          *
673          * Hence, replace the requested rate with the real tx rate to not
674          * confuse the rate control algortihm by providing clearly wrong
675          * data.
676          */
677         if (aggr == 1 && ampdu == 0 && real_mcs != mcs) {
678                 skbdesc->tx_rate_idx = real_mcs;
679                 mcs = real_mcs;
680         }
681
682         /*
683          * Ralink has a retry mechanism using a global fallback
684          * table. We setup this fallback table to try the immediate
685          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
686          * always contains the MCS used for the last transmission, be
687          * it successful or not.
688          */
689         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
690                 /*
691                  * Transmission succeeded. The number of retries is
692                  * mcs - real_mcs
693                  */
694                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
695                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
696         } else {
697                 /*
698                  * Transmission failed. The number of retries is
699                  * always 7 in this case (for a total number of 8
700                  * frames sent).
701                  */
702                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
703                 txdesc.retry = rt2x00dev->long_retry;
704         }
705
706         /*
707          * the frame was retried at least once
708          * -> hw used fallback rates
709          */
710         if (txdesc.retry)
711                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
712
713         rt2x00lib_txdone(entry, &txdesc);
714 }
715 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
716
717 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
718 {
719         struct data_queue *queue;
720         struct queue_entry *entry;
721         u32 reg;
722         u8 pid;
723         int i;
724
725         /*
726          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
727          * at most X times and also stop processing once the TX_STA_FIFO_VALID
728          * flag is not set anymore.
729          *
730          * The legacy drivers use X=TX_RING_SIZE but state in a comment
731          * that the TX_STA_FIFO stack has a size of 16. We stick to our
732          * tx ring size for now.
733          */
734         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
735                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
736                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
737                         break;
738
739                 /*
740                  * Skip this entry when it contains an invalid
741                  * queue identication number.
742                  */
743                 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
744                 if (pid >= QID_RX)
745                         continue;
746
747                 queue = rt2x00queue_get_queue(rt2x00dev, pid);
748                 if (unlikely(!queue))
749                         continue;
750
751                 /*
752                  * Inside each queue, we process each entry in a chronological
753                  * order. We first check that the queue is not empty.
754                  */
755                 entry = NULL;
756                 while (!rt2x00queue_empty(queue)) {
757                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
758                         if (rt2800_txdone_entry_check(entry, reg))
759                                 break;
760                 }
761
762                 if (!entry || rt2x00queue_empty(queue))
763                         break;
764
765                 rt2800_txdone_entry(entry, reg);
766         }
767 }
768 EXPORT_SYMBOL_GPL(rt2800_txdone);
769
770 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
771 {
772         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
773         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
774         unsigned int beacon_base;
775         unsigned int padding_len;
776         u32 reg;
777
778         /*
779          * Disable beaconing while we are reloading the beacon data,
780          * otherwise we might be sending out invalid data.
781          */
782         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
783         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
784         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
785
786         /*
787          * Add space for the TXWI in front of the skb.
788          */
789         skb_push(entry->skb, TXWI_DESC_SIZE);
790         memset(entry->skb, 0, TXWI_DESC_SIZE);
791
792         /*
793          * Register descriptor details in skb frame descriptor.
794          */
795         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
796         skbdesc->desc = entry->skb->data;
797         skbdesc->desc_len = TXWI_DESC_SIZE;
798
799         /*
800          * Add the TXWI for the beacon to the skb.
801          */
802         rt2800_write_tx_data(entry, txdesc);
803
804         /*
805          * Dump beacon to userspace through debugfs.
806          */
807         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
808
809         /*
810          * Write entire beacon with TXWI and padding to register.
811          */
812         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
813         skb_pad(entry->skb, padding_len);
814         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
815         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
816                                    entry->skb->len + padding_len);
817
818         /*
819          * Enable beaconing again.
820          */
821         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
822         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
823
824         /*
825          * Clean up beacon skb.
826          */
827         dev_kfree_skb_any(entry->skb);
828         entry->skb = NULL;
829 }
830 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
831
832 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
833                                                 unsigned int beacon_base)
834 {
835         int i;
836
837         /*
838          * For the Beacon base registers we only need to clear
839          * the whole TXWI which (when set to 0) will invalidate
840          * the entire beacon.
841          */
842         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
843                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
844 }
845
846 void rt2800_clear_beacon(struct queue_entry *entry)
847 {
848         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
849         u32 reg;
850
851         /*
852          * Disable beaconing while we are reloading the beacon data,
853          * otherwise we might be sending out invalid data.
854          */
855         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
856         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
857         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
858
859         /*
860          * Clear beacon.
861          */
862         rt2800_clear_beacon_register(rt2x00dev,
863                                      HW_BEACON_OFFSET(entry->entry_idx));
864
865         /*
866          * Enabled beaconing again.
867          */
868         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
869         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
870 }
871 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
872
873 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
874 const struct rt2x00debug rt2800_rt2x00debug = {
875         .owner  = THIS_MODULE,
876         .csr    = {
877                 .read           = rt2800_register_read,
878                 .write          = rt2800_register_write,
879                 .flags          = RT2X00DEBUGFS_OFFSET,
880                 .word_base      = CSR_REG_BASE,
881                 .word_size      = sizeof(u32),
882                 .word_count     = CSR_REG_SIZE / sizeof(u32),
883         },
884         .eeprom = {
885                 .read           = rt2x00_eeprom_read,
886                 .write          = rt2x00_eeprom_write,
887                 .word_base      = EEPROM_BASE,
888                 .word_size      = sizeof(u16),
889                 .word_count     = EEPROM_SIZE / sizeof(u16),
890         },
891         .bbp    = {
892                 .read           = rt2800_bbp_read,
893                 .write          = rt2800_bbp_write,
894                 .word_base      = BBP_BASE,
895                 .word_size      = sizeof(u8),
896                 .word_count     = BBP_SIZE / sizeof(u8),
897         },
898         .rf     = {
899                 .read           = rt2x00_rf_read,
900                 .write          = rt2800_rf_write,
901                 .word_base      = RF_BASE,
902                 .word_size      = sizeof(u32),
903                 .word_count     = RF_SIZE / sizeof(u32),
904         },
905 };
906 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
907 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
908
909 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
910 {
911         u32 reg;
912
913         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
914         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
915 }
916 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
917
918 #ifdef CONFIG_RT2X00_LIB_LEDS
919 static void rt2800_brightness_set(struct led_classdev *led_cdev,
920                                   enum led_brightness brightness)
921 {
922         struct rt2x00_led *led =
923             container_of(led_cdev, struct rt2x00_led, led_dev);
924         unsigned int enabled = brightness != LED_OFF;
925         unsigned int bg_mode =
926             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
927         unsigned int polarity =
928                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
929                                    EEPROM_FREQ_LED_POLARITY);
930         unsigned int ledmode =
931                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
932                                    EEPROM_FREQ_LED_MODE);
933
934         if (led->type == LED_TYPE_RADIO) {
935                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
936                                       enabled ? 0x20 : 0);
937         } else if (led->type == LED_TYPE_ASSOC) {
938                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
939                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
940         } else if (led->type == LED_TYPE_QUALITY) {
941                 /*
942                  * The brightness is divided into 6 levels (0 - 5),
943                  * The specs tell us the following levels:
944                  *      0, 1 ,3, 7, 15, 31
945                  * to determine the level in a simple way we can simply
946                  * work with bitshifting:
947                  *      (1 << level) - 1
948                  */
949                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
950                                       (1 << brightness / (LED_FULL / 6)) - 1,
951                                       polarity);
952         }
953 }
954
955 static int rt2800_blink_set(struct led_classdev *led_cdev,
956                             unsigned long *delay_on, unsigned long *delay_off)
957 {
958         struct rt2x00_led *led =
959             container_of(led_cdev, struct rt2x00_led, led_dev);
960         u32 reg;
961
962         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
963         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
964         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
965         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
966
967         return 0;
968 }
969
970 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
971                      struct rt2x00_led *led, enum led_type type)
972 {
973         led->rt2x00dev = rt2x00dev;
974         led->type = type;
975         led->led_dev.brightness_set = rt2800_brightness_set;
976         led->led_dev.blink_set = rt2800_blink_set;
977         led->flags = LED_INITIALIZED;
978 }
979 #endif /* CONFIG_RT2X00_LIB_LEDS */
980
981 /*
982  * Configuration handlers.
983  */
984 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
985                                     struct rt2x00lib_crypto *crypto,
986                                     struct ieee80211_key_conf *key)
987 {
988         struct mac_wcid_entry wcid_entry;
989         struct mac_iveiv_entry iveiv_entry;
990         u32 offset;
991         u32 reg;
992
993         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
994
995         if (crypto->cmd == SET_KEY) {
996                 rt2800_register_read(rt2x00dev, offset, &reg);
997                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
998                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
999                 /*
1000                  * Both the cipher as the BSS Idx numbers are split in a main
1001                  * value of 3 bits, and a extended field for adding one additional
1002                  * bit to the value.
1003                  */
1004                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1005                                    (crypto->cipher & 0x7));
1006                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1007                                    (crypto->cipher & 0x8) >> 3);
1008                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
1009                                    (crypto->bssidx & 0x7));
1010                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1011                                    (crypto->bssidx & 0x8) >> 3);
1012                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1013                 rt2800_register_write(rt2x00dev, offset, reg);
1014         } else {
1015                 rt2800_register_write(rt2x00dev, offset, 0);
1016         }
1017
1018         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1019
1020         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1021         if ((crypto->cipher == CIPHER_TKIP) ||
1022             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1023             (crypto->cipher == CIPHER_AES))
1024                 iveiv_entry.iv[3] |= 0x20;
1025         iveiv_entry.iv[3] |= key->keyidx << 6;
1026         rt2800_register_multiwrite(rt2x00dev, offset,
1027                                       &iveiv_entry, sizeof(iveiv_entry));
1028
1029         offset = MAC_WCID_ENTRY(key->hw_key_idx);
1030
1031         memset(&wcid_entry, 0, sizeof(wcid_entry));
1032         if (crypto->cmd == SET_KEY)
1033                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
1034         rt2800_register_multiwrite(rt2x00dev, offset,
1035                                       &wcid_entry, sizeof(wcid_entry));
1036 }
1037
1038 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1039                              struct rt2x00lib_crypto *crypto,
1040                              struct ieee80211_key_conf *key)
1041 {
1042         struct hw_key_entry key_entry;
1043         struct rt2x00_field32 field;
1044         u32 offset;
1045         u32 reg;
1046
1047         if (crypto->cmd == SET_KEY) {
1048                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1049
1050                 memcpy(key_entry.key, crypto->key,
1051                        sizeof(key_entry.key));
1052                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1053                        sizeof(key_entry.tx_mic));
1054                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1055                        sizeof(key_entry.rx_mic));
1056
1057                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1058                 rt2800_register_multiwrite(rt2x00dev, offset,
1059                                               &key_entry, sizeof(key_entry));
1060         }
1061
1062         /*
1063          * The cipher types are stored over multiple registers
1064          * starting with SHARED_KEY_MODE_BASE each word will have
1065          * 32 bits and contains the cipher types for 2 bssidx each.
1066          * Using the correct defines correctly will cause overhead,
1067          * so just calculate the correct offset.
1068          */
1069         field.bit_offset = 4 * (key->hw_key_idx % 8);
1070         field.bit_mask = 0x7 << field.bit_offset;
1071
1072         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1073
1074         rt2800_register_read(rt2x00dev, offset, &reg);
1075         rt2x00_set_field32(&reg, field,
1076                            (crypto->cmd == SET_KEY) * crypto->cipher);
1077         rt2800_register_write(rt2x00dev, offset, reg);
1078
1079         /*
1080          * Update WCID information
1081          */
1082         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1083
1084         return 0;
1085 }
1086 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1087
1088 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1089                                struct rt2x00lib_crypto *crypto,
1090                                struct ieee80211_key_conf *key)
1091 {
1092         struct hw_key_entry key_entry;
1093         u32 offset;
1094
1095         if (crypto->cmd == SET_KEY) {
1096                 /*
1097                  * 1 pairwise key is possible per AID, this means that the AID
1098                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
1099                  * last possible shared key entry.
1100                  *
1101                  * Since parts of the pairwise key table might be shared with
1102                  * the beacon frame buffers 6 & 7 we should only write into the
1103                  * first 222 entries.
1104                  */
1105                 if (crypto->aid > (222 - 32))
1106                         return -ENOSPC;
1107
1108                 key->hw_key_idx = 32 + crypto->aid;
1109
1110                 memcpy(key_entry.key, crypto->key,
1111                        sizeof(key_entry.key));
1112                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1113                        sizeof(key_entry.tx_mic));
1114                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1115                        sizeof(key_entry.rx_mic));
1116
1117                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1118                 rt2800_register_multiwrite(rt2x00dev, offset,
1119                                               &key_entry, sizeof(key_entry));
1120         }
1121
1122         /*
1123          * Update WCID information
1124          */
1125         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1126
1127         return 0;
1128 }
1129 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1130
1131 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1132                           const unsigned int filter_flags)
1133 {
1134         u32 reg;
1135
1136         /*
1137          * Start configuration steps.
1138          * Note that the version error will always be dropped
1139          * and broadcast frames will always be accepted since
1140          * there is no filter for it at this time.
1141          */
1142         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1143         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1144                            !(filter_flags & FIF_FCSFAIL));
1145         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1146                            !(filter_flags & FIF_PLCPFAIL));
1147         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1148                            !(filter_flags & FIF_PROMISC_IN_BSS));
1149         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1150         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1151         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1152                            !(filter_flags & FIF_ALLMULTI));
1153         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1154         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1155         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1156                            !(filter_flags & FIF_CONTROL));
1157         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1158                            !(filter_flags & FIF_CONTROL));
1159         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1160                            !(filter_flags & FIF_CONTROL));
1161         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1162                            !(filter_flags & FIF_CONTROL));
1163         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1164                            !(filter_flags & FIF_CONTROL));
1165         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1166                            !(filter_flags & FIF_PSPOLL));
1167         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1168         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1169         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1170                            !(filter_flags & FIF_CONTROL));
1171         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1172 }
1173 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1174
1175 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1176                         struct rt2x00intf_conf *conf, const unsigned int flags)
1177 {
1178         u32 reg;
1179         bool update_bssid = false;
1180
1181         if (flags & CONFIG_UPDATE_TYPE) {
1182                 /*
1183                  * Enable synchronisation.
1184                  */
1185                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1186                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1187                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1188         }
1189
1190         if (flags & CONFIG_UPDATE_MAC) {
1191                 if (flags & CONFIG_UPDATE_TYPE &&
1192                     conf->sync == TSF_SYNC_AP_NONE) {
1193                         /*
1194                          * The BSSID register has to be set to our own mac
1195                          * address in AP mode.
1196                          */
1197                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1198                         update_bssid = true;
1199                 }
1200
1201                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1202                         reg = le32_to_cpu(conf->mac[1]);
1203                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1204                         conf->mac[1] = cpu_to_le32(reg);
1205                 }
1206
1207                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1208                                               conf->mac, sizeof(conf->mac));
1209         }
1210
1211         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1212                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1213                         reg = le32_to_cpu(conf->bssid[1]);
1214                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1215                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1216                         conf->bssid[1] = cpu_to_le32(reg);
1217                 }
1218
1219                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1220                                               conf->bssid, sizeof(conf->bssid));
1221         }
1222 }
1223 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1224
1225 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1226                                     struct rt2x00lib_erp *erp)
1227 {
1228         bool any_sta_nongf = !!(erp->ht_opmode &
1229                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1230         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1231         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1232         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1233         u32 reg;
1234
1235         /* default protection rate for HT20: OFDM 24M */
1236         mm20_rate = gf20_rate = 0x4004;
1237
1238         /* default protection rate for HT40: duplicate OFDM 24M */
1239         mm40_rate = gf40_rate = 0x4084;
1240
1241         switch (protection) {
1242         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1243                 /*
1244                  * All STAs in this BSS are HT20/40 but there might be
1245                  * STAs not supporting greenfield mode.
1246                  * => Disable protection for HT transmissions.
1247                  */
1248                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1249
1250                 break;
1251         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1252                 /*
1253                  * All STAs in this BSS are HT20 or HT20/40 but there
1254                  * might be STAs not supporting greenfield mode.
1255                  * => Protect all HT40 transmissions.
1256                  */
1257                 mm20_mode = gf20_mode = 0;
1258                 mm40_mode = gf40_mode = 2;
1259
1260                 break;
1261         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1262                 /*
1263                  * Nonmember protection:
1264                  * According to 802.11n we _should_ protect all
1265                  * HT transmissions (but we don't have to).
1266                  *
1267                  * But if cts_protection is enabled we _shall_ protect
1268                  * all HT transmissions using a CCK rate.
1269                  *
1270                  * And if any station is non GF we _shall_ protect
1271                  * GF transmissions.
1272                  *
1273                  * We decide to protect everything
1274                  * -> fall through to mixed mode.
1275                  */
1276         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1277                 /*
1278                  * Legacy STAs are present
1279                  * => Protect all HT transmissions.
1280                  */
1281                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1282
1283                 /*
1284                  * If erp protection is needed we have to protect HT
1285                  * transmissions with CCK 11M long preamble.
1286                  */
1287                 if (erp->cts_protection) {
1288                         /* don't duplicate RTS/CTS in CCK mode */
1289                         mm20_rate = mm40_rate = 0x0003;
1290                         gf20_rate = gf40_rate = 0x0003;
1291                 }
1292                 break;
1293         };
1294
1295         /* check for STAs not supporting greenfield mode */
1296         if (any_sta_nongf)
1297                 gf20_mode = gf40_mode = 2;
1298
1299         /* Update HT protection config */
1300         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1301         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1302         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1303         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1304
1305         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1306         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1307         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1308         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1309
1310         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1311         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1312         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1313         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1314
1315         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1316         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1317         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1318         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1319 }
1320
1321 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1322                        u32 changed)
1323 {
1324         u32 reg;
1325
1326         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1327                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1328                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1329                                    !!erp->short_preamble);
1330                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1331                                    !!erp->short_preamble);
1332                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1333         }
1334
1335         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1336                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1337                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1338                                    erp->cts_protection ? 2 : 0);
1339                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1340         }
1341
1342         if (changed & BSS_CHANGED_BASIC_RATES) {
1343                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1344                                          erp->basic_rates);
1345                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1346         }
1347
1348         if (changed & BSS_CHANGED_ERP_SLOT) {
1349                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1350                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1351                                    erp->slot_time);
1352                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1353
1354                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1355                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1356                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1357         }
1358
1359         if (changed & BSS_CHANGED_BEACON_INT) {
1360                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1361                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1362                                    erp->beacon_int * 16);
1363                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1364         }
1365
1366         if (changed & BSS_CHANGED_HT)
1367                 rt2800_config_ht_opmode(rt2x00dev, erp);
1368 }
1369 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1370
1371 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1372 {
1373         u8 r1;
1374         u8 r3;
1375
1376         rt2800_bbp_read(rt2x00dev, 1, &r1);
1377         rt2800_bbp_read(rt2x00dev, 3, &r3);
1378
1379         /*
1380          * Configure the TX antenna.
1381          */
1382         switch ((int)ant->tx) {
1383         case 1:
1384                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1385                 break;
1386         case 2:
1387                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1388                 break;
1389         case 3:
1390                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1391                 break;
1392         }
1393
1394         /*
1395          * Configure the RX antenna.
1396          */
1397         switch ((int)ant->rx) {
1398         case 1:
1399                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1400                 break;
1401         case 2:
1402                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1403                 break;
1404         case 3:
1405                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1406                 break;
1407         }
1408
1409         rt2800_bbp_write(rt2x00dev, 3, r3);
1410         rt2800_bbp_write(rt2x00dev, 1, r1);
1411 }
1412 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1413
1414 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1415                                    struct rt2x00lib_conf *libconf)
1416 {
1417         u16 eeprom;
1418         short lna_gain;
1419
1420         if (libconf->rf.channel <= 14) {
1421                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1422                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1423         } else if (libconf->rf.channel <= 64) {
1424                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1425                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1426         } else if (libconf->rf.channel <= 128) {
1427                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1428                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1429         } else {
1430                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1431                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1432         }
1433
1434         rt2x00dev->lna_gain = lna_gain;
1435 }
1436
1437 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1438                                          struct ieee80211_conf *conf,
1439                                          struct rf_channel *rf,
1440                                          struct channel_info *info)
1441 {
1442         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1443
1444         if (rt2x00dev->default_ant.tx == 1)
1445                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1446
1447         if (rt2x00dev->default_ant.rx == 1) {
1448                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1449                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1450         } else if (rt2x00dev->default_ant.rx == 2)
1451                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1452
1453         if (rf->channel > 14) {
1454                 /*
1455                  * When TX power is below 0, we should increase it by 7 to
1456                  * make it a positive value (Minumum value is -7).
1457                  * However this means that values between 0 and 7 have
1458                  * double meaning, and we should set a 7DBm boost flag.
1459                  */
1460                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1461                                    (info->default_power1 >= 0));
1462
1463                 if (info->default_power1 < 0)
1464                         info->default_power1 += 7;
1465
1466                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1467
1468                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1469                                    (info->default_power2 >= 0));
1470
1471                 if (info->default_power2 < 0)
1472                         info->default_power2 += 7;
1473
1474                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1475         } else {
1476                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1477                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1478         }
1479
1480         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1481
1482         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1483         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1484         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1485         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1486
1487         udelay(200);
1488
1489         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1490         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1491         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1492         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1493
1494         udelay(200);
1495
1496         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1497         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1498         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1499         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1500 }
1501
1502 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1503                                          struct ieee80211_conf *conf,
1504                                          struct rf_channel *rf,
1505                                          struct channel_info *info)
1506 {
1507         u8 rfcsr;
1508
1509         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1510         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1511
1512         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1513         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1514         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1515
1516         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1517         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1518         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1519
1520         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1521         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1522         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1523
1524         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1525         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1526         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1527
1528         rt2800_rfcsr_write(rt2x00dev, 24,
1529                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1530
1531         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1532         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1533         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1534 }
1535
1536 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1537                                   struct ieee80211_conf *conf,
1538                                   struct rf_channel *rf,
1539                                   struct channel_info *info)
1540 {
1541         u32 reg;
1542         unsigned int tx_pin;
1543         u8 bbp;
1544
1545         if (rf->channel <= 14) {
1546                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1547                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1548         } else {
1549                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1550                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1551         }
1552
1553         if (rt2x00_rf(rt2x00dev, RF2020) ||
1554             rt2x00_rf(rt2x00dev, RF3020) ||
1555             rt2x00_rf(rt2x00dev, RF3021) ||
1556             rt2x00_rf(rt2x00dev, RF3022) ||
1557             rt2x00_rf(rt2x00dev, RF3052) ||
1558             rt2x00_rf(rt2x00dev, RF3320))
1559                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1560         else
1561                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1562
1563         /*
1564          * Change BBP settings
1565          */
1566         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1567         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1568         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1569         rt2800_bbp_write(rt2x00dev, 86, 0);
1570
1571         if (rf->channel <= 14) {
1572                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1573                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1574                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1575                 } else {
1576                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
1577                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1578                 }
1579         } else {
1580                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1581
1582                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1583                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1584                 else
1585                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1586         }
1587
1588         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1589         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1590         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1591         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1592         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1593
1594         tx_pin = 0;
1595
1596         /* Turn on unused PA or LNA when not using 1T or 1R */
1597         if (rt2x00dev->default_ant.tx != 1) {
1598                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1599                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1600         }
1601
1602         /* Turn on unused PA or LNA when not using 1T or 1R */
1603         if (rt2x00dev->default_ant.rx != 1) {
1604                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1605                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1606         }
1607
1608         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1609         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1610         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1611         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1612         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1613         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1614
1615         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1616
1617         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1618         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1619         rt2800_bbp_write(rt2x00dev, 4, bbp);
1620
1621         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1622         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1623         rt2800_bbp_write(rt2x00dev, 3, bbp);
1624
1625         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1626                 if (conf_is_ht40(conf)) {
1627                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1628                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1629                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1630                 } else {
1631                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1632                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1633                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1634                 }
1635         }
1636
1637         msleep(1);
1638
1639         /*
1640          * Clear channel statistic counters
1641          */
1642         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1643         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1644         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1645 }
1646
1647 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1648                                   const int max_txpower)
1649 {
1650         u8 txpower;
1651         u8 max_value = (u8)max_txpower;
1652         u16 eeprom;
1653         int i;
1654         u32 reg;
1655         u8 r1;
1656         u32 offset;
1657
1658         /*
1659          * set to normal tx power mode: +/- 0dBm
1660          */
1661         rt2800_bbp_read(rt2x00dev, 1, &r1);
1662         rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
1663         rt2800_bbp_write(rt2x00dev, 1, r1);
1664
1665         /*
1666          * The eeprom contains the tx power values for each rate. These
1667          * values map to 100% tx power. Each 16bit word contains four tx
1668          * power values and the order is the same as used in the TX_PWR_CFG
1669          * registers.
1670          */
1671         offset = TX_PWR_CFG_0;
1672
1673         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1674                 /* just to be safe */
1675                 if (offset > TX_PWR_CFG_4)
1676                         break;
1677
1678                 rt2800_register_read(rt2x00dev, offset, &reg);
1679
1680                 /* read the next four txpower values */
1681                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1682                                    &eeprom);
1683
1684                 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1685                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1686                  * TX_PWR_CFG_4: unknown */
1687                 txpower = rt2x00_get_field16(eeprom,
1688                                              EEPROM_TXPOWER_BYRATE_RATE0);
1689                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0,
1690                                    min(txpower, max_value));
1691
1692                 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1693                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1694                  * TX_PWR_CFG_4: unknown */
1695                 txpower = rt2x00_get_field16(eeprom,
1696                                              EEPROM_TXPOWER_BYRATE_RATE1);
1697                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1,
1698                                    min(txpower, max_value));
1699
1700                 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1701                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
1702                  * TX_PWR_CFG_4: unknown */
1703                 txpower = rt2x00_get_field16(eeprom,
1704                                              EEPROM_TXPOWER_BYRATE_RATE2);
1705                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2,
1706                                    min(txpower, max_value));
1707
1708                 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1709                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
1710                  * TX_PWR_CFG_4: unknown */
1711                 txpower = rt2x00_get_field16(eeprom,
1712                                              EEPROM_TXPOWER_BYRATE_RATE3);
1713                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3,
1714                                    min(txpower, max_value));
1715
1716                 /* read the next four txpower values */
1717                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1718                                    &eeprom);
1719
1720                 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1721                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1722                  * TX_PWR_CFG_4: unknown */
1723                 txpower = rt2x00_get_field16(eeprom,
1724                                              EEPROM_TXPOWER_BYRATE_RATE0);
1725                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4,
1726                                    min(txpower, max_value));
1727
1728                 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1729                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1730                  * TX_PWR_CFG_4: unknown */
1731                 txpower = rt2x00_get_field16(eeprom,
1732                                              EEPROM_TXPOWER_BYRATE_RATE1);
1733                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5,
1734                                    min(txpower, max_value));
1735
1736                 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1737                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1738                  * TX_PWR_CFG_4: unknown */
1739                 txpower = rt2x00_get_field16(eeprom,
1740                                              EEPROM_TXPOWER_BYRATE_RATE2);
1741                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6,
1742                                    min(txpower, max_value));
1743
1744                 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1745                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1746                  * TX_PWR_CFG_4: unknown */
1747                 txpower = rt2x00_get_field16(eeprom,
1748                                              EEPROM_TXPOWER_BYRATE_RATE3);
1749                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7,
1750                                    min(txpower, max_value));
1751
1752                 rt2800_register_write(rt2x00dev, offset, reg);
1753
1754                 /* next TX_PWR_CFG register */
1755                 offset += 4;
1756         }
1757 }
1758
1759 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1760                                       struct rt2x00lib_conf *libconf)
1761 {
1762         u32 reg;
1763
1764         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1765         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1766                            libconf->conf->short_frame_max_tx_count);
1767         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1768                            libconf->conf->long_frame_max_tx_count);
1769         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1770 }
1771
1772 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1773                              struct rt2x00lib_conf *libconf)
1774 {
1775         enum dev_state state =
1776             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1777                 STATE_SLEEP : STATE_AWAKE;
1778         u32 reg;
1779
1780         if (state == STATE_SLEEP) {
1781                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1782
1783                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1784                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1785                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1786                                    libconf->conf->listen_interval - 1);
1787                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1788                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1789
1790                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1791         } else {
1792                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1793                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1794                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1795                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1796                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1797
1798                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1799         }
1800 }
1801
1802 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1803                    struct rt2x00lib_conf *libconf,
1804                    const unsigned int flags)
1805 {
1806         /* Always recalculate LNA gain before changing configuration */
1807         rt2800_config_lna_gain(rt2x00dev, libconf);
1808
1809         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1810                 rt2800_config_channel(rt2x00dev, libconf->conf,
1811                                       &libconf->rf, &libconf->channel);
1812         if (flags & IEEE80211_CONF_CHANGE_POWER)
1813                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1814         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1815                 rt2800_config_retry_limit(rt2x00dev, libconf);
1816         if (flags & IEEE80211_CONF_CHANGE_PS)
1817                 rt2800_config_ps(rt2x00dev, libconf);
1818 }
1819 EXPORT_SYMBOL_GPL(rt2800_config);
1820
1821 /*
1822  * Link tuning
1823  */
1824 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1825 {
1826         u32 reg;
1827
1828         /*
1829          * Update FCS error count from register.
1830          */
1831         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1832         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1833 }
1834 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1835
1836 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1837 {
1838         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1839                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1840                     rt2x00_rt(rt2x00dev, RT3071) ||
1841                     rt2x00_rt(rt2x00dev, RT3090) ||
1842                     rt2x00_rt(rt2x00dev, RT3390))
1843                         return 0x1c + (2 * rt2x00dev->lna_gain);
1844                 else
1845                         return 0x2e + rt2x00dev->lna_gain;
1846         }
1847
1848         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1849                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1850         else
1851                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1852 }
1853
1854 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1855                                   struct link_qual *qual, u8 vgc_level)
1856 {
1857         if (qual->vgc_level != vgc_level) {
1858                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1859                 qual->vgc_level = vgc_level;
1860                 qual->vgc_level_reg = vgc_level;
1861         }
1862 }
1863
1864 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1865 {
1866         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1867 }
1868 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1869
1870 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1871                        const u32 count)
1872 {
1873         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1874                 return;
1875
1876         /*
1877          * When RSSI is better then -80 increase VGC level with 0x10
1878          */
1879         rt2800_set_vgc(rt2x00dev, qual,
1880                        rt2800_get_default_vgc(rt2x00dev) +
1881                        ((qual->rssi > -80) * 0x10));
1882 }
1883 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1884
1885 /*
1886  * Initialization functions.
1887  */
1888 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1889 {
1890         u32 reg;
1891         u16 eeprom;
1892         unsigned int i;
1893         int ret;
1894
1895         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1896         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1897         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1898         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1899         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1900         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1901         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1902
1903         ret = rt2800_drv_init_registers(rt2x00dev);
1904         if (ret)
1905                 return ret;
1906
1907         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1908         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1909         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1910         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1911         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1912         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1913
1914         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1915         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1916         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1917         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1918         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1919         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1920
1921         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1922         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1923
1924         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1925
1926         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1927         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
1928         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1929         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1930         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1931         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1932         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1933         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1934
1935         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1936
1937         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1938         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1939         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1940         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1941
1942         if (rt2x00_rt(rt2x00dev, RT3071) ||
1943             rt2x00_rt(rt2x00dev, RT3090) ||
1944             rt2x00_rt(rt2x00dev, RT3390)) {
1945                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1946                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1947                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1948                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1949                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1950                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1951                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
1952                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1953                                                       0x0000002c);
1954                         else
1955                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1956                                                       0x0000000f);
1957                 } else {
1958                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1959                 }
1960         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1961                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1962
1963                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1964                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1965                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1966                 } else {
1967                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1968                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1969                 }
1970         } else if (rt2800_is_305x_soc(rt2x00dev)) {
1971                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1972                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1973                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
1974         } else {
1975                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1976                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1977         }
1978
1979         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1980         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1981         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1982         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1983         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1984         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1985         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1986         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1987         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1988         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1989
1990         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1991         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1992         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1993         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1994         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1995
1996         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1997         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1998         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1999             rt2x00_rt(rt2x00dev, RT2883) ||
2000             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2001                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2002         else
2003                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2004         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2005         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2006         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2007
2008         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2009         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2010         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2011         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2012         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2013         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2014         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2015         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2016         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2017
2018         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2019
2020         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2021         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2022         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2023         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2024         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2025         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2026         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2027         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2028
2029         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2030         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2031         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2032         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2033         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2034         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2035         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2036         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2037         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2038
2039         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2040         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2041         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2042         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
2043         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2044         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2045         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2046         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2047         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2048         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2049         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2050         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2051
2052         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2053         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2054         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2055         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
2056         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2057         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2058         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2059         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2060         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2061         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2062         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2063         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2064
2065         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2066         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2067         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2068         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
2069         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2070         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2071         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2072         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2073         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2074         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2075         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2076         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2077
2078         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2079         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2080         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2081         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
2082         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2083         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2084         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2085         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2086         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2087         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2088         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2089         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2090
2091         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2092         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2093         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2094         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
2095         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2096         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2097         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2098         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2099         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2100         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2101         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2102         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2103
2104         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2105         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2106         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2107         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
2108         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2109         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2110         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2111         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2112         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2113         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2114         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2115         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2116
2117         if (rt2x00_is_usb(rt2x00dev)) {
2118                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2119
2120                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2121                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2122                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2123                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2124                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2125                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2126                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2127                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2128                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2129                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2130                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2131         }
2132
2133         /*
2134          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2135          * although it is reserved.
2136          */
2137         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2138         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2139         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2140         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2141         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2142         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2143         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2144         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2145         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2146         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2147         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2148         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2149
2150         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2151
2152         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2153         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2154         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2155                            IEEE80211_MAX_RTS_THRESHOLD);
2156         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2157         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2158
2159         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2160
2161         /*
2162          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2163          * time should be set to 16. However, the original Ralink driver uses
2164          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2165          * connection problems with 11g + CTS protection. Hence, use the same
2166          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2167          */
2168         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2169         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2170         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2171         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2172         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2173         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2174         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2175
2176         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2177
2178         /*
2179          * ASIC will keep garbage value after boot, clear encryption keys.
2180          */
2181         for (i = 0; i < 4; i++)
2182                 rt2800_register_write(rt2x00dev,
2183                                          SHARED_KEY_MODE_ENTRY(i), 0);
2184
2185         for (i = 0; i < 256; i++) {
2186                 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2187                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2188                                               wcid, sizeof(wcid));
2189
2190                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2191                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2192         }
2193
2194         /*
2195          * Clear all beacons
2196          */
2197         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2198         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2199         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2200         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2201         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2202         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2203         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2204         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2205
2206         if (rt2x00_is_usb(rt2x00dev)) {
2207                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2208                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2209                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2210         }
2211
2212         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2213         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2214         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2215         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2216         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2217         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2218         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2219         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2220         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2221         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2222
2223         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2224         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2225         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2226         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2227         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2228         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2229         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2230         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2231         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2232         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2233
2234         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2235         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2236         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2237         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2238         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2239         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2240         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2241         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2242         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2243         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2244
2245         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2246         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2247         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2248         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2249         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2250         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2251
2252         /*
2253          * Do not force the BA window size, we use the TXWI to set it
2254          */
2255         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2256         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2257         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2258         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2259
2260         /*
2261          * We must clear the error counters.
2262          * These registers are cleared on read,
2263          * so we may pass a useless variable to store the value.
2264          */
2265         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2266         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2267         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2268         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2269         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2270         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2271
2272         /*
2273          * Setup leadtime for pre tbtt interrupt to 6ms
2274          */
2275         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2276         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2277         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2278
2279         /*
2280          * Set up channel statistics timer
2281          */
2282         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2283         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2284         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2285         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2286         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2287         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2288         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2289
2290         return 0;
2291 }
2292
2293 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2294 {
2295         unsigned int i;
2296         u32 reg;
2297
2298         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2299                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2300                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2301                         return 0;
2302
2303                 udelay(REGISTER_BUSY_DELAY);
2304         }
2305
2306         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2307         return -EACCES;
2308 }
2309
2310 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2311 {
2312         unsigned int i;
2313         u8 value;
2314
2315         /*
2316          * BBP was enabled after firmware was loaded,
2317          * but we need to reactivate it now.
2318          */
2319         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2320         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2321         msleep(1);
2322
2323         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2324                 rt2800_bbp_read(rt2x00dev, 0, &value);
2325                 if ((value != 0xff) && (value != 0x00))
2326                         return 0;
2327                 udelay(REGISTER_BUSY_DELAY);
2328         }
2329
2330         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2331         return -EACCES;
2332 }
2333
2334 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2335 {
2336         unsigned int i;
2337         u16 eeprom;
2338         u8 reg_id;
2339         u8 value;
2340
2341         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2342                      rt2800_wait_bbp_ready(rt2x00dev)))
2343                 return -EACCES;
2344
2345         if (rt2800_is_305x_soc(rt2x00dev))
2346                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2347
2348         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2349         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2350
2351         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2352                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2353                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2354         } else {
2355                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2356                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2357         }
2358
2359         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2360
2361         if (rt2x00_rt(rt2x00dev, RT3070) ||
2362             rt2x00_rt(rt2x00dev, RT3071) ||
2363             rt2x00_rt(rt2x00dev, RT3090) ||
2364             rt2x00_rt(rt2x00dev, RT3390)) {
2365                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2366                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2367                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2368         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2369                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2370                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2371         } else {
2372                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2373         }
2374
2375         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2376         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2377
2378         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2379                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2380         else
2381                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2382
2383         rt2800_bbp_write(rt2x00dev, 86, 0x00);
2384         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2385         rt2800_bbp_write(rt2x00dev, 92, 0x00);
2386
2387         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2388             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2389             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2390             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2391             rt2800_is_305x_soc(rt2x00dev))
2392                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2393         else
2394                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2395
2396         if (rt2800_is_305x_soc(rt2x00dev))
2397                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2398         else
2399                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2400         rt2800_bbp_write(rt2x00dev, 106, 0x35);
2401
2402         if (rt2x00_rt(rt2x00dev, RT3071) ||
2403             rt2x00_rt(rt2x00dev, RT3090) ||
2404             rt2x00_rt(rt2x00dev, RT3390)) {
2405                 rt2800_bbp_read(rt2x00dev, 138, &value);
2406
2407                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2408                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2409                         value |= 0x20;
2410                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2411                         value &= ~0x02;
2412
2413                 rt2800_bbp_write(rt2x00dev, 138, value);
2414         }
2415
2416
2417         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2418                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2419
2420                 if (eeprom != 0xffff && eeprom != 0x0000) {
2421                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2422                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2423                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2424                 }
2425         }
2426
2427         return 0;
2428 }
2429
2430 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2431                                 bool bw40, u8 rfcsr24, u8 filter_target)
2432 {
2433         unsigned int i;
2434         u8 bbp;
2435         u8 rfcsr;
2436         u8 passband;
2437         u8 stopband;
2438         u8 overtuned = 0;
2439
2440         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2441
2442         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2443         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2444         rt2800_bbp_write(rt2x00dev, 4, bbp);
2445
2446         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2447         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2448         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2449
2450         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2451         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2452         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2453
2454         /*
2455          * Set power & frequency of passband test tone
2456          */
2457         rt2800_bbp_write(rt2x00dev, 24, 0);
2458
2459         for (i = 0; i < 100; i++) {
2460                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2461                 msleep(1);
2462
2463                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2464                 if (passband)
2465                         break;
2466         }
2467
2468         /*
2469          * Set power & frequency of stopband test tone
2470          */
2471         rt2800_bbp_write(rt2x00dev, 24, 0x06);
2472
2473         for (i = 0; i < 100; i++) {
2474                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2475                 msleep(1);
2476
2477                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2478
2479                 if ((passband - stopband) <= filter_target) {
2480                         rfcsr24++;
2481                         overtuned += ((passband - stopband) == filter_target);
2482                 } else
2483                         break;
2484
2485                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2486         }
2487
2488         rfcsr24 -= !!overtuned;
2489
2490         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2491         return rfcsr24;
2492 }
2493
2494 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2495 {
2496         u8 rfcsr;
2497         u8 bbp;
2498         u32 reg;
2499         u16 eeprom;
2500
2501         if (!rt2x00_rt(rt2x00dev, RT3070) &&
2502             !rt2x00_rt(rt2x00dev, RT3071) &&
2503             !rt2x00_rt(rt2x00dev, RT3090) &&
2504             !rt2x00_rt(rt2x00dev, RT3390) &&
2505             !rt2800_is_305x_soc(rt2x00dev))
2506                 return 0;
2507
2508         /*
2509          * Init RF calibration.
2510          */
2511         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2512         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2513         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2514         msleep(1);
2515         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2516         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2517
2518         if (rt2x00_rt(rt2x00dev, RT3070) ||
2519             rt2x00_rt(rt2x00dev, RT3071) ||
2520             rt2x00_rt(rt2x00dev, RT3090)) {
2521                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2522                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2523                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2524                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
2525                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2526                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2527                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2528                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2529                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2530                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2531                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2532                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2533                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2534                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2535                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2536                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2537                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2538                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2539                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2540         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2541                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2542                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2543                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2544                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2545                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2546                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2547                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2548                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2549                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2550                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2551                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2552                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2553                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2554                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2555                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2556                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2557                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2558                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2559                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2560                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2561                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2562                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2563                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2564                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2565                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2566                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2567                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2568                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2569                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2570                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2571                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2572                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2573         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2574                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2575                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2576                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2577                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2578                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2579                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2580                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2581                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2582                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2583                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2584                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2585                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2586                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2587                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2588                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2589                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2590                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2591                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2592                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2593                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2594                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2595                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2596                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2597                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2598                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2599                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2600                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2601                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2602                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2603                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2604                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2605                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2606                 return 0;
2607         }
2608
2609         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2610                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2611                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2612                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2613                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2614         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2615                    rt2x00_rt(rt2x00dev, RT3090)) {
2616                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2617
2618                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2619                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2620                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2621
2622                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2623                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2624                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2625                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2626                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2627                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2628                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2629                         else
2630                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2631                 }
2632                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2633
2634                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2635                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2636                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2637         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2638                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2639                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
2640                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2641         }
2642
2643         /*
2644          * Set RX Filter calibration for 20MHz and 40MHz
2645          */
2646         if (rt2x00_rt(rt2x00dev, RT3070)) {
2647                 rt2x00dev->calibration[0] =
2648                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2649                 rt2x00dev->calibration[1] =
2650                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
2651         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2652                    rt2x00_rt(rt2x00dev, RT3090) ||
2653                    rt2x00_rt(rt2x00dev, RT3390)) {
2654                 rt2x00dev->calibration[0] =
2655                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2656                 rt2x00dev->calibration[1] =
2657                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2658         }
2659
2660         /*
2661          * Set back to initial state
2662          */
2663         rt2800_bbp_write(rt2x00dev, 24, 0);
2664
2665         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2666         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2667         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2668
2669         /*
2670          * set BBP back to BW20
2671          */
2672         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2673         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2674         rt2800_bbp_write(rt2x00dev, 4, bbp);
2675
2676         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2677             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2678             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2679             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
2680                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2681
2682         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2683         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2684         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2685
2686         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2687         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2688         if (rt2x00_rt(rt2x00dev, RT3070) ||
2689             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2690             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2691             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2692                 if (!test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2693                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2694         }
2695         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2696         if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2697                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2698                                   rt2x00_get_field16(eeprom,
2699                                                    EEPROM_TXMIXER_GAIN_BG_VAL));
2700         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2701
2702         if (rt2x00_rt(rt2x00dev, RT3090)) {
2703                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2704
2705                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
2706                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2707                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2708                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2709                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2710                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2711
2712                 rt2800_bbp_write(rt2x00dev, 138, bbp);
2713         }
2714
2715         if (rt2x00_rt(rt2x00dev, RT3071) ||
2716             rt2x00_rt(rt2x00dev, RT3090) ||
2717             rt2x00_rt(rt2x00dev, RT3390)) {
2718                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2719                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2720                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2721                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2722                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2723                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2724                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2725
2726                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2727                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2728                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2729
2730                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2731                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2732                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2733
2734                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2735                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2736                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2737         }
2738
2739         if (rt2x00_rt(rt2x00dev, RT3070)) {
2740                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2741                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
2742                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2743                 else
2744                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2745                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2746                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2747                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2748                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2749         }
2750
2751         return 0;
2752 }
2753
2754 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2755 {
2756         u32 reg;
2757         u16 word;
2758
2759         /*
2760          * Initialize all registers.
2761          */
2762         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2763                      rt2800_init_registers(rt2x00dev) ||
2764                      rt2800_init_bbp(rt2x00dev) ||
2765                      rt2800_init_rfcsr(rt2x00dev)))
2766                 return -EIO;
2767
2768         /*
2769          * Send signal to firmware during boot time.
2770          */
2771         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2772
2773         if (rt2x00_is_usb(rt2x00dev) &&
2774             (rt2x00_rt(rt2x00dev, RT3070) ||
2775              rt2x00_rt(rt2x00dev, RT3071) ||
2776              rt2x00_rt(rt2x00dev, RT3572))) {
2777                 udelay(200);
2778                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2779                 udelay(10);
2780         }
2781
2782         /*
2783          * Enable RX.
2784          */
2785         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2786         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2787         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2788         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2789
2790         udelay(50);
2791
2792         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2793         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2794         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2795         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2796         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2797         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2798
2799         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2800         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2801         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2802         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2803
2804         /*
2805          * Initialize LED control
2806          */
2807         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
2808         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
2809                            word & 0xff, (word >> 8) & 0xff);
2810
2811         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
2812         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
2813                            word & 0xff, (word >> 8) & 0xff);
2814
2815         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
2816         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
2817                            word & 0xff, (word >> 8) & 0xff);
2818
2819         return 0;
2820 }
2821 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2822
2823 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2824 {
2825         u32 reg;
2826
2827         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2828         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2829         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2830         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2831
2832         /* Wait for DMA, ignore error */
2833         rt2800_wait_wpdma_ready(rt2x00dev);
2834
2835         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2836         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2837         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2838         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2839 }
2840 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2841
2842 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2843 {
2844         u32 reg;
2845
2846         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
2847
2848         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2849 }
2850 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2851
2852 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2853 {
2854         u32 reg;
2855
2856         mutex_lock(&rt2x00dev->csr_mutex);
2857
2858         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
2859         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
2860         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
2861         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
2862         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
2863
2864         /* Wait until the EEPROM has been loaded */
2865         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
2866
2867         /* Apparently the data is read from end to start */
2868         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2869                                         (u32 *)&rt2x00dev->eeprom[i]);
2870         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2871                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
2872         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2873                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
2874         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2875                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
2876
2877         mutex_unlock(&rt2x00dev->csr_mutex);
2878 }
2879
2880 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2881 {
2882         unsigned int i;
2883
2884         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2885                 rt2800_efuse_read(rt2x00dev, i);
2886 }
2887 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2888
2889 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2890 {
2891         u16 word;
2892         u8 *mac;
2893         u8 default_lna_gain;
2894
2895         /*
2896          * Start validation of the data that has been read.
2897          */
2898         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2899         if (!is_valid_ether_addr(mac)) {
2900                 random_ether_addr(mac);
2901                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2902         }
2903
2904         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
2905         if (word == 0xffff) {
2906                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2907                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
2908                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
2909                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
2910                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2911         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2912                    rt2x00_rt(rt2x00dev, RT2872)) {
2913                 /*
2914                  * There is a max of 2 RX streams for RT28x0 series
2915                  */
2916                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
2917                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
2918                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
2919         }
2920
2921         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
2922         if (word == 0xffff) {
2923                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
2924                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
2925                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
2926                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
2927                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
2928                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
2929                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
2930                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
2931                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
2932                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
2933                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
2934                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
2935                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
2936                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
2937                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
2938                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
2939                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2940         }
2941
2942         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2943         if ((word & 0x00ff) == 0x00ff) {
2944                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2945                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2946                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2947         }
2948         if ((word & 0xff00) == 0xff00) {
2949                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2950                                    LED_MODE_TXRX_ACTIVITY);
2951                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2952                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2953                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
2954                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
2955                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
2956                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
2957         }
2958
2959         /*
2960          * During the LNA validation we are going to use
2961          * lna0 as correct value. Note that EEPROM_LNA
2962          * is never validated.
2963          */
2964         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2965         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2966
2967         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2968         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2969                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2970         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2971                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2972         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2973
2974         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2975         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2976                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2977         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2978             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2979                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2980                                    default_lna_gain);
2981         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2982
2983         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2984         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2985                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2986         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2987                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2988         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2989
2990         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2991         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2992                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2993         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2994             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2995                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2996                                    default_lna_gain);
2997         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2998
2999         rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
3000         if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
3001                 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
3002         if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
3003                 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
3004         rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
3005
3006         return 0;
3007 }
3008 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3009
3010 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3011 {
3012         u32 reg;
3013         u16 value;
3014         u16 eeprom;
3015
3016         /*
3017          * Read EEPROM word for configuration.
3018          */
3019         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3020
3021         /*
3022          * Identify RF chipset.
3023          */
3024         value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3025         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3026
3027         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3028                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3029
3030         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3031             !rt2x00_rt(rt2x00dev, RT2872) &&
3032             !rt2x00_rt(rt2x00dev, RT2883) &&
3033             !rt2x00_rt(rt2x00dev, RT3070) &&
3034             !rt2x00_rt(rt2x00dev, RT3071) &&
3035             !rt2x00_rt(rt2x00dev, RT3090) &&
3036             !rt2x00_rt(rt2x00dev, RT3390) &&
3037             !rt2x00_rt(rt2x00dev, RT3572)) {
3038                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3039                 return -ENODEV;
3040         }
3041
3042         if (!rt2x00_rf(rt2x00dev, RF2820) &&
3043             !rt2x00_rf(rt2x00dev, RF2850) &&
3044             !rt2x00_rf(rt2x00dev, RF2720) &&
3045             !rt2x00_rf(rt2x00dev, RF2750) &&
3046             !rt2x00_rf(rt2x00dev, RF3020) &&
3047             !rt2x00_rf(rt2x00dev, RF2020) &&
3048             !rt2x00_rf(rt2x00dev, RF3021) &&
3049             !rt2x00_rf(rt2x00dev, RF3022) &&
3050             !rt2x00_rf(rt2x00dev, RF3052) &&
3051             !rt2x00_rf(rt2x00dev, RF3320)) {
3052                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3053                 return -ENODEV;
3054         }
3055
3056         /*
3057          * Identify default antenna configuration.
3058          */
3059         rt2x00dev->default_ant.tx =
3060             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3061         rt2x00dev->default_ant.rx =
3062             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3063
3064         /*
3065          * Read frequency offset and RF programming sequence.
3066          */
3067         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3068         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3069
3070         /*
3071          * Read external LNA informations.
3072          */
3073         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3074
3075         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
3076                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
3077         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3078                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3079
3080         /*
3081          * Detect if this device has an hardware controlled radio.
3082          */
3083         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3084                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3085
3086         /*
3087          * Store led settings, for correct led behaviour.
3088          */
3089 #ifdef CONFIG_RT2X00_LIB_LEDS
3090         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3091         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3092         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3093
3094         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3095 #endif /* CONFIG_RT2X00_LIB_LEDS */
3096
3097         return 0;
3098 }
3099 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3100
3101 /*
3102  * RF value list for rt28xx
3103  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3104  */
3105 static const struct rf_channel rf_vals[] = {
3106         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3107         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3108         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3109         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3110         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3111         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3112         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3113         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3114         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3115         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3116         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3117         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3118         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3119         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3120
3121         /* 802.11 UNI / HyperLan 2 */
3122         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3123         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3124         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3125         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3126         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3127         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3128         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3129         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3130         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3131         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3132         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3133         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3134
3135         /* 802.11 HyperLan 2 */
3136         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3137         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3138         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3139         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3140         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3141         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3142         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3143         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3144         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3145         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3146         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3147         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3148         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3149         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3150         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3151         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3152
3153         /* 802.11 UNII */
3154         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3155         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3156         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3157         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3158         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3159         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3160         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3161         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3162         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3163         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3164         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3165
3166         /* 802.11 Japan */
3167         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3168         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3169         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3170         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3171         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3172         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3173         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3174 };
3175
3176 /*
3177  * RF value list for rt3xxx
3178  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3179  */
3180 static const struct rf_channel rf_vals_3x[] = {
3181         {1,  241, 2, 2 },
3182         {2,  241, 2, 7 },
3183         {3,  242, 2, 2 },
3184         {4,  242, 2, 7 },
3185         {5,  243, 2, 2 },
3186         {6,  243, 2, 7 },
3187         {7,  244, 2, 2 },
3188         {8,  244, 2, 7 },
3189         {9,  245, 2, 2 },
3190         {10, 245, 2, 7 },
3191         {11, 246, 2, 2 },
3192         {12, 246, 2, 7 },
3193         {13, 247, 2, 2 },
3194         {14, 248, 2, 4 },
3195
3196         /* 802.11 UNI / HyperLan 2 */
3197         {36, 0x56, 0, 4},
3198         {38, 0x56, 0, 6},
3199         {40, 0x56, 0, 8},
3200         {44, 0x57, 0, 0},
3201         {46, 0x57, 0, 2},
3202         {48, 0x57, 0, 4},
3203         {52, 0x57, 0, 8},
3204         {54, 0x57, 0, 10},
3205         {56, 0x58, 0, 0},
3206         {60, 0x58, 0, 4},
3207         {62, 0x58, 0, 6},
3208         {64, 0x58, 0, 8},
3209
3210         /* 802.11 HyperLan 2 */
3211         {100, 0x5b, 0, 8},
3212         {102, 0x5b, 0, 10},
3213         {104, 0x5c, 0, 0},
3214         {108, 0x5c, 0, 4},
3215         {110, 0x5c, 0, 6},
3216         {112, 0x5c, 0, 8},
3217         {116, 0x5d, 0, 0},
3218         {118, 0x5d, 0, 2},
3219         {120, 0x5d, 0, 4},
3220         {124, 0x5d, 0, 8},
3221         {126, 0x5d, 0, 10},
3222         {128, 0x5e, 0, 0},
3223         {132, 0x5e, 0, 4},
3224         {134, 0x5e, 0, 6},
3225         {136, 0x5e, 0, 8},
3226         {140, 0x5f, 0, 0},
3227
3228         /* 802.11 UNII */
3229         {149, 0x5f, 0, 9},
3230         {151, 0x5f, 0, 11},
3231         {153, 0x60, 0, 1},
3232         {157, 0x60, 0, 5},
3233         {159, 0x60, 0, 7},
3234         {161, 0x60, 0, 9},
3235         {165, 0x61, 0, 1},
3236         {167, 0x61, 0, 3},
3237         {169, 0x61, 0, 5},
3238         {171, 0x61, 0, 7},
3239         {173, 0x61, 0, 9},
3240 };
3241
3242 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3243 {
3244         struct hw_mode_spec *spec = &rt2x00dev->spec;
3245         struct channel_info *info;
3246         char *default_power1;
3247         char *default_power2;
3248         unsigned int i;
3249         unsigned short max_power;
3250         u16 eeprom;
3251
3252         /*
3253          * Disable powersaving as default on PCI devices.
3254          */
3255         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3256                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3257
3258         /*
3259          * Initialize all hw fields.
3260          */
3261         rt2x00dev->hw->flags =
3262             IEEE80211_HW_SIGNAL_DBM |
3263             IEEE80211_HW_SUPPORTS_PS |
3264             IEEE80211_HW_PS_NULLFUNC_STACK |
3265             IEEE80211_HW_AMPDU_AGGREGATION;
3266         /*
3267          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3268          * unless we are capable of sending the buffered frames out after the
3269          * DTIM transmission using rt2x00lib_beacondone. This will send out
3270          * multicast and broadcast traffic immediately instead of buffering it
3271          * infinitly and thus dropping it after some time.
3272          */
3273         if (!rt2x00_is_usb(rt2x00dev))
3274                 rt2x00dev->hw->flags |=
3275                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
3276
3277         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3278         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3279                                 rt2x00_eeprom_addr(rt2x00dev,
3280                                                    EEPROM_MAC_ADDR_0));
3281
3282         /*
3283          * As rt2800 has a global fallback table we cannot specify
3284          * more then one tx rate per frame but since the hw will
3285          * try several rates (based on the fallback table) we should
3286          * initialize max_report_rates to the maximum number of rates
3287          * we are going to try. Otherwise mac80211 will truncate our
3288          * reported tx rates and the rc algortihm will end up with
3289          * incorrect data.
3290          */
3291         rt2x00dev->hw->max_rates = 1;
3292         rt2x00dev->hw->max_report_rates = 7;
3293         rt2x00dev->hw->max_rate_tries = 1;
3294
3295         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3296
3297         /*
3298          * Initialize hw_mode information.
3299          */
3300         spec->supported_bands = SUPPORT_BAND_2GHZ;
3301         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3302
3303         if (rt2x00_rf(rt2x00dev, RF2820) ||
3304             rt2x00_rf(rt2x00dev, RF2720)) {
3305                 spec->num_channels = 14;
3306                 spec->channels = rf_vals;
3307         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3308                    rt2x00_rf(rt2x00dev, RF2750)) {
3309                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3310                 spec->num_channels = ARRAY_SIZE(rf_vals);
3311                 spec->channels = rf_vals;
3312         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3313                    rt2x00_rf(rt2x00dev, RF2020) ||
3314                    rt2x00_rf(rt2x00dev, RF3021) ||
3315                    rt2x00_rf(rt2x00dev, RF3022) ||
3316                    rt2x00_rf(rt2x00dev, RF3320)) {
3317                 spec->num_channels = 14;
3318                 spec->channels = rf_vals_3x;
3319         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3320                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3321                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3322                 spec->channels = rf_vals_3x;
3323         }
3324
3325         /*
3326          * Initialize HT information.
3327          */
3328         if (!rt2x00_rf(rt2x00dev, RF2020))
3329                 spec->ht.ht_supported = true;
3330         else
3331                 spec->ht.ht_supported = false;
3332
3333         spec->ht.cap =
3334             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3335             IEEE80211_HT_CAP_GRN_FLD |
3336             IEEE80211_HT_CAP_SGI_20 |
3337             IEEE80211_HT_CAP_SGI_40;
3338
3339         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
3340                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3341
3342         spec->ht.cap |=
3343             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
3344                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3345
3346         spec->ht.ampdu_factor = 3;
3347         spec->ht.ampdu_density = 4;
3348         spec->ht.mcs.tx_params =
3349             IEEE80211_HT_MCS_TX_DEFINED |
3350             IEEE80211_HT_MCS_TX_RX_DIFF |
3351             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
3352                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3353
3354         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
3355         case 3:
3356                 spec->ht.mcs.rx_mask[2] = 0xff;
3357         case 2:
3358                 spec->ht.mcs.rx_mask[1] = 0xff;
3359         case 1:
3360                 spec->ht.mcs.rx_mask[0] = 0xff;
3361                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3362                 break;
3363         }
3364
3365         /*
3366          * Create channel information array
3367          */
3368         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
3369         if (!info)
3370                 return -ENOMEM;
3371
3372         spec->channels_info = info;
3373
3374         rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3375         max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3376         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3377         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3378
3379         for (i = 0; i < 14; i++) {
3380                 info[i].max_power = max_power;
3381                 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3382                 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
3383         }
3384
3385         if (spec->num_channels > 14) {
3386                 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3387                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3388                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3389
3390                 for (i = 14; i < spec->num_channels; i++) {
3391                         info[i].max_power = max_power;
3392                         info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3393                         info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
3394                 }
3395         }
3396
3397         return 0;
3398 }
3399 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3400
3401 /*
3402  * IEEE80211 stack callback functions.
3403  */
3404 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3405                          u16 *iv16)
3406 {
3407         struct rt2x00_dev *rt2x00dev = hw->priv;
3408         struct mac_iveiv_entry iveiv_entry;
3409         u32 offset;
3410
3411         offset = MAC_IVEIV_ENTRY(hw_key_idx);
3412         rt2800_register_multiread(rt2x00dev, offset,
3413                                       &iveiv_entry, sizeof(iveiv_entry));
3414
3415         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3416         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
3417 }
3418 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
3419
3420 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3421 {
3422         struct rt2x00_dev *rt2x00dev = hw->priv;
3423         u32 reg;
3424         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3425
3426         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3427         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3428         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3429
3430         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3431         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3432         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3433
3434         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3435         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3436         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3437
3438         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3439         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3440         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3441
3442         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3443         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3444         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3445
3446         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3447         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3448         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3449
3450         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3451         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3452         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3453
3454         return 0;
3455 }
3456 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
3457
3458 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3459                    const struct ieee80211_tx_queue_params *params)
3460 {
3461         struct rt2x00_dev *rt2x00dev = hw->priv;
3462         struct data_queue *queue;
3463         struct rt2x00_field32 field;
3464         int retval;
3465         u32 reg;
3466         u32 offset;
3467
3468         /*
3469          * First pass the configuration through rt2x00lib, that will
3470          * update the queue settings and validate the input. After that
3471          * we are free to update the registers based on the value
3472          * in the queue parameter.
3473          */
3474         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3475         if (retval)
3476                 return retval;
3477
3478         /*
3479          * We only need to perform additional register initialization
3480          * for WMM queues/
3481          */
3482         if (queue_idx >= 4)
3483                 return 0;
3484
3485         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3486
3487         /* Update WMM TXOP register */
3488         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3489         field.bit_offset = (queue_idx & 1) * 16;
3490         field.bit_mask = 0xffff << field.bit_offset;
3491
3492         rt2800_register_read(rt2x00dev, offset, &reg);
3493         rt2x00_set_field32(&reg, field, queue->txop);
3494         rt2800_register_write(rt2x00dev, offset, reg);
3495
3496         /* Update WMM registers */
3497         field.bit_offset = queue_idx * 4;
3498         field.bit_mask = 0xf << field.bit_offset;
3499
3500         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3501         rt2x00_set_field32(&reg, field, queue->aifs);
3502         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3503
3504         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3505         rt2x00_set_field32(&reg, field, queue->cw_min);
3506         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3507
3508         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3509         rt2x00_set_field32(&reg, field, queue->cw_max);
3510         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3511
3512         /* Update EDCA registers */
3513         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3514
3515         rt2800_register_read(rt2x00dev, offset, &reg);
3516         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3517         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3518         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3519         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3520         rt2800_register_write(rt2x00dev, offset, reg);
3521
3522         return 0;
3523 }
3524 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
3525
3526 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
3527 {
3528         struct rt2x00_dev *rt2x00dev = hw->priv;
3529         u64 tsf;
3530         u32 reg;
3531
3532         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3533         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3534         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3535         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3536
3537         return tsf;
3538 }
3539 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
3540
3541 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3542                         enum ieee80211_ampdu_mlme_action action,
3543                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3544                         u8 buf_size)
3545 {
3546         int ret = 0;
3547
3548         switch (action) {
3549         case IEEE80211_AMPDU_RX_START:
3550         case IEEE80211_AMPDU_RX_STOP:
3551                 /*
3552                  * The hw itself takes care of setting up BlockAck mechanisms.
3553                  * So, we only have to allow mac80211 to nagotiate a BlockAck
3554                  * agreement. Once that is done, the hw will BlockAck incoming
3555                  * AMPDUs without further setup.
3556                  */
3557                 break;
3558         case IEEE80211_AMPDU_TX_START:
3559                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3560                 break;
3561         case IEEE80211_AMPDU_TX_STOP:
3562                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3563                 break;
3564         case IEEE80211_AMPDU_TX_OPERATIONAL:
3565                 break;
3566         default:
3567                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
3568         }
3569
3570         return ret;
3571 }
3572 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
3573
3574 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
3575                       struct survey_info *survey)
3576 {
3577         struct rt2x00_dev *rt2x00dev = hw->priv;
3578         struct ieee80211_conf *conf = &hw->conf;
3579         u32 idle, busy, busy_ext;
3580
3581         if (idx != 0)
3582                 return -ENOENT;
3583
3584         survey->channel = conf->channel;
3585
3586         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
3587         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
3588         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
3589
3590         if (idle || busy) {
3591                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
3592                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
3593                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
3594
3595                 survey->channel_time = (idle + busy) / 1000;
3596                 survey->channel_time_busy = busy / 1000;
3597                 survey->channel_time_ext_busy = busy_ext / 1000;
3598         }
3599
3600         return 0;
3601
3602 }
3603 EXPORT_SYMBOL_GPL(rt2800_get_survey);
3604
3605 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3606 MODULE_VERSION(DRV_VERSION);
3607 MODULE_DESCRIPTION("Ralink RT2800 library");
3608 MODULE_LICENSE("GPL");