Merge branch 'master' of github.com:davem330/net
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2800lib.c
1 /*
2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7         Based on the original rt2800pci.c and rt2800usb.c.
8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14           <http://rt2x00.serialmonkey.com>
15
16         This program is free software; you can redistribute it and/or modify
17         it under the terms of the GNU General Public License as published by
18         the Free Software Foundation; either version 2 of the License, or
19         (at your option) any later version.
20
21         This program is distributed in the hope that it will be useful,
22         but WITHOUT ANY WARRANTY; without even the implied warranty of
23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24         GNU General Public License for more details.
25
26         You should have received a copy of the GNU General Public License
27         along with this program; if not, write to the
28         Free Software Foundation, Inc.,
29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30  */
31
32 /*
33         Module: rt2800lib
34         Abstract: rt2800 generic device routines.
35  */
36
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41
42 #include "rt2x00.h"
43 #include "rt2800lib.h"
44 #include "rt2800.h"
45
46 /*
47  * Register access.
48  * All access to the CSR registers will go through the methods
49  * rt2800_register_read and rt2800_register_write.
50  * BBP and RF register require indirect register access,
51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
52  * These indirect registers work with busy bits,
53  * and we will try maximal REGISTER_BUSY_COUNT times to access
54  * the register while taking a REGISTER_BUSY_DELAY us delay
55  * between each attampt. When the busy bit is still set at that time,
56  * the access attempt is considered to have failed,
57  * and we will print an error.
58  * The _lock versions must be used if you already hold the csr_mutex
59  */
60 #define WAIT_FOR_BBP(__dev, __reg) \
61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68                             H2M_MAILBOX_CSR_OWNER, (__reg))
69
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
71 {
72         /* check for rt2872 on SoC */
73         if (!rt2x00_is_soc(rt2x00dev) ||
74             !rt2x00_rt(rt2x00dev, RT2872))
75                 return false;
76
77         /* we know for sure that these rf chipsets are used on rt305x boards */
78         if (rt2x00_rf(rt2x00dev, RF3020) ||
79             rt2x00_rf(rt2x00dev, RF3021) ||
80             rt2x00_rf(rt2x00dev, RF3022))
81                 return true;
82
83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
84         return false;
85 }
86
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88                              const unsigned int word, const u8 value)
89 {
90         u32 reg;
91
92         mutex_lock(&rt2x00dev->csr_mutex);
93
94         /*
95          * Wait until the BBP becomes available, afterwards we
96          * can safely write the new data into the register.
97          */
98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
99                 reg = 0;
100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
105
106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
107         }
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113                             const unsigned int word, u8 *value)
114 {
115         u32 reg;
116
117         mutex_lock(&rt2x00dev->csr_mutex);
118
119         /*
120          * Wait until the BBP becomes available, afterwards we
121          * can safely write the read request into the register.
122          * After the data has been written, we wait until hardware
123          * returns the correct value, if at any time the register
124          * doesn't become available in time, reg will be 0xffffffff
125          * which means we return 0xff to the caller.
126          */
127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
128                 reg = 0;
129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133
134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
135
136                 WAIT_FOR_BBP(rt2x00dev, &reg);
137         }
138
139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
140
141         mutex_unlock(&rt2x00dev->csr_mutex);
142 }
143
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145                                const unsigned int word, const u8 value)
146 {
147         u32 reg;
148
149         mutex_lock(&rt2x00dev->csr_mutex);
150
151         /*
152          * Wait until the RFCSR becomes available, afterwards we
153          * can safely write the new data into the register.
154          */
155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
156                 reg = 0;
157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
161
162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163         }
164
165         mutex_unlock(&rt2x00dev->csr_mutex);
166 }
167
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169                               const unsigned int word, u8 *value)
170 {
171         u32 reg;
172
173         mutex_lock(&rt2x00dev->csr_mutex);
174
175         /*
176          * Wait until the RFCSR becomes available, afterwards we
177          * can safely write the read request into the register.
178          * After the data has been written, we wait until hardware
179          * returns the correct value, if at any time the register
180          * doesn't become available in time, reg will be 0xffffffff
181          * which means we return 0xff to the caller.
182          */
183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184                 reg = 0;
185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
188
189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
190
191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
192         }
193
194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
195
196         mutex_unlock(&rt2x00dev->csr_mutex);
197 }
198
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200                             const unsigned int word, const u32 value)
201 {
202         u32 reg;
203
204         mutex_lock(&rt2x00dev->csr_mutex);
205
206         /*
207          * Wait until the RF becomes available, afterwards we
208          * can safely write the new data into the register.
209          */
210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
211                 reg = 0;
212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
216
217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218                 rt2x00_rf_write(rt2x00dev, word, value);
219         }
220
221         mutex_unlock(&rt2x00dev->csr_mutex);
222 }
223
224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225                         const u8 command, const u8 token,
226                         const u8 arg0, const u8 arg1)
227 {
228         u32 reg;
229
230         /*
231          * SOC devices don't support MCU requests.
232          */
233         if (rt2x00_is_soc(rt2x00dev))
234                 return;
235
236         mutex_lock(&rt2x00dev->csr_mutex);
237
238         /*
239          * Wait until the MCU becomes available, afterwards we
240          * can safely write the new data into the register.
241          */
242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
248
249                 reg = 0;
250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
252         }
253
254         mutex_unlock(&rt2x00dev->csr_mutex);
255 }
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
257
258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
259 {
260         unsigned int i = 0;
261         u32 reg;
262
263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
265                 if (reg && reg != ~0)
266                         return 0;
267                 msleep(1);
268         }
269
270         ERROR(rt2x00dev, "Unstable hardware.\n");
271         return -EBUSY;
272 }
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
274
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
276 {
277         unsigned int i;
278         u32 reg;
279
280         /*
281          * Some devices are really slow to respond here. Wait a whole second
282          * before timing out.
283          */
284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
288                         return 0;
289
290                 msleep(10);
291         }
292
293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
294         return -EACCES;
295 }
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
297
298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
299 {
300         u16 fw_crc;
301         u16 crc;
302
303         /*
304          * The last 2 bytes in the firmware array are the crc checksum itself,
305          * this means that we should never pass those 2 bytes to the crc
306          * algorithm.
307          */
308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
309
310         /*
311          * Use the crc ccitt algorithm.
312          * This will return the same value as the legacy driver which
313          * used bit ordering reversion on the both the firmware bytes
314          * before input input as well as on the final output.
315          * Obviously using crc ccitt directly is much more efficient.
316          */
317         crc = crc_ccitt(~0, data, len - 2);
318
319         /*
320          * There is a small difference between the crc-itu-t + bitrev and
321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
322          * will be swapped, use swab16 to convert the crc to the correct
323          * value.
324          */
325         crc = swab16(crc);
326
327         return fw_crc == crc;
328 }
329
330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331                           const u8 *data, const size_t len)
332 {
333         size_t offset = 0;
334         size_t fw_len;
335         bool multiple;
336
337         /*
338          * PCI(e) & SOC devices require firmware with a length
339          * of 8kb. USB devices require firmware files with a length
340          * of 4kb. Certain USB chipsets however require different firmware,
341          * which Ralink only provides attached to the original firmware
342          * file. Thus for USB devices, firmware files have a length
343          * which is a multiple of 4kb.
344          */
345         if (rt2x00_is_usb(rt2x00dev)) {
346                 fw_len = 4096;
347                 multiple = true;
348         } else {
349                 fw_len = 8192;
350                 multiple = true;
351         }
352
353         /*
354          * Validate the firmware length
355          */
356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
357                 return FW_BAD_LENGTH;
358
359         /*
360          * Check if the chipset requires one of the upper parts
361          * of the firmware.
362          */
363         if (rt2x00_is_usb(rt2x00dev) &&
364             !rt2x00_rt(rt2x00dev, RT2860) &&
365             !rt2x00_rt(rt2x00dev, RT2872) &&
366             !rt2x00_rt(rt2x00dev, RT3070) &&
367             ((len / fw_len) == 1))
368                 return FW_BAD_VERSION;
369
370         /*
371          * 8kb firmware files must be checked as if it were
372          * 2 separate firmware files.
373          */
374         while (offset < len) {
375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
376                         return FW_BAD_CRC;
377
378                 offset += fw_len;
379         }
380
381         return FW_OK;
382 }
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
384
385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386                          const u8 *data, const size_t len)
387 {
388         unsigned int i;
389         u32 reg;
390
391         /*
392          * If driver doesn't wake up firmware here,
393          * rt2800_load_firmware will hang forever when interface is up again.
394          */
395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
396
397         /*
398          * Wait for stable hardware.
399          */
400         if (rt2800_wait_csr_ready(rt2x00dev))
401                 return -EBUSY;
402
403         if (rt2x00_is_pci(rt2x00dev)) {
404                 if (rt2x00_rt(rt2x00dev, RT3572) ||
405                     rt2x00_rt(rt2x00dev, RT5390)) {
406                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
407                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
408                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
409                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
410                 }
411                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
412         }
413
414         /*
415          * Disable DMA, will be reenabled later when enabling
416          * the radio.
417          */
418         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
419         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
420         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
421         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
422         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
423         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
424         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
425
426         /*
427          * Write firmware to the device.
428          */
429         rt2800_drv_write_firmware(rt2x00dev, data, len);
430
431         /*
432          * Wait for device to stabilize.
433          */
434         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
435                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
436                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
437                         break;
438                 msleep(1);
439         }
440
441         if (i == REGISTER_BUSY_COUNT) {
442                 ERROR(rt2x00dev, "PBF system register not ready.\n");
443                 return -EBUSY;
444         }
445
446         /*
447          * Initialize firmware.
448          */
449         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
450         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
451         msleep(1);
452
453         return 0;
454 }
455 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
456
457 void rt2800_write_tx_data(struct queue_entry *entry,
458                           struct txentry_desc *txdesc)
459 {
460         __le32 *txwi = rt2800_drv_get_txwi(entry);
461         u32 word;
462
463         /*
464          * Initialize TX Info descriptor
465          */
466         rt2x00_desc_read(txwi, 0, &word);
467         rt2x00_set_field32(&word, TXWI_W0_FRAG,
468                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
469         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
470                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
471         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
472         rt2x00_set_field32(&word, TXWI_W0_TS,
473                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
474         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
475                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
476         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
477                            txdesc->u.ht.mpdu_density);
478         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
479         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
480         rt2x00_set_field32(&word, TXWI_W0_BW,
481                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
482         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
483                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
484         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
485         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
486         rt2x00_desc_write(txwi, 0, word);
487
488         rt2x00_desc_read(txwi, 1, &word);
489         rt2x00_set_field32(&word, TXWI_W1_ACK,
490                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
491         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
492                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
493         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
494         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
495                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
496                            txdesc->key_idx : txdesc->u.ht.wcid);
497         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
498                            txdesc->length);
499         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
500         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
501         rt2x00_desc_write(txwi, 1, word);
502
503         /*
504          * Always write 0 to IV/EIV fields, hardware will insert the IV
505          * from the IVEIV register when TXD_W3_WIV is set to 0.
506          * When TXD_W3_WIV is set to 1 it will use the IV data
507          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
508          * crypto entry in the registers should be used to encrypt the frame.
509          */
510         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
511         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
512 }
513 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
514
515 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
516 {
517         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
518         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
519         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
520         u16 eeprom;
521         u8 offset0;
522         u8 offset1;
523         u8 offset2;
524
525         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
526                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
527                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
528                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
529                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
530                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
531         } else {
532                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
533                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
534                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
535                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
536                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
537         }
538
539         /*
540          * Convert the value from the descriptor into the RSSI value
541          * If the value in the descriptor is 0, it is considered invalid
542          * and the default (extremely low) rssi value is assumed
543          */
544         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
545         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
546         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
547
548         /*
549          * mac80211 only accepts a single RSSI value. Calculating the
550          * average doesn't deliver a fair answer either since -60:-60 would
551          * be considered equally good as -50:-70 while the second is the one
552          * which gives less energy...
553          */
554         rssi0 = max(rssi0, rssi1);
555         return max(rssi0, rssi2);
556 }
557
558 void rt2800_process_rxwi(struct queue_entry *entry,
559                          struct rxdone_entry_desc *rxdesc)
560 {
561         __le32 *rxwi = (__le32 *) entry->skb->data;
562         u32 word;
563
564         rt2x00_desc_read(rxwi, 0, &word);
565
566         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
567         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
568
569         rt2x00_desc_read(rxwi, 1, &word);
570
571         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
572                 rxdesc->flags |= RX_FLAG_SHORT_GI;
573
574         if (rt2x00_get_field32(word, RXWI_W1_BW))
575                 rxdesc->flags |= RX_FLAG_40MHZ;
576
577         /*
578          * Detect RX rate, always use MCS as signal type.
579          */
580         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
581         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
582         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
583
584         /*
585          * Mask of 0x8 bit to remove the short preamble flag.
586          */
587         if (rxdesc->rate_mode == RATE_MODE_CCK)
588                 rxdesc->signal &= ~0x8;
589
590         rt2x00_desc_read(rxwi, 2, &word);
591
592         /*
593          * Convert descriptor AGC value to RSSI value.
594          */
595         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
596
597         /*
598          * Remove RXWI descriptor from start of buffer.
599          */
600         skb_pull(entry->skb, RXWI_DESC_SIZE);
601 }
602 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
603
604 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
605 {
606         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
607         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
608         struct txdone_entry_desc txdesc;
609         u32 word;
610         u16 mcs, real_mcs;
611         int aggr, ampdu;
612
613         /*
614          * Obtain the status about this packet.
615          */
616         txdesc.flags = 0;
617         rt2x00_desc_read(txwi, 0, &word);
618
619         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
620         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
621
622         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
623         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
624
625         /*
626          * If a frame was meant to be sent as a single non-aggregated MPDU
627          * but ended up in an aggregate the used tx rate doesn't correlate
628          * with the one specified in the TXWI as the whole aggregate is sent
629          * with the same rate.
630          *
631          * For example: two frames are sent to rt2x00, the first one sets
632          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
633          * and requests MCS15. If the hw aggregates both frames into one
634          * AMDPU the tx status for both frames will contain MCS7 although
635          * the frame was sent successfully.
636          *
637          * Hence, replace the requested rate with the real tx rate to not
638          * confuse the rate control algortihm by providing clearly wrong
639          * data.
640          */
641         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
642                 skbdesc->tx_rate_idx = real_mcs;
643                 mcs = real_mcs;
644         }
645
646         if (aggr == 1 || ampdu == 1)
647                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
648
649         /*
650          * Ralink has a retry mechanism using a global fallback
651          * table. We setup this fallback table to try the immediate
652          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
653          * always contains the MCS used for the last transmission, be
654          * it successful or not.
655          */
656         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
657                 /*
658                  * Transmission succeeded. The number of retries is
659                  * mcs - real_mcs
660                  */
661                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
662                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
663         } else {
664                 /*
665                  * Transmission failed. The number of retries is
666                  * always 7 in this case (for a total number of 8
667                  * frames sent).
668                  */
669                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
670                 txdesc.retry = rt2x00dev->long_retry;
671         }
672
673         /*
674          * the frame was retried at least once
675          * -> hw used fallback rates
676          */
677         if (txdesc.retry)
678                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
679
680         rt2x00lib_txdone(entry, &txdesc);
681 }
682 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
683
684 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
685 {
686         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
687         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
688         unsigned int beacon_base;
689         unsigned int padding_len;
690         u32 orig_reg, reg;
691
692         /*
693          * Disable beaconing while we are reloading the beacon data,
694          * otherwise we might be sending out invalid data.
695          */
696         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
697         orig_reg = reg;
698         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
699         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
700
701         /*
702          * Add space for the TXWI in front of the skb.
703          */
704         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
705
706         /*
707          * Register descriptor details in skb frame descriptor.
708          */
709         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
710         skbdesc->desc = entry->skb->data;
711         skbdesc->desc_len = TXWI_DESC_SIZE;
712
713         /*
714          * Add the TXWI for the beacon to the skb.
715          */
716         rt2800_write_tx_data(entry, txdesc);
717
718         /*
719          * Dump beacon to userspace through debugfs.
720          */
721         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
722
723         /*
724          * Write entire beacon with TXWI and padding to register.
725          */
726         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
727         if (padding_len && skb_pad(entry->skb, padding_len)) {
728                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
729                 /* skb freed by skb_pad() on failure */
730                 entry->skb = NULL;
731                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
732                 return;
733         }
734
735         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
736         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
737                                    entry->skb->len + padding_len);
738
739         /*
740          * Enable beaconing again.
741          */
742         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
743         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
744
745         /*
746          * Clean up beacon skb.
747          */
748         dev_kfree_skb_any(entry->skb);
749         entry->skb = NULL;
750 }
751 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
752
753 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
754                                                 unsigned int beacon_base)
755 {
756         int i;
757
758         /*
759          * For the Beacon base registers we only need to clear
760          * the whole TXWI which (when set to 0) will invalidate
761          * the entire beacon.
762          */
763         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
764                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
765 }
766
767 void rt2800_clear_beacon(struct queue_entry *entry)
768 {
769         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
770         u32 reg;
771
772         /*
773          * Disable beaconing while we are reloading the beacon data,
774          * otherwise we might be sending out invalid data.
775          */
776         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
777         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
778         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
779
780         /*
781          * Clear beacon.
782          */
783         rt2800_clear_beacon_register(rt2x00dev,
784                                      HW_BEACON_OFFSET(entry->entry_idx));
785
786         /*
787          * Enabled beaconing again.
788          */
789         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
790         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
791 }
792 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
793
794 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
795 const struct rt2x00debug rt2800_rt2x00debug = {
796         .owner  = THIS_MODULE,
797         .csr    = {
798                 .read           = rt2800_register_read,
799                 .write          = rt2800_register_write,
800                 .flags          = RT2X00DEBUGFS_OFFSET,
801                 .word_base      = CSR_REG_BASE,
802                 .word_size      = sizeof(u32),
803                 .word_count     = CSR_REG_SIZE / sizeof(u32),
804         },
805         .eeprom = {
806                 .read           = rt2x00_eeprom_read,
807                 .write          = rt2x00_eeprom_write,
808                 .word_base      = EEPROM_BASE,
809                 .word_size      = sizeof(u16),
810                 .word_count     = EEPROM_SIZE / sizeof(u16),
811         },
812         .bbp    = {
813                 .read           = rt2800_bbp_read,
814                 .write          = rt2800_bbp_write,
815                 .word_base      = BBP_BASE,
816                 .word_size      = sizeof(u8),
817                 .word_count     = BBP_SIZE / sizeof(u8),
818         },
819         .rf     = {
820                 .read           = rt2x00_rf_read,
821                 .write          = rt2800_rf_write,
822                 .word_base      = RF_BASE,
823                 .word_size      = sizeof(u32),
824                 .word_count     = RF_SIZE / sizeof(u32),
825         },
826 };
827 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
828 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
829
830 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
831 {
832         u32 reg;
833
834         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
835         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
836 }
837 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
838
839 #ifdef CONFIG_RT2X00_LIB_LEDS
840 static void rt2800_brightness_set(struct led_classdev *led_cdev,
841                                   enum led_brightness brightness)
842 {
843         struct rt2x00_led *led =
844             container_of(led_cdev, struct rt2x00_led, led_dev);
845         unsigned int enabled = brightness != LED_OFF;
846         unsigned int bg_mode =
847             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
848         unsigned int polarity =
849                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
850                                    EEPROM_FREQ_LED_POLARITY);
851         unsigned int ledmode =
852                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
853                                    EEPROM_FREQ_LED_MODE);
854         u32 reg;
855
856         /* Check for SoC (SOC devices don't support MCU requests) */
857         if (rt2x00_is_soc(led->rt2x00dev)) {
858                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
859
860                 /* Set LED Polarity */
861                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
862
863                 /* Set LED Mode */
864                 if (led->type == LED_TYPE_RADIO) {
865                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
866                                            enabled ? 3 : 0);
867                 } else if (led->type == LED_TYPE_ASSOC) {
868                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
869                                            enabled ? 3 : 0);
870                 } else if (led->type == LED_TYPE_QUALITY) {
871                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
872                                            enabled ? 3 : 0);
873                 }
874
875                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
876
877         } else {
878                 if (led->type == LED_TYPE_RADIO) {
879                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
880                                               enabled ? 0x20 : 0);
881                 } else if (led->type == LED_TYPE_ASSOC) {
882                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
883                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
884                 } else if (led->type == LED_TYPE_QUALITY) {
885                         /*
886                          * The brightness is divided into 6 levels (0 - 5),
887                          * The specs tell us the following levels:
888                          *      0, 1 ,3, 7, 15, 31
889                          * to determine the level in a simple way we can simply
890                          * work with bitshifting:
891                          *      (1 << level) - 1
892                          */
893                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
894                                               (1 << brightness / (LED_FULL / 6)) - 1,
895                                               polarity);
896                 }
897         }
898 }
899
900 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
901                      struct rt2x00_led *led, enum led_type type)
902 {
903         led->rt2x00dev = rt2x00dev;
904         led->type = type;
905         led->led_dev.brightness_set = rt2800_brightness_set;
906         led->flags = LED_INITIALIZED;
907 }
908 #endif /* CONFIG_RT2X00_LIB_LEDS */
909
910 /*
911  * Configuration handlers.
912  */
913 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
914                                const u8 *address,
915                                int wcid)
916 {
917         struct mac_wcid_entry wcid_entry;
918         u32 offset;
919
920         offset = MAC_WCID_ENTRY(wcid);
921
922         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
923         if (address)
924                 memcpy(wcid_entry.mac, address, ETH_ALEN);
925
926         rt2800_register_multiwrite(rt2x00dev, offset,
927                                       &wcid_entry, sizeof(wcid_entry));
928 }
929
930 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
931 {
932         u32 offset;
933         offset = MAC_WCID_ATTR_ENTRY(wcid);
934         rt2800_register_write(rt2x00dev, offset, 0);
935 }
936
937 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
938                                            int wcid, u32 bssidx)
939 {
940         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
941         u32 reg;
942
943         /*
944          * The BSS Idx numbers is split in a main value of 3 bits,
945          * and a extended field for adding one additional bit to the value.
946          */
947         rt2800_register_read(rt2x00dev, offset, &reg);
948         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
949         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
950                            (bssidx & 0x8) >> 3);
951         rt2800_register_write(rt2x00dev, offset, reg);
952 }
953
954 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
955                                            struct rt2x00lib_crypto *crypto,
956                                            struct ieee80211_key_conf *key)
957 {
958         struct mac_iveiv_entry iveiv_entry;
959         u32 offset;
960         u32 reg;
961
962         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
963
964         if (crypto->cmd == SET_KEY) {
965                 rt2800_register_read(rt2x00dev, offset, &reg);
966                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
967                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
968                 /*
969                  * Both the cipher as the BSS Idx numbers are split in a main
970                  * value of 3 bits, and a extended field for adding one additional
971                  * bit to the value.
972                  */
973                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
974                                    (crypto->cipher & 0x7));
975                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
976                                    (crypto->cipher & 0x8) >> 3);
977                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
978                 rt2800_register_write(rt2x00dev, offset, reg);
979         } else {
980                 /* Delete the cipher without touching the bssidx */
981                 rt2800_register_read(rt2x00dev, offset, &reg);
982                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
983                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
984                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
985                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
986                 rt2800_register_write(rt2x00dev, offset, reg);
987         }
988
989         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
990
991         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
992         if ((crypto->cipher == CIPHER_TKIP) ||
993             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
994             (crypto->cipher == CIPHER_AES))
995                 iveiv_entry.iv[3] |= 0x20;
996         iveiv_entry.iv[3] |= key->keyidx << 6;
997         rt2800_register_multiwrite(rt2x00dev, offset,
998                                       &iveiv_entry, sizeof(iveiv_entry));
999 }
1000
1001 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1002                              struct rt2x00lib_crypto *crypto,
1003                              struct ieee80211_key_conf *key)
1004 {
1005         struct hw_key_entry key_entry;
1006         struct rt2x00_field32 field;
1007         u32 offset;
1008         u32 reg;
1009
1010         if (crypto->cmd == SET_KEY) {
1011                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1012
1013                 memcpy(key_entry.key, crypto->key,
1014                        sizeof(key_entry.key));
1015                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1016                        sizeof(key_entry.tx_mic));
1017                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1018                        sizeof(key_entry.rx_mic));
1019
1020                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1021                 rt2800_register_multiwrite(rt2x00dev, offset,
1022                                               &key_entry, sizeof(key_entry));
1023         }
1024
1025         /*
1026          * The cipher types are stored over multiple registers
1027          * starting with SHARED_KEY_MODE_BASE each word will have
1028          * 32 bits and contains the cipher types for 2 bssidx each.
1029          * Using the correct defines correctly will cause overhead,
1030          * so just calculate the correct offset.
1031          */
1032         field.bit_offset = 4 * (key->hw_key_idx % 8);
1033         field.bit_mask = 0x7 << field.bit_offset;
1034
1035         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1036
1037         rt2800_register_read(rt2x00dev, offset, &reg);
1038         rt2x00_set_field32(&reg, field,
1039                            (crypto->cmd == SET_KEY) * crypto->cipher);
1040         rt2800_register_write(rt2x00dev, offset, reg);
1041
1042         /*
1043          * Update WCID information
1044          */
1045         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1046         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1047                                        crypto->bssidx);
1048         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1049
1050         return 0;
1051 }
1052 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1053
1054 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1055 {
1056         struct mac_wcid_entry wcid_entry;
1057         int idx;
1058         u32 offset;
1059
1060         /*
1061          * Search for the first free WCID entry and return the corresponding
1062          * index.
1063          *
1064          * Make sure the WCID starts _after_ the last possible shared key
1065          * entry (>32).
1066          *
1067          * Since parts of the pairwise key table might be shared with
1068          * the beacon frame buffers 6 & 7 we should only write into the
1069          * first 222 entries.
1070          */
1071         for (idx = 33; idx <= 222; idx++) {
1072                 offset = MAC_WCID_ENTRY(idx);
1073                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1074                                           sizeof(wcid_entry));
1075                 if (is_broadcast_ether_addr(wcid_entry.mac))
1076                         return idx;
1077         }
1078
1079         /*
1080          * Use -1 to indicate that we don't have any more space in the WCID
1081          * table.
1082          */
1083         return -1;
1084 }
1085
1086 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1087                                struct rt2x00lib_crypto *crypto,
1088                                struct ieee80211_key_conf *key)
1089 {
1090         struct hw_key_entry key_entry;
1091         u32 offset;
1092
1093         if (crypto->cmd == SET_KEY) {
1094                 /*
1095                  * Allow key configuration only for STAs that are
1096                  * known by the hw.
1097                  */
1098                 if (crypto->wcid < 0)
1099                         return -ENOSPC;
1100                 key->hw_key_idx = crypto->wcid;
1101
1102                 memcpy(key_entry.key, crypto->key,
1103                        sizeof(key_entry.key));
1104                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1105                        sizeof(key_entry.tx_mic));
1106                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1107                        sizeof(key_entry.rx_mic));
1108
1109                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1110                 rt2800_register_multiwrite(rt2x00dev, offset,
1111                                               &key_entry, sizeof(key_entry));
1112         }
1113
1114         /*
1115          * Update WCID information
1116          */
1117         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1118
1119         return 0;
1120 }
1121 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1122
1123 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1124                    struct ieee80211_sta *sta)
1125 {
1126         int wcid;
1127         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1128
1129         /*
1130          * Find next free WCID.
1131          */
1132         wcid = rt2800_find_wcid(rt2x00dev);
1133
1134         /*
1135          * Store selected wcid even if it is invalid so that we can
1136          * later decide if the STA is uploaded into the hw.
1137          */
1138         sta_priv->wcid = wcid;
1139
1140         /*
1141          * No space left in the device, however, we can still communicate
1142          * with the STA -> No error.
1143          */
1144         if (wcid < 0)
1145                 return 0;
1146
1147         /*
1148          * Clean up WCID attributes and write STA address to the device.
1149          */
1150         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1151         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1152         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1153                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1154         return 0;
1155 }
1156 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1157
1158 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1159 {
1160         /*
1161          * Remove WCID entry, no need to clean the attributes as they will
1162          * get renewed when the WCID is reused.
1163          */
1164         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1165
1166         return 0;
1167 }
1168 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1169
1170 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1171                           const unsigned int filter_flags)
1172 {
1173         u32 reg;
1174
1175         /*
1176          * Start configuration steps.
1177          * Note that the version error will always be dropped
1178          * and broadcast frames will always be accepted since
1179          * there is no filter for it at this time.
1180          */
1181         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1182         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1183                            !(filter_flags & FIF_FCSFAIL));
1184         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1185                            !(filter_flags & FIF_PLCPFAIL));
1186         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1187                            !(filter_flags & FIF_PROMISC_IN_BSS));
1188         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1189         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1190         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1191                            !(filter_flags & FIF_ALLMULTI));
1192         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1193         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1194         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1195                            !(filter_flags & FIF_CONTROL));
1196         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1197                            !(filter_flags & FIF_CONTROL));
1198         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1199                            !(filter_flags & FIF_CONTROL));
1200         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1201                            !(filter_flags & FIF_CONTROL));
1202         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1203                            !(filter_flags & FIF_CONTROL));
1204         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1205                            !(filter_flags & FIF_PSPOLL));
1206         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1207         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1208         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1209                            !(filter_flags & FIF_CONTROL));
1210         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1211 }
1212 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1213
1214 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1215                         struct rt2x00intf_conf *conf, const unsigned int flags)
1216 {
1217         u32 reg;
1218         bool update_bssid = false;
1219
1220         if (flags & CONFIG_UPDATE_TYPE) {
1221                 /*
1222                  * Enable synchronisation.
1223                  */
1224                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1225                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1226                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1227
1228                 if (conf->sync == TSF_SYNC_AP_NONE) {
1229                         /*
1230                          * Tune beacon queue transmit parameters for AP mode
1231                          */
1232                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1233                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1234                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1235                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1236                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1237                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1238                 } else {
1239                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1240                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1241                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1242                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1243                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1244                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1245                 }
1246         }
1247
1248         if (flags & CONFIG_UPDATE_MAC) {
1249                 if (flags & CONFIG_UPDATE_TYPE &&
1250                     conf->sync == TSF_SYNC_AP_NONE) {
1251                         /*
1252                          * The BSSID register has to be set to our own mac
1253                          * address in AP mode.
1254                          */
1255                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1256                         update_bssid = true;
1257                 }
1258
1259                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1260                         reg = le32_to_cpu(conf->mac[1]);
1261                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1262                         conf->mac[1] = cpu_to_le32(reg);
1263                 }
1264
1265                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1266                                               conf->mac, sizeof(conf->mac));
1267         }
1268
1269         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1270                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1271                         reg = le32_to_cpu(conf->bssid[1]);
1272                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1273                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1274                         conf->bssid[1] = cpu_to_le32(reg);
1275                 }
1276
1277                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1278                                               conf->bssid, sizeof(conf->bssid));
1279         }
1280 }
1281 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1282
1283 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1284                                     struct rt2x00lib_erp *erp)
1285 {
1286         bool any_sta_nongf = !!(erp->ht_opmode &
1287                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1288         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1289         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1290         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1291         u32 reg;
1292
1293         /* default protection rate for HT20: OFDM 24M */
1294         mm20_rate = gf20_rate = 0x4004;
1295
1296         /* default protection rate for HT40: duplicate OFDM 24M */
1297         mm40_rate = gf40_rate = 0x4084;
1298
1299         switch (protection) {
1300         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1301                 /*
1302                  * All STAs in this BSS are HT20/40 but there might be
1303                  * STAs not supporting greenfield mode.
1304                  * => Disable protection for HT transmissions.
1305                  */
1306                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1307
1308                 break;
1309         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1310                 /*
1311                  * All STAs in this BSS are HT20 or HT20/40 but there
1312                  * might be STAs not supporting greenfield mode.
1313                  * => Protect all HT40 transmissions.
1314                  */
1315                 mm20_mode = gf20_mode = 0;
1316                 mm40_mode = gf40_mode = 2;
1317
1318                 break;
1319         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1320                 /*
1321                  * Nonmember protection:
1322                  * According to 802.11n we _should_ protect all
1323                  * HT transmissions (but we don't have to).
1324                  *
1325                  * But if cts_protection is enabled we _shall_ protect
1326                  * all HT transmissions using a CCK rate.
1327                  *
1328                  * And if any station is non GF we _shall_ protect
1329                  * GF transmissions.
1330                  *
1331                  * We decide to protect everything
1332                  * -> fall through to mixed mode.
1333                  */
1334         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1335                 /*
1336                  * Legacy STAs are present
1337                  * => Protect all HT transmissions.
1338                  */
1339                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1340
1341                 /*
1342                  * If erp protection is needed we have to protect HT
1343                  * transmissions with CCK 11M long preamble.
1344                  */
1345                 if (erp->cts_protection) {
1346                         /* don't duplicate RTS/CTS in CCK mode */
1347                         mm20_rate = mm40_rate = 0x0003;
1348                         gf20_rate = gf40_rate = 0x0003;
1349                 }
1350                 break;
1351         }
1352
1353         /* check for STAs not supporting greenfield mode */
1354         if (any_sta_nongf)
1355                 gf20_mode = gf40_mode = 2;
1356
1357         /* Update HT protection config */
1358         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1359         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1360         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1361         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1362
1363         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1364         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1365         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1366         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1367
1368         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1369         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1370         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1371         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1372
1373         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1374         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1375         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1376         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1377 }
1378
1379 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1380                        u32 changed)
1381 {
1382         u32 reg;
1383
1384         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1385                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1386                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1387                                    !!erp->short_preamble);
1388                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1389                                    !!erp->short_preamble);
1390                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1391         }
1392
1393         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1394                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1395                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1396                                    erp->cts_protection ? 2 : 0);
1397                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1398         }
1399
1400         if (changed & BSS_CHANGED_BASIC_RATES) {
1401                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1402                                          erp->basic_rates);
1403                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1404         }
1405
1406         if (changed & BSS_CHANGED_ERP_SLOT) {
1407                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1408                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1409                                    erp->slot_time);
1410                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1411
1412                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1413                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1414                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1415         }
1416
1417         if (changed & BSS_CHANGED_BEACON_INT) {
1418                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1419                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1420                                    erp->beacon_int * 16);
1421                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1422         }
1423
1424         if (changed & BSS_CHANGED_HT)
1425                 rt2800_config_ht_opmode(rt2x00dev, erp);
1426 }
1427 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1428
1429 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1430 {
1431         u32 reg;
1432         u16 eeprom;
1433         u8 led_ctrl, led_g_mode, led_r_mode;
1434
1435         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1436         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1437                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1438                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1439         } else {
1440                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1441                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1442         }
1443         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1444
1445         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1446         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1447         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1448         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1449             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1450                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1451                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1452                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1453                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1454                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1455                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1456                 } else {
1457                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1458                                            (led_g_mode << 2) | led_r_mode, 1);
1459                 }
1460         }
1461 }
1462
1463 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1464                                      enum antenna ant)
1465 {
1466         u32 reg;
1467         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1468         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1469
1470         if (rt2x00_is_pci(rt2x00dev)) {
1471                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1472                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1473                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1474         } else if (rt2x00_is_usb(rt2x00dev))
1475                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1476                                    eesk_pin, 0);
1477
1478         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1479         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1480         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1481         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1482 }
1483
1484 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1485 {
1486         u8 r1;
1487         u8 r3;
1488         u16 eeprom;
1489
1490         rt2800_bbp_read(rt2x00dev, 1, &r1);
1491         rt2800_bbp_read(rt2x00dev, 3, &r3);
1492
1493         if (rt2x00_rt(rt2x00dev, RT3572) &&
1494             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1495                 rt2800_config_3572bt_ant(rt2x00dev);
1496
1497         /*
1498          * Configure the TX antenna.
1499          */
1500         switch (ant->tx_chain_num) {
1501         case 1:
1502                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1503                 break;
1504         case 2:
1505                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1506                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1507                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1508                 else
1509                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1510                 break;
1511         case 3:
1512                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1513                 break;
1514         }
1515
1516         /*
1517          * Configure the RX antenna.
1518          */
1519         switch (ant->rx_chain_num) {
1520         case 1:
1521                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1522                     rt2x00_rt(rt2x00dev, RT3090) ||
1523                     rt2x00_rt(rt2x00dev, RT3390)) {
1524                         rt2x00_eeprom_read(rt2x00dev,
1525                                            EEPROM_NIC_CONF1, &eeprom);
1526                         if (rt2x00_get_field16(eeprom,
1527                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1528                                 rt2800_set_ant_diversity(rt2x00dev,
1529                                                 rt2x00dev->default_ant.rx);
1530                 }
1531                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1532                 break;
1533         case 2:
1534                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1535                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1536                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1537                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1538                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1539                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1540                 } else {
1541                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1542                 }
1543                 break;
1544         case 3:
1545                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1546                 break;
1547         }
1548
1549         rt2800_bbp_write(rt2x00dev, 3, r3);
1550         rt2800_bbp_write(rt2x00dev, 1, r1);
1551 }
1552 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1553
1554 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1555                                    struct rt2x00lib_conf *libconf)
1556 {
1557         u16 eeprom;
1558         short lna_gain;
1559
1560         if (libconf->rf.channel <= 14) {
1561                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1562                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1563         } else if (libconf->rf.channel <= 64) {
1564                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1565                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1566         } else if (libconf->rf.channel <= 128) {
1567                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1568                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1569         } else {
1570                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1571                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1572         }
1573
1574         rt2x00dev->lna_gain = lna_gain;
1575 }
1576
1577 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1578                                          struct ieee80211_conf *conf,
1579                                          struct rf_channel *rf,
1580                                          struct channel_info *info)
1581 {
1582         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1583
1584         if (rt2x00dev->default_ant.tx_chain_num == 1)
1585                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1586
1587         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1588                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1589                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1590         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1591                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1592
1593         if (rf->channel > 14) {
1594                 /*
1595                  * When TX power is below 0, we should increase it by 7 to
1596                  * make it a positive value (Minimum value is -7).
1597                  * However this means that values between 0 and 7 have
1598                  * double meaning, and we should set a 7DBm boost flag.
1599                  */
1600                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1601                                    (info->default_power1 >= 0));
1602
1603                 if (info->default_power1 < 0)
1604                         info->default_power1 += 7;
1605
1606                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1607
1608                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1609                                    (info->default_power2 >= 0));
1610
1611                 if (info->default_power2 < 0)
1612                         info->default_power2 += 7;
1613
1614                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1615         } else {
1616                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1617                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1618         }
1619
1620         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1621
1622         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1623         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1624         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1625         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1626
1627         udelay(200);
1628
1629         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1630         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1631         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1632         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1633
1634         udelay(200);
1635
1636         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1637         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1638         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1639         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1640 }
1641
1642 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1643                                          struct ieee80211_conf *conf,
1644                                          struct rf_channel *rf,
1645                                          struct channel_info *info)
1646 {
1647         u8 rfcsr;
1648
1649         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1650         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1651
1652         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1653         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1654         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1655
1656         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1657         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1658         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1659
1660         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1661         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1662         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1663
1664         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1665         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1666         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1667
1668         rt2800_rfcsr_write(rt2x00dev, 24,
1669                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1670
1671         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1672         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1673         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1674 }
1675
1676 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1677                                          struct ieee80211_conf *conf,
1678                                          struct rf_channel *rf,
1679                                          struct channel_info *info)
1680 {
1681         u8 rfcsr;
1682         u32 reg;
1683
1684         if (rf->channel <= 14) {
1685                 rt2800_bbp_write(rt2x00dev, 25, 0x15);
1686                 rt2800_bbp_write(rt2x00dev, 26, 0x85);
1687         } else {
1688                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1689                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1690         }
1691
1692         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1693         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1694
1695         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1696         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1697         if (rf->channel <= 14)
1698                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1699         else
1700                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1701         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1702
1703         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1704         if (rf->channel <= 14)
1705                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1706         else
1707                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1708         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1709
1710         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1711         if (rf->channel <= 14) {
1712                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1713                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1714                                 (info->default_power1 & 0x3) |
1715                                 ((info->default_power1 & 0xC) << 1));
1716         } else {
1717                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1718                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1719                                 (info->default_power1 & 0x3) |
1720                                 ((info->default_power1 & 0xC) << 1));
1721         }
1722         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1723
1724         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1725         if (rf->channel <= 14) {
1726                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1727                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1728                                 (info->default_power2 & 0x3) |
1729                                 ((info->default_power2 & 0xC) << 1));
1730         } else {
1731                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1732                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1733                                 (info->default_power2 & 0x3) |
1734                                 ((info->default_power2 & 0xC) << 1));
1735         }
1736         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1737
1738         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1739         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1740         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1741         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1742         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1743         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1744         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1745                 if (rf->channel <= 14) {
1746                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1747                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1748                 }
1749                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1750                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1751         } else {
1752                 switch (rt2x00dev->default_ant.tx_chain_num) {
1753                 case 1:
1754                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1755                 case 2:
1756                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1757                         break;
1758                 }
1759
1760                 switch (rt2x00dev->default_ant.rx_chain_num) {
1761                 case 1:
1762                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1763                 case 2:
1764                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1765                         break;
1766                 }
1767         }
1768         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1769
1770         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1771         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1772         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1773
1774         rt2800_rfcsr_write(rt2x00dev, 24,
1775                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1776         rt2800_rfcsr_write(rt2x00dev, 31,
1777                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1778
1779         if (rf->channel <= 14) {
1780                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1781                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1782                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1783                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1784                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1785                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
1786                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1787                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1788                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1789                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1790                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1791                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1792                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1793         } else {
1794                 rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
1795                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1796                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1797                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1798                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1799                 rt2800_rfcsr_write(rt2x00dev, 16, 0x7a);
1800                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1801                 if (rf->channel <= 64) {
1802                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1803                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1804                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1805                 } else if (rf->channel <= 128) {
1806                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1807                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1808                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1809                 } else {
1810                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1811                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1812                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1813                 }
1814                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1815                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1816                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1817         }
1818
1819         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1820         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1821         if (rf->channel <= 14)
1822                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1823         else
1824                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1825         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1826
1827         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1828         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1829         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1830 }
1831
1832 #define RT5390_POWER_BOUND     0x27
1833 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1834
1835 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1836                                          struct ieee80211_conf *conf,
1837                                          struct rf_channel *rf,
1838                                          struct channel_info *info)
1839 {
1840         u8 rfcsr;
1841
1842         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1843         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1844         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1845         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1846         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1847
1848         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1849         if (info->default_power1 > RT5390_POWER_BOUND)
1850                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1851         else
1852                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1853         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1854
1855         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1856         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1857         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1858         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1859         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1860         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1861
1862         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1863         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1864                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1865                                   RT5390_FREQ_OFFSET_BOUND);
1866         else
1867                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1868         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1869
1870         if (rf->channel <= 14) {
1871                 int idx = rf->channel-1;
1872
1873                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1874                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1875                                 /* r55/r59 value array of channel 1~14 */
1876                                 static const char r55_bt_rev[] = {0x83, 0x83,
1877                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1878                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1879                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1880                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1881                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1882
1883                                 rt2800_rfcsr_write(rt2x00dev, 55,
1884                                                    r55_bt_rev[idx]);
1885                                 rt2800_rfcsr_write(rt2x00dev, 59,
1886                                                    r59_bt_rev[idx]);
1887                         } else {
1888                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1889                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1890                                         0x88, 0x88, 0x86, 0x85, 0x84};
1891
1892                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1893                         }
1894                 } else {
1895                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1896                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1897                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1898                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1899                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1900                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1901                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1902
1903                                 rt2800_rfcsr_write(rt2x00dev, 55,
1904                                                    r55_nonbt_rev[idx]);
1905                                 rt2800_rfcsr_write(rt2x00dev, 59,
1906                                                    r59_nonbt_rev[idx]);
1907                         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1908                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1909                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1910                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1911
1912                                 rt2800_rfcsr_write(rt2x00dev, 59,
1913                                                    r59_non_bt[idx]);
1914                         }
1915                 }
1916         }
1917
1918         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1919         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1920         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1921         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1922
1923         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1924         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1925         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1926 }
1927
1928 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1929                                   struct ieee80211_conf *conf,
1930                                   struct rf_channel *rf,
1931                                   struct channel_info *info)
1932 {
1933         u32 reg;
1934         unsigned int tx_pin;
1935         u8 bbp;
1936
1937         if (rf->channel <= 14) {
1938                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1939                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1940         } else {
1941                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1942                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1943         }
1944
1945         if (rt2x00_rf(rt2x00dev, RF2020) ||
1946             rt2x00_rf(rt2x00dev, RF3020) ||
1947             rt2x00_rf(rt2x00dev, RF3021) ||
1948             rt2x00_rf(rt2x00dev, RF3022) ||
1949             rt2x00_rf(rt2x00dev, RF3320))
1950                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1951         else if (rt2x00_rf(rt2x00dev, RF3052))
1952                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
1953         else if (rt2x00_rf(rt2x00dev, RF5370) ||
1954                  rt2x00_rf(rt2x00dev, RF5390))
1955                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1956         else
1957                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1958
1959         /*
1960          * Change BBP settings
1961          */
1962         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1963         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1964         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1965         rt2800_bbp_write(rt2x00dev, 86, 0);
1966
1967         if (rf->channel <= 14) {
1968                 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1969                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
1970                                      &rt2x00dev->cap_flags)) {
1971                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1972                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1973                         } else {
1974                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1975                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1976                         }
1977                 }
1978         } else {
1979                 if (rt2x00_rt(rt2x00dev, RT3572))
1980                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
1981                 else
1982                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1983
1984                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
1985                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1986                 else
1987                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1988         }
1989
1990         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1991         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1992         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1993         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1994         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1995
1996         if (rt2x00_rt(rt2x00dev, RT3572))
1997                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
1998
1999         tx_pin = 0;
2000
2001         /* Turn on unused PA or LNA when not using 1T or 1R */
2002         if (rt2x00dev->default_ant.tx_chain_num == 2) {
2003                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2004                                    rf->channel > 14);
2005                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2006                                    rf->channel <= 14);
2007         }
2008
2009         /* Turn on unused PA or LNA when not using 1T or 1R */
2010         if (rt2x00dev->default_ant.rx_chain_num == 2) {
2011                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2012                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2013         }
2014
2015         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2016         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2017         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2018         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2019         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2020                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2021         else
2022                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2023                                    rf->channel <= 14);
2024         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2025
2026         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2027
2028         if (rt2x00_rt(rt2x00dev, RT3572))
2029                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2030
2031         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2032         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2033         rt2800_bbp_write(rt2x00dev, 4, bbp);
2034
2035         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2036         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2037         rt2800_bbp_write(rt2x00dev, 3, bbp);
2038
2039         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2040                 if (conf_is_ht40(conf)) {
2041                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2042                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2043                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2044                 } else {
2045                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2046                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2047                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2048                 }
2049         }
2050
2051         msleep(1);
2052
2053         /*
2054          * Clear channel statistic counters
2055          */
2056         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2057         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2058         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2059 }
2060
2061 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2062 {
2063         u8 tssi_bounds[9];
2064         u8 current_tssi;
2065         u16 eeprom;
2066         u8 step;
2067         int i;
2068
2069         /*
2070          * Read TSSI boundaries for temperature compensation from
2071          * the EEPROM.
2072          *
2073          * Array idx               0    1    2    3    4    5    6    7    8
2074          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2075          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2076          */
2077         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2078                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2079                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2080                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2081                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2082                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2083
2084                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2085                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2086                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2087                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2088                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2089
2090                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2091                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2092                                         EEPROM_TSSI_BOUND_BG3_REF);
2093                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2094                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2095
2096                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2097                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2098                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2099                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2100                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2101
2102                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2103                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2104                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2105
2106                 step = rt2x00_get_field16(eeprom,
2107                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2108         } else {
2109                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2110                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2111                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2112                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2113                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2114
2115                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2116                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2117                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2118                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2119                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2120
2121                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2122                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2123                                         EEPROM_TSSI_BOUND_A3_REF);
2124                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2125                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2126
2127                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2128                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2129                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2130                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2131                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2132
2133                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2134                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2135                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2136
2137                 step = rt2x00_get_field16(eeprom,
2138                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2139         }
2140
2141         /*
2142          * Check if temperature compensation is supported.
2143          */
2144         if (tssi_bounds[4] == 0xff)
2145                 return 0;
2146
2147         /*
2148          * Read current TSSI (BBP 49).
2149          */
2150         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2151
2152         /*
2153          * Compare TSSI value (BBP49) with the compensation boundaries
2154          * from the EEPROM and increase or decrease tx power.
2155          */
2156         for (i = 0; i <= 3; i++) {
2157                 if (current_tssi > tssi_bounds[i])
2158                         break;
2159         }
2160
2161         if (i == 4) {
2162                 for (i = 8; i >= 5; i--) {
2163                         if (current_tssi < tssi_bounds[i])
2164                                 break;
2165                 }
2166         }
2167
2168         return (i - 4) * step;
2169 }
2170
2171 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2172                                       enum ieee80211_band band)
2173 {
2174         u16 eeprom;
2175         u8 comp_en;
2176         u8 comp_type;
2177         int comp_value = 0;
2178
2179         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2180
2181         /*
2182          * HT40 compensation not required.
2183          */
2184         if (eeprom == 0xffff ||
2185             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2186                 return 0;
2187
2188         if (band == IEEE80211_BAND_2GHZ) {
2189                 comp_en = rt2x00_get_field16(eeprom,
2190                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2191                 if (comp_en) {
2192                         comp_type = rt2x00_get_field16(eeprom,
2193                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2194                         comp_value = rt2x00_get_field16(eeprom,
2195                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2196                         if (!comp_type)
2197                                 comp_value = -comp_value;
2198                 }
2199         } else {
2200                 comp_en = rt2x00_get_field16(eeprom,
2201                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2202                 if (comp_en) {
2203                         comp_type = rt2x00_get_field16(eeprom,
2204                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2205                         comp_value = rt2x00_get_field16(eeprom,
2206                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2207                         if (!comp_type)
2208                                 comp_value = -comp_value;
2209                 }
2210         }
2211
2212         return comp_value;
2213 }
2214
2215 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2216                                    enum ieee80211_band band, int power_level,
2217                                    u8 txpower, int delta)
2218 {
2219         u32 reg;
2220         u16 eeprom;
2221         u8 criterion;
2222         u8 eirp_txpower;
2223         u8 eirp_txpower_criterion;
2224         u8 reg_limit;
2225
2226         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2227                 return txpower;
2228
2229         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2230                 /*
2231                  * Check if eirp txpower exceed txpower_limit.
2232                  * We use OFDM 6M as criterion and its eirp txpower
2233                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2234                  * .11b data rate need add additional 4dbm
2235                  * when calculating eirp txpower.
2236                  */
2237                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2238                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2239
2240                 rt2x00_eeprom_read(rt2x00dev,
2241                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2242
2243                 if (band == IEEE80211_BAND_2GHZ)
2244                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2245                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2246                 else
2247                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2248                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2249
2250                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2251                                (is_rate_b ? 4 : 0) + delta;
2252
2253                 reg_limit = (eirp_txpower > power_level) ?
2254                                         (eirp_txpower - power_level) : 0;
2255         } else
2256                 reg_limit = 0;
2257
2258         return txpower + delta - reg_limit;
2259 }
2260
2261 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2262                                   enum ieee80211_band band,
2263                                   int power_level)
2264 {
2265         u8 txpower;
2266         u16 eeprom;
2267         int i, is_rate_b;
2268         u32 reg;
2269         u8 r1;
2270         u32 offset;
2271         int delta;
2272
2273         /*
2274          * Calculate HT40 compensation delta
2275          */
2276         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2277
2278         /*
2279          * calculate temperature compensation delta
2280          */
2281         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2282
2283         /*
2284          * set to normal bbp tx power control mode: +/- 0dBm
2285          */
2286         rt2800_bbp_read(rt2x00dev, 1, &r1);
2287         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2288         rt2800_bbp_write(rt2x00dev, 1, r1);
2289         offset = TX_PWR_CFG_0;
2290
2291         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2292                 /* just to be safe */
2293                 if (offset > TX_PWR_CFG_4)
2294                         break;
2295
2296                 rt2800_register_read(rt2x00dev, offset, &reg);
2297
2298                 /* read the next four txpower values */
2299                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2300                                    &eeprom);
2301
2302                 is_rate_b = i ? 0 : 1;
2303                 /*
2304                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2305                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2306                  * TX_PWR_CFG_4: unknown
2307                  */
2308                 txpower = rt2x00_get_field16(eeprom,
2309                                              EEPROM_TXPOWER_BYRATE_RATE0);
2310                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2311                                              power_level, txpower, delta);
2312                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2313
2314                 /*
2315                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2316                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2317                  * TX_PWR_CFG_4: unknown
2318                  */
2319                 txpower = rt2x00_get_field16(eeprom,
2320                                              EEPROM_TXPOWER_BYRATE_RATE1);
2321                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2322                                              power_level, txpower, delta);
2323                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2324
2325                 /*
2326                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2327                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2328                  * TX_PWR_CFG_4: unknown
2329                  */
2330                 txpower = rt2x00_get_field16(eeprom,
2331                                              EEPROM_TXPOWER_BYRATE_RATE2);
2332                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2333                                              power_level, txpower, delta);
2334                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2335
2336                 /*
2337                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2338                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2339                  * TX_PWR_CFG_4: unknown
2340                  */
2341                 txpower = rt2x00_get_field16(eeprom,
2342                                              EEPROM_TXPOWER_BYRATE_RATE3);
2343                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2344                                              power_level, txpower, delta);
2345                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2346
2347                 /* read the next four txpower values */
2348                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2349                                    &eeprom);
2350
2351                 is_rate_b = 0;
2352                 /*
2353                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2354                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2355                  * TX_PWR_CFG_4: unknown
2356                  */
2357                 txpower = rt2x00_get_field16(eeprom,
2358                                              EEPROM_TXPOWER_BYRATE_RATE0);
2359                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2360                                              power_level, txpower, delta);
2361                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2362
2363                 /*
2364                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2365                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2366                  * TX_PWR_CFG_4: unknown
2367                  */
2368                 txpower = rt2x00_get_field16(eeprom,
2369                                              EEPROM_TXPOWER_BYRATE_RATE1);
2370                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2371                                              power_level, txpower, delta);
2372                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2373
2374                 /*
2375                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2376                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2377                  * TX_PWR_CFG_4: unknown
2378                  */
2379                 txpower = rt2x00_get_field16(eeprom,
2380                                              EEPROM_TXPOWER_BYRATE_RATE2);
2381                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2382                                              power_level, txpower, delta);
2383                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2384
2385                 /*
2386                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2387                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2388                  * TX_PWR_CFG_4: unknown
2389                  */
2390                 txpower = rt2x00_get_field16(eeprom,
2391                                              EEPROM_TXPOWER_BYRATE_RATE3);
2392                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2393                                              power_level, txpower, delta);
2394                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2395
2396                 rt2800_register_write(rt2x00dev, offset, reg);
2397
2398                 /* next TX_PWR_CFG register */
2399                 offset += 4;
2400         }
2401 }
2402
2403 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2404 {
2405         rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2406                               rt2x00dev->tx_power);
2407 }
2408 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2409
2410 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2411                                       struct rt2x00lib_conf *libconf)
2412 {
2413         u32 reg;
2414
2415         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2416         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2417                            libconf->conf->short_frame_max_tx_count);
2418         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2419                            libconf->conf->long_frame_max_tx_count);
2420         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2421 }
2422
2423 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2424                              struct rt2x00lib_conf *libconf)
2425 {
2426         enum dev_state state =
2427             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2428                 STATE_SLEEP : STATE_AWAKE;
2429         u32 reg;
2430
2431         if (state == STATE_SLEEP) {
2432                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2433
2434                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2435                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2436                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2437                                    libconf->conf->listen_interval - 1);
2438                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2439                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2440
2441                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2442         } else {
2443                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2444                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2445                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2446                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2447                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2448
2449                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2450         }
2451 }
2452
2453 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2454                    struct rt2x00lib_conf *libconf,
2455                    const unsigned int flags)
2456 {
2457         /* Always recalculate LNA gain before changing configuration */
2458         rt2800_config_lna_gain(rt2x00dev, libconf);
2459
2460         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2461                 rt2800_config_channel(rt2x00dev, libconf->conf,
2462                                       &libconf->rf, &libconf->channel);
2463                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2464                                       libconf->conf->power_level);
2465         }
2466         if (flags & IEEE80211_CONF_CHANGE_POWER)
2467                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2468                                       libconf->conf->power_level);
2469         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2470                 rt2800_config_retry_limit(rt2x00dev, libconf);
2471         if (flags & IEEE80211_CONF_CHANGE_PS)
2472                 rt2800_config_ps(rt2x00dev, libconf);
2473 }
2474 EXPORT_SYMBOL_GPL(rt2800_config);
2475
2476 /*
2477  * Link tuning
2478  */
2479 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2480 {
2481         u32 reg;
2482
2483         /*
2484          * Update FCS error count from register.
2485          */
2486         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2487         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2488 }
2489 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2490
2491 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2492 {
2493         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2494                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2495                     rt2x00_rt(rt2x00dev, RT3071) ||
2496                     rt2x00_rt(rt2x00dev, RT3090) ||
2497                     rt2x00_rt(rt2x00dev, RT3390) ||
2498                     rt2x00_rt(rt2x00dev, RT5390))
2499                         return 0x1c + (2 * rt2x00dev->lna_gain);
2500                 else
2501                         return 0x2e + rt2x00dev->lna_gain;
2502         }
2503
2504         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2505                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2506         else
2507                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2508 }
2509
2510 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2511                                   struct link_qual *qual, u8 vgc_level)
2512 {
2513         if (qual->vgc_level != vgc_level) {
2514                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2515                 qual->vgc_level = vgc_level;
2516                 qual->vgc_level_reg = vgc_level;
2517         }
2518 }
2519
2520 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2521 {
2522         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2523 }
2524 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2525
2526 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2527                        const u32 count)
2528 {
2529         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2530                 return;
2531
2532         /*
2533          * When RSSI is better then -80 increase VGC level with 0x10
2534          */
2535         rt2800_set_vgc(rt2x00dev, qual,
2536                        rt2800_get_default_vgc(rt2x00dev) +
2537                        ((qual->rssi > -80) * 0x10));
2538 }
2539 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2540
2541 /*
2542  * Initialization functions.
2543  */
2544 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2545 {
2546         u32 reg;
2547         u16 eeprom;
2548         unsigned int i;
2549         int ret;
2550
2551         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2552         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2553         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2554         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2555         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2556         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2557         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2558
2559         ret = rt2800_drv_init_registers(rt2x00dev);
2560         if (ret)
2561                 return ret;
2562
2563         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2564         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2565         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2566         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2567         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2568         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2569
2570         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2571         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2572         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2573         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2574         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2575         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2576
2577         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2578         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2579
2580         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2581
2582         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2583         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2584         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2585         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2586         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2587         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2588         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2589         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2590
2591         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2592
2593         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2594         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2595         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2596         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2597
2598         if (rt2x00_rt(rt2x00dev, RT3071) ||
2599             rt2x00_rt(rt2x00dev, RT3090) ||
2600             rt2x00_rt(rt2x00dev, RT3390)) {
2601                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2602                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2603                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2604                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2605                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2606                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2607                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2608                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2609                                                       0x0000002c);
2610                         else
2611                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2612                                                       0x0000000f);
2613                 } else {
2614                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2615                 }
2616         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2617                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2618
2619                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2620                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2621                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2622                 } else {
2623                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2624                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2625                 }
2626         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2627                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2628                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2629                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2630         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2631                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2632                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2633         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2634                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2635                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2636                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2637         } else {
2638                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2639                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2640         }
2641
2642         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2643         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2644         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2645         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2646         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2647         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2648         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2649         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2650         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2651         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2652
2653         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2654         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2655         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2656         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2657         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2658
2659         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2660         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2661         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2662             rt2x00_rt(rt2x00dev, RT2883) ||
2663             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2664                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2665         else
2666                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2667         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2668         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2669         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2670
2671         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2672         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2673         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2674         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2675         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2676         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2677         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2678         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2679         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2680
2681         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2682
2683         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2684         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2685         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2686         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2687         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2688         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2689         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2690         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2691
2692         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2693         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2694         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2695         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2696         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2697         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2698         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2699         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2700         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2701
2702         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2703         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2704         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2705         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2706         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2707         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2708         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2709         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2710         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2711         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2712         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2713         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2714
2715         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2716         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2717         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2718         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2719         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2720         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2721         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2722         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2723         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2724         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2725         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2726         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2727
2728         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2729         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2730         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2731         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2732         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2733         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2734         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2735         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2736         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2737         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2738         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2739         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2740
2741         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2742         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2743         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2744         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2745         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2746         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2747         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2748         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2749         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2750         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2751         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2752         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2753
2754         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2755         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2756         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2757         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2758         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2759         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2760         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2761         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2762         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2763         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2764         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2765         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2766
2767         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2768         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2769         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2770         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2771         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2772         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2773         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2774         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2775         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2776         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2777         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2778         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2779
2780         if (rt2x00_is_usb(rt2x00dev)) {
2781                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2782
2783                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2784                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2785                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2786                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2787                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2788                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2789                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2790                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2791                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2792                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2793                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2794         }
2795
2796         /*
2797          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2798          * although it is reserved.
2799          */
2800         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2801         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2802         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2803         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2804         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2805         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2806         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2807         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2808         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2809         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2810         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2811         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2812
2813         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2814
2815         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2816         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2817         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2818                            IEEE80211_MAX_RTS_THRESHOLD);
2819         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2820         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2821
2822         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2823
2824         /*
2825          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2826          * time should be set to 16. However, the original Ralink driver uses
2827          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2828          * connection problems with 11g + CTS protection. Hence, use the same
2829          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2830          */
2831         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2832         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2833         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2834         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2835         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2836         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2837         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2838
2839         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2840
2841         /*
2842          * ASIC will keep garbage value after boot, clear encryption keys.
2843          */
2844         for (i = 0; i < 4; i++)
2845                 rt2800_register_write(rt2x00dev,
2846                                          SHARED_KEY_MODE_ENTRY(i), 0);
2847
2848         for (i = 0; i < 256; i++) {
2849                 rt2800_config_wcid(rt2x00dev, NULL, i);
2850                 rt2800_delete_wcid_attr(rt2x00dev, i);
2851                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2852         }
2853
2854         /*
2855          * Clear all beacons
2856          */
2857         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2858         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2859         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2860         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2861         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2862         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2863         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2864         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2865
2866         if (rt2x00_is_usb(rt2x00dev)) {
2867                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2868                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2869                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2870         } else if (rt2x00_is_pcie(rt2x00dev)) {
2871                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2872                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2873                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2874         }
2875
2876         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2877         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2878         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2879         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2880         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2881         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2882         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2883         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2884         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2885         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2886
2887         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2888         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2889         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2890         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2891         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2892         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2893         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2894         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2895         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2896         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2897
2898         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2899         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2900         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2901         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2902         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2903         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2904         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2905         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2906         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2907         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2908
2909         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2910         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2911         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2912         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2913         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2914         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2915
2916         /*
2917          * Do not force the BA window size, we use the TXWI to set it
2918          */
2919         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2920         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2921         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2922         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2923
2924         /*
2925          * We must clear the error counters.
2926          * These registers are cleared on read,
2927          * so we may pass a useless variable to store the value.
2928          */
2929         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2930         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2931         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2932         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2933         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2934         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2935
2936         /*
2937          * Setup leadtime for pre tbtt interrupt to 6ms
2938          */
2939         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2940         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2941         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2942
2943         /*
2944          * Set up channel statistics timer
2945          */
2946         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2947         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2948         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2949         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2950         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2951         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2952         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2953
2954         return 0;
2955 }
2956
2957 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2958 {
2959         unsigned int i;
2960         u32 reg;
2961
2962         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2963                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2964                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2965                         return 0;
2966
2967                 udelay(REGISTER_BUSY_DELAY);
2968         }
2969
2970         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2971         return -EACCES;
2972 }
2973
2974 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2975 {
2976         unsigned int i;
2977         u8 value;
2978
2979         /*
2980          * BBP was enabled after firmware was loaded,
2981          * but we need to reactivate it now.
2982          */
2983         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2984         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2985         msleep(1);
2986
2987         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2988                 rt2800_bbp_read(rt2x00dev, 0, &value);
2989                 if ((value != 0xff) && (value != 0x00))
2990                         return 0;
2991                 udelay(REGISTER_BUSY_DELAY);
2992         }
2993
2994         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2995         return -EACCES;
2996 }
2997
2998 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2999 {
3000         unsigned int i;
3001         u16 eeprom;
3002         u8 reg_id;
3003         u8 value;
3004
3005         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3006                      rt2800_wait_bbp_ready(rt2x00dev)))
3007                 return -EACCES;
3008
3009         if (rt2x00_rt(rt2x00dev, RT5390)) {
3010                 rt2800_bbp_read(rt2x00dev, 4, &value);
3011                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3012                 rt2800_bbp_write(rt2x00dev, 4, value);
3013         }
3014
3015         if (rt2800_is_305x_soc(rt2x00dev) ||
3016             rt2x00_rt(rt2x00dev, RT3572) ||
3017             rt2x00_rt(rt2x00dev, RT5390))
3018                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3019
3020         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3021         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3022
3023         if (rt2x00_rt(rt2x00dev, RT5390))
3024                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3025
3026         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3027                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3028                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3029         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3030                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3031                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3032                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3033                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3034                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3035         } else {
3036                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3037                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3038         }
3039
3040         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3041
3042         if (rt2x00_rt(rt2x00dev, RT3070) ||
3043             rt2x00_rt(rt2x00dev, RT3071) ||
3044             rt2x00_rt(rt2x00dev, RT3090) ||
3045             rt2x00_rt(rt2x00dev, RT3390) ||
3046             rt2x00_rt(rt2x00dev, RT3572) ||
3047             rt2x00_rt(rt2x00dev, RT5390)) {
3048                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3049                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3050                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3051         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3052                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3053                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3054         } else {
3055                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3056         }
3057
3058         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3059         if (rt2x00_rt(rt2x00dev, RT5390))
3060                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3061         else
3062                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3063
3064         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3065                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3066         else if (rt2x00_rt(rt2x00dev, RT5390))
3067                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3068         else
3069                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3070
3071         if (rt2x00_rt(rt2x00dev, RT5390))
3072                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3073         else
3074                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3075
3076         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3077
3078         if (rt2x00_rt(rt2x00dev, RT5390))
3079                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3080         else
3081                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3082
3083         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3084             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3085             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3086             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3087             rt2x00_rt(rt2x00dev, RT3572) ||
3088             rt2x00_rt(rt2x00dev, RT5390) ||
3089             rt2800_is_305x_soc(rt2x00dev))
3090                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3091         else
3092                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3093
3094         if (rt2x00_rt(rt2x00dev, RT5390))
3095                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3096
3097         if (rt2800_is_305x_soc(rt2x00dev))
3098                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3099         else if (rt2x00_rt(rt2x00dev, RT5390))
3100                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3101         else
3102                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3103
3104         if (rt2x00_rt(rt2x00dev, RT5390))
3105                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3106         else
3107                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3108
3109         if (rt2x00_rt(rt2x00dev, RT5390))
3110                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3111
3112         if (rt2x00_rt(rt2x00dev, RT3071) ||
3113             rt2x00_rt(rt2x00dev, RT3090) ||
3114             rt2x00_rt(rt2x00dev, RT3390) ||
3115             rt2x00_rt(rt2x00dev, RT3572) ||
3116             rt2x00_rt(rt2x00dev, RT5390)) {
3117                 rt2800_bbp_read(rt2x00dev, 138, &value);
3118
3119                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3120                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3121                         value |= 0x20;
3122                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3123                         value &= ~0x02;
3124
3125                 rt2800_bbp_write(rt2x00dev, 138, value);
3126         }
3127
3128         if (rt2x00_rt(rt2x00dev, RT5390)) {
3129                 int ant, div_mode;
3130
3131                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3132                 div_mode = rt2x00_get_field16(eeprom,
3133                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
3134                 ant = (div_mode == 3) ? 1 : 0;
3135
3136                 /* check if this is a Bluetooth combo card */
3137                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3138                         u32 reg;
3139
3140                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3141                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3142                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3143                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3144                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3145                         if (ant == 0)
3146                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3147                         else if (ant == 1)
3148                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3149                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3150                 }
3151
3152                 rt2800_bbp_read(rt2x00dev, 152, &value);
3153                 if (ant == 0)
3154                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3155                 else
3156                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3157                 rt2800_bbp_write(rt2x00dev, 152, value);
3158
3159                 /* Init frequency calibration */
3160                 rt2800_bbp_write(rt2x00dev, 142, 1);
3161                 rt2800_bbp_write(rt2x00dev, 143, 57);
3162         }
3163
3164         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3165                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3166
3167                 if (eeprom != 0xffff && eeprom != 0x0000) {
3168                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3169                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3170                         rt2800_bbp_write(rt2x00dev, reg_id, value);
3171                 }
3172         }
3173
3174         return 0;
3175 }
3176
3177 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3178                                 bool bw40, u8 rfcsr24, u8 filter_target)
3179 {
3180         unsigned int i;
3181         u8 bbp;
3182         u8 rfcsr;
3183         u8 passband;
3184         u8 stopband;
3185         u8 overtuned = 0;
3186
3187         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3188
3189         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3190         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3191         rt2800_bbp_write(rt2x00dev, 4, bbp);
3192
3193         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3194         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3195         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3196
3197         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3198         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3199         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3200
3201         /*
3202          * Set power & frequency of passband test tone
3203          */
3204         rt2800_bbp_write(rt2x00dev, 24, 0);
3205
3206         for (i = 0; i < 100; i++) {
3207                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3208                 msleep(1);
3209
3210                 rt2800_bbp_read(rt2x00dev, 55, &passband);
3211                 if (passband)
3212                         break;
3213         }
3214
3215         /*
3216          * Set power & frequency of stopband test tone
3217          */
3218         rt2800_bbp_write(rt2x00dev, 24, 0x06);
3219
3220         for (i = 0; i < 100; i++) {
3221                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3222                 msleep(1);
3223
3224                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3225
3226                 if ((passband - stopband) <= filter_target) {
3227                         rfcsr24++;
3228                         overtuned += ((passband - stopband) == filter_target);
3229                 } else
3230                         break;
3231
3232                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3233         }
3234
3235         rfcsr24 -= !!overtuned;
3236
3237         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3238         return rfcsr24;
3239 }
3240
3241 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3242 {
3243         u8 rfcsr;
3244         u8 bbp;
3245         u32 reg;
3246         u16 eeprom;
3247
3248         if (!rt2x00_rt(rt2x00dev, RT3070) &&
3249             !rt2x00_rt(rt2x00dev, RT3071) &&
3250             !rt2x00_rt(rt2x00dev, RT3090) &&
3251             !rt2x00_rt(rt2x00dev, RT3390) &&
3252             !rt2x00_rt(rt2x00dev, RT3572) &&
3253             !rt2x00_rt(rt2x00dev, RT5390) &&
3254             !rt2800_is_305x_soc(rt2x00dev))
3255                 return 0;
3256
3257         /*
3258          * Init RF calibration.
3259          */
3260         if (rt2x00_rt(rt2x00dev, RT5390)) {
3261                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3262                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3263                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3264                 msleep(1);
3265                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3266                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3267         } else {
3268                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3269                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3270                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3271                 msleep(1);
3272                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3273                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3274         }
3275
3276         if (rt2x00_rt(rt2x00dev, RT3070) ||
3277             rt2x00_rt(rt2x00dev, RT3071) ||
3278             rt2x00_rt(rt2x00dev, RT3090)) {
3279                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3280                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3281                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3282                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3283                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3284                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3285                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3286                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3287                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3288                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3289                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3290                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3291                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3292                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3293                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3294                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3295                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3296                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3297                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3298         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3299                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3300                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3301                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3302                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3303                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3304                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3305                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3306                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3307                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3308                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3309                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3310                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3311                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3312                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3313                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3314                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3315                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3316                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3317                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3318                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3319                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3320                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3321                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3322                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3323                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3324                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3325                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3326                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3327                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3328                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3329                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3330                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3331         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3332                 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3333                 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3334                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3335                 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3336                 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3337                 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3338                 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3339                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3340                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3341                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3342                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3343                 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3344                 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3345                 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3346                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3347                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3348                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3349                 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3350                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3351                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3352                 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3353                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3354                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3355                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3356                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3357                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3358                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3359                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3360                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3361                 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3362                 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3363         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3364                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3365                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3366                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3367                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3368                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3369                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3370                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3371                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3372                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3373                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3374                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3375                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3376                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3377                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3378                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3379                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3380                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3381                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3382                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3383                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3384                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3385                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3386                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3387                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3388                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3389                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3390                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3391                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3392                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3393                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3394                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3395                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3396                 return 0;
3397         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3398                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3399                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3400                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3401                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3402                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3403                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3404                 else
3405                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3406                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3407                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3408                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3409                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3410                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3411                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3412                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3413                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3414                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3415                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3416
3417                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3418                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3419                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3420                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3421                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3422                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3423                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3424                 else
3425                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3426                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3427                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3428                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3429                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3430
3431                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3432                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3433                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3434                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3435                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3436                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3437                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3438                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3439                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3440                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3441
3442                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3443                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3444                 else
3445                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3446                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3447                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3448                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3449                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3450                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3451                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3452                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3453                 else
3454                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3455                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3456                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3457                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3458
3459                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3460                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3461                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3462                 else
3463                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3464                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3465                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3466                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3467                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3468                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3469                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3470
3471                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3472                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3473                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3474                 else
3475                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3476                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3477                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3478         }
3479
3480         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3481                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3482                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3483                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3484                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3485         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3486                    rt2x00_rt(rt2x00dev, RT3090)) {
3487                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3488
3489                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3490                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3491                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3492
3493                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3494                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3495                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3496                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3497                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3498                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3499                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3500                         else
3501                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3502                 }
3503                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3504
3505                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3506                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3507                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3508         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3509                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3510                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3511                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3512         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3513                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3514                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3515                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3516
3517                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3518                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3519                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3520                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3521                 msleep(1);
3522                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3523                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3524                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3525         }
3526
3527         /*
3528          * Set RX Filter calibration for 20MHz and 40MHz
3529          */
3530         if (rt2x00_rt(rt2x00dev, RT3070)) {
3531                 rt2x00dev->calibration[0] =
3532                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3533                 rt2x00dev->calibration[1] =
3534                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3535         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3536                    rt2x00_rt(rt2x00dev, RT3090) ||
3537                    rt2x00_rt(rt2x00dev, RT3390) ||
3538                    rt2x00_rt(rt2x00dev, RT3572)) {
3539                 rt2x00dev->calibration[0] =
3540                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3541                 rt2x00dev->calibration[1] =
3542                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3543         }
3544
3545         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3546                 /*
3547                  * Set back to initial state
3548                  */
3549                 rt2800_bbp_write(rt2x00dev, 24, 0);
3550
3551                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3552                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3553                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3554
3555                 /*
3556                  * Set BBP back to BW20
3557                  */
3558                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3559                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3560                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3561         }
3562
3563         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3564             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3565             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3566             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3567                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3568
3569         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3570         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3571         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3572
3573         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3574                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3575                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3576                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3577                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3578                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3579                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3580                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3581                                       &rt2x00dev->cap_flags))
3582                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3583                 }
3584                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3585                 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3586                         rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3587                                         rt2x00_get_field16(eeprom,
3588                                                 EEPROM_TXMIXER_GAIN_BG_VAL));
3589                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3590         }
3591
3592         if (rt2x00_rt(rt2x00dev, RT3090)) {
3593                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3594
3595                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3596                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3597                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3598                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3599                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3600                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3601
3602                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3603         }
3604
3605         if (rt2x00_rt(rt2x00dev, RT3071) ||
3606             rt2x00_rt(rt2x00dev, RT3090) ||
3607             rt2x00_rt(rt2x00dev, RT3390)) {
3608                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3609                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3610                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3611                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3612                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3613                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3614                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3615
3616                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3617                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3618                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3619
3620                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3621                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3622                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3623
3624                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3625                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3626                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3627         }
3628
3629         if (rt2x00_rt(rt2x00dev, RT3070)) {
3630                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3631                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3632                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3633                 else
3634                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3635                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3636                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3637                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3638                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3639         }
3640
3641         if (rt2x00_rt(rt2x00dev, RT5390)) {
3642                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3643                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3644                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3645
3646                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3647                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3648                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3649
3650                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3651                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3652                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3653         }
3654
3655         return 0;
3656 }
3657
3658 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3659 {
3660         u32 reg;
3661         u16 word;
3662
3663         /*
3664          * Initialize all registers.
3665          */
3666         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3667                      rt2800_init_registers(rt2x00dev) ||
3668                      rt2800_init_bbp(rt2x00dev) ||
3669                      rt2800_init_rfcsr(rt2x00dev)))
3670                 return -EIO;
3671
3672         /*
3673          * Send signal to firmware during boot time.
3674          */
3675         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3676
3677         if (rt2x00_is_usb(rt2x00dev) &&
3678             (rt2x00_rt(rt2x00dev, RT3070) ||
3679              rt2x00_rt(rt2x00dev, RT3071) ||
3680              rt2x00_rt(rt2x00dev, RT3572))) {
3681                 udelay(200);
3682                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3683                 udelay(10);
3684         }
3685
3686         /*
3687          * Enable RX.
3688          */
3689         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3690         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3691         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3692         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3693
3694         udelay(50);
3695
3696         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3697         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3698         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3699         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3700         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3701         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3702
3703         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3704         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3705         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3706         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3707
3708         /*
3709          * Initialize LED control
3710          */
3711         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3712         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3713                            word & 0xff, (word >> 8) & 0xff);
3714
3715         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3716         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3717                            word & 0xff, (word >> 8) & 0xff);
3718
3719         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3720         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3721                            word & 0xff, (word >> 8) & 0xff);
3722
3723         return 0;
3724 }
3725 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3726
3727 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3728 {
3729         u32 reg;
3730
3731         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3732         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3733         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3734         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3735
3736         /* Wait for DMA, ignore error */
3737         rt2800_wait_wpdma_ready(rt2x00dev);
3738
3739         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3740         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3741         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3742         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3743 }
3744 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3745
3746 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3747 {
3748         u32 reg;
3749
3750         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3751
3752         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3753 }
3754 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3755
3756 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3757 {
3758         u32 reg;
3759
3760         mutex_lock(&rt2x00dev->csr_mutex);
3761
3762         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3763         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3764         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3765         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3766         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3767
3768         /* Wait until the EEPROM has been loaded */
3769         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3770
3771         /* Apparently the data is read from end to start */
3772         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
3773         /* The returned value is in CPU order, but eeprom is le */
3774         rt2x00dev->eeprom[i] = cpu_to_le32(reg);
3775         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
3776         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
3777         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
3778         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
3779         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
3780         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
3781
3782         mutex_unlock(&rt2x00dev->csr_mutex);
3783 }
3784
3785 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3786 {
3787         unsigned int i;
3788
3789         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3790                 rt2800_efuse_read(rt2x00dev, i);
3791 }
3792 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3793
3794 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3795 {
3796         u16 word;
3797         u8 *mac;
3798         u8 default_lna_gain;
3799
3800         /*
3801          * Start validation of the data that has been read.
3802          */
3803         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3804         if (!is_valid_ether_addr(mac)) {
3805                 random_ether_addr(mac);
3806                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3807         }
3808
3809         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3810         if (word == 0xffff) {
3811                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3812                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3813                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3814                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3815                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3816         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3817                    rt2x00_rt(rt2x00dev, RT2872)) {
3818                 /*
3819                  * There is a max of 2 RX streams for RT28x0 series
3820                  */
3821                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3822                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3823                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3824         }
3825
3826         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3827         if (word == 0xffff) {
3828                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3829                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3830                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3831                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3832                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3833                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3834                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3835                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3836                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3837                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3838                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3839                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3840                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3841                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3842                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3843                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3844                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3845         }
3846
3847         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3848         if ((word & 0x00ff) == 0x00ff) {
3849                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3850                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3851                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3852         }
3853         if ((word & 0xff00) == 0xff00) {
3854                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3855                                    LED_MODE_TXRX_ACTIVITY);
3856                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3857                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3858                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3859                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3860                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3861                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3862         }
3863
3864         /*
3865          * During the LNA validation we are going to use
3866          * lna0 as correct value. Note that EEPROM_LNA
3867          * is never validated.
3868          */
3869         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3870         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3871
3872         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3873         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3874                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3875         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3876                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3877         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3878
3879         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3880         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3881                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3882         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3883             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3884                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3885                                    default_lna_gain);
3886         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3887
3888         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3889         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3890                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3891         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3892                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3893         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3894
3895         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3896         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3897                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3898         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3899             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3900                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3901                                    default_lna_gain);
3902         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3903
3904         return 0;
3905 }
3906 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3907
3908 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3909 {
3910         u32 reg;
3911         u16 value;
3912         u16 eeprom;
3913
3914         /*
3915          * Read EEPROM word for configuration.
3916          */
3917         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3918
3919         /*
3920          * Identify RF chipset by EEPROM value
3921          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3922          * RT53xx: defined in "EEPROM_CHIP_ID" field
3923          */
3924         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3925         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3926                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3927         else
3928                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3929
3930         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3931                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3932
3933         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3934             !rt2x00_rt(rt2x00dev, RT2872) &&
3935             !rt2x00_rt(rt2x00dev, RT2883) &&
3936             !rt2x00_rt(rt2x00dev, RT3070) &&
3937             !rt2x00_rt(rt2x00dev, RT3071) &&
3938             !rt2x00_rt(rt2x00dev, RT3090) &&
3939             !rt2x00_rt(rt2x00dev, RT3390) &&
3940             !rt2x00_rt(rt2x00dev, RT3572) &&
3941             !rt2x00_rt(rt2x00dev, RT5390)) {
3942                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3943                 return -ENODEV;
3944         }
3945
3946         switch (rt2x00dev->chip.rf) {
3947         case RF2820:
3948         case RF2850:
3949         case RF2720:
3950         case RF2750:
3951         case RF3020:
3952         case RF2020:
3953         case RF3021:
3954         case RF3022:
3955         case RF3052:
3956         case RF3320:
3957         case RF5370:
3958         case RF5390:
3959                 break;
3960         default:
3961                 ERROR(rt2x00dev, "Invalid RF chipset 0x%x detected.\n",
3962                       rt2x00dev->chip.rf);
3963                 return -ENODEV;
3964         }
3965
3966         /*
3967          * Identify default antenna configuration.
3968          */
3969         rt2x00dev->default_ant.tx_chain_num =
3970             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3971         rt2x00dev->default_ant.rx_chain_num =
3972             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3973
3974         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3975
3976         if (rt2x00_rt(rt2x00dev, RT3070) ||
3977             rt2x00_rt(rt2x00dev, RT3090) ||
3978             rt2x00_rt(rt2x00dev, RT3390)) {
3979                 value = rt2x00_get_field16(eeprom,
3980                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3981                 switch (value) {
3982                 case 0:
3983                 case 1:
3984                 case 2:
3985                         rt2x00dev->default_ant.tx = ANTENNA_A;
3986                         rt2x00dev->default_ant.rx = ANTENNA_A;
3987                         break;
3988                 case 3:
3989                         rt2x00dev->default_ant.tx = ANTENNA_A;
3990                         rt2x00dev->default_ant.rx = ANTENNA_B;
3991                         break;
3992                 }
3993         } else {
3994                 rt2x00dev->default_ant.tx = ANTENNA_A;
3995                 rt2x00dev->default_ant.rx = ANTENNA_A;
3996         }
3997
3998         /*
3999          * Determine external LNA informations.
4000          */
4001         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
4002                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
4003         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
4004                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4005
4006         /*
4007          * Detect if this device has an hardware controlled radio.
4008          */
4009         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
4010                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4011
4012         /*
4013          * Detect if this device has Bluetooth co-existence.
4014          */
4015         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4016                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4017
4018         /*
4019          * Read frequency offset and RF programming sequence.
4020          */
4021         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4022         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4023
4024         /*
4025          * Store led settings, for correct led behaviour.
4026          */
4027 #ifdef CONFIG_RT2X00_LIB_LEDS
4028         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4029         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4030         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4031
4032         rt2x00dev->led_mcu_reg = eeprom;
4033 #endif /* CONFIG_RT2X00_LIB_LEDS */
4034
4035         /*
4036          * Check if support EIRP tx power limit feature.
4037          */
4038         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4039
4040         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4041                                         EIRP_MAX_TX_POWER_LIMIT)
4042                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4043
4044         return 0;
4045 }
4046 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4047
4048 /*
4049  * RF value list for rt28xx
4050  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4051  */
4052 static const struct rf_channel rf_vals[] = {
4053         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4054         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4055         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4056         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4057         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4058         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4059         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4060         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4061         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4062         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4063         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4064         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4065         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4066         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4067
4068         /* 802.11 UNI / HyperLan 2 */
4069         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4070         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4071         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4072         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4073         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4074         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4075         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4076         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4077         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4078         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4079         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4080         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4081
4082         /* 802.11 HyperLan 2 */
4083         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4084         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4085         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4086         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4087         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4088         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4089         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4090         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4091         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4092         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4093         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4094         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4095         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4096         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4097         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4098         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4099
4100         /* 802.11 UNII */
4101         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4102         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4103         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4104         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4105         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4106         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4107         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4108         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4109         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4110         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4111         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4112
4113         /* 802.11 Japan */
4114         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4115         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4116         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4117         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4118         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4119         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4120         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4121 };
4122
4123 /*
4124  * RF value list for rt3xxx
4125  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4126  */
4127 static const struct rf_channel rf_vals_3x[] = {
4128         {1,  241, 2, 2 },
4129         {2,  241, 2, 7 },
4130         {3,  242, 2, 2 },
4131         {4,  242, 2, 7 },
4132         {5,  243, 2, 2 },
4133         {6,  243, 2, 7 },
4134         {7,  244, 2, 2 },
4135         {8,  244, 2, 7 },
4136         {9,  245, 2, 2 },
4137         {10, 245, 2, 7 },
4138         {11, 246, 2, 2 },
4139         {12, 246, 2, 7 },
4140         {13, 247, 2, 2 },
4141         {14, 248, 2, 4 },
4142
4143         /* 802.11 UNI / HyperLan 2 */
4144         {36, 0x56, 0, 4},
4145         {38, 0x56, 0, 6},
4146         {40, 0x56, 0, 8},
4147         {44, 0x57, 0, 0},
4148         {46, 0x57, 0, 2},
4149         {48, 0x57, 0, 4},
4150         {52, 0x57, 0, 8},
4151         {54, 0x57, 0, 10},
4152         {56, 0x58, 0, 0},
4153         {60, 0x58, 0, 4},
4154         {62, 0x58, 0, 6},
4155         {64, 0x58, 0, 8},
4156
4157         /* 802.11 HyperLan 2 */
4158         {100, 0x5b, 0, 8},
4159         {102, 0x5b, 0, 10},
4160         {104, 0x5c, 0, 0},
4161         {108, 0x5c, 0, 4},
4162         {110, 0x5c, 0, 6},
4163         {112, 0x5c, 0, 8},
4164         {116, 0x5d, 0, 0},
4165         {118, 0x5d, 0, 2},
4166         {120, 0x5d, 0, 4},
4167         {124, 0x5d, 0, 8},
4168         {126, 0x5d, 0, 10},
4169         {128, 0x5e, 0, 0},
4170         {132, 0x5e, 0, 4},
4171         {134, 0x5e, 0, 6},
4172         {136, 0x5e, 0, 8},
4173         {140, 0x5f, 0, 0},
4174
4175         /* 802.11 UNII */
4176         {149, 0x5f, 0, 9},
4177         {151, 0x5f, 0, 11},
4178         {153, 0x60, 0, 1},
4179         {157, 0x60, 0, 5},
4180         {159, 0x60, 0, 7},
4181         {161, 0x60, 0, 9},
4182         {165, 0x61, 0, 1},
4183         {167, 0x61, 0, 3},
4184         {169, 0x61, 0, 5},
4185         {171, 0x61, 0, 7},
4186         {173, 0x61, 0, 9},
4187 };
4188
4189 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4190 {
4191         struct hw_mode_spec *spec = &rt2x00dev->spec;
4192         struct channel_info *info;
4193         char *default_power1;
4194         char *default_power2;
4195         unsigned int i;
4196         u16 eeprom;
4197
4198         /*
4199          * Disable powersaving as default on PCI devices.
4200          */
4201         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4202                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4203
4204         /*
4205          * Initialize all hw fields.
4206          */
4207         rt2x00dev->hw->flags =
4208             IEEE80211_HW_SIGNAL_DBM |
4209             IEEE80211_HW_SUPPORTS_PS |
4210             IEEE80211_HW_PS_NULLFUNC_STACK |
4211             IEEE80211_HW_AMPDU_AGGREGATION;
4212         /*
4213          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4214          * unless we are capable of sending the buffered frames out after the
4215          * DTIM transmission using rt2x00lib_beacondone. This will send out
4216          * multicast and broadcast traffic immediately instead of buffering it
4217          * infinitly and thus dropping it after some time.
4218          */
4219         if (!rt2x00_is_usb(rt2x00dev))
4220                 rt2x00dev->hw->flags |=
4221                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4222
4223         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4224         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4225                                 rt2x00_eeprom_addr(rt2x00dev,
4226                                                    EEPROM_MAC_ADDR_0));
4227
4228         /*
4229          * As rt2800 has a global fallback table we cannot specify
4230          * more then one tx rate per frame but since the hw will
4231          * try several rates (based on the fallback table) we should
4232          * initialize max_report_rates to the maximum number of rates
4233          * we are going to try. Otherwise mac80211 will truncate our
4234          * reported tx rates and the rc algortihm will end up with
4235          * incorrect data.
4236          */
4237         rt2x00dev->hw->max_rates = 1;
4238         rt2x00dev->hw->max_report_rates = 7;
4239         rt2x00dev->hw->max_rate_tries = 1;
4240
4241         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4242
4243         /*
4244          * Initialize hw_mode information.
4245          */
4246         spec->supported_bands = SUPPORT_BAND_2GHZ;
4247         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4248
4249         if (rt2x00_rf(rt2x00dev, RF2820) ||
4250             rt2x00_rf(rt2x00dev, RF2720)) {
4251                 spec->num_channels = 14;
4252                 spec->channels = rf_vals;
4253         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4254                    rt2x00_rf(rt2x00dev, RF2750)) {
4255                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4256                 spec->num_channels = ARRAY_SIZE(rf_vals);
4257                 spec->channels = rf_vals;
4258         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4259                    rt2x00_rf(rt2x00dev, RF2020) ||
4260                    rt2x00_rf(rt2x00dev, RF3021) ||
4261                    rt2x00_rf(rt2x00dev, RF3022) ||
4262                    rt2x00_rf(rt2x00dev, RF3320) ||
4263                    rt2x00_rf(rt2x00dev, RF5370) ||
4264                    rt2x00_rf(rt2x00dev, RF5390)) {
4265                 spec->num_channels = 14;
4266                 spec->channels = rf_vals_3x;
4267         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4268                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4269                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4270                 spec->channels = rf_vals_3x;
4271         }
4272
4273         /*
4274          * Initialize HT information.
4275          */
4276         if (!rt2x00_rf(rt2x00dev, RF2020))
4277                 spec->ht.ht_supported = true;
4278         else
4279                 spec->ht.ht_supported = false;
4280
4281         spec->ht.cap =
4282             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4283             IEEE80211_HT_CAP_GRN_FLD |
4284             IEEE80211_HT_CAP_SGI_20 |
4285             IEEE80211_HT_CAP_SGI_40;
4286
4287         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4288                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4289
4290         spec->ht.cap |=
4291             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4292                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4293
4294         spec->ht.ampdu_factor = 3;
4295         spec->ht.ampdu_density = 4;
4296         spec->ht.mcs.tx_params =
4297             IEEE80211_HT_MCS_TX_DEFINED |
4298             IEEE80211_HT_MCS_TX_RX_DIFF |
4299             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4300                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4301
4302         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4303         case 3:
4304                 spec->ht.mcs.rx_mask[2] = 0xff;
4305         case 2:
4306                 spec->ht.mcs.rx_mask[1] = 0xff;
4307         case 1:
4308                 spec->ht.mcs.rx_mask[0] = 0xff;
4309                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4310                 break;
4311         }
4312
4313         /*
4314          * Create channel information array
4315          */
4316         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4317         if (!info)
4318                 return -ENOMEM;
4319
4320         spec->channels_info = info;
4321
4322         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4323         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4324
4325         for (i = 0; i < 14; i++) {
4326                 info[i].default_power1 = default_power1[i];
4327                 info[i].default_power2 = default_power2[i];
4328         }
4329
4330         if (spec->num_channels > 14) {
4331                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4332                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4333
4334                 for (i = 14; i < spec->num_channels; i++) {
4335                         info[i].default_power1 = default_power1[i];
4336                         info[i].default_power2 = default_power2[i];
4337                 }
4338         }
4339
4340         return 0;
4341 }
4342 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4343
4344 /*
4345  * IEEE80211 stack callback functions.
4346  */
4347 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4348                          u16 *iv16)
4349 {
4350         struct rt2x00_dev *rt2x00dev = hw->priv;
4351         struct mac_iveiv_entry iveiv_entry;
4352         u32 offset;
4353
4354         offset = MAC_IVEIV_ENTRY(hw_key_idx);
4355         rt2800_register_multiread(rt2x00dev, offset,
4356                                       &iveiv_entry, sizeof(iveiv_entry));
4357
4358         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4359         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4360 }
4361 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4362
4363 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4364 {
4365         struct rt2x00_dev *rt2x00dev = hw->priv;
4366         u32 reg;
4367         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4368
4369         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4370         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4371         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4372
4373         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4374         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4375         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4376
4377         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4378         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4379         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4380
4381         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4382         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4383         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4384
4385         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4386         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4387         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4388
4389         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4390         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4391         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4392
4393         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4394         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4395         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4396
4397         return 0;
4398 }
4399 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4400
4401 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
4402                    const struct ieee80211_tx_queue_params *params)
4403 {
4404         struct rt2x00_dev *rt2x00dev = hw->priv;
4405         struct data_queue *queue;
4406         struct rt2x00_field32 field;
4407         int retval;
4408         u32 reg;
4409         u32 offset;
4410
4411         /*
4412          * First pass the configuration through rt2x00lib, that will
4413          * update the queue settings and validate the input. After that
4414          * we are free to update the registers based on the value
4415          * in the queue parameter.
4416          */
4417         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
4418         if (retval)
4419                 return retval;
4420
4421         /*
4422          * We only need to perform additional register initialization
4423          * for WMM queues/
4424          */
4425         if (queue_idx >= 4)
4426                 return 0;
4427
4428         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4429
4430         /* Update WMM TXOP register */
4431         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4432         field.bit_offset = (queue_idx & 1) * 16;
4433         field.bit_mask = 0xffff << field.bit_offset;
4434
4435         rt2800_register_read(rt2x00dev, offset, &reg);
4436         rt2x00_set_field32(&reg, field, queue->txop);
4437         rt2800_register_write(rt2x00dev, offset, reg);
4438
4439         /* Update WMM registers */
4440         field.bit_offset = queue_idx * 4;
4441         field.bit_mask = 0xf << field.bit_offset;
4442
4443         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4444         rt2x00_set_field32(&reg, field, queue->aifs);
4445         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4446
4447         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4448         rt2x00_set_field32(&reg, field, queue->cw_min);
4449         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4450
4451         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4452         rt2x00_set_field32(&reg, field, queue->cw_max);
4453         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4454
4455         /* Update EDCA registers */
4456         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4457
4458         rt2800_register_read(rt2x00dev, offset, &reg);
4459         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4460         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4461         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4462         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4463         rt2800_register_write(rt2x00dev, offset, reg);
4464
4465         return 0;
4466 }
4467 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4468
4469 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
4470 {
4471         struct rt2x00_dev *rt2x00dev = hw->priv;
4472         u64 tsf;
4473         u32 reg;
4474
4475         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4476         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4477         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4478         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4479
4480         return tsf;
4481 }
4482 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4483
4484 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4485                         enum ieee80211_ampdu_mlme_action action,
4486                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4487                         u8 buf_size)
4488 {
4489         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
4490         int ret = 0;
4491
4492         /*
4493          * Don't allow aggregation for stations the hardware isn't aware
4494          * of because tx status reports for frames to an unknown station
4495          * always contain wcid=255 and thus we can't distinguish between
4496          * multiple stations which leads to unwanted situations when the
4497          * hw reorders frames due to aggregation.
4498          */
4499         if (sta_priv->wcid < 0)
4500                 return 1;
4501
4502         switch (action) {
4503         case IEEE80211_AMPDU_RX_START:
4504         case IEEE80211_AMPDU_RX_STOP:
4505                 /*
4506                  * The hw itself takes care of setting up BlockAck mechanisms.
4507                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4508                  * agreement. Once that is done, the hw will BlockAck incoming
4509                  * AMPDUs without further setup.
4510                  */
4511                 break;
4512         case IEEE80211_AMPDU_TX_START:
4513                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4514                 break;
4515         case IEEE80211_AMPDU_TX_STOP:
4516                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4517                 break;
4518         case IEEE80211_AMPDU_TX_OPERATIONAL:
4519                 break;
4520         default:
4521                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4522         }
4523
4524         return ret;
4525 }
4526 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4527
4528 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4529                       struct survey_info *survey)
4530 {
4531         struct rt2x00_dev *rt2x00dev = hw->priv;
4532         struct ieee80211_conf *conf = &hw->conf;
4533         u32 idle, busy, busy_ext;
4534
4535         if (idx != 0)
4536                 return -ENOENT;
4537
4538         survey->channel = conf->channel;
4539
4540         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4541         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4542         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4543
4544         if (idle || busy) {
4545                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4546                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4547                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4548
4549                 survey->channel_time = (idle + busy) / 1000;
4550                 survey->channel_time_busy = busy / 1000;
4551                 survey->channel_time_ext_busy = busy_ext / 1000;
4552         }
4553
4554         return 0;
4555
4556 }
4557 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4558
4559 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4560 MODULE_VERSION(DRV_VERSION);
4561 MODULE_DESCRIPTION("Ralink RT2800 library");
4562 MODULE_LICENSE("GPL");