e1be67ca23d824c3ffb58d0de1373eb982aa2113
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
1 /*
2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2500pci
23         Abstract: rt2500pci device specific routines.
24         Supported chipsets: RT2560.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
38
39 /*
40  * Register access.
41  * All access to the CSR registers will go through the methods
42  * rt2x00pci_register_read and rt2x00pci_register_write.
43  * BBP and RF register require indirect register access,
44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
45  * These indirect registers work with busy bits,
46  * and we will try maximal REGISTER_BUSY_COUNT times to access
47  * the register while taking a REGISTER_BUSY_DELAY us delay
48  * between each attampt. When the busy bit is still set at that time,
49  * the access attempt is considered to have failed,
50  * and we will print an error.
51  */
52 #define WAIT_FOR_BBP(__dev, __reg) \
53         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 #define WAIT_FOR_RF(__dev, __reg) \
55         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
58                                 const unsigned int word, const u8 value)
59 {
60         u32 reg;
61
62         mutex_lock(&rt2x00dev->csr_mutex);
63
64         /*
65          * Wait until the BBP becomes available, afterwards we
66          * can safely write the new data into the register.
67          */
68         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69                 reg = 0;
70                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76         }
77
78         mutex_unlock(&rt2x00dev->csr_mutex);
79 }
80
81 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
82                                const unsigned int word, u8 *value)
83 {
84         u32 reg;
85
86         mutex_lock(&rt2x00dev->csr_mutex);
87
88         /*
89          * Wait until the BBP becomes available, afterwards we
90          * can safely write the read request into the register.
91          * After the data has been written, we wait until hardware
92          * returns the correct value, if at any time the register
93          * doesn't become available in time, reg will be 0xffffffff
94          * which means we return 0xff to the caller.
95          */
96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97                 reg = 0;
98                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
101
102                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
103
104                 WAIT_FOR_BBP(rt2x00dev, &reg);
105         }
106
107         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
113                                const unsigned int word, const u32 value)
114 {
115         u32 reg;
116
117         mutex_lock(&rt2x00dev->csr_mutex);
118
119         /*
120          * Wait until the RF becomes available, afterwards we
121          * can safely write the new data into the register.
122          */
123         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
124                 reg = 0;
125                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
126                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
127                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
128                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
129
130                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
131                 rt2x00_rf_write(rt2x00dev, word, value);
132         }
133
134         mutex_unlock(&rt2x00dev->csr_mutex);
135 }
136
137 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
138 {
139         struct rt2x00_dev *rt2x00dev = eeprom->data;
140         u32 reg;
141
142         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
143
144         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
145         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
146         eeprom->reg_data_clock =
147             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
148         eeprom->reg_chip_select =
149             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
150 }
151
152 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
153 {
154         struct rt2x00_dev *rt2x00dev = eeprom->data;
155         u32 reg = 0;
156
157         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
160                            !!eeprom->reg_data_clock);
161         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
162                            !!eeprom->reg_chip_select);
163
164         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
165 }
166
167 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
168 static const struct rt2x00debug rt2500pci_rt2x00debug = {
169         .owner  = THIS_MODULE,
170         .csr    = {
171                 .read           = rt2x00pci_register_read,
172                 .write          = rt2x00pci_register_write,
173                 .flags          = RT2X00DEBUGFS_OFFSET,
174                 .word_base      = CSR_REG_BASE,
175                 .word_size      = sizeof(u32),
176                 .word_count     = CSR_REG_SIZE / sizeof(u32),
177         },
178         .eeprom = {
179                 .read           = rt2x00_eeprom_read,
180                 .write          = rt2x00_eeprom_write,
181                 .word_base      = EEPROM_BASE,
182                 .word_size      = sizeof(u16),
183                 .word_count     = EEPROM_SIZE / sizeof(u16),
184         },
185         .bbp    = {
186                 .read           = rt2500pci_bbp_read,
187                 .write          = rt2500pci_bbp_write,
188                 .word_base      = BBP_BASE,
189                 .word_size      = sizeof(u8),
190                 .word_count     = BBP_SIZE / sizeof(u8),
191         },
192         .rf     = {
193                 .read           = rt2x00_rf_read,
194                 .write          = rt2500pci_rf_write,
195                 .word_base      = RF_BASE,
196                 .word_size      = sizeof(u32),
197                 .word_count     = RF_SIZE / sizeof(u32),
198         },
199 };
200 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
201
202 #ifdef CONFIG_RT2X00_LIB_RFKILL
203 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
204 {
205         u32 reg;
206
207         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
208         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
209 }
210 #else
211 #define rt2500pci_rfkill_poll   NULL
212 #endif /* CONFIG_RT2X00_LIB_RFKILL */
213
214 #ifdef CONFIG_RT2X00_LIB_LEDS
215 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
216                                      enum led_brightness brightness)
217 {
218         struct rt2x00_led *led =
219             container_of(led_cdev, struct rt2x00_led, led_dev);
220         unsigned int enabled = brightness != LED_OFF;
221         u32 reg;
222
223         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
224
225         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
226                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
227         else if (led->type == LED_TYPE_ACTIVITY)
228                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
229
230         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
231 }
232
233 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
234                                unsigned long *delay_on,
235                                unsigned long *delay_off)
236 {
237         struct rt2x00_led *led =
238             container_of(led_cdev, struct rt2x00_led, led_dev);
239         u32 reg;
240
241         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
242         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
243         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
244         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
245
246         return 0;
247 }
248
249 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
250                                struct rt2x00_led *led,
251                                enum led_type type)
252 {
253         led->rt2x00dev = rt2x00dev;
254         led->type = type;
255         led->led_dev.brightness_set = rt2500pci_brightness_set;
256         led->led_dev.blink_set = rt2500pci_blink_set;
257         led->flags = LED_INITIALIZED;
258 }
259 #endif /* CONFIG_RT2X00_LIB_LEDS */
260
261 /*
262  * Configuration handlers.
263  */
264 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
265                                     const unsigned int filter_flags)
266 {
267         u32 reg;
268
269         /*
270          * Start configuration steps.
271          * Note that the version error will always be dropped
272          * and broadcast frames will always be accepted since
273          * there is no filter for it at this time.
274          */
275         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
276         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
277                            !(filter_flags & FIF_FCSFAIL));
278         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
279                            !(filter_flags & FIF_PLCPFAIL));
280         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
281                            !(filter_flags & FIF_CONTROL));
282         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
283                            !(filter_flags & FIF_PROMISC_IN_BSS));
284         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
285                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
286                            !rt2x00dev->intf_ap_count);
287         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
288         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
289                            !(filter_flags & FIF_ALLMULTI));
290         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
291         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
292 }
293
294 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
295                                   struct rt2x00_intf *intf,
296                                   struct rt2x00intf_conf *conf,
297                                   const unsigned int flags)
298 {
299         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
300         unsigned int bcn_preload;
301         u32 reg;
302
303         if (flags & CONFIG_UPDATE_TYPE) {
304                 /*
305                  * Enable beacon config
306                  */
307                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
308                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
309                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
310                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
311                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
312
313                 /*
314                  * Enable synchronisation.
315                  */
316                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
317                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
318                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
319                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
320                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
321         }
322
323         if (flags & CONFIG_UPDATE_MAC)
324                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
325                                               conf->mac, sizeof(conf->mac));
326
327         if (flags & CONFIG_UPDATE_BSSID)
328                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
329                                               conf->bssid, sizeof(conf->bssid));
330 }
331
332 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
333                                  struct rt2x00lib_erp *erp)
334 {
335         int preamble_mask;
336         u32 reg;
337
338         /*
339          * When short preamble is enabled, we should set bit 0x08
340          */
341         preamble_mask = erp->short_preamble << 3;
342
343         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
344         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
345                            erp->ack_timeout);
346         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
347                            erp->ack_consume_time);
348         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
349
350         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
351         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
352         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
353         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
354         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
355
356         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
357         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
358         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
359         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
360         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
361
362         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
363         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
364         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
365         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
366         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
367
368         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
369         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
370         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
371         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
372         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
373
374         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
375
376         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
377         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
378         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
379
380         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
381         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
382         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
383         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
384
385         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
386         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
387         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
388         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
389 }
390
391 static void rt2500pci_config_ant(struct rt2x00_dev *rt2x00dev,
392                                  struct antenna_setup *ant)
393 {
394         u32 reg;
395         u8 r14;
396         u8 r2;
397
398         /*
399          * We should never come here because rt2x00lib is supposed
400          * to catch this and send us the correct antenna explicitely.
401          */
402         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
403                ant->tx == ANTENNA_SW_DIVERSITY);
404
405         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
406         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
407         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
408
409         /*
410          * Configure the TX antenna.
411          */
412         switch (ant->tx) {
413         case ANTENNA_A:
414                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
415                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
416                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
417                 break;
418         case ANTENNA_B:
419         default:
420                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
421                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
422                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
423                 break;
424         }
425
426         /*
427          * Configure the RX antenna.
428          */
429         switch (ant->rx) {
430         case ANTENNA_A:
431                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
432                 break;
433         case ANTENNA_B:
434         default:
435                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
436                 break;
437         }
438
439         /*
440          * RT2525E and RT5222 need to flip TX I/Q
441          */
442         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
443             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
444                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
445                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
446                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
447
448                 /*
449                  * RT2525E does not need RX I/Q Flip.
450                  */
451                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
452                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
453         } else {
454                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
455                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
456         }
457
458         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
459         rt2500pci_bbp_write(rt2x00dev, 14, r14);
460         rt2500pci_bbp_write(rt2x00dev, 2, r2);
461 }
462
463 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
464                                      struct rf_channel *rf, const int txpower)
465 {
466         u8 r70;
467
468         /*
469          * Set TXpower.
470          */
471         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
472
473         /*
474          * Switch on tuning bits.
475          * For RT2523 devices we do not need to update the R1 register.
476          */
477         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
478                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
479         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
480
481         /*
482          * For RT2525 we should first set the channel to half band higher.
483          */
484         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
485                 static const u32 vals[] = {
486                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
487                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
488                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
489                         0x00080d2e, 0x00080d3a
490                 };
491
492                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
493                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
494                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
495                 if (rf->rf4)
496                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
497         }
498
499         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
500         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
501         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
502         if (rf->rf4)
503                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
504
505         /*
506          * Channel 14 requires the Japan filter bit to be set.
507          */
508         r70 = 0x46;
509         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
510         rt2500pci_bbp_write(rt2x00dev, 70, r70);
511
512         msleep(1);
513
514         /*
515          * Switch off tuning bits.
516          * For RT2523 devices we do not need to update the R1 register.
517          */
518         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
519                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
520                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
521         }
522
523         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
524         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
525
526         /*
527          * Clear false CRC during channel switch.
528          */
529         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
530 }
531
532 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
533                                      const int txpower)
534 {
535         u32 rf3;
536
537         rt2x00_rf_read(rt2x00dev, 3, &rf3);
538         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
539         rt2500pci_rf_write(rt2x00dev, 3, rf3);
540 }
541
542 static void rt2500pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
543                                          struct rt2x00lib_conf *libconf)
544 {
545         u32 reg;
546
547         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
548         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
549                            libconf->conf->long_frame_max_tx_count);
550         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
551                            libconf->conf->short_frame_max_tx_count);
552         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
553 }
554
555 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
556                                       struct rt2x00lib_conf *libconf)
557 {
558         u32 reg;
559
560         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
561         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
562         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
563         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
564
565         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
566         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
567                            libconf->conf->beacon_int * 16);
568         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
569                            libconf->conf->beacon_int * 16);
570         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
571 }
572
573 static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
574                                 struct rt2x00lib_conf *libconf)
575 {
576         enum dev_state state =
577             (libconf->conf->flags & IEEE80211_CONF_PS) ?
578                 STATE_SLEEP : STATE_AWAKE;
579         u32 reg;
580
581         if (state == STATE_SLEEP) {
582                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
583                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
584                                    (libconf->conf->beacon_int - 20) * 16);
585                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
586                                    libconf->conf->listen_interval - 1);
587
588                 /* We must first disable autowake before it can be enabled */
589                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
590                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
591
592                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
593                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
594         }
595
596         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
597 }
598
599 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
600                              struct rt2x00lib_conf *libconf,
601                              const unsigned int flags)
602 {
603         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
604                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
605                                          libconf->conf->power_level);
606         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
607             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
608                 rt2500pci_config_txpower(rt2x00dev,
609                                          libconf->conf->power_level);
610         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
611                 rt2500pci_config_retry_limit(rt2x00dev, libconf);
612         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
613                 rt2500pci_config_duration(rt2x00dev, libconf);
614         if (flags & IEEE80211_CONF_CHANGE_PS)
615                 rt2500pci_config_ps(rt2x00dev, libconf);
616 }
617
618 /*
619  * Link tuning
620  */
621 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
622                                  struct link_qual *qual)
623 {
624         u32 reg;
625
626         /*
627          * Update FCS error count from register.
628          */
629         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
630         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
631
632         /*
633          * Update False CCA count from register.
634          */
635         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
636         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
637 }
638
639 static inline void rt2500pci_set_vgc(struct rt2x00_dev *rt2x00dev,
640                                      struct link_qual *qual, u8 vgc_level)
641 {
642         if (qual->vgc_level_reg != vgc_level) {
643                 rt2500pci_bbp_write(rt2x00dev, 17, vgc_level);
644                 qual->vgc_level_reg = vgc_level;
645         }
646 }
647
648 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
649                                   struct link_qual *qual)
650 {
651         rt2500pci_set_vgc(rt2x00dev, qual, 0x48);
652 }
653
654 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev,
655                                  struct link_qual *qual, const u32 count)
656 {
657         /*
658          * To prevent collisions with MAC ASIC on chipsets
659          * up to version C the link tuning should halt after 20
660          * seconds while being associated.
661          */
662         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
663             rt2x00dev->intf_associated && count > 20)
664                 return;
665
666         /*
667          * Chipset versions C and lower should directly continue
668          * to the dynamic CCA tuning. Chipset version D and higher
669          * should go straight to dynamic CCA tuning when they
670          * are not associated.
671          */
672         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
673             !rt2x00dev->intf_associated)
674                 goto dynamic_cca_tune;
675
676         /*
677          * A too low RSSI will cause too much false CCA which will
678          * then corrupt the R17 tuning. To remidy this the tuning should
679          * be stopped (While making sure the R17 value will not exceed limits)
680          */
681         if (qual->rssi < -80 && count > 20) {
682                 if (qual->vgc_level_reg >= 0x41)
683                         rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
684                 return;
685         }
686
687         /*
688          * Special big-R17 for short distance
689          */
690         if (qual->rssi >= -58) {
691                 rt2500pci_set_vgc(rt2x00dev, qual, 0x50);
692                 return;
693         }
694
695         /*
696          * Special mid-R17 for middle distance
697          */
698         if (qual->rssi >= -74) {
699                 rt2500pci_set_vgc(rt2x00dev, qual, 0x41);
700                 return;
701         }
702
703         /*
704          * Leave short or middle distance condition, restore r17
705          * to the dynamic tuning range.
706          */
707         if (qual->vgc_level_reg >= 0x41) {
708                 rt2500pci_set_vgc(rt2x00dev, qual, qual->vgc_level);
709                 return;
710         }
711
712 dynamic_cca_tune:
713
714         /*
715          * R17 is inside the dynamic tuning range,
716          * start tuning the link based on the false cca counter.
717          */
718         if (qual->false_cca > 512 && qual->vgc_level_reg < 0x40) {
719                 rt2500pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level_reg);
720                 qual->vgc_level = qual->vgc_level_reg;
721         } else if (qual->false_cca < 100 && qual->vgc_level_reg > 0x32) {
722                 rt2500pci_set_vgc(rt2x00dev, qual, --qual->vgc_level_reg);
723                 qual->vgc_level = qual->vgc_level_reg;
724         }
725 }
726
727 /*
728  * Initialization functions.
729  */
730 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
731 {
732         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
733         u32 word;
734
735         if (entry->queue->qid == QID_RX) {
736                 rt2x00_desc_read(entry_priv->desc, 0, &word);
737
738                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
739         } else {
740                 rt2x00_desc_read(entry_priv->desc, 0, &word);
741
742                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
743                         rt2x00_get_field32(word, TXD_W0_VALID));
744         }
745 }
746
747 static void rt2500pci_clear_entry(struct queue_entry *entry)
748 {
749         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
750         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
751         u32 word;
752
753         if (entry->queue->qid == QID_RX) {
754                 rt2x00_desc_read(entry_priv->desc, 1, &word);
755                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
756                 rt2x00_desc_write(entry_priv->desc, 1, word);
757
758                 rt2x00_desc_read(entry_priv->desc, 0, &word);
759                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
760                 rt2x00_desc_write(entry_priv->desc, 0, word);
761         } else {
762                 rt2x00_desc_read(entry_priv->desc, 0, &word);
763                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
764                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
765                 rt2x00_desc_write(entry_priv->desc, 0, word);
766         }
767 }
768
769 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
770 {
771         struct queue_entry_priv_pci *entry_priv;
772         u32 reg;
773
774         /*
775          * Initialize registers.
776          */
777         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
778         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
779         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
780         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
781         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
782         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
783
784         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
785         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
786         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
787                            entry_priv->desc_dma);
788         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
789
790         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
791         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
792         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
793                            entry_priv->desc_dma);
794         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
795
796         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
797         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
798         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
799                            entry_priv->desc_dma);
800         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
801
802         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
803         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
804         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
805                            entry_priv->desc_dma);
806         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
807
808         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
809         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
810         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
811         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
812
813         entry_priv = rt2x00dev->rx->entries[0].priv_data;
814         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
815         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
816                            entry_priv->desc_dma);
817         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
818
819         return 0;
820 }
821
822 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
823 {
824         u32 reg;
825
826         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
827         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
828         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
829         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
830
831         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
832         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
833         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
834         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
835         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
836
837         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
838         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
839                            rt2x00dev->rx->data_size / 128);
840         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
841
842         /*
843          * Always use CWmin and CWmax set in descriptor.
844          */
845         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
846         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
847         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
848
849         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
850         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
851         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
852         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
853         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
854         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
855         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
856         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
857         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
858         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
859
860         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
861
862         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
863         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
864         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
865         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
866         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
867         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
868         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
869         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
870         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
871         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
872
873         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
874         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
875         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
876         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
877         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
878         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
879
880         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
881         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
882         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
883         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
884         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
885         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
886
887         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
888         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
889         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
890         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
891         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
892         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
893
894         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
895         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
896         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
897         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
898         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
899         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
900         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
901         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
902         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
903         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
904
905         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
906         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
907         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
908         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
909         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
910         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
911         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
912         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
913         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
914
915         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
916
917         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
918         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
919
920         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
921                 return -EBUSY;
922
923         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
924         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
925
926         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
927         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
928         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
929
930         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
931         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
932         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
933         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
934         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
935         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
936         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
937         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
938
939         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
940
941         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
942
943         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
944         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
945         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
946         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
947         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
948
949         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
950         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
951         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
952         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
953
954         /*
955          * We must clear the FCS and FIFO error count.
956          * These registers are cleared on read,
957          * so we may pass a useless variable to store the value.
958          */
959         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
960         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
961
962         return 0;
963 }
964
965 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
966 {
967         unsigned int i;
968         u8 value;
969
970         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
971                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
972                 if ((value != 0xff) && (value != 0x00))
973                         return 0;
974                 udelay(REGISTER_BUSY_DELAY);
975         }
976
977         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
978         return -EACCES;
979 }
980
981 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
982 {
983         unsigned int i;
984         u16 eeprom;
985         u8 reg_id;
986         u8 value;
987
988         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
989                 return -EACCES;
990
991         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
992         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
993         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
994         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
995         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
996         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
997         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
998         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
999         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1000         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1001         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1002         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1003         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1004         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1005         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1006         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1007         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1008         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1009         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1010         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1011         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1012         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1013         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1014         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1015         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1016         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1017         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1018         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1019         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1020         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1021
1022         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1023                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1024
1025                 if (eeprom != 0xffff && eeprom != 0x0000) {
1026                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1027                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1028                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1029                 }
1030         }
1031
1032         return 0;
1033 }
1034
1035 /*
1036  * Device state switch handlers.
1037  */
1038 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1039                                 enum dev_state state)
1040 {
1041         u32 reg;
1042
1043         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1044         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1045                            (state == STATE_RADIO_RX_OFF) ||
1046                            (state == STATE_RADIO_RX_OFF_LINK));
1047         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1048 }
1049
1050 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1051                                  enum dev_state state)
1052 {
1053         int mask = (state == STATE_RADIO_IRQ_OFF);
1054         u32 reg;
1055
1056         /*
1057          * When interrupts are being enabled, the interrupt registers
1058          * should clear the register to assure a clean state.
1059          */
1060         if (state == STATE_RADIO_IRQ_ON) {
1061                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1062                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1063         }
1064
1065         /*
1066          * Only toggle the interrupts bits we are going to use.
1067          * Non-checked interrupt bits are disabled by default.
1068          */
1069         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1070         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1071         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1072         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1073         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1074         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1075         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1076 }
1077
1078 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1079 {
1080         /*
1081          * Initialize all registers.
1082          */
1083         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1084                      rt2500pci_init_registers(rt2x00dev) ||
1085                      rt2500pci_init_bbp(rt2x00dev)))
1086                 return -EIO;
1087
1088         return 0;
1089 }
1090
1091 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1092 {
1093         /*
1094          * Disable power
1095          */
1096         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1097 }
1098
1099 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1100                                enum dev_state state)
1101 {
1102         u32 reg;
1103         unsigned int i;
1104         char put_to_sleep;
1105         char bbp_state;
1106         char rf_state;
1107
1108         put_to_sleep = (state != STATE_AWAKE);
1109
1110         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1111         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1112         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1113         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1114         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1115         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1116
1117         /*
1118          * Device is not guaranteed to be in the requested state yet.
1119          * We must wait until the register indicates that the
1120          * device has entered the correct state.
1121          */
1122         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1123                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1124                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1125                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1126                 if (bbp_state == state && rf_state == state)
1127                         return 0;
1128                 msleep(10);
1129         }
1130
1131         return -EBUSY;
1132 }
1133
1134 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1135                                       enum dev_state state)
1136 {
1137         int retval = 0;
1138
1139         switch (state) {
1140         case STATE_RADIO_ON:
1141                 retval = rt2500pci_enable_radio(rt2x00dev);
1142                 break;
1143         case STATE_RADIO_OFF:
1144                 rt2500pci_disable_radio(rt2x00dev);
1145                 break;
1146         case STATE_RADIO_RX_ON:
1147         case STATE_RADIO_RX_ON_LINK:
1148         case STATE_RADIO_RX_OFF:
1149         case STATE_RADIO_RX_OFF_LINK:
1150                 rt2500pci_toggle_rx(rt2x00dev, state);
1151                 break;
1152         case STATE_RADIO_IRQ_ON:
1153         case STATE_RADIO_IRQ_OFF:
1154                 rt2500pci_toggle_irq(rt2x00dev, state);
1155                 break;
1156         case STATE_DEEP_SLEEP:
1157         case STATE_SLEEP:
1158         case STATE_STANDBY:
1159         case STATE_AWAKE:
1160                 retval = rt2500pci_set_state(rt2x00dev, state);
1161                 break;
1162         default:
1163                 retval = -ENOTSUPP;
1164                 break;
1165         }
1166
1167         if (unlikely(retval))
1168                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1169                       state, retval);
1170
1171         return retval;
1172 }
1173
1174 /*
1175  * TX descriptor initialization
1176  */
1177 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1178                                     struct sk_buff *skb,
1179                                     struct txentry_desc *txdesc)
1180 {
1181         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1182         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1183         __le32 *txd = skbdesc->desc;
1184         u32 word;
1185
1186         /*
1187          * Start writing the descriptor words.
1188          */
1189         rt2x00_desc_read(entry_priv->desc, 1, &word);
1190         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1191         rt2x00_desc_write(entry_priv->desc, 1, word);
1192
1193         rt2x00_desc_read(txd, 2, &word);
1194         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1195         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1196         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1197         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1198         rt2x00_desc_write(txd, 2, word);
1199
1200         rt2x00_desc_read(txd, 3, &word);
1201         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1202         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1203         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1204         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1205         rt2x00_desc_write(txd, 3, word);
1206
1207         rt2x00_desc_read(txd, 10, &word);
1208         rt2x00_set_field32(&word, TXD_W10_RTS,
1209                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1210         rt2x00_desc_write(txd, 10, word);
1211
1212         rt2x00_desc_read(txd, 0, &word);
1213         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1214         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1215         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1216                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1217         rt2x00_set_field32(&word, TXD_W0_ACK,
1218                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1219         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1220                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1221         rt2x00_set_field32(&word, TXD_W0_OFDM,
1222                            (txdesc->rate_mode == RATE_MODE_OFDM));
1223         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1224         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1225         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1226                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1227         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1228         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1229         rt2x00_desc_write(txd, 0, word);
1230 }
1231
1232 /*
1233  * TX data initialization
1234  */
1235 static void rt2500pci_write_beacon(struct queue_entry *entry)
1236 {
1237         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1238         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1239         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1240         u32 word;
1241         u32 reg;
1242
1243         /*
1244          * Disable beaconing while we are reloading the beacon data,
1245          * otherwise we might be sending out invalid data.
1246          */
1247         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1248         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1249         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1250         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1251         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1252
1253         /*
1254          * Replace rt2x00lib allocated descriptor with the
1255          * pointer to the _real_ hardware descriptor.
1256          * After that, map the beacon to DMA and update the
1257          * descriptor.
1258          */
1259         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1260         skbdesc->desc = entry_priv->desc;
1261
1262         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1263
1264         rt2x00_desc_read(entry_priv->desc, 1, &word);
1265         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1266         rt2x00_desc_write(entry_priv->desc, 1, word);
1267 }
1268
1269 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1270                                     const enum data_queue_qid queue)
1271 {
1272         u32 reg;
1273
1274         if (queue == QID_BEACON) {
1275                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1276                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1277                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1278                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1279                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1280                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1281                 }
1282                 return;
1283         }
1284
1285         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1286         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1287         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1288         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1289         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1290 }
1291
1292 static void rt2500pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1293                                     const enum data_queue_qid qid)
1294 {
1295         u32 reg;
1296
1297         if (qid == QID_BEACON) {
1298                 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1299         } else {
1300                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1301                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1302                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1303         }
1304 }
1305
1306 /*
1307  * RX control handlers
1308  */
1309 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1310                                   struct rxdone_entry_desc *rxdesc)
1311 {
1312         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1313         u32 word0;
1314         u32 word2;
1315
1316         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1317         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1318
1319         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1320                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1321         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1322                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1323
1324         /*
1325          * Obtain the status about this packet.
1326          * When frame was received with an OFDM bitrate,
1327          * the signal is the PLCP value. If it was received with
1328          * a CCK bitrate the signal is the rate in 100kbit/s.
1329          */
1330         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1331         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1332             entry->queue->rt2x00dev->rssi_offset;
1333         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1334
1335         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1336                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1337         else
1338                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
1339         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1340                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1341 }
1342
1343 /*
1344  * Interrupt functions.
1345  */
1346 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1347                              const enum data_queue_qid queue_idx)
1348 {
1349         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1350         struct queue_entry_priv_pci *entry_priv;
1351         struct queue_entry *entry;
1352         struct txdone_entry_desc txdesc;
1353         u32 word;
1354
1355         while (!rt2x00queue_empty(queue)) {
1356                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1357                 entry_priv = entry->priv_data;
1358                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1359
1360                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1361                     !rt2x00_get_field32(word, TXD_W0_VALID))
1362                         break;
1363
1364                 /*
1365                  * Obtain the status about this packet.
1366                  */
1367                 txdesc.flags = 0;
1368                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1369                 case 0: /* Success */
1370                 case 1: /* Success with retry */
1371                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1372                         break;
1373                 case 2: /* Failure, excessive retries */
1374                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1375                         /* Don't break, this is a failed frame! */
1376                 default: /* Failure */
1377                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1378                 }
1379                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1380
1381                 rt2x00lib_txdone(entry, &txdesc);
1382         }
1383 }
1384
1385 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1386 {
1387         struct rt2x00_dev *rt2x00dev = dev_instance;
1388         u32 reg;
1389
1390         /*
1391          * Get the interrupt sources & saved to local variable.
1392          * Write register value back to clear pending interrupts.
1393          */
1394         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1395         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1396
1397         if (!reg)
1398                 return IRQ_NONE;
1399
1400         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1401                 return IRQ_HANDLED;
1402
1403         /*
1404          * Handle interrupts, walk through all bits
1405          * and run the tasks, the bits are checked in order of
1406          * priority.
1407          */
1408
1409         /*
1410          * 1 - Beacon timer expired interrupt.
1411          */
1412         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1413                 rt2x00lib_beacondone(rt2x00dev);
1414
1415         /*
1416          * 2 - Rx ring done interrupt.
1417          */
1418         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1419                 rt2x00pci_rxdone(rt2x00dev);
1420
1421         /*
1422          * 3 - Atim ring transmit done interrupt.
1423          */
1424         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1425                 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1426
1427         /*
1428          * 4 - Priority ring transmit done interrupt.
1429          */
1430         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1431                 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1432
1433         /*
1434          * 5 - Tx ring transmit done interrupt.
1435          */
1436         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1437                 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1438
1439         return IRQ_HANDLED;
1440 }
1441
1442 /*
1443  * Device probe functions.
1444  */
1445 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1446 {
1447         struct eeprom_93cx6 eeprom;
1448         u32 reg;
1449         u16 word;
1450         u8 *mac;
1451
1452         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1453
1454         eeprom.data = rt2x00dev;
1455         eeprom.register_read = rt2500pci_eepromregister_read;
1456         eeprom.register_write = rt2500pci_eepromregister_write;
1457         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1458             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1459         eeprom.reg_data_in = 0;
1460         eeprom.reg_data_out = 0;
1461         eeprom.reg_data_clock = 0;
1462         eeprom.reg_chip_select = 0;
1463
1464         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1465                                EEPROM_SIZE / sizeof(u16));
1466
1467         /*
1468          * Start validation of the data that has been read.
1469          */
1470         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1471         if (!is_valid_ether_addr(mac)) {
1472                 random_ether_addr(mac);
1473                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1474         }
1475
1476         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1477         if (word == 0xffff) {
1478                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1479                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1480                                    ANTENNA_SW_DIVERSITY);
1481                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1482                                    ANTENNA_SW_DIVERSITY);
1483                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1484                                    LED_MODE_DEFAULT);
1485                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1486                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1487                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1488                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1489                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1490         }
1491
1492         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1493         if (word == 0xffff) {
1494                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1495                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1496                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1497                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1498                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1499         }
1500
1501         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1502         if (word == 0xffff) {
1503                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1504                                    DEFAULT_RSSI_OFFSET);
1505                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1506                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1507         }
1508
1509         return 0;
1510 }
1511
1512 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1513 {
1514         u32 reg;
1515         u16 value;
1516         u16 eeprom;
1517
1518         /*
1519          * Read EEPROM word for configuration.
1520          */
1521         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1522
1523         /*
1524          * Identify RF chipset.
1525          */
1526         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1527         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1528         rt2x00_set_chip_rf(rt2x00dev, value, reg);
1529
1530         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1531             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1532             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1533             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1534             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1535             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1536                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1537                 return -ENODEV;
1538         }
1539
1540         /*
1541          * Identify default antenna configuration.
1542          */
1543         rt2x00dev->default_ant.tx =
1544             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1545         rt2x00dev->default_ant.rx =
1546             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1547
1548         /*
1549          * Store led mode, for correct led behaviour.
1550          */
1551 #ifdef CONFIG_RT2X00_LIB_LEDS
1552         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1553
1554         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1555         if (value == LED_MODE_TXRX_ACTIVITY ||
1556             value == LED_MODE_DEFAULT ||
1557             value == LED_MODE_ASUS)
1558                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1559                                    LED_TYPE_ACTIVITY);
1560 #endif /* CONFIG_RT2X00_LIB_LEDS */
1561
1562         /*
1563          * Detect if this device has an hardware controlled radio.
1564          */
1565 #ifdef CONFIG_RT2X00_LIB_RFKILL
1566         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1567                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1568 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1569
1570         /*
1571          * Check if the BBP tuning should be enabled.
1572          */
1573         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1574
1575         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1576                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1577
1578         /*
1579          * Read the RSSI <-> dBm offset information.
1580          */
1581         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1582         rt2x00dev->rssi_offset =
1583             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1584
1585         return 0;
1586 }
1587
1588 /*
1589  * RF value list for RF2522
1590  * Supports: 2.4 GHz
1591  */
1592 static const struct rf_channel rf_vals_bg_2522[] = {
1593         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1594         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1595         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1596         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1597         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1598         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1599         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1600         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1601         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1602         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1603         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1604         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1605         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1606         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1607 };
1608
1609 /*
1610  * RF value list for RF2523
1611  * Supports: 2.4 GHz
1612  */
1613 static const struct rf_channel rf_vals_bg_2523[] = {
1614         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1615         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1616         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1617         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1618         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1619         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1620         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1621         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1622         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1623         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1624         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1625         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1626         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1627         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1628 };
1629
1630 /*
1631  * RF value list for RF2524
1632  * Supports: 2.4 GHz
1633  */
1634 static const struct rf_channel rf_vals_bg_2524[] = {
1635         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1636         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1637         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1638         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1639         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1640         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1641         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1642         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1643         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1644         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1645         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1646         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1647         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1648         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1649 };
1650
1651 /*
1652  * RF value list for RF2525
1653  * Supports: 2.4 GHz
1654  */
1655 static const struct rf_channel rf_vals_bg_2525[] = {
1656         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1657         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1658         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1659         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1660         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1661         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1662         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1663         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1664         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1665         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1666         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1667         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1668         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1669         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1670 };
1671
1672 /*
1673  * RF value list for RF2525e
1674  * Supports: 2.4 GHz
1675  */
1676 static const struct rf_channel rf_vals_bg_2525e[] = {
1677         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1678         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1679         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1680         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1681         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1682         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1683         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1684         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1685         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1686         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1687         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1688         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1689         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1690         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1691 };
1692
1693 /*
1694  * RF value list for RF5222
1695  * Supports: 2.4 GHz & 5.2 GHz
1696  */
1697 static const struct rf_channel rf_vals_5222[] = {
1698         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1699         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1700         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1701         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1702         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1703         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1704         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1705         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1706         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1707         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1708         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1709         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1710         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1711         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1712
1713         /* 802.11 UNI / HyperLan 2 */
1714         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1715         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1716         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1717         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1718         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1719         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1720         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1721         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1722
1723         /* 802.11 HyperLan 2 */
1724         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1725         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1726         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1727         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1728         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1729         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1730         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1731         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1732         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1733         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1734
1735         /* 802.11 UNII */
1736         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1737         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1738         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1739         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1740         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1741 };
1742
1743 static int rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1744 {
1745         struct hw_mode_spec *spec = &rt2x00dev->spec;
1746         struct channel_info *info;
1747         char *tx_power;
1748         unsigned int i;
1749
1750         /*
1751          * Initialize all hw fields.
1752          */
1753         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1754                                IEEE80211_HW_SIGNAL_DBM |
1755                                IEEE80211_HW_SUPPORTS_PS |
1756                                IEEE80211_HW_PS_NULLFUNC_STACK;
1757
1758         rt2x00dev->hw->extra_tx_headroom = 0;
1759
1760         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1761         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1762                                 rt2x00_eeprom_addr(rt2x00dev,
1763                                                    EEPROM_MAC_ADDR_0));
1764
1765         /*
1766          * Initialize hw_mode information.
1767          */
1768         spec->supported_bands = SUPPORT_BAND_2GHZ;
1769         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1770
1771         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1772                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1773                 spec->channels = rf_vals_bg_2522;
1774         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1775                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1776                 spec->channels = rf_vals_bg_2523;
1777         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1778                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1779                 spec->channels = rf_vals_bg_2524;
1780         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1781                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1782                 spec->channels = rf_vals_bg_2525;
1783         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1784                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1785                 spec->channels = rf_vals_bg_2525e;
1786         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1787                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1788                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1789                 spec->channels = rf_vals_5222;
1790         }
1791
1792         /*
1793          * Create channel information array
1794          */
1795         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1796         if (!info)
1797                 return -ENOMEM;
1798
1799         spec->channels_info = info;
1800
1801         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1802         for (i = 0; i < 14; i++)
1803                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1804
1805         if (spec->num_channels > 14) {
1806                 for (i = 14; i < spec->num_channels; i++)
1807                         info[i].tx_power1 = DEFAULT_TXPOWER;
1808         }
1809
1810         return 0;
1811 }
1812
1813 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1814 {
1815         int retval;
1816
1817         /*
1818          * Allocate eeprom data.
1819          */
1820         retval = rt2500pci_validate_eeprom(rt2x00dev);
1821         if (retval)
1822                 return retval;
1823
1824         retval = rt2500pci_init_eeprom(rt2x00dev);
1825         if (retval)
1826                 return retval;
1827
1828         /*
1829          * Initialize hw specifications.
1830          */
1831         retval = rt2500pci_probe_hw_mode(rt2x00dev);
1832         if (retval)
1833                 return retval;
1834
1835         /*
1836          * This device requires the atim queue and DMA-mapped skbs.
1837          */
1838         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1839         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1840
1841         /*
1842          * Set the rssi offset.
1843          */
1844         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1845
1846         return 0;
1847 }
1848
1849 /*
1850  * IEEE80211 stack callback functions.
1851  */
1852 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1853 {
1854         struct rt2x00_dev *rt2x00dev = hw->priv;
1855         u64 tsf;
1856         u32 reg;
1857
1858         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1859         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1860         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1861         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1862
1863         return tsf;
1864 }
1865
1866 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1867 {
1868         struct rt2x00_dev *rt2x00dev = hw->priv;
1869         u32 reg;
1870
1871         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1872         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1873 }
1874
1875 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1876         .tx                     = rt2x00mac_tx,
1877         .start                  = rt2x00mac_start,
1878         .stop                   = rt2x00mac_stop,
1879         .add_interface          = rt2x00mac_add_interface,
1880         .remove_interface       = rt2x00mac_remove_interface,
1881         .config                 = rt2x00mac_config,
1882         .config_interface       = rt2x00mac_config_interface,
1883         .configure_filter       = rt2x00mac_configure_filter,
1884         .get_stats              = rt2x00mac_get_stats,
1885         .bss_info_changed       = rt2x00mac_bss_info_changed,
1886         .conf_tx                = rt2x00mac_conf_tx,
1887         .get_tx_stats           = rt2x00mac_get_tx_stats,
1888         .get_tsf                = rt2500pci_get_tsf,
1889         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1890 };
1891
1892 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1893         .irq_handler            = rt2500pci_interrupt,
1894         .probe_hw               = rt2500pci_probe_hw,
1895         .initialize             = rt2x00pci_initialize,
1896         .uninitialize           = rt2x00pci_uninitialize,
1897         .get_entry_state        = rt2500pci_get_entry_state,
1898         .clear_entry            = rt2500pci_clear_entry,
1899         .set_device_state       = rt2500pci_set_device_state,
1900         .rfkill_poll            = rt2500pci_rfkill_poll,
1901         .link_stats             = rt2500pci_link_stats,
1902         .reset_tuner            = rt2500pci_reset_tuner,
1903         .link_tuner             = rt2500pci_link_tuner,
1904         .write_tx_desc          = rt2500pci_write_tx_desc,
1905         .write_tx_data          = rt2x00pci_write_tx_data,
1906         .write_beacon           = rt2500pci_write_beacon,
1907         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1908         .kill_tx_queue          = rt2500pci_kill_tx_queue,
1909         .fill_rxdone            = rt2500pci_fill_rxdone,
1910         .config_filter          = rt2500pci_config_filter,
1911         .config_intf            = rt2500pci_config_intf,
1912         .config_erp             = rt2500pci_config_erp,
1913         .config_ant             = rt2500pci_config_ant,
1914         .config                 = rt2500pci_config,
1915 };
1916
1917 static const struct data_queue_desc rt2500pci_queue_rx = {
1918         .entry_num              = RX_ENTRIES,
1919         .data_size              = DATA_FRAME_SIZE,
1920         .desc_size              = RXD_DESC_SIZE,
1921         .priv_size              = sizeof(struct queue_entry_priv_pci),
1922 };
1923
1924 static const struct data_queue_desc rt2500pci_queue_tx = {
1925         .entry_num              = TX_ENTRIES,
1926         .data_size              = DATA_FRAME_SIZE,
1927         .desc_size              = TXD_DESC_SIZE,
1928         .priv_size              = sizeof(struct queue_entry_priv_pci),
1929 };
1930
1931 static const struct data_queue_desc rt2500pci_queue_bcn = {
1932         .entry_num              = BEACON_ENTRIES,
1933         .data_size              = MGMT_FRAME_SIZE,
1934         .desc_size              = TXD_DESC_SIZE,
1935         .priv_size              = sizeof(struct queue_entry_priv_pci),
1936 };
1937
1938 static const struct data_queue_desc rt2500pci_queue_atim = {
1939         .entry_num              = ATIM_ENTRIES,
1940         .data_size              = DATA_FRAME_SIZE,
1941         .desc_size              = TXD_DESC_SIZE,
1942         .priv_size              = sizeof(struct queue_entry_priv_pci),
1943 };
1944
1945 static const struct rt2x00_ops rt2500pci_ops = {
1946         .name           = KBUILD_MODNAME,
1947         .max_sta_intf   = 1,
1948         .max_ap_intf    = 1,
1949         .eeprom_size    = EEPROM_SIZE,
1950         .rf_size        = RF_SIZE,
1951         .tx_queues      = NUM_TX_QUEUES,
1952         .rx             = &rt2500pci_queue_rx,
1953         .tx             = &rt2500pci_queue_tx,
1954         .bcn            = &rt2500pci_queue_bcn,
1955         .atim           = &rt2500pci_queue_atim,
1956         .lib            = &rt2500pci_rt2x00_ops,
1957         .hw             = &rt2500pci_mac80211_ops,
1958 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1959         .debugfs        = &rt2500pci_rt2x00debug,
1960 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1961 };
1962
1963 /*
1964  * RT2500pci module information.
1965  */
1966 static struct pci_device_id rt2500pci_device_table[] = {
1967         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1968         { 0, }
1969 };
1970
1971 MODULE_AUTHOR(DRV_PROJECT);
1972 MODULE_VERSION(DRV_VERSION);
1973 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1974 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1975 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1976 MODULE_LICENSE("GPL");
1977
1978 static struct pci_driver rt2500pci_driver = {
1979         .name           = KBUILD_MODNAME,
1980         .id_table       = rt2500pci_device_table,
1981         .probe          = rt2x00pci_probe,
1982         .remove         = __devexit_p(rt2x00pci_remove),
1983         .suspend        = rt2x00pci_suspend,
1984         .resume         = rt2x00pci_resume,
1985 };
1986
1987 static int __init rt2500pci_init(void)
1988 {
1989         return pci_register_driver(&rt2500pci_driver);
1990 }
1991
1992 static void __exit rt2500pci_exit(void)
1993 {
1994         pci_unregister_driver(&rt2500pci_driver);
1995 }
1996
1997 module_init(rt2500pci_init);
1998 module_exit(rt2500pci_exit);