e87ad43e8e8d36f599494bbddfc81c9c6ac65988
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2400pci
23         Abstract: rt2400pci device specific routines.
24         Supported chipsets: RT2460.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
38
39 /*
40  * Register access.
41  * All access to the CSR registers will go through the methods
42  * rt2x00pci_register_read and rt2x00pci_register_write.
43  * BBP and RF register require indirect register access,
44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
45  * These indirect registers work with busy bits,
46  * and we will try maximal REGISTER_BUSY_COUNT times to access
47  * the register while taking a REGISTER_BUSY_DELAY us delay
48  * between each attampt. When the busy bit is still set at that time,
49  * the access attempt is considered to have failed,
50  * and we will print an error.
51  */
52 #define WAIT_FOR_BBP(__dev, __reg) \
53         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 #define WAIT_FOR_RF(__dev, __reg) \
55         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
58                                 const unsigned int word, const u8 value)
59 {
60         u32 reg;
61
62         mutex_lock(&rt2x00dev->csr_mutex);
63
64         /*
65          * Wait until the BBP becomes available, afterwards we
66          * can safely write the new data into the register.
67          */
68         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69                 reg = 0;
70                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76         }
77
78         mutex_unlock(&rt2x00dev->csr_mutex);
79 }
80
81 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
82                                const unsigned int word, u8 *value)
83 {
84         u32 reg;
85
86         mutex_lock(&rt2x00dev->csr_mutex);
87
88         /*
89          * Wait until the BBP becomes available, afterwards we
90          * can safely write the read request into the register.
91          * After the data has been written, we wait until hardware
92          * returns the correct value, if at any time the register
93          * doesn't become available in time, reg will be 0xffffffff
94          * which means we return 0xff to the caller.
95          */
96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97                 reg = 0;
98                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
101
102                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
103
104                 WAIT_FOR_BBP(rt2x00dev, &reg);
105         }
106
107         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
113                                const unsigned int word, const u32 value)
114 {
115         u32 reg;
116
117         if (!word)
118                 return;
119
120         mutex_lock(&rt2x00dev->csr_mutex);
121
122         /*
123          * Wait until the RF becomes available, afterwards we
124          * can safely write the new data into the register.
125          */
126         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
127                 reg = 0;
128                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
129                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
130                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
131                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
132
133                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
134                 rt2x00_rf_write(rt2x00dev, word, value);
135         }
136
137         mutex_unlock(&rt2x00dev->csr_mutex);
138 }
139
140 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
141 {
142         struct rt2x00_dev *rt2x00dev = eeprom->data;
143         u32 reg;
144
145         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
146
147         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
148         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
149         eeprom->reg_data_clock =
150             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
151         eeprom->reg_chip_select =
152             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
153 }
154
155 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
156 {
157         struct rt2x00_dev *rt2x00dev = eeprom->data;
158         u32 reg = 0;
159
160         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
161         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
162         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
163                            !!eeprom->reg_data_clock);
164         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
165                            !!eeprom->reg_chip_select);
166
167         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
168 }
169
170 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
171 static const struct rt2x00debug rt2400pci_rt2x00debug = {
172         .owner  = THIS_MODULE,
173         .csr    = {
174                 .read           = rt2x00pci_register_read,
175                 .write          = rt2x00pci_register_write,
176                 .flags          = RT2X00DEBUGFS_OFFSET,
177                 .word_base      = CSR_REG_BASE,
178                 .word_size      = sizeof(u32),
179                 .word_count     = CSR_REG_SIZE / sizeof(u32),
180         },
181         .eeprom = {
182                 .read           = rt2x00_eeprom_read,
183                 .write          = rt2x00_eeprom_write,
184                 .word_base      = EEPROM_BASE,
185                 .word_size      = sizeof(u16),
186                 .word_count     = EEPROM_SIZE / sizeof(u16),
187         },
188         .bbp    = {
189                 .read           = rt2400pci_bbp_read,
190                 .write          = rt2400pci_bbp_write,
191                 .word_base      = BBP_BASE,
192                 .word_size      = sizeof(u8),
193                 .word_count     = BBP_SIZE / sizeof(u8),
194         },
195         .rf     = {
196                 .read           = rt2x00_rf_read,
197                 .write          = rt2400pci_rf_write,
198                 .word_base      = RF_BASE,
199                 .word_size      = sizeof(u32),
200                 .word_count     = RF_SIZE / sizeof(u32),
201         },
202 };
203 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
204
205 #ifdef CONFIG_RT2X00_LIB_RFKILL
206 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
207 {
208         u32 reg;
209
210         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
211         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
212 }
213 #else
214 #define rt2400pci_rfkill_poll   NULL
215 #endif /* CONFIG_RT2X00_LIB_RFKILL */
216
217 #ifdef CONFIG_RT2X00_LIB_LEDS
218 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
219                                      enum led_brightness brightness)
220 {
221         struct rt2x00_led *led =
222             container_of(led_cdev, struct rt2x00_led, led_dev);
223         unsigned int enabled = brightness != LED_OFF;
224         u32 reg;
225
226         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
227
228         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
229                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
230         else if (led->type == LED_TYPE_ACTIVITY)
231                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
232
233         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
234 }
235
236 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
237                                unsigned long *delay_on,
238                                unsigned long *delay_off)
239 {
240         struct rt2x00_led *led =
241             container_of(led_cdev, struct rt2x00_led, led_dev);
242         u32 reg;
243
244         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
245         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
246         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
247         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
248
249         return 0;
250 }
251
252 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
253                                struct rt2x00_led *led,
254                                enum led_type type)
255 {
256         led->rt2x00dev = rt2x00dev;
257         led->type = type;
258         led->led_dev.brightness_set = rt2400pci_brightness_set;
259         led->led_dev.blink_set = rt2400pci_blink_set;
260         led->flags = LED_INITIALIZED;
261 }
262 #endif /* CONFIG_RT2X00_LIB_LEDS */
263
264 /*
265  * Configuration handlers.
266  */
267 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
268                                     const unsigned int filter_flags)
269 {
270         u32 reg;
271
272         /*
273          * Start configuration steps.
274          * Note that the version error will always be dropped
275          * since there is no filter for it at this time.
276          */
277         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
278         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
279                            !(filter_flags & FIF_FCSFAIL));
280         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
281                            !(filter_flags & FIF_PLCPFAIL));
282         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
283                            !(filter_flags & FIF_CONTROL));
284         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
285                            !(filter_flags & FIF_PROMISC_IN_BSS));
286         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
287                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
288                            !rt2x00dev->intf_ap_count);
289         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
290         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
291 }
292
293 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
294                                   struct rt2x00_intf *intf,
295                                   struct rt2x00intf_conf *conf,
296                                   const unsigned int flags)
297 {
298         unsigned int bcn_preload;
299         u32 reg;
300
301         if (flags & CONFIG_UPDATE_TYPE) {
302                 /*
303                  * Enable beacon config
304                  */
305                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
306                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
307                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
308                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
309
310                 /*
311                  * Enable synchronisation.
312                  */
313                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
314                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
315                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
316                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
317                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
318         }
319
320         if (flags & CONFIG_UPDATE_MAC)
321                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
322                                               conf->mac, sizeof(conf->mac));
323
324         if (flags & CONFIG_UPDATE_BSSID)
325                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
326                                               conf->bssid, sizeof(conf->bssid));
327 }
328
329 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
330                                  struct rt2x00lib_erp *erp)
331 {
332         int preamble_mask;
333         u32 reg;
334
335         /*
336          * When short preamble is enabled, we should set bit 0x08
337          */
338         preamble_mask = erp->short_preamble << 3;
339
340         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
341         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
342                            erp->ack_timeout);
343         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
344                            erp->ack_consume_time);
345         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
346
347         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
348         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
349         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
350         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
351         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
352
353         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
354         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
355         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
356         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
357         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
358
359         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
360         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
361         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
362         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
363         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
364
365         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
366         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
367         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
368         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
369         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
370
371         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
372
373         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
374         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
375         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
376
377         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
378         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
379         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
380         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
381
382         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
383         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
384         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
385         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
386 }
387
388 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
389                                  struct antenna_setup *ant)
390 {
391         u8 r1;
392         u8 r4;
393
394         /*
395          * We should never come here because rt2x00lib is supposed
396          * to catch this and send us the correct antenna explicitely.
397          */
398         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
399                ant->tx == ANTENNA_SW_DIVERSITY);
400
401         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
402         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
403
404         /*
405          * Configure the TX antenna.
406          */
407         switch (ant->tx) {
408         case ANTENNA_HW_DIVERSITY:
409                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
410                 break;
411         case ANTENNA_A:
412                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
413                 break;
414         case ANTENNA_B:
415         default:
416                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
417                 break;
418         }
419
420         /*
421          * Configure the RX antenna.
422          */
423         switch (ant->rx) {
424         case ANTENNA_HW_DIVERSITY:
425                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
426                 break;
427         case ANTENNA_A:
428                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
429                 break;
430         case ANTENNA_B:
431         default:
432                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
433                 break;
434         }
435
436         rt2400pci_bbp_write(rt2x00dev, 4, r4);
437         rt2400pci_bbp_write(rt2x00dev, 1, r1);
438 }
439
440 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
441                                      struct rf_channel *rf)
442 {
443         /*
444          * Switch on tuning bits.
445          */
446         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
447         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
448
449         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
450         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
451         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
452
453         /*
454          * RF2420 chipset don't need any additional actions.
455          */
456         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
457                 return;
458
459         /*
460          * For the RT2421 chipsets we need to write an invalid
461          * reference clock rate to activate auto_tune.
462          * After that we set the value back to the correct channel.
463          */
464         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
465         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
466         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
467
468         msleep(1);
469
470         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
471         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
472         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
473
474         msleep(1);
475
476         /*
477          * Switch off tuning bits.
478          */
479         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
480         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
481
482         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
483         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
484
485         /*
486          * Clear false CRC during channel switch.
487          */
488         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
489 }
490
491 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
492 {
493         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
494 }
495
496 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
497                                          struct rt2x00lib_conf *libconf)
498 {
499         u32 reg;
500
501         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
502         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
503                            libconf->conf->long_frame_max_tx_count);
504         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
505                            libconf->conf->short_frame_max_tx_count);
506         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
507 }
508
509 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
510                                       struct rt2x00lib_conf *libconf)
511 {
512         u32 reg;
513
514         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
515         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
516         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
517         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
518
519         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
520         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
521                            libconf->conf->beacon_int * 16);
522         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
523                            libconf->conf->beacon_int * 16);
524         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
525 }
526
527 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
528                                 struct rt2x00lib_conf *libconf)
529 {
530         enum dev_state state =
531             (libconf->conf->flags & IEEE80211_CONF_PS) ?
532                 STATE_SLEEP : STATE_AWAKE;
533         u32 reg;
534
535         if (state == STATE_SLEEP) {
536                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
537                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
538                                    (libconf->conf->beacon_int - 20) * 16);
539                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
540                                    libconf->conf->listen_interval - 1);
541
542                 /* We must first disable autowake before it can be enabled */
543                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
544                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
545
546                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
547                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
548         }
549
550         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
551 }
552
553 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
554                              struct rt2x00lib_conf *libconf,
555                              const unsigned int flags)
556 {
557         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
558                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
559         if (flags & IEEE80211_CONF_CHANGE_POWER)
560                 rt2400pci_config_txpower(rt2x00dev,
561                                          libconf->conf->power_level);
562         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
563                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
564         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
565                 rt2400pci_config_duration(rt2x00dev, libconf);
566         if (flags & IEEE80211_CONF_CHANGE_PS)
567                 rt2400pci_config_ps(rt2x00dev, libconf);
568 }
569
570 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
571                                 const int cw_min, const int cw_max)
572 {
573         u32 reg;
574
575         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
576         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
577         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
578         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
579 }
580
581 /*
582  * Link tuning
583  */
584 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
585                                  struct link_qual *qual)
586 {
587         u32 reg;
588         u8 bbp;
589
590         /*
591          * Update FCS error count from register.
592          */
593         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
594         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
595
596         /*
597          * Update False CCA count from register.
598          */
599         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
600         qual->false_cca = bbp;
601 }
602
603 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev, u8 vgc_level)
604 {
605         rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
606         rt2x00dev->link.vgc_level = vgc_level;
607         rt2x00dev->link.vgc_level_reg = vgc_level;
608 }
609
610 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
611 {
612         rt2400pci_set_vgc(rt2x00dev, 0x08);
613 }
614
615 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
616 {
617         struct link *link = &rt2x00dev->link;
618
619         /*
620          * The link tuner should not run longer then 60 seconds,
621          * and should run once every 2 seconds.
622          */
623         if (link->count > 60 || !(link->count & 1))
624                 return;
625
626         /*
627          * Base r13 link tuning on the false cca count.
628          */
629         if ((link->qual.false_cca > 512) && (link->vgc_level < 0x20))
630                 rt2400pci_set_vgc(rt2x00dev, ++link->vgc_level);
631         else if ((link->qual.false_cca < 100) && (link->vgc_level > 0x08))
632                 rt2400pci_set_vgc(rt2x00dev, --link->vgc_level);
633 }
634
635 /*
636  * Initialization functions.
637  */
638 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
639 {
640         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
641         u32 word;
642
643         if (entry->queue->qid == QID_RX) {
644                 rt2x00_desc_read(entry_priv->desc, 0, &word);
645
646                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
647         } else {
648                 rt2x00_desc_read(entry_priv->desc, 0, &word);
649
650                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
651                         rt2x00_get_field32(word, TXD_W0_VALID));
652         }
653 }
654
655 static void rt2400pci_clear_entry(struct queue_entry *entry)
656 {
657         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
658         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
659         u32 word;
660
661         if (entry->queue->qid == QID_RX) {
662                 rt2x00_desc_read(entry_priv->desc, 2, &word);
663                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
664                 rt2x00_desc_write(entry_priv->desc, 2, word);
665
666                 rt2x00_desc_read(entry_priv->desc, 1, &word);
667                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
668                 rt2x00_desc_write(entry_priv->desc, 1, word);
669
670                 rt2x00_desc_read(entry_priv->desc, 0, &word);
671                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
672                 rt2x00_desc_write(entry_priv->desc, 0, word);
673         } else {
674                 rt2x00_desc_read(entry_priv->desc, 0, &word);
675                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
676                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
677                 rt2x00_desc_write(entry_priv->desc, 0, word);
678         }
679 }
680
681 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
682 {
683         struct queue_entry_priv_pci *entry_priv;
684         u32 reg;
685
686         /*
687          * Initialize registers.
688          */
689         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
690         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
691         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
692         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
693         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
694         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
695
696         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
697         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
698         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
699                            entry_priv->desc_dma);
700         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
701
702         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
703         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
704         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
705                            entry_priv->desc_dma);
706         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
707
708         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
709         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
710         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
711                            entry_priv->desc_dma);
712         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
713
714         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
715         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
716         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
717                            entry_priv->desc_dma);
718         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
719
720         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
721         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
722         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
723         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
724
725         entry_priv = rt2x00dev->rx->entries[0].priv_data;
726         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
727         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
728                            entry_priv->desc_dma);
729         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
730
731         return 0;
732 }
733
734 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
735 {
736         u32 reg;
737
738         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
739         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
740         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
741         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
742
743         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
744         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
745         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
746         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
747         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
748
749         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
750         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
751                            (rt2x00dev->rx->data_size / 128));
752         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
753
754         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
755         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
756         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
757         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
758         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
759         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
760         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
761         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
762         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
763         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
764
765         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
766
767         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
768         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
769         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
770         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
771         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
772         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
773
774         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
775         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
776         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
777         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
778         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
779         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
780         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
781         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
782
783         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
784
785         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
786                 return -EBUSY;
787
788         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
789         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
790
791         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
792         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
793         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
794
795         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
796         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
797         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
798         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
799         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
800         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
801
802         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
803         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
804         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
805         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
806         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
807
808         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
809         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
810         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
811         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
812
813         /*
814          * We must clear the FCS and FIFO error count.
815          * These registers are cleared on read,
816          * so we may pass a useless variable to store the value.
817          */
818         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
819         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
820
821         return 0;
822 }
823
824 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
825 {
826         unsigned int i;
827         u8 value;
828
829         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
830                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
831                 if ((value != 0xff) && (value != 0x00))
832                         return 0;
833                 udelay(REGISTER_BUSY_DELAY);
834         }
835
836         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
837         return -EACCES;
838 }
839
840 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
841 {
842         unsigned int i;
843         u16 eeprom;
844         u8 reg_id;
845         u8 value;
846
847         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
848                 return -EACCES;
849
850         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
851         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
852         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
853         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
854         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
855         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
856         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
857         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
858         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
859         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
860         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
861         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
862         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
863         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
864
865         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
866                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
867
868                 if (eeprom != 0xffff && eeprom != 0x0000) {
869                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
870                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
871                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
872                 }
873         }
874
875         return 0;
876 }
877
878 /*
879  * Device state switch handlers.
880  */
881 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
882                                 enum dev_state state)
883 {
884         u32 reg;
885
886         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
887         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
888                            (state == STATE_RADIO_RX_OFF) ||
889                            (state == STATE_RADIO_RX_OFF_LINK));
890         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
891 }
892
893 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
894                                  enum dev_state state)
895 {
896         int mask = (state == STATE_RADIO_IRQ_OFF);
897         u32 reg;
898
899         /*
900          * When interrupts are being enabled, the interrupt registers
901          * should clear the register to assure a clean state.
902          */
903         if (state == STATE_RADIO_IRQ_ON) {
904                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
905                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
906         }
907
908         /*
909          * Only toggle the interrupts bits we are going to use.
910          * Non-checked interrupt bits are disabled by default.
911          */
912         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
913         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
914         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
915         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
916         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
917         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
918         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
919 }
920
921 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
922 {
923         /*
924          * Initialize all registers.
925          */
926         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
927                      rt2400pci_init_registers(rt2x00dev) ||
928                      rt2400pci_init_bbp(rt2x00dev)))
929                 return -EIO;
930
931         return 0;
932 }
933
934 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
935 {
936         u32 reg;
937
938         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
939
940         /*
941          * Disable synchronisation.
942          */
943         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
944
945         /*
946          * Cancel RX and TX.
947          */
948         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
949         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
950         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
951 }
952
953 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
954                                enum dev_state state)
955 {
956         u32 reg;
957         unsigned int i;
958         char put_to_sleep;
959         char bbp_state;
960         char rf_state;
961
962         put_to_sleep = (state != STATE_AWAKE);
963
964         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
965         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
966         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
967         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
968         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
969         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
970
971         /*
972          * Device is not guaranteed to be in the requested state yet.
973          * We must wait until the register indicates that the
974          * device has entered the correct state.
975          */
976         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
977                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
978                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
979                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
980                 if (bbp_state == state && rf_state == state)
981                         return 0;
982                 msleep(10);
983         }
984
985         return -EBUSY;
986 }
987
988 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
989                                       enum dev_state state)
990 {
991         int retval = 0;
992
993         switch (state) {
994         case STATE_RADIO_ON:
995                 retval = rt2400pci_enable_radio(rt2x00dev);
996                 break;
997         case STATE_RADIO_OFF:
998                 rt2400pci_disable_radio(rt2x00dev);
999                 break;
1000         case STATE_RADIO_RX_ON:
1001         case STATE_RADIO_RX_ON_LINK:
1002         case STATE_RADIO_RX_OFF:
1003         case STATE_RADIO_RX_OFF_LINK:
1004                 rt2400pci_toggle_rx(rt2x00dev, state);
1005                 break;
1006         case STATE_RADIO_IRQ_ON:
1007         case STATE_RADIO_IRQ_OFF:
1008                 rt2400pci_toggle_irq(rt2x00dev, state);
1009                 break;
1010         case STATE_DEEP_SLEEP:
1011         case STATE_SLEEP:
1012         case STATE_STANDBY:
1013         case STATE_AWAKE:
1014                 retval = rt2400pci_set_state(rt2x00dev, state);
1015                 break;
1016         default:
1017                 retval = -ENOTSUPP;
1018                 break;
1019         }
1020
1021         if (unlikely(retval))
1022                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1023                       state, retval);
1024
1025         return retval;
1026 }
1027
1028 /*
1029  * TX descriptor initialization
1030  */
1031 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1032                                     struct sk_buff *skb,
1033                                     struct txentry_desc *txdesc)
1034 {
1035         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1036         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1037         __le32 *txd = skbdesc->desc;
1038         u32 word;
1039
1040         /*
1041          * Start writing the descriptor words.
1042          */
1043         rt2x00_desc_read(entry_priv->desc, 1, &word);
1044         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1045         rt2x00_desc_write(entry_priv->desc, 1, word);
1046
1047         rt2x00_desc_read(txd, 2, &word);
1048         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1049         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1050         rt2x00_desc_write(txd, 2, word);
1051
1052         rt2x00_desc_read(txd, 3, &word);
1053         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1054         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1055         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1056         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1057         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1058         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1059         rt2x00_desc_write(txd, 3, word);
1060
1061         rt2x00_desc_read(txd, 4, &word);
1062         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1063         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1064         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1065         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1066         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1067         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1068         rt2x00_desc_write(txd, 4, word);
1069
1070         rt2x00_desc_read(txd, 0, &word);
1071         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1072         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1073         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1074                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1075         rt2x00_set_field32(&word, TXD_W0_ACK,
1076                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1077         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1078                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1079         rt2x00_set_field32(&word, TXD_W0_RTS,
1080                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1081         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1082         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1083                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1084         rt2x00_desc_write(txd, 0, word);
1085 }
1086
1087 /*
1088  * TX data initialization
1089  */
1090 static void rt2400pci_write_beacon(struct queue_entry *entry)
1091 {
1092         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1093         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1094         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1095         u32 word;
1096         u32 reg;
1097
1098         /*
1099          * Disable beaconing while we are reloading the beacon data,
1100          * otherwise we might be sending out invalid data.
1101          */
1102         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1103         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1104         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1105         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1106         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1107
1108         /*
1109          * Replace rt2x00lib allocated descriptor with the
1110          * pointer to the _real_ hardware descriptor.
1111          * After that, map the beacon to DMA and update the
1112          * descriptor.
1113          */
1114         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1115         skbdesc->desc = entry_priv->desc;
1116
1117         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1118
1119         rt2x00_desc_read(entry_priv->desc, 1, &word);
1120         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1121         rt2x00_desc_write(entry_priv->desc, 1, word);
1122 }
1123
1124 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1125                                     const enum data_queue_qid queue)
1126 {
1127         u32 reg;
1128
1129         if (queue == QID_BEACON) {
1130                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1131                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1132                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1133                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1134                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1135                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1136                 }
1137                 return;
1138         }
1139
1140         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1141         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1142         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1143         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1144         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1145 }
1146
1147 /*
1148  * RX control handlers
1149  */
1150 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1151                                   struct rxdone_entry_desc *rxdesc)
1152 {
1153         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1154         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1155         u32 word0;
1156         u32 word2;
1157         u32 word3;
1158         u32 word4;
1159         u64 tsf;
1160         u32 rx_low;
1161         u32 rx_high;
1162
1163         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1164         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1165         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1166         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1167
1168         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1169                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1170         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1171                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1172
1173         /*
1174          * We only get the lower 32bits from the timestamp,
1175          * to get the full 64bits we must complement it with
1176          * the timestamp from get_tsf().
1177          * Note that when a wraparound of the lower 32bits
1178          * has occurred between the frame arrival and the get_tsf()
1179          * call, we must decrease the higher 32bits with 1 to get
1180          * to correct value.
1181          */
1182         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1183         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1184         rx_high = upper_32_bits(tsf);
1185
1186         if ((u32)tsf <= rx_low)
1187                 rx_high--;
1188
1189         /*
1190          * Obtain the status about this packet.
1191          * The signal is the PLCP value, and needs to be stripped
1192          * of the preamble bit (0x08).
1193          */
1194         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1195         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1196         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1197             entry->queue->rt2x00dev->rssi_offset;
1198         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1199
1200         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1201         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1202                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1203 }
1204
1205 /*
1206  * Interrupt functions.
1207  */
1208 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1209                              const enum data_queue_qid queue_idx)
1210 {
1211         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1212         struct queue_entry_priv_pci *entry_priv;
1213         struct queue_entry *entry;
1214         struct txdone_entry_desc txdesc;
1215         u32 word;
1216
1217         while (!rt2x00queue_empty(queue)) {
1218                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1219                 entry_priv = entry->priv_data;
1220                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1221
1222                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1223                     !rt2x00_get_field32(word, TXD_W0_VALID))
1224                         break;
1225
1226                 /*
1227                  * Obtain the status about this packet.
1228                  */
1229                 txdesc.flags = 0;
1230                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1231                 case 0: /* Success */
1232                 case 1: /* Success with retry */
1233                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1234                         break;
1235                 case 2: /* Failure, excessive retries */
1236                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1237                         /* Don't break, this is a failed frame! */
1238                 default: /* Failure */
1239                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1240                 }
1241                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1242
1243                 rt2x00lib_txdone(entry, &txdesc);
1244         }
1245 }
1246
1247 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1248 {
1249         struct rt2x00_dev *rt2x00dev = dev_instance;
1250         u32 reg;
1251
1252         /*
1253          * Get the interrupt sources & saved to local variable.
1254          * Write register value back to clear pending interrupts.
1255          */
1256         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1257         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1258
1259         if (!reg)
1260                 return IRQ_NONE;
1261
1262         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1263                 return IRQ_HANDLED;
1264
1265         /*
1266          * Handle interrupts, walk through all bits
1267          * and run the tasks, the bits are checked in order of
1268          * priority.
1269          */
1270
1271         /*
1272          * 1 - Beacon timer expired interrupt.
1273          */
1274         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1275                 rt2x00lib_beacondone(rt2x00dev);
1276
1277         /*
1278          * 2 - Rx ring done interrupt.
1279          */
1280         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1281                 rt2x00pci_rxdone(rt2x00dev);
1282
1283         /*
1284          * 3 - Atim ring transmit done interrupt.
1285          */
1286         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1287                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1288
1289         /*
1290          * 4 - Priority ring transmit done interrupt.
1291          */
1292         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1293                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1294
1295         /*
1296          * 5 - Tx ring transmit done interrupt.
1297          */
1298         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1299                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1300
1301         return IRQ_HANDLED;
1302 }
1303
1304 /*
1305  * Device probe functions.
1306  */
1307 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1308 {
1309         struct eeprom_93cx6 eeprom;
1310         u32 reg;
1311         u16 word;
1312         u8 *mac;
1313
1314         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1315
1316         eeprom.data = rt2x00dev;
1317         eeprom.register_read = rt2400pci_eepromregister_read;
1318         eeprom.register_write = rt2400pci_eepromregister_write;
1319         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1320             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1321         eeprom.reg_data_in = 0;
1322         eeprom.reg_data_out = 0;
1323         eeprom.reg_data_clock = 0;
1324         eeprom.reg_chip_select = 0;
1325
1326         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1327                                EEPROM_SIZE / sizeof(u16));
1328
1329         /*
1330          * Start validation of the data that has been read.
1331          */
1332         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1333         if (!is_valid_ether_addr(mac)) {
1334                 random_ether_addr(mac);
1335                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1336         }
1337
1338         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1339         if (word == 0xffff) {
1340                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1341                 return -EINVAL;
1342         }
1343
1344         return 0;
1345 }
1346
1347 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1348 {
1349         u32 reg;
1350         u16 value;
1351         u16 eeprom;
1352
1353         /*
1354          * Read EEPROM word for configuration.
1355          */
1356         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1357
1358         /*
1359          * Identify RF chipset.
1360          */
1361         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1362         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1363         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1364
1365         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1366             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1367                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1368                 return -ENODEV;
1369         }
1370
1371         /*
1372          * Identify default antenna configuration.
1373          */
1374         rt2x00dev->default_ant.tx =
1375             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1376         rt2x00dev->default_ant.rx =
1377             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1378
1379         /*
1380          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1381          * I am not 100% sure about this, but the legacy drivers do not
1382          * indicate antenna swapping in software is required when
1383          * diversity is enabled.
1384          */
1385         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1386                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1387         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1388                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1389
1390         /*
1391          * Store led mode, for correct led behaviour.
1392          */
1393 #ifdef CONFIG_RT2X00_LIB_LEDS
1394         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1395
1396         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1397         if (value == LED_MODE_TXRX_ACTIVITY)
1398                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1399                                    LED_TYPE_ACTIVITY);
1400 #endif /* CONFIG_RT2X00_LIB_LEDS */
1401
1402         /*
1403          * Detect if this device has an hardware controlled radio.
1404          */
1405 #ifdef CONFIG_RT2X00_LIB_RFKILL
1406         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1407                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1408 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1409
1410         /*
1411          * Check if the BBP tuning should be enabled.
1412          */
1413         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1414                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1415
1416         return 0;
1417 }
1418
1419 /*
1420  * RF value list for RF2420 & RF2421
1421  * Supports: 2.4 GHz
1422  */
1423 static const struct rf_channel rf_vals_b[] = {
1424         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1425         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1426         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1427         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1428         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1429         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1430         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1431         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1432         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1433         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1434         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1435         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1436         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1437         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1438 };
1439
1440 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1441 {
1442         struct hw_mode_spec *spec = &rt2x00dev->spec;
1443         struct channel_info *info;
1444         char *tx_power;
1445         unsigned int i;
1446
1447         /*
1448          * Initialize all hw fields.
1449          */
1450         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1451                                IEEE80211_HW_SIGNAL_DBM;
1452         rt2x00dev->hw->extra_tx_headroom = 0;
1453
1454         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1455         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1456                                 rt2x00_eeprom_addr(rt2x00dev,
1457                                                    EEPROM_MAC_ADDR_0));
1458
1459         /*
1460          * Initialize hw_mode information.
1461          */
1462         spec->supported_bands = SUPPORT_BAND_2GHZ;
1463         spec->supported_rates = SUPPORT_RATE_CCK;
1464
1465         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1466         spec->channels = rf_vals_b;
1467
1468         /*
1469          * Create channel information array
1470          */
1471         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1472         if (!info)
1473                 return -ENOMEM;
1474
1475         spec->channels_info = info;
1476
1477         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1478         for (i = 0; i < 14; i++)
1479                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1480
1481         return 0;
1482 }
1483
1484 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1485 {
1486         int retval;
1487
1488         /*
1489          * Allocate eeprom data.
1490          */
1491         retval = rt2400pci_validate_eeprom(rt2x00dev);
1492         if (retval)
1493                 return retval;
1494
1495         retval = rt2400pci_init_eeprom(rt2x00dev);
1496         if (retval)
1497                 return retval;
1498
1499         /*
1500          * Initialize hw specifications.
1501          */
1502         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1503         if (retval)
1504                 return retval;
1505
1506         /*
1507          * This device requires the atim queue and DMA-mapped skbs.
1508          */
1509         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1510         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1511
1512         /*
1513          * Set the rssi offset.
1514          */
1515         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1516
1517         return 0;
1518 }
1519
1520 /*
1521  * IEEE80211 stack callback functions.
1522  */
1523 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1524                              const struct ieee80211_tx_queue_params *params)
1525 {
1526         struct rt2x00_dev *rt2x00dev = hw->priv;
1527
1528         /*
1529          * We don't support variating cw_min and cw_max variables
1530          * per queue. So by default we only configure the TX queue,
1531          * and ignore all other configurations.
1532          */
1533         if (queue != 0)
1534                 return -EINVAL;
1535
1536         if (rt2x00mac_conf_tx(hw, queue, params))
1537                 return -EINVAL;
1538
1539         /*
1540          * Write configuration to register.
1541          */
1542         rt2400pci_config_cw(rt2x00dev,
1543                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1544
1545         return 0;
1546 }
1547
1548 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1549 {
1550         struct rt2x00_dev *rt2x00dev = hw->priv;
1551         u64 tsf;
1552         u32 reg;
1553
1554         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1555         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1556         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1557         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1558
1559         return tsf;
1560 }
1561
1562 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1563 {
1564         struct rt2x00_dev *rt2x00dev = hw->priv;
1565         u32 reg;
1566
1567         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1568         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1569 }
1570
1571 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1572         .tx                     = rt2x00mac_tx,
1573         .start                  = rt2x00mac_start,
1574         .stop                   = rt2x00mac_stop,
1575         .add_interface          = rt2x00mac_add_interface,
1576         .remove_interface       = rt2x00mac_remove_interface,
1577         .config                 = rt2x00mac_config,
1578         .config_interface       = rt2x00mac_config_interface,
1579         .configure_filter       = rt2x00mac_configure_filter,
1580         .get_stats              = rt2x00mac_get_stats,
1581         .bss_info_changed       = rt2x00mac_bss_info_changed,
1582         .conf_tx                = rt2400pci_conf_tx,
1583         .get_tx_stats           = rt2x00mac_get_tx_stats,
1584         .get_tsf                = rt2400pci_get_tsf,
1585         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1586 };
1587
1588 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1589         .irq_handler            = rt2400pci_interrupt,
1590         .probe_hw               = rt2400pci_probe_hw,
1591         .initialize             = rt2x00pci_initialize,
1592         .uninitialize           = rt2x00pci_uninitialize,
1593         .get_entry_state        = rt2400pci_get_entry_state,
1594         .clear_entry            = rt2400pci_clear_entry,
1595         .set_device_state       = rt2400pci_set_device_state,
1596         .rfkill_poll            = rt2400pci_rfkill_poll,
1597         .link_stats             = rt2400pci_link_stats,
1598         .reset_tuner            = rt2400pci_reset_tuner,
1599         .link_tuner             = rt2400pci_link_tuner,
1600         .write_tx_desc          = rt2400pci_write_tx_desc,
1601         .write_tx_data          = rt2x00pci_write_tx_data,
1602         .write_beacon           = rt2400pci_write_beacon,
1603         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1604         .fill_rxdone            = rt2400pci_fill_rxdone,
1605         .config_filter          = rt2400pci_config_filter,
1606         .config_intf            = rt2400pci_config_intf,
1607         .config_erp             = rt2400pci_config_erp,
1608         .config_ant             = rt2400pci_config_ant,
1609         .config                 = rt2400pci_config,
1610 };
1611
1612 static const struct data_queue_desc rt2400pci_queue_rx = {
1613         .entry_num              = RX_ENTRIES,
1614         .data_size              = DATA_FRAME_SIZE,
1615         .desc_size              = RXD_DESC_SIZE,
1616         .priv_size              = sizeof(struct queue_entry_priv_pci),
1617 };
1618
1619 static const struct data_queue_desc rt2400pci_queue_tx = {
1620         .entry_num              = TX_ENTRIES,
1621         .data_size              = DATA_FRAME_SIZE,
1622         .desc_size              = TXD_DESC_SIZE,
1623         .priv_size              = sizeof(struct queue_entry_priv_pci),
1624 };
1625
1626 static const struct data_queue_desc rt2400pci_queue_bcn = {
1627         .entry_num              = BEACON_ENTRIES,
1628         .data_size              = MGMT_FRAME_SIZE,
1629         .desc_size              = TXD_DESC_SIZE,
1630         .priv_size              = sizeof(struct queue_entry_priv_pci),
1631 };
1632
1633 static const struct data_queue_desc rt2400pci_queue_atim = {
1634         .entry_num              = ATIM_ENTRIES,
1635         .data_size              = DATA_FRAME_SIZE,
1636         .desc_size              = TXD_DESC_SIZE,
1637         .priv_size              = sizeof(struct queue_entry_priv_pci),
1638 };
1639
1640 static const struct rt2x00_ops rt2400pci_ops = {
1641         .name           = KBUILD_MODNAME,
1642         .max_sta_intf   = 1,
1643         .max_ap_intf    = 1,
1644         .eeprom_size    = EEPROM_SIZE,
1645         .rf_size        = RF_SIZE,
1646         .tx_queues      = NUM_TX_QUEUES,
1647         .rx             = &rt2400pci_queue_rx,
1648         .tx             = &rt2400pci_queue_tx,
1649         .bcn            = &rt2400pci_queue_bcn,
1650         .atim           = &rt2400pci_queue_atim,
1651         .lib            = &rt2400pci_rt2x00_ops,
1652         .hw             = &rt2400pci_mac80211_ops,
1653 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1654         .debugfs        = &rt2400pci_rt2x00debug,
1655 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1656 };
1657
1658 /*
1659  * RT2400pci module information.
1660  */
1661 static struct pci_device_id rt2400pci_device_table[] = {
1662         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1663         { 0, }
1664 };
1665
1666 MODULE_AUTHOR(DRV_PROJECT);
1667 MODULE_VERSION(DRV_VERSION);
1668 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1669 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1670 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1671 MODULE_LICENSE("GPL");
1672
1673 static struct pci_driver rt2400pci_driver = {
1674         .name           = KBUILD_MODNAME,
1675         .id_table       = rt2400pci_device_table,
1676         .probe          = rt2x00pci_probe,
1677         .remove         = __devexit_p(rt2x00pci_remove),
1678         .suspend        = rt2x00pci_suspend,
1679         .resume         = rt2x00pci_resume,
1680 };
1681
1682 static int __init rt2400pci_init(void)
1683 {
1684         return pci_register_driver(&rt2400pci_driver);
1685 }
1686
1687 static void __exit rt2400pci_exit(void)
1688 {
1689         pci_unregister_driver(&rt2400pci_driver);
1690 }
1691
1692 module_init(rt2400pci_init);
1693 module_exit(rt2400pci_exit);