rt2x00: Restrict interface between rt2x00link and drivers
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2400pci
23         Abstract: rt2400pci device specific routines.
24         Supported chipsets: RT2460.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
38
39 /*
40  * Register access.
41  * All access to the CSR registers will go through the methods
42  * rt2x00pci_register_read and rt2x00pci_register_write.
43  * BBP and RF register require indirect register access,
44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
45  * These indirect registers work with busy bits,
46  * and we will try maximal REGISTER_BUSY_COUNT times to access
47  * the register while taking a REGISTER_BUSY_DELAY us delay
48  * between each attampt. When the busy bit is still set at that time,
49  * the access attempt is considered to have failed,
50  * and we will print an error.
51  */
52 #define WAIT_FOR_BBP(__dev, __reg) \
53         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 #define WAIT_FOR_RF(__dev, __reg) \
55         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
58                                 const unsigned int word, const u8 value)
59 {
60         u32 reg;
61
62         mutex_lock(&rt2x00dev->csr_mutex);
63
64         /*
65          * Wait until the BBP becomes available, afterwards we
66          * can safely write the new data into the register.
67          */
68         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69                 reg = 0;
70                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76         }
77
78         mutex_unlock(&rt2x00dev->csr_mutex);
79 }
80
81 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
82                                const unsigned int word, u8 *value)
83 {
84         u32 reg;
85
86         mutex_lock(&rt2x00dev->csr_mutex);
87
88         /*
89          * Wait until the BBP becomes available, afterwards we
90          * can safely write the read request into the register.
91          * After the data has been written, we wait until hardware
92          * returns the correct value, if at any time the register
93          * doesn't become available in time, reg will be 0xffffffff
94          * which means we return 0xff to the caller.
95          */
96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97                 reg = 0;
98                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
101
102                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
103
104                 WAIT_FOR_BBP(rt2x00dev, &reg);
105         }
106
107         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
113                                const unsigned int word, const u32 value)
114 {
115         u32 reg;
116
117         if (!word)
118                 return;
119
120         mutex_lock(&rt2x00dev->csr_mutex);
121
122         /*
123          * Wait until the RF becomes available, afterwards we
124          * can safely write the new data into the register.
125          */
126         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
127                 reg = 0;
128                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
129                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
130                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
131                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
132
133                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
134                 rt2x00_rf_write(rt2x00dev, word, value);
135         }
136
137         mutex_unlock(&rt2x00dev->csr_mutex);
138 }
139
140 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
141 {
142         struct rt2x00_dev *rt2x00dev = eeprom->data;
143         u32 reg;
144
145         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
146
147         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
148         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
149         eeprom->reg_data_clock =
150             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
151         eeprom->reg_chip_select =
152             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
153 }
154
155 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
156 {
157         struct rt2x00_dev *rt2x00dev = eeprom->data;
158         u32 reg = 0;
159
160         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
161         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
162         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
163                            !!eeprom->reg_data_clock);
164         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
165                            !!eeprom->reg_chip_select);
166
167         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
168 }
169
170 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
171 static const struct rt2x00debug rt2400pci_rt2x00debug = {
172         .owner  = THIS_MODULE,
173         .csr    = {
174                 .read           = rt2x00pci_register_read,
175                 .write          = rt2x00pci_register_write,
176                 .flags          = RT2X00DEBUGFS_OFFSET,
177                 .word_base      = CSR_REG_BASE,
178                 .word_size      = sizeof(u32),
179                 .word_count     = CSR_REG_SIZE / sizeof(u32),
180         },
181         .eeprom = {
182                 .read           = rt2x00_eeprom_read,
183                 .write          = rt2x00_eeprom_write,
184                 .word_base      = EEPROM_BASE,
185                 .word_size      = sizeof(u16),
186                 .word_count     = EEPROM_SIZE / sizeof(u16),
187         },
188         .bbp    = {
189                 .read           = rt2400pci_bbp_read,
190                 .write          = rt2400pci_bbp_write,
191                 .word_base      = BBP_BASE,
192                 .word_size      = sizeof(u8),
193                 .word_count     = BBP_SIZE / sizeof(u8),
194         },
195         .rf     = {
196                 .read           = rt2x00_rf_read,
197                 .write          = rt2400pci_rf_write,
198                 .word_base      = RF_BASE,
199                 .word_size      = sizeof(u32),
200                 .word_count     = RF_SIZE / sizeof(u32),
201         },
202 };
203 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
204
205 #ifdef CONFIG_RT2X00_LIB_RFKILL
206 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
207 {
208         u32 reg;
209
210         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
211         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
212 }
213 #else
214 #define rt2400pci_rfkill_poll   NULL
215 #endif /* CONFIG_RT2X00_LIB_RFKILL */
216
217 #ifdef CONFIG_RT2X00_LIB_LEDS
218 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
219                                      enum led_brightness brightness)
220 {
221         struct rt2x00_led *led =
222             container_of(led_cdev, struct rt2x00_led, led_dev);
223         unsigned int enabled = brightness != LED_OFF;
224         u32 reg;
225
226         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
227
228         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
229                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
230         else if (led->type == LED_TYPE_ACTIVITY)
231                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
232
233         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
234 }
235
236 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
237                                unsigned long *delay_on,
238                                unsigned long *delay_off)
239 {
240         struct rt2x00_led *led =
241             container_of(led_cdev, struct rt2x00_led, led_dev);
242         u32 reg;
243
244         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
245         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
246         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
247         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
248
249         return 0;
250 }
251
252 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
253                                struct rt2x00_led *led,
254                                enum led_type type)
255 {
256         led->rt2x00dev = rt2x00dev;
257         led->type = type;
258         led->led_dev.brightness_set = rt2400pci_brightness_set;
259         led->led_dev.blink_set = rt2400pci_blink_set;
260         led->flags = LED_INITIALIZED;
261 }
262 #endif /* CONFIG_RT2X00_LIB_LEDS */
263
264 /*
265  * Configuration handlers.
266  */
267 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
268                                     const unsigned int filter_flags)
269 {
270         u32 reg;
271
272         /*
273          * Start configuration steps.
274          * Note that the version error will always be dropped
275          * since there is no filter for it at this time.
276          */
277         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
278         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
279                            !(filter_flags & FIF_FCSFAIL));
280         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
281                            !(filter_flags & FIF_PLCPFAIL));
282         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
283                            !(filter_flags & FIF_CONTROL));
284         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
285                            !(filter_flags & FIF_PROMISC_IN_BSS));
286         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
287                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
288                            !rt2x00dev->intf_ap_count);
289         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
290         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
291 }
292
293 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
294                                   struct rt2x00_intf *intf,
295                                   struct rt2x00intf_conf *conf,
296                                   const unsigned int flags)
297 {
298         unsigned int bcn_preload;
299         u32 reg;
300
301         if (flags & CONFIG_UPDATE_TYPE) {
302                 /*
303                  * Enable beacon config
304                  */
305                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
306                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
307                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
308                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
309
310                 /*
311                  * Enable synchronisation.
312                  */
313                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
314                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
315                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
316                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
317                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
318         }
319
320         if (flags & CONFIG_UPDATE_MAC)
321                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
322                                               conf->mac, sizeof(conf->mac));
323
324         if (flags & CONFIG_UPDATE_BSSID)
325                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
326                                               conf->bssid, sizeof(conf->bssid));
327 }
328
329 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
330                                  struct rt2x00lib_erp *erp)
331 {
332         int preamble_mask;
333         u32 reg;
334
335         /*
336          * When short preamble is enabled, we should set bit 0x08
337          */
338         preamble_mask = erp->short_preamble << 3;
339
340         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
341         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
342                            erp->ack_timeout);
343         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
344                            erp->ack_consume_time);
345         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
346
347         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
348         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
349         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
350         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
351         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
352
353         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
354         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
355         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
356         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
357         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
358
359         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
360         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
361         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
362         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
363         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
364
365         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
366         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
367         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
368         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
369         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
370
371         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
372
373         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
374         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
375         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
376
377         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
378         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
379         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
380         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
381
382         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
383         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
384         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
385         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
386 }
387
388 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
389                                  struct antenna_setup *ant)
390 {
391         u8 r1;
392         u8 r4;
393
394         /*
395          * We should never come here because rt2x00lib is supposed
396          * to catch this and send us the correct antenna explicitely.
397          */
398         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
399                ant->tx == ANTENNA_SW_DIVERSITY);
400
401         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
402         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
403
404         /*
405          * Configure the TX antenna.
406          */
407         switch (ant->tx) {
408         case ANTENNA_HW_DIVERSITY:
409                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
410                 break;
411         case ANTENNA_A:
412                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
413                 break;
414         case ANTENNA_B:
415         default:
416                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
417                 break;
418         }
419
420         /*
421          * Configure the RX antenna.
422          */
423         switch (ant->rx) {
424         case ANTENNA_HW_DIVERSITY:
425                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
426                 break;
427         case ANTENNA_A:
428                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
429                 break;
430         case ANTENNA_B:
431         default:
432                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
433                 break;
434         }
435
436         rt2400pci_bbp_write(rt2x00dev, 4, r4);
437         rt2400pci_bbp_write(rt2x00dev, 1, r1);
438 }
439
440 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
441                                      struct rf_channel *rf)
442 {
443         /*
444          * Switch on tuning bits.
445          */
446         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
447         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
448
449         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
450         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
451         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
452
453         /*
454          * RF2420 chipset don't need any additional actions.
455          */
456         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
457                 return;
458
459         /*
460          * For the RT2421 chipsets we need to write an invalid
461          * reference clock rate to activate auto_tune.
462          * After that we set the value back to the correct channel.
463          */
464         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
465         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
466         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
467
468         msleep(1);
469
470         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
471         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
472         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
473
474         msleep(1);
475
476         /*
477          * Switch off tuning bits.
478          */
479         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
480         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
481
482         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
483         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
484
485         /*
486          * Clear false CRC during channel switch.
487          */
488         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
489 }
490
491 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
492 {
493         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
494 }
495
496 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
497                                          struct rt2x00lib_conf *libconf)
498 {
499         u32 reg;
500
501         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
502         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
503                            libconf->conf->long_frame_max_tx_count);
504         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
505                            libconf->conf->short_frame_max_tx_count);
506         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
507 }
508
509 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
510                                       struct rt2x00lib_conf *libconf)
511 {
512         u32 reg;
513
514         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
515         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
516         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
517         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
518
519         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
520         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
521                            libconf->conf->beacon_int * 16);
522         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
523                            libconf->conf->beacon_int * 16);
524         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
525 }
526
527 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
528                                 struct rt2x00lib_conf *libconf)
529 {
530         enum dev_state state =
531             (libconf->conf->flags & IEEE80211_CONF_PS) ?
532                 STATE_SLEEP : STATE_AWAKE;
533         u32 reg;
534
535         if (state == STATE_SLEEP) {
536                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
537                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
538                                    (libconf->conf->beacon_int - 20) * 16);
539                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
540                                    libconf->conf->listen_interval - 1);
541
542                 /* We must first disable autowake before it can be enabled */
543                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
544                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
545
546                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
547                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
548         }
549
550         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
551 }
552
553 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
554                              struct rt2x00lib_conf *libconf,
555                              const unsigned int flags)
556 {
557         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
558                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
559         if (flags & IEEE80211_CONF_CHANGE_POWER)
560                 rt2400pci_config_txpower(rt2x00dev,
561                                          libconf->conf->power_level);
562         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
563                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
564         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
565                 rt2400pci_config_duration(rt2x00dev, libconf);
566         if (flags & IEEE80211_CONF_CHANGE_PS)
567                 rt2400pci_config_ps(rt2x00dev, libconf);
568 }
569
570 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
571                                 const int cw_min, const int cw_max)
572 {
573         u32 reg;
574
575         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
576         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
577         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
578         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
579 }
580
581 /*
582  * Link tuning
583  */
584 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
585                                  struct link_qual *qual)
586 {
587         u32 reg;
588         u8 bbp;
589
590         /*
591          * Update FCS error count from register.
592          */
593         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
594         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
595
596         /*
597          * Update False CCA count from register.
598          */
599         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
600         qual->false_cca = bbp;
601 }
602
603 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
604                                      struct link_qual *qual, u8 vgc_level)
605 {
606         rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
607         qual->vgc_level = vgc_level;
608         qual->vgc_level_reg = vgc_level;
609 }
610
611 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
612                                   struct link_qual *qual)
613 {
614         rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
615 }
616
617 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
618                                  struct link_qual *qual, const u32 count)
619 {
620         /*
621          * The link tuner should not run longer then 60 seconds,
622          * and should run once every 2 seconds.
623          */
624         if (count > 60 || !(count & 1))
625                 return;
626
627         /*
628          * Base r13 link tuning on the false cca count.
629          */
630         if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
631                 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
632         else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
633                 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
634 }
635
636 /*
637  * Initialization functions.
638  */
639 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
640 {
641         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
642         u32 word;
643
644         if (entry->queue->qid == QID_RX) {
645                 rt2x00_desc_read(entry_priv->desc, 0, &word);
646
647                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
648         } else {
649                 rt2x00_desc_read(entry_priv->desc, 0, &word);
650
651                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
652                         rt2x00_get_field32(word, TXD_W0_VALID));
653         }
654 }
655
656 static void rt2400pci_clear_entry(struct queue_entry *entry)
657 {
658         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
659         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
660         u32 word;
661
662         if (entry->queue->qid == QID_RX) {
663                 rt2x00_desc_read(entry_priv->desc, 2, &word);
664                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
665                 rt2x00_desc_write(entry_priv->desc, 2, word);
666
667                 rt2x00_desc_read(entry_priv->desc, 1, &word);
668                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
669                 rt2x00_desc_write(entry_priv->desc, 1, word);
670
671                 rt2x00_desc_read(entry_priv->desc, 0, &word);
672                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
673                 rt2x00_desc_write(entry_priv->desc, 0, word);
674         } else {
675                 rt2x00_desc_read(entry_priv->desc, 0, &word);
676                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
677                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
678                 rt2x00_desc_write(entry_priv->desc, 0, word);
679         }
680 }
681
682 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
683 {
684         struct queue_entry_priv_pci *entry_priv;
685         u32 reg;
686
687         /*
688          * Initialize registers.
689          */
690         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
691         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
692         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
693         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
694         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
695         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
696
697         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
698         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
699         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
700                            entry_priv->desc_dma);
701         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
702
703         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
704         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
705         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
706                            entry_priv->desc_dma);
707         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
708
709         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
710         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
711         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
712                            entry_priv->desc_dma);
713         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
714
715         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
716         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
717         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
718                            entry_priv->desc_dma);
719         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
720
721         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
722         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
723         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
724         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
725
726         entry_priv = rt2x00dev->rx->entries[0].priv_data;
727         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
728         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
729                            entry_priv->desc_dma);
730         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
731
732         return 0;
733 }
734
735 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
736 {
737         u32 reg;
738
739         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
740         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
741         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
742         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
743
744         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
745         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
746         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
747         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
748         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
749
750         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
751         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
752                            (rt2x00dev->rx->data_size / 128));
753         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
754
755         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
756         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
757         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
758         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
759         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
760         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
761         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
762         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
763         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
764         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
765
766         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
767
768         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
769         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
770         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
771         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
772         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
773         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
774
775         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
776         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
777         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
778         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
779         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
780         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
781         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
782         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
783
784         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
785
786         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
787                 return -EBUSY;
788
789         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
790         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
791
792         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
793         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
794         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
795
796         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
797         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
798         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
799         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
800         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
801         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
802
803         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
804         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
805         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
806         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
807         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
808
809         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
810         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
811         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
812         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
813
814         /*
815          * We must clear the FCS and FIFO error count.
816          * These registers are cleared on read,
817          * so we may pass a useless variable to store the value.
818          */
819         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
820         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
821
822         return 0;
823 }
824
825 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
826 {
827         unsigned int i;
828         u8 value;
829
830         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
831                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
832                 if ((value != 0xff) && (value != 0x00))
833                         return 0;
834                 udelay(REGISTER_BUSY_DELAY);
835         }
836
837         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
838         return -EACCES;
839 }
840
841 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
842 {
843         unsigned int i;
844         u16 eeprom;
845         u8 reg_id;
846         u8 value;
847
848         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
849                 return -EACCES;
850
851         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
852         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
853         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
854         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
855         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
856         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
857         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
858         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
859         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
860         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
861         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
862         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
863         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
864         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
865
866         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
867                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
868
869                 if (eeprom != 0xffff && eeprom != 0x0000) {
870                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
871                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
872                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
873                 }
874         }
875
876         return 0;
877 }
878
879 /*
880  * Device state switch handlers.
881  */
882 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
883                                 enum dev_state state)
884 {
885         u32 reg;
886
887         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
888         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
889                            (state == STATE_RADIO_RX_OFF) ||
890                            (state == STATE_RADIO_RX_OFF_LINK));
891         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
892 }
893
894 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
895                                  enum dev_state state)
896 {
897         int mask = (state == STATE_RADIO_IRQ_OFF);
898         u32 reg;
899
900         /*
901          * When interrupts are being enabled, the interrupt registers
902          * should clear the register to assure a clean state.
903          */
904         if (state == STATE_RADIO_IRQ_ON) {
905                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
906                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
907         }
908
909         /*
910          * Only toggle the interrupts bits we are going to use.
911          * Non-checked interrupt bits are disabled by default.
912          */
913         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
914         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
915         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
916         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
917         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
918         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
919         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
920 }
921
922 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
923 {
924         /*
925          * Initialize all registers.
926          */
927         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
928                      rt2400pci_init_registers(rt2x00dev) ||
929                      rt2400pci_init_bbp(rt2x00dev)))
930                 return -EIO;
931
932         return 0;
933 }
934
935 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
936 {
937         u32 reg;
938
939         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
940
941         /*
942          * Disable synchronisation.
943          */
944         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
945
946         /*
947          * Cancel RX and TX.
948          */
949         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
950         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
951         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
952 }
953
954 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
955                                enum dev_state state)
956 {
957         u32 reg;
958         unsigned int i;
959         char put_to_sleep;
960         char bbp_state;
961         char rf_state;
962
963         put_to_sleep = (state != STATE_AWAKE);
964
965         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
966         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
967         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
968         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
969         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
970         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
971
972         /*
973          * Device is not guaranteed to be in the requested state yet.
974          * We must wait until the register indicates that the
975          * device has entered the correct state.
976          */
977         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
978                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
979                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
980                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
981                 if (bbp_state == state && rf_state == state)
982                         return 0;
983                 msleep(10);
984         }
985
986         return -EBUSY;
987 }
988
989 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
990                                       enum dev_state state)
991 {
992         int retval = 0;
993
994         switch (state) {
995         case STATE_RADIO_ON:
996                 retval = rt2400pci_enable_radio(rt2x00dev);
997                 break;
998         case STATE_RADIO_OFF:
999                 rt2400pci_disable_radio(rt2x00dev);
1000                 break;
1001         case STATE_RADIO_RX_ON:
1002         case STATE_RADIO_RX_ON_LINK:
1003         case STATE_RADIO_RX_OFF:
1004         case STATE_RADIO_RX_OFF_LINK:
1005                 rt2400pci_toggle_rx(rt2x00dev, state);
1006                 break;
1007         case STATE_RADIO_IRQ_ON:
1008         case STATE_RADIO_IRQ_OFF:
1009                 rt2400pci_toggle_irq(rt2x00dev, state);
1010                 break;
1011         case STATE_DEEP_SLEEP:
1012         case STATE_SLEEP:
1013         case STATE_STANDBY:
1014         case STATE_AWAKE:
1015                 retval = rt2400pci_set_state(rt2x00dev, state);
1016                 break;
1017         default:
1018                 retval = -ENOTSUPP;
1019                 break;
1020         }
1021
1022         if (unlikely(retval))
1023                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1024                       state, retval);
1025
1026         return retval;
1027 }
1028
1029 /*
1030  * TX descriptor initialization
1031  */
1032 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1033                                     struct sk_buff *skb,
1034                                     struct txentry_desc *txdesc)
1035 {
1036         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1037         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1038         __le32 *txd = skbdesc->desc;
1039         u32 word;
1040
1041         /*
1042          * Start writing the descriptor words.
1043          */
1044         rt2x00_desc_read(entry_priv->desc, 1, &word);
1045         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1046         rt2x00_desc_write(entry_priv->desc, 1, word);
1047
1048         rt2x00_desc_read(txd, 2, &word);
1049         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1050         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1051         rt2x00_desc_write(txd, 2, word);
1052
1053         rt2x00_desc_read(txd, 3, &word);
1054         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1055         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1056         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1057         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1058         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1059         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1060         rt2x00_desc_write(txd, 3, word);
1061
1062         rt2x00_desc_read(txd, 4, &word);
1063         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1064         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1065         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1066         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1067         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1068         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1069         rt2x00_desc_write(txd, 4, word);
1070
1071         rt2x00_desc_read(txd, 0, &word);
1072         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1073         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1074         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1075                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1076         rt2x00_set_field32(&word, TXD_W0_ACK,
1077                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1078         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1079                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1080         rt2x00_set_field32(&word, TXD_W0_RTS,
1081                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1082         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1083         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1084                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1085         rt2x00_desc_write(txd, 0, word);
1086 }
1087
1088 /*
1089  * TX data initialization
1090  */
1091 static void rt2400pci_write_beacon(struct queue_entry *entry)
1092 {
1093         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1094         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1095         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1096         u32 word;
1097         u32 reg;
1098
1099         /*
1100          * Disable beaconing while we are reloading the beacon data,
1101          * otherwise we might be sending out invalid data.
1102          */
1103         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1104         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1105         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1106         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1107         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1108
1109         /*
1110          * Replace rt2x00lib allocated descriptor with the
1111          * pointer to the _real_ hardware descriptor.
1112          * After that, map the beacon to DMA and update the
1113          * descriptor.
1114          */
1115         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1116         skbdesc->desc = entry_priv->desc;
1117
1118         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1119
1120         rt2x00_desc_read(entry_priv->desc, 1, &word);
1121         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1122         rt2x00_desc_write(entry_priv->desc, 1, word);
1123 }
1124
1125 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1126                                     const enum data_queue_qid queue)
1127 {
1128         u32 reg;
1129
1130         if (queue == QID_BEACON) {
1131                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1132                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1133                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1134                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1135                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1136                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1137                 }
1138                 return;
1139         }
1140
1141         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1142         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1143         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1144         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1145         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1146 }
1147
1148 /*
1149  * RX control handlers
1150  */
1151 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1152                                   struct rxdone_entry_desc *rxdesc)
1153 {
1154         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1155         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1156         u32 word0;
1157         u32 word2;
1158         u32 word3;
1159         u32 word4;
1160         u64 tsf;
1161         u32 rx_low;
1162         u32 rx_high;
1163
1164         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1165         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1166         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1167         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1168
1169         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1170                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1171         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1172                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1173
1174         /*
1175          * We only get the lower 32bits from the timestamp,
1176          * to get the full 64bits we must complement it with
1177          * the timestamp from get_tsf().
1178          * Note that when a wraparound of the lower 32bits
1179          * has occurred between the frame arrival and the get_tsf()
1180          * call, we must decrease the higher 32bits with 1 to get
1181          * to correct value.
1182          */
1183         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1184         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1185         rx_high = upper_32_bits(tsf);
1186
1187         if ((u32)tsf <= rx_low)
1188                 rx_high--;
1189
1190         /*
1191          * Obtain the status about this packet.
1192          * The signal is the PLCP value, and needs to be stripped
1193          * of the preamble bit (0x08).
1194          */
1195         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1196         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1197         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1198             entry->queue->rt2x00dev->rssi_offset;
1199         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1200
1201         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1202         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1203                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1204 }
1205
1206 /*
1207  * Interrupt functions.
1208  */
1209 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1210                              const enum data_queue_qid queue_idx)
1211 {
1212         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1213         struct queue_entry_priv_pci *entry_priv;
1214         struct queue_entry *entry;
1215         struct txdone_entry_desc txdesc;
1216         u32 word;
1217
1218         while (!rt2x00queue_empty(queue)) {
1219                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1220                 entry_priv = entry->priv_data;
1221                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1222
1223                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1224                     !rt2x00_get_field32(word, TXD_W0_VALID))
1225                         break;
1226
1227                 /*
1228                  * Obtain the status about this packet.
1229                  */
1230                 txdesc.flags = 0;
1231                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1232                 case 0: /* Success */
1233                 case 1: /* Success with retry */
1234                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1235                         break;
1236                 case 2: /* Failure, excessive retries */
1237                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1238                         /* Don't break, this is a failed frame! */
1239                 default: /* Failure */
1240                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1241                 }
1242                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1243
1244                 rt2x00lib_txdone(entry, &txdesc);
1245         }
1246 }
1247
1248 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1249 {
1250         struct rt2x00_dev *rt2x00dev = dev_instance;
1251         u32 reg;
1252
1253         /*
1254          * Get the interrupt sources & saved to local variable.
1255          * Write register value back to clear pending interrupts.
1256          */
1257         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1258         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1259
1260         if (!reg)
1261                 return IRQ_NONE;
1262
1263         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1264                 return IRQ_HANDLED;
1265
1266         /*
1267          * Handle interrupts, walk through all bits
1268          * and run the tasks, the bits are checked in order of
1269          * priority.
1270          */
1271
1272         /*
1273          * 1 - Beacon timer expired interrupt.
1274          */
1275         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1276                 rt2x00lib_beacondone(rt2x00dev);
1277
1278         /*
1279          * 2 - Rx ring done interrupt.
1280          */
1281         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1282                 rt2x00pci_rxdone(rt2x00dev);
1283
1284         /*
1285          * 3 - Atim ring transmit done interrupt.
1286          */
1287         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1288                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1289
1290         /*
1291          * 4 - Priority ring transmit done interrupt.
1292          */
1293         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1294                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1295
1296         /*
1297          * 5 - Tx ring transmit done interrupt.
1298          */
1299         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1300                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1301
1302         return IRQ_HANDLED;
1303 }
1304
1305 /*
1306  * Device probe functions.
1307  */
1308 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1309 {
1310         struct eeprom_93cx6 eeprom;
1311         u32 reg;
1312         u16 word;
1313         u8 *mac;
1314
1315         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1316
1317         eeprom.data = rt2x00dev;
1318         eeprom.register_read = rt2400pci_eepromregister_read;
1319         eeprom.register_write = rt2400pci_eepromregister_write;
1320         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1321             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1322         eeprom.reg_data_in = 0;
1323         eeprom.reg_data_out = 0;
1324         eeprom.reg_data_clock = 0;
1325         eeprom.reg_chip_select = 0;
1326
1327         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1328                                EEPROM_SIZE / sizeof(u16));
1329
1330         /*
1331          * Start validation of the data that has been read.
1332          */
1333         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1334         if (!is_valid_ether_addr(mac)) {
1335                 random_ether_addr(mac);
1336                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1337         }
1338
1339         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1340         if (word == 0xffff) {
1341                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1342                 return -EINVAL;
1343         }
1344
1345         return 0;
1346 }
1347
1348 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1349 {
1350         u32 reg;
1351         u16 value;
1352         u16 eeprom;
1353
1354         /*
1355          * Read EEPROM word for configuration.
1356          */
1357         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1358
1359         /*
1360          * Identify RF chipset.
1361          */
1362         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1363         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1364         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1365
1366         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1367             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1368                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1369                 return -ENODEV;
1370         }
1371
1372         /*
1373          * Identify default antenna configuration.
1374          */
1375         rt2x00dev->default_ant.tx =
1376             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1377         rt2x00dev->default_ant.rx =
1378             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1379
1380         /*
1381          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1382          * I am not 100% sure about this, but the legacy drivers do not
1383          * indicate antenna swapping in software is required when
1384          * diversity is enabled.
1385          */
1386         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1387                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1388         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1389                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1390
1391         /*
1392          * Store led mode, for correct led behaviour.
1393          */
1394 #ifdef CONFIG_RT2X00_LIB_LEDS
1395         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1396
1397         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1398         if (value == LED_MODE_TXRX_ACTIVITY)
1399                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1400                                    LED_TYPE_ACTIVITY);
1401 #endif /* CONFIG_RT2X00_LIB_LEDS */
1402
1403         /*
1404          * Detect if this device has an hardware controlled radio.
1405          */
1406 #ifdef CONFIG_RT2X00_LIB_RFKILL
1407         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1408                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1409 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1410
1411         /*
1412          * Check if the BBP tuning should be enabled.
1413          */
1414         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1415                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1416
1417         return 0;
1418 }
1419
1420 /*
1421  * RF value list for RF2420 & RF2421
1422  * Supports: 2.4 GHz
1423  */
1424 static const struct rf_channel rf_vals_b[] = {
1425         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1426         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1427         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1428         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1429         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1430         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1431         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1432         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1433         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1434         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1435         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1436         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1437         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1438         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1439 };
1440
1441 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1442 {
1443         struct hw_mode_spec *spec = &rt2x00dev->spec;
1444         struct channel_info *info;
1445         char *tx_power;
1446         unsigned int i;
1447
1448         /*
1449          * Initialize all hw fields.
1450          */
1451         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1452                                IEEE80211_HW_SIGNAL_DBM;
1453         rt2x00dev->hw->extra_tx_headroom = 0;
1454
1455         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1456         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1457                                 rt2x00_eeprom_addr(rt2x00dev,
1458                                                    EEPROM_MAC_ADDR_0));
1459
1460         /*
1461          * Initialize hw_mode information.
1462          */
1463         spec->supported_bands = SUPPORT_BAND_2GHZ;
1464         spec->supported_rates = SUPPORT_RATE_CCK;
1465
1466         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1467         spec->channels = rf_vals_b;
1468
1469         /*
1470          * Create channel information array
1471          */
1472         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1473         if (!info)
1474                 return -ENOMEM;
1475
1476         spec->channels_info = info;
1477
1478         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1479         for (i = 0; i < 14; i++)
1480                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1481
1482         return 0;
1483 }
1484
1485 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1486 {
1487         int retval;
1488
1489         /*
1490          * Allocate eeprom data.
1491          */
1492         retval = rt2400pci_validate_eeprom(rt2x00dev);
1493         if (retval)
1494                 return retval;
1495
1496         retval = rt2400pci_init_eeprom(rt2x00dev);
1497         if (retval)
1498                 return retval;
1499
1500         /*
1501          * Initialize hw specifications.
1502          */
1503         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1504         if (retval)
1505                 return retval;
1506
1507         /*
1508          * This device requires the atim queue and DMA-mapped skbs.
1509          */
1510         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1511         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1512
1513         /*
1514          * Set the rssi offset.
1515          */
1516         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1517
1518         return 0;
1519 }
1520
1521 /*
1522  * IEEE80211 stack callback functions.
1523  */
1524 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1525                              const struct ieee80211_tx_queue_params *params)
1526 {
1527         struct rt2x00_dev *rt2x00dev = hw->priv;
1528
1529         /*
1530          * We don't support variating cw_min and cw_max variables
1531          * per queue. So by default we only configure the TX queue,
1532          * and ignore all other configurations.
1533          */
1534         if (queue != 0)
1535                 return -EINVAL;
1536
1537         if (rt2x00mac_conf_tx(hw, queue, params))
1538                 return -EINVAL;
1539
1540         /*
1541          * Write configuration to register.
1542          */
1543         rt2400pci_config_cw(rt2x00dev,
1544                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1545
1546         return 0;
1547 }
1548
1549 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1550 {
1551         struct rt2x00_dev *rt2x00dev = hw->priv;
1552         u64 tsf;
1553         u32 reg;
1554
1555         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1556         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1557         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1558         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1559
1560         return tsf;
1561 }
1562
1563 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1564 {
1565         struct rt2x00_dev *rt2x00dev = hw->priv;
1566         u32 reg;
1567
1568         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1569         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1570 }
1571
1572 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1573         .tx                     = rt2x00mac_tx,
1574         .start                  = rt2x00mac_start,
1575         .stop                   = rt2x00mac_stop,
1576         .add_interface          = rt2x00mac_add_interface,
1577         .remove_interface       = rt2x00mac_remove_interface,
1578         .config                 = rt2x00mac_config,
1579         .config_interface       = rt2x00mac_config_interface,
1580         .configure_filter       = rt2x00mac_configure_filter,
1581         .get_stats              = rt2x00mac_get_stats,
1582         .bss_info_changed       = rt2x00mac_bss_info_changed,
1583         .conf_tx                = rt2400pci_conf_tx,
1584         .get_tx_stats           = rt2x00mac_get_tx_stats,
1585         .get_tsf                = rt2400pci_get_tsf,
1586         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1587 };
1588
1589 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1590         .irq_handler            = rt2400pci_interrupt,
1591         .probe_hw               = rt2400pci_probe_hw,
1592         .initialize             = rt2x00pci_initialize,
1593         .uninitialize           = rt2x00pci_uninitialize,
1594         .get_entry_state        = rt2400pci_get_entry_state,
1595         .clear_entry            = rt2400pci_clear_entry,
1596         .set_device_state       = rt2400pci_set_device_state,
1597         .rfkill_poll            = rt2400pci_rfkill_poll,
1598         .link_stats             = rt2400pci_link_stats,
1599         .reset_tuner            = rt2400pci_reset_tuner,
1600         .link_tuner             = rt2400pci_link_tuner,
1601         .write_tx_desc          = rt2400pci_write_tx_desc,
1602         .write_tx_data          = rt2x00pci_write_tx_data,
1603         .write_beacon           = rt2400pci_write_beacon,
1604         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1605         .fill_rxdone            = rt2400pci_fill_rxdone,
1606         .config_filter          = rt2400pci_config_filter,
1607         .config_intf            = rt2400pci_config_intf,
1608         .config_erp             = rt2400pci_config_erp,
1609         .config_ant             = rt2400pci_config_ant,
1610         .config                 = rt2400pci_config,
1611 };
1612
1613 static const struct data_queue_desc rt2400pci_queue_rx = {
1614         .entry_num              = RX_ENTRIES,
1615         .data_size              = DATA_FRAME_SIZE,
1616         .desc_size              = RXD_DESC_SIZE,
1617         .priv_size              = sizeof(struct queue_entry_priv_pci),
1618 };
1619
1620 static const struct data_queue_desc rt2400pci_queue_tx = {
1621         .entry_num              = TX_ENTRIES,
1622         .data_size              = DATA_FRAME_SIZE,
1623         .desc_size              = TXD_DESC_SIZE,
1624         .priv_size              = sizeof(struct queue_entry_priv_pci),
1625 };
1626
1627 static const struct data_queue_desc rt2400pci_queue_bcn = {
1628         .entry_num              = BEACON_ENTRIES,
1629         .data_size              = MGMT_FRAME_SIZE,
1630         .desc_size              = TXD_DESC_SIZE,
1631         .priv_size              = sizeof(struct queue_entry_priv_pci),
1632 };
1633
1634 static const struct data_queue_desc rt2400pci_queue_atim = {
1635         .entry_num              = ATIM_ENTRIES,
1636         .data_size              = DATA_FRAME_SIZE,
1637         .desc_size              = TXD_DESC_SIZE,
1638         .priv_size              = sizeof(struct queue_entry_priv_pci),
1639 };
1640
1641 static const struct rt2x00_ops rt2400pci_ops = {
1642         .name           = KBUILD_MODNAME,
1643         .max_sta_intf   = 1,
1644         .max_ap_intf    = 1,
1645         .eeprom_size    = EEPROM_SIZE,
1646         .rf_size        = RF_SIZE,
1647         .tx_queues      = NUM_TX_QUEUES,
1648         .rx             = &rt2400pci_queue_rx,
1649         .tx             = &rt2400pci_queue_tx,
1650         .bcn            = &rt2400pci_queue_bcn,
1651         .atim           = &rt2400pci_queue_atim,
1652         .lib            = &rt2400pci_rt2x00_ops,
1653         .hw             = &rt2400pci_mac80211_ops,
1654 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1655         .debugfs        = &rt2400pci_rt2x00debug,
1656 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1657 };
1658
1659 /*
1660  * RT2400pci module information.
1661  */
1662 static struct pci_device_id rt2400pci_device_table[] = {
1663         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1664         { 0, }
1665 };
1666
1667 MODULE_AUTHOR(DRV_PROJECT);
1668 MODULE_VERSION(DRV_VERSION);
1669 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1670 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1671 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1672 MODULE_LICENSE("GPL");
1673
1674 static struct pci_driver rt2400pci_driver = {
1675         .name           = KBUILD_MODNAME,
1676         .id_table       = rt2400pci_device_table,
1677         .probe          = rt2x00pci_probe,
1678         .remove         = __devexit_p(rt2x00pci_remove),
1679         .suspend        = rt2x00pci_suspend,
1680         .resume         = rt2x00pci_resume,
1681 };
1682
1683 static int __init rt2400pci_init(void)
1684 {
1685         return pci_register_driver(&rt2400pci_driver);
1686 }
1687
1688 static void __exit rt2400pci_exit(void)
1689 {
1690         pci_unregister_driver(&rt2400pci_driver);
1691 }
1692
1693 module_init(rt2400pci_init);
1694 module_exit(rt2400pci_exit);