Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2400pci
23         Abstract: rt2400pci device specific routines.
24         Supported chipsets: RT2460.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34 #include <linux/slab.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00pci.h"
38 #include "rt2400pci.h"
39
40 /*
41  * Register access.
42  * All access to the CSR registers will go through the methods
43  * rt2x00pci_register_read and rt2x00pci_register_write.
44  * BBP and RF register require indirect register access,
45  * and use the CSR registers BBPCSR and RFCSR to achieve this.
46  * These indirect registers work with busy bits,
47  * and we will try maximal REGISTER_BUSY_COUNT times to access
48  * the register while taking a REGISTER_BUSY_DELAY us delay
49  * between each attempt. When the busy bit is still set at that time,
50  * the access attempt is considered to have failed,
51  * and we will print an error.
52  */
53 #define WAIT_FOR_BBP(__dev, __reg) \
54         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
55 #define WAIT_FOR_RF(__dev, __reg) \
56         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
57
58 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
59                                 const unsigned int word, const u8 value)
60 {
61         u32 reg;
62
63         mutex_lock(&rt2x00dev->csr_mutex);
64
65         /*
66          * Wait until the BBP becomes available, afterwards we
67          * can safely write the new data into the register.
68          */
69         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
70                 reg = 0;
71                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
75
76                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
77         }
78
79         mutex_unlock(&rt2x00dev->csr_mutex);
80 }
81
82 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
83                                const unsigned int word, u8 *value)
84 {
85         u32 reg;
86
87         mutex_lock(&rt2x00dev->csr_mutex);
88
89         /*
90          * Wait until the BBP becomes available, afterwards we
91          * can safely write the read request into the register.
92          * After the data has been written, we wait until hardware
93          * returns the correct value, if at any time the register
94          * doesn't become available in time, reg will be 0xffffffff
95          * which means we return 0xff to the caller.
96          */
97         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
98                 reg = 0;
99                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
102
103                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
104
105                 WAIT_FOR_BBP(rt2x00dev, &reg);
106         }
107
108         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
109
110         mutex_unlock(&rt2x00dev->csr_mutex);
111 }
112
113 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
114                                const unsigned int word, const u32 value)
115 {
116         u32 reg;
117
118         mutex_lock(&rt2x00dev->csr_mutex);
119
120         /*
121          * Wait until the RF becomes available, afterwards we
122          * can safely write the new data into the register.
123          */
124         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
125                 reg = 0;
126                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
129                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
130
131                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
132                 rt2x00_rf_write(rt2x00dev, word, value);
133         }
134
135         mutex_unlock(&rt2x00dev->csr_mutex);
136 }
137
138 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
139 {
140         struct rt2x00_dev *rt2x00dev = eeprom->data;
141         u32 reg;
142
143         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
144
145         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
146         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
147         eeprom->reg_data_clock =
148             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
149         eeprom->reg_chip_select =
150             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
151 }
152
153 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
154 {
155         struct rt2x00_dev *rt2x00dev = eeprom->data;
156         u32 reg = 0;
157
158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
160         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
161                            !!eeprom->reg_data_clock);
162         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
163                            !!eeprom->reg_chip_select);
164
165         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
166 }
167
168 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
169 static const struct rt2x00debug rt2400pci_rt2x00debug = {
170         .owner  = THIS_MODULE,
171         .csr    = {
172                 .read           = rt2x00pci_register_read,
173                 .write          = rt2x00pci_register_write,
174                 .flags          = RT2X00DEBUGFS_OFFSET,
175                 .word_base      = CSR_REG_BASE,
176                 .word_size      = sizeof(u32),
177                 .word_count     = CSR_REG_SIZE / sizeof(u32),
178         },
179         .eeprom = {
180                 .read           = rt2x00_eeprom_read,
181                 .write          = rt2x00_eeprom_write,
182                 .word_base      = EEPROM_BASE,
183                 .word_size      = sizeof(u16),
184                 .word_count     = EEPROM_SIZE / sizeof(u16),
185         },
186         .bbp    = {
187                 .read           = rt2400pci_bbp_read,
188                 .write          = rt2400pci_bbp_write,
189                 .word_base      = BBP_BASE,
190                 .word_size      = sizeof(u8),
191                 .word_count     = BBP_SIZE / sizeof(u8),
192         },
193         .rf     = {
194                 .read           = rt2x00_rf_read,
195                 .write          = rt2400pci_rf_write,
196                 .word_base      = RF_BASE,
197                 .word_size      = sizeof(u32),
198                 .word_count     = RF_SIZE / sizeof(u32),
199         },
200 };
201 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
202
203 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
204 {
205         u32 reg;
206
207         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
208         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
209 }
210
211 #ifdef CONFIG_RT2X00_LIB_LEDS
212 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
213                                      enum led_brightness brightness)
214 {
215         struct rt2x00_led *led =
216             container_of(led_cdev, struct rt2x00_led, led_dev);
217         unsigned int enabled = brightness != LED_OFF;
218         u32 reg;
219
220         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
221
222         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
223                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
224         else if (led->type == LED_TYPE_ACTIVITY)
225                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
226
227         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
228 }
229
230 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
231                                unsigned long *delay_on,
232                                unsigned long *delay_off)
233 {
234         struct rt2x00_led *led =
235             container_of(led_cdev, struct rt2x00_led, led_dev);
236         u32 reg;
237
238         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
239         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
240         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
241         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
242
243         return 0;
244 }
245
246 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
247                                struct rt2x00_led *led,
248                                enum led_type type)
249 {
250         led->rt2x00dev = rt2x00dev;
251         led->type = type;
252         led->led_dev.brightness_set = rt2400pci_brightness_set;
253         led->led_dev.blink_set = rt2400pci_blink_set;
254         led->flags = LED_INITIALIZED;
255 }
256 #endif /* CONFIG_RT2X00_LIB_LEDS */
257
258 /*
259  * Configuration handlers.
260  */
261 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
262                                     const unsigned int filter_flags)
263 {
264         u32 reg;
265
266         /*
267          * Start configuration steps.
268          * Note that the version error will always be dropped
269          * since there is no filter for it at this time.
270          */
271         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
272         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
273                            !(filter_flags & FIF_FCSFAIL));
274         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
275                            !(filter_flags & FIF_PLCPFAIL));
276         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
277                            !(filter_flags & FIF_CONTROL));
278         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
279                            !(filter_flags & FIF_PROMISC_IN_BSS));
280         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
281                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
282                            !rt2x00dev->intf_ap_count);
283         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
284         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
285 }
286
287 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
288                                   struct rt2x00_intf *intf,
289                                   struct rt2x00intf_conf *conf,
290                                   const unsigned int flags)
291 {
292         unsigned int bcn_preload;
293         u32 reg;
294
295         if (flags & CONFIG_UPDATE_TYPE) {
296                 /*
297                  * Enable beacon config
298                  */
299                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
300                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
301                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
302                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
303
304                 /*
305                  * Enable synchronisation.
306                  */
307                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
308                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
309                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
310         }
311
312         if (flags & CONFIG_UPDATE_MAC)
313                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
314                                               conf->mac, sizeof(conf->mac));
315
316         if (flags & CONFIG_UPDATE_BSSID)
317                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
318                                               conf->bssid, sizeof(conf->bssid));
319 }
320
321 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
322                                  struct rt2x00lib_erp *erp,
323                                  u32 changed)
324 {
325         int preamble_mask;
326         u32 reg;
327
328         /*
329          * When short preamble is enabled, we should set bit 0x08
330          */
331         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
332                 preamble_mask = erp->short_preamble << 3;
333
334                 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
335                 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
336                 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
337                 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
338                 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
339                 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
340
341                 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
342                 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
343                 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
344                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
345                                    GET_DURATION(ACK_SIZE, 10));
346                 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
347
348                 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
349                 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
350                 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
351                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
352                                    GET_DURATION(ACK_SIZE, 20));
353                 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
354
355                 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
356                 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
357                 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
358                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
359                                    GET_DURATION(ACK_SIZE, 55));
360                 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
361
362                 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
363                 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
364                 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
365                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
366                                    GET_DURATION(ACK_SIZE, 110));
367                 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
368         }
369
370         if (changed & BSS_CHANGED_BASIC_RATES)
371                 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
372
373         if (changed & BSS_CHANGED_ERP_SLOT) {
374                 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
375                 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
376                 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
377
378                 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
379                 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
380                 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
381                 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
382
383                 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
384                 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
385                 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
386                 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
387         }
388
389         if (changed & BSS_CHANGED_BEACON_INT) {
390                 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
391                 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
392                                    erp->beacon_int * 16);
393                 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
394                                    erp->beacon_int * 16);
395                 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
396         }
397 }
398
399 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
400                                  struct antenna_setup *ant)
401 {
402         u8 r1;
403         u8 r4;
404
405         /*
406          * We should never come here because rt2x00lib is supposed
407          * to catch this and send us the correct antenna explicitely.
408          */
409         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
410                ant->tx == ANTENNA_SW_DIVERSITY);
411
412         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
413         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
414
415         /*
416          * Configure the TX antenna.
417          */
418         switch (ant->tx) {
419         case ANTENNA_HW_DIVERSITY:
420                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
421                 break;
422         case ANTENNA_A:
423                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
424                 break;
425         case ANTENNA_B:
426         default:
427                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
428                 break;
429         }
430
431         /*
432          * Configure the RX antenna.
433          */
434         switch (ant->rx) {
435         case ANTENNA_HW_DIVERSITY:
436                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
437                 break;
438         case ANTENNA_A:
439                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
440                 break;
441         case ANTENNA_B:
442         default:
443                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
444                 break;
445         }
446
447         rt2400pci_bbp_write(rt2x00dev, 4, r4);
448         rt2400pci_bbp_write(rt2x00dev, 1, r1);
449 }
450
451 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
452                                      struct rf_channel *rf)
453 {
454         /*
455          * Switch on tuning bits.
456          */
457         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
458         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
459
460         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
461         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
462         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
463
464         /*
465          * RF2420 chipset don't need any additional actions.
466          */
467         if (rt2x00_rf(rt2x00dev, RF2420))
468                 return;
469
470         /*
471          * For the RT2421 chipsets we need to write an invalid
472          * reference clock rate to activate auto_tune.
473          * After that we set the value back to the correct channel.
474          */
475         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
476         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
477         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
478
479         msleep(1);
480
481         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
482         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
483         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
484
485         msleep(1);
486
487         /*
488          * Switch off tuning bits.
489          */
490         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
491         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
492
493         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
494         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
495
496         /*
497          * Clear false CRC during channel switch.
498          */
499         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
500 }
501
502 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
503 {
504         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
505 }
506
507 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
508                                          struct rt2x00lib_conf *libconf)
509 {
510         u32 reg;
511
512         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
513         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
514                            libconf->conf->long_frame_max_tx_count);
515         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
516                            libconf->conf->short_frame_max_tx_count);
517         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
518 }
519
520 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
521                                 struct rt2x00lib_conf *libconf)
522 {
523         enum dev_state state =
524             (libconf->conf->flags & IEEE80211_CONF_PS) ?
525                 STATE_SLEEP : STATE_AWAKE;
526         u32 reg;
527
528         if (state == STATE_SLEEP) {
529                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
530                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
531                                    (rt2x00dev->beacon_int - 20) * 16);
532                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
533                                    libconf->conf->listen_interval - 1);
534
535                 /* We must first disable autowake before it can be enabled */
536                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
537                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
538
539                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
540                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
541         } else {
542                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
543                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
544                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
545         }
546
547         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
548 }
549
550 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
551                              struct rt2x00lib_conf *libconf,
552                              const unsigned int flags)
553 {
554         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
555                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
556         if (flags & IEEE80211_CONF_CHANGE_POWER)
557                 rt2400pci_config_txpower(rt2x00dev,
558                                          libconf->conf->power_level);
559         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
560                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
561         if (flags & IEEE80211_CONF_CHANGE_PS)
562                 rt2400pci_config_ps(rt2x00dev, libconf);
563 }
564
565 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
566                                 const int cw_min, const int cw_max)
567 {
568         u32 reg;
569
570         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
571         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
572         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
573         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
574 }
575
576 /*
577  * Link tuning
578  */
579 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
580                                  struct link_qual *qual)
581 {
582         u32 reg;
583         u8 bbp;
584
585         /*
586          * Update FCS error count from register.
587          */
588         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
589         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
590
591         /*
592          * Update False CCA count from register.
593          */
594         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
595         qual->false_cca = bbp;
596 }
597
598 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
599                                      struct link_qual *qual, u8 vgc_level)
600 {
601         if (qual->vgc_level_reg != vgc_level) {
602                 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
603                 qual->vgc_level = vgc_level;
604                 qual->vgc_level_reg = vgc_level;
605         }
606 }
607
608 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
609                                   struct link_qual *qual)
610 {
611         rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
612 }
613
614 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
615                                  struct link_qual *qual, const u32 count)
616 {
617         /*
618          * The link tuner should not run longer then 60 seconds,
619          * and should run once every 2 seconds.
620          */
621         if (count > 60 || !(count & 1))
622                 return;
623
624         /*
625          * Base r13 link tuning on the false cca count.
626          */
627         if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
628                 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
629         else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
630                 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
631 }
632
633 /*
634  * Queue handlers.
635  */
636 static void rt2400pci_start_queue(struct data_queue *queue)
637 {
638         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
639         u32 reg;
640
641         switch (queue->qid) {
642         case QID_RX:
643                 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
644                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
645                 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
646                 break;
647         case QID_BEACON:
648                 /*
649                  * Allow the tbtt tasklet to be scheduled.
650                  */
651                 tasklet_enable(&rt2x00dev->tbtt_tasklet);
652
653                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
654                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
655                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
656                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
657                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
658                 break;
659         default:
660                 break;
661         }
662 }
663
664 static void rt2400pci_kick_queue(struct data_queue *queue)
665 {
666         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
667         u32 reg;
668
669         switch (queue->qid) {
670         case QID_AC_VO:
671                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
672                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
673                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
674                 break;
675         case QID_AC_VI:
676                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
677                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
678                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
679                 break;
680         case QID_ATIM:
681                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
682                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
683                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
684                 break;
685         default:
686                 break;
687         }
688 }
689
690 static void rt2400pci_stop_queue(struct data_queue *queue)
691 {
692         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
693         u32 reg;
694
695         switch (queue->qid) {
696         case QID_AC_VO:
697         case QID_AC_VI:
698         case QID_ATIM:
699                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
700                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
701                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
702                 break;
703         case QID_RX:
704                 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
705                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
706                 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
707                 break;
708         case QID_BEACON:
709                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
710                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
711                 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
712                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
713                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
714
715                 /*
716                  * Wait for possibly running tbtt tasklets.
717                  */
718                 tasklet_disable(&rt2x00dev->tbtt_tasklet);
719                 break;
720         default:
721                 break;
722         }
723 }
724
725 /*
726  * Initialization functions.
727  */
728 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
729 {
730         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
731         u32 word;
732
733         if (entry->queue->qid == QID_RX) {
734                 rt2x00_desc_read(entry_priv->desc, 0, &word);
735
736                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
737         } else {
738                 rt2x00_desc_read(entry_priv->desc, 0, &word);
739
740                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
741                         rt2x00_get_field32(word, TXD_W0_VALID));
742         }
743 }
744
745 static void rt2400pci_clear_entry(struct queue_entry *entry)
746 {
747         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
748         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
749         u32 word;
750
751         if (entry->queue->qid == QID_RX) {
752                 rt2x00_desc_read(entry_priv->desc, 2, &word);
753                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
754                 rt2x00_desc_write(entry_priv->desc, 2, word);
755
756                 rt2x00_desc_read(entry_priv->desc, 1, &word);
757                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
758                 rt2x00_desc_write(entry_priv->desc, 1, word);
759
760                 rt2x00_desc_read(entry_priv->desc, 0, &word);
761                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
762                 rt2x00_desc_write(entry_priv->desc, 0, word);
763         } else {
764                 rt2x00_desc_read(entry_priv->desc, 0, &word);
765                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
766                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
767                 rt2x00_desc_write(entry_priv->desc, 0, word);
768         }
769 }
770
771 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
772 {
773         struct queue_entry_priv_pci *entry_priv;
774         u32 reg;
775
776         /*
777          * Initialize registers.
778          */
779         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
780         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
781         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
782         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
783         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
784         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
785
786         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
787         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
788         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
789                            entry_priv->desc_dma);
790         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
791
792         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
793         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
794         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
795                            entry_priv->desc_dma);
796         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
797
798         entry_priv = rt2x00dev->atim->entries[0].priv_data;
799         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
800         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
801                            entry_priv->desc_dma);
802         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
803
804         entry_priv = rt2x00dev->bcn->entries[0].priv_data;
805         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
806         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
807                            entry_priv->desc_dma);
808         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
809
810         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
811         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
812         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
813         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
814
815         entry_priv = rt2x00dev->rx->entries[0].priv_data;
816         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
817         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
818                            entry_priv->desc_dma);
819         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
820
821         return 0;
822 }
823
824 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
825 {
826         u32 reg;
827
828         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
829         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
830         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
831         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
832
833         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
834         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
835         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
836         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
837         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
838
839         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
840         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
841                            (rt2x00dev->rx->data_size / 128));
842         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
843
844         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
845         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
846         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
847         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
848         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
849         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
850         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
851         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
852         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
853         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
854
855         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
856
857         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
858         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
859         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
860         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
861         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
862         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
863
864         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
865         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
866         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
867         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
868         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
869         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
870         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
871         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
872
873         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
874
875         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
876                 return -EBUSY;
877
878         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
879         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
880
881         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
882         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
883         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
884
885         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
886         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
887         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
888         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
889         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
890         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
891
892         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
893         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
894         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
895         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
896         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
897
898         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
899         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
900         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
901         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
902
903         /*
904          * We must clear the FCS and FIFO error count.
905          * These registers are cleared on read,
906          * so we may pass a useless variable to store the value.
907          */
908         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
909         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
910
911         return 0;
912 }
913
914 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
915 {
916         unsigned int i;
917         u8 value;
918
919         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
920                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
921                 if ((value != 0xff) && (value != 0x00))
922                         return 0;
923                 udelay(REGISTER_BUSY_DELAY);
924         }
925
926         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
927         return -EACCES;
928 }
929
930 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
931 {
932         unsigned int i;
933         u16 eeprom;
934         u8 reg_id;
935         u8 value;
936
937         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
938                 return -EACCES;
939
940         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
941         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
942         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
943         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
944         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
945         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
946         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
947         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
948         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
949         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
950         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
951         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
952         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
953         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
954
955         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
956                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
957
958                 if (eeprom != 0xffff && eeprom != 0x0000) {
959                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
960                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
961                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
962                 }
963         }
964
965         return 0;
966 }
967
968 /*
969  * Device state switch handlers.
970  */
971 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
972                                  enum dev_state state)
973 {
974         int mask = (state == STATE_RADIO_IRQ_OFF);
975         u32 reg;
976         unsigned long flags;
977
978         /*
979          * When interrupts are being enabled, the interrupt registers
980          * should clear the register to assure a clean state.
981          */
982         if (state == STATE_RADIO_IRQ_ON) {
983                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
984                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
985
986                 /*
987                  * Enable tasklets.
988                  */
989                 tasklet_enable(&rt2x00dev->txstatus_tasklet);
990                 tasklet_enable(&rt2x00dev->rxdone_tasklet);
991         }
992
993         /*
994          * Only toggle the interrupts bits we are going to use.
995          * Non-checked interrupt bits are disabled by default.
996          */
997         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
998
999         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1000         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1001         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1002         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1003         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1004         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1005         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1006
1007         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1008
1009         if (state == STATE_RADIO_IRQ_OFF) {
1010                 /*
1011                  * Ensure that all tasklets are finished before
1012                  * disabling the interrupts.
1013                  */
1014                 tasklet_disable(&rt2x00dev->txstatus_tasklet);
1015                 tasklet_disable(&rt2x00dev->rxdone_tasklet);
1016         }
1017 }
1018
1019 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1020 {
1021         /*
1022          * Initialize all registers.
1023          */
1024         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1025                      rt2400pci_init_registers(rt2x00dev) ||
1026                      rt2400pci_init_bbp(rt2x00dev)))
1027                 return -EIO;
1028
1029         return 0;
1030 }
1031
1032 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1033 {
1034         /*
1035          * Disable power
1036          */
1037         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1038 }
1039
1040 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1041                                enum dev_state state)
1042 {
1043         u32 reg, reg2;
1044         unsigned int i;
1045         char put_to_sleep;
1046         char bbp_state;
1047         char rf_state;
1048
1049         put_to_sleep = (state != STATE_AWAKE);
1050
1051         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1052         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1053         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1054         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1055         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1056         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1057
1058         /*
1059          * Device is not guaranteed to be in the requested state yet.
1060          * We must wait until the register indicates that the
1061          * device has entered the correct state.
1062          */
1063         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1064                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
1065                 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1066                 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1067                 if (bbp_state == state && rf_state == state)
1068                         return 0;
1069                 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1070                 msleep(10);
1071         }
1072
1073         return -EBUSY;
1074 }
1075
1076 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1077                                       enum dev_state state)
1078 {
1079         int retval = 0;
1080
1081         switch (state) {
1082         case STATE_RADIO_ON:
1083                 retval = rt2400pci_enable_radio(rt2x00dev);
1084                 break;
1085         case STATE_RADIO_OFF:
1086                 rt2400pci_disable_radio(rt2x00dev);
1087                 break;
1088         case STATE_RADIO_IRQ_ON:
1089         case STATE_RADIO_IRQ_OFF:
1090                 rt2400pci_toggle_irq(rt2x00dev, state);
1091                 break;
1092         case STATE_DEEP_SLEEP:
1093         case STATE_SLEEP:
1094         case STATE_STANDBY:
1095         case STATE_AWAKE:
1096                 retval = rt2400pci_set_state(rt2x00dev, state);
1097                 break;
1098         default:
1099                 retval = -ENOTSUPP;
1100                 break;
1101         }
1102
1103         if (unlikely(retval))
1104                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1105                       state, retval);
1106
1107         return retval;
1108 }
1109
1110 /*
1111  * TX descriptor initialization
1112  */
1113 static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1114                                     struct txentry_desc *txdesc)
1115 {
1116         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1117         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1118         __le32 *txd = entry_priv->desc;
1119         u32 word;
1120
1121         /*
1122          * Start writing the descriptor words.
1123          */
1124         rt2x00_desc_read(txd, 1, &word);
1125         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1126         rt2x00_desc_write(txd, 1, word);
1127
1128         rt2x00_desc_read(txd, 2, &word);
1129         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1130         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1131         rt2x00_desc_write(txd, 2, word);
1132
1133         rt2x00_desc_read(txd, 3, &word);
1134         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1135         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1136         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1137         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1138         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1139         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1140         rt2x00_desc_write(txd, 3, word);
1141
1142         rt2x00_desc_read(txd, 4, &word);
1143         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1144                            txdesc->u.plcp.length_low);
1145         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1146         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1147         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1148                            txdesc->u.plcp.length_high);
1149         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1150         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1151         rt2x00_desc_write(txd, 4, word);
1152
1153         /*
1154          * Writing TXD word 0 must the last to prevent a race condition with
1155          * the device, whereby the device may take hold of the TXD before we
1156          * finished updating it.
1157          */
1158         rt2x00_desc_read(txd, 0, &word);
1159         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1160         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1161         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1162                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1163         rt2x00_set_field32(&word, TXD_W0_ACK,
1164                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1165         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1166                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1167         rt2x00_set_field32(&word, TXD_W0_RTS,
1168                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1169         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1170         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1171                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1172         rt2x00_desc_write(txd, 0, word);
1173
1174         /*
1175          * Register descriptor details in skb frame descriptor.
1176          */
1177         skbdesc->desc = txd;
1178         skbdesc->desc_len = TXD_DESC_SIZE;
1179 }
1180
1181 /*
1182  * TX data initialization
1183  */
1184 static void rt2400pci_write_beacon(struct queue_entry *entry,
1185                                    struct txentry_desc *txdesc)
1186 {
1187         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1188         u32 reg;
1189
1190         /*
1191          * Disable beaconing while we are reloading the beacon data,
1192          * otherwise we might be sending out invalid data.
1193          */
1194         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1195         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1196         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1197
1198         rt2x00queue_map_txskb(entry);
1199
1200         /*
1201          * Write the TX descriptor for the beacon.
1202          */
1203         rt2400pci_write_tx_desc(entry, txdesc);
1204
1205         /*
1206          * Dump beacon to userspace through debugfs.
1207          */
1208         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1209
1210         /*
1211          * Enable beaconing again.
1212          */
1213         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1214         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1215 }
1216
1217 /*
1218  * RX control handlers
1219  */
1220 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1221                                   struct rxdone_entry_desc *rxdesc)
1222 {
1223         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1224         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1225         u32 word0;
1226         u32 word2;
1227         u32 word3;
1228         u32 word4;
1229         u64 tsf;
1230         u32 rx_low;
1231         u32 rx_high;
1232
1233         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1234         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1235         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1236         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1237
1238         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1239                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1240         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1241                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1242
1243         /*
1244          * We only get the lower 32bits from the timestamp,
1245          * to get the full 64bits we must complement it with
1246          * the timestamp from get_tsf().
1247          * Note that when a wraparound of the lower 32bits
1248          * has occurred between the frame arrival and the get_tsf()
1249          * call, we must decrease the higher 32bits with 1 to get
1250          * to correct value.
1251          */
1252         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1253         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1254         rx_high = upper_32_bits(tsf);
1255
1256         if ((u32)tsf <= rx_low)
1257                 rx_high--;
1258
1259         /*
1260          * Obtain the status about this packet.
1261          * The signal is the PLCP value, and needs to be stripped
1262          * of the preamble bit (0x08).
1263          */
1264         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1265         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1266         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1267             entry->queue->rt2x00dev->rssi_offset;
1268         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1269
1270         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1271         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1272                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1273 }
1274
1275 /*
1276  * Interrupt functions.
1277  */
1278 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1279                              const enum data_queue_qid queue_idx)
1280 {
1281         struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1282         struct queue_entry_priv_pci *entry_priv;
1283         struct queue_entry *entry;
1284         struct txdone_entry_desc txdesc;
1285         u32 word;
1286
1287         while (!rt2x00queue_empty(queue)) {
1288                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1289                 entry_priv = entry->priv_data;
1290                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1291
1292                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1293                     !rt2x00_get_field32(word, TXD_W0_VALID))
1294                         break;
1295
1296                 /*
1297                  * Obtain the status about this packet.
1298                  */
1299                 txdesc.flags = 0;
1300                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1301                 case 0: /* Success */
1302                 case 1: /* Success with retry */
1303                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1304                         break;
1305                 case 2: /* Failure, excessive retries */
1306                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1307                         /* Don't break, this is a failed frame! */
1308                 default: /* Failure */
1309                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1310                 }
1311                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1312
1313                 rt2x00lib_txdone(entry, &txdesc);
1314         }
1315 }
1316
1317 static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1318                                               struct rt2x00_field32 irq_field)
1319 {
1320         u32 reg;
1321
1322         /*
1323          * Enable a single interrupt. The interrupt mask register
1324          * access needs locking.
1325          */
1326         spin_lock_irq(&rt2x00dev->irqmask_lock);
1327
1328         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1329         rt2x00_set_field32(&reg, irq_field, 0);
1330         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1331
1332         spin_unlock_irq(&rt2x00dev->irqmask_lock);
1333 }
1334
1335 static void rt2400pci_txstatus_tasklet(unsigned long data)
1336 {
1337         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1338         u32 reg;
1339
1340         /*
1341          * Handle all tx queues.
1342          */
1343         rt2400pci_txdone(rt2x00dev, QID_ATIM);
1344         rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1345         rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1346
1347         /*
1348          * Enable all TXDONE interrupts again.
1349          */
1350         spin_lock_irq(&rt2x00dev->irqmask_lock);
1351
1352         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1353         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1354         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1355         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1356         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1357
1358         spin_unlock_irq(&rt2x00dev->irqmask_lock);
1359 }
1360
1361 static void rt2400pci_tbtt_tasklet(unsigned long data)
1362 {
1363         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1364         rt2x00lib_beacondone(rt2x00dev);
1365         rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1366 }
1367
1368 static void rt2400pci_rxdone_tasklet(unsigned long data)
1369 {
1370         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1371         if (rt2x00pci_rxdone(rt2x00dev))
1372                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1373         else
1374                 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1375 }
1376
1377 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1378 {
1379         struct rt2x00_dev *rt2x00dev = dev_instance;
1380         u32 reg, mask;
1381
1382         /*
1383          * Get the interrupt sources & saved to local variable.
1384          * Write register value back to clear pending interrupts.
1385          */
1386         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1387         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1388
1389         if (!reg)
1390                 return IRQ_NONE;
1391
1392         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1393                 return IRQ_HANDLED;
1394
1395         mask = reg;
1396
1397         /*
1398          * Schedule tasklets for interrupt handling.
1399          */
1400         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1401                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1402
1403         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1404                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1405
1406         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1407             rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1408             rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1409                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1410                 /*
1411                  * Mask out all txdone interrupts.
1412                  */
1413                 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1414                 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1415                 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1416         }
1417
1418         /*
1419          * Disable all interrupts for which a tasklet was scheduled right now,
1420          * the tasklet will reenable the appropriate interrupts.
1421          */
1422         spin_lock(&rt2x00dev->irqmask_lock);
1423
1424         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1425         reg |= mask;
1426         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1427
1428         spin_unlock(&rt2x00dev->irqmask_lock);
1429
1430
1431
1432         return IRQ_HANDLED;
1433 }
1434
1435 /*
1436  * Device probe functions.
1437  */
1438 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1439 {
1440         struct eeprom_93cx6 eeprom;
1441         u32 reg;
1442         u16 word;
1443         u8 *mac;
1444
1445         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1446
1447         eeprom.data = rt2x00dev;
1448         eeprom.register_read = rt2400pci_eepromregister_read;
1449         eeprom.register_write = rt2400pci_eepromregister_write;
1450         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1451             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1452         eeprom.reg_data_in = 0;
1453         eeprom.reg_data_out = 0;
1454         eeprom.reg_data_clock = 0;
1455         eeprom.reg_chip_select = 0;
1456
1457         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1458                                EEPROM_SIZE / sizeof(u16));
1459
1460         /*
1461          * Start validation of the data that has been read.
1462          */
1463         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1464         if (!is_valid_ether_addr(mac)) {
1465                 random_ether_addr(mac);
1466                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1467         }
1468
1469         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1470         if (word == 0xffff) {
1471                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1472                 return -EINVAL;
1473         }
1474
1475         return 0;
1476 }
1477
1478 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1479 {
1480         u32 reg;
1481         u16 value;
1482         u16 eeprom;
1483
1484         /*
1485          * Read EEPROM word for configuration.
1486          */
1487         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1488
1489         /*
1490          * Identify RF chipset.
1491          */
1492         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1493         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1494         rt2x00_set_chip(rt2x00dev, RT2460, value,
1495                         rt2x00_get_field32(reg, CSR0_REVISION));
1496
1497         if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1498                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1499                 return -ENODEV;
1500         }
1501
1502         /*
1503          * Identify default antenna configuration.
1504          */
1505         rt2x00dev->default_ant.tx =
1506             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1507         rt2x00dev->default_ant.rx =
1508             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1509
1510         /*
1511          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1512          * I am not 100% sure about this, but the legacy drivers do not
1513          * indicate antenna swapping in software is required when
1514          * diversity is enabled.
1515          */
1516         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1517                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1518         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1519                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1520
1521         /*
1522          * Store led mode, for correct led behaviour.
1523          */
1524 #ifdef CONFIG_RT2X00_LIB_LEDS
1525         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1526
1527         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1528         if (value == LED_MODE_TXRX_ACTIVITY ||
1529             value == LED_MODE_DEFAULT ||
1530             value == LED_MODE_ASUS)
1531                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1532                                    LED_TYPE_ACTIVITY);
1533 #endif /* CONFIG_RT2X00_LIB_LEDS */
1534
1535         /*
1536          * Detect if this device has an hardware controlled radio.
1537          */
1538         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1539                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1540
1541         /*
1542          * Check if the BBP tuning should be enabled.
1543          */
1544         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1545                 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1546
1547         return 0;
1548 }
1549
1550 /*
1551  * RF value list for RF2420 & RF2421
1552  * Supports: 2.4 GHz
1553  */
1554 static const struct rf_channel rf_vals_b[] = {
1555         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1556         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1557         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1558         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1559         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1560         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1561         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1562         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1563         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1564         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1565         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1566         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1567         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1568         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1569 };
1570
1571 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1572 {
1573         struct hw_mode_spec *spec = &rt2x00dev->spec;
1574         struct channel_info *info;
1575         char *tx_power;
1576         unsigned int i;
1577
1578         /*
1579          * Initialize all hw fields.
1580          */
1581         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1582                                IEEE80211_HW_SIGNAL_DBM |
1583                                IEEE80211_HW_SUPPORTS_PS |
1584                                IEEE80211_HW_PS_NULLFUNC_STACK;
1585
1586         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1587         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1588                                 rt2x00_eeprom_addr(rt2x00dev,
1589                                                    EEPROM_MAC_ADDR_0));
1590
1591         /*
1592          * Initialize hw_mode information.
1593          */
1594         spec->supported_bands = SUPPORT_BAND_2GHZ;
1595         spec->supported_rates = SUPPORT_RATE_CCK;
1596
1597         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1598         spec->channels = rf_vals_b;
1599
1600         /*
1601          * Create channel information array
1602          */
1603         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1604         if (!info)
1605                 return -ENOMEM;
1606
1607         spec->channels_info = info;
1608
1609         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1610         for (i = 0; i < 14; i++) {
1611                 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1612                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1613         }
1614
1615         return 0;
1616 }
1617
1618 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1619 {
1620         int retval;
1621
1622         /*
1623          * Allocate eeprom data.
1624          */
1625         retval = rt2400pci_validate_eeprom(rt2x00dev);
1626         if (retval)
1627                 return retval;
1628
1629         retval = rt2400pci_init_eeprom(rt2x00dev);
1630         if (retval)
1631                 return retval;
1632
1633         /*
1634          * Initialize hw specifications.
1635          */
1636         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1637         if (retval)
1638                 return retval;
1639
1640         /*
1641          * This device requires the atim queue and DMA-mapped skbs.
1642          */
1643         __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1644         __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1645         __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1646
1647         /*
1648          * Set the rssi offset.
1649          */
1650         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1651
1652         return 0;
1653 }
1654
1655 /*
1656  * IEEE80211 stack callback functions.
1657  */
1658 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1659                              const struct ieee80211_tx_queue_params *params)
1660 {
1661         struct rt2x00_dev *rt2x00dev = hw->priv;
1662
1663         /*
1664          * We don't support variating cw_min and cw_max variables
1665          * per queue. So by default we only configure the TX queue,
1666          * and ignore all other configurations.
1667          */
1668         if (queue != 0)
1669                 return -EINVAL;
1670
1671         if (rt2x00mac_conf_tx(hw, queue, params))
1672                 return -EINVAL;
1673
1674         /*
1675          * Write configuration to register.
1676          */
1677         rt2400pci_config_cw(rt2x00dev,
1678                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1679
1680         return 0;
1681 }
1682
1683 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1684 {
1685         struct rt2x00_dev *rt2x00dev = hw->priv;
1686         u64 tsf;
1687         u32 reg;
1688
1689         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1690         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1691         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1692         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1693
1694         return tsf;
1695 }
1696
1697 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1698 {
1699         struct rt2x00_dev *rt2x00dev = hw->priv;
1700         u32 reg;
1701
1702         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1703         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1704 }
1705
1706 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1707         .tx                     = rt2x00mac_tx,
1708         .start                  = rt2x00mac_start,
1709         .stop                   = rt2x00mac_stop,
1710         .add_interface          = rt2x00mac_add_interface,
1711         .remove_interface       = rt2x00mac_remove_interface,
1712         .config                 = rt2x00mac_config,
1713         .configure_filter       = rt2x00mac_configure_filter,
1714         .sw_scan_start          = rt2x00mac_sw_scan_start,
1715         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
1716         .get_stats              = rt2x00mac_get_stats,
1717         .bss_info_changed       = rt2x00mac_bss_info_changed,
1718         .conf_tx                = rt2400pci_conf_tx,
1719         .get_tsf                = rt2400pci_get_tsf,
1720         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1721         .rfkill_poll            = rt2x00mac_rfkill_poll,
1722         .flush                  = rt2x00mac_flush,
1723         .set_antenna            = rt2x00mac_set_antenna,
1724         .get_antenna            = rt2x00mac_get_antenna,
1725         .get_ringparam          = rt2x00mac_get_ringparam,
1726         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
1727 };
1728
1729 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1730         .irq_handler            = rt2400pci_interrupt,
1731         .txstatus_tasklet       = rt2400pci_txstatus_tasklet,
1732         .tbtt_tasklet           = rt2400pci_tbtt_tasklet,
1733         .rxdone_tasklet         = rt2400pci_rxdone_tasklet,
1734         .probe_hw               = rt2400pci_probe_hw,
1735         .initialize             = rt2x00pci_initialize,
1736         .uninitialize           = rt2x00pci_uninitialize,
1737         .get_entry_state        = rt2400pci_get_entry_state,
1738         .clear_entry            = rt2400pci_clear_entry,
1739         .set_device_state       = rt2400pci_set_device_state,
1740         .rfkill_poll            = rt2400pci_rfkill_poll,
1741         .link_stats             = rt2400pci_link_stats,
1742         .reset_tuner            = rt2400pci_reset_tuner,
1743         .link_tuner             = rt2400pci_link_tuner,
1744         .start_queue            = rt2400pci_start_queue,
1745         .kick_queue             = rt2400pci_kick_queue,
1746         .stop_queue             = rt2400pci_stop_queue,
1747         .flush_queue            = rt2x00pci_flush_queue,
1748         .write_tx_desc          = rt2400pci_write_tx_desc,
1749         .write_beacon           = rt2400pci_write_beacon,
1750         .fill_rxdone            = rt2400pci_fill_rxdone,
1751         .config_filter          = rt2400pci_config_filter,
1752         .config_intf            = rt2400pci_config_intf,
1753         .config_erp             = rt2400pci_config_erp,
1754         .config_ant             = rt2400pci_config_ant,
1755         .config                 = rt2400pci_config,
1756 };
1757
1758 static const struct data_queue_desc rt2400pci_queue_rx = {
1759         .entry_num              = 24,
1760         .data_size              = DATA_FRAME_SIZE,
1761         .desc_size              = RXD_DESC_SIZE,
1762         .priv_size              = sizeof(struct queue_entry_priv_pci),
1763 };
1764
1765 static const struct data_queue_desc rt2400pci_queue_tx = {
1766         .entry_num              = 24,
1767         .data_size              = DATA_FRAME_SIZE,
1768         .desc_size              = TXD_DESC_SIZE,
1769         .priv_size              = sizeof(struct queue_entry_priv_pci),
1770 };
1771
1772 static const struct data_queue_desc rt2400pci_queue_bcn = {
1773         .entry_num              = 1,
1774         .data_size              = MGMT_FRAME_SIZE,
1775         .desc_size              = TXD_DESC_SIZE,
1776         .priv_size              = sizeof(struct queue_entry_priv_pci),
1777 };
1778
1779 static const struct data_queue_desc rt2400pci_queue_atim = {
1780         .entry_num              = 8,
1781         .data_size              = DATA_FRAME_SIZE,
1782         .desc_size              = TXD_DESC_SIZE,
1783         .priv_size              = sizeof(struct queue_entry_priv_pci),
1784 };
1785
1786 static const struct rt2x00_ops rt2400pci_ops = {
1787         .name                   = KBUILD_MODNAME,
1788         .max_sta_intf           = 1,
1789         .max_ap_intf            = 1,
1790         .eeprom_size            = EEPROM_SIZE,
1791         .rf_size                = RF_SIZE,
1792         .tx_queues              = NUM_TX_QUEUES,
1793         .extra_tx_headroom      = 0,
1794         .rx                     = &rt2400pci_queue_rx,
1795         .tx                     = &rt2400pci_queue_tx,
1796         .bcn                    = &rt2400pci_queue_bcn,
1797         .atim                   = &rt2400pci_queue_atim,
1798         .lib                    = &rt2400pci_rt2x00_ops,
1799         .hw                     = &rt2400pci_mac80211_ops,
1800 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1801         .debugfs                = &rt2400pci_rt2x00debug,
1802 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1803 };
1804
1805 /*
1806  * RT2400pci module information.
1807  */
1808 static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
1809         { PCI_DEVICE(0x1814, 0x0101) },
1810         { 0, }
1811 };
1812
1813
1814 MODULE_AUTHOR(DRV_PROJECT);
1815 MODULE_VERSION(DRV_VERSION);
1816 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1817 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1818 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1819 MODULE_LICENSE("GPL");
1820
1821 static int rt2400pci_probe(struct pci_dev *pci_dev,
1822                            const struct pci_device_id *id)
1823 {
1824         return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
1825 }
1826
1827 static struct pci_driver rt2400pci_driver = {
1828         .name           = KBUILD_MODNAME,
1829         .id_table       = rt2400pci_device_table,
1830         .probe          = rt2400pci_probe,
1831         .remove         = __devexit_p(rt2x00pci_remove),
1832         .suspend        = rt2x00pci_suspend,
1833         .resume         = rt2x00pci_resume,
1834 };
1835
1836 static int __init rt2400pci_init(void)
1837 {
1838         return pci_register_driver(&rt2400pci_driver);
1839 }
1840
1841 static void __exit rt2400pci_exit(void)
1842 {
1843         pci_unregister_driver(&rt2400pci_driver);
1844 }
1845
1846 module_init(rt2400pci_init);
1847 module_exit(rt2400pci_exit);