mac80211: unify config_interface and bss_info_changed
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2400pci
23         Abstract: rt2400pci device specific routines.
24         Supported chipsets: RT2460.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2400pci.h"
38
39 /*
40  * Register access.
41  * All access to the CSR registers will go through the methods
42  * rt2x00pci_register_read and rt2x00pci_register_write.
43  * BBP and RF register require indirect register access,
44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
45  * These indirect registers work with busy bits,
46  * and we will try maximal REGISTER_BUSY_COUNT times to access
47  * the register while taking a REGISTER_BUSY_DELAY us delay
48  * between each attampt. When the busy bit is still set at that time,
49  * the access attempt is considered to have failed,
50  * and we will print an error.
51  */
52 #define WAIT_FOR_BBP(__dev, __reg) \
53         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 #define WAIT_FOR_RF(__dev, __reg) \
55         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
58                                 const unsigned int word, const u8 value)
59 {
60         u32 reg;
61
62         mutex_lock(&rt2x00dev->csr_mutex);
63
64         /*
65          * Wait until the BBP becomes available, afterwards we
66          * can safely write the new data into the register.
67          */
68         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
69                 reg = 0;
70                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
71                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
72                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
73                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
74
75                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
76         }
77
78         mutex_unlock(&rt2x00dev->csr_mutex);
79 }
80
81 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
82                                const unsigned int word, u8 *value)
83 {
84         u32 reg;
85
86         mutex_lock(&rt2x00dev->csr_mutex);
87
88         /*
89          * Wait until the BBP becomes available, afterwards we
90          * can safely write the read request into the register.
91          * After the data has been written, we wait until hardware
92          * returns the correct value, if at any time the register
93          * doesn't become available in time, reg will be 0xffffffff
94          * which means we return 0xff to the caller.
95          */
96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
97                 reg = 0;
98                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
101
102                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
103
104                 WAIT_FOR_BBP(rt2x00dev, &reg);
105         }
106
107         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
108
109         mutex_unlock(&rt2x00dev->csr_mutex);
110 }
111
112 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
113                                const unsigned int word, const u32 value)
114 {
115         u32 reg;
116
117         mutex_lock(&rt2x00dev->csr_mutex);
118
119         /*
120          * Wait until the RF becomes available, afterwards we
121          * can safely write the new data into the register.
122          */
123         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
124                 reg = 0;
125                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
126                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
127                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
128                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
129
130                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
131                 rt2x00_rf_write(rt2x00dev, word, value);
132         }
133
134         mutex_unlock(&rt2x00dev->csr_mutex);
135 }
136
137 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
138 {
139         struct rt2x00_dev *rt2x00dev = eeprom->data;
140         u32 reg;
141
142         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
143
144         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
145         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
146         eeprom->reg_data_clock =
147             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
148         eeprom->reg_chip_select =
149             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
150 }
151
152 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
153 {
154         struct rt2x00_dev *rt2x00dev = eeprom->data;
155         u32 reg = 0;
156
157         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
160                            !!eeprom->reg_data_clock);
161         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
162                            !!eeprom->reg_chip_select);
163
164         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
165 }
166
167 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
168 static const struct rt2x00debug rt2400pci_rt2x00debug = {
169         .owner  = THIS_MODULE,
170         .csr    = {
171                 .read           = rt2x00pci_register_read,
172                 .write          = rt2x00pci_register_write,
173                 .flags          = RT2X00DEBUGFS_OFFSET,
174                 .word_base      = CSR_REG_BASE,
175                 .word_size      = sizeof(u32),
176                 .word_count     = CSR_REG_SIZE / sizeof(u32),
177         },
178         .eeprom = {
179                 .read           = rt2x00_eeprom_read,
180                 .write          = rt2x00_eeprom_write,
181                 .word_base      = EEPROM_BASE,
182                 .word_size      = sizeof(u16),
183                 .word_count     = EEPROM_SIZE / sizeof(u16),
184         },
185         .bbp    = {
186                 .read           = rt2400pci_bbp_read,
187                 .write          = rt2400pci_bbp_write,
188                 .word_base      = BBP_BASE,
189                 .word_size      = sizeof(u8),
190                 .word_count     = BBP_SIZE / sizeof(u8),
191         },
192         .rf     = {
193                 .read           = rt2x00_rf_read,
194                 .write          = rt2400pci_rf_write,
195                 .word_base      = RF_BASE,
196                 .word_size      = sizeof(u32),
197                 .word_count     = RF_SIZE / sizeof(u32),
198         },
199 };
200 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
201
202 #ifdef CONFIG_RT2X00_LIB_RFKILL
203 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
204 {
205         u32 reg;
206
207         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
208         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
209 }
210 #else
211 #define rt2400pci_rfkill_poll   NULL
212 #endif /* CONFIG_RT2X00_LIB_RFKILL */
213
214 #ifdef CONFIG_RT2X00_LIB_LEDS
215 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
216                                      enum led_brightness brightness)
217 {
218         struct rt2x00_led *led =
219             container_of(led_cdev, struct rt2x00_led, led_dev);
220         unsigned int enabled = brightness != LED_OFF;
221         u32 reg;
222
223         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
224
225         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
226                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
227         else if (led->type == LED_TYPE_ACTIVITY)
228                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
229
230         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
231 }
232
233 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
234                                unsigned long *delay_on,
235                                unsigned long *delay_off)
236 {
237         struct rt2x00_led *led =
238             container_of(led_cdev, struct rt2x00_led, led_dev);
239         u32 reg;
240
241         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
242         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
243         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
244         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
245
246         return 0;
247 }
248
249 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
250                                struct rt2x00_led *led,
251                                enum led_type type)
252 {
253         led->rt2x00dev = rt2x00dev;
254         led->type = type;
255         led->led_dev.brightness_set = rt2400pci_brightness_set;
256         led->led_dev.blink_set = rt2400pci_blink_set;
257         led->flags = LED_INITIALIZED;
258 }
259 #endif /* CONFIG_RT2X00_LIB_LEDS */
260
261 /*
262  * Configuration handlers.
263  */
264 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
265                                     const unsigned int filter_flags)
266 {
267         u32 reg;
268
269         /*
270          * Start configuration steps.
271          * Note that the version error will always be dropped
272          * since there is no filter for it at this time.
273          */
274         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
275         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
276                            !(filter_flags & FIF_FCSFAIL));
277         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
278                            !(filter_flags & FIF_PLCPFAIL));
279         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
280                            !(filter_flags & FIF_CONTROL));
281         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
282                            !(filter_flags & FIF_PROMISC_IN_BSS));
283         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
284                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
285                            !rt2x00dev->intf_ap_count);
286         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
287         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
288 }
289
290 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
291                                   struct rt2x00_intf *intf,
292                                   struct rt2x00intf_conf *conf,
293                                   const unsigned int flags)
294 {
295         unsigned int bcn_preload;
296         u32 reg;
297
298         if (flags & CONFIG_UPDATE_TYPE) {
299                 /*
300                  * Enable beacon config
301                  */
302                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
303                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
304                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
305                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
306
307                 /*
308                  * Enable synchronisation.
309                  */
310                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
311                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
312                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
313                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
314                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
315         }
316
317         if (flags & CONFIG_UPDATE_MAC)
318                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
319                                               conf->mac, sizeof(conf->mac));
320
321         if (flags & CONFIG_UPDATE_BSSID)
322                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
323                                               conf->bssid, sizeof(conf->bssid));
324 }
325
326 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
327                                  struct rt2x00lib_erp *erp)
328 {
329         int preamble_mask;
330         u32 reg;
331
332         /*
333          * When short preamble is enabled, we should set bit 0x08
334          */
335         preamble_mask = erp->short_preamble << 3;
336
337         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
338         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
339                            erp->ack_timeout);
340         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
341                            erp->ack_consume_time);
342         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
343
344         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
345         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
346         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
347         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
348         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
349
350         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
351         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
352         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
353         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
354         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
355
356         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
357         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
358         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
359         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
360         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
361
362         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
363         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
364         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
365         rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
366         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
367
368         rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
369
370         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
371         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
372         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
373
374         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
375         rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
376         rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
377         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
378
379         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
380         rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
381         rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
382         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
383 }
384
385 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
386                                  struct antenna_setup *ant)
387 {
388         u8 r1;
389         u8 r4;
390
391         /*
392          * We should never come here because rt2x00lib is supposed
393          * to catch this and send us the correct antenna explicitely.
394          */
395         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
396                ant->tx == ANTENNA_SW_DIVERSITY);
397
398         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
399         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
400
401         /*
402          * Configure the TX antenna.
403          */
404         switch (ant->tx) {
405         case ANTENNA_HW_DIVERSITY:
406                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
407                 break;
408         case ANTENNA_A:
409                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
410                 break;
411         case ANTENNA_B:
412         default:
413                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
414                 break;
415         }
416
417         /*
418          * Configure the RX antenna.
419          */
420         switch (ant->rx) {
421         case ANTENNA_HW_DIVERSITY:
422                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
423                 break;
424         case ANTENNA_A:
425                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
426                 break;
427         case ANTENNA_B:
428         default:
429                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
430                 break;
431         }
432
433         rt2400pci_bbp_write(rt2x00dev, 4, r4);
434         rt2400pci_bbp_write(rt2x00dev, 1, r1);
435 }
436
437 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
438                                      struct rf_channel *rf)
439 {
440         /*
441          * Switch on tuning bits.
442          */
443         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
444         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
445
446         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
447         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
448         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
449
450         /*
451          * RF2420 chipset don't need any additional actions.
452          */
453         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
454                 return;
455
456         /*
457          * For the RT2421 chipsets we need to write an invalid
458          * reference clock rate to activate auto_tune.
459          * After that we set the value back to the correct channel.
460          */
461         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
462         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
463         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
464
465         msleep(1);
466
467         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
468         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
469         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
470
471         msleep(1);
472
473         /*
474          * Switch off tuning bits.
475          */
476         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
477         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
478
479         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
480         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
481
482         /*
483          * Clear false CRC during channel switch.
484          */
485         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
486 }
487
488 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
489 {
490         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
491 }
492
493 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
494                                          struct rt2x00lib_conf *libconf)
495 {
496         u32 reg;
497
498         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
499         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
500                            libconf->conf->long_frame_max_tx_count);
501         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
502                            libconf->conf->short_frame_max_tx_count);
503         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
504 }
505
506 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
507                                       struct rt2x00lib_conf *libconf)
508 {
509         u32 reg;
510
511         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
512         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
513         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
514         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
515
516         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
517         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
518                            libconf->conf->beacon_int * 16);
519         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
520                            libconf->conf->beacon_int * 16);
521         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
522 }
523
524 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
525                                 struct rt2x00lib_conf *libconf)
526 {
527         enum dev_state state =
528             (libconf->conf->flags & IEEE80211_CONF_PS) ?
529                 STATE_SLEEP : STATE_AWAKE;
530         u32 reg;
531
532         if (state == STATE_SLEEP) {
533                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
534                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
535                                    (libconf->conf->beacon_int - 20) * 16);
536                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
537                                    libconf->conf->listen_interval - 1);
538
539                 /* We must first disable autowake before it can be enabled */
540                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
541                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
542
543                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
544                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
545         }
546
547         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
548 }
549
550 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
551                              struct rt2x00lib_conf *libconf,
552                              const unsigned int flags)
553 {
554         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
555                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
556         if (flags & IEEE80211_CONF_CHANGE_POWER)
557                 rt2400pci_config_txpower(rt2x00dev,
558                                          libconf->conf->power_level);
559         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
560                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
561         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
562                 rt2400pci_config_duration(rt2x00dev, libconf);
563         if (flags & IEEE80211_CONF_CHANGE_PS)
564                 rt2400pci_config_ps(rt2x00dev, libconf);
565 }
566
567 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
568                                 const int cw_min, const int cw_max)
569 {
570         u32 reg;
571
572         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
573         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
574         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
575         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
576 }
577
578 /*
579  * Link tuning
580  */
581 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
582                                  struct link_qual *qual)
583 {
584         u32 reg;
585         u8 bbp;
586
587         /*
588          * Update FCS error count from register.
589          */
590         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
591         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
592
593         /*
594          * Update False CCA count from register.
595          */
596         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
597         qual->false_cca = bbp;
598 }
599
600 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
601                                      struct link_qual *qual, u8 vgc_level)
602 {
603         rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
604         qual->vgc_level = vgc_level;
605         qual->vgc_level_reg = vgc_level;
606 }
607
608 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
609                                   struct link_qual *qual)
610 {
611         rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
612 }
613
614 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
615                                  struct link_qual *qual, const u32 count)
616 {
617         /*
618          * The link tuner should not run longer then 60 seconds,
619          * and should run once every 2 seconds.
620          */
621         if (count > 60 || !(count & 1))
622                 return;
623
624         /*
625          * Base r13 link tuning on the false cca count.
626          */
627         if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
628                 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
629         else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
630                 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
631 }
632
633 /*
634  * Initialization functions.
635  */
636 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
637 {
638         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
639         u32 word;
640
641         if (entry->queue->qid == QID_RX) {
642                 rt2x00_desc_read(entry_priv->desc, 0, &word);
643
644                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
645         } else {
646                 rt2x00_desc_read(entry_priv->desc, 0, &word);
647
648                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
649                         rt2x00_get_field32(word, TXD_W0_VALID));
650         }
651 }
652
653 static void rt2400pci_clear_entry(struct queue_entry *entry)
654 {
655         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
656         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
657         u32 word;
658
659         if (entry->queue->qid == QID_RX) {
660                 rt2x00_desc_read(entry_priv->desc, 2, &word);
661                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
662                 rt2x00_desc_write(entry_priv->desc, 2, word);
663
664                 rt2x00_desc_read(entry_priv->desc, 1, &word);
665                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
666                 rt2x00_desc_write(entry_priv->desc, 1, word);
667
668                 rt2x00_desc_read(entry_priv->desc, 0, &word);
669                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
670                 rt2x00_desc_write(entry_priv->desc, 0, word);
671         } else {
672                 rt2x00_desc_read(entry_priv->desc, 0, &word);
673                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
674                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
675                 rt2x00_desc_write(entry_priv->desc, 0, word);
676         }
677 }
678
679 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
680 {
681         struct queue_entry_priv_pci *entry_priv;
682         u32 reg;
683
684         /*
685          * Initialize registers.
686          */
687         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
688         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
689         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
690         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
691         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
692         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
693
694         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
695         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
696         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
697                            entry_priv->desc_dma);
698         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
699
700         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
701         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
702         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
703                            entry_priv->desc_dma);
704         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
705
706         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
707         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
708         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
709                            entry_priv->desc_dma);
710         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
711
712         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
713         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
714         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
715                            entry_priv->desc_dma);
716         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
717
718         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
719         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
720         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
721         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
722
723         entry_priv = rt2x00dev->rx->entries[0].priv_data;
724         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
725         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
726                            entry_priv->desc_dma);
727         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
728
729         return 0;
730 }
731
732 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
733 {
734         u32 reg;
735
736         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
737         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
738         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
739         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
740
741         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
742         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
743         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
744         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
745         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
746
747         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
748         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
749                            (rt2x00dev->rx->data_size / 128));
750         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
751
752         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
753         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
754         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
755         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
756         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
757         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
758         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
759         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
760         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
761         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
762
763         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
764
765         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
766         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
767         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
768         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
769         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
770         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
771
772         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
773         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
774         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
775         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
776         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
777         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
778         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
779         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
780
781         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
782
783         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
784                 return -EBUSY;
785
786         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
787         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
788
789         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
790         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
791         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
792
793         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
794         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
795         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
796         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
797         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
798         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
799
800         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
801         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
802         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
803         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
804         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
805
806         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
807         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
808         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
809         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
810
811         /*
812          * We must clear the FCS and FIFO error count.
813          * These registers are cleared on read,
814          * so we may pass a useless variable to store the value.
815          */
816         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
817         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
818
819         return 0;
820 }
821
822 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
823 {
824         unsigned int i;
825         u8 value;
826
827         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
828                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
829                 if ((value != 0xff) && (value != 0x00))
830                         return 0;
831                 udelay(REGISTER_BUSY_DELAY);
832         }
833
834         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
835         return -EACCES;
836 }
837
838 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
839 {
840         unsigned int i;
841         u16 eeprom;
842         u8 reg_id;
843         u8 value;
844
845         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
846                 return -EACCES;
847
848         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
849         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
850         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
851         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
852         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
853         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
854         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
855         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
856         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
857         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
858         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
859         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
860         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
861         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
862
863         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
864                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
865
866                 if (eeprom != 0xffff && eeprom != 0x0000) {
867                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
868                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
869                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
870                 }
871         }
872
873         return 0;
874 }
875
876 /*
877  * Device state switch handlers.
878  */
879 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
880                                 enum dev_state state)
881 {
882         u32 reg;
883
884         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
885         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
886                            (state == STATE_RADIO_RX_OFF) ||
887                            (state == STATE_RADIO_RX_OFF_LINK));
888         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
889 }
890
891 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
892                                  enum dev_state state)
893 {
894         int mask = (state == STATE_RADIO_IRQ_OFF);
895         u32 reg;
896
897         /*
898          * When interrupts are being enabled, the interrupt registers
899          * should clear the register to assure a clean state.
900          */
901         if (state == STATE_RADIO_IRQ_ON) {
902                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
903                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
904         }
905
906         /*
907          * Only toggle the interrupts bits we are going to use.
908          * Non-checked interrupt bits are disabled by default.
909          */
910         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
911         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
912         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
913         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
914         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
915         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
916         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
917 }
918
919 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
920 {
921         /*
922          * Initialize all registers.
923          */
924         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
925                      rt2400pci_init_registers(rt2x00dev) ||
926                      rt2400pci_init_bbp(rt2x00dev)))
927                 return -EIO;
928
929         return 0;
930 }
931
932 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
933 {
934         /*
935          * Disable power
936          */
937         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
938 }
939
940 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
941                                enum dev_state state)
942 {
943         u32 reg;
944         unsigned int i;
945         char put_to_sleep;
946         char bbp_state;
947         char rf_state;
948
949         put_to_sleep = (state != STATE_AWAKE);
950
951         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
952         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
953         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
954         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
955         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
956         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
957
958         /*
959          * Device is not guaranteed to be in the requested state yet.
960          * We must wait until the register indicates that the
961          * device has entered the correct state.
962          */
963         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
964                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
965                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
966                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
967                 if (bbp_state == state && rf_state == state)
968                         return 0;
969                 msleep(10);
970         }
971
972         return -EBUSY;
973 }
974
975 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
976                                       enum dev_state state)
977 {
978         int retval = 0;
979
980         switch (state) {
981         case STATE_RADIO_ON:
982                 retval = rt2400pci_enable_radio(rt2x00dev);
983                 break;
984         case STATE_RADIO_OFF:
985                 rt2400pci_disable_radio(rt2x00dev);
986                 break;
987         case STATE_RADIO_RX_ON:
988         case STATE_RADIO_RX_ON_LINK:
989         case STATE_RADIO_RX_OFF:
990         case STATE_RADIO_RX_OFF_LINK:
991                 rt2400pci_toggle_rx(rt2x00dev, state);
992                 break;
993         case STATE_RADIO_IRQ_ON:
994         case STATE_RADIO_IRQ_OFF:
995                 rt2400pci_toggle_irq(rt2x00dev, state);
996                 break;
997         case STATE_DEEP_SLEEP:
998         case STATE_SLEEP:
999         case STATE_STANDBY:
1000         case STATE_AWAKE:
1001                 retval = rt2400pci_set_state(rt2x00dev, state);
1002                 break;
1003         default:
1004                 retval = -ENOTSUPP;
1005                 break;
1006         }
1007
1008         if (unlikely(retval))
1009                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1010                       state, retval);
1011
1012         return retval;
1013 }
1014
1015 /*
1016  * TX descriptor initialization
1017  */
1018 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1019                                     struct sk_buff *skb,
1020                                     struct txentry_desc *txdesc)
1021 {
1022         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1023         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1024         __le32 *txd = skbdesc->desc;
1025         u32 word;
1026
1027         /*
1028          * Start writing the descriptor words.
1029          */
1030         rt2x00_desc_read(entry_priv->desc, 1, &word);
1031         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1032         rt2x00_desc_write(entry_priv->desc, 1, word);
1033
1034         rt2x00_desc_read(txd, 2, &word);
1035         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1036         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
1037         rt2x00_desc_write(txd, 2, word);
1038
1039         rt2x00_desc_read(txd, 3, &word);
1040         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1041         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1042         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1043         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1044         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1045         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1046         rt2x00_desc_write(txd, 3, word);
1047
1048         rt2x00_desc_read(txd, 4, &word);
1049         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1050         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1051         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1052         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1053         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1054         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1055         rt2x00_desc_write(txd, 4, word);
1056
1057         rt2x00_desc_read(txd, 0, &word);
1058         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1059         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1060         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1061                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1062         rt2x00_set_field32(&word, TXD_W0_ACK,
1063                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1064         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1065                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1066         rt2x00_set_field32(&word, TXD_W0_RTS,
1067                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1068         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1069         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1070                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1071         rt2x00_desc_write(txd, 0, word);
1072 }
1073
1074 /*
1075  * TX data initialization
1076  */
1077 static void rt2400pci_write_beacon(struct queue_entry *entry)
1078 {
1079         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1080         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1081         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1082         u32 word;
1083         u32 reg;
1084
1085         /*
1086          * Disable beaconing while we are reloading the beacon data,
1087          * otherwise we might be sending out invalid data.
1088          */
1089         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1090         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1091         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1092         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1093         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1094
1095         /*
1096          * Replace rt2x00lib allocated descriptor with the
1097          * pointer to the _real_ hardware descriptor.
1098          * After that, map the beacon to DMA and update the
1099          * descriptor.
1100          */
1101         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1102         skbdesc->desc = entry_priv->desc;
1103
1104         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1105
1106         rt2x00_desc_read(entry_priv->desc, 1, &word);
1107         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1108         rt2x00_desc_write(entry_priv->desc, 1, word);
1109 }
1110
1111 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1112                                     const enum data_queue_qid queue)
1113 {
1114         u32 reg;
1115
1116         if (queue == QID_BEACON) {
1117                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1118                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1119                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1120                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1121                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1122                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1123                 }
1124                 return;
1125         }
1126
1127         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1128         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1129         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1130         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1131         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1132 }
1133
1134 static void rt2400pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
1135                                     const enum data_queue_qid qid)
1136 {
1137         u32 reg;
1138
1139         if (qid == QID_BEACON) {
1140                 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1141         } else {
1142                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1143                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1144                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1145         }
1146 }
1147
1148 /*
1149  * RX control handlers
1150  */
1151 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1152                                   struct rxdone_entry_desc *rxdesc)
1153 {
1154         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1155         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1156         u32 word0;
1157         u32 word2;
1158         u32 word3;
1159         u32 word4;
1160         u64 tsf;
1161         u32 rx_low;
1162         u32 rx_high;
1163
1164         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1165         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1166         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1167         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1168
1169         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1170                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1171         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1172                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1173
1174         /*
1175          * We only get the lower 32bits from the timestamp,
1176          * to get the full 64bits we must complement it with
1177          * the timestamp from get_tsf().
1178          * Note that when a wraparound of the lower 32bits
1179          * has occurred between the frame arrival and the get_tsf()
1180          * call, we must decrease the higher 32bits with 1 to get
1181          * to correct value.
1182          */
1183         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1184         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1185         rx_high = upper_32_bits(tsf);
1186
1187         if ((u32)tsf <= rx_low)
1188                 rx_high--;
1189
1190         /*
1191          * Obtain the status about this packet.
1192          * The signal is the PLCP value, and needs to be stripped
1193          * of the preamble bit (0x08).
1194          */
1195         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1196         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1197         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1198             entry->queue->rt2x00dev->rssi_offset;
1199         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1200
1201         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1202         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1203                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1204 }
1205
1206 /*
1207  * Interrupt functions.
1208  */
1209 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1210                              const enum data_queue_qid queue_idx)
1211 {
1212         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1213         struct queue_entry_priv_pci *entry_priv;
1214         struct queue_entry *entry;
1215         struct txdone_entry_desc txdesc;
1216         u32 word;
1217
1218         while (!rt2x00queue_empty(queue)) {
1219                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1220                 entry_priv = entry->priv_data;
1221                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1222
1223                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1224                     !rt2x00_get_field32(word, TXD_W0_VALID))
1225                         break;
1226
1227                 /*
1228                  * Obtain the status about this packet.
1229                  */
1230                 txdesc.flags = 0;
1231                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1232                 case 0: /* Success */
1233                 case 1: /* Success with retry */
1234                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1235                         break;
1236                 case 2: /* Failure, excessive retries */
1237                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1238                         /* Don't break, this is a failed frame! */
1239                 default: /* Failure */
1240                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1241                 }
1242                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1243
1244                 rt2x00lib_txdone(entry, &txdesc);
1245         }
1246 }
1247
1248 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1249 {
1250         struct rt2x00_dev *rt2x00dev = dev_instance;
1251         u32 reg;
1252
1253         /*
1254          * Get the interrupt sources & saved to local variable.
1255          * Write register value back to clear pending interrupts.
1256          */
1257         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1258         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1259
1260         if (!reg)
1261                 return IRQ_NONE;
1262
1263         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1264                 return IRQ_HANDLED;
1265
1266         /*
1267          * Handle interrupts, walk through all bits
1268          * and run the tasks, the bits are checked in order of
1269          * priority.
1270          */
1271
1272         /*
1273          * 1 - Beacon timer expired interrupt.
1274          */
1275         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1276                 rt2x00lib_beacondone(rt2x00dev);
1277
1278         /*
1279          * 2 - Rx ring done interrupt.
1280          */
1281         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1282                 rt2x00pci_rxdone(rt2x00dev);
1283
1284         /*
1285          * 3 - Atim ring transmit done interrupt.
1286          */
1287         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1288                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1289
1290         /*
1291          * 4 - Priority ring transmit done interrupt.
1292          */
1293         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1294                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1295
1296         /*
1297          * 5 - Tx ring transmit done interrupt.
1298          */
1299         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1300                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1301
1302         return IRQ_HANDLED;
1303 }
1304
1305 /*
1306  * Device probe functions.
1307  */
1308 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1309 {
1310         struct eeprom_93cx6 eeprom;
1311         u32 reg;
1312         u16 word;
1313         u8 *mac;
1314
1315         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1316
1317         eeprom.data = rt2x00dev;
1318         eeprom.register_read = rt2400pci_eepromregister_read;
1319         eeprom.register_write = rt2400pci_eepromregister_write;
1320         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1321             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1322         eeprom.reg_data_in = 0;
1323         eeprom.reg_data_out = 0;
1324         eeprom.reg_data_clock = 0;
1325         eeprom.reg_chip_select = 0;
1326
1327         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1328                                EEPROM_SIZE / sizeof(u16));
1329
1330         /*
1331          * Start validation of the data that has been read.
1332          */
1333         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1334         if (!is_valid_ether_addr(mac)) {
1335                 random_ether_addr(mac);
1336                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1337         }
1338
1339         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1340         if (word == 0xffff) {
1341                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1342                 return -EINVAL;
1343         }
1344
1345         return 0;
1346 }
1347
1348 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1349 {
1350         u32 reg;
1351         u16 value;
1352         u16 eeprom;
1353
1354         /*
1355          * Read EEPROM word for configuration.
1356          */
1357         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1358
1359         /*
1360          * Identify RF chipset.
1361          */
1362         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1363         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1364         rt2x00_set_chip_rf(rt2x00dev, value, reg);
1365
1366         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1367             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1368                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1369                 return -ENODEV;
1370         }
1371
1372         /*
1373          * Identify default antenna configuration.
1374          */
1375         rt2x00dev->default_ant.tx =
1376             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1377         rt2x00dev->default_ant.rx =
1378             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1379
1380         /*
1381          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1382          * I am not 100% sure about this, but the legacy drivers do not
1383          * indicate antenna swapping in software is required when
1384          * diversity is enabled.
1385          */
1386         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1387                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1388         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1389                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1390
1391         /*
1392          * Store led mode, for correct led behaviour.
1393          */
1394 #ifdef CONFIG_RT2X00_LIB_LEDS
1395         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1396
1397         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1398         if (value == LED_MODE_TXRX_ACTIVITY ||
1399             value == LED_MODE_DEFAULT ||
1400             value == LED_MODE_ASUS)
1401                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1402                                    LED_TYPE_ACTIVITY);
1403 #endif /* CONFIG_RT2X00_LIB_LEDS */
1404
1405         /*
1406          * Detect if this device has an hardware controlled radio.
1407          */
1408 #ifdef CONFIG_RT2X00_LIB_RFKILL
1409         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1410                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1411 #endif /* CONFIG_RT2X00_LIB_RFKILL */
1412
1413         /*
1414          * Check if the BBP tuning should be enabled.
1415          */
1416         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1417                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1418
1419         return 0;
1420 }
1421
1422 /*
1423  * RF value list for RF2420 & RF2421
1424  * Supports: 2.4 GHz
1425  */
1426 static const struct rf_channel rf_vals_b[] = {
1427         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1428         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1429         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1430         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1431         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1432         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1433         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1434         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1435         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1436         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1437         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1438         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1439         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1440         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1441 };
1442
1443 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1444 {
1445         struct hw_mode_spec *spec = &rt2x00dev->spec;
1446         struct channel_info *info;
1447         char *tx_power;
1448         unsigned int i;
1449
1450         /*
1451          * Initialize all hw fields.
1452          */
1453         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1454                                IEEE80211_HW_SIGNAL_DBM |
1455                                IEEE80211_HW_SUPPORTS_PS |
1456                                IEEE80211_HW_PS_NULLFUNC_STACK;
1457         rt2x00dev->hw->extra_tx_headroom = 0;
1458
1459         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1460         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1461                                 rt2x00_eeprom_addr(rt2x00dev,
1462                                                    EEPROM_MAC_ADDR_0));
1463
1464         /*
1465          * Initialize hw_mode information.
1466          */
1467         spec->supported_bands = SUPPORT_BAND_2GHZ;
1468         spec->supported_rates = SUPPORT_RATE_CCK;
1469
1470         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1471         spec->channels = rf_vals_b;
1472
1473         /*
1474          * Create channel information array
1475          */
1476         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1477         if (!info)
1478                 return -ENOMEM;
1479
1480         spec->channels_info = info;
1481
1482         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1483         for (i = 0; i < 14; i++)
1484                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1485
1486         return 0;
1487 }
1488
1489 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1490 {
1491         int retval;
1492
1493         /*
1494          * Allocate eeprom data.
1495          */
1496         retval = rt2400pci_validate_eeprom(rt2x00dev);
1497         if (retval)
1498                 return retval;
1499
1500         retval = rt2400pci_init_eeprom(rt2x00dev);
1501         if (retval)
1502                 return retval;
1503
1504         /*
1505          * Initialize hw specifications.
1506          */
1507         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1508         if (retval)
1509                 return retval;
1510
1511         /*
1512          * This device requires the atim queue and DMA-mapped skbs.
1513          */
1514         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1515         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1516
1517         /*
1518          * Set the rssi offset.
1519          */
1520         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1521
1522         return 0;
1523 }
1524
1525 /*
1526  * IEEE80211 stack callback functions.
1527  */
1528 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1529                              const struct ieee80211_tx_queue_params *params)
1530 {
1531         struct rt2x00_dev *rt2x00dev = hw->priv;
1532
1533         /*
1534          * We don't support variating cw_min and cw_max variables
1535          * per queue. So by default we only configure the TX queue,
1536          * and ignore all other configurations.
1537          */
1538         if (queue != 0)
1539                 return -EINVAL;
1540
1541         if (rt2x00mac_conf_tx(hw, queue, params))
1542                 return -EINVAL;
1543
1544         /*
1545          * Write configuration to register.
1546          */
1547         rt2400pci_config_cw(rt2x00dev,
1548                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1549
1550         return 0;
1551 }
1552
1553 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1554 {
1555         struct rt2x00_dev *rt2x00dev = hw->priv;
1556         u64 tsf;
1557         u32 reg;
1558
1559         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1560         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1561         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1562         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1563
1564         return tsf;
1565 }
1566
1567 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1568 {
1569         struct rt2x00_dev *rt2x00dev = hw->priv;
1570         u32 reg;
1571
1572         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1573         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1574 }
1575
1576 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1577         .tx                     = rt2x00mac_tx,
1578         .start                  = rt2x00mac_start,
1579         .stop                   = rt2x00mac_stop,
1580         .add_interface          = rt2x00mac_add_interface,
1581         .remove_interface       = rt2x00mac_remove_interface,
1582         .config                 = rt2x00mac_config,
1583         .configure_filter       = rt2x00mac_configure_filter,
1584         .get_stats              = rt2x00mac_get_stats,
1585         .bss_info_changed       = rt2x00mac_bss_info_changed,
1586         .conf_tx                = rt2400pci_conf_tx,
1587         .get_tx_stats           = rt2x00mac_get_tx_stats,
1588         .get_tsf                = rt2400pci_get_tsf,
1589         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1590 };
1591
1592 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1593         .irq_handler            = rt2400pci_interrupt,
1594         .probe_hw               = rt2400pci_probe_hw,
1595         .initialize             = rt2x00pci_initialize,
1596         .uninitialize           = rt2x00pci_uninitialize,
1597         .get_entry_state        = rt2400pci_get_entry_state,
1598         .clear_entry            = rt2400pci_clear_entry,
1599         .set_device_state       = rt2400pci_set_device_state,
1600         .rfkill_poll            = rt2400pci_rfkill_poll,
1601         .link_stats             = rt2400pci_link_stats,
1602         .reset_tuner            = rt2400pci_reset_tuner,
1603         .link_tuner             = rt2400pci_link_tuner,
1604         .write_tx_desc          = rt2400pci_write_tx_desc,
1605         .write_tx_data          = rt2x00pci_write_tx_data,
1606         .write_beacon           = rt2400pci_write_beacon,
1607         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1608         .kill_tx_queue          = rt2400pci_kill_tx_queue,
1609         .fill_rxdone            = rt2400pci_fill_rxdone,
1610         .config_filter          = rt2400pci_config_filter,
1611         .config_intf            = rt2400pci_config_intf,
1612         .config_erp             = rt2400pci_config_erp,
1613         .config_ant             = rt2400pci_config_ant,
1614         .config                 = rt2400pci_config,
1615 };
1616
1617 static const struct data_queue_desc rt2400pci_queue_rx = {
1618         .entry_num              = RX_ENTRIES,
1619         .data_size              = DATA_FRAME_SIZE,
1620         .desc_size              = RXD_DESC_SIZE,
1621         .priv_size              = sizeof(struct queue_entry_priv_pci),
1622 };
1623
1624 static const struct data_queue_desc rt2400pci_queue_tx = {
1625         .entry_num              = TX_ENTRIES,
1626         .data_size              = DATA_FRAME_SIZE,
1627         .desc_size              = TXD_DESC_SIZE,
1628         .priv_size              = sizeof(struct queue_entry_priv_pci),
1629 };
1630
1631 static const struct data_queue_desc rt2400pci_queue_bcn = {
1632         .entry_num              = BEACON_ENTRIES,
1633         .data_size              = MGMT_FRAME_SIZE,
1634         .desc_size              = TXD_DESC_SIZE,
1635         .priv_size              = sizeof(struct queue_entry_priv_pci),
1636 };
1637
1638 static const struct data_queue_desc rt2400pci_queue_atim = {
1639         .entry_num              = ATIM_ENTRIES,
1640         .data_size              = DATA_FRAME_SIZE,
1641         .desc_size              = TXD_DESC_SIZE,
1642         .priv_size              = sizeof(struct queue_entry_priv_pci),
1643 };
1644
1645 static const struct rt2x00_ops rt2400pci_ops = {
1646         .name           = KBUILD_MODNAME,
1647         .max_sta_intf   = 1,
1648         .max_ap_intf    = 1,
1649         .eeprom_size    = EEPROM_SIZE,
1650         .rf_size        = RF_SIZE,
1651         .tx_queues      = NUM_TX_QUEUES,
1652         .rx             = &rt2400pci_queue_rx,
1653         .tx             = &rt2400pci_queue_tx,
1654         .bcn            = &rt2400pci_queue_bcn,
1655         .atim           = &rt2400pci_queue_atim,
1656         .lib            = &rt2400pci_rt2x00_ops,
1657         .hw             = &rt2400pci_mac80211_ops,
1658 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1659         .debugfs        = &rt2400pci_rt2x00debug,
1660 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1661 };
1662
1663 /*
1664  * RT2400pci module information.
1665  */
1666 static struct pci_device_id rt2400pci_device_table[] = {
1667         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1668         { 0, }
1669 };
1670
1671 MODULE_AUTHOR(DRV_PROJECT);
1672 MODULE_VERSION(DRV_VERSION);
1673 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1674 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1675 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1676 MODULE_LICENSE("GPL");
1677
1678 static struct pci_driver rt2400pci_driver = {
1679         .name           = KBUILD_MODNAME,
1680         .id_table       = rt2400pci_device_table,
1681         .probe          = rt2x00pci_probe,
1682         .remove         = __devexit_p(rt2x00pci_remove),
1683         .suspend        = rt2x00pci_suspend,
1684         .resume         = rt2x00pci_resume,
1685 };
1686
1687 static int __init rt2400pci_init(void)
1688 {
1689         return pci_register_driver(&rt2400pci_driver);
1690 }
1691
1692 static void __exit rt2400pci_exit(void)
1693 {
1694         pci_unregister_driver(&rt2400pci_driver);
1695 }
1696
1697 module_init(rt2400pci_init);
1698 module_exit(rt2400pci_exit);