[RT2x00]: add driver for Ralink wireless hardware
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2400pci
23         Abstract: rt2400pci device specific routines.
24         Supported chipsets: RT2460.
25  */
26
27 /*
28  * Set enviroment defines for rt2x00.h
29  */
30 #define DRV_NAME "rt2400pci"
31
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/eeprom_93cx6.h>
39
40 #include "rt2x00.h"
41 #include "rt2x00pci.h"
42 #include "rt2400pci.h"
43
44 /*
45  * Register access.
46  * All access to the CSR registers will go through the methods
47  * rt2x00pci_register_read and rt2x00pci_register_write.
48  * BBP and RF register require indirect register access,
49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
50  * These indirect registers work with busy bits,
51  * and we will try maximal REGISTER_BUSY_COUNT times to access
52  * the register while taking a REGISTER_BUSY_DELAY us delay
53  * between each attampt. When the busy bit is still set at that time,
54  * the access attempt is considered to have failed,
55  * and we will print an error.
56  */
57 static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
58 {
59         u32 reg;
60         unsigned int i;
61
62         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
63                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
64                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
65                         break;
66                 udelay(REGISTER_BUSY_DELAY);
67         }
68
69         return reg;
70 }
71
72 static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
73                                 const unsigned int word, const u8 value)
74 {
75         u32 reg;
76
77         /*
78          * Wait until the BBP becomes ready.
79          */
80         reg = rt2400pci_bbp_check(rt2x00dev);
81         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
82                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
83                 return;
84         }
85
86         /*
87          * Write the data into the BBP.
88          */
89         reg = 0;
90         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
91         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
92         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
93         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
94
95         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
96 }
97
98 static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
99                                const unsigned int word, u8 *value)
100 {
101         u32 reg;
102
103         /*
104          * Wait until the BBP becomes ready.
105          */
106         reg = rt2400pci_bbp_check(rt2x00dev);
107         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
108                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
109                 return;
110         }
111
112         /*
113          * Write the request into the BBP.
114          */
115         reg = 0;
116         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
117         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
118         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
119
120         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
121
122         /*
123          * Wait until the BBP becomes ready.
124          */
125         reg = rt2400pci_bbp_check(rt2x00dev);
126         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
127                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
128                 *value = 0xff;
129                 return;
130         }
131
132         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
133 }
134
135 static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
136                                const unsigned int word, const u32 value)
137 {
138         u32 reg;
139         unsigned int i;
140
141         if (!word)
142                 return;
143
144         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
145                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
146                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
147                         goto rf_write;
148                 udelay(REGISTER_BUSY_DELAY);
149         }
150
151         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
152         return;
153
154 rf_write:
155         reg = 0;
156         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
157         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
158         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
159         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
160
161         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
162         rt2x00_rf_write(rt2x00dev, word, value);
163 }
164
165 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
166 {
167         struct rt2x00_dev *rt2x00dev = eeprom->data;
168         u32 reg;
169
170         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
171
172         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
173         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
174         eeprom->reg_data_clock =
175             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
176         eeprom->reg_chip_select =
177             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
178 }
179
180 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
181 {
182         struct rt2x00_dev *rt2x00dev = eeprom->data;
183         u32 reg = 0;
184
185         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
186         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
187         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
188                            !!eeprom->reg_data_clock);
189         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
190                            !!eeprom->reg_chip_select);
191
192         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
193 }
194
195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
196 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
197
198 static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev,
199                                const unsigned int word, u32 *data)
200 {
201         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
202 }
203
204 static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev,
205                                 const unsigned int word, u32 data)
206 {
207         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
208 }
209
210 static const struct rt2x00debug rt2400pci_rt2x00debug = {
211         .owner  = THIS_MODULE,
212         .csr    = {
213                 .read           = rt2400pci_read_csr,
214                 .write          = rt2400pci_write_csr,
215                 .word_size      = sizeof(u32),
216                 .word_count     = CSR_REG_SIZE / sizeof(u32),
217         },
218         .eeprom = {
219                 .read           = rt2x00_eeprom_read,
220                 .write          = rt2x00_eeprom_write,
221                 .word_size      = sizeof(u16),
222                 .word_count     = EEPROM_SIZE / sizeof(u16),
223         },
224         .bbp    = {
225                 .read           = rt2400pci_bbp_read,
226                 .write          = rt2400pci_bbp_write,
227                 .word_size      = sizeof(u8),
228                 .word_count     = BBP_SIZE / sizeof(u8),
229         },
230         .rf     = {
231                 .read           = rt2x00_rf_read,
232                 .write          = rt2400pci_rf_write,
233                 .word_size      = sizeof(u32),
234                 .word_count     = RF_SIZE / sizeof(u32),
235         },
236 };
237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
238
239 #ifdef CONFIG_RT2400PCI_RFKILL
240 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
241 {
242         u32 reg;
243
244         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
245         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
246 }
247 #endif /* CONFIG_RT2400PCI_RFKILL */
248
249 /*
250  * Configuration handlers.
251  */
252 static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
253 {
254         __le32 reg[2];
255
256         memset(&reg, 0, sizeof(reg));
257         memcpy(&reg, addr, ETH_ALEN);
258
259         /*
260          * The MAC address is passed to us as an array of bytes,
261          * that array is little endian, so no need for byte ordering.
262          */
263         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, &reg, sizeof(reg));
264 }
265
266 static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
267 {
268         __le32 reg[2];
269
270         memset(&reg, 0, sizeof(reg));
271         memcpy(&reg, bssid, ETH_ALEN);
272
273         /*
274          * The BSSID is passed to us as an array of bytes,
275          * that array is little endian, so no need for byte ordering.
276          */
277         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, &reg, sizeof(reg));
278 }
279
280 static void rt2400pci_config_packet_filter(struct rt2x00_dev *rt2x00dev,
281                                            const unsigned int filter)
282 {
283         int promisc = !!(filter & IFF_PROMISC);
284         u32 reg;
285
286         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
287         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME, !promisc);
288         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
289 }
290
291 static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, int type)
292 {
293         u32 reg;
294
295         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
296
297         /*
298          * Apply hardware packet filter.
299          */
300         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
301
302         if (!is_monitor_present(&rt2x00dev->interface) &&
303             (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_STA))
304                 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 1);
305         else
306                 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS, 0);
307
308         /*
309          * If there is a non-monitor interface present
310          * the packet should be strict (even if a monitor interface is present!).
311          * When there is only 1 interface present which is in monitor mode
312          * we should start accepting _all_ frames.
313          */
314         if (is_interface_present(&rt2x00dev->interface)) {
315                 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, 1);
316                 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 1);
317                 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 1);
318                 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
319         } else if (is_monitor_present(&rt2x00dev->interface)) {
320                 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC, 0);
321                 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL, 0);
322                 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL, 0);
323                 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 0);
324         }
325
326         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
327
328         /*
329          * Enable beacon config
330          */
331         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
332         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
333                            PREAMBLE + get_duration(IEEE80211_HEADER, 2));
334         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
335
336         /*
337          * Enable synchronisation.
338          */
339         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
340         if (is_interface_present(&rt2x00dev->interface)) {
341                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
342                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
343         }
344
345         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
346         if (type == IEEE80211_IF_TYPE_IBSS || type == IEEE80211_IF_TYPE_AP)
347                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
348         else if (type == IEEE80211_IF_TYPE_STA)
349                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
350         else if (is_monitor_present(&rt2x00dev->interface) &&
351                  !is_interface_present(&rt2x00dev->interface))
352                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
353
354         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
355 }
356
357 static void rt2400pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
358 {
359         struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
360         u32 reg;
361         u32 preamble;
362         u16 value;
363
364         if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
365                 preamble = SHORT_PREAMBLE;
366         else
367                 preamble = PREAMBLE;
368
369         reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
370         rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
371
372         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
373         value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
374                  SHORT_DIFS : DIFS) +
375             PLCP + preamble + get_duration(ACK_SIZE, 10);
376         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
377         value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
378         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
379         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
380
381         preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
382
383         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
384         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
385         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
386         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
387         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
388
389         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
390         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
391         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
392         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
393         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
394
395         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
396         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
397         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
398         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
399         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
400
401         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
402         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
403         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
404         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
405         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
406 }
407
408 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
409                                      const int phymode)
410 {
411         struct ieee80211_hw_mode *mode;
412         struct ieee80211_rate *rate;
413
414         rt2x00dev->curr_hwmode = HWMODE_B;
415
416         mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
417         rate = &mode->rates[mode->num_rates - 1];
418
419         rt2400pci_config_rate(rt2x00dev, rate->val2);
420 }
421
422 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
423                                      const int index, const int channel)
424 {
425         struct rf_channel reg;
426
427         /*
428          * Fill rf_reg structure.
429          */
430         memcpy(&reg, &rt2x00dev->spec.channels[index], sizeof(reg));
431
432         /*
433          * Switch on tuning bits.
434          */
435         rt2x00_set_field32(&reg.rf1, RF1_TUNER, 1);
436         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 1);
437
438         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
439         rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
440         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
441
442         /*
443          * RF2420 chipset don't need any additional actions.
444          */
445         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
446                 return;
447
448         /*
449          * For the RT2421 chipsets we need to write an invalid
450          * reference clock rate to activate auto_tune.
451          * After that we set the value back to the correct channel.
452          */
453         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
454         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
455         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
456
457         msleep(1);
458
459         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
460         rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
461         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
462
463         msleep(1);
464
465         /*
466          * Switch off tuning bits.
467          */
468         rt2x00_set_field32(&reg.rf1, RF1_TUNER, 0);
469         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 0);
470
471         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
472         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
473
474         /*
475          * Clear false CRC during channel switch.
476          */
477         rt2x00pci_register_read(rt2x00dev, CNT0, &reg.rf1);
478 }
479
480 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
481 {
482         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
483 }
484
485 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
486                                      int antenna_tx, int antenna_rx)
487 {
488         u8 r1;
489         u8 r4;
490
491         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
492         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
493
494         /*
495          * Configure the TX antenna.
496          */
497         switch (antenna_tx) {
498         case ANTENNA_SW_DIVERSITY:
499         case ANTENNA_HW_DIVERSITY:
500                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
501                 break;
502         case ANTENNA_A:
503                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
504                 break;
505         case ANTENNA_B:
506                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
507                 break;
508         }
509
510         /*
511          * Configure the RX antenna.
512          */
513         switch (antenna_rx) {
514         case ANTENNA_SW_DIVERSITY:
515         case ANTENNA_HW_DIVERSITY:
516                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
517                 break;
518         case ANTENNA_A:
519                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
520                 break;
521         case ANTENNA_B:
522                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
523                 break;
524         }
525
526         rt2400pci_bbp_write(rt2x00dev, 4, r4);
527         rt2400pci_bbp_write(rt2x00dev, 1, r1);
528 }
529
530 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
531                                       int short_slot_time, int beacon_int)
532 {
533         u32 reg;
534
535         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
536         rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
537                            short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
538         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
539
540         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
541         rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
542         rt2x00_set_field32(&reg, CSR18_PIFS,
543                            short_slot_time ? SHORT_PIFS : PIFS);
544         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
545
546         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
547         rt2x00_set_field32(&reg, CSR19_DIFS,
548                            short_slot_time ? SHORT_DIFS : DIFS);
549         rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
550         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
551
552         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
553         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
554         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
555         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
556
557         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
558         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
559         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
560         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
561 }
562
563 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
564                              const unsigned int flags,
565                              struct ieee80211_conf *conf)
566 {
567         int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
568
569         if (flags & CONFIG_UPDATE_PHYMODE)
570                 rt2400pci_config_phymode(rt2x00dev, conf->phymode);
571         if (flags & CONFIG_UPDATE_CHANNEL)
572                 rt2400pci_config_channel(rt2x00dev, conf->channel_val,
573                                          conf->channel);
574         if (flags & CONFIG_UPDATE_TXPOWER)
575                 rt2400pci_config_txpower(rt2x00dev, conf->power_level);
576         if (flags & CONFIG_UPDATE_ANTENNA)
577                 rt2400pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
578                                          conf->antenna_sel_rx);
579         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
580                 rt2400pci_config_duration(rt2x00dev, short_slot_time,
581                                           conf->beacon_int);
582 }
583
584 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
585                                 struct ieee80211_tx_queue_params *params)
586 {
587         u32 reg;
588
589         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
590         rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
591         rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
592         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
593 }
594
595 /*
596  * LED functions.
597  */
598 static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
599 {
600         u32 reg;
601
602         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
603
604         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
605         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
606
607         if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
608                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
609                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
610         } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
611                 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
612                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
613         } else {
614                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
615                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
616         }
617
618         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
619 }
620
621 static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
622 {
623         u32 reg;
624
625         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
626         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
627         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
628         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
629 }
630
631 /*
632  * Link tuning
633  */
634 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev)
635 {
636         u32 reg;
637         u8 bbp;
638
639         /*
640          * Update FCS error count from register.
641          */
642         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
643         rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
644
645         /*
646          * Update False CCA count from register.
647          */
648         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
649         rt2x00dev->link.false_cca = bbp;
650 }
651
652 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
653 {
654         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
655         rt2x00dev->link.vgc_level = 0x08;
656 }
657
658 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
659 {
660         u8 reg;
661
662         /*
663          * The link tuner should not run longer then 60 seconds,
664          * and should run once every 2 seconds.
665          */
666         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
667                 return;
668
669         /*
670          * Base r13 link tuning on the false cca count.
671          */
672         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
673
674         if (rt2x00dev->link.false_cca > 512 && reg < 0x20) {
675                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
676                 rt2x00dev->link.vgc_level = reg;
677         } else if (rt2x00dev->link.false_cca < 100 && reg > 0x08) {
678                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
679                 rt2x00dev->link.vgc_level = reg;
680         }
681 }
682
683 /*
684  * Initialization functions.
685  */
686 static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
687 {
688         struct data_ring *ring = rt2x00dev->rx;
689         struct data_desc *rxd;
690         unsigned int i;
691         u32 word;
692
693         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
694
695         for (i = 0; i < ring->stats.limit; i++) {
696                 rxd = ring->entry[i].priv;
697
698                 rt2x00_desc_read(rxd, 2, &word);
699                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
700                                    ring->data_size);
701                 rt2x00_desc_write(rxd, 2, word);
702
703                 rt2x00_desc_read(rxd, 1, &word);
704                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
705                                    ring->entry[i].data_dma);
706                 rt2x00_desc_write(rxd, 1, word);
707
708                 rt2x00_desc_read(rxd, 0, &word);
709                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
710                 rt2x00_desc_write(rxd, 0, word);
711         }
712
713         rt2x00_ring_index_clear(rt2x00dev->rx);
714 }
715
716 static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
717 {
718         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
719         struct data_desc *txd;
720         unsigned int i;
721         u32 word;
722
723         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
724
725         for (i = 0; i < ring->stats.limit; i++) {
726                 txd = ring->entry[i].priv;
727
728                 rt2x00_desc_read(txd, 1, &word);
729                 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
730                                    ring->entry[i].data_dma);
731                 rt2x00_desc_write(txd, 1, word);
732
733                 rt2x00_desc_read(txd, 2, &word);
734                 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
735                                    ring->data_size);
736                 rt2x00_desc_write(txd, 2, word);
737
738                 rt2x00_desc_read(txd, 0, &word);
739                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
740                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
741                 rt2x00_desc_write(txd, 0, word);
742         }
743
744         rt2x00_ring_index_clear(ring);
745 }
746
747 static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
748 {
749         u32 reg;
750
751         /*
752          * Initialize rings.
753          */
754         rt2400pci_init_rxring(rt2x00dev);
755         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
756         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
757         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
758         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
759
760         /*
761          * Initialize registers.
762          */
763         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
764         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
765                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
766         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
767                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
768         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
769                            rt2x00dev->bcn[1].stats.limit);
770         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
771                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
772         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
773
774         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
775         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
776                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
777         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
778
779         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
780         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
781                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
782         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
783
784         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
785         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
786                            rt2x00dev->bcn[1].data_dma);
787         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
788
789         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
790         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
791                            rt2x00dev->bcn[0].data_dma);
792         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
793
794         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
795         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
796         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
797         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
798
799         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
800         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
801                            rt2x00dev->rx->data_dma);
802         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
803
804         return 0;
805 }
806
807 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
808 {
809         u32 reg;
810
811         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
812         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
813         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
814         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
815
816         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
817         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
818         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
819         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
820         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
821
822         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
823         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
824                            (rt2x00dev->rx->data_size / 128));
825         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
826
827         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
828
829         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
830         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
831         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
832         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
833         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
834         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
835
836         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
837         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
838         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
839         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
840         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
841         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
842         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
843         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
844
845         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
846
847         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
848                 return -EBUSY;
849
850         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
851         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
852
853         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
854         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
855         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
856
857         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
858         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
859         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
860         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
861         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
862         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
863
864         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
865         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
866         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
867         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
868         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
869
870         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
871         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
872         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
873         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
874
875         /*
876          * We must clear the FCS and FIFO error count.
877          * These registers are cleared on read,
878          * so we may pass a useless variable to store the value.
879          */
880         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
881         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
882
883         return 0;
884 }
885
886 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
887 {
888         unsigned int i;
889         u16 eeprom;
890         u8 reg_id;
891         u8 value;
892
893         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
894                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
895                 if ((value != 0xff) && (value != 0x00))
896                         goto continue_csr_init;
897                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
898                 udelay(REGISTER_BUSY_DELAY);
899         }
900
901         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
902         return -EACCES;
903
904 continue_csr_init:
905         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
906         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
907         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
908         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
909         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
910         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
911         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
912         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
913         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
914         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
915         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
916         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
917         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
918         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
919
920         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
921         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
922                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
923
924                 if (eeprom != 0xffff && eeprom != 0x0000) {
925                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
926                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
927                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
928                               reg_id, value);
929                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
930                 }
931         }
932         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
933
934         return 0;
935 }
936
937 /*
938  * Device state switch handlers.
939  */
940 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
941                                 enum dev_state state)
942 {
943         u32 reg;
944
945         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
946         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
947                            state == STATE_RADIO_RX_OFF);
948         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
949 }
950
951 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
952                                  enum dev_state state)
953 {
954         int mask = (state == STATE_RADIO_IRQ_OFF);
955         u32 reg;
956
957         /*
958          * When interrupts are being enabled, the interrupt registers
959          * should clear the register to assure a clean state.
960          */
961         if (state == STATE_RADIO_IRQ_ON) {
962                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
963                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
964         }
965
966         /*
967          * Only toggle the interrupts bits we are going to use.
968          * Non-checked interrupt bits are disabled by default.
969          */
970         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
971         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
972         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
973         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
974         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
975         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
976         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
977 }
978
979 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
980 {
981         /*
982          * Initialize all registers.
983          */
984         if (rt2400pci_init_rings(rt2x00dev) ||
985             rt2400pci_init_registers(rt2x00dev) ||
986             rt2400pci_init_bbp(rt2x00dev)) {
987                 ERROR(rt2x00dev, "Register initialization failed.\n");
988                 return -EIO;
989         }
990
991         /*
992          * Enable interrupts.
993          */
994         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
995
996         /*
997          * Enable LED
998          */
999         rt2400pci_enable_led(rt2x00dev);
1000
1001         return 0;
1002 }
1003
1004 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1005 {
1006         u32 reg;
1007
1008         /*
1009          * Disable LED
1010          */
1011         rt2400pci_disable_led(rt2x00dev);
1012
1013         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1014
1015         /*
1016          * Disable synchronisation.
1017          */
1018         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1019
1020         /*
1021          * Cancel RX and TX.
1022          */
1023         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1024         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1025         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1026
1027         /*
1028          * Disable interrupts.
1029          */
1030         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1031 }
1032
1033 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1034                                enum dev_state state)
1035 {
1036         u32 reg;
1037         unsigned int i;
1038         char put_to_sleep;
1039         char bbp_state;
1040         char rf_state;
1041
1042         put_to_sleep = (state != STATE_AWAKE);
1043
1044         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1045         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1046         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1047         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1048         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1049         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1050
1051         /*
1052          * Device is not guaranteed to be in the requested state yet.
1053          * We must wait until the register indicates that the
1054          * device has entered the correct state.
1055          */
1056         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1057                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1058                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1059                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1060                 if (bbp_state == state && rf_state == state)
1061                         return 0;
1062                 msleep(10);
1063         }
1064
1065         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1066                "current device state: bbp %d and rf %d.\n",
1067                state, bbp_state, rf_state);
1068
1069         return -EBUSY;
1070 }
1071
1072 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1073                                       enum dev_state state)
1074 {
1075         int retval = 0;
1076
1077         switch (state) {
1078         case STATE_RADIO_ON:
1079                 retval = rt2400pci_enable_radio(rt2x00dev);
1080                 break;
1081         case STATE_RADIO_OFF:
1082                 rt2400pci_disable_radio(rt2x00dev);
1083                 break;
1084         case STATE_RADIO_RX_ON:
1085         case STATE_RADIO_RX_OFF:
1086                 rt2400pci_toggle_rx(rt2x00dev, state);
1087                 break;
1088         case STATE_DEEP_SLEEP:
1089         case STATE_SLEEP:
1090         case STATE_STANDBY:
1091         case STATE_AWAKE:
1092                 retval = rt2400pci_set_state(rt2x00dev, state);
1093                 break;
1094         default:
1095                 retval = -ENOTSUPP;
1096                 break;
1097         }
1098
1099         return retval;
1100 }
1101
1102 /*
1103  * TX descriptor initialization
1104  */
1105 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1106                                     struct data_desc *txd,
1107                                     struct data_entry_desc *desc,
1108                                     struct ieee80211_hdr *ieee80211hdr,
1109                                     unsigned int length,
1110                                     struct ieee80211_tx_control *control)
1111 {
1112         u32 word;
1113         u32 signal = 0;
1114         u32 service = 0;
1115         u32 length_high = 0;
1116         u32 length_low = 0;
1117
1118         /*
1119          * The PLCP values should be treated as if they
1120          * were BBP values.
1121          */
1122         rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
1123         rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
1124         rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
1125
1126         rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
1127         rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
1128         rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
1129
1130         rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
1131         rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
1132         rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
1133
1134         rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
1135         rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
1136         rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
1137
1138         /*
1139          * Start writing the descriptor words.
1140          */
1141         rt2x00_desc_read(txd, 2, &word);
1142         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1143         rt2x00_desc_write(txd, 2, word);
1144
1145         rt2x00_desc_read(txd, 3, &word);
1146         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
1147         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
1148         rt2x00_desc_write(txd, 3, word);
1149
1150         rt2x00_desc_read(txd, 4, &word);
1151         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
1152         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
1153         rt2x00_desc_write(txd, 4, word);
1154
1155         rt2x00_desc_read(txd, 0, &word);
1156         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1157         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1158         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1159                            test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1160         rt2x00_set_field32(&word, TXD_W0_ACK,
1161                            !(control->flags & IEEE80211_TXCTL_NO_ACK));
1162         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1163                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1164         rt2x00_set_field32(&word, TXD_W0_RTS,
1165                            test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1166         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1167         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1168                            !!(control->flags &
1169                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1170         rt2x00_desc_write(txd, 0, word);
1171 }
1172
1173 /*
1174  * TX data initialization
1175  */
1176 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1177                                     unsigned int queue)
1178 {
1179         u32 reg;
1180
1181         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1182                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1183                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1184                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1185                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1186                 }
1187                 return;
1188         }
1189
1190         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1191         if (queue == IEEE80211_TX_QUEUE_DATA0)
1192                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1193         else if (queue == IEEE80211_TX_QUEUE_DATA1)
1194                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1195         else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1196                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1197         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1198 }
1199
1200 /*
1201  * RX control handlers
1202  */
1203 static int rt2400pci_fill_rxdone(struct data_entry *entry,
1204                                  int *signal, int *rssi, int *ofdm, int *size)
1205 {
1206         struct data_desc *rxd = entry->priv;
1207         u32 word0;
1208         u32 word2;
1209
1210         rt2x00_desc_read(rxd, 0, &word0);
1211         rt2x00_desc_read(rxd, 2, &word2);
1212
1213         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR) ||
1214             rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1215                 return -EINVAL;
1216
1217         /*
1218          * Obtain the status about this packet.
1219          */
1220         *signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1221         *rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1222             entry->ring->rt2x00dev->rssi_offset;
1223         *ofdm = 0;
1224         *size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1225
1226         return 0;
1227 }
1228
1229 /*
1230  * Interrupt functions.
1231  */
1232 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1233 {
1234         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1235         struct data_entry *entry;
1236         struct data_desc *txd;
1237         u32 word;
1238         int tx_status;
1239         int retry;
1240
1241         while (!rt2x00_ring_empty(ring)) {
1242                 entry = rt2x00_get_data_entry_done(ring);
1243                 txd = entry->priv;
1244                 rt2x00_desc_read(txd, 0, &word);
1245
1246                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1247                     !rt2x00_get_field32(word, TXD_W0_VALID))
1248                         break;
1249
1250                 /*
1251                  * Obtain the status about this packet.
1252                  */
1253                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1254                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1255
1256                 rt2x00lib_txdone(entry, tx_status, retry);
1257
1258                 /*
1259                  * Make this entry available for reuse.
1260                  */
1261                 entry->flags = 0;
1262                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1263                 rt2x00_desc_write(txd, 0, word);
1264                 rt2x00_ring_index_done_inc(ring);
1265         }
1266
1267         /*
1268          * If the data ring was full before the txdone handler
1269          * we must make sure the packet queue in the mac80211 stack
1270          * is reenabled when the txdone handler has finished.
1271          */
1272         entry = ring->entry;
1273         if (!rt2x00_ring_full(ring))
1274                 ieee80211_wake_queue(rt2x00dev->hw,
1275                                      entry->tx_status.control.queue);
1276 }
1277
1278 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1279 {
1280         struct rt2x00_dev *rt2x00dev = dev_instance;
1281         u32 reg;
1282
1283         /*
1284          * Get the interrupt sources & saved to local variable.
1285          * Write register value back to clear pending interrupts.
1286          */
1287         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1288         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1289
1290         if (!reg)
1291                 return IRQ_NONE;
1292
1293         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1294                 return IRQ_HANDLED;
1295
1296         /*
1297          * Handle interrupts, walk through all bits
1298          * and run the tasks, the bits are checked in order of
1299          * priority.
1300          */
1301
1302         /*
1303          * 1 - Beacon timer expired interrupt.
1304          */
1305         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1306                 rt2x00lib_beacondone(rt2x00dev);
1307
1308         /*
1309          * 2 - Rx ring done interrupt.
1310          */
1311         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1312                 rt2x00pci_rxdone(rt2x00dev);
1313
1314         /*
1315          * 3 - Atim ring transmit done interrupt.
1316          */
1317         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1318                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1319
1320         /*
1321          * 4 - Priority ring transmit done interrupt.
1322          */
1323         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1324                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1325
1326         /*
1327          * 5 - Tx ring transmit done interrupt.
1328          */
1329         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1330                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1331
1332         return IRQ_HANDLED;
1333 }
1334
1335 /*
1336  * Device probe functions.
1337  */
1338 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1339 {
1340         struct eeprom_93cx6 eeprom;
1341         u32 reg;
1342         u16 word;
1343         u8 *mac;
1344
1345         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1346
1347         eeprom.data = rt2x00dev;
1348         eeprom.register_read = rt2400pci_eepromregister_read;
1349         eeprom.register_write = rt2400pci_eepromregister_write;
1350         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1351             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1352         eeprom.reg_data_in = 0;
1353         eeprom.reg_data_out = 0;
1354         eeprom.reg_data_clock = 0;
1355         eeprom.reg_chip_select = 0;
1356
1357         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1358                                EEPROM_SIZE / sizeof(u16));
1359
1360         /*
1361          * Start validation of the data that has been read.
1362          */
1363         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1364         if (!is_valid_ether_addr(mac)) {
1365                 random_ether_addr(mac);
1366                 EEPROM(rt2x00dev, "MAC: " MAC_FMT "\n", MAC_ARG(mac));
1367         }
1368
1369         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1370         if (word == 0xffff) {
1371                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1372                 return -EINVAL;
1373         }
1374
1375         return 0;
1376 }
1377
1378 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1379 {
1380         u32 reg;
1381         u16 value;
1382         u16 eeprom;
1383
1384         /*
1385          * Read EEPROM word for configuration.
1386          */
1387         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1388
1389         /*
1390          * Identify RF chipset.
1391          */
1392         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1393         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1394         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1395
1396         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1397             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1398                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1399                 return -ENODEV;
1400         }
1401
1402         /*
1403          * Identify default antenna configuration.
1404          */
1405         rt2x00dev->hw->conf.antenna_sel_tx =
1406             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1407         rt2x00dev->hw->conf.antenna_sel_rx =
1408             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1409
1410         /*
1411          * Store led mode, for correct led behaviour.
1412          */
1413         rt2x00dev->led_mode =
1414             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1415
1416         /*
1417          * Detect if this device has an hardware controlled radio.
1418          */
1419         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1420                 __set_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1421
1422         /*
1423          * Check if the BBP tuning should be enabled.
1424          */
1425         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1426                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1427
1428         return 0;
1429 }
1430
1431 /*
1432  * RF value list for RF2420 & RF2421
1433  * Supports: 2.4 GHz
1434  */
1435 static const struct rf_channel rf_vals_bg[] = {
1436         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1437         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1438         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1439         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1440         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1441         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1442         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1443         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1444         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1445         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1446         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1447         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1448         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1449         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1450 };
1451
1452 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1453 {
1454         struct hw_mode_spec *spec = &rt2x00dev->spec;
1455         u8 *txpower;
1456         unsigned int i;
1457
1458         /*
1459          * Initialize all hw fields.
1460          */
1461         rt2x00dev->hw->flags =
1462             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1463             IEEE80211_HW_MONITOR_DURING_OPER |
1464             IEEE80211_HW_NO_PROBE_FILTERING;
1465         rt2x00dev->hw->extra_tx_headroom = 0;
1466         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1467         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1468         rt2x00dev->hw->queues = 2;
1469
1470         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1471         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1472                                 rt2x00_eeprom_addr(rt2x00dev,
1473                                                    EEPROM_MAC_ADDR_0));
1474
1475         /*
1476          * Convert tx_power array in eeprom.
1477          */
1478         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1479         for (i = 0; i < 14; i++)
1480                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1481
1482         /*
1483          * Initialize hw_mode information.
1484          */
1485         spec->num_modes = 1;
1486         spec->num_rates = 4;
1487         spec->tx_power_a = NULL;
1488         spec->tx_power_bg = txpower;
1489         spec->tx_power_default = DEFAULT_TXPOWER;
1490
1491         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1492         spec->channels = rf_vals_bg;
1493 }
1494
1495 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1496 {
1497         int retval;
1498
1499         /*
1500          * Allocate eeprom data.
1501          */
1502         retval = rt2400pci_validate_eeprom(rt2x00dev);
1503         if (retval)
1504                 return retval;
1505
1506         retval = rt2400pci_init_eeprom(rt2x00dev);
1507         if (retval)
1508                 return retval;
1509
1510         /*
1511          * Initialize hw specifications.
1512          */
1513         rt2400pci_probe_hw_mode(rt2x00dev);
1514
1515         /*
1516          * This device requires the beacon ring
1517          */
1518         __set_bit(REQUIRE_BEACON_RING, &rt2x00dev->flags);
1519
1520         /*
1521          * Set the rssi offset.
1522          */
1523         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1524
1525         return 0;
1526 }
1527
1528 /*
1529  * IEEE80211 stack callback functions.
1530  */
1531 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1532                                      u32 short_retry, u32 long_retry)
1533 {
1534         struct rt2x00_dev *rt2x00dev = hw->priv;
1535         u32 reg;
1536
1537         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1538         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1539         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1540         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1541
1542         return 0;
1543 }
1544
1545 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1546                              int queue,
1547                              const struct ieee80211_tx_queue_params *params)
1548 {
1549         struct rt2x00_dev *rt2x00dev = hw->priv;
1550
1551         /*
1552          * We don't support variating cw_min and cw_max variables
1553          * per queue. So by default we only configure the TX queue,
1554          * and ignore all other configurations.
1555          */
1556         if (queue != IEEE80211_TX_QUEUE_DATA0)
1557                 return -EINVAL;
1558
1559         if (rt2x00mac_conf_tx(hw, queue, params))
1560                 return -EINVAL;
1561
1562         /*
1563          * Write configuration to register.
1564          */
1565         rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1566
1567         return 0;
1568 }
1569
1570 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1571 {
1572         struct rt2x00_dev *rt2x00dev = hw->priv;
1573         u64 tsf;
1574         u32 reg;
1575
1576         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1577         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1578         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1579         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1580
1581         return tsf;
1582 }
1583
1584 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1585 {
1586         struct rt2x00_dev *rt2x00dev = hw->priv;
1587
1588         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1589         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1590 }
1591
1592 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1593 {
1594         struct rt2x00_dev *rt2x00dev = hw->priv;
1595         u32 reg;
1596
1597         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1598         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1599 }
1600
1601 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1602         .tx                     = rt2x00mac_tx,
1603         .add_interface          = rt2x00mac_add_interface,
1604         .remove_interface       = rt2x00mac_remove_interface,
1605         .config                 = rt2x00mac_config,
1606         .config_interface       = rt2x00mac_config_interface,
1607         .set_multicast_list     = rt2x00mac_set_multicast_list,
1608         .get_stats              = rt2x00mac_get_stats,
1609         .set_retry_limit        = rt2400pci_set_retry_limit,
1610         .conf_tx                = rt2400pci_conf_tx,
1611         .get_tx_stats           = rt2x00mac_get_tx_stats,
1612         .get_tsf                = rt2400pci_get_tsf,
1613         .reset_tsf              = rt2400pci_reset_tsf,
1614         .beacon_update          = rt2x00pci_beacon_update,
1615         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1616 };
1617
1618 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1619         .irq_handler            = rt2400pci_interrupt,
1620         .probe_hw               = rt2400pci_probe_hw,
1621         .initialize             = rt2x00pci_initialize,
1622         .uninitialize           = rt2x00pci_uninitialize,
1623         .set_device_state       = rt2400pci_set_device_state,
1624 #ifdef CONFIG_RT2400PCI_RFKILL
1625         .rfkill_poll            = rt2400pci_rfkill_poll,
1626 #endif /* CONFIG_RT2400PCI_RFKILL */
1627         .link_stats             = rt2400pci_link_stats,
1628         .reset_tuner            = rt2400pci_reset_tuner,
1629         .link_tuner             = rt2400pci_link_tuner,
1630         .write_tx_desc          = rt2400pci_write_tx_desc,
1631         .write_tx_data          = rt2x00pci_write_tx_data,
1632         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1633         .fill_rxdone            = rt2400pci_fill_rxdone,
1634         .config_mac_addr        = rt2400pci_config_mac_addr,
1635         .config_bssid           = rt2400pci_config_bssid,
1636         .config_packet_filter   = rt2400pci_config_packet_filter,
1637         .config_type            = rt2400pci_config_type,
1638         .config                 = rt2400pci_config,
1639 };
1640
1641 static const struct rt2x00_ops rt2400pci_ops = {
1642         .name           = DRV_NAME,
1643         .rxd_size       = RXD_DESC_SIZE,
1644         .txd_size       = TXD_DESC_SIZE,
1645         .eeprom_size    = EEPROM_SIZE,
1646         .rf_size        = RF_SIZE,
1647         .lib            = &rt2400pci_rt2x00_ops,
1648         .hw             = &rt2400pci_mac80211_ops,
1649 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1650         .debugfs        = &rt2400pci_rt2x00debug,
1651 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1652 };
1653
1654 /*
1655  * RT2400pci module information.
1656  */
1657 static struct pci_device_id rt2400pci_device_table[] = {
1658         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1659         { 0, }
1660 };
1661
1662 MODULE_AUTHOR(DRV_PROJECT);
1663 MODULE_VERSION(DRV_VERSION);
1664 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1665 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1666 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1667 MODULE_LICENSE("GPL");
1668
1669 static struct pci_driver rt2400pci_driver = {
1670         .name           = DRV_NAME,
1671         .id_table       = rt2400pci_device_table,
1672         .probe          = rt2x00pci_probe,
1673         .remove         = __devexit_p(rt2x00pci_remove),
1674         .suspend        = rt2x00pci_suspend,
1675         .resume         = rt2x00pci_resume,
1676 };
1677
1678 static int __init rt2400pci_init(void)
1679 {
1680         return pci_register_driver(&rt2400pci_driver);
1681 }
1682
1683 static void __exit rt2400pci_exit(void)
1684 {
1685         pci_unregister_driver(&rt2400pci_driver);
1686 }
1687
1688 module_init(rt2400pci_init);
1689 module_exit(rt2400pci_exit);