rt2x00: Introduce 3 queue commands in drivers (start, kick, stop).
[linux-2.6.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
1 /*
2         Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2400pci
23         Abstract: rt2400pci device specific routines.
24         Supported chipsets: RT2460.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34 #include <linux/slab.h>
35
36 #include "rt2x00.h"
37 #include "rt2x00pci.h"
38 #include "rt2400pci.h"
39
40 /*
41  * Register access.
42  * All access to the CSR registers will go through the methods
43  * rt2x00pci_register_read and rt2x00pci_register_write.
44  * BBP and RF register require indirect register access,
45  * and use the CSR registers BBPCSR and RFCSR to achieve this.
46  * These indirect registers work with busy bits,
47  * and we will try maximal REGISTER_BUSY_COUNT times to access
48  * the register while taking a REGISTER_BUSY_DELAY us delay
49  * between each attampt. When the busy bit is still set at that time,
50  * the access attempt is considered to have failed,
51  * and we will print an error.
52  */
53 #define WAIT_FOR_BBP(__dev, __reg) \
54         rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
55 #define WAIT_FOR_RF(__dev, __reg) \
56         rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
57
58 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
59                                 const unsigned int word, const u8 value)
60 {
61         u32 reg;
62
63         mutex_lock(&rt2x00dev->csr_mutex);
64
65         /*
66          * Wait until the BBP becomes available, afterwards we
67          * can safely write the new data into the register.
68          */
69         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
70                 reg = 0;
71                 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
75
76                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
77         }
78
79         mutex_unlock(&rt2x00dev->csr_mutex);
80 }
81
82 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
83                                const unsigned int word, u8 *value)
84 {
85         u32 reg;
86
87         mutex_lock(&rt2x00dev->csr_mutex);
88
89         /*
90          * Wait until the BBP becomes available, afterwards we
91          * can safely write the read request into the register.
92          * After the data has been written, we wait until hardware
93          * returns the correct value, if at any time the register
94          * doesn't become available in time, reg will be 0xffffffff
95          * which means we return 0xff to the caller.
96          */
97         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
98                 reg = 0;
99                 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100                 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101                 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
102
103                 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
104
105                 WAIT_FOR_BBP(rt2x00dev, &reg);
106         }
107
108         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
109
110         mutex_unlock(&rt2x00dev->csr_mutex);
111 }
112
113 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
114                                const unsigned int word, const u32 value)
115 {
116         u32 reg;
117
118         mutex_lock(&rt2x00dev->csr_mutex);
119
120         /*
121          * Wait until the RF becomes available, afterwards we
122          * can safely write the new data into the register.
123          */
124         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
125                 reg = 0;
126                 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127                 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128                 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
129                 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
130
131                 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
132                 rt2x00_rf_write(rt2x00dev, word, value);
133         }
134
135         mutex_unlock(&rt2x00dev->csr_mutex);
136 }
137
138 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
139 {
140         struct rt2x00_dev *rt2x00dev = eeprom->data;
141         u32 reg;
142
143         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
144
145         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
146         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
147         eeprom->reg_data_clock =
148             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
149         eeprom->reg_chip_select =
150             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
151 }
152
153 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
154 {
155         struct rt2x00_dev *rt2x00dev = eeprom->data;
156         u32 reg = 0;
157
158         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
159         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
160         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
161                            !!eeprom->reg_data_clock);
162         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
163                            !!eeprom->reg_chip_select);
164
165         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
166 }
167
168 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
169 static const struct rt2x00debug rt2400pci_rt2x00debug = {
170         .owner  = THIS_MODULE,
171         .csr    = {
172                 .read           = rt2x00pci_register_read,
173                 .write          = rt2x00pci_register_write,
174                 .flags          = RT2X00DEBUGFS_OFFSET,
175                 .word_base      = CSR_REG_BASE,
176                 .word_size      = sizeof(u32),
177                 .word_count     = CSR_REG_SIZE / sizeof(u32),
178         },
179         .eeprom = {
180                 .read           = rt2x00_eeprom_read,
181                 .write          = rt2x00_eeprom_write,
182                 .word_base      = EEPROM_BASE,
183                 .word_size      = sizeof(u16),
184                 .word_count     = EEPROM_SIZE / sizeof(u16),
185         },
186         .bbp    = {
187                 .read           = rt2400pci_bbp_read,
188                 .write          = rt2400pci_bbp_write,
189                 .word_base      = BBP_BASE,
190                 .word_size      = sizeof(u8),
191                 .word_count     = BBP_SIZE / sizeof(u8),
192         },
193         .rf     = {
194                 .read           = rt2x00_rf_read,
195                 .write          = rt2400pci_rf_write,
196                 .word_base      = RF_BASE,
197                 .word_size      = sizeof(u32),
198                 .word_count     = RF_SIZE / sizeof(u32),
199         },
200 };
201 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
202
203 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
204 {
205         u32 reg;
206
207         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
208         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
209 }
210
211 #ifdef CONFIG_RT2X00_LIB_LEDS
212 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
213                                      enum led_brightness brightness)
214 {
215         struct rt2x00_led *led =
216             container_of(led_cdev, struct rt2x00_led, led_dev);
217         unsigned int enabled = brightness != LED_OFF;
218         u32 reg;
219
220         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
221
222         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
223                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
224         else if (led->type == LED_TYPE_ACTIVITY)
225                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
226
227         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
228 }
229
230 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
231                                unsigned long *delay_on,
232                                unsigned long *delay_off)
233 {
234         struct rt2x00_led *led =
235             container_of(led_cdev, struct rt2x00_led, led_dev);
236         u32 reg;
237
238         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
239         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
240         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
241         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
242
243         return 0;
244 }
245
246 static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
247                                struct rt2x00_led *led,
248                                enum led_type type)
249 {
250         led->rt2x00dev = rt2x00dev;
251         led->type = type;
252         led->led_dev.brightness_set = rt2400pci_brightness_set;
253         led->led_dev.blink_set = rt2400pci_blink_set;
254         led->flags = LED_INITIALIZED;
255 }
256 #endif /* CONFIG_RT2X00_LIB_LEDS */
257
258 /*
259  * Configuration handlers.
260  */
261 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
262                                     const unsigned int filter_flags)
263 {
264         u32 reg;
265
266         /*
267          * Start configuration steps.
268          * Note that the version error will always be dropped
269          * since there is no filter for it at this time.
270          */
271         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
272         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
273                            !(filter_flags & FIF_FCSFAIL));
274         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
275                            !(filter_flags & FIF_PLCPFAIL));
276         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
277                            !(filter_flags & FIF_CONTROL));
278         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
279                            !(filter_flags & FIF_PROMISC_IN_BSS));
280         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
281                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
282                            !rt2x00dev->intf_ap_count);
283         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
284         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
285 }
286
287 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
288                                   struct rt2x00_intf *intf,
289                                   struct rt2x00intf_conf *conf,
290                                   const unsigned int flags)
291 {
292         unsigned int bcn_preload;
293         u32 reg;
294
295         if (flags & CONFIG_UPDATE_TYPE) {
296                 /*
297                  * Enable beacon config
298                  */
299                 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
300                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
301                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
302                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
303
304                 /*
305                  * Enable synchronisation.
306                  */
307                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
308                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
309                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
310                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
311                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
312         }
313
314         if (flags & CONFIG_UPDATE_MAC)
315                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
316                                               conf->mac, sizeof(conf->mac));
317
318         if (flags & CONFIG_UPDATE_BSSID)
319                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
320                                               conf->bssid, sizeof(conf->bssid));
321 }
322
323 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
324                                  struct rt2x00lib_erp *erp,
325                                  u32 changed)
326 {
327         int preamble_mask;
328         u32 reg;
329
330         /*
331          * When short preamble is enabled, we should set bit 0x08
332          */
333         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
334                 preamble_mask = erp->short_preamble << 3;
335
336                 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
337                 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
338                 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
339                 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
340                 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
341                 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
342
343                 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
344                 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
345                 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
346                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
347                                    GET_DURATION(ACK_SIZE, 10));
348                 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
349
350                 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
351                 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
352                 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
353                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
354                                    GET_DURATION(ACK_SIZE, 20));
355                 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
356
357                 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
358                 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
359                 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
360                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
361                                    GET_DURATION(ACK_SIZE, 55));
362                 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
363
364                 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
365                 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
366                 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
367                 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
368                                    GET_DURATION(ACK_SIZE, 110));
369                 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
370         }
371
372         if (changed & BSS_CHANGED_BASIC_RATES)
373                 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
374
375         if (changed & BSS_CHANGED_ERP_SLOT) {
376                 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
377                 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
378                 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
379
380                 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
381                 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
382                 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
383                 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
384
385                 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
386                 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
387                 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
388                 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
389         }
390
391         if (changed & BSS_CHANGED_BEACON_INT) {
392                 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
393                 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
394                                    erp->beacon_int * 16);
395                 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
396                                    erp->beacon_int * 16);
397                 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
398         }
399 }
400
401 static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
402                                  struct antenna_setup *ant)
403 {
404         u8 r1;
405         u8 r4;
406
407         /*
408          * We should never come here because rt2x00lib is supposed
409          * to catch this and send us the correct antenna explicitely.
410          */
411         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
412                ant->tx == ANTENNA_SW_DIVERSITY);
413
414         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
415         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
416
417         /*
418          * Configure the TX antenna.
419          */
420         switch (ant->tx) {
421         case ANTENNA_HW_DIVERSITY:
422                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
423                 break;
424         case ANTENNA_A:
425                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
426                 break;
427         case ANTENNA_B:
428         default:
429                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
430                 break;
431         }
432
433         /*
434          * Configure the RX antenna.
435          */
436         switch (ant->rx) {
437         case ANTENNA_HW_DIVERSITY:
438                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
439                 break;
440         case ANTENNA_A:
441                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
442                 break;
443         case ANTENNA_B:
444         default:
445                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
446                 break;
447         }
448
449         rt2400pci_bbp_write(rt2x00dev, 4, r4);
450         rt2400pci_bbp_write(rt2x00dev, 1, r1);
451 }
452
453 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
454                                      struct rf_channel *rf)
455 {
456         /*
457          * Switch on tuning bits.
458          */
459         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
460         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
461
462         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
463         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
464         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
465
466         /*
467          * RF2420 chipset don't need any additional actions.
468          */
469         if (rt2x00_rf(rt2x00dev, RF2420))
470                 return;
471
472         /*
473          * For the RT2421 chipsets we need to write an invalid
474          * reference clock rate to activate auto_tune.
475          * After that we set the value back to the correct channel.
476          */
477         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
478         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
479         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
480
481         msleep(1);
482
483         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
484         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
485         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
486
487         msleep(1);
488
489         /*
490          * Switch off tuning bits.
491          */
492         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
493         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
494
495         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
496         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
497
498         /*
499          * Clear false CRC during channel switch.
500          */
501         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
502 }
503
504 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
505 {
506         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
507 }
508
509 static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
510                                          struct rt2x00lib_conf *libconf)
511 {
512         u32 reg;
513
514         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
515         rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
516                            libconf->conf->long_frame_max_tx_count);
517         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
518                            libconf->conf->short_frame_max_tx_count);
519         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
520 }
521
522 static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
523                                 struct rt2x00lib_conf *libconf)
524 {
525         enum dev_state state =
526             (libconf->conf->flags & IEEE80211_CONF_PS) ?
527                 STATE_SLEEP : STATE_AWAKE;
528         u32 reg;
529
530         if (state == STATE_SLEEP) {
531                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
532                 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
533                                    (rt2x00dev->beacon_int - 20) * 16);
534                 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
535                                    libconf->conf->listen_interval - 1);
536
537                 /* We must first disable autowake before it can be enabled */
538                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
539                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
540
541                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
542                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
543         } else {
544                 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
545                 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
546                 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
547         }
548
549         rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
550 }
551
552 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
553                              struct rt2x00lib_conf *libconf,
554                              const unsigned int flags)
555 {
556         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
557                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
558         if (flags & IEEE80211_CONF_CHANGE_POWER)
559                 rt2400pci_config_txpower(rt2x00dev,
560                                          libconf->conf->power_level);
561         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
562                 rt2400pci_config_retry_limit(rt2x00dev, libconf);
563         if (flags & IEEE80211_CONF_CHANGE_PS)
564                 rt2400pci_config_ps(rt2x00dev, libconf);
565 }
566
567 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
568                                 const int cw_min, const int cw_max)
569 {
570         u32 reg;
571
572         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
573         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
574         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
575         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
576 }
577
578 /*
579  * Link tuning
580  */
581 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
582                                  struct link_qual *qual)
583 {
584         u32 reg;
585         u8 bbp;
586
587         /*
588          * Update FCS error count from register.
589          */
590         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
591         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
592
593         /*
594          * Update False CCA count from register.
595          */
596         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
597         qual->false_cca = bbp;
598 }
599
600 static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
601                                      struct link_qual *qual, u8 vgc_level)
602 {
603         if (qual->vgc_level_reg != vgc_level) {
604                 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
605                 qual->vgc_level = vgc_level;
606                 qual->vgc_level_reg = vgc_level;
607         }
608 }
609
610 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
611                                   struct link_qual *qual)
612 {
613         rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
614 }
615
616 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
617                                  struct link_qual *qual, const u32 count)
618 {
619         /*
620          * The link tuner should not run longer then 60 seconds,
621          * and should run once every 2 seconds.
622          */
623         if (count > 60 || !(count & 1))
624                 return;
625
626         /*
627          * Base r13 link tuning on the false cca count.
628          */
629         if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
630                 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
631         else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
632                 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
633 }
634
635 /*
636  * Queue handlers.
637  */
638 static void rt2400pci_start_queue(struct data_queue *queue)
639 {
640         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
641         u32 reg;
642
643         switch (queue->qid) {
644         case QID_RX:
645                 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
646                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
647                 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
648                 break;
649         case QID_BEACON:
650                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
651                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
652                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
653                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
654                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
655                 break;
656         default:
657                 break;
658         }
659 }
660
661 static void rt2400pci_kick_queue(struct data_queue *queue)
662 {
663         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
664         u32 reg;
665
666         switch (queue->qid) {
667         case QID_AC_BE:
668                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
669                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
670                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
671                 break;
672         case QID_AC_BK:
673                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
674                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
675                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
676                 break;
677         case QID_ATIM:
678                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
679                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
680                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
681                 break;
682         default:
683                 break;
684         }
685 }
686
687 static void rt2400pci_stop_queue(struct data_queue *queue)
688 {
689         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
690         u32 reg;
691
692         switch (queue->qid) {
693         case QID_AC_BE:
694         case QID_AC_BK:
695         case QID_ATIM:
696                 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
697                 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
698                 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
699                 break;
700         case QID_RX:
701                 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
702                 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
703                 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
704                 break;
705         case QID_BEACON:
706                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
707                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
708                 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
709                 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
710                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
711                 break;
712         default:
713                 break;
714         }
715 }
716
717 /*
718  * Initialization functions.
719  */
720 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
721 {
722         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
723         u32 word;
724
725         if (entry->queue->qid == QID_RX) {
726                 rt2x00_desc_read(entry_priv->desc, 0, &word);
727
728                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
729         } else {
730                 rt2x00_desc_read(entry_priv->desc, 0, &word);
731
732                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
733                         rt2x00_get_field32(word, TXD_W0_VALID));
734         }
735 }
736
737 static void rt2400pci_clear_entry(struct queue_entry *entry)
738 {
739         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
740         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
741         u32 word;
742
743         if (entry->queue->qid == QID_RX) {
744                 rt2x00_desc_read(entry_priv->desc, 2, &word);
745                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
746                 rt2x00_desc_write(entry_priv->desc, 2, word);
747
748                 rt2x00_desc_read(entry_priv->desc, 1, &word);
749                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
750                 rt2x00_desc_write(entry_priv->desc, 1, word);
751
752                 rt2x00_desc_read(entry_priv->desc, 0, &word);
753                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
754                 rt2x00_desc_write(entry_priv->desc, 0, word);
755         } else {
756                 rt2x00_desc_read(entry_priv->desc, 0, &word);
757                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
758                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
759                 rt2x00_desc_write(entry_priv->desc, 0, word);
760         }
761 }
762
763 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
764 {
765         struct queue_entry_priv_pci *entry_priv;
766         u32 reg;
767
768         /*
769          * Initialize registers.
770          */
771         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
772         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
773         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
774         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
775         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
776         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
777
778         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
779         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
780         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
781                            entry_priv->desc_dma);
782         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
783
784         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
785         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
786         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
787                            entry_priv->desc_dma);
788         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
789
790         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
791         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
792         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
793                            entry_priv->desc_dma);
794         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
795
796         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
797         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
798         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
799                            entry_priv->desc_dma);
800         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
801
802         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
803         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
804         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
805         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
806
807         entry_priv = rt2x00dev->rx->entries[0].priv_data;
808         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
809         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
810                            entry_priv->desc_dma);
811         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
812
813         return 0;
814 }
815
816 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
817 {
818         u32 reg;
819
820         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
821         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
822         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
823         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
824
825         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
826         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
827         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
828         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
829         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
830
831         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
832         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
833                            (rt2x00dev->rx->data_size / 128));
834         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
835
836         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
837         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
838         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
839         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
840         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
841         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
842         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
843         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
844         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
845         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
846
847         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
848
849         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
850         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
851         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
852         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
853         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
854         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
855
856         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
857         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
858         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
859         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
860         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
861         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
862         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
863         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
864
865         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
866
867         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
868                 return -EBUSY;
869
870         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
871         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
872
873         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
874         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
875         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
876
877         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
878         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
879         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
880         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
881         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
882         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
883
884         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
885         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
886         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
887         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
888         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
889
890         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
891         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
892         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
893         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
894
895         /*
896          * We must clear the FCS and FIFO error count.
897          * These registers are cleared on read,
898          * so we may pass a useless variable to store the value.
899          */
900         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
901         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
902
903         return 0;
904 }
905
906 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
907 {
908         unsigned int i;
909         u8 value;
910
911         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
912                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
913                 if ((value != 0xff) && (value != 0x00))
914                         return 0;
915                 udelay(REGISTER_BUSY_DELAY);
916         }
917
918         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
919         return -EACCES;
920 }
921
922 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
923 {
924         unsigned int i;
925         u16 eeprom;
926         u8 reg_id;
927         u8 value;
928
929         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
930                 return -EACCES;
931
932         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
933         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
934         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
935         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
936         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
937         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
938         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
939         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
940         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
941         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
942         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
943         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
944         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
945         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
946
947         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
948                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
949
950                 if (eeprom != 0xffff && eeprom != 0x0000) {
951                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
952                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
953                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
954                 }
955         }
956
957         return 0;
958 }
959
960 /*
961  * Device state switch handlers.
962  */
963 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
964                                  enum dev_state state)
965 {
966         int mask = (state == STATE_RADIO_IRQ_OFF) ||
967                    (state == STATE_RADIO_IRQ_OFF_ISR);
968         u32 reg;
969
970         /*
971          * When interrupts are being enabled, the interrupt registers
972          * should clear the register to assure a clean state.
973          */
974         if (state == STATE_RADIO_IRQ_ON) {
975                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
976                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
977         }
978
979         /*
980          * Only toggle the interrupts bits we are going to use.
981          * Non-checked interrupt bits are disabled by default.
982          */
983         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
984         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
985         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
986         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
987         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
988         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
989         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
990 }
991
992 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
993 {
994         /*
995          * Initialize all registers.
996          */
997         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
998                      rt2400pci_init_registers(rt2x00dev) ||
999                      rt2400pci_init_bbp(rt2x00dev)))
1000                 return -EIO;
1001
1002         return 0;
1003 }
1004
1005 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1006 {
1007         /*
1008          * Disable power
1009          */
1010         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1011 }
1012
1013 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1014                                enum dev_state state)
1015 {
1016         u32 reg, reg2;
1017         unsigned int i;
1018         char put_to_sleep;
1019         char bbp_state;
1020         char rf_state;
1021
1022         put_to_sleep = (state != STATE_AWAKE);
1023
1024         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1025         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1026         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1027         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1028         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1029         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1030
1031         /*
1032          * Device is not guaranteed to be in the requested state yet.
1033          * We must wait until the register indicates that the
1034          * device has entered the correct state.
1035          */
1036         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1037                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
1038                 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1039                 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1040                 if (bbp_state == state && rf_state == state)
1041                         return 0;
1042                 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1043                 msleep(10);
1044         }
1045
1046         return -EBUSY;
1047 }
1048
1049 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1050                                       enum dev_state state)
1051 {
1052         int retval = 0;
1053
1054         switch (state) {
1055         case STATE_RADIO_ON:
1056                 retval = rt2400pci_enable_radio(rt2x00dev);
1057                 break;
1058         case STATE_RADIO_OFF:
1059                 rt2400pci_disable_radio(rt2x00dev);
1060                 break;
1061         case STATE_RADIO_RX_ON:
1062                 rt2400pci_start_queue(rt2x00dev->rx);
1063                 break;
1064         case STATE_RADIO_RX_OFF:
1065                 rt2400pci_stop_queue(rt2x00dev->rx);
1066                 break;
1067         case STATE_RADIO_IRQ_ON:
1068         case STATE_RADIO_IRQ_ON_ISR:
1069         case STATE_RADIO_IRQ_OFF:
1070         case STATE_RADIO_IRQ_OFF_ISR:
1071                 rt2400pci_toggle_irq(rt2x00dev, state);
1072                 break;
1073         case STATE_DEEP_SLEEP:
1074         case STATE_SLEEP:
1075         case STATE_STANDBY:
1076         case STATE_AWAKE:
1077                 retval = rt2400pci_set_state(rt2x00dev, state);
1078                 break;
1079         default:
1080                 retval = -ENOTSUPP;
1081                 break;
1082         }
1083
1084         if (unlikely(retval))
1085                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1086                       state, retval);
1087
1088         return retval;
1089 }
1090
1091 /*
1092  * TX descriptor initialization
1093  */
1094 static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1095                                     struct txentry_desc *txdesc)
1096 {
1097         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1098         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1099         __le32 *txd = entry_priv->desc;
1100         u32 word;
1101
1102         /*
1103          * Start writing the descriptor words.
1104          */
1105         rt2x00_desc_read(txd, 1, &word);
1106         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1107         rt2x00_desc_write(txd, 1, word);
1108
1109         rt2x00_desc_read(txd, 2, &word);
1110         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1111         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1112         rt2x00_desc_write(txd, 2, word);
1113
1114         rt2x00_desc_read(txd, 3, &word);
1115         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1116         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1117         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1118         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1119         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1120         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1121         rt2x00_desc_write(txd, 3, word);
1122
1123         rt2x00_desc_read(txd, 4, &word);
1124         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1125         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1126         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1127         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1128         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1129         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1130         rt2x00_desc_write(txd, 4, word);
1131
1132         /*
1133          * Writing TXD word 0 must the last to prevent a race condition with
1134          * the device, whereby the device may take hold of the TXD before we
1135          * finished updating it.
1136          */
1137         rt2x00_desc_read(txd, 0, &word);
1138         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1139         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1140         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1141                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1142         rt2x00_set_field32(&word, TXD_W0_ACK,
1143                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1144         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1145                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1146         rt2x00_set_field32(&word, TXD_W0_RTS,
1147                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1148         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1149         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1150                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1151         rt2x00_desc_write(txd, 0, word);
1152
1153         /*
1154          * Register descriptor details in skb frame descriptor.
1155          */
1156         skbdesc->desc = txd;
1157         skbdesc->desc_len = TXD_DESC_SIZE;
1158 }
1159
1160 /*
1161  * TX data initialization
1162  */
1163 static void rt2400pci_write_beacon(struct queue_entry *entry,
1164                                    struct txentry_desc *txdesc)
1165 {
1166         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1167         u32 reg;
1168
1169         /*
1170          * Disable beaconing while we are reloading the beacon data,
1171          * otherwise we might be sending out invalid data.
1172          */
1173         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1174         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1175         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1176
1177         rt2x00queue_map_txskb(entry);
1178
1179         /*
1180          * Write the TX descriptor for the beacon.
1181          */
1182         rt2400pci_write_tx_desc(entry, txdesc);
1183
1184         /*
1185          * Dump beacon to userspace through debugfs.
1186          */
1187         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1188
1189         /*
1190          * Enable beaconing again.
1191          */
1192         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1193         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1194         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1195         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1196 }
1197
1198 /*
1199  * RX control handlers
1200  */
1201 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1202                                   struct rxdone_entry_desc *rxdesc)
1203 {
1204         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1205         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1206         u32 word0;
1207         u32 word2;
1208         u32 word3;
1209         u32 word4;
1210         u64 tsf;
1211         u32 rx_low;
1212         u32 rx_high;
1213
1214         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1215         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1216         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1217         rt2x00_desc_read(entry_priv->desc, 4, &word4);
1218
1219         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1220                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1221         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1222                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1223
1224         /*
1225          * We only get the lower 32bits from the timestamp,
1226          * to get the full 64bits we must complement it with
1227          * the timestamp from get_tsf().
1228          * Note that when a wraparound of the lower 32bits
1229          * has occurred between the frame arrival and the get_tsf()
1230          * call, we must decrease the higher 32bits with 1 to get
1231          * to correct value.
1232          */
1233         tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw);
1234         rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1235         rx_high = upper_32_bits(tsf);
1236
1237         if ((u32)tsf <= rx_low)
1238                 rx_high--;
1239
1240         /*
1241          * Obtain the status about this packet.
1242          * The signal is the PLCP value, and needs to be stripped
1243          * of the preamble bit (0x08).
1244          */
1245         rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1246         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1247         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1248             entry->queue->rt2x00dev->rssi_offset;
1249         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1250
1251         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1252         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1253                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1254 }
1255
1256 /*
1257  * Interrupt functions.
1258  */
1259 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1260                              const enum data_queue_qid queue_idx)
1261 {
1262         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1263         struct queue_entry_priv_pci *entry_priv;
1264         struct queue_entry *entry;
1265         struct txdone_entry_desc txdesc;
1266         u32 word;
1267
1268         while (!rt2x00queue_empty(queue)) {
1269                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1270                 entry_priv = entry->priv_data;
1271                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1272
1273                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1274                     !rt2x00_get_field32(word, TXD_W0_VALID))
1275                         break;
1276
1277                 /*
1278                  * Obtain the status about this packet.
1279                  */
1280                 txdesc.flags = 0;
1281                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1282                 case 0: /* Success */
1283                 case 1: /* Success with retry */
1284                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1285                         break;
1286                 case 2: /* Failure, excessive retries */
1287                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1288                         /* Don't break, this is a failed frame! */
1289                 default: /* Failure */
1290                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1291                 }
1292                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1293
1294                 rt2x00lib_txdone(entry, &txdesc);
1295         }
1296 }
1297
1298 static irqreturn_t rt2400pci_interrupt_thread(int irq, void *dev_instance)
1299 {
1300         struct rt2x00_dev *rt2x00dev = dev_instance;
1301         u32 reg = rt2x00dev->irqvalue[0];
1302
1303         /*
1304          * Handle interrupts, walk through all bits
1305          * and run the tasks, the bits are checked in order of
1306          * priority.
1307          */
1308
1309         /*
1310          * 1 - Beacon timer expired interrupt.
1311          */
1312         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1313                 rt2x00lib_beacondone(rt2x00dev);
1314
1315         /*
1316          * 2 - Rx ring done interrupt.
1317          */
1318         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1319                 rt2x00pci_rxdone(rt2x00dev);
1320
1321         /*
1322          * 3 - Atim ring transmit done interrupt.
1323          */
1324         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1325                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1326
1327         /*
1328          * 4 - Priority ring transmit done interrupt.
1329          */
1330         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1331                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1332
1333         /*
1334          * 5 - Tx ring transmit done interrupt.
1335          */
1336         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1337                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1338
1339         /* Enable interrupts again. */
1340         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1341                                               STATE_RADIO_IRQ_ON_ISR);
1342         return IRQ_HANDLED;
1343 }
1344
1345 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1346 {
1347         struct rt2x00_dev *rt2x00dev = dev_instance;
1348         u32 reg;
1349
1350         /*
1351          * Get the interrupt sources & saved to local variable.
1352          * Write register value back to clear pending interrupts.
1353          */
1354         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1355         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1356
1357         if (!reg)
1358                 return IRQ_NONE;
1359
1360         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1361                 return IRQ_HANDLED;
1362
1363         /* Store irqvalues for use in the interrupt thread. */
1364         rt2x00dev->irqvalue[0] = reg;
1365
1366         /* Disable interrupts, will be enabled again in the interrupt thread. */
1367         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
1368                                               STATE_RADIO_IRQ_OFF_ISR);
1369
1370         return IRQ_WAKE_THREAD;
1371 }
1372
1373 /*
1374  * Device probe functions.
1375  */
1376 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1377 {
1378         struct eeprom_93cx6 eeprom;
1379         u32 reg;
1380         u16 word;
1381         u8 *mac;
1382
1383         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1384
1385         eeprom.data = rt2x00dev;
1386         eeprom.register_read = rt2400pci_eepromregister_read;
1387         eeprom.register_write = rt2400pci_eepromregister_write;
1388         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1389             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1390         eeprom.reg_data_in = 0;
1391         eeprom.reg_data_out = 0;
1392         eeprom.reg_data_clock = 0;
1393         eeprom.reg_chip_select = 0;
1394
1395         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1396                                EEPROM_SIZE / sizeof(u16));
1397
1398         /*
1399          * Start validation of the data that has been read.
1400          */
1401         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1402         if (!is_valid_ether_addr(mac)) {
1403                 random_ether_addr(mac);
1404                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1405         }
1406
1407         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1408         if (word == 0xffff) {
1409                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1410                 return -EINVAL;
1411         }
1412
1413         return 0;
1414 }
1415
1416 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1417 {
1418         u32 reg;
1419         u16 value;
1420         u16 eeprom;
1421
1422         /*
1423          * Read EEPROM word for configuration.
1424          */
1425         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1426
1427         /*
1428          * Identify RF chipset.
1429          */
1430         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1431         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1432         rt2x00_set_chip(rt2x00dev, RT2460, value,
1433                         rt2x00_get_field32(reg, CSR0_REVISION));
1434
1435         if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1436                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1437                 return -ENODEV;
1438         }
1439
1440         /*
1441          * Identify default antenna configuration.
1442          */
1443         rt2x00dev->default_ant.tx =
1444             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1445         rt2x00dev->default_ant.rx =
1446             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1447
1448         /*
1449          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1450          * I am not 100% sure about this, but the legacy drivers do not
1451          * indicate antenna swapping in software is required when
1452          * diversity is enabled.
1453          */
1454         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1455                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1456         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1457                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1458
1459         /*
1460          * Store led mode, for correct led behaviour.
1461          */
1462 #ifdef CONFIG_RT2X00_LIB_LEDS
1463         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1464
1465         rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1466         if (value == LED_MODE_TXRX_ACTIVITY ||
1467             value == LED_MODE_DEFAULT ||
1468             value == LED_MODE_ASUS)
1469                 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1470                                    LED_TYPE_ACTIVITY);
1471 #endif /* CONFIG_RT2X00_LIB_LEDS */
1472
1473         /*
1474          * Detect if this device has an hardware controlled radio.
1475          */
1476         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1477                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1478
1479         /*
1480          * Check if the BBP tuning should be enabled.
1481          */
1482         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1483                 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
1484
1485         return 0;
1486 }
1487
1488 /*
1489  * RF value list for RF2420 & RF2421
1490  * Supports: 2.4 GHz
1491  */
1492 static const struct rf_channel rf_vals_b[] = {
1493         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1494         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1495         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1496         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1497         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1498         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1499         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1500         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1501         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1502         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1503         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1504         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1505         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1506         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1507 };
1508
1509 static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1510 {
1511         struct hw_mode_spec *spec = &rt2x00dev->spec;
1512         struct channel_info *info;
1513         char *tx_power;
1514         unsigned int i;
1515
1516         /*
1517          * Initialize all hw fields.
1518          */
1519         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1520                                IEEE80211_HW_SIGNAL_DBM |
1521                                IEEE80211_HW_SUPPORTS_PS |
1522                                IEEE80211_HW_PS_NULLFUNC_STACK;
1523
1524         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1525         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1526                                 rt2x00_eeprom_addr(rt2x00dev,
1527                                                    EEPROM_MAC_ADDR_0));
1528
1529         /*
1530          * Initialize hw_mode information.
1531          */
1532         spec->supported_bands = SUPPORT_BAND_2GHZ;
1533         spec->supported_rates = SUPPORT_RATE_CCK;
1534
1535         spec->num_channels = ARRAY_SIZE(rf_vals_b);
1536         spec->channels = rf_vals_b;
1537
1538         /*
1539          * Create channel information array
1540          */
1541         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1542         if (!info)
1543                 return -ENOMEM;
1544
1545         spec->channels_info = info;
1546
1547         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1548         for (i = 0; i < 14; i++) {
1549                 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1550                 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1551         }
1552
1553         return 0;
1554 }
1555
1556 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1557 {
1558         int retval;
1559
1560         /*
1561          * Allocate eeprom data.
1562          */
1563         retval = rt2400pci_validate_eeprom(rt2x00dev);
1564         if (retval)
1565                 return retval;
1566
1567         retval = rt2400pci_init_eeprom(rt2x00dev);
1568         if (retval)
1569                 return retval;
1570
1571         /*
1572          * Initialize hw specifications.
1573          */
1574         retval = rt2400pci_probe_hw_mode(rt2x00dev);
1575         if (retval)
1576                 return retval;
1577
1578         /*
1579          * This device requires the atim queue and DMA-mapped skbs.
1580          */
1581         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1582         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1583
1584         /*
1585          * Set the rssi offset.
1586          */
1587         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1588
1589         return 0;
1590 }
1591
1592 /*
1593  * IEEE80211 stack callback functions.
1594  */
1595 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1596                              const struct ieee80211_tx_queue_params *params)
1597 {
1598         struct rt2x00_dev *rt2x00dev = hw->priv;
1599
1600         /*
1601          * We don't support variating cw_min and cw_max variables
1602          * per queue. So by default we only configure the TX queue,
1603          * and ignore all other configurations.
1604          */
1605         if (queue != 0)
1606                 return -EINVAL;
1607
1608         if (rt2x00mac_conf_tx(hw, queue, params))
1609                 return -EINVAL;
1610
1611         /*
1612          * Write configuration to register.
1613          */
1614         rt2400pci_config_cw(rt2x00dev,
1615                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1616
1617         return 0;
1618 }
1619
1620 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1621 {
1622         struct rt2x00_dev *rt2x00dev = hw->priv;
1623         u64 tsf;
1624         u32 reg;
1625
1626         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1627         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1628         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1629         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1630
1631         return tsf;
1632 }
1633
1634 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1635 {
1636         struct rt2x00_dev *rt2x00dev = hw->priv;
1637         u32 reg;
1638
1639         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1640         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1641 }
1642
1643 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1644         .tx                     = rt2x00mac_tx,
1645         .start                  = rt2x00mac_start,
1646         .stop                   = rt2x00mac_stop,
1647         .add_interface          = rt2x00mac_add_interface,
1648         .remove_interface       = rt2x00mac_remove_interface,
1649         .config                 = rt2x00mac_config,
1650         .configure_filter       = rt2x00mac_configure_filter,
1651         .sw_scan_start          = rt2x00mac_sw_scan_start,
1652         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
1653         .get_stats              = rt2x00mac_get_stats,
1654         .bss_info_changed       = rt2x00mac_bss_info_changed,
1655         .conf_tx                = rt2400pci_conf_tx,
1656         .get_tsf                = rt2400pci_get_tsf,
1657         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1658         .rfkill_poll            = rt2x00mac_rfkill_poll,
1659         .flush                  = rt2x00mac_flush,
1660 };
1661
1662 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1663         .irq_handler            = rt2400pci_interrupt,
1664         .irq_handler_thread     = rt2400pci_interrupt_thread,
1665         .probe_hw               = rt2400pci_probe_hw,
1666         .initialize             = rt2x00pci_initialize,
1667         .uninitialize           = rt2x00pci_uninitialize,
1668         .get_entry_state        = rt2400pci_get_entry_state,
1669         .clear_entry            = rt2400pci_clear_entry,
1670         .set_device_state       = rt2400pci_set_device_state,
1671         .rfkill_poll            = rt2400pci_rfkill_poll,
1672         .link_stats             = rt2400pci_link_stats,
1673         .reset_tuner            = rt2400pci_reset_tuner,
1674         .link_tuner             = rt2400pci_link_tuner,
1675         .write_tx_desc          = rt2400pci_write_tx_desc,
1676         .write_beacon           = rt2400pci_write_beacon,
1677         .kick_tx_queue          = rt2400pci_kick_queue,
1678         .kill_tx_queue          = rt2400pci_stop_queue,
1679         .fill_rxdone            = rt2400pci_fill_rxdone,
1680         .config_filter          = rt2400pci_config_filter,
1681         .config_intf            = rt2400pci_config_intf,
1682         .config_erp             = rt2400pci_config_erp,
1683         .config_ant             = rt2400pci_config_ant,
1684         .config                 = rt2400pci_config,
1685 };
1686
1687 static const struct data_queue_desc rt2400pci_queue_rx = {
1688         .entry_num              = 24,
1689         .data_size              = DATA_FRAME_SIZE,
1690         .desc_size              = RXD_DESC_SIZE,
1691         .priv_size              = sizeof(struct queue_entry_priv_pci),
1692 };
1693
1694 static const struct data_queue_desc rt2400pci_queue_tx = {
1695         .entry_num              = 24,
1696         .data_size              = DATA_FRAME_SIZE,
1697         .desc_size              = TXD_DESC_SIZE,
1698         .priv_size              = sizeof(struct queue_entry_priv_pci),
1699 };
1700
1701 static const struct data_queue_desc rt2400pci_queue_bcn = {
1702         .entry_num              = 1,
1703         .data_size              = MGMT_FRAME_SIZE,
1704         .desc_size              = TXD_DESC_SIZE,
1705         .priv_size              = sizeof(struct queue_entry_priv_pci),
1706 };
1707
1708 static const struct data_queue_desc rt2400pci_queue_atim = {
1709         .entry_num              = 8,
1710         .data_size              = DATA_FRAME_SIZE,
1711         .desc_size              = TXD_DESC_SIZE,
1712         .priv_size              = sizeof(struct queue_entry_priv_pci),
1713 };
1714
1715 static const struct rt2x00_ops rt2400pci_ops = {
1716         .name                   = KBUILD_MODNAME,
1717         .max_sta_intf           = 1,
1718         .max_ap_intf            = 1,
1719         .eeprom_size            = EEPROM_SIZE,
1720         .rf_size                = RF_SIZE,
1721         .tx_queues              = NUM_TX_QUEUES,
1722         .extra_tx_headroom      = 0,
1723         .rx                     = &rt2400pci_queue_rx,
1724         .tx                     = &rt2400pci_queue_tx,
1725         .bcn                    = &rt2400pci_queue_bcn,
1726         .atim                   = &rt2400pci_queue_atim,
1727         .lib                    = &rt2400pci_rt2x00_ops,
1728         .hw                     = &rt2400pci_mac80211_ops,
1729 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1730         .debugfs                = &rt2400pci_rt2x00debug,
1731 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1732 };
1733
1734 /*
1735  * RT2400pci module information.
1736  */
1737 static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
1738         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1739         { 0, }
1740 };
1741
1742 MODULE_AUTHOR(DRV_PROJECT);
1743 MODULE_VERSION(DRV_VERSION);
1744 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1745 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1746 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1747 MODULE_LICENSE("GPL");
1748
1749 static struct pci_driver rt2400pci_driver = {
1750         .name           = KBUILD_MODNAME,
1751         .id_table       = rt2400pci_device_table,
1752         .probe          = rt2x00pci_probe,
1753         .remove         = __devexit_p(rt2x00pci_remove),
1754         .suspend        = rt2x00pci_suspend,
1755         .resume         = rt2x00pci_resume,
1756 };
1757
1758 static int __init rt2400pci_init(void)
1759 {
1760         return pci_register_driver(&rt2400pci_driver);
1761 }
1762
1763 static void __exit rt2400pci_exit(void)
1764 {
1765         pci_unregister_driver(&rt2400pci_driver);
1766 }
1767
1768 module_init(rt2400pci_init);
1769 module_exit(rt2400pci_exit);