Merge git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-2.6
[linux-2.6.git] / drivers / net / wireless / p54 / p54pci.c
1
2 /*
3  * Linux device driver for PCI based Prism54
4  *
5  * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6  * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
7  *
8  * Based on the islsm (softmac prism54) driver, which is:
9  * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15
16 #include <linux/init.h>
17 #include <linux/pci.h>
18 #include <linux/firmware.h>
19 #include <linux/etherdevice.h>
20 #include <linux/delay.h>
21 #include <linux/completion.h>
22 #include <net/mac80211.h>
23
24 #include "p54.h"
25 #include "lmac.h"
26 #include "p54pci.h"
27
28 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
29 MODULE_DESCRIPTION("Prism54 PCI wireless driver");
30 MODULE_LICENSE("GPL");
31 MODULE_ALIAS("prism54pci");
32 MODULE_FIRMWARE("isl3886pci");
33
34 static struct pci_device_id p54p_table[] __devinitdata = {
35         /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
36         { PCI_DEVICE(0x1260, 0x3890) },
37         /* 3COM 3CRWE154G72 Wireless LAN adapter */
38         { PCI_DEVICE(0x10b7, 0x6001) },
39         /* Intersil PRISM Indigo Wireless LAN adapter */
40         { PCI_DEVICE(0x1260, 0x3877) },
41         /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
42         { PCI_DEVICE(0x1260, 0x3886) },
43         { },
44 };
45
46 MODULE_DEVICE_TABLE(pci, p54p_table);
47
48 static int p54p_upload_firmware(struct ieee80211_hw *dev)
49 {
50         struct p54p_priv *priv = dev->priv;
51         __le32 reg;
52         int err;
53         __le32 *data;
54         u32 remains, left, device_addr;
55
56         P54P_WRITE(int_enable, cpu_to_le32(0));
57         P54P_READ(int_enable);
58         udelay(10);
59
60         reg = P54P_READ(ctrl_stat);
61         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
62         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
63         P54P_WRITE(ctrl_stat, reg);
64         P54P_READ(ctrl_stat);
65         udelay(10);
66
67         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
68         P54P_WRITE(ctrl_stat, reg);
69         wmb();
70         udelay(10);
71
72         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
73         P54P_WRITE(ctrl_stat, reg);
74         wmb();
75
76         /* wait for the firmware to reset properly */
77         mdelay(10);
78
79         err = p54_parse_firmware(dev, priv->firmware);
80         if (err)
81                 return err;
82
83         if (priv->common.fw_interface != FW_LM86) {
84                 dev_err(&priv->pdev->dev, "wrong firmware, "
85                         "please get a LM86(PCI) firmware a try again.\n");
86                 return -EINVAL;
87         }
88
89         data = (__le32 *) priv->firmware->data;
90         remains = priv->firmware->size;
91         device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
92         while (remains) {
93                 u32 i = 0;
94                 left = min((u32)0x1000, remains);
95                 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
96                 P54P_READ(int_enable);
97
98                 device_addr += 0x1000;
99                 while (i < left) {
100                         P54P_WRITE(direct_mem_win[i], *data++);
101                         i += sizeof(u32);
102                 }
103
104                 remains -= left;
105                 P54P_READ(int_enable);
106         }
107
108         reg = P54P_READ(ctrl_stat);
109         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
110         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
111         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
112         P54P_WRITE(ctrl_stat, reg);
113         P54P_READ(ctrl_stat);
114         udelay(10);
115
116         reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
117         P54P_WRITE(ctrl_stat, reg);
118         wmb();
119         udelay(10);
120
121         reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
122         P54P_WRITE(ctrl_stat, reg);
123         wmb();
124         udelay(10);
125
126         /* wait for the firmware to boot properly */
127         mdelay(100);
128
129         return 0;
130 }
131
132 static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
133         int ring_index, struct p54p_desc *ring, u32 ring_limit,
134         struct sk_buff **rx_buf)
135 {
136         struct p54p_priv *priv = dev->priv;
137         struct p54p_ring_control *ring_control = priv->ring_control;
138         u32 limit, idx, i;
139
140         idx = le32_to_cpu(ring_control->host_idx[ring_index]);
141         limit = idx;
142         limit -= le32_to_cpu(ring_control->device_idx[ring_index]);
143         limit = ring_limit - limit;
144
145         i = idx % ring_limit;
146         while (limit-- > 1) {
147                 struct p54p_desc *desc = &ring[i];
148
149                 if (!desc->host_addr) {
150                         struct sk_buff *skb;
151                         dma_addr_t mapping;
152                         skb = dev_alloc_skb(priv->common.rx_mtu + 32);
153                         if (!skb)
154                                 break;
155
156                         mapping = pci_map_single(priv->pdev,
157                                                  skb_tail_pointer(skb),
158                                                  priv->common.rx_mtu + 32,
159                                                  PCI_DMA_FROMDEVICE);
160                         desc->host_addr = cpu_to_le32(mapping);
161                         desc->device_addr = 0;  // FIXME: necessary?
162                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
163                         desc->flags = 0;
164                         rx_buf[i] = skb;
165                 }
166
167                 i++;
168                 idx++;
169                 i %= ring_limit;
170         }
171
172         wmb();
173         ring_control->host_idx[ring_index] = cpu_to_le32(idx);
174 }
175
176 static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
177         int ring_index, struct p54p_desc *ring, u32 ring_limit,
178         struct sk_buff **rx_buf)
179 {
180         struct p54p_priv *priv = dev->priv;
181         struct p54p_ring_control *ring_control = priv->ring_control;
182         struct p54p_desc *desc;
183         u32 idx, i;
184
185         i = (*index) % ring_limit;
186         (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
187         idx %= ring_limit;
188         while (i != idx) {
189                 u16 len;
190                 struct sk_buff *skb;
191                 desc = &ring[i];
192                 len = le16_to_cpu(desc->len);
193                 skb = rx_buf[i];
194
195                 if (!skb) {
196                         i++;
197                         i %= ring_limit;
198                         continue;
199                 }
200
201                 if (unlikely(len > priv->common.rx_mtu)) {
202                         if (net_ratelimit())
203                                 dev_err(&priv->pdev->dev, "rx'd frame size "
204                                         "exceeds length threshold.\n");
205
206                         len = priv->common.rx_mtu;
207                 }
208                 skb_put(skb, len);
209
210                 if (p54_rx(dev, skb)) {
211                         pci_unmap_single(priv->pdev,
212                                          le32_to_cpu(desc->host_addr),
213                                          priv->common.rx_mtu + 32,
214                                          PCI_DMA_FROMDEVICE);
215                         rx_buf[i] = NULL;
216                         desc->host_addr = 0;
217                 } else {
218                         skb_trim(skb, 0);
219                         desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
220                 }
221
222                 i++;
223                 i %= ring_limit;
224         }
225
226         p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf);
227 }
228
229 /* caller must hold priv->lock */
230 static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
231         int ring_index, struct p54p_desc *ring, u32 ring_limit,
232         void **tx_buf)
233 {
234         struct p54p_priv *priv = dev->priv;
235         struct p54p_ring_control *ring_control = priv->ring_control;
236         struct p54p_desc *desc;
237         u32 idx, i;
238
239         i = (*index) % ring_limit;
240         (*index) = idx = le32_to_cpu(ring_control->device_idx[1]);
241         idx %= ring_limit;
242
243         while (i != idx) {
244                 desc = &ring[i];
245                 if (tx_buf[i])
246                         if (FREE_AFTER_TX((struct sk_buff *) tx_buf[i]))
247                                 p54_free_skb(dev, tx_buf[i]);
248                 tx_buf[i] = NULL;
249
250                 pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
251                                  le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
252
253                 desc->host_addr = 0;
254                 desc->device_addr = 0;
255                 desc->len = 0;
256                 desc->flags = 0;
257
258                 i++;
259                 i %= ring_limit;
260         }
261 }
262
263 static void p54p_rx_tasklet(unsigned long dev_id)
264 {
265         struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
266         struct p54p_priv *priv = dev->priv;
267         struct p54p_ring_control *ring_control = priv->ring_control;
268
269         p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
270                 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
271
272         p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
273                 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
274
275         wmb();
276         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
277 }
278
279 static irqreturn_t p54p_interrupt(int irq, void *dev_id)
280 {
281         struct ieee80211_hw *dev = dev_id;
282         struct p54p_priv *priv = dev->priv;
283         struct p54p_ring_control *ring_control = priv->ring_control;
284         __le32 reg;
285
286         spin_lock(&priv->lock);
287         reg = P54P_READ(int_ident);
288         if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
289                 spin_unlock(&priv->lock);
290                 return IRQ_HANDLED;
291         }
292
293         P54P_WRITE(int_ack, reg);
294
295         reg &= P54P_READ(int_enable);
296
297         if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) {
298                 p54p_check_tx_ring(dev, &priv->tx_idx_mgmt,
299                                    3, ring_control->tx_mgmt,
300                                    ARRAY_SIZE(ring_control->tx_mgmt),
301                                    priv->tx_buf_mgmt);
302
303                 p54p_check_tx_ring(dev, &priv->tx_idx_data,
304                                    1, ring_control->tx_data,
305                                    ARRAY_SIZE(ring_control->tx_data),
306                                    priv->tx_buf_data);
307
308                 tasklet_schedule(&priv->rx_tasklet);
309
310         } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
311                 complete(&priv->boot_comp);
312
313         spin_unlock(&priv->lock);
314
315         return reg ? IRQ_HANDLED : IRQ_NONE;
316 }
317
318 static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
319 {
320         struct p54p_priv *priv = dev->priv;
321         struct p54p_ring_control *ring_control = priv->ring_control;
322         unsigned long flags;
323         struct p54p_desc *desc;
324         dma_addr_t mapping;
325         u32 device_idx, idx, i;
326
327         spin_lock_irqsave(&priv->lock, flags);
328
329         device_idx = le32_to_cpu(ring_control->device_idx[1]);
330         idx = le32_to_cpu(ring_control->host_idx[1]);
331         i = idx % ARRAY_SIZE(ring_control->tx_data);
332
333         priv->tx_buf_data[i] = skb;
334         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
335                                  PCI_DMA_TODEVICE);
336         desc = &ring_control->tx_data[i];
337         desc->host_addr = cpu_to_le32(mapping);
338         desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
339         desc->len = cpu_to_le16(skb->len);
340         desc->flags = 0;
341
342         wmb();
343         ring_control->host_idx[1] = cpu_to_le32(idx + 1);
344         spin_unlock_irqrestore(&priv->lock, flags);
345
346         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
347         P54P_READ(dev_int);
348 }
349
350 static void p54p_stop(struct ieee80211_hw *dev)
351 {
352         struct p54p_priv *priv = dev->priv;
353         struct p54p_ring_control *ring_control = priv->ring_control;
354         unsigned int i;
355         struct p54p_desc *desc;
356
357         tasklet_kill(&priv->rx_tasklet);
358
359         P54P_WRITE(int_enable, cpu_to_le32(0));
360         P54P_READ(int_enable);
361         udelay(10);
362
363         free_irq(priv->pdev->irq, dev);
364
365         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
366
367         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
368                 desc = &ring_control->rx_data[i];
369                 if (desc->host_addr)
370                         pci_unmap_single(priv->pdev,
371                                          le32_to_cpu(desc->host_addr),
372                                          priv->common.rx_mtu + 32,
373                                          PCI_DMA_FROMDEVICE);
374                 kfree_skb(priv->rx_buf_data[i]);
375                 priv->rx_buf_data[i] = NULL;
376         }
377
378         for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
379                 desc = &ring_control->rx_mgmt[i];
380                 if (desc->host_addr)
381                         pci_unmap_single(priv->pdev,
382                                          le32_to_cpu(desc->host_addr),
383                                          priv->common.rx_mtu + 32,
384                                          PCI_DMA_FROMDEVICE);
385                 kfree_skb(priv->rx_buf_mgmt[i]);
386                 priv->rx_buf_mgmt[i] = NULL;
387         }
388
389         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
390                 desc = &ring_control->tx_data[i];
391                 if (desc->host_addr)
392                         pci_unmap_single(priv->pdev,
393                                          le32_to_cpu(desc->host_addr),
394                                          le16_to_cpu(desc->len),
395                                          PCI_DMA_TODEVICE);
396
397                 p54_free_skb(dev, priv->tx_buf_data[i]);
398                 priv->tx_buf_data[i] = NULL;
399         }
400
401         for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
402                 desc = &ring_control->tx_mgmt[i];
403                 if (desc->host_addr)
404                         pci_unmap_single(priv->pdev,
405                                          le32_to_cpu(desc->host_addr),
406                                          le16_to_cpu(desc->len),
407                                          PCI_DMA_TODEVICE);
408
409                 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
410                 priv->tx_buf_mgmt[i] = NULL;
411         }
412
413         memset(ring_control, 0, sizeof(*ring_control));
414 }
415
416 static int p54p_open(struct ieee80211_hw *dev)
417 {
418         struct p54p_priv *priv = dev->priv;
419         int err;
420
421         init_completion(&priv->boot_comp);
422         err = request_irq(priv->pdev->irq, p54p_interrupt,
423                           IRQF_SHARED, "p54pci", dev);
424         if (err) {
425                 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
426                 return err;
427         }
428
429         memset(priv->ring_control, 0, sizeof(*priv->ring_control));
430         err = p54p_upload_firmware(dev);
431         if (err) {
432                 free_irq(priv->pdev->irq, dev);
433                 return err;
434         }
435         priv->rx_idx_data = priv->tx_idx_data = 0;
436         priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
437
438         p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
439                 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data);
440
441         p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
442                 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt);
443
444         P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
445         P54P_READ(ring_control_base);
446         wmb();
447         udelay(10);
448
449         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
450         P54P_READ(int_enable);
451         wmb();
452         udelay(10);
453
454         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
455         P54P_READ(dev_int);
456
457         if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
458                 printk(KERN_ERR "%s: Cannot boot firmware!\n",
459                        wiphy_name(dev->wiphy));
460                 p54p_stop(dev);
461                 return -ETIMEDOUT;
462         }
463
464         P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
465         P54P_READ(int_enable);
466         wmb();
467         udelay(10);
468
469         P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
470         P54P_READ(dev_int);
471         wmb();
472         udelay(10);
473
474         return 0;
475 }
476
477 static int __devinit p54p_probe(struct pci_dev *pdev,
478                                 const struct pci_device_id *id)
479 {
480         struct p54p_priv *priv;
481         struct ieee80211_hw *dev;
482         unsigned long mem_addr, mem_len;
483         int err;
484
485         err = pci_enable_device(pdev);
486         if (err) {
487                 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
488                 return err;
489         }
490
491         mem_addr = pci_resource_start(pdev, 0);
492         mem_len = pci_resource_len(pdev, 0);
493         if (mem_len < sizeof(struct p54p_csr)) {
494                 dev_err(&pdev->dev, "Too short PCI resources\n");
495                 goto err_disable_dev;
496         }
497
498         err = pci_request_regions(pdev, "p54pci");
499         if (err) {
500                 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
501                 goto err_disable_dev;
502         }
503
504         if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
505             pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
506                 dev_err(&pdev->dev, "No suitable DMA available\n");
507                 goto err_free_reg;
508         }
509
510         pci_set_master(pdev);
511         pci_try_set_mwi(pdev);
512
513         pci_write_config_byte(pdev, 0x40, 0);
514         pci_write_config_byte(pdev, 0x41, 0);
515
516         dev = p54_init_common(sizeof(*priv));
517         if (!dev) {
518                 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
519                 err = -ENOMEM;
520                 goto err_free_reg;
521         }
522
523         priv = dev->priv;
524         priv->pdev = pdev;
525
526         SET_IEEE80211_DEV(dev, &pdev->dev);
527         pci_set_drvdata(pdev, dev);
528
529         priv->map = ioremap(mem_addr, mem_len);
530         if (!priv->map) {
531                 dev_err(&pdev->dev, "Cannot map device memory\n");
532                 err = -ENOMEM;
533                 goto err_free_dev;
534         }
535
536         priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
537                                                   &priv->ring_control_dma);
538         if (!priv->ring_control) {
539                 dev_err(&pdev->dev, "Cannot allocate rings\n");
540                 err = -ENOMEM;
541                 goto err_iounmap;
542         }
543         priv->common.open = p54p_open;
544         priv->common.stop = p54p_stop;
545         priv->common.tx = p54p_tx;
546
547         spin_lock_init(&priv->lock);
548         tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev);
549
550         err = request_firmware(&priv->firmware, "isl3886pci",
551                                &priv->pdev->dev);
552         if (err) {
553                 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
554                 err = request_firmware(&priv->firmware, "isl3886",
555                                        &priv->pdev->dev);
556                 if (err)
557                         goto err_free_common;
558         }
559
560         err = p54p_open(dev);
561         if (err)
562                 goto err_free_common;
563         err = p54_read_eeprom(dev);
564         p54p_stop(dev);
565         if (err)
566                 goto err_free_common;
567
568         err = p54_register_common(dev, &pdev->dev);
569         if (err)
570                 goto err_free_common;
571
572         return 0;
573
574  err_free_common:
575         release_firmware(priv->firmware);
576         pci_free_consistent(pdev, sizeof(*priv->ring_control),
577                             priv->ring_control, priv->ring_control_dma);
578
579  err_iounmap:
580         iounmap(priv->map);
581
582  err_free_dev:
583         pci_set_drvdata(pdev, NULL);
584         p54_free_common(dev);
585
586  err_free_reg:
587         pci_release_regions(pdev);
588  err_disable_dev:
589         pci_disable_device(pdev);
590         return err;
591 }
592
593 static void __devexit p54p_remove(struct pci_dev *pdev)
594 {
595         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
596         struct p54p_priv *priv;
597
598         if (!dev)
599                 return;
600
601         p54_unregister_common(dev);
602         priv = dev->priv;
603         release_firmware(priv->firmware);
604         pci_free_consistent(pdev, sizeof(*priv->ring_control),
605                             priv->ring_control, priv->ring_control_dma);
606         iounmap(priv->map);
607         pci_release_regions(pdev);
608         pci_disable_device(pdev);
609         p54_free_common(dev);
610 }
611
612 #ifdef CONFIG_PM
613 static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
614 {
615         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
616         struct p54p_priv *priv = dev->priv;
617
618         if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
619                 ieee80211_stop_queues(dev);
620                 p54p_stop(dev);
621         }
622
623         pci_save_state(pdev);
624         pci_set_power_state(pdev, pci_choose_state(pdev, state));
625         return 0;
626 }
627
628 static int p54p_resume(struct pci_dev *pdev)
629 {
630         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
631         struct p54p_priv *priv = dev->priv;
632
633         pci_set_power_state(pdev, PCI_D0);
634         pci_restore_state(pdev);
635
636         if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
637                 p54p_open(dev);
638                 ieee80211_wake_queues(dev);
639         }
640
641         return 0;
642 }
643 #endif /* CONFIG_PM */
644
645 static struct pci_driver p54p_driver = {
646         .name           = "p54pci",
647         .id_table       = p54p_table,
648         .probe          = p54p_probe,
649         .remove         = __devexit_p(p54p_remove),
650 #ifdef CONFIG_PM
651         .suspend        = p54p_suspend,
652         .resume         = p54p_resume,
653 #endif /* CONFIG_PM */
654 };
655
656 static int __init p54p_init(void)
657 {
658         return pci_register_driver(&p54p_driver);
659 }
660
661 static void __exit p54p_exit(void)
662 {
663         pci_unregister_driver(&p54p_driver);
664 }
665
666 module_init(p54p_init);
667 module_exit(p54p_exit);