Merge branch 'master' of github.com:davem330/net
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-trans-tx-pcie.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project, as well
6  * as portions of the ieee80211 subsystem header files.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of version 2 of the GNU General Public License as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20  *
21  * The full GNU General Public License is included in this distribution in the
22  * file called LICENSE.
23  *
24  * Contact Information:
25  *  Intel Linux Wireless <ilw@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
32
33 /* TODO: remove include to iwl-dev.h */
34 #include "iwl-dev.h"
35 #include "iwl-debug.h"
36 #include "iwl-csr.h"
37 #include "iwl-prph.h"
38 #include "iwl-io.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-helpers.h"
41 #include "iwl-trans-int-pcie.h"
42
43 #define IWL_TX_CRC_SIZE 4
44 #define IWL_TX_DELIMITER_SIZE 4
45
46 /**
47  * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
48  */
49 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
50                                            struct iwl_tx_queue *txq,
51                                            u16 byte_cnt)
52 {
53         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
54         struct iwl_trans_pcie *trans_pcie =
55                 IWL_TRANS_GET_PCIE_TRANS(trans);
56         int write_ptr = txq->q.write_ptr;
57         int txq_id = txq->q.id;
58         u8 sec_ctl = 0;
59         u8 sta_id = 0;
60         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
61         __le16 bc_ent;
62
63         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
64
65         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
66
67         sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
68         sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
69
70         switch (sec_ctl & TX_CMD_SEC_MSK) {
71         case TX_CMD_SEC_CCM:
72                 len += CCMP_MIC_LEN;
73                 break;
74         case TX_CMD_SEC_TKIP:
75                 len += TKIP_ICV_LEN;
76                 break;
77         case TX_CMD_SEC_WEP:
78                 len += WEP_IV_LEN + WEP_ICV_LEN;
79                 break;
80         }
81
82         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
83
84         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
85
86         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
87                 scd_bc_tbl[txq_id].
88                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
89 }
90
91 /**
92  * iwl_txq_update_write_ptr - Send new write index to hardware
93  */
94 void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
95 {
96         u32 reg = 0;
97         int txq_id = txq->q.id;
98
99         if (txq->need_update == 0)
100                 return;
101
102         if (hw_params(trans).shadow_reg_enable) {
103                 /* shadow register enabled */
104                 iwl_write32(bus(trans), HBUS_TARG_WRPTR,
105                             txq->q.write_ptr | (txq_id << 8));
106         } else {
107                 /* if we're trying to save power */
108                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
109                         /* wake up nic if it's powered down ...
110                          * uCode will wake up, and interrupt us again, so next
111                          * time we'll skip this part. */
112                         reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
113
114                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
115                                 IWL_DEBUG_INFO(trans,
116                                         "Tx queue %d requesting wakeup,"
117                                         " GP1 = 0x%x\n", txq_id, reg);
118                                 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
119                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
120                                 return;
121                         }
122
123                         iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
124                                      txq->q.write_ptr | (txq_id << 8));
125
126                 /*
127                  * else not in power-save mode,
128                  * uCode will never sleep when we're
129                  * trying to tx (during RFKILL, we're not trying to tx).
130                  */
131                 } else
132                         iwl_write32(bus(trans), HBUS_TARG_WRPTR,
133                                     txq->q.write_ptr | (txq_id << 8));
134         }
135         txq->need_update = 0;
136 }
137
138 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
139 {
140         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
141
142         dma_addr_t addr = get_unaligned_le32(&tb->lo);
143         if (sizeof(dma_addr_t) > sizeof(u32))
144                 addr |=
145                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
146
147         return addr;
148 }
149
150 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
151 {
152         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
153
154         return le16_to_cpu(tb->hi_n_len) >> 4;
155 }
156
157 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
158                                   dma_addr_t addr, u16 len)
159 {
160         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
161         u16 hi_n_len = len << 4;
162
163         put_unaligned_le32(addr, &tb->lo);
164         if (sizeof(dma_addr_t) > sizeof(u32))
165                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
166
167         tb->hi_n_len = cpu_to_le16(hi_n_len);
168
169         tfd->num_tbs = idx + 1;
170 }
171
172 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
173 {
174         return tfd->num_tbs & 0x1f;
175 }
176
177 static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
178                      struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
179 {
180         int i;
181         int num_tbs;
182
183         /* Sanity check on number of chunks */
184         num_tbs = iwl_tfd_get_num_tbs(tfd);
185
186         if (num_tbs >= IWL_NUM_OF_TBS) {
187                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
188                 /* @todo issue fatal error, it is quite serious situation */
189                 return;
190         }
191
192         /* Unmap tx_cmd */
193         if (num_tbs)
194                 dma_unmap_single(bus(trans)->dev,
195                                 dma_unmap_addr(meta, mapping),
196                                 dma_unmap_len(meta, len),
197                                 DMA_BIDIRECTIONAL);
198
199         /* Unmap chunks, if any. */
200         for (i = 1; i < num_tbs; i++)
201                 dma_unmap_single(bus(trans)->dev, iwl_tfd_tb_get_addr(tfd, i),
202                                 iwl_tfd_tb_get_len(tfd, i), dma_dir);
203 }
204
205 /**
206  * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
207  * @trans - transport private data
208  * @txq - tx queue
209  * @index - the index of the TFD to be freed
210  *
211  * Does NOT advance any TFD circular buffer read/write indexes
212  * Does NOT free the TFD itself (which is within circular buffer)
213  */
214 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
215         int index)
216 {
217         struct iwl_tfd *tfd_tmp = txq->tfds;
218
219         iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index],
220                          DMA_TO_DEVICE);
221
222         /* free SKB */
223         if (txq->skbs) {
224                 struct sk_buff *skb;
225
226                 skb = txq->skbs[index];
227
228                 /* can be called from irqs-disabled context */
229                 if (skb) {
230                         dev_kfree_skb_any(skb);
231                         txq->skbs[index] = NULL;
232                 }
233         }
234 }
235
236 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
237                                  struct iwl_tx_queue *txq,
238                                  dma_addr_t addr, u16 len,
239                                  u8 reset)
240 {
241         struct iwl_queue *q;
242         struct iwl_tfd *tfd, *tfd_tmp;
243         u32 num_tbs;
244
245         q = &txq->q;
246         tfd_tmp = txq->tfds;
247         tfd = &tfd_tmp[q->write_ptr];
248
249         if (reset)
250                 memset(tfd, 0, sizeof(*tfd));
251
252         num_tbs = iwl_tfd_get_num_tbs(tfd);
253
254         /* Each TFD can point to a maximum 20 Tx buffers */
255         if (num_tbs >= IWL_NUM_OF_TBS) {
256                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
257                           IWL_NUM_OF_TBS);
258                 return -EINVAL;
259         }
260
261         if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
262                 return -EINVAL;
263
264         if (unlikely(addr & ~IWL_TX_DMA_MASK))
265                 IWL_ERR(trans, "Unaligned address = %llx\n",
266                           (unsigned long long)addr);
267
268         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
269
270         return 0;
271 }
272
273 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
274  * DMA services
275  *
276  * Theory of operation
277  *
278  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
279  * of buffer descriptors, each of which points to one or more data buffers for
280  * the device to read from or fill.  Driver and device exchange status of each
281  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
282  * entries in each circular buffer, to protect against confusing empty and full
283  * queue states.
284  *
285  * The device reads or writes the data in the queues via the device's several
286  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
287  *
288  * For Tx queue, there are low mark and high mark limits. If, after queuing
289  * the packet for Tx, free space become < low mark, Tx queue stopped. When
290  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
291  * Tx queue resumed.
292  *
293  ***************************************************/
294
295 int iwl_queue_space(const struct iwl_queue *q)
296 {
297         int s = q->read_ptr - q->write_ptr;
298
299         if (q->read_ptr > q->write_ptr)
300                 s -= q->n_bd;
301
302         if (s <= 0)
303                 s += q->n_window;
304         /* keep some reserve to not confuse empty and full situations */
305         s -= 2;
306         if (s < 0)
307                 s = 0;
308         return s;
309 }
310
311 /**
312  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
313  */
314 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
315 {
316         q->n_bd = count;
317         q->n_window = slots_num;
318         q->id = id;
319
320         /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
321          * and iwl_queue_dec_wrap are broken. */
322         if (WARN_ON(!is_power_of_2(count)))
323                 return -EINVAL;
324
325         /* slots_num must be power-of-two size, otherwise
326          * get_cmd_index is broken. */
327         if (WARN_ON(!is_power_of_2(slots_num)))
328                 return -EINVAL;
329
330         q->low_mark = q->n_window / 4;
331         if (q->low_mark < 4)
332                 q->low_mark = 4;
333
334         q->high_mark = q->n_window / 8;
335         if (q->high_mark < 2)
336                 q->high_mark = 2;
337
338         q->write_ptr = q->read_ptr = 0;
339
340         return 0;
341 }
342
343 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
344                                           struct iwl_tx_queue *txq)
345 {
346         struct iwl_trans_pcie *trans_pcie =
347                 IWL_TRANS_GET_PCIE_TRANS(trans);
348         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
349         int txq_id = txq->q.id;
350         int read_ptr = txq->q.read_ptr;
351         u8 sta_id = 0;
352         __le16 bc_ent;
353
354         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
355
356         if (txq_id != trans->shrd->cmd_queue)
357                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
358
359         bc_ent = cpu_to_le16(1 | (sta_id << 12));
360         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
361
362         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
363                 scd_bc_tbl[txq_id].
364                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
365 }
366
367 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
368                                         u16 txq_id)
369 {
370         u32 tbl_dw_addr;
371         u32 tbl_dw;
372         u16 scd_q2ratid;
373
374         struct iwl_trans_pcie *trans_pcie =
375                 IWL_TRANS_GET_PCIE_TRANS(trans);
376
377         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
378
379         tbl_dw_addr = trans_pcie->scd_base_addr +
380                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
381
382         tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr);
383
384         if (txq_id & 0x1)
385                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
386         else
387                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
388
389         iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw);
390
391         return 0;
392 }
393
394 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
395 {
396         /* Simply stop the queue, but don't change any configuration;
397          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
398         iwl_write_prph(bus(trans),
399                 SCD_QUEUE_STATUS_BITS(txq_id),
400                 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
401                 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
402 }
403
404 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
405                                 int txq_id, u32 index)
406 {
407         iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
408                         (index & 0xff) | (txq_id << 8));
409         iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index);
410 }
411
412 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
413                                         struct iwl_tx_queue *txq,
414                                         int tx_fifo_id, int scd_retry)
415 {
416         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
417         int txq_id = txq->q.id;
418         int active =
419                 test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0;
420
421         iwl_write_prph(bus(trans), SCD_QUEUE_STATUS_BITS(txq_id),
422                         (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
423                         (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
424                         (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
425                         SCD_QUEUE_STTS_REG_MSK);
426
427         txq->sched_retry = scd_retry;
428
429         IWL_DEBUG_INFO(trans, "%s %s Queue %d on FIFO %d\n",
430                        active ? "Activate" : "Deactivate",
431                        scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
432 }
433
434 static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
435                                     u8 ctx, u16 tid)
436 {
437         const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx];
438         if (likely(tid < ARRAY_SIZE(tid_to_ac)))
439                 return ac_to_fifo[tid_to_ac[tid]];
440
441         /* no support for TIDs 8-15 yet */
442         return -EINVAL;
443 }
444
445 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
446                                  enum iwl_rxon_context_id ctx, int sta_id,
447                                  int tid, int frame_limit)
448 {
449         int tx_fifo, txq_id, ssn_idx;
450         u16 ra_tid;
451         unsigned long flags;
452         struct iwl_tid_data *tid_data;
453
454         struct iwl_trans_pcie *trans_pcie =
455                 IWL_TRANS_GET_PCIE_TRANS(trans);
456
457         if (WARN_ON(sta_id == IWL_INVALID_STATION))
458                 return;
459         if (WARN_ON(tid >= IWL_MAX_TID_COUNT))
460                 return;
461
462         tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid);
463         if (WARN_ON(tx_fifo < 0)) {
464                 IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo);
465                 return;
466         }
467
468         spin_lock_irqsave(&trans->shrd->sta_lock, flags);
469         tid_data = &trans->shrd->tid_data[sta_id][tid];
470         ssn_idx = SEQ_TO_SN(tid_data->seq_number);
471         txq_id = tid_data->agg.txq_id;
472         spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
473
474         ra_tid = BUILD_RAxTID(sta_id, tid);
475
476         spin_lock_irqsave(&trans->shrd->lock, flags);
477
478         /* Stop this Tx queue before configuring it */
479         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
480
481         /* Map receiver-address / traffic-ID to this queue */
482         iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
483
484         /* Set this queue as a chain-building queue */
485         iwl_set_bits_prph(bus(trans), SCD_QUEUECHAIN_SEL, (1<<txq_id));
486
487         /* enable aggregations for the queue */
488         iwl_set_bits_prph(bus(trans), SCD_AGGR_SEL, (1<<txq_id));
489
490         /* Place first TFD at index corresponding to start sequence number.
491          * Assumes that ssn_idx is valid (!= 0xFFF) */
492         trans_pcie->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
493         trans_pcie->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
494         iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
495
496         /* Set up Tx window size and frame limit for this queue */
497         iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
498                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
499                         sizeof(u32),
500                         ((frame_limit <<
501                         SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
502                         SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
503                         ((frame_limit <<
504                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
505                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
506
507         iwl_set_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
508
509         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
510         iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
511                                         tx_fifo, 1);
512
513         trans_pcie->txq[txq_id].sta_id = sta_id;
514         trans_pcie->txq[txq_id].tid = tid;
515
516         spin_unlock_irqrestore(&trans->shrd->lock, flags);
517 }
518
519 /*
520  * Find first available (lowest unused) Tx Queue, mark it "active".
521  * Called only when finding queue for aggregation.
522  * Should never return anything < 7, because they should already
523  * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
524  */
525 static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans)
526 {
527         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
528         int txq_id;
529
530         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
531                 if (!test_and_set_bit(txq_id,
532                                         &trans_pcie->txq_ctx_active_msk))
533                         return txq_id;
534         return -1;
535 }
536
537 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
538                                 enum iwl_rxon_context_id ctx, int sta_id,
539                                 int tid, u16 *ssn)
540 {
541         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
542         struct iwl_tid_data *tid_data;
543         unsigned long flags;
544         int txq_id;
545
546         txq_id = iwlagn_txq_ctx_activate_free(trans);
547         if (txq_id == -1) {
548                 IWL_ERR(trans, "No free aggregation queue available\n");
549                 return -ENXIO;
550         }
551
552         spin_lock_irqsave(&trans->shrd->sta_lock, flags);
553         tid_data = &trans->shrd->tid_data[sta_id][tid];
554         *ssn = SEQ_TO_SN(tid_data->seq_number);
555         tid_data->agg.txq_id = txq_id;
556         iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id);
557
558         tid_data = &trans->shrd->tid_data[sta_id][tid];
559         if (tid_data->tfds_in_queue == 0) {
560                 IWL_DEBUG_HT(trans, "HW queue is empty\n");
561                 tid_data->agg.state = IWL_AGG_ON;
562                 iwl_start_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid);
563         } else {
564                 IWL_DEBUG_HT(trans, "HW queue is NOT empty: %d packets in HW"
565                              "queue\n", tid_data->tfds_in_queue);
566                 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
567         }
568         spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
569
570         return 0;
571 }
572
573 void iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id)
574 {
575         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
576         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
577
578         iwl_clear_bits_prph(bus(trans), SCD_AGGR_SEL, (1 << txq_id));
579
580         trans_pcie->txq[txq_id].q.read_ptr = 0;
581         trans_pcie->txq[txq_id].q.write_ptr = 0;
582         /* supposes that ssn_idx is valid (!= 0xFFF) */
583         iwl_trans_set_wr_ptrs(trans, txq_id, 0);
584
585         iwl_clear_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
586         iwl_txq_ctx_deactivate(trans_pcie, txq_id);
587         iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0);
588 }
589
590 int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
591                                   enum iwl_rxon_context_id ctx, int sta_id,
592                                   int tid)
593 {
594         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
595         unsigned long flags;
596         int read_ptr, write_ptr;
597         struct iwl_tid_data *tid_data;
598         int txq_id;
599
600         spin_lock_irqsave(&trans->shrd->sta_lock, flags);
601
602         tid_data = &trans->shrd->tid_data[sta_id][tid];
603         txq_id = tid_data->agg.txq_id;
604
605         if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
606             (IWLAGN_FIRST_AMPDU_QUEUE +
607                 hw_params(trans).num_ampdu_queues <= txq_id)) {
608                 IWL_ERR(trans,
609                         "queue number out of range: %d, must be %d to %d\n",
610                         txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
611                         IWLAGN_FIRST_AMPDU_QUEUE +
612                         hw_params(trans).num_ampdu_queues - 1);
613                 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
614                 return -EINVAL;
615         }
616
617         switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
618         case IWL_EMPTYING_HW_QUEUE_ADDBA:
619                 /*
620                 * This can happen if the peer stops aggregation
621                 * again before we've had a chance to drain the
622                 * queue we selected previously, i.e. before the
623                 * session was really started completely.
624                 */
625                 IWL_DEBUG_HT(trans, "AGG stop before setup done\n");
626                 goto turn_off;
627         case IWL_AGG_ON:
628                 break;
629         default:
630                 IWL_WARN(trans, "Stopping AGG while state not ON"
631                                 "or starting\n");
632         }
633
634         write_ptr = trans_pcie->txq[txq_id].q.write_ptr;
635         read_ptr = trans_pcie->txq[txq_id].q.read_ptr;
636
637         /* The queue is not empty */
638         if (write_ptr != read_ptr) {
639                 IWL_DEBUG_HT(trans, "Stopping a non empty AGG HW QUEUE\n");
640                 trans->shrd->tid_data[sta_id][tid].agg.state =
641                         IWL_EMPTYING_HW_QUEUE_DELBA;
642                 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
643                 return 0;
644         }
645
646         IWL_DEBUG_HT(trans, "HW queue is empty\n");
647 turn_off:
648         trans->shrd->tid_data[sta_id][tid].agg.state = IWL_AGG_OFF;
649
650         /* do not restore/save irqs */
651         spin_unlock(&trans->shrd->sta_lock);
652         spin_lock(&trans->shrd->lock);
653
654         iwl_trans_pcie_txq_agg_disable(trans, txq_id);
655
656         spin_unlock_irqrestore(&trans->shrd->lock, flags);
657
658         iwl_stop_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid);
659
660         return 0;
661 }
662
663 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
664
665 /**
666  * iwl_enqueue_hcmd - enqueue a uCode command
667  * @priv: device private data point
668  * @cmd: a point to the ucode command structure
669  *
670  * The function returns < 0 values to indicate the operation is
671  * failed. On success, it turns the index (> 0) of command in the
672  * command queue.
673  */
674 static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
675 {
676         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
677         struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
678         struct iwl_queue *q = &txq->q;
679         struct iwl_device_cmd *out_cmd;
680         struct iwl_cmd_meta *out_meta;
681         dma_addr_t phys_addr;
682         unsigned long flags;
683         u32 idx;
684         u16 copy_size, cmd_size;
685         bool is_ct_kill = false;
686         bool had_nocopy = false;
687         int i;
688         u8 *cmd_dest;
689 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
690         const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
691         int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
692         int trace_idx;
693 #endif
694
695         if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
696                 IWL_WARN(trans, "fw recovery, no hcmd send\n");
697                 return -EIO;
698         }
699
700         if ((trans->shrd->ucode_owner == IWL_OWNERSHIP_TM) &&
701             !(cmd->flags & CMD_ON_DEMAND)) {
702                 IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n");
703                 return -EIO;
704         }
705
706         copy_size = sizeof(out_cmd->hdr);
707         cmd_size = sizeof(out_cmd->hdr);
708
709         /* need one for the header if the first is NOCOPY */
710         BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
711
712         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
713                 if (!cmd->len[i])
714                         continue;
715                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
716                         had_nocopy = true;
717                 } else {
718                         /* NOCOPY must not be followed by normal! */
719                         if (WARN_ON(had_nocopy))
720                                 return -EINVAL;
721                         copy_size += cmd->len[i];
722                 }
723                 cmd_size += cmd->len[i];
724         }
725
726         /*
727          * If any of the command structures end up being larger than
728          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
729          * allocated into separate TFDs, then we will need to
730          * increase the size of the buffers.
731          */
732         if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
733                 return -EINVAL;
734
735         if (iwl_is_rfkill(trans->shrd) || iwl_is_ctkill(trans->shrd)) {
736                 IWL_WARN(trans, "Not sending command - %s KILL\n",
737                          iwl_is_rfkill(trans->shrd) ? "RF" : "CT");
738                 return -EIO;
739         }
740
741         spin_lock_irqsave(&trans->hcmd_lock, flags);
742
743         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
744                 spin_unlock_irqrestore(&trans->hcmd_lock, flags);
745
746                 IWL_ERR(trans, "No space in command queue\n");
747                 is_ct_kill = iwl_check_for_ct_kill(priv(trans));
748                 if (!is_ct_kill) {
749                         IWL_ERR(trans, "Restarting adapter queue is full\n");
750                         iwlagn_fw_error(priv(trans), false);
751                 }
752                 return -ENOSPC;
753         }
754
755         idx = get_cmd_index(q, q->write_ptr);
756         out_cmd = txq->cmd[idx];
757         out_meta = &txq->meta[idx];
758
759         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
760         if (cmd->flags & CMD_WANT_SKB)
761                 out_meta->source = cmd;
762         if (cmd->flags & CMD_ASYNC)
763                 out_meta->callback = cmd->callback;
764
765         /* set up the header */
766
767         out_cmd->hdr.cmd = cmd->id;
768         out_cmd->hdr.flags = 0;
769         out_cmd->hdr.sequence =
770                 cpu_to_le16(QUEUE_TO_SEQ(trans->shrd->cmd_queue) |
771                                          INDEX_TO_SEQ(q->write_ptr));
772
773         /* and copy the data that needs to be copied */
774
775         cmd_dest = &out_cmd->cmd.payload[0];
776         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
777                 if (!cmd->len[i])
778                         continue;
779                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
780                         break;
781                 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
782                 cmd_dest += cmd->len[i];
783         }
784
785         IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, "
786                         "%d bytes at %d[%d]:%d\n",
787                         get_cmd_string(out_cmd->hdr.cmd),
788                         out_cmd->hdr.cmd,
789                         le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
790                         q->write_ptr, idx, trans->shrd->cmd_queue);
791
792         phys_addr = dma_map_single(bus(trans)->dev, &out_cmd->hdr, copy_size,
793                                 DMA_BIDIRECTIONAL);
794         if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
795                 idx = -ENOMEM;
796                 goto out;
797         }
798
799         dma_unmap_addr_set(out_meta, mapping, phys_addr);
800         dma_unmap_len_set(out_meta, len, copy_size);
801
802         iwlagn_txq_attach_buf_to_tfd(trans, txq,
803                                         phys_addr, copy_size, 1);
804 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
805         trace_bufs[0] = &out_cmd->hdr;
806         trace_lens[0] = copy_size;
807         trace_idx = 1;
808 #endif
809
810         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
811                 if (!cmd->len[i])
812                         continue;
813                 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
814                         continue;
815                 phys_addr = dma_map_single(bus(trans)->dev,
816                                            (void *)cmd->data[i],
817                                            cmd->len[i], DMA_BIDIRECTIONAL);
818                 if (dma_mapping_error(bus(trans)->dev, phys_addr)) {
819                         iwlagn_unmap_tfd(trans, out_meta,
820                                          &txq->tfds[q->write_ptr],
821                                          DMA_BIDIRECTIONAL);
822                         idx = -ENOMEM;
823                         goto out;
824                 }
825
826                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
827                                              cmd->len[i], 0);
828 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
829                 trace_bufs[trace_idx] = cmd->data[i];
830                 trace_lens[trace_idx] = cmd->len[i];
831                 trace_idx++;
832 #endif
833         }
834
835         out_meta->flags = cmd->flags;
836
837         txq->need_update = 1;
838
839         /* check that tracing gets all possible blocks */
840         BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
841 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
842         trace_iwlwifi_dev_hcmd(priv(trans), cmd->flags,
843                                trace_bufs[0], trace_lens[0],
844                                trace_bufs[1], trace_lens[1],
845                                trace_bufs[2], trace_lens[2]);
846 #endif
847
848         /* Increment and update queue's write index */
849         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
850         iwl_txq_update_write_ptr(trans, txq);
851
852  out:
853         spin_unlock_irqrestore(&trans->hcmd_lock, flags);
854         return idx;
855 }
856
857 /**
858  * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
859  *
860  * When FW advances 'R' index, all entries between old and new 'R' index
861  * need to be reclaimed. As result, some free space forms.  If there is
862  * enough free space (> low mark), wake the stack that feeds us.
863  */
864 static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id,
865                                    int idx)
866 {
867         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
868         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
869         struct iwl_queue *q = &txq->q;
870         int nfreed = 0;
871
872         if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
873                 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
874                           "index %d is out of range [0-%d] %d %d.\n", __func__,
875                           txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
876                 return;
877         }
878
879         for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
880              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
881
882                 if (nfreed++ > 0) {
883                         IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx,
884                                         q->write_ptr, q->read_ptr);
885                         iwlagn_fw_error(priv(trans), false);
886                 }
887
888         }
889 }
890
891 /**
892  * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
893  * @rxb: Rx buffer to reclaim
894  *
895  * If an Rx buffer has an async callback associated with it the callback
896  * will be executed.  The attached skb (if present) will only be freed
897  * if the callback returns 1
898  */
899 void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_mem_buffer *rxb)
900 {
901         struct iwl_rx_packet *pkt = rxb_addr(rxb);
902         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
903         int txq_id = SEQ_TO_QUEUE(sequence);
904         int index = SEQ_TO_INDEX(sequence);
905         int cmd_index;
906         struct iwl_device_cmd *cmd;
907         struct iwl_cmd_meta *meta;
908         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
909         struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
910         unsigned long flags;
911
912         /* If a Tx command is being handled and it isn't in the actual
913          * command queue then there a command routing bug has been introduced
914          * in the queue management code. */
915         if (WARN(txq_id != trans->shrd->cmd_queue,
916                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
917                   txq_id, trans->shrd->cmd_queue, sequence,
918                   trans_pcie->txq[trans->shrd->cmd_queue].q.read_ptr,
919                   trans_pcie->txq[trans->shrd->cmd_queue].q.write_ptr)) {
920                 iwl_print_hex_error(trans, pkt, 32);
921                 return;
922         }
923
924         cmd_index = get_cmd_index(&txq->q, index);
925         cmd = txq->cmd[cmd_index];
926         meta = &txq->meta[cmd_index];
927
928         txq->time_stamp = jiffies;
929
930         iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
931                          DMA_BIDIRECTIONAL);
932
933         /* Input error checking is done when commands are added to queue. */
934         if (meta->flags & CMD_WANT_SKB) {
935                 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
936                 rxb->page = NULL;
937         } else if (meta->callback)
938                 meta->callback(trans->shrd, cmd, pkt);
939
940         spin_lock_irqsave(&trans->hcmd_lock, flags);
941
942         iwl_hcmd_queue_reclaim(trans, txq_id, index);
943
944         if (!(meta->flags & CMD_ASYNC)) {
945                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
946                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
947                                get_cmd_string(cmd->hdr.cmd));
948                 wake_up_interruptible(&trans->shrd->wait_command_queue);
949         }
950
951         meta->flags = 0;
952
953         spin_unlock_irqrestore(&trans->hcmd_lock, flags);
954 }
955
956 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
957
958 static void iwl_generic_cmd_callback(struct iwl_shared *shrd,
959                                      struct iwl_device_cmd *cmd,
960                                      struct iwl_rx_packet *pkt)
961 {
962         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
963                 IWL_ERR(shrd->trans, "Bad return from %s (0x%08X)\n",
964                         get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
965                 return;
966         }
967
968 #ifdef CONFIG_IWLWIFI_DEBUG
969         switch (cmd->hdr.cmd) {
970         case REPLY_TX_LINK_QUALITY_CMD:
971         case SENSITIVITY_CMD:
972                 IWL_DEBUG_HC_DUMP(shrd->trans, "back from %s (0x%08X)\n",
973                                 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
974                 break;
975         default:
976                 IWL_DEBUG_HC(shrd->trans, "back from %s (0x%08X)\n",
977                                 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
978         }
979 #endif
980 }
981
982 static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
983 {
984         int ret;
985
986         /* An asynchronous command can not expect an SKB to be set. */
987         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
988                 return -EINVAL;
989
990         /* Assign a generic callback if one is not provided */
991         if (!cmd->callback)
992                 cmd->callback = iwl_generic_cmd_callback;
993
994         if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
995                 return -EBUSY;
996
997         ret = iwl_enqueue_hcmd(trans, cmd);
998         if (ret < 0) {
999                 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
1000                           get_cmd_string(cmd->id), ret);
1001                 return ret;
1002         }
1003         return 0;
1004 }
1005
1006 static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1007 {
1008         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1009         int cmd_idx;
1010         int ret;
1011
1012         lockdep_assert_held(&trans->shrd->mutex);
1013
1014          /* A synchronous command can not have a callback set. */
1015         if (WARN_ON(cmd->callback))
1016                 return -EINVAL;
1017
1018         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1019                         get_cmd_string(cmd->id));
1020
1021         set_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1022         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1023                         get_cmd_string(cmd->id));
1024
1025         cmd_idx = iwl_enqueue_hcmd(trans, cmd);
1026         if (cmd_idx < 0) {
1027                 ret = cmd_idx;
1028                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1029                 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
1030                           get_cmd_string(cmd->id), ret);
1031                 return ret;
1032         }
1033
1034         ret = wait_event_interruptible_timeout(trans->shrd->wait_command_queue,
1035                         !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status),
1036                         HOST_COMPLETE_TIMEOUT);
1037         if (!ret) {
1038                 if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
1039                         IWL_ERR(trans,
1040                                 "Error sending %s: time out after %dms.\n",
1041                                 get_cmd_string(cmd->id),
1042                                 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1043
1044                         clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1045                         IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command"
1046                                  "%s\n", get_cmd_string(cmd->id));
1047                         ret = -ETIMEDOUT;
1048                         goto cancel;
1049                 }
1050         }
1051
1052         if (test_bit(STATUS_RF_KILL_HW, &trans->shrd->status)) {
1053                 IWL_ERR(trans, "Command %s aborted: RF KILL Switch\n",
1054                                get_cmd_string(cmd->id));
1055                 ret = -ECANCELED;
1056                 goto fail;
1057         }
1058         if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
1059                 IWL_ERR(trans, "Command %s failed: FW Error\n",
1060                                get_cmd_string(cmd->id));
1061                 ret = -EIO;
1062                 goto fail;
1063         }
1064         if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
1065                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1066                           get_cmd_string(cmd->id));
1067                 ret = -EIO;
1068                 goto cancel;
1069         }
1070
1071         return 0;
1072
1073 cancel:
1074         if (cmd->flags & CMD_WANT_SKB) {
1075                 /*
1076                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1077                  * TX cmd queue. Otherwise in case the cmd comes
1078                  * in later, it will possibly set an invalid
1079                  * address (cmd->meta.source).
1080                  */
1081                 trans_pcie->txq[trans->shrd->cmd_queue].meta[cmd_idx].flags &=
1082                                                         ~CMD_WANT_SKB;
1083         }
1084 fail:
1085         if (cmd->reply_page) {
1086                 iwl_free_pages(trans->shrd, cmd->reply_page);
1087                 cmd->reply_page = 0;
1088         }
1089
1090         return ret;
1091 }
1092
1093 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1094 {
1095         if (cmd->flags & CMD_ASYNC)
1096                 return iwl_send_cmd_async(trans, cmd);
1097
1098         return iwl_send_cmd_sync(trans, cmd);
1099 }
1100
1101 int iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id, u32 flags,
1102                 u16 len, const void *data)
1103 {
1104         struct iwl_host_cmd cmd = {
1105                 .id = id,
1106                 .len = { len, },
1107                 .data = { data, },
1108                 .flags = flags,
1109         };
1110
1111         return iwl_trans_pcie_send_cmd(trans, &cmd);
1112 }
1113
1114 /* Frees buffers until index _not_ inclusive */
1115 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
1116                          struct sk_buff_head *skbs)
1117 {
1118         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1119         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1120         struct iwl_queue *q = &txq->q;
1121         int last_to_free;
1122         int freed = 0;
1123
1124         /*Since we free until index _not_ inclusive, the one before index is
1125          * the last we will free. This one must be used */
1126         last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
1127
1128         if ((index >= q->n_bd) ||
1129            (iwl_queue_used(q, last_to_free) == 0)) {
1130                 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
1131                           "last_to_free %d is out of range [0-%d] %d %d.\n",
1132                           __func__, txq_id, last_to_free, q->n_bd,
1133                           q->write_ptr, q->read_ptr);
1134                 return 0;
1135         }
1136
1137         IWL_DEBUG_TX_REPLY(trans, "reclaim: [%d, %d, %d]\n", txq_id,
1138                            q->read_ptr, index);
1139
1140         if (WARN_ON(!skb_queue_empty(skbs)))
1141                 return 0;
1142
1143         for (;
1144              q->read_ptr != index;
1145              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1146
1147                 if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL))
1148                         continue;
1149
1150                 __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]);
1151
1152                 txq->skbs[txq->q.read_ptr] = NULL;
1153
1154                 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
1155
1156                 iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr);
1157                 freed++;
1158         }
1159         return freed;
1160 }