4678da447ff6883ebd2cfc64a5422e45dc73347b
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-core.c
1 /******************************************************************************
2  *
3  * GPL LICENSE SUMMARY
4  *
5  * Copyright(c) 2008 Intel Corporation. All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of version 2 of the GNU General Public License as
9  * published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but
12  * WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19  * USA
20  *
21  * The full GNU General Public License is included in this distribution
22  * in the file called LICENSE.GPL.
23  *
24  * Contact Information:
25  * Tomas Winkler <tomas.winkler@intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *****************************************************************************/
28
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <net/mac80211.h>
32
33 struct iwl_priv; /* FIXME: remove */
34 #include "iwl-debug.h"
35 #include "iwl-eeprom.h"
36 #include "iwl-dev.h" /* FIXME: remove */
37 #include "iwl-core.h"
38 #include "iwl-io.h"
39 #include "iwl-rfkill.h"
40 #include "iwl-power.h"
41
42
43 MODULE_DESCRIPTION("iwl core");
44 MODULE_VERSION(IWLWIFI_VERSION);
45 MODULE_AUTHOR(DRV_COPYRIGHT);
46 MODULE_LICENSE("GPL");
47
48 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np)    \
49         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,      \
50                                     IWL_RATE_SISO_##s##M_PLCP, \
51                                     IWL_RATE_MIMO2_##s##M_PLCP,\
52                                     IWL_RATE_MIMO3_##s##M_PLCP,\
53                                     IWL_RATE_##r##M_IEEE,      \
54                                     IWL_RATE_##ip##M_INDEX,    \
55                                     IWL_RATE_##in##M_INDEX,    \
56                                     IWL_RATE_##rp##M_INDEX,    \
57                                     IWL_RATE_##rn##M_INDEX,    \
58                                     IWL_RATE_##pp##M_INDEX,    \
59                                     IWL_RATE_##np##M_INDEX }
60
61 /*
62  * Parameter order:
63  *   rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
64  *
65  * If there isn't a valid next or previous rate then INV is used which
66  * maps to IWL_RATE_INVALID
67  *
68  */
69 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
70         IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2),    /*  1mbps */
71         IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5),          /*  2mbps */
72         IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
73         IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18),      /* 11mbps */
74         IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
75         IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11),       /*  9mbps */
76         IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
77         IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
78         IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
79         IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
80         IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
81         IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
82         IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
83         /* FIXME:RS:          ^^    should be INV (legacy) */
84 };
85 EXPORT_SYMBOL(iwl_rates);
86
87 /**
88  * translate ucode response to mac80211 tx status control values
89  */
90 void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
91                                   struct ieee80211_tx_info *control)
92 {
93         int rate_index;
94
95         control->antenna_sel_tx =
96                 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
97         if (rate_n_flags & RATE_MCS_HT_MSK)
98                 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
99         if (rate_n_flags & RATE_MCS_GF_MSK)
100                 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
101         if (rate_n_flags & RATE_MCS_FAT_MSK)
102                 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
103         if (rate_n_flags & RATE_MCS_DUP_MSK)
104                 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
105         if (rate_n_flags & RATE_MCS_SGI_MSK)
106                 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
107         rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
108         if (control->band == IEEE80211_BAND_5GHZ)
109                 rate_index -= IWL_FIRST_OFDM_RATE;
110         control->tx_rate_idx = rate_index;
111 }
112 EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
113
114 int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
115 {
116         int idx = 0;
117
118         /* HT rate format */
119         if (rate_n_flags & RATE_MCS_HT_MSK) {
120                 idx = (rate_n_flags & 0xff);
121
122                 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
123                         idx = idx - IWL_RATE_MIMO2_6M_PLCP;
124
125                 idx += IWL_FIRST_OFDM_RATE;
126                 /* skip 9M not supported in ht*/
127                 if (idx >= IWL_RATE_9M_INDEX)
128                         idx += 1;
129                 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
130                         return idx;
131
132         /* legacy rate format, search for match in table */
133         } else {
134                 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
135                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
136                                 return idx;
137         }
138
139         return -1;
140 }
141 EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
142
143
144
145 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
146 EXPORT_SYMBOL(iwl_bcast_addr);
147
148
149 /* This function both allocates and initializes hw and priv. */
150 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
151                 struct ieee80211_ops *hw_ops)
152 {
153         struct iwl_priv *priv;
154
155         /* mac80211 allocates memory for this device instance, including
156          *   space for this driver's private structure */
157         struct ieee80211_hw *hw =
158                 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
159         if (hw == NULL) {
160                 IWL_ERROR("Can not allocate network device\n");
161                 goto out;
162         }
163
164         priv = hw->priv;
165         priv->hw = hw;
166
167 out:
168         return hw;
169 }
170 EXPORT_SYMBOL(iwl_alloc_all);
171
172 void iwl_hw_detect(struct iwl_priv *priv)
173 {
174         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
175         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
176         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
177 }
178 EXPORT_SYMBOL(iwl_hw_detect);
179
180 /* Tell nic where to find the "keep warm" buffer */
181 int iwl_kw_init(struct iwl_priv *priv)
182 {
183         unsigned long flags;
184         int ret;
185
186         spin_lock_irqsave(&priv->lock, flags);
187         ret = iwl_grab_nic_access(priv);
188         if (ret)
189                 goto out;
190
191         iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
192                              priv->kw.dma_addr >> 4);
193         iwl_release_nic_access(priv);
194 out:
195         spin_unlock_irqrestore(&priv->lock, flags);
196         return ret;
197 }
198
199 int iwl_kw_alloc(struct iwl_priv *priv)
200 {
201         struct pci_dev *dev = priv->pci_dev;
202         struct iwl_kw *kw = &priv->kw;
203
204         kw->size = IWL_KW_SIZE;
205         kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
206         if (!kw->v_addr)
207                 return -ENOMEM;
208
209         return 0;
210 }
211
212 /**
213  * iwl_kw_free - Free the "keep warm" buffer
214  */
215 void iwl_kw_free(struct iwl_priv *priv)
216 {
217         struct pci_dev *dev = priv->pci_dev;
218         struct iwl_kw *kw = &priv->kw;
219
220         if (kw->v_addr) {
221                 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
222                 memset(kw, 0, sizeof(*kw));
223         }
224 }
225
226 int iwl_hw_nic_init(struct iwl_priv *priv)
227 {
228         unsigned long flags;
229         struct iwl_rx_queue *rxq = &priv->rxq;
230         int ret;
231
232         /* nic_init */
233         spin_lock_irqsave(&priv->lock, flags);
234         priv->cfg->ops->lib->apm_ops.init(priv);
235         iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
236         spin_unlock_irqrestore(&priv->lock, flags);
237
238         ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
239
240         priv->cfg->ops->lib->apm_ops.config(priv);
241
242         /* Allocate the RX queue, or reset if it is already allocated */
243         if (!rxq->bd) {
244                 ret = iwl_rx_queue_alloc(priv);
245                 if (ret) {
246                         IWL_ERROR("Unable to initialize Rx queue\n");
247                         return -ENOMEM;
248                 }
249         } else
250                 iwl_rx_queue_reset(priv, rxq);
251
252         iwl_rx_replenish(priv);
253
254         iwl_rx_init(priv, rxq);
255
256         spin_lock_irqsave(&priv->lock, flags);
257
258         rxq->need_update = 1;
259         iwl_rx_queue_update_write_ptr(priv, rxq);
260
261         spin_unlock_irqrestore(&priv->lock, flags);
262
263         /* Allocate and init all Tx and Command queues */
264         ret = iwl_txq_ctx_reset(priv);
265         if (ret)
266                 return ret;
267
268         set_bit(STATUS_INIT, &priv->status);
269
270         return 0;
271 }
272 EXPORT_SYMBOL(iwl_hw_nic_init);
273
274 /**
275  * iwl_clear_stations_table - Clear the driver's station table
276  *
277  * NOTE:  This does not clear or otherwise alter the device's station table.
278  */
279 void iwl_clear_stations_table(struct iwl_priv *priv)
280 {
281         unsigned long flags;
282
283         spin_lock_irqsave(&priv->sta_lock, flags);
284
285         if (iwl_is_alive(priv) &&
286            !test_bit(STATUS_EXIT_PENDING, &priv->status) &&
287            iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
288                 IWL_ERROR("Couldn't clear the station table\n");
289
290         priv->num_stations = 0;
291         memset(priv->stations, 0, sizeof(priv->stations));
292
293         spin_unlock_irqrestore(&priv->sta_lock, flags);
294 }
295 EXPORT_SYMBOL(iwl_clear_stations_table);
296
297 void iwl_reset_qos(struct iwl_priv *priv)
298 {
299         u16 cw_min = 15;
300         u16 cw_max = 1023;
301         u8 aifs = 2;
302         u8 is_legacy = 0;
303         unsigned long flags;
304         int i;
305
306         spin_lock_irqsave(&priv->lock, flags);
307         priv->qos_data.qos_active = 0;
308
309         if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
310                 if (priv->qos_data.qos_enable)
311                         priv->qos_data.qos_active = 1;
312                 if (!(priv->active_rate & 0xfff0)) {
313                         cw_min = 31;
314                         is_legacy = 1;
315                 }
316         } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
317                 if (priv->qos_data.qos_enable)
318                         priv->qos_data.qos_active = 1;
319         } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
320                 cw_min = 31;
321                 is_legacy = 1;
322         }
323
324         if (priv->qos_data.qos_active)
325                 aifs = 3;
326
327         priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
328         priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
329         priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
330         priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
331         priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
332
333         if (priv->qos_data.qos_active) {
334                 i = 1;
335                 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
336                 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
337                 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
338                 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
339                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
340
341                 i = 2;
342                 priv->qos_data.def_qos_parm.ac[i].cw_min =
343                         cpu_to_le16((cw_min + 1) / 2 - 1);
344                 priv->qos_data.def_qos_parm.ac[i].cw_max =
345                         cpu_to_le16(cw_max);
346                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
347                 if (is_legacy)
348                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
349                                 cpu_to_le16(6016);
350                 else
351                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
352                                 cpu_to_le16(3008);
353                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
354
355                 i = 3;
356                 priv->qos_data.def_qos_parm.ac[i].cw_min =
357                         cpu_to_le16((cw_min + 1) / 4 - 1);
358                 priv->qos_data.def_qos_parm.ac[i].cw_max =
359                         cpu_to_le16((cw_max + 1) / 2 - 1);
360                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
361                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
362                 if (is_legacy)
363                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
364                                 cpu_to_le16(3264);
365                 else
366                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
367                                 cpu_to_le16(1504);
368         } else {
369                 for (i = 1; i < 4; i++) {
370                         priv->qos_data.def_qos_parm.ac[i].cw_min =
371                                 cpu_to_le16(cw_min);
372                         priv->qos_data.def_qos_parm.ac[i].cw_max =
373                                 cpu_to_le16(cw_max);
374                         priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
375                         priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
376                         priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
377                 }
378         }
379         IWL_DEBUG_QOS("set QoS to default \n");
380
381         spin_unlock_irqrestore(&priv->lock, flags);
382 }
383 EXPORT_SYMBOL(iwl_reset_qos);
384
385 #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
386 #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
387 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
388                               struct ieee80211_sta_ht_cap *ht_info,
389                               enum ieee80211_band band)
390 {
391         u16 max_bit_rate = 0;
392         u8 rx_chains_num = priv->hw_params.rx_chains_num;
393         u8 tx_chains_num = priv->hw_params.tx_chains_num;
394
395         ht_info->cap = 0;
396         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
397
398         ht_info->ht_supported = true;
399
400         ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
401         ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
402         ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
403                              (WLAN_HT_CAP_SM_PS_DISABLED << 2));
404
405         max_bit_rate = MAX_BIT_RATE_20_MHZ;
406         if (priv->hw_params.fat_channel & BIT(band)) {
407                 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
408                 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
409                 ht_info->mcs.rx_mask[4] = 0x01;
410                 max_bit_rate = MAX_BIT_RATE_40_MHZ;
411         }
412
413         if (priv->cfg->mod_params->amsdu_size_8K)
414                 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
415
416         ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
417         ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
418
419         ht_info->mcs.rx_mask[0] = 0xFF;
420         if (rx_chains_num >= 2)
421                 ht_info->mcs.rx_mask[1] = 0xFF;
422         if (rx_chains_num >= 3)
423                 ht_info->mcs.rx_mask[2] = 0xFF;
424
425         /* Highest supported Rx data rate */
426         max_bit_rate *= rx_chains_num;
427         WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
428         ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
429
430         /* Tx MCS capabilities */
431         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
432         if (tx_chains_num != rx_chains_num) {
433                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
434                 ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
435                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
436         }
437 }
438
439 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
440                               struct ieee80211_rate *rates)
441 {
442         int i;
443
444         for (i = 0; i < IWL_RATE_COUNT; i++) {
445                 rates[i].bitrate = iwl_rates[i].ieee * 5;
446                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
447                 rates[i].hw_value_short = i;
448                 rates[i].flags = 0;
449                 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
450                         /*
451                          * If CCK != 1M then set short preamble rate flag.
452                          */
453                         rates[i].flags |=
454                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
455                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
456                 }
457         }
458 }
459
460 /**
461  * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
462  */
463 static int iwlcore_init_geos(struct iwl_priv *priv)
464 {
465         struct iwl_channel_info *ch;
466         struct ieee80211_supported_band *sband;
467         struct ieee80211_channel *channels;
468         struct ieee80211_channel *geo_ch;
469         struct ieee80211_rate *rates;
470         int i = 0;
471
472         if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
473             priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
474                 IWL_DEBUG_INFO("Geography modes already initialized.\n");
475                 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
476                 return 0;
477         }
478
479         channels = kzalloc(sizeof(struct ieee80211_channel) *
480                            priv->channel_count, GFP_KERNEL);
481         if (!channels)
482                 return -ENOMEM;
483
484         rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
485                         GFP_KERNEL);
486         if (!rates) {
487                 kfree(channels);
488                 return -ENOMEM;
489         }
490
491         /* 5.2GHz channels start after the 2.4GHz channels */
492         sband = &priv->bands[IEEE80211_BAND_5GHZ];
493         sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
494         /* just OFDM */
495         sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
496         sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
497
498         if (priv->cfg->sku & IWL_SKU_N)
499                 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
500                                          IEEE80211_BAND_5GHZ);
501
502         sband = &priv->bands[IEEE80211_BAND_2GHZ];
503         sband->channels = channels;
504         /* OFDM & CCK */
505         sband->bitrates = rates;
506         sband->n_bitrates = IWL_RATE_COUNT;
507
508         if (priv->cfg->sku & IWL_SKU_N)
509                 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
510                                          IEEE80211_BAND_2GHZ);
511
512         priv->ieee_channels = channels;
513         priv->ieee_rates = rates;
514
515         iwlcore_init_hw_rates(priv, rates);
516
517         for (i = 0;  i < priv->channel_count; i++) {
518                 ch = &priv->channel_info[i];
519
520                 /* FIXME: might be removed if scan is OK */
521                 if (!is_channel_valid(ch))
522                         continue;
523
524                 if (is_channel_a_band(ch))
525                         sband =  &priv->bands[IEEE80211_BAND_5GHZ];
526                 else
527                         sband =  &priv->bands[IEEE80211_BAND_2GHZ];
528
529                 geo_ch = &sband->channels[sband->n_channels++];
530
531                 geo_ch->center_freq =
532                                 ieee80211_channel_to_frequency(ch->channel);
533                 geo_ch->max_power = ch->max_power_avg;
534                 geo_ch->max_antenna_gain = 0xff;
535                 geo_ch->hw_value = ch->channel;
536
537                 if (is_channel_valid(ch)) {
538                         if (!(ch->flags & EEPROM_CHANNEL_IBSS))
539                                 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
540
541                         if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
542                                 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
543
544                         if (ch->flags & EEPROM_CHANNEL_RADAR)
545                                 geo_ch->flags |= IEEE80211_CHAN_RADAR;
546
547                         geo_ch->flags |= ch->fat_extension_channel;
548
549                         if (ch->max_power_avg > priv->tx_power_channel_lmt)
550                                 priv->tx_power_channel_lmt = ch->max_power_avg;
551                 } else {
552                         geo_ch->flags |= IEEE80211_CHAN_DISABLED;
553                 }
554
555                 /* Save flags for reg domain usage */
556                 geo_ch->orig_flags = geo_ch->flags;
557
558                 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
559                                 ch->channel, geo_ch->center_freq,
560                                 is_channel_a_band(ch) ?  "5.2" : "2.4",
561                                 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
562                                 "restricted" : "valid",
563                                  geo_ch->flags);
564         }
565
566         if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
567              priv->cfg->sku & IWL_SKU_A) {
568                 printk(KERN_INFO DRV_NAME
569                        ": Incorrectly detected BG card as ABG.  Please send "
570                        "your PCI ID 0x%04X:0x%04X to maintainer.\n",
571                        priv->pci_dev->device, priv->pci_dev->subsystem_device);
572                 priv->cfg->sku &= ~IWL_SKU_A;
573         }
574
575         printk(KERN_INFO DRV_NAME
576                ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
577                priv->bands[IEEE80211_BAND_2GHZ].n_channels,
578                priv->bands[IEEE80211_BAND_5GHZ].n_channels);
579
580
581         set_bit(STATUS_GEO_CONFIGURED, &priv->status);
582
583         return 0;
584 }
585
586 /*
587  * iwlcore_free_geos - undo allocations in iwlcore_init_geos
588  */
589 static void iwlcore_free_geos(struct iwl_priv *priv)
590 {
591         kfree(priv->ieee_channels);
592         kfree(priv->ieee_rates);
593         clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
594 }
595
596 static bool is_single_rx_stream(struct iwl_priv *priv)
597 {
598         return !priv->current_ht_config.is_ht ||
599                ((priv->current_ht_config.mcs.rx_mask[1] == 0) &&
600                 (priv->current_ht_config.mcs.rx_mask[2] == 0));
601 }
602
603 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
604                                    enum ieee80211_band band,
605                                    u16 channel, u8 extension_chan_offset)
606 {
607         const struct iwl_channel_info *ch_info;
608
609         ch_info = iwl_get_channel_info(priv, band, channel);
610         if (!is_channel_valid(ch_info))
611                 return 0;
612
613         if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
614                 return !(ch_info->fat_extension_channel &
615                                         IEEE80211_CHAN_NO_FAT_ABOVE);
616         else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
617                 return !(ch_info->fat_extension_channel &
618                                         IEEE80211_CHAN_NO_FAT_BELOW);
619
620         return 0;
621 }
622
623 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
624                          struct ieee80211_sta_ht_cap *sta_ht_inf)
625 {
626         struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
627
628         if ((!iwl_ht_conf->is_ht) ||
629            (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
630            (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE))
631                 return 0;
632
633         if (sta_ht_inf) {
634                 if ((!sta_ht_inf->ht_supported) ||
635                    (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)))
636                         return 0;
637         }
638
639         return iwl_is_channel_extension(priv, priv->band,
640                                          iwl_ht_conf->control_channel,
641                                          iwl_ht_conf->extension_chan_offset);
642 }
643 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
644
645 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
646 {
647         struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
648         u32 val;
649
650         if (!ht_info->is_ht) {
651                 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
652                         RXON_FLG_CHANNEL_MODE_PURE_40_MSK |
653                         RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
654                         RXON_FLG_FAT_PROT_MSK |
655                         RXON_FLG_HT_PROT_MSK);
656                 return;
657         }
658
659         /* Set up channel bandwidth:  20 MHz only, or 20/40 mixed if fat ok */
660         if (iwl_is_fat_tx_allowed(priv, NULL))
661                 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
662         else
663                 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
664                                  RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
665
666         if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
667                 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
668                                 le16_to_cpu(rxon->channel),
669                                 ht_info->control_channel);
670                 return;
671         }
672
673         /* Note: control channel is opposite of extension channel */
674         switch (ht_info->extension_chan_offset) {
675         case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
676                 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
677                 break;
678         case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
679                 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
680                 break;
681         case IEEE80211_HT_PARAM_CHA_SEC_NONE:
682         default:
683                 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
684                 break;
685         }
686
687         val = ht_info->ht_protection;
688
689         rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
690
691         iwl_set_rxon_chain(priv);
692
693         IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
694                         "rxon flags 0x%X operation mode :0x%X "
695                         "extension channel offset 0x%x "
696                         "control chan %d\n",
697                         ht_info->mcs.rx_mask[0],
698                         ht_info->mcs.rx_mask[1],
699                         ht_info->mcs.rx_mask[2],
700                         le32_to_cpu(rxon->flags), ht_info->ht_protection,
701                         ht_info->extension_chan_offset,
702                         ht_info->control_channel);
703         return;
704 }
705 EXPORT_SYMBOL(iwl_set_rxon_ht);
706
707 #define IWL_NUM_RX_CHAINS_MULTIPLE      3
708 #define IWL_NUM_RX_CHAINS_SINGLE        2
709 #define IWL_NUM_IDLE_CHAINS_DUAL        2
710 #define IWL_NUM_IDLE_CHAINS_SINGLE      1
711
712 /* Determine how many receiver/antenna chains to use.
713  * More provides better reception via diversity.  Fewer saves power.
714  * MIMO (dual stream) requires at least 2, but works better with 3.
715  * This does not determine *which* chains to use, just how many.
716  */
717 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
718 {
719         bool is_single = is_single_rx_stream(priv);
720         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
721
722         /* # of Rx chains to use when expecting MIMO. */
723         if (is_single || (!is_cam && (priv->current_ht_config.sm_ps ==
724                                                  WLAN_HT_CAP_SM_PS_STATIC)))
725                 return IWL_NUM_RX_CHAINS_SINGLE;
726         else
727                 return IWL_NUM_RX_CHAINS_MULTIPLE;
728 }
729
730 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
731 {
732         int idle_cnt;
733         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
734         /* # Rx chains when idling and maybe trying to save power */
735         switch (priv->current_ht_config.sm_ps) {
736         case WLAN_HT_CAP_SM_PS_STATIC:
737         case WLAN_HT_CAP_SM_PS_DYNAMIC:
738                 idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
739                                         IWL_NUM_IDLE_CHAINS_SINGLE;
740                 break;
741         case WLAN_HT_CAP_SM_PS_DISABLED:
742                 idle_cnt = (is_cam) ? active_cnt : IWL_NUM_IDLE_CHAINS_SINGLE;
743                 break;
744         case WLAN_HT_CAP_SM_PS_INVALID:
745         default:
746                 IWL_ERROR("invalide mimo ps mode %d\n",
747                            priv->current_ht_config.sm_ps);
748                 WARN_ON(1);
749                 idle_cnt = -1;
750                 break;
751         }
752         return idle_cnt;
753 }
754
755 /* up to 4 chains */
756 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
757 {
758         u8 res;
759         res = (chain_bitmap & BIT(0)) >> 0;
760         res += (chain_bitmap & BIT(1)) >> 1;
761         res += (chain_bitmap & BIT(2)) >> 2;
762         res += (chain_bitmap & BIT(4)) >> 4;
763         return res;
764 }
765
766 /**
767  * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
768  *
769  * Selects how many and which Rx receivers/antennas/chains to use.
770  * This should not be used for scan command ... it puts data in wrong place.
771  */
772 void iwl_set_rxon_chain(struct iwl_priv *priv)
773 {
774         bool is_single = is_single_rx_stream(priv);
775         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
776         u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
777         u32 active_chains;
778         u16 rx_chain;
779
780         /* Tell uCode which antennas are actually connected.
781          * Before first association, we assume all antennas are connected.
782          * Just after first association, iwl_chain_noise_calibration()
783          *    checks which antennas actually *are* connected. */
784          if (priv->chain_noise_data.active_chains)
785                 active_chains = priv->chain_noise_data.active_chains;
786         else
787                 active_chains = priv->hw_params.valid_rx_ant;
788
789         rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
790
791         /* How many receivers should we use? */
792         active_rx_cnt = iwl_get_active_rx_chain_count(priv);
793         idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
794
795
796         /* correct rx chain count according hw settings
797          * and chain noise calibration
798          */
799         valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
800         if (valid_rx_cnt < active_rx_cnt)
801                 active_rx_cnt = valid_rx_cnt;
802
803         if (valid_rx_cnt < idle_rx_cnt)
804                 idle_rx_cnt = valid_rx_cnt;
805
806         rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
807         rx_chain |= idle_rx_cnt  << RXON_RX_CHAIN_CNT_POS;
808
809         priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
810
811         if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
812                 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
813         else
814                 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
815
816         IWL_DEBUG_ASSOC("rx_chain=0x%X active=%d idle=%d\n",
817                         priv->staging_rxon.rx_chain,
818                         active_rx_cnt, idle_rx_cnt);
819
820         WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
821                 active_rx_cnt < idle_rx_cnt);
822 }
823 EXPORT_SYMBOL(iwl_set_rxon_chain);
824
825 /**
826  * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
827  * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
828  * @channel: Any channel valid for the requested phymode
829
830  * In addition to setting the staging RXON, priv->phymode is also set.
831  *
832  * NOTE:  Does not commit to the hardware; it sets appropriate bit fields
833  * in the staging RXON flag structure based on the phymode
834  */
835 int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
836 {
837         enum ieee80211_band band = ch->band;
838         u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
839
840         if (!iwl_get_channel_info(priv, band, channel)) {
841                 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
842                                channel, band);
843                 return -EINVAL;
844         }
845
846         if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
847             (priv->band == band))
848                 return 0;
849
850         priv->staging_rxon.channel = cpu_to_le16(channel);
851         if (band == IEEE80211_BAND_5GHZ)
852                 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
853         else
854                 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
855
856         priv->band = band;
857
858         IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
859
860         return 0;
861 }
862 EXPORT_SYMBOL(iwl_set_rxon_channel);
863
864 int iwl_setup_mac(struct iwl_priv *priv)
865 {
866         int ret;
867         struct ieee80211_hw *hw = priv->hw;
868         hw->rate_control_algorithm = "iwl-agn-rs";
869
870         /* Tell mac80211 our characteristics */
871         hw->flags = IEEE80211_HW_SIGNAL_DBM |
872                     IEEE80211_HW_NOISE_DBM;
873         hw->wiphy->interface_modes =
874                 BIT(NL80211_IFTYPE_AP) |
875                 BIT(NL80211_IFTYPE_STATION) |
876                 BIT(NL80211_IFTYPE_ADHOC);
877         /* Default value; 4 EDCA QOS priorities */
878         hw->queues = 4;
879         /* queues to support 11n aggregation */
880         if (priv->cfg->sku & IWL_SKU_N)
881                 hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues;
882
883         hw->conf.beacon_int = 100;
884         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
885
886         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
887                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
888                         &priv->bands[IEEE80211_BAND_2GHZ];
889         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
890                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
891                         &priv->bands[IEEE80211_BAND_5GHZ];
892
893         ret = ieee80211_register_hw(priv->hw);
894         if (ret) {
895                 IWL_ERROR("Failed to register hw (error %d)\n", ret);
896                 return ret;
897         }
898         priv->mac80211_registered = 1;
899
900         return 0;
901 }
902 EXPORT_SYMBOL(iwl_setup_mac);
903
904 int iwl_set_hw_params(struct iwl_priv *priv)
905 {
906         priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
907         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
908         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
909         if (priv->cfg->mod_params->amsdu_size_8K)
910                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
911         else
912                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
913         priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
914
915         if (priv->cfg->mod_params->disable_11n)
916                 priv->cfg->sku &= ~IWL_SKU_N;
917
918         /* Device-specific setup */
919         return priv->cfg->ops->lib->set_hw_params(priv);
920 }
921 EXPORT_SYMBOL(iwl_set_hw_params);
922
923 int iwl_init_drv(struct iwl_priv *priv)
924 {
925         int ret;
926
927         priv->retry_rate = 1;
928         priv->ibss_beacon = NULL;
929
930         spin_lock_init(&priv->lock);
931         spin_lock_init(&priv->power_data.lock);
932         spin_lock_init(&priv->sta_lock);
933         spin_lock_init(&priv->hcmd_lock);
934
935         INIT_LIST_HEAD(&priv->free_frames);
936
937         mutex_init(&priv->mutex);
938
939         /* Clear the driver's (not device's) station table */
940         iwl_clear_stations_table(priv);
941
942         priv->data_retry_limit = -1;
943         priv->ieee_channels = NULL;
944         priv->ieee_rates = NULL;
945         priv->band = IEEE80211_BAND_2GHZ;
946
947         priv->iw_mode = NL80211_IFTYPE_STATION;
948
949         priv->use_ant_b_for_management_frame = 1; /* start with ant B */
950         priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
951
952         /* Choose which receivers/antennas to use */
953         iwl_set_rxon_chain(priv);
954         iwl_init_scan_params(priv);
955
956         if (priv->cfg->mod_params->enable_qos)
957                 priv->qos_data.qos_enable = 1;
958
959         iwl_reset_qos(priv);
960
961         priv->qos_data.qos_active = 0;
962         priv->qos_data.qos_cap.val = 0;
963
964         priv->rates_mask = IWL_RATES_MASK;
965         /* If power management is turned on, default to AC mode */
966         priv->power_mode = IWL_POWER_AC;
967         priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
968
969         ret = iwl_init_channel_map(priv);
970         if (ret) {
971                 IWL_ERROR("initializing regulatory failed: %d\n", ret);
972                 goto err;
973         }
974
975         ret = iwlcore_init_geos(priv);
976         if (ret) {
977                 IWL_ERROR("initializing geos failed: %d\n", ret);
978                 goto err_free_channel_map;
979         }
980
981         return 0;
982
983 err_free_channel_map:
984         iwl_free_channel_map(priv);
985 err:
986         return ret;
987 }
988 EXPORT_SYMBOL(iwl_init_drv);
989
990 int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
991 {
992         int ret = 0;
993         if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
994                 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
995                             priv->tx_power_user_lmt);
996                 return -EINVAL;
997         }
998
999         if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
1000                 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1001                             priv->tx_power_user_lmt);
1002                 return -EINVAL;
1003         }
1004
1005         if (priv->tx_power_user_lmt != tx_power)
1006                 force = true;
1007
1008         priv->tx_power_user_lmt = tx_power;
1009
1010         if (force && priv->cfg->ops->lib->send_tx_power)
1011                 ret = priv->cfg->ops->lib->send_tx_power(priv);
1012
1013         return ret;
1014 }
1015 EXPORT_SYMBOL(iwl_set_tx_power);
1016
1017 void iwl_uninit_drv(struct iwl_priv *priv)
1018 {
1019         iwl_calib_free_results(priv);
1020         iwlcore_free_geos(priv);
1021         iwl_free_channel_map(priv);
1022         kfree(priv->scan);
1023 }
1024 EXPORT_SYMBOL(iwl_uninit_drv);
1025
1026 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
1027 {
1028         u32 stat_flags = 0;
1029         struct iwl_host_cmd cmd = {
1030                 .id = REPLY_STATISTICS_CMD,
1031                 .meta.flags = flags,
1032                 .len = sizeof(stat_flags),
1033                 .data = (u8 *) &stat_flags,
1034         };
1035         return iwl_send_cmd(priv, &cmd);
1036 }
1037 EXPORT_SYMBOL(iwl_send_statistics_request);
1038
1039 /**
1040  * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
1041  *   using sample data 100 bytes apart.  If these sample points are good,
1042  *   it's a pretty good bet that everything between them is good, too.
1043  */
1044 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
1045 {
1046         u32 val;
1047         int ret = 0;
1048         u32 errcnt = 0;
1049         u32 i;
1050
1051         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1052
1053         ret = iwl_grab_nic_access(priv);
1054         if (ret)
1055                 return ret;
1056
1057         for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1058                 /* read data comes through single port, auto-incr addr */
1059                 /* NOTE: Use the debugless read so we don't flood kernel log
1060                  * if IWL_DL_IO is set */
1061                 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1062                         i + RTC_INST_LOWER_BOUND);
1063                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1064                 if (val != le32_to_cpu(*image)) {
1065                         ret = -EIO;
1066                         errcnt++;
1067                         if (errcnt >= 3)
1068                                 break;
1069                 }
1070         }
1071
1072         iwl_release_nic_access(priv);
1073
1074         return ret;
1075 }
1076
1077 /**
1078  * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1079  *     looking at all data.
1080  */
1081 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1082                                  u32 len)
1083 {
1084         u32 val;
1085         u32 save_len = len;
1086         int ret = 0;
1087         u32 errcnt;
1088
1089         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1090
1091         ret = iwl_grab_nic_access(priv);
1092         if (ret)
1093                 return ret;
1094
1095         iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1096
1097         errcnt = 0;
1098         for (; len > 0; len -= sizeof(u32), image++) {
1099                 /* read data comes through single port, auto-incr addr */
1100                 /* NOTE: Use the debugless read so we don't flood kernel log
1101                  * if IWL_DL_IO is set */
1102                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1103                 if (val != le32_to_cpu(*image)) {
1104                         IWL_ERROR("uCode INST section is invalid at "
1105                                   "offset 0x%x, is 0x%x, s/b 0x%x\n",
1106                                   save_len - len, val, le32_to_cpu(*image));
1107                         ret = -EIO;
1108                         errcnt++;
1109                         if (errcnt >= 20)
1110                                 break;
1111                 }
1112         }
1113
1114         iwl_release_nic_access(priv);
1115
1116         if (!errcnt)
1117                 IWL_DEBUG_INFO
1118                     ("ucode image in INSTRUCTION memory is good\n");
1119
1120         return ret;
1121 }
1122
1123 /**
1124  * iwl_verify_ucode - determine which instruction image is in SRAM,
1125  *    and verify its contents
1126  */
1127 int iwl_verify_ucode(struct iwl_priv *priv)
1128 {
1129         __le32 *image;
1130         u32 len;
1131         int ret;
1132
1133         /* Try bootstrap */
1134         image = (__le32 *)priv->ucode_boot.v_addr;
1135         len = priv->ucode_boot.len;
1136         ret = iwlcore_verify_inst_sparse(priv, image, len);
1137         if (!ret) {
1138                 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1139                 return 0;
1140         }
1141
1142         /* Try initialize */
1143         image = (__le32 *)priv->ucode_init.v_addr;
1144         len = priv->ucode_init.len;
1145         ret = iwlcore_verify_inst_sparse(priv, image, len);
1146         if (!ret) {
1147                 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1148                 return 0;
1149         }
1150
1151         /* Try runtime/protocol */
1152         image = (__le32 *)priv->ucode_code.v_addr;
1153         len = priv->ucode_code.len;
1154         ret = iwlcore_verify_inst_sparse(priv, image, len);
1155         if (!ret) {
1156                 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1157                 return 0;
1158         }
1159
1160         IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1161
1162         /* Since nothing seems to match, show first several data entries in
1163          * instruction SRAM, so maybe visual inspection will give a clue.
1164          * Selection of bootstrap image (vs. other images) is arbitrary. */
1165         image = (__le32 *)priv->ucode_boot.v_addr;
1166         len = priv->ucode_boot.len;
1167         ret = iwl_verify_inst_full(priv, image, len);
1168
1169         return ret;
1170 }
1171 EXPORT_SYMBOL(iwl_verify_ucode);
1172
1173 static const char *desc_lookup(int i)
1174 {
1175         switch (i) {
1176         case 1:
1177                 return "FAIL";
1178         case 2:
1179                 return "BAD_PARAM";
1180         case 3:
1181                 return "BAD_CHECKSUM";
1182         case 4:
1183                 return "NMI_INTERRUPT";
1184         case 5:
1185                 return "SYSASSERT";
1186         case 6:
1187                 return "FATAL_ERROR";
1188         }
1189
1190         return "UNKNOWN";
1191 }
1192
1193 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1194 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1195
1196 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1197 {
1198         u32 data2, line;
1199         u32 desc, time, count, base, data1;
1200         u32 blink1, blink2, ilink1, ilink2;
1201         int ret;
1202
1203         if (priv->ucode_type == UCODE_INIT)
1204                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1205         else
1206                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1207
1208         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1209                 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1210                 return;
1211         }
1212
1213         ret = iwl_grab_nic_access(priv);
1214         if (ret) {
1215                 IWL_WARNING("Can not read from adapter at this time.\n");
1216                 return;
1217         }
1218
1219         count = iwl_read_targ_mem(priv, base);
1220
1221         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1222                 IWL_ERROR("Start IWL Error Log Dump:\n");
1223                 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1224         }
1225
1226         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1227         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1228         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1229         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1230         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1231         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1232         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1233         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1234         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1235
1236         IWL_ERROR("Desc        Time       "
1237                 "data1      data2      line\n");
1238         IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1239                 desc_lookup(desc), desc, time, data1, data2, line);
1240         IWL_ERROR("blink1  blink2  ilink1  ilink2\n");
1241         IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1242                 ilink1, ilink2);
1243
1244         iwl_release_nic_access(priv);
1245 }
1246 EXPORT_SYMBOL(iwl_dump_nic_error_log);
1247
1248 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1249
1250 /**
1251  * iwl_print_event_log - Dump error event log to syslog
1252  *
1253  * NOTE: Must be called with iwl_grab_nic_access() already obtained!
1254  */
1255 static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1256                                 u32 num_events, u32 mode)
1257 {
1258         u32 i;
1259         u32 base;       /* SRAM byte address of event log header */
1260         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1261         u32 ptr;        /* SRAM byte address of log data */
1262         u32 ev, time, data; /* event log data */
1263
1264         if (num_events == 0)
1265                 return;
1266         if (priv->ucode_type == UCODE_INIT)
1267                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1268         else
1269                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1270
1271         if (mode == 0)
1272                 event_size = 2 * sizeof(u32);
1273         else
1274                 event_size = 3 * sizeof(u32);
1275
1276         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1277
1278         /* "time" is actually "data" for mode 0 (no timestamp).
1279         * place event id # at far right for easier visual parsing. */
1280         for (i = 0; i < num_events; i++) {
1281                 ev = iwl_read_targ_mem(priv, ptr);
1282                 ptr += sizeof(u32);
1283                 time = iwl_read_targ_mem(priv, ptr);
1284                 ptr += sizeof(u32);
1285                 if (mode == 0) {
1286                         /* data, ev */
1287                         IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1288                 } else {
1289                         data = iwl_read_targ_mem(priv, ptr);
1290                         ptr += sizeof(u32);
1291                         IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1292                                         time, data, ev);
1293                 }
1294         }
1295 }
1296
1297 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1298 {
1299         int ret;
1300         u32 base;       /* SRAM byte address of event log header */
1301         u32 capacity;   /* event log capacity in # entries */
1302         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
1303         u32 num_wraps;  /* # times uCode wrapped to top of log */
1304         u32 next_entry; /* index of next entry to be written by uCode */
1305         u32 size;       /* # entries that we'll print */
1306
1307         if (priv->ucode_type == UCODE_INIT)
1308                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1309         else
1310                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1311
1312         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1313                 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1314                 return;
1315         }
1316
1317         ret = iwl_grab_nic_access(priv);
1318         if (ret) {
1319                 IWL_WARNING("Can not read from adapter at this time.\n");
1320                 return;
1321         }
1322
1323         /* event log header */
1324         capacity = iwl_read_targ_mem(priv, base);
1325         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1326         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1327         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1328
1329         size = num_wraps ? capacity : next_entry;
1330
1331         /* bail out if nothing in log */
1332         if (size == 0) {
1333                 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1334                 iwl_release_nic_access(priv);
1335                 return;
1336         }
1337
1338         IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1339                         size, num_wraps);
1340
1341         /* if uCode has wrapped back to top of log, start at the oldest entry,
1342          * i.e the next one that uCode would fill. */
1343         if (num_wraps)
1344                 iwl_print_event_log(priv, next_entry,
1345                                         capacity - next_entry, mode);
1346         /* (then/else) start at top of log */
1347         iwl_print_event_log(priv, 0, next_entry, mode);
1348
1349         iwl_release_nic_access(priv);
1350 }
1351 EXPORT_SYMBOL(iwl_dump_nic_event_log);
1352
1353 void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1354 {
1355         struct iwl_ct_kill_config cmd;
1356         unsigned long flags;
1357         int ret = 0;
1358
1359         spin_lock_irqsave(&priv->lock, flags);
1360         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1361                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1362         spin_unlock_irqrestore(&priv->lock, flags);
1363
1364         cmd.critical_temperature_R =
1365                 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1366
1367         ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1368                                sizeof(cmd), &cmd);
1369         if (ret)
1370                 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1371         else
1372                 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1373                         "critical temperature is %d\n",
1374                         cmd.critical_temperature_R);
1375 }
1376 EXPORT_SYMBOL(iwl_rf_kill_ct_config);
1377
1378 /*
1379  * CARD_STATE_CMD
1380  *
1381  * Use: Sets the device's internal card state to enable, disable, or halt
1382  *
1383  * When in the 'enable' state the card operates as normal.
1384  * When in the 'disable' state, the card enters into a low power mode.
1385  * When in the 'halt' state, the card is shut down and must be fully
1386  * restarted to come back on.
1387  */
1388 static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1389 {
1390         struct iwl_host_cmd cmd = {
1391                 .id = REPLY_CARD_STATE_CMD,
1392                 .len = sizeof(u32),
1393                 .data = &flags,
1394                 .meta.flags = meta_flag,
1395         };
1396
1397         return iwl_send_cmd(priv, &cmd);
1398 }
1399
1400 void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1401 {
1402         unsigned long flags;
1403
1404         if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1405                 return;
1406
1407         IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1408
1409         iwl_scan_cancel(priv);
1410         /* FIXME: This is a workaround for AP */
1411         if (priv->iw_mode != NL80211_IFTYPE_AP) {
1412                 spin_lock_irqsave(&priv->lock, flags);
1413                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1414                             CSR_UCODE_SW_BIT_RFKILL);
1415                 spin_unlock_irqrestore(&priv->lock, flags);
1416                 /* call the host command only if no hw rf-kill set */
1417                 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1418                     iwl_is_ready(priv))
1419                         iwl_send_card_state(priv,
1420                                 CARD_STATE_CMD_DISABLE, 0);
1421                 set_bit(STATUS_RF_KILL_SW, &priv->status);
1422                         /* make sure mac80211 stop sending Tx frame */
1423                 if (priv->mac80211_registered)
1424                         ieee80211_stop_queues(priv->hw);
1425         }
1426 }
1427 EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1428
1429 int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1430 {
1431         unsigned long flags;
1432
1433         if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1434                 return 0;
1435
1436         IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1437
1438         spin_lock_irqsave(&priv->lock, flags);
1439         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1440
1441         /* If the driver is up it will receive CARD_STATE_NOTIFICATION
1442          * notification where it will clear SW rfkill status.
1443          * Setting it here would break the handler. Only if the
1444          * interface is down we can set here since we don't
1445          * receive any further notification.
1446          */
1447         if (!priv->is_open)
1448                 clear_bit(STATUS_RF_KILL_SW, &priv->status);
1449         spin_unlock_irqrestore(&priv->lock, flags);
1450
1451         /* wake up ucode */
1452         msleep(10);
1453
1454         spin_lock_irqsave(&priv->lock, flags);
1455         iwl_read32(priv, CSR_UCODE_DRV_GP1);
1456         if (!iwl_grab_nic_access(priv))
1457                 iwl_release_nic_access(priv);
1458         spin_unlock_irqrestore(&priv->lock, flags);
1459
1460         if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1461                 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1462                                   "disabled by HW switch\n");
1463                 return 0;
1464         }
1465
1466         /* If the driver is already loaded, it will receive
1467          * CARD_STATE_NOTIFICATION notifications and the handler will
1468          * call restart to reload the driver.
1469          */
1470         return 1;
1471 }
1472 EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);