iwlwifi: remove legacy isr tasklet
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project, as well
6  * as portions of the ieee80211 subsystem header files.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of version 2 of the GNU General Public License as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20  *
21  * The full GNU General Public License is included in this distribution in the
22  * file called LICENSE.
23  *
24  * Contact Information:
25  *  Intel Linux Wireless <ilw@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
47
48 #include <net/mac80211.h>
49
50 #include <asm/div64.h>
51
52 #define DRV_NAME        "iwlagn"
53
54 #include "iwl-eeprom.h"
55 #include "iwl-dev.h"
56 #include "iwl-core.h"
57 #include "iwl-io.h"
58 #include "iwl-helpers.h"
59 #include "iwl-sta.h"
60 #include "iwl-agn-calib.h"
61 #include "iwl-agn.h"
62 #include "iwl-agn-led.h"
63
64
65 /******************************************************************************
66  *
67  * module boiler plate
68  *
69  ******************************************************************************/
70
71 /*
72  * module name, copyright, version, etc.
73  */
74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
75
76 #ifdef CONFIG_IWLWIFI_DEBUG
77 #define VD "d"
78 #else
79 #define VD
80 #endif
81
82 #define DRV_VERSION     IWLWIFI_VERSION VD
83
84
85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
86 MODULE_VERSION(DRV_VERSION);
87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
88 MODULE_LICENSE("GPL");
89
90 static int iwlagn_ant_coupling;
91 static bool iwlagn_bt_ch_announce = 1;
92
93 void iwl_update_chain_flags(struct iwl_priv *priv)
94 {
95         struct iwl_rxon_context *ctx;
96
97         if (priv->cfg->ops->hcmd->set_rxon_chain) {
98                 for_each_context(priv, ctx) {
99                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
100                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
101                                 iwlcore_commit_rxon(priv, ctx);
102                 }
103         }
104 }
105
106 static void iwl_clear_free_frames(struct iwl_priv *priv)
107 {
108         struct list_head *element;
109
110         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
111                        priv->frames_count);
112
113         while (!list_empty(&priv->free_frames)) {
114                 element = priv->free_frames.next;
115                 list_del(element);
116                 kfree(list_entry(element, struct iwl_frame, list));
117                 priv->frames_count--;
118         }
119
120         if (priv->frames_count) {
121                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
122                             priv->frames_count);
123                 priv->frames_count = 0;
124         }
125 }
126
127 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
128 {
129         struct iwl_frame *frame;
130         struct list_head *element;
131         if (list_empty(&priv->free_frames)) {
132                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
133                 if (!frame) {
134                         IWL_ERR(priv, "Could not allocate frame!\n");
135                         return NULL;
136                 }
137
138                 priv->frames_count++;
139                 return frame;
140         }
141
142         element = priv->free_frames.next;
143         list_del(element);
144         return list_entry(element, struct iwl_frame, list);
145 }
146
147 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
148 {
149         memset(frame, 0, sizeof(*frame));
150         list_add(&frame->list, &priv->free_frames);
151 }
152
153 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
154                                  struct ieee80211_hdr *hdr,
155                                  int left)
156 {
157         lockdep_assert_held(&priv->mutex);
158
159         if (!priv->beacon_skb)
160                 return 0;
161
162         if (priv->beacon_skb->len > left)
163                 return 0;
164
165         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
166
167         return priv->beacon_skb->len;
168 }
169
170 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
171 static void iwl_set_beacon_tim(struct iwl_priv *priv,
172                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
173                                u8 *beacon, u32 frame_size)
174 {
175         u16 tim_idx;
176         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
177
178         /*
179          * The index is relative to frame start but we start looking at the
180          * variable-length part of the beacon.
181          */
182         tim_idx = mgmt->u.beacon.variable - beacon;
183
184         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
185         while ((tim_idx < (frame_size - 2)) &&
186                         (beacon[tim_idx] != WLAN_EID_TIM))
187                 tim_idx += beacon[tim_idx+1] + 2;
188
189         /* If TIM field was found, set variables */
190         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
191                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
192                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
193         } else
194                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
195 }
196
197 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
198                                        struct iwl_frame *frame)
199 {
200         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
201         u32 frame_size;
202         u32 rate_flags;
203         u32 rate;
204         /*
205          * We have to set up the TX command, the TX Beacon command, and the
206          * beacon contents.
207          */
208
209         lockdep_assert_held(&priv->mutex);
210
211         if (!priv->beacon_ctx) {
212                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
213                 return 0;
214         }
215
216         /* Initialize memory */
217         tx_beacon_cmd = &frame->u.beacon;
218         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
219
220         /* Set up TX beacon contents */
221         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
222                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
223         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
224                 return 0;
225         if (!frame_size)
226                 return 0;
227
228         /* Set up TX command fields */
229         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
230         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
231         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
232         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
233                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
234
235         /* Set up TX beacon command fields */
236         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
237                            frame_size);
238
239         /* Set up packet rate and flags */
240         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
241         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
242                                               priv->hw_params.valid_tx_ant);
243         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
244         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
245                 rate_flags |= RATE_MCS_CCK_MSK;
246         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
247                         rate_flags);
248
249         return sizeof(*tx_beacon_cmd) + frame_size;
250 }
251
252 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
253 {
254         struct iwl_frame *frame;
255         unsigned int frame_size;
256         int rc;
257
258         frame = iwl_get_free_frame(priv);
259         if (!frame) {
260                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
261                           "command.\n");
262                 return -ENOMEM;
263         }
264
265         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
266         if (!frame_size) {
267                 IWL_ERR(priv, "Error configuring the beacon command\n");
268                 iwl_free_frame(priv, frame);
269                 return -EINVAL;
270         }
271
272         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
273                               &frame->u.cmd[0]);
274
275         iwl_free_frame(priv, frame);
276
277         return rc;
278 }
279
280 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
281 {
282         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
283
284         dma_addr_t addr = get_unaligned_le32(&tb->lo);
285         if (sizeof(dma_addr_t) > sizeof(u32))
286                 addr |=
287                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
288
289         return addr;
290 }
291
292 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
293 {
294         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
295
296         return le16_to_cpu(tb->hi_n_len) >> 4;
297 }
298
299 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
300                                   dma_addr_t addr, u16 len)
301 {
302         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
303         u16 hi_n_len = len << 4;
304
305         put_unaligned_le32(addr, &tb->lo);
306         if (sizeof(dma_addr_t) > sizeof(u32))
307                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
308
309         tb->hi_n_len = cpu_to_le16(hi_n_len);
310
311         tfd->num_tbs = idx + 1;
312 }
313
314 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
315 {
316         return tfd->num_tbs & 0x1f;
317 }
318
319 /**
320  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
321  * @priv - driver private data
322  * @txq - tx queue
323  *
324  * Does NOT advance any TFD circular buffer read/write indexes
325  * Does NOT free the TFD itself (which is within circular buffer)
326  */
327 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
328 {
329         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
330         struct iwl_tfd *tfd;
331         struct pci_dev *dev = priv->pci_dev;
332         int index = txq->q.read_ptr;
333         int i;
334         int num_tbs;
335
336         tfd = &tfd_tmp[index];
337
338         /* Sanity check on number of chunks */
339         num_tbs = iwl_tfd_get_num_tbs(tfd);
340
341         if (num_tbs >= IWL_NUM_OF_TBS) {
342                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
343                 /* @todo issue fatal error, it is quite serious situation */
344                 return;
345         }
346
347         /* Unmap tx_cmd */
348         if (num_tbs)
349                 pci_unmap_single(dev,
350                                 dma_unmap_addr(&txq->meta[index], mapping),
351                                 dma_unmap_len(&txq->meta[index], len),
352                                 PCI_DMA_BIDIRECTIONAL);
353
354         /* Unmap chunks, if any. */
355         for (i = 1; i < num_tbs; i++)
356                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
357                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
358
359         /* free SKB */
360         if (txq->txb) {
361                 struct sk_buff *skb;
362
363                 skb = txq->txb[txq->q.read_ptr].skb;
364
365                 /* can be called from irqs-disabled context */
366                 if (skb) {
367                         dev_kfree_skb_any(skb);
368                         txq->txb[txq->q.read_ptr].skb = NULL;
369                 }
370         }
371 }
372
373 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
374                                  struct iwl_tx_queue *txq,
375                                  dma_addr_t addr, u16 len,
376                                  u8 reset, u8 pad)
377 {
378         struct iwl_queue *q;
379         struct iwl_tfd *tfd, *tfd_tmp;
380         u32 num_tbs;
381
382         q = &txq->q;
383         tfd_tmp = (struct iwl_tfd *)txq->tfds;
384         tfd = &tfd_tmp[q->write_ptr];
385
386         if (reset)
387                 memset(tfd, 0, sizeof(*tfd));
388
389         num_tbs = iwl_tfd_get_num_tbs(tfd);
390
391         /* Each TFD can point to a maximum 20 Tx buffers */
392         if (num_tbs >= IWL_NUM_OF_TBS) {
393                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
394                           IWL_NUM_OF_TBS);
395                 return -EINVAL;
396         }
397
398         BUG_ON(addr & ~DMA_BIT_MASK(36));
399         if (unlikely(addr & ~IWL_TX_DMA_MASK))
400                 IWL_ERR(priv, "Unaligned address = %llx\n",
401                           (unsigned long long)addr);
402
403         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
404
405         return 0;
406 }
407
408 /*
409  * Tell nic where to find circular buffer of Tx Frame Descriptors for
410  * given Tx queue, and enable the DMA channel used for that queue.
411  *
412  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
413  * channels supported in hardware.
414  */
415 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
416                          struct iwl_tx_queue *txq)
417 {
418         int txq_id = txq->q.id;
419
420         /* Circular buffer (TFD queue in DRAM) physical base address */
421         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
422                              txq->q.dma_addr >> 8);
423
424         return 0;
425 }
426
427 static void iwl_bg_beacon_update(struct work_struct *work)
428 {
429         struct iwl_priv *priv =
430                 container_of(work, struct iwl_priv, beacon_update);
431         struct sk_buff *beacon;
432
433         mutex_lock(&priv->mutex);
434         if (!priv->beacon_ctx) {
435                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
436                 goto out;
437         }
438
439         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
440                 /*
441                  * The ucode will send beacon notifications even in
442                  * IBSS mode, but we don't want to process them. But
443                  * we need to defer the type check to here due to
444                  * requiring locking around the beacon_ctx access.
445                  */
446                 goto out;
447         }
448
449         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
450         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
451         if (!beacon) {
452                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
453                 goto out;
454         }
455
456         /* new beacon skb is allocated every time; dispose previous.*/
457         dev_kfree_skb(priv->beacon_skb);
458
459         priv->beacon_skb = beacon;
460
461         iwlagn_send_beacon_cmd(priv);
462  out:
463         mutex_unlock(&priv->mutex);
464 }
465
466 static void iwl_bg_bt_runtime_config(struct work_struct *work)
467 {
468         struct iwl_priv *priv =
469                 container_of(work, struct iwl_priv, bt_runtime_config);
470
471         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
472                 return;
473
474         /* dont send host command if rf-kill is on */
475         if (!iwl_is_ready_rf(priv))
476                 return;
477         priv->cfg->ops->hcmd->send_bt_config(priv);
478 }
479
480 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
481 {
482         struct iwl_priv *priv =
483                 container_of(work, struct iwl_priv, bt_full_concurrency);
484         struct iwl_rxon_context *ctx;
485
486         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
487                 return;
488
489         /* dont send host command if rf-kill is on */
490         if (!iwl_is_ready_rf(priv))
491                 return;
492
493         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
494                        priv->bt_full_concurrent ?
495                        "full concurrency" : "3-wire");
496
497         /*
498          * LQ & RXON updated cmds must be sent before BT Config cmd
499          * to avoid 3-wire collisions
500          */
501         mutex_lock(&priv->mutex);
502         for_each_context(priv, ctx) {
503                 if (priv->cfg->ops->hcmd->set_rxon_chain)
504                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
505                 iwlcore_commit_rxon(priv, ctx);
506         }
507         mutex_unlock(&priv->mutex);
508
509         priv->cfg->ops->hcmd->send_bt_config(priv);
510 }
511
512 /**
513  * iwl_bg_statistics_periodic - Timer callback to queue statistics
514  *
515  * This callback is provided in order to send a statistics request.
516  *
517  * This timer function is continually reset to execute within
518  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
519  * was received.  We need to ensure we receive the statistics in order
520  * to update the temperature used for calibrating the TXPOWER.
521  */
522 static void iwl_bg_statistics_periodic(unsigned long data)
523 {
524         struct iwl_priv *priv = (struct iwl_priv *)data;
525
526         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
527                 return;
528
529         /* dont send host command if rf-kill is on */
530         if (!iwl_is_ready_rf(priv))
531                 return;
532
533         iwl_send_statistics_request(priv, CMD_ASYNC, false);
534 }
535
536
537 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
538                                         u32 start_idx, u32 num_events,
539                                         u32 mode)
540 {
541         u32 i;
542         u32 ptr;        /* SRAM byte address of log data */
543         u32 ev, time, data; /* event log data */
544         unsigned long reg_flags;
545
546         if (mode == 0)
547                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
548         else
549                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
550
551         /* Make sure device is powered up for SRAM reads */
552         spin_lock_irqsave(&priv->reg_lock, reg_flags);
553         if (iwl_grab_nic_access(priv)) {
554                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
555                 return;
556         }
557
558         /* Set starting address; reads will auto-increment */
559         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
560         rmb();
561
562         /*
563          * "time" is actually "data" for mode 0 (no timestamp).
564          * place event id # at far right for easier visual parsing.
565          */
566         for (i = 0; i < num_events; i++) {
567                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
568                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
569                 if (mode == 0) {
570                         trace_iwlwifi_dev_ucode_cont_event(priv,
571                                                         0, time, ev);
572                 } else {
573                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
574                         trace_iwlwifi_dev_ucode_cont_event(priv,
575                                                 time, data, ev);
576                 }
577         }
578         /* Allow device to power down */
579         iwl_release_nic_access(priv);
580         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
581 }
582
583 static void iwl_continuous_event_trace(struct iwl_priv *priv)
584 {
585         u32 capacity;   /* event log capacity in # entries */
586         u32 base;       /* SRAM byte address of event log header */
587         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
588         u32 num_wraps;  /* # times uCode wrapped to top of log */
589         u32 next_entry; /* index of next entry to be written by uCode */
590
591         if (priv->ucode_type == UCODE_INIT)
592                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
593         else
594                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
595         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
596                 capacity = iwl_read_targ_mem(priv, base);
597                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
598                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
599                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
600         } else
601                 return;
602
603         if (num_wraps == priv->event_log.num_wraps) {
604                 iwl_print_cont_event_trace(priv,
605                                        base, priv->event_log.next_entry,
606                                        next_entry - priv->event_log.next_entry,
607                                        mode);
608                 priv->event_log.non_wraps_count++;
609         } else {
610                 if ((num_wraps - priv->event_log.num_wraps) > 1)
611                         priv->event_log.wraps_more_count++;
612                 else
613                         priv->event_log.wraps_once_count++;
614                 trace_iwlwifi_dev_ucode_wrap_event(priv,
615                                 num_wraps - priv->event_log.num_wraps,
616                                 next_entry, priv->event_log.next_entry);
617                 if (next_entry < priv->event_log.next_entry) {
618                         iwl_print_cont_event_trace(priv, base,
619                                priv->event_log.next_entry,
620                                capacity - priv->event_log.next_entry,
621                                mode);
622
623                         iwl_print_cont_event_trace(priv, base, 0,
624                                 next_entry, mode);
625                 } else {
626                         iwl_print_cont_event_trace(priv, base,
627                                next_entry, capacity - next_entry,
628                                mode);
629
630                         iwl_print_cont_event_trace(priv, base, 0,
631                                 next_entry, mode);
632                 }
633         }
634         priv->event_log.num_wraps = num_wraps;
635         priv->event_log.next_entry = next_entry;
636 }
637
638 /**
639  * iwl_bg_ucode_trace - Timer callback to log ucode event
640  *
641  * The timer is continually set to execute every
642  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
643  * this function is to perform continuous uCode event logging operation
644  * if enabled
645  */
646 static void iwl_bg_ucode_trace(unsigned long data)
647 {
648         struct iwl_priv *priv = (struct iwl_priv *)data;
649
650         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
651                 return;
652
653         if (priv->event_log.ucode_trace) {
654                 iwl_continuous_event_trace(priv);
655                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
656                 mod_timer(&priv->ucode_trace,
657                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
658         }
659 }
660
661 static void iwl_bg_tx_flush(struct work_struct *work)
662 {
663         struct iwl_priv *priv =
664                 container_of(work, struct iwl_priv, tx_flush);
665
666         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
667                 return;
668
669         /* do nothing if rf-kill is on */
670         if (!iwl_is_ready_rf(priv))
671                 return;
672
673         if (priv->cfg->ops->lib->txfifo_flush) {
674                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
675                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
676         }
677 }
678
679 /**
680  * iwl_rx_handle - Main entry function for receiving responses from uCode
681  *
682  * Uses the priv->rx_handlers callback function array to invoke
683  * the appropriate handlers, including command responses,
684  * frame-received notifications, and other notifications.
685  */
686 static void iwl_rx_handle(struct iwl_priv *priv)
687 {
688         struct iwl_rx_mem_buffer *rxb;
689         struct iwl_rx_packet *pkt;
690         struct iwl_rx_queue *rxq = &priv->rxq;
691         u32 r, i;
692         int reclaim;
693         unsigned long flags;
694         u8 fill_rx = 0;
695         u32 count = 8;
696         int total_empty;
697
698         /* uCode's read index (stored in shared DRAM) indicates the last Rx
699          * buffer that the driver may process (last buffer filled by ucode). */
700         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
701         i = rxq->read;
702
703         /* Rx interrupt, but nothing sent from uCode */
704         if (i == r)
705                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
706
707         /* calculate total frames need to be restock after handling RX */
708         total_empty = r - rxq->write_actual;
709         if (total_empty < 0)
710                 total_empty += RX_QUEUE_SIZE;
711
712         if (total_empty > (RX_QUEUE_SIZE / 2))
713                 fill_rx = 1;
714
715         while (i != r) {
716                 int len;
717
718                 rxb = rxq->queue[i];
719
720                 /* If an RXB doesn't have a Rx queue slot associated with it,
721                  * then a bug has been introduced in the queue refilling
722                  * routines -- catch it here */
723                 BUG_ON(rxb == NULL);
724
725                 rxq->queue[i] = NULL;
726
727                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
728                                PAGE_SIZE << priv->hw_params.rx_page_order,
729                                PCI_DMA_FROMDEVICE);
730                 pkt = rxb_addr(rxb);
731
732                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
733                 len += sizeof(u32); /* account for status word */
734                 trace_iwlwifi_dev_rx(priv, pkt, len);
735
736                 /* Reclaim a command buffer only if this packet is a response
737                  *   to a (driver-originated) command.
738                  * If the packet (e.g. Rx frame) originated from uCode,
739                  *   there is no command buffer to reclaim.
740                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
741                  *   but apparently a few don't get set; catch them here. */
742                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
743                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
744                         (pkt->hdr.cmd != REPLY_RX) &&
745                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
746                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
747                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
748                         (pkt->hdr.cmd != REPLY_TX);
749
750                 /*
751                  * Do the notification wait before RX handlers so
752                  * even if the RX handler consumes the RXB we have
753                  * access to it in the notification wait entry.
754                  */
755                 if (!list_empty(&priv->_agn.notif_waits)) {
756                         struct iwl_notification_wait *w;
757
758                         spin_lock(&priv->_agn.notif_wait_lock);
759                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
760                                 if (w->cmd == pkt->hdr.cmd) {
761                                         w->triggered = true;
762                                         if (w->fn)
763                                                 w->fn(priv, pkt);
764                                 }
765                         }
766                         spin_unlock(&priv->_agn.notif_wait_lock);
767
768                         wake_up_all(&priv->_agn.notif_waitq);
769                 }
770
771                 /* Based on type of command response or notification,
772                  *   handle those that need handling via function in
773                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
774                 if (priv->rx_handlers[pkt->hdr.cmd]) {
775                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
776                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
777                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
778                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
779                 } else {
780                         /* No handling needed */
781                         IWL_DEBUG_RX(priv,
782                                 "r %d i %d No handler needed for %s, 0x%02x\n",
783                                 r, i, get_cmd_string(pkt->hdr.cmd),
784                                 pkt->hdr.cmd);
785                 }
786
787                 /*
788                  * XXX: After here, we should always check rxb->page
789                  * against NULL before touching it or its virtual
790                  * memory (pkt). Because some rx_handler might have
791                  * already taken or freed the pages.
792                  */
793
794                 if (reclaim) {
795                         /* Invoke any callbacks, transfer the buffer to caller,
796                          * and fire off the (possibly) blocking iwl_send_cmd()
797                          * as we reclaim the driver command queue */
798                         if (rxb->page)
799                                 iwl_tx_cmd_complete(priv, rxb);
800                         else
801                                 IWL_WARN(priv, "Claim null rxb?\n");
802                 }
803
804                 /* Reuse the page if possible. For notification packets and
805                  * SKBs that fail to Rx correctly, add them back into the
806                  * rx_free list for reuse later. */
807                 spin_lock_irqsave(&rxq->lock, flags);
808                 if (rxb->page != NULL) {
809                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
810                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
811                                 PCI_DMA_FROMDEVICE);
812                         list_add_tail(&rxb->list, &rxq->rx_free);
813                         rxq->free_count++;
814                 } else
815                         list_add_tail(&rxb->list, &rxq->rx_used);
816
817                 spin_unlock_irqrestore(&rxq->lock, flags);
818
819                 i = (i + 1) & RX_QUEUE_MASK;
820                 /* If there are a lot of unused frames,
821                  * restock the Rx queue so ucode wont assert. */
822                 if (fill_rx) {
823                         count++;
824                         if (count >= 8) {
825                                 rxq->read = i;
826                                 iwlagn_rx_replenish_now(priv);
827                                 count = 0;
828                         }
829                 }
830         }
831
832         /* Backtrack one entry */
833         rxq->read = i;
834         if (fill_rx)
835                 iwlagn_rx_replenish_now(priv);
836         else
837                 iwlagn_rx_queue_restock(priv);
838 }
839
840 /* call this function to flush any scheduled tasklet */
841 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
842 {
843         /* wait to make sure we flush pending tasklet*/
844         synchronize_irq(priv->pci_dev->irq);
845         tasklet_kill(&priv->irq_tasklet);
846 }
847
848 /* tasklet for iwlagn interrupt */
849 static void iwl_irq_tasklet(struct iwl_priv *priv)
850 {
851         u32 inta = 0;
852         u32 handled = 0;
853         unsigned long flags;
854         u32 i;
855 #ifdef CONFIG_IWLWIFI_DEBUG
856         u32 inta_mask;
857 #endif
858
859         spin_lock_irqsave(&priv->lock, flags);
860
861         /* Ack/clear/reset pending uCode interrupts.
862          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
863          */
864         /* There is a hardware bug in the interrupt mask function that some
865          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
866          * they are disabled in the CSR_INT_MASK register. Furthermore the
867          * ICT interrupt handling mechanism has another bug that might cause
868          * these unmasked interrupts fail to be detected. We workaround the
869          * hardware bugs here by ACKing all the possible interrupts so that
870          * interrupt coalescing can still be achieved.
871          */
872         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
873
874         inta = priv->_agn.inta;
875
876 #ifdef CONFIG_IWLWIFI_DEBUG
877         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
878                 /* just for debug */
879                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
880                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
881                                 inta, inta_mask);
882         }
883 #endif
884
885         spin_unlock_irqrestore(&priv->lock, flags);
886
887         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
888         priv->_agn.inta = 0;
889
890         /* Now service all interrupt bits discovered above. */
891         if (inta & CSR_INT_BIT_HW_ERR) {
892                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
893
894                 /* Tell the device to stop sending interrupts */
895                 iwl_disable_interrupts(priv);
896
897                 priv->isr_stats.hw++;
898                 iwl_irq_handle_error(priv);
899
900                 handled |= CSR_INT_BIT_HW_ERR;
901
902                 return;
903         }
904
905 #ifdef CONFIG_IWLWIFI_DEBUG
906         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
907                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
908                 if (inta & CSR_INT_BIT_SCD) {
909                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
910                                       "the frame/frames.\n");
911                         priv->isr_stats.sch++;
912                 }
913
914                 /* Alive notification via Rx interrupt will do the real work */
915                 if (inta & CSR_INT_BIT_ALIVE) {
916                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
917                         priv->isr_stats.alive++;
918                 }
919         }
920 #endif
921         /* Safely ignore these bits for debug checks below */
922         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
923
924         /* HW RF KILL switch toggled */
925         if (inta & CSR_INT_BIT_RF_KILL) {
926                 int hw_rf_kill = 0;
927                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
928                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
929                         hw_rf_kill = 1;
930
931                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
932                                 hw_rf_kill ? "disable radio" : "enable radio");
933
934                 priv->isr_stats.rfkill++;
935
936                 /* driver only loads ucode once setting the interface up.
937                  * the driver allows loading the ucode even if the radio
938                  * is killed. Hence update the killswitch state here. The
939                  * rfkill handler will care about restarting if needed.
940                  */
941                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
942                         if (hw_rf_kill)
943                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
944                         else
945                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
946                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
947                 }
948
949                 handled |= CSR_INT_BIT_RF_KILL;
950         }
951
952         /* Chip got too hot and stopped itself */
953         if (inta & CSR_INT_BIT_CT_KILL) {
954                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
955                 priv->isr_stats.ctkill++;
956                 handled |= CSR_INT_BIT_CT_KILL;
957         }
958
959         /* Error detected by uCode */
960         if (inta & CSR_INT_BIT_SW_ERR) {
961                 IWL_ERR(priv, "Microcode SW error detected. "
962                         " Restarting 0x%X.\n", inta);
963                 priv->isr_stats.sw++;
964                 iwl_irq_handle_error(priv);
965                 handled |= CSR_INT_BIT_SW_ERR;
966         }
967
968         /* uCode wakes up after power-down sleep */
969         if (inta & CSR_INT_BIT_WAKEUP) {
970                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
971                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
972                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
973                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
974
975                 priv->isr_stats.wakeup++;
976
977                 handled |= CSR_INT_BIT_WAKEUP;
978         }
979
980         /* All uCode command responses, including Tx command responses,
981          * Rx "responses" (frame-received notification), and other
982          * notifications from uCode come through here*/
983         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
984                         CSR_INT_BIT_RX_PERIODIC)) {
985                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
986                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
987                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
988                         iwl_write32(priv, CSR_FH_INT_STATUS,
989                                         CSR49_FH_INT_RX_MASK);
990                 }
991                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
992                         handled |= CSR_INT_BIT_RX_PERIODIC;
993                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
994                 }
995                 /* Sending RX interrupt require many steps to be done in the
996                  * the device:
997                  * 1- write interrupt to current index in ICT table.
998                  * 2- dma RX frame.
999                  * 3- update RX shared data to indicate last write index.
1000                  * 4- send interrupt.
1001                  * This could lead to RX race, driver could receive RX interrupt
1002                  * but the shared data changes does not reflect this;
1003                  * periodic interrupt will detect any dangling Rx activity.
1004                  */
1005
1006                 /* Disable periodic interrupt; we use it as just a one-shot. */
1007                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1008                             CSR_INT_PERIODIC_DIS);
1009                 iwl_rx_handle(priv);
1010
1011                 /*
1012                  * Enable periodic interrupt in 8 msec only if we received
1013                  * real RX interrupt (instead of just periodic int), to catch
1014                  * any dangling Rx interrupt.  If it was just the periodic
1015                  * interrupt, there was no dangling Rx activity, and no need
1016                  * to extend the periodic interrupt; one-shot is enough.
1017                  */
1018                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1019                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1020                                     CSR_INT_PERIODIC_ENA);
1021
1022                 priv->isr_stats.rx++;
1023         }
1024
1025         /* This "Tx" DMA channel is used only for loading uCode */
1026         if (inta & CSR_INT_BIT_FH_TX) {
1027                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1028                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1029                 priv->isr_stats.tx++;
1030                 handled |= CSR_INT_BIT_FH_TX;
1031                 /* Wake up uCode load routine, now that load is complete */
1032                 priv->ucode_write_complete = 1;
1033                 wake_up_interruptible(&priv->wait_command_queue);
1034         }
1035
1036         if (inta & ~handled) {
1037                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1038                 priv->isr_stats.unhandled++;
1039         }
1040
1041         if (inta & ~(priv->inta_mask)) {
1042                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1043                          inta & ~priv->inta_mask);
1044         }
1045
1046         /* Re-enable all interrupts */
1047         /* only Re-enable if disabled by irq */
1048         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1049                 iwl_enable_interrupts(priv);
1050         /* Re-enable RF_KILL if it occurred */
1051         else if (handled & CSR_INT_BIT_RF_KILL)
1052                 iwl_enable_rfkill_int(priv);
1053 }
1054
1055 /*****************************************************************************
1056  *
1057  * sysfs attributes
1058  *
1059  *****************************************************************************/
1060
1061 #ifdef CONFIG_IWLWIFI_DEBUG
1062
1063 /*
1064  * The following adds a new attribute to the sysfs representation
1065  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1066  * used for controlling the debug level.
1067  *
1068  * See the level definitions in iwl for details.
1069  *
1070  * The debug_level being managed using sysfs below is a per device debug
1071  * level that is used instead of the global debug level if it (the per
1072  * device debug level) is set.
1073  */
1074 static ssize_t show_debug_level(struct device *d,
1075                                 struct device_attribute *attr, char *buf)
1076 {
1077         struct iwl_priv *priv = dev_get_drvdata(d);
1078         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1079 }
1080 static ssize_t store_debug_level(struct device *d,
1081                                 struct device_attribute *attr,
1082                                  const char *buf, size_t count)
1083 {
1084         struct iwl_priv *priv = dev_get_drvdata(d);
1085         unsigned long val;
1086         int ret;
1087
1088         ret = strict_strtoul(buf, 0, &val);
1089         if (ret)
1090                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1091         else {
1092                 priv->debug_level = val;
1093                 if (iwl_alloc_traffic_mem(priv))
1094                         IWL_ERR(priv,
1095                                 "Not enough memory to generate traffic log\n");
1096         }
1097         return strnlen(buf, count);
1098 }
1099
1100 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1101                         show_debug_level, store_debug_level);
1102
1103
1104 #endif /* CONFIG_IWLWIFI_DEBUG */
1105
1106
1107 static ssize_t show_temperature(struct device *d,
1108                                 struct device_attribute *attr, char *buf)
1109 {
1110         struct iwl_priv *priv = dev_get_drvdata(d);
1111
1112         if (!iwl_is_alive(priv))
1113                 return -EAGAIN;
1114
1115         return sprintf(buf, "%d\n", priv->temperature);
1116 }
1117
1118 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1119
1120 static ssize_t show_tx_power(struct device *d,
1121                              struct device_attribute *attr, char *buf)
1122 {
1123         struct iwl_priv *priv = dev_get_drvdata(d);
1124
1125         if (!iwl_is_ready_rf(priv))
1126                 return sprintf(buf, "off\n");
1127         else
1128                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1129 }
1130
1131 static ssize_t store_tx_power(struct device *d,
1132                               struct device_attribute *attr,
1133                               const char *buf, size_t count)
1134 {
1135         struct iwl_priv *priv = dev_get_drvdata(d);
1136         unsigned long val;
1137         int ret;
1138
1139         ret = strict_strtoul(buf, 10, &val);
1140         if (ret)
1141                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1142         else {
1143                 ret = iwl_set_tx_power(priv, val, false);
1144                 if (ret)
1145                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1146                                 ret);
1147                 else
1148                         ret = count;
1149         }
1150         return ret;
1151 }
1152
1153 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1154
1155 static struct attribute *iwl_sysfs_entries[] = {
1156         &dev_attr_temperature.attr,
1157         &dev_attr_tx_power.attr,
1158 #ifdef CONFIG_IWLWIFI_DEBUG
1159         &dev_attr_debug_level.attr,
1160 #endif
1161         NULL
1162 };
1163
1164 static struct attribute_group iwl_attribute_group = {
1165         .name = NULL,           /* put in device directory */
1166         .attrs = iwl_sysfs_entries,
1167 };
1168
1169 /******************************************************************************
1170  *
1171  * uCode download functions
1172  *
1173  ******************************************************************************/
1174
1175 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1176 {
1177         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1178         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1179         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1180         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1181         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1182         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1183 }
1184
1185 static void iwl_nic_start(struct iwl_priv *priv)
1186 {
1187         /* Remove all resets to allow NIC to operate */
1188         iwl_write32(priv, CSR_RESET, 0);
1189 }
1190
1191 struct iwlagn_ucode_capabilities {
1192         u32 max_probe_length;
1193         u32 standard_phy_calibration_size;
1194         bool pan;
1195 };
1196
1197 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1198 static int iwl_mac_setup_register(struct iwl_priv *priv,
1199                                   struct iwlagn_ucode_capabilities *capa);
1200
1201 #define UCODE_EXPERIMENTAL_INDEX        100
1202 #define UCODE_EXPERIMENTAL_TAG          "exp"
1203
1204 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1205 {
1206         const char *name_pre = priv->cfg->fw_name_pre;
1207         char tag[8];
1208
1209         if (first) {
1210 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1211                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1212                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1213         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1214 #endif
1215                 priv->fw_index = priv->cfg->ucode_api_max;
1216                 sprintf(tag, "%d", priv->fw_index);
1217         } else {
1218                 priv->fw_index--;
1219                 sprintf(tag, "%d", priv->fw_index);
1220         }
1221
1222         if (priv->fw_index < priv->cfg->ucode_api_min) {
1223                 IWL_ERR(priv, "no suitable firmware found!\n");
1224                 return -ENOENT;
1225         }
1226
1227         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1228
1229         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1230                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1231                                 ? "EXPERIMENTAL " : "",
1232                        priv->firmware_name);
1233
1234         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1235                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1236                                        iwl_ucode_callback);
1237 }
1238
1239 struct iwlagn_firmware_pieces {
1240         const void *inst, *data, *init, *init_data, *boot;
1241         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1242
1243         u32 build;
1244
1245         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1246         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1247 };
1248
1249 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1250                                        const struct firmware *ucode_raw,
1251                                        struct iwlagn_firmware_pieces *pieces)
1252 {
1253         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1254         u32 api_ver, hdr_size;
1255         const u8 *src;
1256
1257         priv->ucode_ver = le32_to_cpu(ucode->ver);
1258         api_ver = IWL_UCODE_API(priv->ucode_ver);
1259
1260         switch (api_ver) {
1261         default:
1262                 /*
1263                  * 4965 doesn't revision the firmware file format
1264                  * along with the API version, it always uses v1
1265                  * file format.
1266                  */
1267                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1268                                 CSR_HW_REV_TYPE_4965) {
1269                         hdr_size = 28;
1270                         if (ucode_raw->size < hdr_size) {
1271                                 IWL_ERR(priv, "File size too small!\n");
1272                                 return -EINVAL;
1273                         }
1274                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1275                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1276                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1277                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1278                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1279                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1280                         src = ucode->u.v2.data;
1281                         break;
1282                 }
1283                 /* fall through for 4965 */
1284         case 0:
1285         case 1:
1286         case 2:
1287                 hdr_size = 24;
1288                 if (ucode_raw->size < hdr_size) {
1289                         IWL_ERR(priv, "File size too small!\n");
1290                         return -EINVAL;
1291                 }
1292                 pieces->build = 0;
1293                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1294                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1295                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1296                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1297                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1298                 src = ucode->u.v1.data;
1299                 break;
1300         }
1301
1302         /* Verify size of file vs. image size info in file's header */
1303         if (ucode_raw->size != hdr_size + pieces->inst_size +
1304                                 pieces->data_size + pieces->init_size +
1305                                 pieces->init_data_size + pieces->boot_size) {
1306
1307                 IWL_ERR(priv,
1308                         "uCode file size %d does not match expected size\n",
1309                         (int)ucode_raw->size);
1310                 return -EINVAL;
1311         }
1312
1313         pieces->inst = src;
1314         src += pieces->inst_size;
1315         pieces->data = src;
1316         src += pieces->data_size;
1317         pieces->init = src;
1318         src += pieces->init_size;
1319         pieces->init_data = src;
1320         src += pieces->init_data_size;
1321         pieces->boot = src;
1322         src += pieces->boot_size;
1323
1324         return 0;
1325 }
1326
1327 static int iwlagn_wanted_ucode_alternative = 1;
1328
1329 static int iwlagn_load_firmware(struct iwl_priv *priv,
1330                                 const struct firmware *ucode_raw,
1331                                 struct iwlagn_firmware_pieces *pieces,
1332                                 struct iwlagn_ucode_capabilities *capa)
1333 {
1334         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1335         struct iwl_ucode_tlv *tlv;
1336         size_t len = ucode_raw->size;
1337         const u8 *data;
1338         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1339         u64 alternatives;
1340         u32 tlv_len;
1341         enum iwl_ucode_tlv_type tlv_type;
1342         const u8 *tlv_data;
1343
1344         if (len < sizeof(*ucode)) {
1345                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1346                 return -EINVAL;
1347         }
1348
1349         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1350                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1351                         le32_to_cpu(ucode->magic));
1352                 return -EINVAL;
1353         }
1354
1355         /*
1356          * Check which alternatives are present, and "downgrade"
1357          * when the chosen alternative is not present, warning
1358          * the user when that happens. Some files may not have
1359          * any alternatives, so don't warn in that case.
1360          */
1361         alternatives = le64_to_cpu(ucode->alternatives);
1362         tmp = wanted_alternative;
1363         if (wanted_alternative > 63)
1364                 wanted_alternative = 63;
1365         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1366                 wanted_alternative--;
1367         if (wanted_alternative && wanted_alternative != tmp)
1368                 IWL_WARN(priv,
1369                          "uCode alternative %d not available, choosing %d\n",
1370                          tmp, wanted_alternative);
1371
1372         priv->ucode_ver = le32_to_cpu(ucode->ver);
1373         pieces->build = le32_to_cpu(ucode->build);
1374         data = ucode->data;
1375
1376         len -= sizeof(*ucode);
1377
1378         while (len >= sizeof(*tlv)) {
1379                 u16 tlv_alt;
1380
1381                 len -= sizeof(*tlv);
1382                 tlv = (void *)data;
1383
1384                 tlv_len = le32_to_cpu(tlv->length);
1385                 tlv_type = le16_to_cpu(tlv->type);
1386                 tlv_alt = le16_to_cpu(tlv->alternative);
1387                 tlv_data = tlv->data;
1388
1389                 if (len < tlv_len) {
1390                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1391                                 len, tlv_len);
1392                         return -EINVAL;
1393                 }
1394                 len -= ALIGN(tlv_len, 4);
1395                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1396
1397                 /*
1398                  * Alternative 0 is always valid.
1399                  *
1400                  * Skip alternative TLVs that are not selected.
1401                  */
1402                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1403                         continue;
1404
1405                 switch (tlv_type) {
1406                 case IWL_UCODE_TLV_INST:
1407                         pieces->inst = tlv_data;
1408                         pieces->inst_size = tlv_len;
1409                         break;
1410                 case IWL_UCODE_TLV_DATA:
1411                         pieces->data = tlv_data;
1412                         pieces->data_size = tlv_len;
1413                         break;
1414                 case IWL_UCODE_TLV_INIT:
1415                         pieces->init = tlv_data;
1416                         pieces->init_size = tlv_len;
1417                         break;
1418                 case IWL_UCODE_TLV_INIT_DATA:
1419                         pieces->init_data = tlv_data;
1420                         pieces->init_data_size = tlv_len;
1421                         break;
1422                 case IWL_UCODE_TLV_BOOT:
1423                         pieces->boot = tlv_data;
1424                         pieces->boot_size = tlv_len;
1425                         break;
1426                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1427                         if (tlv_len != sizeof(u32))
1428                                 goto invalid_tlv_len;
1429                         capa->max_probe_length =
1430                                         le32_to_cpup((__le32 *)tlv_data);
1431                         break;
1432                 case IWL_UCODE_TLV_PAN:
1433                         if (tlv_len)
1434                                 goto invalid_tlv_len;
1435                         capa->pan = true;
1436                         break;
1437                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1438                         if (tlv_len != sizeof(u32))
1439                                 goto invalid_tlv_len;
1440                         pieces->init_evtlog_ptr =
1441                                         le32_to_cpup((__le32 *)tlv_data);
1442                         break;
1443                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1444                         if (tlv_len != sizeof(u32))
1445                                 goto invalid_tlv_len;
1446                         pieces->init_evtlog_size =
1447                                         le32_to_cpup((__le32 *)tlv_data);
1448                         break;
1449                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1450                         if (tlv_len != sizeof(u32))
1451                                 goto invalid_tlv_len;
1452                         pieces->init_errlog_ptr =
1453                                         le32_to_cpup((__le32 *)tlv_data);
1454                         break;
1455                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1456                         if (tlv_len != sizeof(u32))
1457                                 goto invalid_tlv_len;
1458                         pieces->inst_evtlog_ptr =
1459                                         le32_to_cpup((__le32 *)tlv_data);
1460                         break;
1461                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1462                         if (tlv_len != sizeof(u32))
1463                                 goto invalid_tlv_len;
1464                         pieces->inst_evtlog_size =
1465                                         le32_to_cpup((__le32 *)tlv_data);
1466                         break;
1467                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1468                         if (tlv_len != sizeof(u32))
1469                                 goto invalid_tlv_len;
1470                         pieces->inst_errlog_ptr =
1471                                         le32_to_cpup((__le32 *)tlv_data);
1472                         break;
1473                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1474                         if (tlv_len)
1475                                 goto invalid_tlv_len;
1476                         priv->enhance_sensitivity_table = true;
1477                         break;
1478                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1479                         if (tlv_len != sizeof(u32))
1480                                 goto invalid_tlv_len;
1481                         capa->standard_phy_calibration_size =
1482                                         le32_to_cpup((__le32 *)tlv_data);
1483                         break;
1484                 default:
1485                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1486                         break;
1487                 }
1488         }
1489
1490         if (len) {
1491                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1492                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1493                 return -EINVAL;
1494         }
1495
1496         return 0;
1497
1498  invalid_tlv_len:
1499         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1500         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1501
1502         return -EINVAL;
1503 }
1504
1505 /**
1506  * iwl_ucode_callback - callback when firmware was loaded
1507  *
1508  * If loaded successfully, copies the firmware into buffers
1509  * for the card to fetch (via DMA).
1510  */
1511 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1512 {
1513         struct iwl_priv *priv = context;
1514         struct iwl_ucode_header *ucode;
1515         int err;
1516         struct iwlagn_firmware_pieces pieces;
1517         const unsigned int api_max = priv->cfg->ucode_api_max;
1518         const unsigned int api_min = priv->cfg->ucode_api_min;
1519         u32 api_ver;
1520         char buildstr[25];
1521         u32 build;
1522         struct iwlagn_ucode_capabilities ucode_capa = {
1523                 .max_probe_length = 200,
1524                 .standard_phy_calibration_size =
1525                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1526         };
1527
1528         memset(&pieces, 0, sizeof(pieces));
1529
1530         if (!ucode_raw) {
1531                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1532                         IWL_ERR(priv,
1533                                 "request for firmware file '%s' failed.\n",
1534                                 priv->firmware_name);
1535                 goto try_again;
1536         }
1537
1538         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1539                        priv->firmware_name, ucode_raw->size);
1540
1541         /* Make sure that we got at least the API version number */
1542         if (ucode_raw->size < 4) {
1543                 IWL_ERR(priv, "File size way too small!\n");
1544                 goto try_again;
1545         }
1546
1547         /* Data from ucode file:  header followed by uCode images */
1548         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1549
1550         if (ucode->ver)
1551                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1552         else
1553                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1554                                            &ucode_capa);
1555
1556         if (err)
1557                 goto try_again;
1558
1559         api_ver = IWL_UCODE_API(priv->ucode_ver);
1560         build = pieces.build;
1561
1562         /*
1563          * api_ver should match the api version forming part of the
1564          * firmware filename ... but we don't check for that and only rely
1565          * on the API version read from firmware header from here on forward
1566          */
1567         /* no api version check required for experimental uCode */
1568         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1569                 if (api_ver < api_min || api_ver > api_max) {
1570                         IWL_ERR(priv,
1571                                 "Driver unable to support your firmware API. "
1572                                 "Driver supports v%u, firmware is v%u.\n",
1573                                 api_max, api_ver);
1574                         goto try_again;
1575                 }
1576
1577                 if (api_ver != api_max)
1578                         IWL_ERR(priv,
1579                                 "Firmware has old API version. Expected v%u, "
1580                                 "got v%u. New firmware can be obtained "
1581                                 "from http://www.intellinuxwireless.org.\n",
1582                                 api_max, api_ver);
1583         }
1584
1585         if (build)
1586                 sprintf(buildstr, " build %u%s", build,
1587                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1588                                 ? " (EXP)" : "");
1589         else
1590                 buildstr[0] = '\0';
1591
1592         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1593                  IWL_UCODE_MAJOR(priv->ucode_ver),
1594                  IWL_UCODE_MINOR(priv->ucode_ver),
1595                  IWL_UCODE_API(priv->ucode_ver),
1596                  IWL_UCODE_SERIAL(priv->ucode_ver),
1597                  buildstr);
1598
1599         snprintf(priv->hw->wiphy->fw_version,
1600                  sizeof(priv->hw->wiphy->fw_version),
1601                  "%u.%u.%u.%u%s",
1602                  IWL_UCODE_MAJOR(priv->ucode_ver),
1603                  IWL_UCODE_MINOR(priv->ucode_ver),
1604                  IWL_UCODE_API(priv->ucode_ver),
1605                  IWL_UCODE_SERIAL(priv->ucode_ver),
1606                  buildstr);
1607
1608         /*
1609          * For any of the failures below (before allocating pci memory)
1610          * we will try to load a version with a smaller API -- maybe the
1611          * user just got a corrupted version of the latest API.
1612          */
1613
1614         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1615                        priv->ucode_ver);
1616         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1617                        pieces.inst_size);
1618         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1619                        pieces.data_size);
1620         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1621                        pieces.init_size);
1622         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1623                        pieces.init_data_size);
1624         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
1625                        pieces.boot_size);
1626
1627         /* Verify that uCode images will fit in card's SRAM */
1628         if (pieces.inst_size > priv->hw_params.max_inst_size) {
1629                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1630                         pieces.inst_size);
1631                 goto try_again;
1632         }
1633
1634         if (pieces.data_size > priv->hw_params.max_data_size) {
1635                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1636                         pieces.data_size);
1637                 goto try_again;
1638         }
1639
1640         if (pieces.init_size > priv->hw_params.max_inst_size) {
1641                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1642                         pieces.init_size);
1643                 goto try_again;
1644         }
1645
1646         if (pieces.init_data_size > priv->hw_params.max_data_size) {
1647                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1648                         pieces.init_data_size);
1649                 goto try_again;
1650         }
1651
1652         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
1653                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
1654                         pieces.boot_size);
1655                 goto try_again;
1656         }
1657
1658         /* Allocate ucode buffers for card's bus-master loading ... */
1659
1660         /* Runtime instructions and 2 copies of data:
1661          * 1) unmodified from disk
1662          * 2) backup cache for save/restore during power-downs */
1663         priv->ucode_code.len = pieces.inst_size;
1664         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1665
1666         priv->ucode_data.len = pieces.data_size;
1667         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1668
1669         priv->ucode_data_backup.len = pieces.data_size;
1670         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1671
1672         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1673             !priv->ucode_data_backup.v_addr)
1674                 goto err_pci_alloc;
1675
1676         /* Initialization instructions and data */
1677         if (pieces.init_size && pieces.init_data_size) {
1678                 priv->ucode_init.len = pieces.init_size;
1679                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1680
1681                 priv->ucode_init_data.len = pieces.init_data_size;
1682                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1683
1684                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1685                         goto err_pci_alloc;
1686         }
1687
1688         /* Bootstrap (instructions only, no data) */
1689         if (pieces.boot_size) {
1690                 priv->ucode_boot.len = pieces.boot_size;
1691                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1692
1693                 if (!priv->ucode_boot.v_addr)
1694                         goto err_pci_alloc;
1695         }
1696
1697         /* Now that we can no longer fail, copy information */
1698
1699         /*
1700          * The (size - 16) / 12 formula is based on the information recorded
1701          * for each event, which is of mode 1 (including timestamp) for all
1702          * new microcodes that include this information.
1703          */
1704         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1705         if (pieces.init_evtlog_size)
1706                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1707         else
1708                 priv->_agn.init_evtlog_size =
1709                         priv->cfg->base_params->max_event_log_size;
1710         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1711         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1712         if (pieces.inst_evtlog_size)
1713                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1714         else
1715                 priv->_agn.inst_evtlog_size =
1716                         priv->cfg->base_params->max_event_log_size;
1717         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1718
1719         if (ucode_capa.pan) {
1720                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1721                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1722         } else
1723                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1724
1725         /* Copy images into buffers for card's bus-master reads ... */
1726
1727         /* Runtime instructions (first block of data in file) */
1728         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1729                         pieces.inst_size);
1730         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1731
1732         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1733                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1734
1735         /*
1736          * Runtime data
1737          * NOTE:  Copy into backup buffer will be done in iwl_up()
1738          */
1739         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1740                         pieces.data_size);
1741         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1742         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
1743
1744         /* Initialization instructions */
1745         if (pieces.init_size) {
1746                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1747                                 pieces.init_size);
1748                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1749         }
1750
1751         /* Initialization data */
1752         if (pieces.init_data_size) {
1753                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1754                                pieces.init_data_size);
1755                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1756                        pieces.init_data_size);
1757         }
1758
1759         /* Bootstrap instructions */
1760         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
1761                         pieces.boot_size);
1762         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
1763
1764         /*
1765          * figure out the offset of chain noise reset and gain commands
1766          * base on the size of standard phy calibration commands table size
1767          */
1768         if (ucode_capa.standard_phy_calibration_size >
1769             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1770                 ucode_capa.standard_phy_calibration_size =
1771                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1772
1773         priv->_agn.phy_calib_chain_noise_reset_cmd =
1774                 ucode_capa.standard_phy_calibration_size;
1775         priv->_agn.phy_calib_chain_noise_gain_cmd =
1776                 ucode_capa.standard_phy_calibration_size + 1;
1777
1778         /**************************************************
1779          * This is still part of probe() in a sense...
1780          *
1781          * 9. Setup and register with mac80211 and debugfs
1782          **************************************************/
1783         err = iwl_mac_setup_register(priv, &ucode_capa);
1784         if (err)
1785                 goto out_unbind;
1786
1787         err = iwl_dbgfs_register(priv, DRV_NAME);
1788         if (err)
1789                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1790
1791         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1792                                         &iwl_attribute_group);
1793         if (err) {
1794                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1795                 goto out_unbind;
1796         }
1797
1798         /* We have our copies now, allow OS release its copies */
1799         release_firmware(ucode_raw);
1800         complete(&priv->_agn.firmware_loading_complete);
1801         return;
1802
1803  try_again:
1804         /* try next, if any */
1805         if (iwl_request_firmware(priv, false))
1806                 goto out_unbind;
1807         release_firmware(ucode_raw);
1808         return;
1809
1810  err_pci_alloc:
1811         IWL_ERR(priv, "failed to allocate pci memory\n");
1812         iwl_dealloc_ucode_pci(priv);
1813  out_unbind:
1814         complete(&priv->_agn.firmware_loading_complete);
1815         device_release_driver(&priv->pci_dev->dev);
1816         release_firmware(ucode_raw);
1817 }
1818
1819 static const char *desc_lookup_text[] = {
1820         "OK",
1821         "FAIL",
1822         "BAD_PARAM",
1823         "BAD_CHECKSUM",
1824         "NMI_INTERRUPT_WDG",
1825         "SYSASSERT",
1826         "FATAL_ERROR",
1827         "BAD_COMMAND",
1828         "HW_ERROR_TUNE_LOCK",
1829         "HW_ERROR_TEMPERATURE",
1830         "ILLEGAL_CHAN_FREQ",
1831         "VCC_NOT_STABLE",
1832         "FH_ERROR",
1833         "NMI_INTERRUPT_HOST",
1834         "NMI_INTERRUPT_ACTION_PT",
1835         "NMI_INTERRUPT_UNKNOWN",
1836         "UCODE_VERSION_MISMATCH",
1837         "HW_ERROR_ABS_LOCK",
1838         "HW_ERROR_CAL_LOCK_FAIL",
1839         "NMI_INTERRUPT_INST_ACTION_PT",
1840         "NMI_INTERRUPT_DATA_ACTION_PT",
1841         "NMI_TRM_HW_ER",
1842         "NMI_INTERRUPT_TRM",
1843         "NMI_INTERRUPT_BREAK_POINT"
1844         "DEBUG_0",
1845         "DEBUG_1",
1846         "DEBUG_2",
1847         "DEBUG_3",
1848 };
1849
1850 static struct { char *name; u8 num; } advanced_lookup[] = {
1851         { "NMI_INTERRUPT_WDG", 0x34 },
1852         { "SYSASSERT", 0x35 },
1853         { "UCODE_VERSION_MISMATCH", 0x37 },
1854         { "BAD_COMMAND", 0x38 },
1855         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1856         { "FATAL_ERROR", 0x3D },
1857         { "NMI_TRM_HW_ERR", 0x46 },
1858         { "NMI_INTERRUPT_TRM", 0x4C },
1859         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1860         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1861         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1862         { "NMI_INTERRUPT_HOST", 0x66 },
1863         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1864         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1865         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1866         { "ADVANCED_SYSASSERT", 0 },
1867 };
1868
1869 static const char *desc_lookup(u32 num)
1870 {
1871         int i;
1872         int max = ARRAY_SIZE(desc_lookup_text);
1873
1874         if (num < max)
1875                 return desc_lookup_text[num];
1876
1877         max = ARRAY_SIZE(advanced_lookup) - 1;
1878         for (i = 0; i < max; i++) {
1879                 if (advanced_lookup[i].num == num)
1880                         break;;
1881         }
1882         return advanced_lookup[i].name;
1883 }
1884
1885 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1886 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1887
1888 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1889 {
1890         u32 data2, line;
1891         u32 desc, time, count, base, data1;
1892         u32 blink1, blink2, ilink1, ilink2;
1893         u32 pc, hcmd;
1894
1895         if (priv->ucode_type == UCODE_INIT) {
1896                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1897                 if (!base)
1898                         base = priv->_agn.init_errlog_ptr;
1899         } else {
1900                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1901                 if (!base)
1902                         base = priv->_agn.inst_errlog_ptr;
1903         }
1904
1905         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1906                 IWL_ERR(priv,
1907                         "Not valid error log pointer 0x%08X for %s uCode\n",
1908                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1909                 return;
1910         }
1911
1912         count = iwl_read_targ_mem(priv, base);
1913
1914         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1915                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1916                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1917                         priv->status, count);
1918         }
1919
1920         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1921         priv->isr_stats.err_code = desc;
1922         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
1923         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1924         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1925         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1926         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1927         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1928         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1929         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1930         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1931         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
1932
1933         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1934                                       blink1, blink2, ilink1, ilink2);
1935
1936         IWL_ERR(priv, "Desc                                  Time       "
1937                 "data1      data2      line\n");
1938         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1939                 desc_lookup(desc), desc, time, data1, data2, line);
1940         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
1941         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1942                 pc, blink1, blink2, ilink1, ilink2, hcmd);
1943 }
1944
1945 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1946
1947 /**
1948  * iwl_print_event_log - Dump error event log to syslog
1949  *
1950  */
1951 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1952                                u32 num_events, u32 mode,
1953                                int pos, char **buf, size_t bufsz)
1954 {
1955         u32 i;
1956         u32 base;       /* SRAM byte address of event log header */
1957         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1958         u32 ptr;        /* SRAM byte address of log data */
1959         u32 ev, time, data; /* event log data */
1960         unsigned long reg_flags;
1961
1962         if (num_events == 0)
1963                 return pos;
1964
1965         if (priv->ucode_type == UCODE_INIT) {
1966                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1967                 if (!base)
1968                         base = priv->_agn.init_evtlog_ptr;
1969         } else {
1970                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1971                 if (!base)
1972                         base = priv->_agn.inst_evtlog_ptr;
1973         }
1974
1975         if (mode == 0)
1976                 event_size = 2 * sizeof(u32);
1977         else
1978                 event_size = 3 * sizeof(u32);
1979
1980         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1981
1982         /* Make sure device is powered up for SRAM reads */
1983         spin_lock_irqsave(&priv->reg_lock, reg_flags);
1984         iwl_grab_nic_access(priv);
1985
1986         /* Set starting address; reads will auto-increment */
1987         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1988         rmb();
1989
1990         /* "time" is actually "data" for mode 0 (no timestamp).
1991         * place event id # at far right for easier visual parsing. */
1992         for (i = 0; i < num_events; i++) {
1993                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1994                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1995                 if (mode == 0) {
1996                         /* data, ev */
1997                         if (bufsz) {
1998                                 pos += scnprintf(*buf + pos, bufsz - pos,
1999                                                 "EVT_LOG:0x%08x:%04u\n",
2000                                                 time, ev);
2001                         } else {
2002                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2003                                         time, ev);
2004                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2005                                         time, ev);
2006                         }
2007                 } else {
2008                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2009                         if (bufsz) {
2010                                 pos += scnprintf(*buf + pos, bufsz - pos,
2011                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2012                                                  time, data, ev);
2013                         } else {
2014                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2015                                         time, data, ev);
2016                                 trace_iwlwifi_dev_ucode_event(priv, time,
2017                                         data, ev);
2018                         }
2019                 }
2020         }
2021
2022         /* Allow device to power down */
2023         iwl_release_nic_access(priv);
2024         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2025         return pos;
2026 }
2027
2028 /**
2029  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2030  */
2031 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2032                                     u32 num_wraps, u32 next_entry,
2033                                     u32 size, u32 mode,
2034                                     int pos, char **buf, size_t bufsz)
2035 {
2036         /*
2037          * display the newest DEFAULT_LOG_ENTRIES entries
2038          * i.e the entries just before the next ont that uCode would fill.
2039          */
2040         if (num_wraps) {
2041                 if (next_entry < size) {
2042                         pos = iwl_print_event_log(priv,
2043                                                 capacity - (size - next_entry),
2044                                                 size - next_entry, mode,
2045                                                 pos, buf, bufsz);
2046                         pos = iwl_print_event_log(priv, 0,
2047                                                   next_entry, mode,
2048                                                   pos, buf, bufsz);
2049                 } else
2050                         pos = iwl_print_event_log(priv, next_entry - size,
2051                                                   size, mode, pos, buf, bufsz);
2052         } else {
2053                 if (next_entry < size) {
2054                         pos = iwl_print_event_log(priv, 0, next_entry,
2055                                                   mode, pos, buf, bufsz);
2056                 } else {
2057                         pos = iwl_print_event_log(priv, next_entry - size,
2058                                                   size, mode, pos, buf, bufsz);
2059                 }
2060         }
2061         return pos;
2062 }
2063
2064 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2065
2066 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2067                             char **buf, bool display)
2068 {
2069         u32 base;       /* SRAM byte address of event log header */
2070         u32 capacity;   /* event log capacity in # entries */
2071         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2072         u32 num_wraps;  /* # times uCode wrapped to top of log */
2073         u32 next_entry; /* index of next entry to be written by uCode */
2074         u32 size;       /* # entries that we'll print */
2075         u32 logsize;
2076         int pos = 0;
2077         size_t bufsz = 0;
2078
2079         if (priv->ucode_type == UCODE_INIT) {
2080                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2081                 logsize = priv->_agn.init_evtlog_size;
2082                 if (!base)
2083                         base = priv->_agn.init_evtlog_ptr;
2084         } else {
2085                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2086                 logsize = priv->_agn.inst_evtlog_size;
2087                 if (!base)
2088                         base = priv->_agn.inst_evtlog_ptr;
2089         }
2090
2091         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2092                 IWL_ERR(priv,
2093                         "Invalid event log pointer 0x%08X for %s uCode\n",
2094                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2095                 return -EINVAL;
2096         }
2097
2098         /* event log header */
2099         capacity = iwl_read_targ_mem(priv, base);
2100         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2101         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2102         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2103
2104         if (capacity > logsize) {
2105                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2106                         capacity, logsize);
2107                 capacity = logsize;
2108         }
2109
2110         if (next_entry > logsize) {
2111                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2112                         next_entry, logsize);
2113                 next_entry = logsize;
2114         }
2115
2116         size = num_wraps ? capacity : next_entry;
2117
2118         /* bail out if nothing in log */
2119         if (size == 0) {
2120                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2121                 return pos;
2122         }
2123
2124         /* enable/disable bt channel inhibition */
2125         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2126
2127 #ifdef CONFIG_IWLWIFI_DEBUG
2128         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2129                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2130                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2131 #else
2132         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2133                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2134 #endif
2135         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2136                 size);
2137
2138 #ifdef CONFIG_IWLWIFI_DEBUG
2139         if (display) {
2140                 if (full_log)
2141                         bufsz = capacity * 48;
2142                 else
2143                         bufsz = size * 48;
2144                 *buf = kmalloc(bufsz, GFP_KERNEL);
2145                 if (!*buf)
2146                         return -ENOMEM;
2147         }
2148         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2149                 /*
2150                  * if uCode has wrapped back to top of log,
2151                  * start at the oldest entry,
2152                  * i.e the next one that uCode would fill.
2153                  */
2154                 if (num_wraps)
2155                         pos = iwl_print_event_log(priv, next_entry,
2156                                                 capacity - next_entry, mode,
2157                                                 pos, buf, bufsz);
2158                 /* (then/else) start at top of log */
2159                 pos = iwl_print_event_log(priv, 0,
2160                                           next_entry, mode, pos, buf, bufsz);
2161         } else
2162                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2163                                                 next_entry, size, mode,
2164                                                 pos, buf, bufsz);
2165 #else
2166         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2167                                         next_entry, size, mode,
2168                                         pos, buf, bufsz);
2169 #endif
2170         return pos;
2171 }
2172
2173 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2174 {
2175         struct iwl_ct_kill_config cmd;
2176         struct iwl_ct_kill_throttling_config adv_cmd;
2177         unsigned long flags;
2178         int ret = 0;
2179
2180         spin_lock_irqsave(&priv->lock, flags);
2181         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2182                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2183         spin_unlock_irqrestore(&priv->lock, flags);
2184         priv->thermal_throttle.ct_kill_toggle = false;
2185
2186         if (priv->cfg->base_params->support_ct_kill_exit) {
2187                 adv_cmd.critical_temperature_enter =
2188                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2189                 adv_cmd.critical_temperature_exit =
2190                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2191
2192                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2193                                        sizeof(adv_cmd), &adv_cmd);
2194                 if (ret)
2195                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2196                 else
2197                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2198                                         "succeeded, "
2199                                         "critical temperature enter is %d,"
2200                                         "exit is %d\n",
2201                                        priv->hw_params.ct_kill_threshold,
2202                                        priv->hw_params.ct_kill_exit_threshold);
2203         } else {
2204                 cmd.critical_temperature_R =
2205                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2206
2207                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2208                                        sizeof(cmd), &cmd);
2209                 if (ret)
2210                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2211                 else
2212                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2213                                         "succeeded, "
2214                                         "critical temperature is %d\n",
2215                                         priv->hw_params.ct_kill_threshold);
2216         }
2217 }
2218
2219 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2220 {
2221         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2222         struct iwl_host_cmd cmd = {
2223                 .id = CALIBRATION_CFG_CMD,
2224                 .len = sizeof(struct iwl_calib_cfg_cmd),
2225                 .data = &calib_cfg_cmd,
2226         };
2227
2228         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2229         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2230         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2231
2232         return iwl_send_cmd(priv, &cmd);
2233 }
2234
2235
2236 /**
2237  * iwl_alive_start - called after REPLY_ALIVE notification received
2238  *                   from protocol/runtime uCode (initialization uCode's
2239  *                   Alive gets handled by iwl_init_alive_start()).
2240  */
2241 static void iwl_alive_start(struct iwl_priv *priv)
2242 {
2243         int ret = 0;
2244         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2245
2246         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2247
2248         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2249          * This is a paranoid check, because we would not have gotten the
2250          * "runtime" alive if code weren't properly loaded.  */
2251         if (iwl_verify_ucode(priv)) {
2252                 /* Runtime instruction load was bad;
2253                  * take it all the way back down so we can try again */
2254                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2255                 goto restart;
2256         }
2257
2258         ret = priv->cfg->ops->lib->alive_notify(priv);
2259         if (ret) {
2260                 IWL_WARN(priv,
2261                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2262                 goto restart;
2263         }
2264
2265
2266         /* After the ALIVE response, we can send host commands to the uCode */
2267         set_bit(STATUS_ALIVE, &priv->status);
2268
2269         /* Enable watchdog to monitor the driver tx queues */
2270         iwl_setup_watchdog(priv);
2271
2272         if (iwl_is_rfkill(priv))
2273                 return;
2274
2275         /* download priority table before any calibration request */
2276         if (priv->cfg->bt_params &&
2277             priv->cfg->bt_params->advanced_bt_coexist) {
2278                 /* Configure Bluetooth device coexistence support */
2279                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2280                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2281                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2282                 priv->cfg->ops->hcmd->send_bt_config(priv);
2283                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2284                 iwlagn_send_prio_tbl(priv);
2285
2286                 /* FIXME: w/a to force change uCode BT state machine */
2287                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2288                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2289                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2290                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2291         }
2292         if (priv->hw_params.calib_rt_cfg)
2293                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2294
2295         ieee80211_wake_queues(priv->hw);
2296
2297         priv->active_rate = IWL_RATES_MASK;
2298
2299         /* Configure Tx antenna selection based on H/W config */
2300         if (priv->cfg->ops->hcmd->set_tx_ant)
2301                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2302
2303         if (iwl_is_associated_ctx(ctx)) {
2304                 struct iwl_rxon_cmd *active_rxon =
2305                                 (struct iwl_rxon_cmd *)&ctx->active;
2306                 /* apply any changes in staging */
2307                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2308                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2309         } else {
2310                 struct iwl_rxon_context *tmp;
2311                 /* Initialize our rx_config data */
2312                 for_each_context(priv, tmp)
2313                         iwl_connection_init_rx_config(priv, tmp);
2314
2315                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2316                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2317         }
2318
2319         if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2320             !priv->cfg->bt_params->advanced_bt_coexist)) {
2321                 /*
2322                  * default is 2-wire BT coexexistence support
2323                  */
2324                 priv->cfg->ops->hcmd->send_bt_config(priv);
2325         }
2326
2327         iwl_reset_run_time_calib(priv);
2328
2329         set_bit(STATUS_READY, &priv->status);
2330
2331         /* Configure the adapter for unassociated operation */
2332         iwlcore_commit_rxon(priv, ctx);
2333
2334         /* At this point, the NIC is initialized and operational */
2335         iwl_rf_kill_ct_config(priv);
2336
2337         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2338         wake_up_interruptible(&priv->wait_command_queue);
2339
2340         iwl_power_update_mode(priv, true);
2341         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2342
2343
2344         return;
2345
2346  restart:
2347         queue_work(priv->workqueue, &priv->restart);
2348 }
2349
2350 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2351
2352 static void __iwl_down(struct iwl_priv *priv)
2353 {
2354         unsigned long flags;
2355         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2356
2357         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2358
2359         iwl_scan_cancel_timeout(priv, 200);
2360
2361         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2362
2363         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2364          * to prevent rearm timer */
2365         del_timer_sync(&priv->watchdog);
2366
2367         iwl_clear_ucode_stations(priv, NULL);
2368         iwl_dealloc_bcast_stations(priv);
2369         iwl_clear_driver_stations(priv);
2370
2371         /* reset BT coex data */
2372         priv->bt_status = 0;
2373         if (priv->cfg->bt_params)
2374                 priv->bt_traffic_load =
2375                          priv->cfg->bt_params->bt_init_traffic_load;
2376         else
2377                 priv->bt_traffic_load = 0;
2378         priv->bt_full_concurrent = false;
2379         priv->bt_ci_compliance = 0;
2380
2381         /* Unblock any waiting calls */
2382         wake_up_interruptible_all(&priv->wait_command_queue);
2383
2384         /* Wipe out the EXIT_PENDING status bit if we are not actually
2385          * exiting the module */
2386         if (!exit_pending)
2387                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2388
2389         /* stop and reset the on-board processor */
2390         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2391
2392         /* tell the device to stop sending interrupts */
2393         spin_lock_irqsave(&priv->lock, flags);
2394         iwl_disable_interrupts(priv);
2395         spin_unlock_irqrestore(&priv->lock, flags);
2396         iwl_synchronize_irq(priv);
2397
2398         if (priv->mac80211_registered)
2399                 ieee80211_stop_queues(priv->hw);
2400
2401         /* If we have not previously called iwl_init() then
2402          * clear all bits but the RF Kill bit and return */
2403         if (!iwl_is_init(priv)) {
2404                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2405                                         STATUS_RF_KILL_HW |
2406                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2407                                         STATUS_GEO_CONFIGURED |
2408                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2409                                         STATUS_EXIT_PENDING;
2410                 goto exit;
2411         }
2412
2413         /* ...otherwise clear out all the status bits but the RF Kill
2414          * bit and continue taking the NIC down. */
2415         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2416                                 STATUS_RF_KILL_HW |
2417                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2418                                 STATUS_GEO_CONFIGURED |
2419                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2420                                 STATUS_FW_ERROR |
2421                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2422                                 STATUS_EXIT_PENDING;
2423
2424         /* device going down, Stop using ICT table */
2425         if (priv->cfg->ops->lib->isr_ops.disable)
2426                 priv->cfg->ops->lib->isr_ops.disable(priv);
2427
2428         iwlagn_txq_ctx_stop(priv);
2429         iwlagn_rxq_stop(priv);
2430
2431         /* Power-down device's busmaster DMA clocks */
2432         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2433         udelay(5);
2434
2435         /* Make sure (redundant) we've released our request to stay awake */
2436         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2437
2438         /* Stop the device, and put it in low power state */
2439         iwl_apm_stop(priv);
2440
2441  exit:
2442         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2443
2444         dev_kfree_skb(priv->beacon_skb);
2445         priv->beacon_skb = NULL;
2446
2447         /* clear out any free frames */
2448         iwl_clear_free_frames(priv);
2449 }
2450
2451 static void iwl_down(struct iwl_priv *priv)
2452 {
2453         mutex_lock(&priv->mutex);
2454         __iwl_down(priv);
2455         mutex_unlock(&priv->mutex);
2456
2457         iwl_cancel_deferred_work(priv);
2458 }
2459
2460 #define HW_READY_TIMEOUT (50)
2461
2462 static int iwl_set_hw_ready(struct iwl_priv *priv)
2463 {
2464         int ret = 0;
2465
2466         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2467                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2468
2469         /* See if we got it */
2470         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2471                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2472                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2473                                 HW_READY_TIMEOUT);
2474         if (ret != -ETIMEDOUT)
2475                 priv->hw_ready = true;
2476         else
2477                 priv->hw_ready = false;
2478
2479         IWL_DEBUG_INFO(priv, "hardware %s\n",
2480                       (priv->hw_ready == 1) ? "ready" : "not ready");
2481         return ret;
2482 }
2483
2484 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2485 {
2486         int ret = 0;
2487
2488         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2489
2490         ret = iwl_set_hw_ready(priv);
2491         if (priv->hw_ready)
2492                 return ret;
2493
2494         /* If HW is not ready, prepare the conditions to check again */
2495         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2496                         CSR_HW_IF_CONFIG_REG_PREPARE);
2497
2498         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2499                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2500                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2501
2502         /* HW should be ready by now, check again. */
2503         if (ret != -ETIMEDOUT)
2504                 iwl_set_hw_ready(priv);
2505
2506         return ret;
2507 }
2508
2509 #define MAX_HW_RESTARTS 5
2510
2511 static int __iwl_up(struct iwl_priv *priv)
2512 {
2513         struct iwl_rxon_context *ctx;
2514         int i;
2515         int ret;
2516
2517         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2518                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2519                 return -EIO;
2520         }
2521
2522         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2523                 IWL_ERR(priv, "ucode not available for device bringup\n");
2524                 return -EIO;
2525         }
2526
2527         for_each_context(priv, ctx) {
2528                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2529                 if (ret) {
2530                         iwl_dealloc_bcast_stations(priv);
2531                         return ret;
2532                 }
2533         }
2534
2535         iwl_prepare_card_hw(priv);
2536
2537         if (!priv->hw_ready) {
2538                 IWL_WARN(priv, "Exit HW not ready\n");
2539                 return -EIO;
2540         }
2541
2542         /* If platform's RF_KILL switch is NOT set to KILL */
2543         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2544                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2545         else
2546                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2547
2548         if (iwl_is_rfkill(priv)) {
2549                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2550
2551                 iwl_enable_interrupts(priv);
2552                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2553                 return 0;
2554         }
2555
2556         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2557
2558         /* must be initialised before iwl_hw_nic_init */
2559         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2560                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2561         else
2562                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2563
2564         ret = iwlagn_hw_nic_init(priv);
2565         if (ret) {
2566                 IWL_ERR(priv, "Unable to init nic\n");
2567                 return ret;
2568         }
2569
2570         /* make sure rfkill handshake bits are cleared */
2571         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2572         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2573                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2574
2575         /* clear (again), then enable host interrupts */
2576         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2577         iwl_enable_interrupts(priv);
2578
2579         /* really make sure rfkill handshake bits are cleared */
2580         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2581         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2582
2583         /* Copy original ucode data image from disk into backup cache.
2584          * This will be used to initialize the on-board processor's
2585          * data SRAM for a clean start when the runtime program first loads. */
2586         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2587                priv->ucode_data.len);
2588
2589         for (i = 0; i < MAX_HW_RESTARTS; i++) {
2590
2591                 /* load bootstrap state machine,
2592                  * load bootstrap program into processor's memory,
2593                  * prepare to load the "initialize" uCode */
2594                 ret = priv->cfg->ops->lib->load_ucode(priv);
2595
2596                 if (ret) {
2597                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2598                                 ret);
2599                         continue;
2600                 }
2601
2602                 /* start card; "initialize" will load runtime ucode */
2603                 iwl_nic_start(priv);
2604
2605                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2606
2607                 return 0;
2608         }
2609
2610         set_bit(STATUS_EXIT_PENDING, &priv->status);
2611         __iwl_down(priv);
2612         clear_bit(STATUS_EXIT_PENDING, &priv->status);
2613
2614         /* tried to restart and config the device for as long as our
2615          * patience could withstand */
2616         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2617         return -EIO;
2618 }
2619
2620
2621 /*****************************************************************************
2622  *
2623  * Workqueue callbacks
2624  *
2625  *****************************************************************************/
2626
2627 static void iwl_bg_init_alive_start(struct work_struct *data)
2628 {
2629         struct iwl_priv *priv =
2630             container_of(data, struct iwl_priv, init_alive_start.work);
2631
2632         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2633                 return;
2634
2635         mutex_lock(&priv->mutex);
2636         priv->cfg->ops->lib->init_alive_start(priv);
2637         mutex_unlock(&priv->mutex);
2638 }
2639
2640 static void iwl_bg_alive_start(struct work_struct *data)
2641 {
2642         struct iwl_priv *priv =
2643             container_of(data, struct iwl_priv, alive_start.work);
2644
2645         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2646                 return;
2647
2648         /* enable dram interrupt */
2649         if (priv->cfg->ops->lib->isr_ops.reset)
2650                 priv->cfg->ops->lib->isr_ops.reset(priv);
2651
2652         mutex_lock(&priv->mutex);
2653         iwl_alive_start(priv);
2654         mutex_unlock(&priv->mutex);
2655 }
2656
2657 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2658 {
2659         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2660                         run_time_calib_work);
2661
2662         mutex_lock(&priv->mutex);
2663
2664         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2665             test_bit(STATUS_SCANNING, &priv->status)) {
2666                 mutex_unlock(&priv->mutex);
2667                 return;
2668         }
2669
2670         if (priv->start_calib) {
2671                 if (iwl_bt_statistics(priv)) {
2672                         iwl_chain_noise_calibration(priv,
2673                                         (void *)&priv->_agn.statistics_bt);
2674                         iwl_sensitivity_calibration(priv,
2675                                         (void *)&priv->_agn.statistics_bt);
2676                 } else {
2677                         iwl_chain_noise_calibration(priv,
2678                                         (void *)&priv->_agn.statistics);
2679                         iwl_sensitivity_calibration(priv,
2680                                         (void *)&priv->_agn.statistics);
2681                 }
2682         }
2683
2684         mutex_unlock(&priv->mutex);
2685 }
2686
2687 static void iwl_bg_restart(struct work_struct *data)
2688 {
2689         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2690
2691         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2692                 return;
2693
2694         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2695                 struct iwl_rxon_context *ctx;
2696                 bool bt_full_concurrent;
2697                 u8 bt_ci_compliance;
2698                 u8 bt_load;
2699                 u8 bt_status;
2700
2701                 mutex_lock(&priv->mutex);
2702                 for_each_context(priv, ctx)
2703                         ctx->vif = NULL;
2704                 priv->is_open = 0;
2705
2706                 /*
2707                  * __iwl_down() will clear the BT status variables,
2708                  * which is correct, but when we restart we really
2709                  * want to keep them so restore them afterwards.
2710                  *
2711                  * The restart process will later pick them up and
2712                  * re-configure the hw when we reconfigure the BT
2713                  * command.
2714                  */
2715                 bt_full_concurrent = priv->bt_full_concurrent;
2716                 bt_ci_compliance = priv->bt_ci_compliance;
2717                 bt_load = priv->bt_traffic_load;
2718                 bt_status = priv->bt_status;
2719
2720                 __iwl_down(priv);
2721
2722                 priv->bt_full_concurrent = bt_full_concurrent;
2723                 priv->bt_ci_compliance = bt_ci_compliance;
2724                 priv->bt_traffic_load = bt_load;
2725                 priv->bt_status = bt_status;
2726
2727                 mutex_unlock(&priv->mutex);
2728                 iwl_cancel_deferred_work(priv);
2729                 ieee80211_restart_hw(priv->hw);
2730         } else {
2731                 iwl_down(priv);
2732
2733                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2734                         return;
2735
2736                 mutex_lock(&priv->mutex);
2737                 __iwl_up(priv);
2738                 mutex_unlock(&priv->mutex);
2739         }
2740 }
2741
2742 static void iwl_bg_rx_replenish(struct work_struct *data)
2743 {
2744         struct iwl_priv *priv =
2745             container_of(data, struct iwl_priv, rx_replenish);
2746
2747         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2748                 return;
2749
2750         mutex_lock(&priv->mutex);
2751         iwlagn_rx_replenish(priv);
2752         mutex_unlock(&priv->mutex);
2753 }
2754
2755 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2756                                  struct ieee80211_channel *chan,
2757                                  enum nl80211_channel_type channel_type,
2758                                  unsigned int wait)
2759 {
2760         struct iwl_priv *priv = hw->priv;
2761         int ret;
2762
2763         /* Not supported if we don't have PAN */
2764         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2765                 ret = -EOPNOTSUPP;
2766                 goto free;
2767         }
2768
2769         /* Not supported on pre-P2P firmware */
2770         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2771                                         BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2772                 ret = -EOPNOTSUPP;
2773                 goto free;
2774         }
2775
2776         mutex_lock(&priv->mutex);
2777
2778         if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2779                 /*
2780                  * If the PAN context is free, use the normal
2781                  * way of doing remain-on-channel offload + TX.
2782                  */
2783                 ret = 1;
2784                 goto out;
2785         }
2786
2787         /* TODO: queue up if scanning? */
2788         if (test_bit(STATUS_SCANNING, &priv->status) ||
2789             priv->_agn.offchan_tx_skb) {
2790                 ret = -EBUSY;
2791                 goto out;
2792         }
2793
2794         /*
2795          * max_scan_ie_len doesn't include the blank SSID or the header,
2796          * so need to add that again here.
2797          */
2798         if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2799                 ret = -ENOBUFS;
2800                 goto out;
2801         }
2802
2803         priv->_agn.offchan_tx_skb = skb;
2804         priv->_agn.offchan_tx_timeout = wait;
2805         priv->_agn.offchan_tx_chan = chan;
2806
2807         ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2808                                 IWL_SCAN_OFFCH_TX, chan->band);
2809         if (ret)
2810                 priv->_agn.offchan_tx_skb = NULL;
2811  out:
2812         mutex_unlock(&priv->mutex);
2813  free:
2814         if (ret < 0)
2815                 kfree_skb(skb);
2816
2817         return ret;
2818 }
2819
2820 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2821 {
2822         struct iwl_priv *priv = hw->priv;
2823         int ret;
2824
2825         mutex_lock(&priv->mutex);
2826
2827         if (!priv->_agn.offchan_tx_skb)
2828                 return -EINVAL;
2829
2830         priv->_agn.offchan_tx_skb = NULL;
2831
2832         ret = iwl_scan_cancel_timeout(priv, 200);
2833         if (ret)
2834                 ret = -EIO;
2835         mutex_unlock(&priv->mutex);
2836
2837         return ret;
2838 }
2839
2840 /*****************************************************************************
2841  *
2842  * mac80211 entry point functions
2843  *
2844  *****************************************************************************/
2845
2846 #define UCODE_READY_TIMEOUT     (4 * HZ)
2847
2848 /*
2849  * Not a mac80211 entry point function, but it fits in with all the
2850  * other mac80211 functions grouped here.
2851  */
2852 static int iwl_mac_setup_register(struct iwl_priv *priv,
2853                                   struct iwlagn_ucode_capabilities *capa)
2854 {
2855         int ret;
2856         struct ieee80211_hw *hw = priv->hw;
2857         struct iwl_rxon_context *ctx;
2858
2859         hw->rate_control_algorithm = "iwl-agn-rs";
2860
2861         /* Tell mac80211 our characteristics */
2862         hw->flags = IEEE80211_HW_SIGNAL_DBM |
2863                     IEEE80211_HW_AMPDU_AGGREGATION |
2864                     IEEE80211_HW_NEED_DTIM_PERIOD |
2865                     IEEE80211_HW_SPECTRUM_MGMT |
2866                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2867
2868         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2869
2870         if (!priv->cfg->base_params->broken_powersave)
2871                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2872                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2873
2874         if (priv->cfg->sku & IWL_SKU_N)
2875                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2876                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2877
2878         hw->sta_data_size = sizeof(struct iwl_station_priv);
2879         hw->vif_data_size = sizeof(struct iwl_vif_priv);
2880
2881         for_each_context(priv, ctx) {
2882                 hw->wiphy->interface_modes |= ctx->interface_modes;
2883                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2884         }
2885
2886         hw->wiphy->max_remain_on_channel_duration = 1000;
2887
2888         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2889                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
2890                             WIPHY_FLAG_IBSS_RSN;
2891
2892         /*
2893          * For now, disable PS by default because it affects
2894          * RX performance significantly.
2895          */
2896         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2897
2898         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2899         /* we create the 802.11 header and a zero-length SSID element */
2900         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2901
2902         /* Default value; 4 EDCA QOS priorities */
2903         hw->queues = 4;
2904
2905         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2906
2907         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2908                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2909                         &priv->bands[IEEE80211_BAND_2GHZ];
2910         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2911                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2912                         &priv->bands[IEEE80211_BAND_5GHZ];
2913
2914         iwl_leds_init(priv);
2915
2916         ret = ieee80211_register_hw(priv->hw);
2917         if (ret) {
2918                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2919                 return ret;
2920         }
2921         priv->mac80211_registered = 1;
2922
2923         return 0;
2924 }
2925
2926
2927 int iwlagn_mac_start(struct ieee80211_hw *hw)
2928 {
2929         struct iwl_priv *priv = hw->priv;
2930         int ret;
2931
2932         IWL_DEBUG_MAC80211(priv, "enter\n");
2933
2934         /* we should be verifying the device is ready to be opened */
2935         mutex_lock(&priv->mutex);
2936         ret = __iwl_up(priv);
2937         mutex_unlock(&priv->mutex);
2938
2939         if (ret)
2940                 return ret;
2941
2942         if (iwl_is_rfkill(priv))
2943                 goto out;
2944
2945         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2946
2947         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2948          * mac80211 will not be run successfully. */
2949         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2950                         test_bit(STATUS_READY, &priv->status),
2951                         UCODE_READY_TIMEOUT);
2952         if (!ret) {
2953                 if (!test_bit(STATUS_READY, &priv->status)) {
2954                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2955                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2956                         return -ETIMEDOUT;
2957                 }
2958         }
2959
2960         iwlagn_led_enable(priv);
2961
2962 out:
2963         priv->is_open = 1;
2964         IWL_DEBUG_MAC80211(priv, "leave\n");
2965         return 0;
2966 }
2967
2968 void iwlagn_mac_stop(struct ieee80211_hw *hw)
2969 {
2970         struct iwl_priv *priv = hw->priv;
2971
2972         IWL_DEBUG_MAC80211(priv, "enter\n");
2973
2974         if (!priv->is_open)
2975                 return;
2976
2977         priv->is_open = 0;
2978
2979         iwl_down(priv);
2980
2981         flush_workqueue(priv->workqueue);
2982
2983         /* User space software may expect getting rfkill changes
2984          * even if interface is down */
2985         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2986         iwl_enable_rfkill_int(priv);
2987
2988         IWL_DEBUG_MAC80211(priv, "leave\n");
2989 }
2990
2991 void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2992 {
2993         struct iwl_priv *priv = hw->priv;
2994
2995         IWL_DEBUG_MACDUMP(priv, "enter\n");
2996
2997         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2998                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2999
3000         if (iwlagn_tx_skb(priv, skb))
3001                 dev_kfree_skb_any(skb);
3002
3003         IWL_DEBUG_MACDUMP(priv, "leave\n");
3004 }
3005
3006 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3007                                 struct ieee80211_vif *vif,
3008                                 struct ieee80211_key_conf *keyconf,
3009                                 struct ieee80211_sta *sta,
3010                                 u32 iv32, u16 *phase1key)
3011 {
3012         struct iwl_priv *priv = hw->priv;
3013         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3014
3015         IWL_DEBUG_MAC80211(priv, "enter\n");
3016
3017         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3018                             iv32, phase1key);
3019
3020         IWL_DEBUG_MAC80211(priv, "leave\n");
3021 }
3022
3023 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3024                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3025                        struct ieee80211_key_conf *key)
3026 {
3027         struct iwl_priv *priv = hw->priv;
3028         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3029         struct iwl_rxon_context *ctx = vif_priv->ctx;
3030         int ret;
3031         u8 sta_id;
3032         bool is_default_wep_key = false;
3033
3034         IWL_DEBUG_MAC80211(priv, "enter\n");
3035
3036         if (priv->cfg->mod_params->sw_crypto) {
3037                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3038                 return -EOPNOTSUPP;
3039         }
3040
3041         /*
3042          * To support IBSS RSN, don't program group keys in IBSS, the
3043          * hardware will then not attempt to decrypt the frames.
3044          */
3045         if (vif->type == NL80211_IFTYPE_ADHOC &&
3046             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3047                 return -EOPNOTSUPP;
3048
3049         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3050         if (sta_id == IWL_INVALID_STATION)
3051                 return -EINVAL;
3052
3053         mutex_lock(&priv->mutex);
3054         iwl_scan_cancel_timeout(priv, 100);
3055
3056         /*
3057          * If we are getting WEP group key and we didn't receive any key mapping
3058          * so far, we are in legacy wep mode (group key only), otherwise we are
3059          * in 1X mode.
3060          * In legacy wep mode, we use another host command to the uCode.
3061          */
3062         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3063              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3064             !sta) {
3065                 if (cmd == SET_KEY)
3066                         is_default_wep_key = !ctx->key_mapping_keys;
3067                 else
3068                         is_default_wep_key =
3069                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3070         }
3071
3072         switch (cmd) {
3073         case SET_KEY:
3074                 if (is_default_wep_key)
3075                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3076                 else
3077                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3078                                                   key, sta_id);
3079
3080                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3081                 break;
3082         case DISABLE_KEY:
3083                 if (is_default_wep_key)
3084                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3085                 else
3086                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3087
3088                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3089                 break;
3090         default:
3091                 ret = -EINVAL;
3092         }
3093
3094         mutex_unlock(&priv->mutex);
3095         IWL_DEBUG_MAC80211(priv, "leave\n");
3096
3097         return ret;
3098 }
3099
3100 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3101                             struct ieee80211_vif *vif,
3102                             enum ieee80211_ampdu_mlme_action action,
3103                             struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3104                             u8 buf_size)
3105 {
3106         struct iwl_priv *priv = hw->priv;
3107         int ret = -EINVAL;
3108         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3109
3110         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3111                      sta->addr, tid);
3112
3113         if (!(priv->cfg->sku & IWL_SKU_N))
3114                 return -EACCES;
3115
3116         mutex_lock(&priv->mutex);
3117
3118         switch (action) {
3119         case IEEE80211_AMPDU_RX_START:
3120                 IWL_DEBUG_HT(priv, "start Rx\n");
3121                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3122                 break;
3123         case IEEE80211_AMPDU_RX_STOP:
3124                 IWL_DEBUG_HT(priv, "stop Rx\n");
3125                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3126                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3127                         ret = 0;
3128                 break;
3129         case IEEE80211_AMPDU_TX_START:
3130                 IWL_DEBUG_HT(priv, "start Tx\n");
3131                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3132                 if (ret == 0) {
3133                         priv->_agn.agg_tids_count++;
3134                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3135                                      priv->_agn.agg_tids_count);
3136                 }
3137                 break;
3138         case IEEE80211_AMPDU_TX_STOP:
3139                 IWL_DEBUG_HT(priv, "stop Tx\n");
3140                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3141                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3142                         priv->_agn.agg_tids_count--;
3143                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3144                                      priv->_agn.agg_tids_count);
3145                 }
3146                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3147                         ret = 0;
3148                 if (priv->cfg->ht_params &&
3149                     priv->cfg->ht_params->use_rts_for_aggregation) {
3150                         struct iwl_station_priv *sta_priv =
3151                                 (void *) sta->drv_priv;
3152                         /*
3153                          * switch off RTS/CTS if it was previously enabled
3154                          */
3155
3156                         sta_priv->lq_sta.lq.general_params.flags &=
3157                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3158                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3159                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3160                 }
3161                 break;
3162         case IEEE80211_AMPDU_TX_OPERATIONAL:
3163                 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
3164
3165                 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
3166
3167                 /*
3168                  * If the limit is 0, then it wasn't initialised yet,
3169                  * use the default. We can do that since we take the
3170                  * minimum below, and we don't want to go above our
3171                  * default due to hardware restrictions.
3172                  */
3173                 if (sta_priv->max_agg_bufsize == 0)
3174                         sta_priv->max_agg_bufsize =
3175                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3176
3177                 /*
3178                  * Even though in theory the peer could have different
3179                  * aggregation reorder buffer sizes for different sessions,
3180                  * our ucode doesn't allow for that and has a global limit
3181                  * for each station. Therefore, use the minimum of all the
3182                  * aggregation sessions and our default value.
3183                  */
3184                 sta_priv->max_agg_bufsize =
3185                         min(sta_priv->max_agg_bufsize, buf_size);
3186
3187                 if (priv->cfg->ht_params &&
3188                     priv->cfg->ht_params->use_rts_for_aggregation) {
3189                         /*
3190                          * switch to RTS/CTS if it is the prefer protection
3191                          * method for HT traffic
3192                          */
3193
3194                         sta_priv->lq_sta.lq.general_params.flags |=
3195                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3196                 }
3197
3198                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3199                         sta_priv->max_agg_bufsize;
3200
3201                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3202                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3203                 ret = 0;
3204                 break;
3205         }
3206         mutex_unlock(&priv->mutex);
3207
3208         return ret;
3209 }
3210
3211 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3212                        struct ieee80211_vif *vif,
3213                        struct ieee80211_sta *sta)
3214 {
3215         struct iwl_priv *priv = hw->priv;
3216         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3217         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3218         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3219         int ret;
3220         u8 sta_id;
3221
3222         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3223                         sta->addr);
3224         mutex_lock(&priv->mutex);
3225         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3226                         sta->addr);
3227         sta_priv->common.sta_id = IWL_INVALID_STATION;
3228
3229         atomic_set(&sta_priv->pending_frames, 0);
3230         if (vif->type == NL80211_IFTYPE_AP)
3231                 sta_priv->client = true;
3232
3233         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3234                                      is_ap, sta, &sta_id);
3235         if (ret) {
3236                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3237                         sta->addr, ret);
3238                 /* Should we return success if return code is EEXIST ? */
3239                 mutex_unlock(&priv->mutex);
3240                 return ret;
3241         }
3242
3243         sta_priv->common.sta_id = sta_id;
3244
3245         /* Initialize rate scaling */
3246         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3247                        sta->addr);
3248         iwl_rs_rate_init(priv, sta, sta_id);
3249         mutex_unlock(&priv->mutex);
3250
3251         return 0;
3252 }
3253
3254 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3255                                struct ieee80211_channel_switch *ch_switch)
3256 {
3257         struct iwl_priv *priv = hw->priv;
3258         const struct iwl_channel_info *ch_info;
3259         struct ieee80211_conf *conf = &hw->conf;
3260         struct ieee80211_channel *channel = ch_switch->channel;
3261         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3262         /*
3263          * MULTI-FIXME
3264          * When we add support for multiple interfaces, we need to
3265          * revisit this. The channel switch command in the device
3266          * only affects the BSS context, but what does that really
3267          * mean? And what if we get a CSA on the second interface?
3268          * This needs a lot of work.
3269          */
3270         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3271         u16 ch;
3272         unsigned long flags = 0;
3273
3274         IWL_DEBUG_MAC80211(priv, "enter\n");
3275
3276         if (iwl_is_rfkill(priv))
3277                 goto out_exit;
3278
3279         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3280             test_bit(STATUS_SCANNING, &priv->status))
3281                 goto out_exit;
3282
3283         if (!iwl_is_associated_ctx(ctx))
3284                 goto out_exit;
3285
3286         /* channel switch in progress */
3287         if (priv->switch_rxon.switch_in_progress == true)
3288                 goto out_exit;
3289
3290         mutex_lock(&priv->mutex);
3291         if (priv->cfg->ops->lib->set_channel_switch) {
3292
3293                 ch = channel->hw_value;
3294                 if (le16_to_cpu(ctx->active.channel) != ch) {
3295                         ch_info = iwl_get_channel_info(priv,
3296                                                        channel->band,
3297                                                        ch);
3298                         if (!is_channel_valid(ch_info)) {
3299                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3300                                 goto out;
3301                         }
3302                         spin_lock_irqsave(&priv->lock, flags);
3303
3304                         priv->current_ht_config.smps = conf->smps_mode;
3305
3306                         /* Configure HT40 channels */
3307                         ctx->ht.enabled = conf_is_ht(conf);
3308                         if (ctx->ht.enabled) {
3309                                 if (conf_is_ht40_minus(conf)) {
3310                                         ctx->ht.extension_chan_offset =
3311                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3312                                         ctx->ht.is_40mhz = true;
3313                                 } else if (conf_is_ht40_plus(conf)) {
3314                                         ctx->ht.extension_chan_offset =
3315                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3316                                         ctx->ht.is_40mhz = true;
3317                                 } else {
3318                                         ctx->ht.extension_chan_offset =
3319                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3320                                         ctx->ht.is_40mhz = false;
3321                                 }
3322                         } else
3323                                 ctx->ht.is_40mhz = false;
3324
3325                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3326                                 ctx->staging.flags = 0;
3327
3328                         iwl_set_rxon_channel(priv, channel, ctx);
3329                         iwl_set_rxon_ht(priv, ht_conf);
3330                         iwl_set_flags_for_band(priv, ctx, channel->band,
3331                                                ctx->vif);
3332                         spin_unlock_irqrestore(&priv->lock, flags);
3333
3334                         iwl_set_rate(priv);
3335                         /*
3336                          * at this point, staging_rxon has the
3337                          * configuration for channel switch
3338                          */
3339                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3340                                                                     ch_switch))
3341                                 priv->switch_rxon.switch_in_progress = false;
3342                 }
3343         }
3344 out:
3345         mutex_unlock(&priv->mutex);
3346 out_exit:
3347         if (!priv->switch_rxon.switch_in_progress)
3348                 ieee80211_chswitch_done(ctx->vif, false);
3349         IWL_DEBUG_MAC80211(priv, "leave\n");
3350 }
3351
3352 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3353                              unsigned int changed_flags,
3354                              unsigned int *total_flags,
3355                              u64 multicast)
3356 {
3357         struct iwl_priv *priv = hw->priv;
3358         __le32 filter_or = 0, filter_nand = 0;
3359         struct iwl_rxon_context *ctx;
3360
3361 #define CHK(test, flag) do { \
3362         if (*total_flags & (test))              \
3363                 filter_or |= (flag);            \
3364         else                                    \
3365                 filter_nand |= (flag);          \
3366         } while (0)
3367
3368         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3369                         changed_flags, *total_flags);
3370
3371         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3372         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3373         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3374         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3375
3376 #undef CHK
3377
3378         mutex_lock(&priv->mutex);
3379
3380         for_each_context(priv, ctx) {
3381                 ctx->staging.filter_flags &= ~filter_nand;
3382                 ctx->staging.filter_flags |= filter_or;
3383
3384                 /*
3385                  * Not committing directly because hardware can perform a scan,
3386                  * but we'll eventually commit the filter flags change anyway.
3387                  */
3388         }
3389
3390         mutex_unlock(&priv->mutex);
3391
3392         /*
3393          * Receiving all multicast frames is always enabled by the
3394          * default flags setup in iwl_connection_init_rx_config()
3395          * since we currently do not support programming multicast
3396          * filters into the device.
3397          */
3398         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3399                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3400 }
3401
3402 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3403 {
3404         struct iwl_priv *priv = hw->priv;
3405
3406         mutex_lock(&priv->mutex);
3407         IWL_DEBUG_MAC80211(priv, "enter\n");
3408
3409         /* do not support "flush" */
3410         if (!priv->cfg->ops->lib->txfifo_flush)
3411                 goto done;
3412
3413         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3414                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3415                 goto done;
3416         }
3417         if (iwl_is_rfkill(priv)) {
3418                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3419                 goto done;
3420         }
3421
3422         /*
3423          * mac80211 will not push any more frames for transmit
3424          * until the flush is completed
3425          */
3426         if (drop) {
3427                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3428                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3429                         IWL_ERR(priv, "flush request fail\n");
3430                         goto done;
3431                 }
3432         }
3433         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3434         iwlagn_wait_tx_queue_empty(priv);
3435 done:
3436         mutex_unlock(&priv->mutex);
3437         IWL_DEBUG_MAC80211(priv, "leave\n");
3438 }
3439
3440 static void iwlagn_disable_roc(struct iwl_priv *priv)
3441 {
3442         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3443         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3444
3445         lockdep_assert_held(&priv->mutex);
3446
3447         if (!ctx->is_active)
3448                 return;
3449
3450         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3451         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3452         iwl_set_rxon_channel(priv, chan, ctx);
3453         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3454
3455         priv->_agn.hw_roc_channel = NULL;
3456
3457         iwlcore_commit_rxon(priv, ctx);
3458
3459         ctx->is_active = false;
3460 }
3461
3462 static void iwlagn_bg_roc_done(struct work_struct *work)
3463 {
3464         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3465                                              _agn.hw_roc_work.work);
3466
3467         mutex_lock(&priv->mutex);
3468         ieee80211_remain_on_channel_expired(priv->hw);
3469         iwlagn_disable_roc(priv);
3470         mutex_unlock(&priv->mutex);
3471 }
3472
3473 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3474                                      struct ieee80211_channel *channel,
3475                                      enum nl80211_channel_type channel_type,
3476                                      int duration)
3477 {
3478         struct iwl_priv *priv = hw->priv;
3479         int err = 0;
3480
3481         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3482                 return -EOPNOTSUPP;
3483
3484         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3485                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3486                 return -EOPNOTSUPP;
3487
3488         mutex_lock(&priv->mutex);
3489
3490         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3491             test_bit(STATUS_SCAN_HW, &priv->status)) {
3492                 err = -EBUSY;
3493                 goto out;
3494         }
3495
3496         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3497         priv->_agn.hw_roc_channel = channel;
3498         priv->_agn.hw_roc_chantype = channel_type;
3499         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3500         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3501         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3502                            msecs_to_jiffies(duration + 20));
3503
3504         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3505         ieee80211_ready_on_channel(priv->hw);
3506
3507  out:
3508         mutex_unlock(&priv->mutex);
3509
3510         return err;
3511 }
3512
3513 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3514 {
3515         struct iwl_priv *priv = hw->priv;
3516
3517         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3518                 return -EOPNOTSUPP;
3519
3520         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3521
3522         mutex_lock(&priv->mutex);
3523         iwlagn_disable_roc(priv);
3524         mutex_unlock(&priv->mutex);
3525
3526         return 0;
3527 }
3528
3529 /*****************************************************************************
3530  *
3531  * driver setup and teardown
3532  *
3533  *****************************************************************************/
3534
3535 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3536 {
3537         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3538
3539         init_waitqueue_head(&priv->wait_command_queue);
3540
3541         INIT_WORK(&priv->restart, iwl_bg_restart);
3542         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3543         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3544         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3545         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3546         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3547         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3548         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3549         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3550         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3551
3552         iwl_setup_scan_deferred_work(priv);
3553
3554         if (priv->cfg->ops->lib->setup_deferred_work)
3555                 priv->cfg->ops->lib->setup_deferred_work(priv);
3556
3557         init_timer(&priv->statistics_periodic);
3558         priv->statistics_periodic.data = (unsigned long)priv;
3559         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3560
3561         init_timer(&priv->ucode_trace);
3562         priv->ucode_trace.data = (unsigned long)priv;
3563         priv->ucode_trace.function = iwl_bg_ucode_trace;
3564
3565         init_timer(&priv->watchdog);
3566         priv->watchdog.data = (unsigned long)priv;
3567         priv->watchdog.function = iwl_bg_watchdog;
3568
3569         tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3570                 iwl_irq_tasklet, (unsigned long)priv);
3571 }
3572
3573 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3574 {
3575         if (priv->cfg->ops->lib->cancel_deferred_work)
3576                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3577
3578         cancel_delayed_work_sync(&priv->init_alive_start);
3579         cancel_delayed_work(&priv->alive_start);
3580         cancel_work_sync(&priv->run_time_calib_work);
3581         cancel_work_sync(&priv->beacon_update);
3582
3583         iwl_cancel_scan_deferred_work(priv);
3584
3585         cancel_work_sync(&priv->bt_full_concurrency);
3586         cancel_work_sync(&priv->bt_runtime_config);
3587
3588         del_timer_sync(&priv->statistics_periodic);
3589         del_timer_sync(&priv->ucode_trace);
3590 }
3591
3592 static void iwl_init_hw_rates(struct iwl_priv *priv,
3593                               struct ieee80211_rate *rates)
3594 {
3595         int i;
3596
3597         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3598                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3599                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3600                 rates[i].hw_value_short = i;
3601                 rates[i].flags = 0;
3602                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3603                         /*
3604                          * If CCK != 1M then set short preamble rate flag.
3605                          */
3606                         rates[i].flags |=
3607                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3608                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3609                 }
3610         }
3611 }
3612
3613 static int iwl_init_drv(struct iwl_priv *priv)
3614 {
3615         int ret;
3616
3617         spin_lock_init(&priv->sta_lock);
3618         spin_lock_init(&priv->hcmd_lock);
3619
3620         INIT_LIST_HEAD(&priv->free_frames);
3621
3622         mutex_init(&priv->mutex);
3623         mutex_init(&priv->sync_cmd_mutex);
3624
3625         priv->ieee_channels = NULL;
3626         priv->ieee_rates = NULL;
3627         priv->band = IEEE80211_BAND_2GHZ;
3628
3629         priv->iw_mode = NL80211_IFTYPE_STATION;
3630         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3631         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3632         priv->_agn.agg_tids_count = 0;
3633
3634         /* initialize force reset */
3635         priv->force_reset[IWL_RF_RESET].reset_duration =
3636                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3637         priv->force_reset[IWL_FW_RESET].reset_duration =
3638                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3639
3640         priv->rx_statistics_jiffies = jiffies;
3641
3642         /* Choose which receivers/antennas to use */
3643         if (priv->cfg->ops->hcmd->set_rxon_chain)
3644                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3645                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3646
3647         iwl_init_scan_params(priv);
3648
3649         /* init bt coex */
3650         if (priv->cfg->bt_params &&
3651             priv->cfg->bt_params->advanced_bt_coexist) {
3652                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3653                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3654                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3655                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3656                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3657                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3658         }
3659
3660         /* Set the tx_power_user_lmt to the lowest power level
3661          * this value will get overwritten by channel max power avg
3662          * from eeprom */
3663         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3664         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3665
3666         ret = iwl_init_channel_map(priv);
3667         if (ret) {
3668                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3669                 goto err;
3670         }
3671
3672         ret = iwlcore_init_geos(priv);
3673         if (ret) {
3674                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3675                 goto err_free_channel_map;
3676         }
3677         iwl_init_hw_rates(priv, priv->ieee_rates);
3678
3679         return 0;
3680
3681 err_free_channel_map:
3682         iwl_free_channel_map(priv);
3683 err:
3684         return ret;
3685 }
3686
3687 static void iwl_uninit_drv(struct iwl_priv *priv)
3688 {
3689         iwl_calib_free_results(priv);
3690         iwlcore_free_geos(priv);
3691         iwl_free_channel_map(priv);
3692         kfree(priv->scan_cmd);
3693 }
3694
3695 struct ieee80211_ops iwlagn_hw_ops = {
3696         .tx = iwlagn_mac_tx,
3697         .start = iwlagn_mac_start,
3698         .stop = iwlagn_mac_stop,
3699         .add_interface = iwl_mac_add_interface,
3700         .remove_interface = iwl_mac_remove_interface,
3701         .change_interface = iwl_mac_change_interface,
3702         .config = iwlagn_mac_config,
3703         .configure_filter = iwlagn_configure_filter,
3704         .set_key = iwlagn_mac_set_key,
3705         .update_tkip_key = iwlagn_mac_update_tkip_key,
3706         .conf_tx = iwl_mac_conf_tx,
3707         .bss_info_changed = iwlagn_bss_info_changed,
3708         .ampdu_action = iwlagn_mac_ampdu_action,
3709         .hw_scan = iwl_mac_hw_scan,
3710         .sta_notify = iwlagn_mac_sta_notify,
3711         .sta_add = iwlagn_mac_sta_add,
3712         .sta_remove = iwl_mac_sta_remove,
3713         .channel_switch = iwlagn_mac_channel_switch,
3714         .flush = iwlagn_mac_flush,
3715         .tx_last_beacon = iwl_mac_tx_last_beacon,
3716         .remain_on_channel = iwl_mac_remain_on_channel,
3717         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3718         .offchannel_tx = iwl_mac_offchannel_tx,
3719         .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3720 };
3721
3722 static void iwl_hw_detect(struct iwl_priv *priv)
3723 {
3724         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
3725         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
3726         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
3727         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3728 }
3729
3730 static int iwl_set_hw_params(struct iwl_priv *priv)
3731 {
3732         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3733         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3734         if (priv->cfg->mod_params->amsdu_size_8K)
3735                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3736         else
3737                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3738
3739         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3740
3741         if (priv->cfg->mod_params->disable_11n)
3742                 priv->cfg->sku &= ~IWL_SKU_N;
3743
3744         /* Device-specific setup */
3745         return priv->cfg->ops->lib->set_hw_params(priv);
3746 }
3747
3748 static const u8 iwlagn_bss_ac_to_fifo[] = {
3749         IWL_TX_FIFO_VO,
3750         IWL_TX_FIFO_VI,
3751         IWL_TX_FIFO_BE,
3752         IWL_TX_FIFO_BK,
3753 };
3754
3755 static const u8 iwlagn_bss_ac_to_queue[] = {
3756         0, 1, 2, 3,
3757 };
3758
3759 static const u8 iwlagn_pan_ac_to_fifo[] = {
3760         IWL_TX_FIFO_VO_IPAN,
3761         IWL_TX_FIFO_VI_IPAN,
3762         IWL_TX_FIFO_BE_IPAN,
3763         IWL_TX_FIFO_BK_IPAN,
3764 };
3765
3766 static const u8 iwlagn_pan_ac_to_queue[] = {
3767         7, 6, 5, 4,
3768 };
3769
3770 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3771 {
3772         int err = 0, i;
3773         struct iwl_priv *priv;
3774         struct ieee80211_hw *hw;
3775         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3776         unsigned long flags;
3777         u16 pci_cmd, num_mac;
3778
3779         /************************
3780          * 1. Allocating HW data
3781          ************************/
3782
3783         /* Disabling hardware scan means that mac80211 will perform scans
3784          * "the hard way", rather than using device's scan. */
3785         if (cfg->mod_params->disable_hw_scan) {
3786                 dev_printk(KERN_DEBUG, &(pdev->dev),
3787                         "sw scan support is deprecated\n");
3788                 iwlagn_hw_ops.hw_scan = NULL;
3789         }
3790
3791         hw = iwl_alloc_all(cfg);
3792         if (!hw) {
3793                 err = -ENOMEM;
3794                 goto out;
3795         }
3796         priv = hw->priv;
3797         /* At this point both hw and priv are allocated. */
3798
3799         /*
3800          * The default context is always valid,
3801          * more may be discovered when firmware
3802          * is loaded.
3803          */
3804         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3805
3806         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3807                 priv->contexts[i].ctxid = i;
3808
3809         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3810         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3811         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3812         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3813         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3814         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3815         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3816         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3817         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3818         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3819         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3820                 BIT(NL80211_IFTYPE_ADHOC);
3821         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3822                 BIT(NL80211_IFTYPE_STATION);
3823         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3824         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3825         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3826         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3827
3828         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3829         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3830         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3831         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3832         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3833         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3834         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3835         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3836         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3837         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3838         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3839         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3840                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3841 #ifdef CONFIG_IWL_P2P
3842         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3843                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3844 #endif
3845         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3846         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3847         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3848
3849         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3850
3851         SET_IEEE80211_DEV(hw, &pdev->dev);
3852
3853         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3854         priv->cfg = cfg;
3855         priv->pci_dev = pdev;
3856         priv->inta_mask = CSR_INI_SET_MASK;
3857
3858         /* is antenna coupling more than 35dB ? */
3859         priv->bt_ant_couple_ok =
3860                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3861                 true : false;
3862
3863         /* enable/disable bt channel inhibition */
3864         priv->bt_ch_announce = iwlagn_bt_ch_announce;
3865         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3866                        (priv->bt_ch_announce) ? "On" : "Off");
3867
3868         if (iwl_alloc_traffic_mem(priv))
3869                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3870
3871         /**************************
3872          * 2. Initializing PCI bus
3873          **************************/
3874         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3875                                 PCIE_LINK_STATE_CLKPM);
3876
3877         if (pci_enable_device(pdev)) {
3878                 err = -ENODEV;
3879                 goto out_ieee80211_free_hw;
3880         }
3881
3882         pci_set_master(pdev);
3883
3884         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3885         if (!err)
3886                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3887         if (err) {
3888                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3889                 if (!err)
3890                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3891                 /* both attempts failed: */
3892                 if (err) {
3893                         IWL_WARN(priv, "No suitable DMA available.\n");
3894                         goto out_pci_disable_device;
3895                 }
3896         }
3897
3898         err = pci_request_regions(pdev, DRV_NAME);
3899         if (err)
3900                 goto out_pci_disable_device;
3901
3902         pci_set_drvdata(pdev, priv);
3903
3904
3905         /***********************
3906          * 3. Read REV register
3907          ***********************/
3908         priv->hw_base = pci_iomap(pdev, 0, 0);
3909         if (!priv->hw_base) {
3910                 err = -ENODEV;
3911                 goto out_pci_release_regions;
3912         }
3913
3914         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3915                 (unsigned long long) pci_resource_len(pdev, 0));
3916         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3917
3918         /* these spin locks will be used in apm_ops.init and EEPROM access
3919          * we should init now
3920          */
3921         spin_lock_init(&priv->reg_lock);
3922         spin_lock_init(&priv->lock);
3923
3924         /*
3925          * stop and reset the on-board processor just in case it is in a
3926          * strange state ... like being left stranded by a primary kernel
3927          * and this is now the kdump kernel trying to start up
3928          */
3929         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3930
3931         iwl_hw_detect(priv);
3932         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3933                 priv->cfg->name, priv->hw_rev);
3934
3935         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3936          * PCI Tx retries from interfering with C3 CPU state */
3937         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3938
3939         iwl_prepare_card_hw(priv);
3940         if (!priv->hw_ready) {
3941                 IWL_WARN(priv, "Failed, HW not ready\n");
3942                 goto out_iounmap;
3943         }
3944
3945         /*****************
3946          * 4. Read EEPROM
3947          *****************/
3948         /* Read the EEPROM */
3949         err = iwl_eeprom_init(priv);
3950         if (err) {
3951                 IWL_ERR(priv, "Unable to init EEPROM\n");
3952                 goto out_iounmap;
3953         }
3954         err = iwl_eeprom_check_version(priv);
3955         if (err)
3956                 goto out_free_eeprom;
3957
3958         err = iwl_eeprom_check_sku(priv);
3959         if (err)
3960                 goto out_free_eeprom;
3961
3962         /* extract MAC Address */
3963         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3964         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3965         priv->hw->wiphy->addresses = priv->addresses;
3966         priv->hw->wiphy->n_addresses = 1;
3967         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3968         if (num_mac > 1) {
3969                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3970                        ETH_ALEN);
3971                 priv->addresses[1].addr[5]++;
3972                 priv->hw->wiphy->n_addresses++;
3973         }
3974
3975         /************************
3976          * 5. Setup HW constants
3977          ************************/
3978         if (iwl_set_hw_params(priv)) {
3979                 IWL_ERR(priv, "failed to set hw parameters\n");
3980                 goto out_free_eeprom;
3981         }
3982
3983         /*******************
3984          * 6. Setup priv
3985          *******************/
3986
3987         err = iwl_init_drv(priv);
3988         if (err)
3989                 goto out_free_eeprom;
3990         /* At this point both hw and priv are initialized. */
3991
3992         /********************
3993          * 7. Setup services
3994          ********************/
3995         spin_lock_irqsave(&priv->lock, flags);
3996         iwl_disable_interrupts(priv);
3997         spin_unlock_irqrestore(&priv->lock, flags);
3998
3999         pci_enable_msi(priv->pci_dev);
4000
4001         if (priv->cfg->ops->lib->isr_ops.alloc)
4002                 priv->cfg->ops->lib->isr_ops.alloc(priv);
4003
4004         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4005                           IRQF_SHARED, DRV_NAME, priv);
4006         if (err) {
4007                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4008                 goto out_disable_msi;
4009         }
4010
4011         iwl_setup_deferred_work(priv);
4012         iwl_setup_rx_handlers(priv);
4013
4014         /*********************************************
4015          * 8. Enable interrupts and read RFKILL state
4016          *********************************************/
4017
4018         /* enable rfkill interrupt: hw bug w/a */
4019         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4020         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4021                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4022                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4023         }
4024
4025         iwl_enable_rfkill_int(priv);
4026
4027         /* If platform's RF_KILL switch is NOT set to KILL */
4028         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4029                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4030         else
4031                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4032
4033         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4034                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4035
4036         iwl_power_initialize(priv);
4037         iwl_tt_initialize(priv);
4038
4039         init_completion(&priv->_agn.firmware_loading_complete);
4040
4041         err = iwl_request_firmware(priv, true);
4042         if (err)
4043                 goto out_destroy_workqueue;
4044
4045         return 0;
4046
4047  out_destroy_workqueue:
4048         destroy_workqueue(priv->workqueue);
4049         priv->workqueue = NULL;
4050         free_irq(priv->pci_dev->irq, priv);
4051         if (priv->cfg->ops->lib->isr_ops.free)
4052                 priv->cfg->ops->lib->isr_ops.free(priv);
4053  out_disable_msi:
4054         pci_disable_msi(priv->pci_dev);
4055         iwl_uninit_drv(priv);
4056  out_free_eeprom:
4057         iwl_eeprom_free(priv);
4058  out_iounmap:
4059         pci_iounmap(pdev, priv->hw_base);
4060  out_pci_release_regions:
4061         pci_set_drvdata(pdev, NULL);
4062         pci_release_regions(pdev);
4063  out_pci_disable_device:
4064         pci_disable_device(pdev);
4065  out_ieee80211_free_hw:
4066         iwl_free_traffic_mem(priv);
4067         ieee80211_free_hw(priv->hw);
4068  out:
4069         return err;
4070 }
4071
4072 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4073 {
4074         struct iwl_priv *priv = pci_get_drvdata(pdev);
4075         unsigned long flags;
4076
4077         if (!priv)
4078                 return;
4079
4080         wait_for_completion(&priv->_agn.firmware_loading_complete);
4081
4082         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4083
4084         iwl_dbgfs_unregister(priv);
4085         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4086
4087         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4088          * to be called and iwl_down since we are removing the device
4089          * we need to set STATUS_EXIT_PENDING bit.
4090          */
4091         set_bit(STATUS_EXIT_PENDING, &priv->status);
4092
4093         iwl_leds_exit(priv);
4094
4095         if (priv->mac80211_registered) {
4096                 ieee80211_unregister_hw(priv->hw);
4097                 priv->mac80211_registered = 0;
4098         } else {
4099                 iwl_down(priv);
4100         }
4101
4102         /*
4103          * Make sure device is reset to low power before unloading driver.
4104          * This may be redundant with iwl_down(), but there are paths to
4105          * run iwl_down() without calling apm_ops.stop(), and there are
4106          * paths to avoid running iwl_down() at all before leaving driver.
4107          * This (inexpensive) call *makes sure* device is reset.
4108          */
4109         iwl_apm_stop(priv);
4110
4111         iwl_tt_exit(priv);
4112
4113         /* make sure we flush any pending irq or
4114          * tasklet for the driver
4115          */
4116         spin_lock_irqsave(&priv->lock, flags);
4117         iwl_disable_interrupts(priv);
4118         spin_unlock_irqrestore(&priv->lock, flags);
4119
4120         iwl_synchronize_irq(priv);
4121
4122         iwl_dealloc_ucode_pci(priv);
4123
4124         if (priv->rxq.bd)
4125                 iwlagn_rx_queue_free(priv, &priv->rxq);
4126         iwlagn_hw_txq_ctx_free(priv);
4127
4128         iwl_eeprom_free(priv);
4129
4130
4131         /*netif_stop_queue(dev); */
4132         flush_workqueue(priv->workqueue);
4133
4134         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4135          * priv->workqueue... so we can't take down the workqueue
4136          * until now... */
4137         destroy_workqueue(priv->workqueue);
4138         priv->workqueue = NULL;
4139         iwl_free_traffic_mem(priv);
4140
4141         free_irq(priv->pci_dev->irq, priv);
4142         pci_disable_msi(priv->pci_dev);
4143         pci_iounmap(pdev, priv->hw_base);
4144         pci_release_regions(pdev);
4145         pci_disable_device(pdev);
4146         pci_set_drvdata(pdev, NULL);
4147
4148         iwl_uninit_drv(priv);
4149
4150         if (priv->cfg->ops->lib->isr_ops.free)
4151                 priv->cfg->ops->lib->isr_ops.free(priv);
4152
4153         dev_kfree_skb(priv->beacon_skb);
4154
4155         ieee80211_free_hw(priv->hw);
4156 }
4157
4158
4159 /*****************************************************************************
4160  *
4161  * driver and module entry point
4162  *
4163  *****************************************************************************/
4164
4165 /* Hardware specific file defines the PCI IDs table for that hardware module */
4166 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4167         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4168         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4169         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4170         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4171         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4172         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4173         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4174         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4175         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4176         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4177         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4178         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4179         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4180         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4181         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4182         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4183         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4184         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4185         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4186         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4187         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4188         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4189         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4190         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4191
4192 /* 5300 Series WiFi */
4193         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4194         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4195         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4196         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4197         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4198         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4199         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4200         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4201         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4202         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4203         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4204         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4205
4206 /* 5350 Series WiFi/WiMax */
4207         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4208         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4209         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4210
4211 /* 5150 Series Wifi/WiMax */
4212         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4213         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4214         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4215         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4216         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4217         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4218
4219         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4220         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4221         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4222         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4223
4224 /* 6x00 Series */
4225         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4226         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4227         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4228         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4229         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4230         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4231         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4232         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4233         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4234         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4235
4236 /* 6x05 Series */
4237         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4238         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4239         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4240         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4241         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4242         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4243         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4244
4245 /* 6x30 Series */
4246         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4247         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4248         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4249         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4250         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4251         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4252         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4253         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4254         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4255         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4256         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4257         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4258         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4259         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4260         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4261         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4262
4263 /* 6x50 WiFi/WiMax Series */
4264         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4265         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4266         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4267         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4268         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4269         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4270
4271 /* 6150 WiFi/WiMax Series */
4272         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4273         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4274         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4275         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4276         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4277         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4278
4279 /* 1000 Series WiFi */
4280         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4281         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4282         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4283         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4284         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4285         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4286         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4287         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4288         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4289         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4290         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4291         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4292
4293 /* 100 Series WiFi */
4294         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4295         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4296         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4297         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4298         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4299         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4300
4301 /* 130 Series WiFi */
4302         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4303         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4304         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4305         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4306         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4307         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4308
4309 /* 2x00 Series */
4310         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4311         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4312         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4313         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4314         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4315         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4316
4317 /* 2x30 Series */
4318         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4319         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4320         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4321         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4322         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4323         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4324
4325 /* 6x35 Series */
4326         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4327         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4328         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4329         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4330         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4331         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4332         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4333         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4334         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4335
4336 /* 200 Series */
4337         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4338         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4339         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4340         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4341         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4342         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4343
4344 /* 230 Series */
4345         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4346         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4347         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4348         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4349         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4350         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4351
4352         {0}
4353 };
4354 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4355
4356 static struct pci_driver iwl_driver = {
4357         .name = DRV_NAME,
4358         .id_table = iwl_hw_card_ids,
4359         .probe = iwl_pci_probe,
4360         .remove = __devexit_p(iwl_pci_remove),
4361         .driver.pm = IWL_PM_OPS,
4362 };
4363
4364 static int __init iwl_init(void)
4365 {
4366
4367         int ret;
4368         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4369         pr_info(DRV_COPYRIGHT "\n");
4370
4371         ret = iwlagn_rate_control_register();
4372         if (ret) {
4373                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4374                 return ret;
4375         }
4376
4377         ret = pci_register_driver(&iwl_driver);
4378         if (ret) {
4379                 pr_err("Unable to initialize PCI module\n");
4380                 goto error_register;
4381         }
4382
4383         return ret;
4384
4385 error_register:
4386         iwlagn_rate_control_unregister();
4387         return ret;
4388 }
4389
4390 static void __exit iwl_exit(void)
4391 {
4392         pci_unregister_driver(&iwl_driver);
4393         iwlagn_rate_control_unregister();
4394 }
4395
4396 module_exit(iwl_exit);
4397 module_init(iwl_init);
4398
4399 #ifdef CONFIG_IWLWIFI_DEBUG
4400 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4401 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4402 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4403 MODULE_PARM_DESC(debug, "debug output mask");
4404 #endif
4405
4406 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4407 MODULE_PARM_DESC(swcrypto50,
4408                  "using crypto in software (default 0 [hardware]) (deprecated)");
4409 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4410 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4411 module_param_named(queues_num50,
4412                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4413 MODULE_PARM_DESC(queues_num50,
4414                  "number of hw queues in 50xx series (deprecated)");
4415 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4416 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4417 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4418 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4419 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4420 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4421 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4422                    int, S_IRUGO);
4423 MODULE_PARM_DESC(amsdu_size_8K50,
4424                  "enable 8K amsdu size in 50XX series (deprecated)");
4425 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4426                    int, S_IRUGO);
4427 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4428 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4429 MODULE_PARM_DESC(fw_restart50,
4430                  "restart firmware in case of error (deprecated)");
4431 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4432 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4433 module_param_named(
4434         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4435 MODULE_PARM_DESC(disable_hw_scan,
4436                  "disable hardware scanning (default 0) (deprecated)");
4437
4438 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4439                    S_IRUGO);
4440 MODULE_PARM_DESC(ucode_alternative,
4441                  "specify ucode alternative to use from ucode file");
4442
4443 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4444 MODULE_PARM_DESC(antenna_coupling,
4445                  "specify antenna coupling in dB (defualt: 0 dB)");
4446
4447 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4448 MODULE_PARM_DESC(bt_ch_inhibition,
4449                  "Disable BT channel inhibition (default: enable)");
4450
4451 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4452 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4453
4454 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4455 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");