iwlagn: use huge command for beacon
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project, as well
6  * as portions of the ieee80211 subsystem header files.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of version 2 of the GNU General Public License as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20  *
21  * The full GNU General Public License is included in this distribution in the
22  * file called LICENSE.
23  *
24  * Contact Information:
25  *  Intel Linux Wireless <ilw@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
47
48 #include <net/mac80211.h>
49
50 #include <asm/div64.h>
51
52 #define DRV_NAME        "iwlagn"
53
54 #include "iwl-eeprom.h"
55 #include "iwl-dev.h"
56 #include "iwl-core.h"
57 #include "iwl-io.h"
58 #include "iwl-helpers.h"
59 #include "iwl-sta.h"
60 #include "iwl-agn-calib.h"
61 #include "iwl-agn.h"
62
63
64 /******************************************************************************
65  *
66  * module boiler plate
67  *
68  ******************************************************************************/
69
70 /*
71  * module name, copyright, version, etc.
72  */
73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
74
75 #ifdef CONFIG_IWLWIFI_DEBUG
76 #define VD "d"
77 #else
78 #define VD
79 #endif
80
81 #define DRV_VERSION     IWLWIFI_VERSION VD
82
83
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88
89 static int iwlagn_ant_coupling;
90 static bool iwlagn_bt_ch_announce = 1;
91
92 void iwl_update_chain_flags(struct iwl_priv *priv)
93 {
94         struct iwl_rxon_context *ctx;
95
96         if (priv->cfg->ops->hcmd->set_rxon_chain) {
97                 for_each_context(priv, ctx) {
98                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
99                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
100                                 iwlcore_commit_rxon(priv, ctx);
101                 }
102         }
103 }
104
105 static void iwl_clear_free_frames(struct iwl_priv *priv)
106 {
107         struct list_head *element;
108
109         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
110                        priv->frames_count);
111
112         while (!list_empty(&priv->free_frames)) {
113                 element = priv->free_frames.next;
114                 list_del(element);
115                 kfree(list_entry(element, struct iwl_frame, list));
116                 priv->frames_count--;
117         }
118
119         if (priv->frames_count) {
120                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
121                             priv->frames_count);
122                 priv->frames_count = 0;
123         }
124 }
125
126 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
127 {
128         struct iwl_frame *frame;
129         struct list_head *element;
130         if (list_empty(&priv->free_frames)) {
131                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
132                 if (!frame) {
133                         IWL_ERR(priv, "Could not allocate frame!\n");
134                         return NULL;
135                 }
136
137                 priv->frames_count++;
138                 return frame;
139         }
140
141         element = priv->free_frames.next;
142         list_del(element);
143         return list_entry(element, struct iwl_frame, list);
144 }
145
146 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
147 {
148         memset(frame, 0, sizeof(*frame));
149         list_add(&frame->list, &priv->free_frames);
150 }
151
152 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
153                                  struct ieee80211_hdr *hdr,
154                                  int left)
155 {
156         lockdep_assert_held(&priv->mutex);
157
158         if (!priv->beacon_skb)
159                 return 0;
160
161         if (priv->beacon_skb->len > left)
162                 return 0;
163
164         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
165
166         return priv->beacon_skb->len;
167 }
168
169 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
170 static void iwl_set_beacon_tim(struct iwl_priv *priv,
171                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
172                                u8 *beacon, u32 frame_size)
173 {
174         u16 tim_idx;
175         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
176
177         /*
178          * The index is relative to frame start but we start looking at the
179          * variable-length part of the beacon.
180          */
181         tim_idx = mgmt->u.beacon.variable - beacon;
182
183         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
184         while ((tim_idx < (frame_size - 2)) &&
185                         (beacon[tim_idx] != WLAN_EID_TIM))
186                 tim_idx += beacon[tim_idx+1] + 2;
187
188         /* If TIM field was found, set variables */
189         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
190                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
191                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
192         } else
193                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
194 }
195
196 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
197                                        struct iwl_frame *frame)
198 {
199         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
200         u32 frame_size;
201         u32 rate_flags;
202         u32 rate;
203         /*
204          * We have to set up the TX command, the TX Beacon command, and the
205          * beacon contents.
206          */
207
208         lockdep_assert_held(&priv->mutex);
209
210         if (!priv->beacon_ctx) {
211                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
212                 return 0;
213         }
214
215         /* Initialize memory */
216         tx_beacon_cmd = &frame->u.beacon;
217         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
218
219         /* Set up TX beacon contents */
220         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
221                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
222         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
223                 return 0;
224         if (!frame_size)
225                 return 0;
226
227         /* Set up TX command fields */
228         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
229         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
230         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
231         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
232                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
233
234         /* Set up TX beacon command fields */
235         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
236                            frame_size);
237
238         /* Set up packet rate and flags */
239         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
240         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
241                                               priv->hw_params.valid_tx_ant);
242         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
243         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
244                 rate_flags |= RATE_MCS_CCK_MSK;
245         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
246                         rate_flags);
247
248         return sizeof(*tx_beacon_cmd) + frame_size;
249 }
250
251 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
252 {
253         struct iwl_frame *frame;
254         unsigned int frame_size;
255         int rc;
256         struct iwl_host_cmd cmd = {
257                 .id = REPLY_TX_BEACON,
258                 .flags = CMD_SIZE_HUGE,
259         };
260
261         frame = iwl_get_free_frame(priv);
262         if (!frame) {
263                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
264                           "command.\n");
265                 return -ENOMEM;
266         }
267
268         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
269         if (!frame_size) {
270                 IWL_ERR(priv, "Error configuring the beacon command\n");
271                 iwl_free_frame(priv, frame);
272                 return -EINVAL;
273         }
274
275         cmd.len = frame_size;
276         cmd.data = &frame->u.cmd[0];
277
278         rc = iwl_send_cmd_sync(priv, &cmd);
279
280         iwl_free_frame(priv, frame);
281
282         return rc;
283 }
284
285 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
286 {
287         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
288
289         dma_addr_t addr = get_unaligned_le32(&tb->lo);
290         if (sizeof(dma_addr_t) > sizeof(u32))
291                 addr |=
292                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
293
294         return addr;
295 }
296
297 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
298 {
299         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
300
301         return le16_to_cpu(tb->hi_n_len) >> 4;
302 }
303
304 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
305                                   dma_addr_t addr, u16 len)
306 {
307         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
308         u16 hi_n_len = len << 4;
309
310         put_unaligned_le32(addr, &tb->lo);
311         if (sizeof(dma_addr_t) > sizeof(u32))
312                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
313
314         tb->hi_n_len = cpu_to_le16(hi_n_len);
315
316         tfd->num_tbs = idx + 1;
317 }
318
319 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
320 {
321         return tfd->num_tbs & 0x1f;
322 }
323
324 /**
325  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
326  * @priv - driver private data
327  * @txq - tx queue
328  *
329  * Does NOT advance any TFD circular buffer read/write indexes
330  * Does NOT free the TFD itself (which is within circular buffer)
331  */
332 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
333 {
334         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
335         struct iwl_tfd *tfd;
336         struct pci_dev *dev = priv->pci_dev;
337         int index = txq->q.read_ptr;
338         int i;
339         int num_tbs;
340
341         tfd = &tfd_tmp[index];
342
343         /* Sanity check on number of chunks */
344         num_tbs = iwl_tfd_get_num_tbs(tfd);
345
346         if (num_tbs >= IWL_NUM_OF_TBS) {
347                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
348                 /* @todo issue fatal error, it is quite serious situation */
349                 return;
350         }
351
352         /* Unmap tx_cmd */
353         if (num_tbs)
354                 pci_unmap_single(dev,
355                                 dma_unmap_addr(&txq->meta[index], mapping),
356                                 dma_unmap_len(&txq->meta[index], len),
357                                 PCI_DMA_BIDIRECTIONAL);
358
359         /* Unmap chunks, if any. */
360         for (i = 1; i < num_tbs; i++)
361                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
362                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
363
364         /* free SKB */
365         if (txq->txb) {
366                 struct sk_buff *skb;
367
368                 skb = txq->txb[txq->q.read_ptr].skb;
369
370                 /* can be called from irqs-disabled context */
371                 if (skb) {
372                         dev_kfree_skb_any(skb);
373                         txq->txb[txq->q.read_ptr].skb = NULL;
374                 }
375         }
376 }
377
378 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
379                                  struct iwl_tx_queue *txq,
380                                  dma_addr_t addr, u16 len,
381                                  u8 reset, u8 pad)
382 {
383         struct iwl_queue *q;
384         struct iwl_tfd *tfd, *tfd_tmp;
385         u32 num_tbs;
386
387         q = &txq->q;
388         tfd_tmp = (struct iwl_tfd *)txq->tfds;
389         tfd = &tfd_tmp[q->write_ptr];
390
391         if (reset)
392                 memset(tfd, 0, sizeof(*tfd));
393
394         num_tbs = iwl_tfd_get_num_tbs(tfd);
395
396         /* Each TFD can point to a maximum 20 Tx buffers */
397         if (num_tbs >= IWL_NUM_OF_TBS) {
398                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
399                           IWL_NUM_OF_TBS);
400                 return -EINVAL;
401         }
402
403         if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
404                 return -EINVAL;
405
406         if (unlikely(addr & ~IWL_TX_DMA_MASK))
407                 IWL_ERR(priv, "Unaligned address = %llx\n",
408                           (unsigned long long)addr);
409
410         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
411
412         return 0;
413 }
414
415 /*
416  * Tell nic where to find circular buffer of Tx Frame Descriptors for
417  * given Tx queue, and enable the DMA channel used for that queue.
418  *
419  * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
420  * channels supported in hardware.
421  */
422 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
423                          struct iwl_tx_queue *txq)
424 {
425         int txq_id = txq->q.id;
426
427         /* Circular buffer (TFD queue in DRAM) physical base address */
428         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
429                              txq->q.dma_addr >> 8);
430
431         return 0;
432 }
433
434 static void iwl_bg_beacon_update(struct work_struct *work)
435 {
436         struct iwl_priv *priv =
437                 container_of(work, struct iwl_priv, beacon_update);
438         struct sk_buff *beacon;
439
440         mutex_lock(&priv->mutex);
441         if (!priv->beacon_ctx) {
442                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
443                 goto out;
444         }
445
446         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
447                 /*
448                  * The ucode will send beacon notifications even in
449                  * IBSS mode, but we don't want to process them. But
450                  * we need to defer the type check to here due to
451                  * requiring locking around the beacon_ctx access.
452                  */
453                 goto out;
454         }
455
456         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
457         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
458         if (!beacon) {
459                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
460                 goto out;
461         }
462
463         /* new beacon skb is allocated every time; dispose previous.*/
464         dev_kfree_skb(priv->beacon_skb);
465
466         priv->beacon_skb = beacon;
467
468         iwlagn_send_beacon_cmd(priv);
469  out:
470         mutex_unlock(&priv->mutex);
471 }
472
473 static void iwl_bg_bt_runtime_config(struct work_struct *work)
474 {
475         struct iwl_priv *priv =
476                 container_of(work, struct iwl_priv, bt_runtime_config);
477
478         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
479                 return;
480
481         /* dont send host command if rf-kill is on */
482         if (!iwl_is_ready_rf(priv))
483                 return;
484         priv->cfg->ops->hcmd->send_bt_config(priv);
485 }
486
487 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
488 {
489         struct iwl_priv *priv =
490                 container_of(work, struct iwl_priv, bt_full_concurrency);
491         struct iwl_rxon_context *ctx;
492
493         mutex_lock(&priv->mutex);
494
495         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
496                 goto out;
497
498         /* dont send host command if rf-kill is on */
499         if (!iwl_is_ready_rf(priv))
500                 goto out;
501
502         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
503                        priv->bt_full_concurrent ?
504                        "full concurrency" : "3-wire");
505
506         /*
507          * LQ & RXON updated cmds must be sent before BT Config cmd
508          * to avoid 3-wire collisions
509          */
510         for_each_context(priv, ctx) {
511                 if (priv->cfg->ops->hcmd->set_rxon_chain)
512                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
513                 iwlcore_commit_rxon(priv, ctx);
514         }
515
516         priv->cfg->ops->hcmd->send_bt_config(priv);
517 out:
518         mutex_unlock(&priv->mutex);
519 }
520
521 /**
522  * iwl_bg_statistics_periodic - Timer callback to queue statistics
523  *
524  * This callback is provided in order to send a statistics request.
525  *
526  * This timer function is continually reset to execute within
527  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
528  * was received.  We need to ensure we receive the statistics in order
529  * to update the temperature used for calibrating the TXPOWER.
530  */
531 static void iwl_bg_statistics_periodic(unsigned long data)
532 {
533         struct iwl_priv *priv = (struct iwl_priv *)data;
534
535         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
536                 return;
537
538         /* dont send host command if rf-kill is on */
539         if (!iwl_is_ready_rf(priv))
540                 return;
541
542         iwl_send_statistics_request(priv, CMD_ASYNC, false);
543 }
544
545
546 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
547                                         u32 start_idx, u32 num_events,
548                                         u32 mode)
549 {
550         u32 i;
551         u32 ptr;        /* SRAM byte address of log data */
552         u32 ev, time, data; /* event log data */
553         unsigned long reg_flags;
554
555         if (mode == 0)
556                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
557         else
558                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
559
560         /* Make sure device is powered up for SRAM reads */
561         spin_lock_irqsave(&priv->reg_lock, reg_flags);
562         if (iwl_grab_nic_access(priv)) {
563                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
564                 return;
565         }
566
567         /* Set starting address; reads will auto-increment */
568         iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
569         rmb();
570
571         /*
572          * "time" is actually "data" for mode 0 (no timestamp).
573          * place event id # at far right for easier visual parsing.
574          */
575         for (i = 0; i < num_events; i++) {
576                 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
577                 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
578                 if (mode == 0) {
579                         trace_iwlwifi_dev_ucode_cont_event(priv,
580                                                         0, time, ev);
581                 } else {
582                         data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
583                         trace_iwlwifi_dev_ucode_cont_event(priv,
584                                                 time, data, ev);
585                 }
586         }
587         /* Allow device to power down */
588         iwl_release_nic_access(priv);
589         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
590 }
591
592 static void iwl_continuous_event_trace(struct iwl_priv *priv)
593 {
594         u32 capacity;   /* event log capacity in # entries */
595         u32 base;       /* SRAM byte address of event log header */
596         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
597         u32 num_wraps;  /* # times uCode wrapped to top of log */
598         u32 next_entry; /* index of next entry to be written by uCode */
599
600         base = priv->device_pointers.error_event_table;
601         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
602                 capacity = iwl_read_targ_mem(priv, base);
603                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
604                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
605                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
606         } else
607                 return;
608
609         if (num_wraps == priv->event_log.num_wraps) {
610                 iwl_print_cont_event_trace(priv,
611                                        base, priv->event_log.next_entry,
612                                        next_entry - priv->event_log.next_entry,
613                                        mode);
614                 priv->event_log.non_wraps_count++;
615         } else {
616                 if ((num_wraps - priv->event_log.num_wraps) > 1)
617                         priv->event_log.wraps_more_count++;
618                 else
619                         priv->event_log.wraps_once_count++;
620                 trace_iwlwifi_dev_ucode_wrap_event(priv,
621                                 num_wraps - priv->event_log.num_wraps,
622                                 next_entry, priv->event_log.next_entry);
623                 if (next_entry < priv->event_log.next_entry) {
624                         iwl_print_cont_event_trace(priv, base,
625                                priv->event_log.next_entry,
626                                capacity - priv->event_log.next_entry,
627                                mode);
628
629                         iwl_print_cont_event_trace(priv, base, 0,
630                                 next_entry, mode);
631                 } else {
632                         iwl_print_cont_event_trace(priv, base,
633                                next_entry, capacity - next_entry,
634                                mode);
635
636                         iwl_print_cont_event_trace(priv, base, 0,
637                                 next_entry, mode);
638                 }
639         }
640         priv->event_log.num_wraps = num_wraps;
641         priv->event_log.next_entry = next_entry;
642 }
643
644 /**
645  * iwl_bg_ucode_trace - Timer callback to log ucode event
646  *
647  * The timer is continually set to execute every
648  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
649  * this function is to perform continuous uCode event logging operation
650  * if enabled
651  */
652 static void iwl_bg_ucode_trace(unsigned long data)
653 {
654         struct iwl_priv *priv = (struct iwl_priv *)data;
655
656         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
657                 return;
658
659         if (priv->event_log.ucode_trace) {
660                 iwl_continuous_event_trace(priv);
661                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
662                 mod_timer(&priv->ucode_trace,
663                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
664         }
665 }
666
667 static void iwl_bg_tx_flush(struct work_struct *work)
668 {
669         struct iwl_priv *priv =
670                 container_of(work, struct iwl_priv, tx_flush);
671
672         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
673                 return;
674
675         /* do nothing if rf-kill is on */
676         if (!iwl_is_ready_rf(priv))
677                 return;
678
679         if (priv->cfg->ops->lib->txfifo_flush) {
680                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
681                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
682         }
683 }
684
685 /**
686  * iwl_rx_handle - Main entry function for receiving responses from uCode
687  *
688  * Uses the priv->rx_handlers callback function array to invoke
689  * the appropriate handlers, including command responses,
690  * frame-received notifications, and other notifications.
691  */
692 static void iwl_rx_handle(struct iwl_priv *priv)
693 {
694         struct iwl_rx_mem_buffer *rxb;
695         struct iwl_rx_packet *pkt;
696         struct iwl_rx_queue *rxq = &priv->rxq;
697         u32 r, i;
698         int reclaim;
699         unsigned long flags;
700         u8 fill_rx = 0;
701         u32 count = 8;
702         int total_empty;
703
704         /* uCode's read index (stored in shared DRAM) indicates the last Rx
705          * buffer that the driver may process (last buffer filled by ucode). */
706         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
707         i = rxq->read;
708
709         /* Rx interrupt, but nothing sent from uCode */
710         if (i == r)
711                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
712
713         /* calculate total frames need to be restock after handling RX */
714         total_empty = r - rxq->write_actual;
715         if (total_empty < 0)
716                 total_empty += RX_QUEUE_SIZE;
717
718         if (total_empty > (RX_QUEUE_SIZE / 2))
719                 fill_rx = 1;
720
721         while (i != r) {
722                 int len;
723
724                 rxb = rxq->queue[i];
725
726                 /* If an RXB doesn't have a Rx queue slot associated with it,
727                  * then a bug has been introduced in the queue refilling
728                  * routines -- catch it here */
729                 if (WARN_ON(rxb == NULL)) {
730                         i = (i + 1) & RX_QUEUE_MASK;
731                         continue;
732                 }
733
734                 rxq->queue[i] = NULL;
735
736                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
737                                PAGE_SIZE << priv->hw_params.rx_page_order,
738                                PCI_DMA_FROMDEVICE);
739                 pkt = rxb_addr(rxb);
740
741                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
742                 len += sizeof(u32); /* account for status word */
743                 trace_iwlwifi_dev_rx(priv, pkt, len);
744
745                 /* Reclaim a command buffer only if this packet is a response
746                  *   to a (driver-originated) command.
747                  * If the packet (e.g. Rx frame) originated from uCode,
748                  *   there is no command buffer to reclaim.
749                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
750                  *   but apparently a few don't get set; catch them here. */
751                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
752                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
753                         (pkt->hdr.cmd != REPLY_RX) &&
754                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
755                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
756                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
757                         (pkt->hdr.cmd != REPLY_TX);
758
759                 /*
760                  * Do the notification wait before RX handlers so
761                  * even if the RX handler consumes the RXB we have
762                  * access to it in the notification wait entry.
763                  */
764                 if (!list_empty(&priv->_agn.notif_waits)) {
765                         struct iwl_notification_wait *w;
766
767                         spin_lock(&priv->_agn.notif_wait_lock);
768                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
769                                 if (w->cmd == pkt->hdr.cmd) {
770                                         w->triggered = true;
771                                         if (w->fn)
772                                                 w->fn(priv, pkt);
773                                 }
774                         }
775                         spin_unlock(&priv->_agn.notif_wait_lock);
776
777                         wake_up_all(&priv->_agn.notif_waitq);
778                 }
779
780                 /* Based on type of command response or notification,
781                  *   handle those that need handling via function in
782                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
783                 if (priv->rx_handlers[pkt->hdr.cmd]) {
784                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
785                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
786                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
787                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
788                 } else {
789                         /* No handling needed */
790                         IWL_DEBUG_RX(priv,
791                                 "r %d i %d No handler needed for %s, 0x%02x\n",
792                                 r, i, get_cmd_string(pkt->hdr.cmd),
793                                 pkt->hdr.cmd);
794                 }
795
796                 /*
797                  * XXX: After here, we should always check rxb->page
798                  * against NULL before touching it or its virtual
799                  * memory (pkt). Because some rx_handler might have
800                  * already taken or freed the pages.
801                  */
802
803                 if (reclaim) {
804                         /* Invoke any callbacks, transfer the buffer to caller,
805                          * and fire off the (possibly) blocking iwl_send_cmd()
806                          * as we reclaim the driver command queue */
807                         if (rxb->page)
808                                 iwl_tx_cmd_complete(priv, rxb);
809                         else
810                                 IWL_WARN(priv, "Claim null rxb?\n");
811                 }
812
813                 /* Reuse the page if possible. For notification packets and
814                  * SKBs that fail to Rx correctly, add them back into the
815                  * rx_free list for reuse later. */
816                 spin_lock_irqsave(&rxq->lock, flags);
817                 if (rxb->page != NULL) {
818                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
819                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
820                                 PCI_DMA_FROMDEVICE);
821                         list_add_tail(&rxb->list, &rxq->rx_free);
822                         rxq->free_count++;
823                 } else
824                         list_add_tail(&rxb->list, &rxq->rx_used);
825
826                 spin_unlock_irqrestore(&rxq->lock, flags);
827
828                 i = (i + 1) & RX_QUEUE_MASK;
829                 /* If there are a lot of unused frames,
830                  * restock the Rx queue so ucode wont assert. */
831                 if (fill_rx) {
832                         count++;
833                         if (count >= 8) {
834                                 rxq->read = i;
835                                 iwlagn_rx_replenish_now(priv);
836                                 count = 0;
837                         }
838                 }
839         }
840
841         /* Backtrack one entry */
842         rxq->read = i;
843         if (fill_rx)
844                 iwlagn_rx_replenish_now(priv);
845         else
846                 iwlagn_rx_queue_restock(priv);
847 }
848
849 /* call this function to flush any scheduled tasklet */
850 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
851 {
852         /* wait to make sure we flush pending tasklet*/
853         synchronize_irq(priv->pci_dev->irq);
854         tasklet_kill(&priv->irq_tasklet);
855 }
856
857 /* tasklet for iwlagn interrupt */
858 static void iwl_irq_tasklet(struct iwl_priv *priv)
859 {
860         u32 inta = 0;
861         u32 handled = 0;
862         unsigned long flags;
863         u32 i;
864 #ifdef CONFIG_IWLWIFI_DEBUG
865         u32 inta_mask;
866 #endif
867
868         spin_lock_irqsave(&priv->lock, flags);
869
870         /* Ack/clear/reset pending uCode interrupts.
871          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
872          */
873         /* There is a hardware bug in the interrupt mask function that some
874          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
875          * they are disabled in the CSR_INT_MASK register. Furthermore the
876          * ICT interrupt handling mechanism has another bug that might cause
877          * these unmasked interrupts fail to be detected. We workaround the
878          * hardware bugs here by ACKing all the possible interrupts so that
879          * interrupt coalescing can still be achieved.
880          */
881         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
882
883         inta = priv->_agn.inta;
884
885 #ifdef CONFIG_IWLWIFI_DEBUG
886         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
887                 /* just for debug */
888                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
889                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
890                                 inta, inta_mask);
891         }
892 #endif
893
894         spin_unlock_irqrestore(&priv->lock, flags);
895
896         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
897         priv->_agn.inta = 0;
898
899         /* Now service all interrupt bits discovered above. */
900         if (inta & CSR_INT_BIT_HW_ERR) {
901                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
902
903                 /* Tell the device to stop sending interrupts */
904                 iwl_disable_interrupts(priv);
905
906                 priv->isr_stats.hw++;
907                 iwl_irq_handle_error(priv);
908
909                 handled |= CSR_INT_BIT_HW_ERR;
910
911                 return;
912         }
913
914 #ifdef CONFIG_IWLWIFI_DEBUG
915         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
916                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
917                 if (inta & CSR_INT_BIT_SCD) {
918                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
919                                       "the frame/frames.\n");
920                         priv->isr_stats.sch++;
921                 }
922
923                 /* Alive notification via Rx interrupt will do the real work */
924                 if (inta & CSR_INT_BIT_ALIVE) {
925                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
926                         priv->isr_stats.alive++;
927                 }
928         }
929 #endif
930         /* Safely ignore these bits for debug checks below */
931         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
932
933         /* HW RF KILL switch toggled */
934         if (inta & CSR_INT_BIT_RF_KILL) {
935                 int hw_rf_kill = 0;
936                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
937                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
938                         hw_rf_kill = 1;
939
940                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
941                                 hw_rf_kill ? "disable radio" : "enable radio");
942
943                 priv->isr_stats.rfkill++;
944
945                 /* driver only loads ucode once setting the interface up.
946                  * the driver allows loading the ucode even if the radio
947                  * is killed. Hence update the killswitch state here. The
948                  * rfkill handler will care about restarting if needed.
949                  */
950                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
951                         if (hw_rf_kill)
952                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
953                         else
954                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
955                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
956                 }
957
958                 handled |= CSR_INT_BIT_RF_KILL;
959         }
960
961         /* Chip got too hot and stopped itself */
962         if (inta & CSR_INT_BIT_CT_KILL) {
963                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
964                 priv->isr_stats.ctkill++;
965                 handled |= CSR_INT_BIT_CT_KILL;
966         }
967
968         /* Error detected by uCode */
969         if (inta & CSR_INT_BIT_SW_ERR) {
970                 IWL_ERR(priv, "Microcode SW error detected. "
971                         " Restarting 0x%X.\n", inta);
972                 priv->isr_stats.sw++;
973                 iwl_irq_handle_error(priv);
974                 handled |= CSR_INT_BIT_SW_ERR;
975         }
976
977         /* uCode wakes up after power-down sleep */
978         if (inta & CSR_INT_BIT_WAKEUP) {
979                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
980                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
981                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
982                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
983
984                 priv->isr_stats.wakeup++;
985
986                 handled |= CSR_INT_BIT_WAKEUP;
987         }
988
989         /* All uCode command responses, including Tx command responses,
990          * Rx "responses" (frame-received notification), and other
991          * notifications from uCode come through here*/
992         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
993                         CSR_INT_BIT_RX_PERIODIC)) {
994                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
995                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
996                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
997                         iwl_write32(priv, CSR_FH_INT_STATUS,
998                                         CSR_FH_INT_RX_MASK);
999                 }
1000                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1001                         handled |= CSR_INT_BIT_RX_PERIODIC;
1002                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1003                 }
1004                 /* Sending RX interrupt require many steps to be done in the
1005                  * the device:
1006                  * 1- write interrupt to current index in ICT table.
1007                  * 2- dma RX frame.
1008                  * 3- update RX shared data to indicate last write index.
1009                  * 4- send interrupt.
1010                  * This could lead to RX race, driver could receive RX interrupt
1011                  * but the shared data changes does not reflect this;
1012                  * periodic interrupt will detect any dangling Rx activity.
1013                  */
1014
1015                 /* Disable periodic interrupt; we use it as just a one-shot. */
1016                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1017                             CSR_INT_PERIODIC_DIS);
1018                 iwl_rx_handle(priv);
1019
1020                 /*
1021                  * Enable periodic interrupt in 8 msec only if we received
1022                  * real RX interrupt (instead of just periodic int), to catch
1023                  * any dangling Rx interrupt.  If it was just the periodic
1024                  * interrupt, there was no dangling Rx activity, and no need
1025                  * to extend the periodic interrupt; one-shot is enough.
1026                  */
1027                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1028                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1029                                     CSR_INT_PERIODIC_ENA);
1030
1031                 priv->isr_stats.rx++;
1032         }
1033
1034         /* This "Tx" DMA channel is used only for loading uCode */
1035         if (inta & CSR_INT_BIT_FH_TX) {
1036                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1037                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1038                 priv->isr_stats.tx++;
1039                 handled |= CSR_INT_BIT_FH_TX;
1040                 /* Wake up uCode load routine, now that load is complete */
1041                 priv->ucode_write_complete = 1;
1042                 wake_up_interruptible(&priv->wait_command_queue);
1043         }
1044
1045         if (inta & ~handled) {
1046                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1047                 priv->isr_stats.unhandled++;
1048         }
1049
1050         if (inta & ~(priv->inta_mask)) {
1051                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1052                          inta & ~priv->inta_mask);
1053         }
1054
1055         /* Re-enable all interrupts */
1056         /* only Re-enable if disabled by irq */
1057         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1058                 iwl_enable_interrupts(priv);
1059         /* Re-enable RF_KILL if it occurred */
1060         else if (handled & CSR_INT_BIT_RF_KILL)
1061                 iwl_enable_rfkill_int(priv);
1062 }
1063
1064 /*****************************************************************************
1065  *
1066  * sysfs attributes
1067  *
1068  *****************************************************************************/
1069
1070 #ifdef CONFIG_IWLWIFI_DEBUG
1071
1072 /*
1073  * The following adds a new attribute to the sysfs representation
1074  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1075  * used for controlling the debug level.
1076  *
1077  * See the level definitions in iwl for details.
1078  *
1079  * The debug_level being managed using sysfs below is a per device debug
1080  * level that is used instead of the global debug level if it (the per
1081  * device debug level) is set.
1082  */
1083 static ssize_t show_debug_level(struct device *d,
1084                                 struct device_attribute *attr, char *buf)
1085 {
1086         struct iwl_priv *priv = dev_get_drvdata(d);
1087         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1088 }
1089 static ssize_t store_debug_level(struct device *d,
1090                                 struct device_attribute *attr,
1091                                  const char *buf, size_t count)
1092 {
1093         struct iwl_priv *priv = dev_get_drvdata(d);
1094         unsigned long val;
1095         int ret;
1096
1097         ret = strict_strtoul(buf, 0, &val);
1098         if (ret)
1099                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1100         else {
1101                 priv->debug_level = val;
1102                 if (iwl_alloc_traffic_mem(priv))
1103                         IWL_ERR(priv,
1104                                 "Not enough memory to generate traffic log\n");
1105         }
1106         return strnlen(buf, count);
1107 }
1108
1109 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1110                         show_debug_level, store_debug_level);
1111
1112
1113 #endif /* CONFIG_IWLWIFI_DEBUG */
1114
1115
1116 static ssize_t show_temperature(struct device *d,
1117                                 struct device_attribute *attr, char *buf)
1118 {
1119         struct iwl_priv *priv = dev_get_drvdata(d);
1120
1121         if (!iwl_is_alive(priv))
1122                 return -EAGAIN;
1123
1124         return sprintf(buf, "%d\n", priv->temperature);
1125 }
1126
1127 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1128
1129 static ssize_t show_tx_power(struct device *d,
1130                              struct device_attribute *attr, char *buf)
1131 {
1132         struct iwl_priv *priv = dev_get_drvdata(d);
1133
1134         if (!iwl_is_ready_rf(priv))
1135                 return sprintf(buf, "off\n");
1136         else
1137                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1138 }
1139
1140 static ssize_t store_tx_power(struct device *d,
1141                               struct device_attribute *attr,
1142                               const char *buf, size_t count)
1143 {
1144         struct iwl_priv *priv = dev_get_drvdata(d);
1145         unsigned long val;
1146         int ret;
1147
1148         ret = strict_strtoul(buf, 10, &val);
1149         if (ret)
1150                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1151         else {
1152                 ret = iwl_set_tx_power(priv, val, false);
1153                 if (ret)
1154                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1155                                 ret);
1156                 else
1157                         ret = count;
1158         }
1159         return ret;
1160 }
1161
1162 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1163
1164 static struct attribute *iwl_sysfs_entries[] = {
1165         &dev_attr_temperature.attr,
1166         &dev_attr_tx_power.attr,
1167 #ifdef CONFIG_IWLWIFI_DEBUG
1168         &dev_attr_debug_level.attr,
1169 #endif
1170         NULL
1171 };
1172
1173 static struct attribute_group iwl_attribute_group = {
1174         .name = NULL,           /* put in device directory */
1175         .attrs = iwl_sysfs_entries,
1176 };
1177
1178 /******************************************************************************
1179  *
1180  * uCode download functions
1181  *
1182  ******************************************************************************/
1183
1184 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1185 {
1186         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1187         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1188         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1189         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1190 }
1191
1192 static void iwl_nic_start(struct iwl_priv *priv)
1193 {
1194         /* Remove all resets to allow NIC to operate */
1195         iwl_write32(priv, CSR_RESET, 0);
1196 }
1197
1198 struct iwlagn_ucode_capabilities {
1199         u32 max_probe_length;
1200         u32 standard_phy_calibration_size;
1201         u32 flags;
1202 };
1203
1204 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1205 static int iwl_mac_setup_register(struct iwl_priv *priv,
1206                                   struct iwlagn_ucode_capabilities *capa);
1207
1208 #define UCODE_EXPERIMENTAL_INDEX        100
1209 #define UCODE_EXPERIMENTAL_TAG          "exp"
1210
1211 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1212 {
1213         const char *name_pre = priv->cfg->fw_name_pre;
1214         char tag[8];
1215
1216         if (first) {
1217 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1218                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1219                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1220         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1221 #endif
1222                 priv->fw_index = priv->cfg->ucode_api_max;
1223                 sprintf(tag, "%d", priv->fw_index);
1224         } else {
1225                 priv->fw_index--;
1226                 sprintf(tag, "%d", priv->fw_index);
1227         }
1228
1229         if (priv->fw_index < priv->cfg->ucode_api_min) {
1230                 IWL_ERR(priv, "no suitable firmware found!\n");
1231                 return -ENOENT;
1232         }
1233
1234         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1235
1236         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1237                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1238                                 ? "EXPERIMENTAL " : "",
1239                        priv->firmware_name);
1240
1241         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1242                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1243                                        iwl_ucode_callback);
1244 }
1245
1246 struct iwlagn_firmware_pieces {
1247         const void *inst, *data, *init, *init_data;
1248         size_t inst_size, data_size, init_size, init_data_size;
1249
1250         u32 build;
1251
1252         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1253         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1254 };
1255
1256 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1257                                        const struct firmware *ucode_raw,
1258                                        struct iwlagn_firmware_pieces *pieces)
1259 {
1260         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1261         u32 api_ver, hdr_size;
1262         const u8 *src;
1263
1264         priv->ucode_ver = le32_to_cpu(ucode->ver);
1265         api_ver = IWL_UCODE_API(priv->ucode_ver);
1266
1267         switch (api_ver) {
1268         default:
1269                 hdr_size = 28;
1270                 if (ucode_raw->size < hdr_size) {
1271                         IWL_ERR(priv, "File size too small!\n");
1272                         return -EINVAL;
1273                 }
1274                 pieces->build = le32_to_cpu(ucode->u.v2.build);
1275                 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1276                 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1277                 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1278                 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1279                 src = ucode->u.v2.data;
1280                 break;
1281         case 0:
1282         case 1:
1283         case 2:
1284                 hdr_size = 24;
1285                 if (ucode_raw->size < hdr_size) {
1286                         IWL_ERR(priv, "File size too small!\n");
1287                         return -EINVAL;
1288                 }
1289                 pieces->build = 0;
1290                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1291                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1292                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1293                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1294                 src = ucode->u.v1.data;
1295                 break;
1296         }
1297
1298         /* Verify size of file vs. image size info in file's header */
1299         if (ucode_raw->size != hdr_size + pieces->inst_size +
1300                                 pieces->data_size + pieces->init_size +
1301                                 pieces->init_data_size) {
1302
1303                 IWL_ERR(priv,
1304                         "uCode file size %d does not match expected size\n",
1305                         (int)ucode_raw->size);
1306                 return -EINVAL;
1307         }
1308
1309         pieces->inst = src;
1310         src += pieces->inst_size;
1311         pieces->data = src;
1312         src += pieces->data_size;
1313         pieces->init = src;
1314         src += pieces->init_size;
1315         pieces->init_data = src;
1316         src += pieces->init_data_size;
1317
1318         return 0;
1319 }
1320
1321 static int iwlagn_wanted_ucode_alternative = 1;
1322
1323 static int iwlagn_load_firmware(struct iwl_priv *priv,
1324                                 const struct firmware *ucode_raw,
1325                                 struct iwlagn_firmware_pieces *pieces,
1326                                 struct iwlagn_ucode_capabilities *capa)
1327 {
1328         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1329         struct iwl_ucode_tlv *tlv;
1330         size_t len = ucode_raw->size;
1331         const u8 *data;
1332         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1333         u64 alternatives;
1334         u32 tlv_len;
1335         enum iwl_ucode_tlv_type tlv_type;
1336         const u8 *tlv_data;
1337
1338         if (len < sizeof(*ucode)) {
1339                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1340                 return -EINVAL;
1341         }
1342
1343         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1344                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1345                         le32_to_cpu(ucode->magic));
1346                 return -EINVAL;
1347         }
1348
1349         /*
1350          * Check which alternatives are present, and "downgrade"
1351          * when the chosen alternative is not present, warning
1352          * the user when that happens. Some files may not have
1353          * any alternatives, so don't warn in that case.
1354          */
1355         alternatives = le64_to_cpu(ucode->alternatives);
1356         tmp = wanted_alternative;
1357         if (wanted_alternative > 63)
1358                 wanted_alternative = 63;
1359         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1360                 wanted_alternative--;
1361         if (wanted_alternative && wanted_alternative != tmp)
1362                 IWL_WARN(priv,
1363                          "uCode alternative %d not available, choosing %d\n",
1364                          tmp, wanted_alternative);
1365
1366         priv->ucode_ver = le32_to_cpu(ucode->ver);
1367         pieces->build = le32_to_cpu(ucode->build);
1368         data = ucode->data;
1369
1370         len -= sizeof(*ucode);
1371
1372         while (len >= sizeof(*tlv)) {
1373                 u16 tlv_alt;
1374
1375                 len -= sizeof(*tlv);
1376                 tlv = (void *)data;
1377
1378                 tlv_len = le32_to_cpu(tlv->length);
1379                 tlv_type = le16_to_cpu(tlv->type);
1380                 tlv_alt = le16_to_cpu(tlv->alternative);
1381                 tlv_data = tlv->data;
1382
1383                 if (len < tlv_len) {
1384                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1385                                 len, tlv_len);
1386                         return -EINVAL;
1387                 }
1388                 len -= ALIGN(tlv_len, 4);
1389                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1390
1391                 /*
1392                  * Alternative 0 is always valid.
1393                  *
1394                  * Skip alternative TLVs that are not selected.
1395                  */
1396                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1397                         continue;
1398
1399                 switch (tlv_type) {
1400                 case IWL_UCODE_TLV_INST:
1401                         pieces->inst = tlv_data;
1402                         pieces->inst_size = tlv_len;
1403                         break;
1404                 case IWL_UCODE_TLV_DATA:
1405                         pieces->data = tlv_data;
1406                         pieces->data_size = tlv_len;
1407                         break;
1408                 case IWL_UCODE_TLV_INIT:
1409                         pieces->init = tlv_data;
1410                         pieces->init_size = tlv_len;
1411                         break;
1412                 case IWL_UCODE_TLV_INIT_DATA:
1413                         pieces->init_data = tlv_data;
1414                         pieces->init_data_size = tlv_len;
1415                         break;
1416                 case IWL_UCODE_TLV_BOOT:
1417                         IWL_ERR(priv, "Found unexpected BOOT ucode\n");
1418                         break;
1419                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1420                         if (tlv_len != sizeof(u32))
1421                                 goto invalid_tlv_len;
1422                         capa->max_probe_length =
1423                                         le32_to_cpup((__le32 *)tlv_data);
1424                         break;
1425                 case IWL_UCODE_TLV_PAN:
1426                         if (tlv_len)
1427                                 goto invalid_tlv_len;
1428                         capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
1429                         break;
1430                 case IWL_UCODE_TLV_FLAGS:
1431                         /* must be at least one u32 */
1432                         if (tlv_len < sizeof(u32))
1433                                 goto invalid_tlv_len;
1434                         /* and a proper number of u32s */
1435                         if (tlv_len % sizeof(u32))
1436                                 goto invalid_tlv_len;
1437                         /*
1438                          * This driver only reads the first u32 as
1439                          * right now no more features are defined,
1440                          * if that changes then either the driver
1441                          * will not work with the new firmware, or
1442                          * it'll not take advantage of new features.
1443                          */
1444                         capa->flags = le32_to_cpup((__le32 *)tlv_data);
1445                         break;
1446                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1447                         if (tlv_len != sizeof(u32))
1448                                 goto invalid_tlv_len;
1449                         pieces->init_evtlog_ptr =
1450                                         le32_to_cpup((__le32 *)tlv_data);
1451                         break;
1452                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1453                         if (tlv_len != sizeof(u32))
1454                                 goto invalid_tlv_len;
1455                         pieces->init_evtlog_size =
1456                                         le32_to_cpup((__le32 *)tlv_data);
1457                         break;
1458                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1459                         if (tlv_len != sizeof(u32))
1460                                 goto invalid_tlv_len;
1461                         pieces->init_errlog_ptr =
1462                                         le32_to_cpup((__le32 *)tlv_data);
1463                         break;
1464                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1465                         if (tlv_len != sizeof(u32))
1466                                 goto invalid_tlv_len;
1467                         pieces->inst_evtlog_ptr =
1468                                         le32_to_cpup((__le32 *)tlv_data);
1469                         break;
1470                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1471                         if (tlv_len != sizeof(u32))
1472                                 goto invalid_tlv_len;
1473                         pieces->inst_evtlog_size =
1474                                         le32_to_cpup((__le32 *)tlv_data);
1475                         break;
1476                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1477                         if (tlv_len != sizeof(u32))
1478                                 goto invalid_tlv_len;
1479                         pieces->inst_errlog_ptr =
1480                                         le32_to_cpup((__le32 *)tlv_data);
1481                         break;
1482                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1483                         if (tlv_len)
1484                                 goto invalid_tlv_len;
1485                         priv->enhance_sensitivity_table = true;
1486                         break;
1487                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1488                         if (tlv_len != sizeof(u32))
1489                                 goto invalid_tlv_len;
1490                         capa->standard_phy_calibration_size =
1491                                         le32_to_cpup((__le32 *)tlv_data);
1492                         break;
1493                 default:
1494                         IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
1495                         break;
1496                 }
1497         }
1498
1499         if (len) {
1500                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1501                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1502                 return -EINVAL;
1503         }
1504
1505         return 0;
1506
1507  invalid_tlv_len:
1508         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1509         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1510
1511         return -EINVAL;
1512 }
1513
1514 /**
1515  * iwl_ucode_callback - callback when firmware was loaded
1516  *
1517  * If loaded successfully, copies the firmware into buffers
1518  * for the card to fetch (via DMA).
1519  */
1520 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1521 {
1522         struct iwl_priv *priv = context;
1523         struct iwl_ucode_header *ucode;
1524         int err;
1525         struct iwlagn_firmware_pieces pieces;
1526         const unsigned int api_max = priv->cfg->ucode_api_max;
1527         const unsigned int api_min = priv->cfg->ucode_api_min;
1528         u32 api_ver;
1529         char buildstr[25];
1530         u32 build;
1531         struct iwlagn_ucode_capabilities ucode_capa = {
1532                 .max_probe_length = 200,
1533                 .standard_phy_calibration_size =
1534                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1535         };
1536
1537         memset(&pieces, 0, sizeof(pieces));
1538
1539         if (!ucode_raw) {
1540                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1541                         IWL_ERR(priv,
1542                                 "request for firmware file '%s' failed.\n",
1543                                 priv->firmware_name);
1544                 goto try_again;
1545         }
1546
1547         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1548                        priv->firmware_name, ucode_raw->size);
1549
1550         /* Make sure that we got at least the API version number */
1551         if (ucode_raw->size < 4) {
1552                 IWL_ERR(priv, "File size way too small!\n");
1553                 goto try_again;
1554         }
1555
1556         /* Data from ucode file:  header followed by uCode images */
1557         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1558
1559         if (ucode->ver)
1560                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1561         else
1562                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1563                                            &ucode_capa);
1564
1565         if (err)
1566                 goto try_again;
1567
1568         api_ver = IWL_UCODE_API(priv->ucode_ver);
1569         build = pieces.build;
1570
1571         /*
1572          * api_ver should match the api version forming part of the
1573          * firmware filename ... but we don't check for that and only rely
1574          * on the API version read from firmware header from here on forward
1575          */
1576         /* no api version check required for experimental uCode */
1577         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1578                 if (api_ver < api_min || api_ver > api_max) {
1579                         IWL_ERR(priv,
1580                                 "Driver unable to support your firmware API. "
1581                                 "Driver supports v%u, firmware is v%u.\n",
1582                                 api_max, api_ver);
1583                         goto try_again;
1584                 }
1585
1586                 if (api_ver != api_max)
1587                         IWL_ERR(priv,
1588                                 "Firmware has old API version. Expected v%u, "
1589                                 "got v%u. New firmware can be obtained "
1590                                 "from http://www.intellinuxwireless.org.\n",
1591                                 api_max, api_ver);
1592         }
1593
1594         if (build)
1595                 sprintf(buildstr, " build %u%s", build,
1596                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1597                                 ? " (EXP)" : "");
1598         else
1599                 buildstr[0] = '\0';
1600
1601         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1602                  IWL_UCODE_MAJOR(priv->ucode_ver),
1603                  IWL_UCODE_MINOR(priv->ucode_ver),
1604                  IWL_UCODE_API(priv->ucode_ver),
1605                  IWL_UCODE_SERIAL(priv->ucode_ver),
1606                  buildstr);
1607
1608         snprintf(priv->hw->wiphy->fw_version,
1609                  sizeof(priv->hw->wiphy->fw_version),
1610                  "%u.%u.%u.%u%s",
1611                  IWL_UCODE_MAJOR(priv->ucode_ver),
1612                  IWL_UCODE_MINOR(priv->ucode_ver),
1613                  IWL_UCODE_API(priv->ucode_ver),
1614                  IWL_UCODE_SERIAL(priv->ucode_ver),
1615                  buildstr);
1616
1617         /*
1618          * For any of the failures below (before allocating pci memory)
1619          * we will try to load a version with a smaller API -- maybe the
1620          * user just got a corrupted version of the latest API.
1621          */
1622
1623         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1624                        priv->ucode_ver);
1625         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1626                        pieces.inst_size);
1627         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1628                        pieces.data_size);
1629         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1630                        pieces.init_size);
1631         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1632                        pieces.init_data_size);
1633
1634         /* Verify that uCode images will fit in card's SRAM */
1635         if (pieces.inst_size > priv->hw_params.max_inst_size) {
1636                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1637                         pieces.inst_size);
1638                 goto try_again;
1639         }
1640
1641         if (pieces.data_size > priv->hw_params.max_data_size) {
1642                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1643                         pieces.data_size);
1644                 goto try_again;
1645         }
1646
1647         if (pieces.init_size > priv->hw_params.max_inst_size) {
1648                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1649                         pieces.init_size);
1650                 goto try_again;
1651         }
1652
1653         if (pieces.init_data_size > priv->hw_params.max_data_size) {
1654                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1655                         pieces.init_data_size);
1656                 goto try_again;
1657         }
1658
1659         /* Allocate ucode buffers for card's bus-master loading ... */
1660
1661         /* Runtime instructions and 2 copies of data:
1662          * 1) unmodified from disk
1663          * 2) backup cache for save/restore during power-downs */
1664         priv->ucode_code.len = pieces.inst_size;
1665         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1666
1667         priv->ucode_data.len = pieces.data_size;
1668         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1669
1670         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr)
1671                 goto err_pci_alloc;
1672
1673         /* Initialization instructions and data */
1674         if (pieces.init_size && pieces.init_data_size) {
1675                 priv->ucode_init.len = pieces.init_size;
1676                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1677
1678                 priv->ucode_init_data.len = pieces.init_data_size;
1679                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1680
1681                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1682                         goto err_pci_alloc;
1683         }
1684
1685         /* Now that we can no longer fail, copy information */
1686
1687         /*
1688          * The (size - 16) / 12 formula is based on the information recorded
1689          * for each event, which is of mode 1 (including timestamp) for all
1690          * new microcodes that include this information.
1691          */
1692         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1693         if (pieces.init_evtlog_size)
1694                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1695         else
1696                 priv->_agn.init_evtlog_size =
1697                         priv->cfg->base_params->max_event_log_size;
1698         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1699         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1700         if (pieces.inst_evtlog_size)
1701                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1702         else
1703                 priv->_agn.inst_evtlog_size =
1704                         priv->cfg->base_params->max_event_log_size;
1705         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1706
1707         if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) {
1708                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1709                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1710         } else
1711                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1712
1713         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1714                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
1715         else
1716                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
1717
1718         /* Copy images into buffers for card's bus-master reads ... */
1719
1720         /* Runtime instructions (first block of data in file) */
1721         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1722                         pieces.inst_size);
1723         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1724
1725         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1726                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1727
1728         /*
1729          * Runtime data
1730          * NOTE:  Copy into backup buffer will be done in iwl_up()
1731          */
1732         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1733                         pieces.data_size);
1734         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1735
1736         /* Initialization instructions */
1737         if (pieces.init_size) {
1738                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1739                                 pieces.init_size);
1740                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1741         }
1742
1743         /* Initialization data */
1744         if (pieces.init_data_size) {
1745                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1746                                pieces.init_data_size);
1747                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1748                        pieces.init_data_size);
1749         }
1750
1751         /*
1752          * figure out the offset of chain noise reset and gain commands
1753          * base on the size of standard phy calibration commands table size
1754          */
1755         if (ucode_capa.standard_phy_calibration_size >
1756             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1757                 ucode_capa.standard_phy_calibration_size =
1758                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1759
1760         priv->_agn.phy_calib_chain_noise_reset_cmd =
1761                 ucode_capa.standard_phy_calibration_size;
1762         priv->_agn.phy_calib_chain_noise_gain_cmd =
1763                 ucode_capa.standard_phy_calibration_size + 1;
1764
1765         /**************************************************
1766          * This is still part of probe() in a sense...
1767          *
1768          * 9. Setup and register with mac80211 and debugfs
1769          **************************************************/
1770         err = iwl_mac_setup_register(priv, &ucode_capa);
1771         if (err)
1772                 goto out_unbind;
1773
1774         err = iwl_dbgfs_register(priv, DRV_NAME);
1775         if (err)
1776                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1777
1778         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1779                                         &iwl_attribute_group);
1780         if (err) {
1781                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1782                 goto out_unbind;
1783         }
1784
1785         /* We have our copies now, allow OS release its copies */
1786         release_firmware(ucode_raw);
1787         complete(&priv->_agn.firmware_loading_complete);
1788         return;
1789
1790  try_again:
1791         /* try next, if any */
1792         if (iwl_request_firmware(priv, false))
1793                 goto out_unbind;
1794         release_firmware(ucode_raw);
1795         return;
1796
1797  err_pci_alloc:
1798         IWL_ERR(priv, "failed to allocate pci memory\n");
1799         iwl_dealloc_ucode_pci(priv);
1800  out_unbind:
1801         complete(&priv->_agn.firmware_loading_complete);
1802         device_release_driver(&priv->pci_dev->dev);
1803         release_firmware(ucode_raw);
1804 }
1805
1806 static const char *desc_lookup_text[] = {
1807         "OK",
1808         "FAIL",
1809         "BAD_PARAM",
1810         "BAD_CHECKSUM",
1811         "NMI_INTERRUPT_WDG",
1812         "SYSASSERT",
1813         "FATAL_ERROR",
1814         "BAD_COMMAND",
1815         "HW_ERROR_TUNE_LOCK",
1816         "HW_ERROR_TEMPERATURE",
1817         "ILLEGAL_CHAN_FREQ",
1818         "VCC_NOT_STABLE",
1819         "FH_ERROR",
1820         "NMI_INTERRUPT_HOST",
1821         "NMI_INTERRUPT_ACTION_PT",
1822         "NMI_INTERRUPT_UNKNOWN",
1823         "UCODE_VERSION_MISMATCH",
1824         "HW_ERROR_ABS_LOCK",
1825         "HW_ERROR_CAL_LOCK_FAIL",
1826         "NMI_INTERRUPT_INST_ACTION_PT",
1827         "NMI_INTERRUPT_DATA_ACTION_PT",
1828         "NMI_TRM_HW_ER",
1829         "NMI_INTERRUPT_TRM",
1830         "NMI_INTERRUPT_BREAK_POINT"
1831         "DEBUG_0",
1832         "DEBUG_1",
1833         "DEBUG_2",
1834         "DEBUG_3",
1835 };
1836
1837 static struct { char *name; u8 num; } advanced_lookup[] = {
1838         { "NMI_INTERRUPT_WDG", 0x34 },
1839         { "SYSASSERT", 0x35 },
1840         { "UCODE_VERSION_MISMATCH", 0x37 },
1841         { "BAD_COMMAND", 0x38 },
1842         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1843         { "FATAL_ERROR", 0x3D },
1844         { "NMI_TRM_HW_ERR", 0x46 },
1845         { "NMI_INTERRUPT_TRM", 0x4C },
1846         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1847         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1848         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1849         { "NMI_INTERRUPT_HOST", 0x66 },
1850         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1851         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1852         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1853         { "ADVANCED_SYSASSERT", 0 },
1854 };
1855
1856 static const char *desc_lookup(u32 num)
1857 {
1858         int i;
1859         int max = ARRAY_SIZE(desc_lookup_text);
1860
1861         if (num < max)
1862                 return desc_lookup_text[num];
1863
1864         max = ARRAY_SIZE(advanced_lookup) - 1;
1865         for (i = 0; i < max; i++) {
1866                 if (advanced_lookup[i].num == num)
1867                         break;;
1868         }
1869         return advanced_lookup[i].name;
1870 }
1871
1872 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1873 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1874
1875 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1876 {
1877         u32 data2, line;
1878         u32 desc, time, count, base, data1;
1879         u32 blink1, blink2, ilink1, ilink2;
1880         u32 pc, hcmd;
1881
1882         base = priv->device_pointers.error_event_table;
1883         if (priv->ucode_type == UCODE_INIT) {
1884                 if (!base)
1885                         base = priv->_agn.init_errlog_ptr;
1886         } else {
1887                 if (!base)
1888                         base = priv->_agn.inst_errlog_ptr;
1889         }
1890
1891         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1892                 IWL_ERR(priv,
1893                         "Not valid error log pointer 0x%08X for %s uCode\n",
1894                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1895                 return;
1896         }
1897
1898         count = iwl_read_targ_mem(priv, base);
1899
1900         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1901                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1902                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1903                         priv->status, count);
1904         }
1905
1906         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1907         priv->isr_stats.err_code = desc;
1908         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
1909         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1910         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1911         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1912         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1913         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1914         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1915         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1916         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1917         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
1918
1919         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1920                                       blink1, blink2, ilink1, ilink2);
1921
1922         IWL_ERR(priv, "Desc                                  Time       "
1923                 "data1      data2      line\n");
1924         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1925                 desc_lookup(desc), desc, time, data1, data2, line);
1926         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
1927         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1928                 pc, blink1, blink2, ilink1, ilink2, hcmd);
1929 }
1930
1931 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1932
1933 /**
1934  * iwl_print_event_log - Dump error event log to syslog
1935  *
1936  */
1937 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1938                                u32 num_events, u32 mode,
1939                                int pos, char **buf, size_t bufsz)
1940 {
1941         u32 i;
1942         u32 base;       /* SRAM byte address of event log header */
1943         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1944         u32 ptr;        /* SRAM byte address of log data */
1945         u32 ev, time, data; /* event log data */
1946         unsigned long reg_flags;
1947
1948         if (num_events == 0)
1949                 return pos;
1950
1951         base = priv->device_pointers.log_event_table;
1952         if (priv->ucode_type == UCODE_INIT) {
1953                 if (!base)
1954                         base = priv->_agn.init_evtlog_ptr;
1955         } else {
1956                 if (!base)
1957                         base = priv->_agn.inst_evtlog_ptr;
1958         }
1959
1960         if (mode == 0)
1961                 event_size = 2 * sizeof(u32);
1962         else
1963                 event_size = 3 * sizeof(u32);
1964
1965         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1966
1967         /* Make sure device is powered up for SRAM reads */
1968         spin_lock_irqsave(&priv->reg_lock, reg_flags);
1969         iwl_grab_nic_access(priv);
1970
1971         /* Set starting address; reads will auto-increment */
1972         iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
1973         rmb();
1974
1975         /* "time" is actually "data" for mode 0 (no timestamp).
1976         * place event id # at far right for easier visual parsing. */
1977         for (i = 0; i < num_events; i++) {
1978                 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1979                 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1980                 if (mode == 0) {
1981                         /* data, ev */
1982                         if (bufsz) {
1983                                 pos += scnprintf(*buf + pos, bufsz - pos,
1984                                                 "EVT_LOG:0x%08x:%04u\n",
1985                                                 time, ev);
1986                         } else {
1987                                 trace_iwlwifi_dev_ucode_event(priv, 0,
1988                                         time, ev);
1989                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1990                                         time, ev);
1991                         }
1992                 } else {
1993                         data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1994                         if (bufsz) {
1995                                 pos += scnprintf(*buf + pos, bufsz - pos,
1996                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
1997                                                  time, data, ev);
1998                         } else {
1999                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2000                                         time, data, ev);
2001                                 trace_iwlwifi_dev_ucode_event(priv, time,
2002                                         data, ev);
2003                         }
2004                 }
2005         }
2006
2007         /* Allow device to power down */
2008         iwl_release_nic_access(priv);
2009         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2010         return pos;
2011 }
2012
2013 /**
2014  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2015  */
2016 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2017                                     u32 num_wraps, u32 next_entry,
2018                                     u32 size, u32 mode,
2019                                     int pos, char **buf, size_t bufsz)
2020 {
2021         /*
2022          * display the newest DEFAULT_LOG_ENTRIES entries
2023          * i.e the entries just before the next ont that uCode would fill.
2024          */
2025         if (num_wraps) {
2026                 if (next_entry < size) {
2027                         pos = iwl_print_event_log(priv,
2028                                                 capacity - (size - next_entry),
2029                                                 size - next_entry, mode,
2030                                                 pos, buf, bufsz);
2031                         pos = iwl_print_event_log(priv, 0,
2032                                                   next_entry, mode,
2033                                                   pos, buf, bufsz);
2034                 } else
2035                         pos = iwl_print_event_log(priv, next_entry - size,
2036                                                   size, mode, pos, buf, bufsz);
2037         } else {
2038                 if (next_entry < size) {
2039                         pos = iwl_print_event_log(priv, 0, next_entry,
2040                                                   mode, pos, buf, bufsz);
2041                 } else {
2042                         pos = iwl_print_event_log(priv, next_entry - size,
2043                                                   size, mode, pos, buf, bufsz);
2044                 }
2045         }
2046         return pos;
2047 }
2048
2049 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2050
2051 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2052                             char **buf, bool display)
2053 {
2054         u32 base;       /* SRAM byte address of event log header */
2055         u32 capacity;   /* event log capacity in # entries */
2056         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2057         u32 num_wraps;  /* # times uCode wrapped to top of log */
2058         u32 next_entry; /* index of next entry to be written by uCode */
2059         u32 size;       /* # entries that we'll print */
2060         u32 logsize;
2061         int pos = 0;
2062         size_t bufsz = 0;
2063
2064         base = priv->device_pointers.log_event_table;
2065         if (priv->ucode_type == UCODE_INIT) {
2066                 logsize = priv->_agn.init_evtlog_size;
2067                 if (!base)
2068                         base = priv->_agn.init_evtlog_ptr;
2069         } else {
2070                 logsize = priv->_agn.inst_evtlog_size;
2071                 if (!base)
2072                         base = priv->_agn.inst_evtlog_ptr;
2073         }
2074
2075         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2076                 IWL_ERR(priv,
2077                         "Invalid event log pointer 0x%08X for %s uCode\n",
2078                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2079                 return -EINVAL;
2080         }
2081
2082         /* event log header */
2083         capacity = iwl_read_targ_mem(priv, base);
2084         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2085         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2086         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2087
2088         if (capacity > logsize) {
2089                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2090                         capacity, logsize);
2091                 capacity = logsize;
2092         }
2093
2094         if (next_entry > logsize) {
2095                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2096                         next_entry, logsize);
2097                 next_entry = logsize;
2098         }
2099
2100         size = num_wraps ? capacity : next_entry;
2101
2102         /* bail out if nothing in log */
2103         if (size == 0) {
2104                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2105                 return pos;
2106         }
2107
2108         /* enable/disable bt channel inhibition */
2109         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2110
2111 #ifdef CONFIG_IWLWIFI_DEBUG
2112         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2113                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2114                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2115 #else
2116         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2117                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2118 #endif
2119         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2120                 size);
2121
2122 #ifdef CONFIG_IWLWIFI_DEBUG
2123         if (display) {
2124                 if (full_log)
2125                         bufsz = capacity * 48;
2126                 else
2127                         bufsz = size * 48;
2128                 *buf = kmalloc(bufsz, GFP_KERNEL);
2129                 if (!*buf)
2130                         return -ENOMEM;
2131         }
2132         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2133                 /*
2134                  * if uCode has wrapped back to top of log,
2135                  * start at the oldest entry,
2136                  * i.e the next one that uCode would fill.
2137                  */
2138                 if (num_wraps)
2139                         pos = iwl_print_event_log(priv, next_entry,
2140                                                 capacity - next_entry, mode,
2141                                                 pos, buf, bufsz);
2142                 /* (then/else) start at top of log */
2143                 pos = iwl_print_event_log(priv, 0,
2144                                           next_entry, mode, pos, buf, bufsz);
2145         } else
2146                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2147                                                 next_entry, size, mode,
2148                                                 pos, buf, bufsz);
2149 #else
2150         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2151                                         next_entry, size, mode,
2152                                         pos, buf, bufsz);
2153 #endif
2154         return pos;
2155 }
2156
2157 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2158 {
2159         struct iwl_ct_kill_config cmd;
2160         struct iwl_ct_kill_throttling_config adv_cmd;
2161         unsigned long flags;
2162         int ret = 0;
2163
2164         spin_lock_irqsave(&priv->lock, flags);
2165         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2166                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2167         spin_unlock_irqrestore(&priv->lock, flags);
2168         priv->thermal_throttle.ct_kill_toggle = false;
2169
2170         if (priv->cfg->base_params->support_ct_kill_exit) {
2171                 adv_cmd.critical_temperature_enter =
2172                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2173                 adv_cmd.critical_temperature_exit =
2174                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2175
2176                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2177                                        sizeof(adv_cmd), &adv_cmd);
2178                 if (ret)
2179                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2180                 else
2181                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2182                                         "succeeded, "
2183                                         "critical temperature enter is %d,"
2184                                         "exit is %d\n",
2185                                        priv->hw_params.ct_kill_threshold,
2186                                        priv->hw_params.ct_kill_exit_threshold);
2187         } else {
2188                 cmd.critical_temperature_R =
2189                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2190
2191                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2192                                        sizeof(cmd), &cmd);
2193                 if (ret)
2194                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2195                 else
2196                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2197                                         "succeeded, "
2198                                         "critical temperature is %d\n",
2199                                         priv->hw_params.ct_kill_threshold);
2200         }
2201 }
2202
2203 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2204 {
2205         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2206         struct iwl_host_cmd cmd = {
2207                 .id = CALIBRATION_CFG_CMD,
2208                 .len = sizeof(struct iwl_calib_cfg_cmd),
2209                 .data = &calib_cfg_cmd,
2210         };
2211
2212         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2213         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2214         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2215
2216         return iwl_send_cmd(priv, &cmd);
2217 }
2218
2219
2220 /**
2221  * iwl_alive_start - called after REPLY_ALIVE notification received
2222  *                   from protocol/runtime uCode (initialization uCode's
2223  *                   Alive gets handled by iwl_init_alive_start()).
2224  */
2225 static void iwl_alive_start(struct iwl_priv *priv)
2226 {
2227         int ret = 0;
2228         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2229
2230         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2231
2232         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2233          * This is a paranoid check, because we would not have gotten the
2234          * "runtime" alive if code weren't properly loaded.  */
2235         if (iwl_verify_ucode(priv, &priv->ucode_code)) {
2236                 /* Runtime instruction load was bad;
2237                  * take it all the way back down so we can try again */
2238                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2239                 goto restart;
2240         }
2241
2242         ret = iwlagn_alive_notify(priv);
2243         if (ret) {
2244                 IWL_WARN(priv,
2245                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2246                 goto restart;
2247         }
2248
2249
2250         /* After the ALIVE response, we can send host commands to the uCode */
2251         set_bit(STATUS_ALIVE, &priv->status);
2252
2253         /* Enable watchdog to monitor the driver tx queues */
2254         iwl_setup_watchdog(priv);
2255
2256         if (iwl_is_rfkill(priv))
2257                 return;
2258
2259         /* download priority table before any calibration request */
2260         if (priv->cfg->bt_params &&
2261             priv->cfg->bt_params->advanced_bt_coexist) {
2262                 /* Configure Bluetooth device coexistence support */
2263                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2264                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2265                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2266                 priv->cfg->ops->hcmd->send_bt_config(priv);
2267                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2268                 iwlagn_send_prio_tbl(priv);
2269
2270                 /* FIXME: w/a to force change uCode BT state machine */
2271                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2272                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2273                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2274                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2275         }
2276         if (priv->hw_params.calib_rt_cfg)
2277                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2278
2279         ieee80211_wake_queues(priv->hw);
2280
2281         priv->active_rate = IWL_RATES_MASK;
2282
2283         /* Configure Tx antenna selection based on H/W config */
2284         if (priv->cfg->ops->hcmd->set_tx_ant)
2285                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2286
2287         if (iwl_is_associated_ctx(ctx)) {
2288                 struct iwl_rxon_cmd *active_rxon =
2289                                 (struct iwl_rxon_cmd *)&ctx->active;
2290                 /* apply any changes in staging */
2291                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2292                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2293         } else {
2294                 struct iwl_rxon_context *tmp;
2295                 /* Initialize our rx_config data */
2296                 for_each_context(priv, tmp)
2297                         iwl_connection_init_rx_config(priv, tmp);
2298
2299                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2300                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2301         }
2302
2303         if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2304             !priv->cfg->bt_params->advanced_bt_coexist)) {
2305                 /*
2306                  * default is 2-wire BT coexexistence support
2307                  */
2308                 priv->cfg->ops->hcmd->send_bt_config(priv);
2309         }
2310
2311         iwl_reset_run_time_calib(priv);
2312
2313         set_bit(STATUS_READY, &priv->status);
2314
2315         /* Configure the adapter for unassociated operation */
2316         iwlcore_commit_rxon(priv, ctx);
2317
2318         /* At this point, the NIC is initialized and operational */
2319         iwl_rf_kill_ct_config(priv);
2320
2321         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2322         wake_up_interruptible(&priv->wait_command_queue);
2323
2324         iwl_power_update_mode(priv, true);
2325         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2326
2327
2328         return;
2329
2330  restart:
2331         queue_work(priv->workqueue, &priv->restart);
2332 }
2333
2334 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2335
2336 static void __iwl_down(struct iwl_priv *priv)
2337 {
2338         unsigned long flags;
2339         int exit_pending;
2340
2341         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2342
2343         iwl_scan_cancel_timeout(priv, 200);
2344
2345         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2346
2347         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2348          * to prevent rearm timer */
2349         del_timer_sync(&priv->watchdog);
2350
2351         iwl_clear_ucode_stations(priv, NULL);
2352         iwl_dealloc_bcast_stations(priv);
2353         iwl_clear_driver_stations(priv);
2354
2355         /* reset BT coex data */
2356         priv->bt_status = 0;
2357         if (priv->cfg->bt_params)
2358                 priv->bt_traffic_load =
2359                          priv->cfg->bt_params->bt_init_traffic_load;
2360         else
2361                 priv->bt_traffic_load = 0;
2362         priv->bt_full_concurrent = false;
2363         priv->bt_ci_compliance = 0;
2364
2365         /* Wipe out the EXIT_PENDING status bit if we are not actually
2366          * exiting the module */
2367         if (!exit_pending)
2368                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2369
2370         /* stop and reset the on-board processor */
2371         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2372
2373         /* tell the device to stop sending interrupts */
2374         spin_lock_irqsave(&priv->lock, flags);
2375         iwl_disable_interrupts(priv);
2376         spin_unlock_irqrestore(&priv->lock, flags);
2377         iwl_synchronize_irq(priv);
2378
2379         if (priv->mac80211_registered)
2380                 ieee80211_stop_queues(priv->hw);
2381
2382         /* If we have not previously called iwl_init() then
2383          * clear all bits but the RF Kill bit and return */
2384         if (!iwl_is_init(priv)) {
2385                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2386                                         STATUS_RF_KILL_HW |
2387                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2388                                         STATUS_GEO_CONFIGURED |
2389                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2390                                         STATUS_EXIT_PENDING;
2391                 goto exit;
2392         }
2393
2394         /* ...otherwise clear out all the status bits but the RF Kill
2395          * bit and continue taking the NIC down. */
2396         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2397                                 STATUS_RF_KILL_HW |
2398                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2399                                 STATUS_GEO_CONFIGURED |
2400                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2401                                 STATUS_FW_ERROR |
2402                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2403                                 STATUS_EXIT_PENDING;
2404
2405         /* device going down, Stop using ICT table */
2406         iwl_disable_ict(priv);
2407
2408         iwlagn_txq_ctx_stop(priv);
2409         iwlagn_rxq_stop(priv);
2410
2411         /* Power-down device's busmaster DMA clocks */
2412         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2413         udelay(5);
2414
2415         /* Make sure (redundant) we've released our request to stay awake */
2416         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2417
2418         /* Stop the device, and put it in low power state */
2419         iwl_apm_stop(priv);
2420
2421  exit:
2422         dev_kfree_skb(priv->beacon_skb);
2423         priv->beacon_skb = NULL;
2424
2425         /* clear out any free frames */
2426         iwl_clear_free_frames(priv);
2427 }
2428
2429 static void iwl_down(struct iwl_priv *priv)
2430 {
2431         mutex_lock(&priv->mutex);
2432         __iwl_down(priv);
2433         mutex_unlock(&priv->mutex);
2434
2435         iwl_cancel_deferred_work(priv);
2436 }
2437
2438 #define HW_READY_TIMEOUT (50)
2439
2440 static int iwl_set_hw_ready(struct iwl_priv *priv)
2441 {
2442         int ret = 0;
2443
2444         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2445                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2446
2447         /* See if we got it */
2448         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2449                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2450                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2451                                 HW_READY_TIMEOUT);
2452         if (ret != -ETIMEDOUT)
2453                 priv->hw_ready = true;
2454         else
2455                 priv->hw_ready = false;
2456
2457         IWL_DEBUG_INFO(priv, "hardware %s\n",
2458                       (priv->hw_ready == 1) ? "ready" : "not ready");
2459         return ret;
2460 }
2461
2462 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2463 {
2464         int ret = 0;
2465
2466         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2467
2468         ret = iwl_set_hw_ready(priv);
2469         if (priv->hw_ready)
2470                 return ret;
2471
2472         /* If HW is not ready, prepare the conditions to check again */
2473         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2474                         CSR_HW_IF_CONFIG_REG_PREPARE);
2475
2476         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2477                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2478                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2479
2480         /* HW should be ready by now, check again. */
2481         if (ret != -ETIMEDOUT)
2482                 iwl_set_hw_ready(priv);
2483
2484         return ret;
2485 }
2486
2487 #define MAX_HW_RESTARTS 5
2488
2489 static int __iwl_up(struct iwl_priv *priv)
2490 {
2491         struct iwl_rxon_context *ctx;
2492         int i;
2493         int ret;
2494
2495         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2496                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2497                 return -EIO;
2498         }
2499
2500         for_each_context(priv, ctx) {
2501                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2502                 if (ret) {
2503                         iwl_dealloc_bcast_stations(priv);
2504                         return ret;
2505                 }
2506         }
2507
2508         iwl_prepare_card_hw(priv);
2509
2510         if (!priv->hw_ready) {
2511                 IWL_WARN(priv, "Exit HW not ready\n");
2512                 return -EIO;
2513         }
2514
2515         /* If platform's RF_KILL switch is NOT set to KILL */
2516         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2517                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2518         else
2519                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2520
2521         if (iwl_is_rfkill(priv)) {
2522                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2523
2524                 iwl_enable_interrupts(priv);
2525                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2526                 return 0;
2527         }
2528
2529         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2530
2531         ret = iwlagn_hw_nic_init(priv);
2532         if (ret) {
2533                 IWL_ERR(priv, "Unable to init nic\n");
2534                 return ret;
2535         }
2536
2537         /* make sure rfkill handshake bits are cleared */
2538         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2539         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2540                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2541
2542         /* clear (again), then enable host interrupts */
2543         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2544         iwl_enable_interrupts(priv);
2545
2546         /* really make sure rfkill handshake bits are cleared */
2547         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2548         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2549
2550         for (i = 0; i < MAX_HW_RESTARTS; i++) {
2551
2552                 /* load bootstrap state machine,
2553                  * load bootstrap program into processor's memory,
2554                  * prepare to load the "initialize" uCode */
2555                 ret = iwlagn_load_ucode(priv);
2556
2557                 if (ret) {
2558                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2559                                 ret);
2560                         continue;
2561                 }
2562
2563                 /* start card; "initialize" will load runtime ucode */
2564                 iwl_nic_start(priv);
2565
2566                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2567
2568                 return 0;
2569         }
2570
2571         set_bit(STATUS_EXIT_PENDING, &priv->status);
2572         __iwl_down(priv);
2573         clear_bit(STATUS_EXIT_PENDING, &priv->status);
2574
2575         /* tried to restart and config the device for as long as our
2576          * patience could withstand */
2577         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2578         return -EIO;
2579 }
2580
2581
2582 /*****************************************************************************
2583  *
2584  * Workqueue callbacks
2585  *
2586  *****************************************************************************/
2587
2588 static void iwl_bg_init_alive_start(struct work_struct *data)
2589 {
2590         struct iwl_priv *priv =
2591             container_of(data, struct iwl_priv, init_alive_start.work);
2592
2593         mutex_lock(&priv->mutex);
2594
2595         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2596                 mutex_unlock(&priv->mutex);
2597                 return;
2598         }
2599
2600         iwlagn_init_alive_start(priv);
2601         mutex_unlock(&priv->mutex);
2602 }
2603
2604 static void iwl_bg_alive_start(struct work_struct *data)
2605 {
2606         struct iwl_priv *priv =
2607             container_of(data, struct iwl_priv, alive_start.work);
2608
2609         mutex_lock(&priv->mutex);
2610         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2611                 goto unlock;
2612
2613         /* enable dram interrupt */
2614         iwl_reset_ict(priv);
2615
2616         iwl_alive_start(priv);
2617 unlock:
2618         mutex_unlock(&priv->mutex);
2619 }
2620
2621 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2622 {
2623         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2624                         run_time_calib_work);
2625
2626         mutex_lock(&priv->mutex);
2627
2628         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2629             test_bit(STATUS_SCANNING, &priv->status)) {
2630                 mutex_unlock(&priv->mutex);
2631                 return;
2632         }
2633
2634         if (priv->start_calib) {
2635                 iwl_chain_noise_calibration(priv);
2636                 iwl_sensitivity_calibration(priv);
2637         }
2638
2639         mutex_unlock(&priv->mutex);
2640 }
2641
2642 static void iwl_bg_restart(struct work_struct *data)
2643 {
2644         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2645
2646         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2647                 return;
2648
2649         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2650                 struct iwl_rxon_context *ctx;
2651                 bool bt_full_concurrent;
2652                 u8 bt_ci_compliance;
2653                 u8 bt_load;
2654                 u8 bt_status;
2655
2656                 mutex_lock(&priv->mutex);
2657                 for_each_context(priv, ctx)
2658                         ctx->vif = NULL;
2659                 priv->is_open = 0;
2660
2661                 /*
2662                  * __iwl_down() will clear the BT status variables,
2663                  * which is correct, but when we restart we really
2664                  * want to keep them so restore them afterwards.
2665                  *
2666                  * The restart process will later pick them up and
2667                  * re-configure the hw when we reconfigure the BT
2668                  * command.
2669                  */
2670                 bt_full_concurrent = priv->bt_full_concurrent;
2671                 bt_ci_compliance = priv->bt_ci_compliance;
2672                 bt_load = priv->bt_traffic_load;
2673                 bt_status = priv->bt_status;
2674
2675                 __iwl_down(priv);
2676
2677                 priv->bt_full_concurrent = bt_full_concurrent;
2678                 priv->bt_ci_compliance = bt_ci_compliance;
2679                 priv->bt_traffic_load = bt_load;
2680                 priv->bt_status = bt_status;
2681
2682                 mutex_unlock(&priv->mutex);
2683                 iwl_cancel_deferred_work(priv);
2684                 ieee80211_restart_hw(priv->hw);
2685         } else {
2686                 iwl_down(priv);
2687
2688                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2689                         return;
2690
2691                 mutex_lock(&priv->mutex);
2692                 __iwl_up(priv);
2693                 mutex_unlock(&priv->mutex);
2694         }
2695 }
2696
2697 static void iwl_bg_rx_replenish(struct work_struct *data)
2698 {
2699         struct iwl_priv *priv =
2700             container_of(data, struct iwl_priv, rx_replenish);
2701
2702         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2703                 return;
2704
2705         mutex_lock(&priv->mutex);
2706         iwlagn_rx_replenish(priv);
2707         mutex_unlock(&priv->mutex);
2708 }
2709
2710 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2711                                  struct ieee80211_channel *chan,
2712                                  enum nl80211_channel_type channel_type,
2713                                  unsigned int wait)
2714 {
2715         struct iwl_priv *priv = hw->priv;
2716         int ret;
2717
2718         /* Not supported if we don't have PAN */
2719         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2720                 ret = -EOPNOTSUPP;
2721                 goto free;
2722         }
2723
2724         /* Not supported on pre-P2P firmware */
2725         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2726                                         BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2727                 ret = -EOPNOTSUPP;
2728                 goto free;
2729         }
2730
2731         mutex_lock(&priv->mutex);
2732
2733         if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2734                 /*
2735                  * If the PAN context is free, use the normal
2736                  * way of doing remain-on-channel offload + TX.
2737                  */
2738                 ret = 1;
2739                 goto out;
2740         }
2741
2742         /* TODO: queue up if scanning? */
2743         if (test_bit(STATUS_SCANNING, &priv->status) ||
2744             priv->_agn.offchan_tx_skb) {
2745                 ret = -EBUSY;
2746                 goto out;
2747         }
2748
2749         /*
2750          * max_scan_ie_len doesn't include the blank SSID or the header,
2751          * so need to add that again here.
2752          */
2753         if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2754                 ret = -ENOBUFS;
2755                 goto out;
2756         }
2757
2758         priv->_agn.offchan_tx_skb = skb;
2759         priv->_agn.offchan_tx_timeout = wait;
2760         priv->_agn.offchan_tx_chan = chan;
2761
2762         ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2763                                 IWL_SCAN_OFFCH_TX, chan->band);
2764         if (ret)
2765                 priv->_agn.offchan_tx_skb = NULL;
2766  out:
2767         mutex_unlock(&priv->mutex);
2768  free:
2769         if (ret < 0)
2770                 kfree_skb(skb);
2771
2772         return ret;
2773 }
2774
2775 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2776 {
2777         struct iwl_priv *priv = hw->priv;
2778         int ret;
2779
2780         mutex_lock(&priv->mutex);
2781
2782         if (!priv->_agn.offchan_tx_skb) {
2783                 ret = -EINVAL;
2784                 goto unlock;
2785         }
2786
2787         priv->_agn.offchan_tx_skb = NULL;
2788
2789         ret = iwl_scan_cancel_timeout(priv, 200);
2790         if (ret)
2791                 ret = -EIO;
2792 unlock:
2793         mutex_unlock(&priv->mutex);
2794
2795         return ret;
2796 }
2797
2798 /*****************************************************************************
2799  *
2800  * mac80211 entry point functions
2801  *
2802  *****************************************************************************/
2803
2804 #define UCODE_READY_TIMEOUT     (4 * HZ)
2805
2806 /*
2807  * Not a mac80211 entry point function, but it fits in with all the
2808  * other mac80211 functions grouped here.
2809  */
2810 static int iwl_mac_setup_register(struct iwl_priv *priv,
2811                                   struct iwlagn_ucode_capabilities *capa)
2812 {
2813         int ret;
2814         struct ieee80211_hw *hw = priv->hw;
2815         struct iwl_rxon_context *ctx;
2816
2817         hw->rate_control_algorithm = "iwl-agn-rs";
2818
2819         /* Tell mac80211 our characteristics */
2820         hw->flags = IEEE80211_HW_SIGNAL_DBM |
2821                     IEEE80211_HW_AMPDU_AGGREGATION |
2822                     IEEE80211_HW_NEED_DTIM_PERIOD |
2823                     IEEE80211_HW_SPECTRUM_MGMT |
2824                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2825
2826         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2827
2828         hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2829                      IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2830
2831         if (priv->cfg->sku & IWL_SKU_N)
2832                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2833                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2834
2835         if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
2836                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
2837
2838         hw->sta_data_size = sizeof(struct iwl_station_priv);
2839         hw->vif_data_size = sizeof(struct iwl_vif_priv);
2840
2841         for_each_context(priv, ctx) {
2842                 hw->wiphy->interface_modes |= ctx->interface_modes;
2843                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2844         }
2845
2846         hw->wiphy->max_remain_on_channel_duration = 1000;
2847
2848         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2849                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
2850                             WIPHY_FLAG_IBSS_RSN;
2851
2852         /*
2853          * For now, disable PS by default because it affects
2854          * RX performance significantly.
2855          */
2856         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2857
2858         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2859         /* we create the 802.11 header and a zero-length SSID element */
2860         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2861
2862         /* Default value; 4 EDCA QOS priorities */
2863         hw->queues = 4;
2864
2865         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2866
2867         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2868                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2869                         &priv->bands[IEEE80211_BAND_2GHZ];
2870         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2871                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2872                         &priv->bands[IEEE80211_BAND_5GHZ];
2873
2874         iwl_leds_init(priv);
2875
2876         ret = ieee80211_register_hw(priv->hw);
2877         if (ret) {
2878                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2879                 return ret;
2880         }
2881         priv->mac80211_registered = 1;
2882
2883         return 0;
2884 }
2885
2886
2887 static int iwlagn_mac_start(struct ieee80211_hw *hw)
2888 {
2889         struct iwl_priv *priv = hw->priv;
2890         int ret;
2891
2892         IWL_DEBUG_MAC80211(priv, "enter\n");
2893
2894         /* we should be verifying the device is ready to be opened */
2895         mutex_lock(&priv->mutex);
2896         ret = __iwl_up(priv);
2897         mutex_unlock(&priv->mutex);
2898
2899         if (ret)
2900                 return ret;
2901
2902         if (iwl_is_rfkill(priv))
2903                 goto out;
2904
2905         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2906
2907         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2908          * mac80211 will not be run successfully. */
2909         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2910                         test_bit(STATUS_READY, &priv->status),
2911                         UCODE_READY_TIMEOUT);
2912         if (!ret) {
2913                 if (!test_bit(STATUS_READY, &priv->status)) {
2914                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2915                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2916                         return -ETIMEDOUT;
2917                 }
2918         }
2919
2920         iwlagn_led_enable(priv);
2921
2922 out:
2923         priv->is_open = 1;
2924         IWL_DEBUG_MAC80211(priv, "leave\n");
2925         return 0;
2926 }
2927
2928 static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2929 {
2930         struct iwl_priv *priv = hw->priv;
2931
2932         IWL_DEBUG_MAC80211(priv, "enter\n");
2933
2934         if (!priv->is_open)
2935                 return;
2936
2937         priv->is_open = 0;
2938
2939         iwl_down(priv);
2940
2941         flush_workqueue(priv->workqueue);
2942
2943         /* User space software may expect getting rfkill changes
2944          * even if interface is down */
2945         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2946         iwl_enable_rfkill_int(priv);
2947
2948         IWL_DEBUG_MAC80211(priv, "leave\n");
2949 }
2950
2951 static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2952 {
2953         struct iwl_priv *priv = hw->priv;
2954
2955         IWL_DEBUG_MACDUMP(priv, "enter\n");
2956
2957         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2958                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2959
2960         if (iwlagn_tx_skb(priv, skb))
2961                 dev_kfree_skb_any(skb);
2962
2963         IWL_DEBUG_MACDUMP(priv, "leave\n");
2964 }
2965
2966 static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2967                                        struct ieee80211_vif *vif,
2968                                        struct ieee80211_key_conf *keyconf,
2969                                        struct ieee80211_sta *sta,
2970                                        u32 iv32, u16 *phase1key)
2971 {
2972         struct iwl_priv *priv = hw->priv;
2973         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2974
2975         IWL_DEBUG_MAC80211(priv, "enter\n");
2976
2977         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2978                             iv32, phase1key);
2979
2980         IWL_DEBUG_MAC80211(priv, "leave\n");
2981 }
2982
2983 static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2984                               struct ieee80211_vif *vif,
2985                               struct ieee80211_sta *sta,
2986                               struct ieee80211_key_conf *key)
2987 {
2988         struct iwl_priv *priv = hw->priv;
2989         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2990         struct iwl_rxon_context *ctx = vif_priv->ctx;
2991         int ret;
2992         u8 sta_id;
2993         bool is_default_wep_key = false;
2994
2995         IWL_DEBUG_MAC80211(priv, "enter\n");
2996
2997         if (priv->cfg->mod_params->sw_crypto) {
2998                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2999                 return -EOPNOTSUPP;
3000         }
3001
3002         /*
3003          * To support IBSS RSN, don't program group keys in IBSS, the
3004          * hardware will then not attempt to decrypt the frames.
3005          */
3006         if (vif->type == NL80211_IFTYPE_ADHOC &&
3007             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3008                 return -EOPNOTSUPP;
3009
3010         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3011         if (sta_id == IWL_INVALID_STATION)
3012                 return -EINVAL;
3013
3014         mutex_lock(&priv->mutex);
3015         iwl_scan_cancel_timeout(priv, 100);
3016
3017         /*
3018          * If we are getting WEP group key and we didn't receive any key mapping
3019          * so far, we are in legacy wep mode (group key only), otherwise we are
3020          * in 1X mode.
3021          * In legacy wep mode, we use another host command to the uCode.
3022          */
3023         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3024              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3025             !sta) {
3026                 if (cmd == SET_KEY)
3027                         is_default_wep_key = !ctx->key_mapping_keys;
3028                 else
3029                         is_default_wep_key =
3030                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3031         }
3032
3033         switch (cmd) {
3034         case SET_KEY:
3035                 if (is_default_wep_key)
3036                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3037                 else
3038                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3039                                                   key, sta_id);
3040
3041                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3042                 break;
3043         case DISABLE_KEY:
3044                 if (is_default_wep_key)
3045                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3046                 else
3047                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3048
3049                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3050                 break;
3051         default:
3052                 ret = -EINVAL;
3053         }
3054
3055         mutex_unlock(&priv->mutex);
3056         IWL_DEBUG_MAC80211(priv, "leave\n");
3057
3058         return ret;
3059 }
3060
3061 static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3062                                    struct ieee80211_vif *vif,
3063                                    enum ieee80211_ampdu_mlme_action action,
3064                                    struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3065                                    u8 buf_size)
3066 {
3067         struct iwl_priv *priv = hw->priv;
3068         int ret = -EINVAL;
3069         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3070
3071         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3072                      sta->addr, tid);
3073
3074         if (!(priv->cfg->sku & IWL_SKU_N))
3075                 return -EACCES;
3076
3077         mutex_lock(&priv->mutex);
3078
3079         switch (action) {
3080         case IEEE80211_AMPDU_RX_START:
3081                 IWL_DEBUG_HT(priv, "start Rx\n");
3082                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3083                 break;
3084         case IEEE80211_AMPDU_RX_STOP:
3085                 IWL_DEBUG_HT(priv, "stop Rx\n");
3086                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3087                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3088                         ret = 0;
3089                 break;
3090         case IEEE80211_AMPDU_TX_START:
3091                 IWL_DEBUG_HT(priv, "start Tx\n");
3092                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3093                 if (ret == 0) {
3094                         priv->_agn.agg_tids_count++;
3095                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3096                                      priv->_agn.agg_tids_count);
3097                 }
3098                 break;
3099         case IEEE80211_AMPDU_TX_STOP:
3100                 IWL_DEBUG_HT(priv, "stop Tx\n");
3101                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3102                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3103                         priv->_agn.agg_tids_count--;
3104                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3105                                      priv->_agn.agg_tids_count);
3106                 }
3107                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3108                         ret = 0;
3109                 if (priv->cfg->ht_params &&
3110                     priv->cfg->ht_params->use_rts_for_aggregation) {
3111                         struct iwl_station_priv *sta_priv =
3112                                 (void *) sta->drv_priv;
3113                         /*
3114                          * switch off RTS/CTS if it was previously enabled
3115                          */
3116
3117                         sta_priv->lq_sta.lq.general_params.flags &=
3118                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3119                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3120                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3121                 }
3122                 break;
3123         case IEEE80211_AMPDU_TX_OPERATIONAL:
3124                 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
3125
3126                 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
3127
3128                 /*
3129                  * If the limit is 0, then it wasn't initialised yet,
3130                  * use the default. We can do that since we take the
3131                  * minimum below, and we don't want to go above our
3132                  * default due to hardware restrictions.
3133                  */
3134                 if (sta_priv->max_agg_bufsize == 0)
3135                         sta_priv->max_agg_bufsize =
3136                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3137
3138                 /*
3139                  * Even though in theory the peer could have different
3140                  * aggregation reorder buffer sizes for different sessions,
3141                  * our ucode doesn't allow for that and has a global limit
3142                  * for each station. Therefore, use the minimum of all the
3143                  * aggregation sessions and our default value.
3144                  */
3145                 sta_priv->max_agg_bufsize =
3146                         min(sta_priv->max_agg_bufsize, buf_size);
3147
3148                 if (priv->cfg->ht_params &&
3149                     priv->cfg->ht_params->use_rts_for_aggregation) {
3150                         /*
3151                          * switch to RTS/CTS if it is the prefer protection
3152                          * method for HT traffic
3153                          */
3154
3155                         sta_priv->lq_sta.lq.general_params.flags |=
3156                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3157                 }
3158
3159                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3160                         sta_priv->max_agg_bufsize;
3161
3162                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3163                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3164                 ret = 0;
3165                 break;
3166         }
3167         mutex_unlock(&priv->mutex);
3168
3169         return ret;
3170 }
3171
3172 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3173                               struct ieee80211_vif *vif,
3174                               struct ieee80211_sta *sta)
3175 {
3176         struct iwl_priv *priv = hw->priv;
3177         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3178         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3179         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3180         int ret;
3181         u8 sta_id;
3182
3183         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3184                         sta->addr);
3185         mutex_lock(&priv->mutex);
3186         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3187                         sta->addr);
3188         sta_priv->common.sta_id = IWL_INVALID_STATION;
3189
3190         atomic_set(&sta_priv->pending_frames, 0);
3191         if (vif->type == NL80211_IFTYPE_AP)
3192                 sta_priv->client = true;
3193
3194         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3195                                      is_ap, sta, &sta_id);
3196         if (ret) {
3197                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3198                         sta->addr, ret);
3199                 /* Should we return success if return code is EEXIST ? */
3200                 mutex_unlock(&priv->mutex);
3201                 return ret;
3202         }
3203
3204         sta_priv->common.sta_id = sta_id;
3205
3206         /* Initialize rate scaling */
3207         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3208                        sta->addr);
3209         iwl_rs_rate_init(priv, sta, sta_id);
3210         mutex_unlock(&priv->mutex);
3211
3212         return 0;
3213 }
3214
3215 static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3216                                 struct ieee80211_channel_switch *ch_switch)
3217 {
3218         struct iwl_priv *priv = hw->priv;
3219         const struct iwl_channel_info *ch_info;
3220         struct ieee80211_conf *conf = &hw->conf;
3221         struct ieee80211_channel *channel = ch_switch->channel;
3222         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3223         /*
3224          * MULTI-FIXME
3225          * When we add support for multiple interfaces, we need to
3226          * revisit this. The channel switch command in the device
3227          * only affects the BSS context, but what does that really
3228          * mean? And what if we get a CSA on the second interface?
3229          * This needs a lot of work.
3230          */
3231         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3232         u16 ch;
3233         unsigned long flags = 0;
3234
3235         IWL_DEBUG_MAC80211(priv, "enter\n");
3236
3237         mutex_lock(&priv->mutex);
3238
3239         if (iwl_is_rfkill(priv))
3240                 goto out;
3241
3242         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3243             test_bit(STATUS_SCANNING, &priv->status))
3244                 goto out;
3245
3246         if (!iwl_is_associated_ctx(ctx))
3247                 goto out;
3248
3249         /* channel switch in progress */
3250         if (priv->switch_rxon.switch_in_progress == true)
3251                 goto out;
3252
3253         if (priv->cfg->ops->lib->set_channel_switch) {
3254
3255                 ch = channel->hw_value;
3256                 if (le16_to_cpu(ctx->active.channel) != ch) {
3257                         ch_info = iwl_get_channel_info(priv,
3258                                                        channel->band,
3259                                                        ch);
3260                         if (!is_channel_valid(ch_info)) {
3261                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3262                                 goto out;
3263                         }
3264                         spin_lock_irqsave(&priv->lock, flags);
3265
3266                         priv->current_ht_config.smps = conf->smps_mode;
3267
3268                         /* Configure HT40 channels */
3269                         ctx->ht.enabled = conf_is_ht(conf);
3270                         if (ctx->ht.enabled) {
3271                                 if (conf_is_ht40_minus(conf)) {
3272                                         ctx->ht.extension_chan_offset =
3273                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3274                                         ctx->ht.is_40mhz = true;
3275                                 } else if (conf_is_ht40_plus(conf)) {
3276                                         ctx->ht.extension_chan_offset =
3277                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3278                                         ctx->ht.is_40mhz = true;
3279                                 } else {
3280                                         ctx->ht.extension_chan_offset =
3281                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3282                                         ctx->ht.is_40mhz = false;
3283                                 }
3284                         } else
3285                                 ctx->ht.is_40mhz = false;
3286
3287                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3288                                 ctx->staging.flags = 0;
3289
3290                         iwl_set_rxon_channel(priv, channel, ctx);
3291                         iwl_set_rxon_ht(priv, ht_conf);
3292                         iwl_set_flags_for_band(priv, ctx, channel->band,
3293                                                ctx->vif);
3294                         spin_unlock_irqrestore(&priv->lock, flags);
3295
3296                         iwl_set_rate(priv);
3297                         /*
3298                          * at this point, staging_rxon has the
3299                          * configuration for channel switch
3300                          */
3301                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3302                                                                     ch_switch))
3303                                 priv->switch_rxon.switch_in_progress = false;
3304                 }
3305         }
3306 out:
3307         mutex_unlock(&priv->mutex);
3308         if (!priv->switch_rxon.switch_in_progress)
3309                 ieee80211_chswitch_done(ctx->vif, false);
3310         IWL_DEBUG_MAC80211(priv, "leave\n");
3311 }
3312
3313 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3314                                     unsigned int changed_flags,
3315                                     unsigned int *total_flags,
3316                                     u64 multicast)
3317 {
3318         struct iwl_priv *priv = hw->priv;
3319         __le32 filter_or = 0, filter_nand = 0;
3320         struct iwl_rxon_context *ctx;
3321
3322 #define CHK(test, flag) do { \
3323         if (*total_flags & (test))              \
3324                 filter_or |= (flag);            \
3325         else                                    \
3326                 filter_nand |= (flag);          \
3327         } while (0)
3328
3329         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3330                         changed_flags, *total_flags);
3331
3332         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3333         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3334         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3335         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3336
3337 #undef CHK
3338
3339         mutex_lock(&priv->mutex);
3340
3341         for_each_context(priv, ctx) {
3342                 ctx->staging.filter_flags &= ~filter_nand;
3343                 ctx->staging.filter_flags |= filter_or;
3344
3345                 /*
3346                  * Not committing directly because hardware can perform a scan,
3347                  * but we'll eventually commit the filter flags change anyway.
3348                  */
3349         }
3350
3351         mutex_unlock(&priv->mutex);
3352
3353         /*
3354          * Receiving all multicast frames is always enabled by the
3355          * default flags setup in iwl_connection_init_rx_config()
3356          * since we currently do not support programming multicast
3357          * filters into the device.
3358          */
3359         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3360                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3361 }
3362
3363 static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3364 {
3365         struct iwl_priv *priv = hw->priv;
3366
3367         mutex_lock(&priv->mutex);
3368         IWL_DEBUG_MAC80211(priv, "enter\n");
3369
3370         /* do not support "flush" */
3371         if (!priv->cfg->ops->lib->txfifo_flush)
3372                 goto done;
3373
3374         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3375                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3376                 goto done;
3377         }
3378         if (iwl_is_rfkill(priv)) {
3379                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3380                 goto done;
3381         }
3382
3383         /*
3384          * mac80211 will not push any more frames for transmit
3385          * until the flush is completed
3386          */
3387         if (drop) {
3388                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3389                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3390                         IWL_ERR(priv, "flush request fail\n");
3391                         goto done;
3392                 }
3393         }
3394         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3395         iwlagn_wait_tx_queue_empty(priv);
3396 done:
3397         mutex_unlock(&priv->mutex);
3398         IWL_DEBUG_MAC80211(priv, "leave\n");
3399 }
3400
3401 static void iwlagn_disable_roc(struct iwl_priv *priv)
3402 {
3403         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3404         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3405
3406         lockdep_assert_held(&priv->mutex);
3407
3408         if (!ctx->is_active)
3409                 return;
3410
3411         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3412         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3413         iwl_set_rxon_channel(priv, chan, ctx);
3414         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3415
3416         priv->_agn.hw_roc_channel = NULL;
3417
3418         iwlcore_commit_rxon(priv, ctx);
3419
3420         ctx->is_active = false;
3421 }
3422
3423 static void iwlagn_bg_roc_done(struct work_struct *work)
3424 {
3425         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3426                                              _agn.hw_roc_work.work);
3427
3428         mutex_lock(&priv->mutex);
3429         ieee80211_remain_on_channel_expired(priv->hw);
3430         iwlagn_disable_roc(priv);
3431         mutex_unlock(&priv->mutex);
3432 }
3433
3434 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3435                                      struct ieee80211_channel *channel,
3436                                      enum nl80211_channel_type channel_type,
3437                                      int duration)
3438 {
3439         struct iwl_priv *priv = hw->priv;
3440         int err = 0;
3441
3442         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3443                 return -EOPNOTSUPP;
3444
3445         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3446                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3447                 return -EOPNOTSUPP;
3448
3449         mutex_lock(&priv->mutex);
3450
3451         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3452             test_bit(STATUS_SCAN_HW, &priv->status)) {
3453                 err = -EBUSY;
3454                 goto out;
3455         }
3456
3457         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3458         priv->_agn.hw_roc_channel = channel;
3459         priv->_agn.hw_roc_chantype = channel_type;
3460         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3461         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3462         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3463                            msecs_to_jiffies(duration + 20));
3464
3465         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3466         ieee80211_ready_on_channel(priv->hw);
3467
3468  out:
3469         mutex_unlock(&priv->mutex);
3470
3471         return err;
3472 }
3473
3474 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3475 {
3476         struct iwl_priv *priv = hw->priv;
3477
3478         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3479                 return -EOPNOTSUPP;
3480
3481         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3482
3483         mutex_lock(&priv->mutex);
3484         iwlagn_disable_roc(priv);
3485         mutex_unlock(&priv->mutex);
3486
3487         return 0;
3488 }
3489
3490 /*****************************************************************************
3491  *
3492  * driver setup and teardown
3493  *
3494  *****************************************************************************/
3495
3496 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3497 {
3498         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3499
3500         init_waitqueue_head(&priv->wait_command_queue);
3501
3502         INIT_WORK(&priv->restart, iwl_bg_restart);
3503         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3504         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3505         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3506         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3507         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3508         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3509         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3510         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3511         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3512
3513         iwl_setup_scan_deferred_work(priv);
3514
3515         if (priv->cfg->ops->lib->setup_deferred_work)
3516                 priv->cfg->ops->lib->setup_deferred_work(priv);
3517
3518         init_timer(&priv->statistics_periodic);
3519         priv->statistics_periodic.data = (unsigned long)priv;
3520         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3521
3522         init_timer(&priv->ucode_trace);
3523         priv->ucode_trace.data = (unsigned long)priv;
3524         priv->ucode_trace.function = iwl_bg_ucode_trace;
3525
3526         init_timer(&priv->watchdog);
3527         priv->watchdog.data = (unsigned long)priv;
3528         priv->watchdog.function = iwl_bg_watchdog;
3529
3530         tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3531                 iwl_irq_tasklet, (unsigned long)priv);
3532 }
3533
3534 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3535 {
3536         if (priv->cfg->ops->lib->cancel_deferred_work)
3537                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3538
3539         cancel_delayed_work_sync(&priv->init_alive_start);
3540         cancel_delayed_work(&priv->alive_start);
3541         cancel_work_sync(&priv->run_time_calib_work);
3542         cancel_work_sync(&priv->beacon_update);
3543
3544         iwl_cancel_scan_deferred_work(priv);
3545
3546         cancel_work_sync(&priv->bt_full_concurrency);
3547         cancel_work_sync(&priv->bt_runtime_config);
3548
3549         del_timer_sync(&priv->statistics_periodic);
3550         del_timer_sync(&priv->ucode_trace);
3551 }
3552
3553 static void iwl_init_hw_rates(struct iwl_priv *priv,
3554                               struct ieee80211_rate *rates)
3555 {
3556         int i;
3557
3558         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3559                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3560                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3561                 rates[i].hw_value_short = i;
3562                 rates[i].flags = 0;
3563                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3564                         /*
3565                          * If CCK != 1M then set short preamble rate flag.
3566                          */
3567                         rates[i].flags |=
3568                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3569                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3570                 }
3571         }
3572 }
3573
3574 static int iwl_init_drv(struct iwl_priv *priv)
3575 {
3576         int ret;
3577
3578         spin_lock_init(&priv->sta_lock);
3579         spin_lock_init(&priv->hcmd_lock);
3580
3581         INIT_LIST_HEAD(&priv->free_frames);
3582
3583         mutex_init(&priv->mutex);
3584
3585         priv->ieee_channels = NULL;
3586         priv->ieee_rates = NULL;
3587         priv->band = IEEE80211_BAND_2GHZ;
3588
3589         priv->iw_mode = NL80211_IFTYPE_STATION;
3590         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3591         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3592         priv->_agn.agg_tids_count = 0;
3593
3594         /* initialize force reset */
3595         priv->force_reset[IWL_RF_RESET].reset_duration =
3596                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3597         priv->force_reset[IWL_FW_RESET].reset_duration =
3598                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3599
3600         priv->rx_statistics_jiffies = jiffies;
3601
3602         /* Choose which receivers/antennas to use */
3603         if (priv->cfg->ops->hcmd->set_rxon_chain)
3604                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3605                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3606
3607         iwl_init_scan_params(priv);
3608
3609         /* init bt coex */
3610         if (priv->cfg->bt_params &&
3611             priv->cfg->bt_params->advanced_bt_coexist) {
3612                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3613                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3614                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3615                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3616                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3617                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3618         }
3619
3620         /* Set the tx_power_user_lmt to the lowest power level
3621          * this value will get overwritten by channel max power avg
3622          * from eeprom */
3623         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3624         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3625
3626         ret = iwl_init_channel_map(priv);
3627         if (ret) {
3628                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3629                 goto err;
3630         }
3631
3632         ret = iwlcore_init_geos(priv);
3633         if (ret) {
3634                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3635                 goto err_free_channel_map;
3636         }
3637         iwl_init_hw_rates(priv, priv->ieee_rates);
3638
3639         return 0;
3640
3641 err_free_channel_map:
3642         iwl_free_channel_map(priv);
3643 err:
3644         return ret;
3645 }
3646
3647 static void iwl_uninit_drv(struct iwl_priv *priv)
3648 {
3649         iwl_calib_free_results(priv);
3650         iwlcore_free_geos(priv);
3651         iwl_free_channel_map(priv);
3652         kfree(priv->scan_cmd);
3653 }
3654
3655 struct ieee80211_ops iwlagn_hw_ops = {
3656         .tx = iwlagn_mac_tx,
3657         .start = iwlagn_mac_start,
3658         .stop = iwlagn_mac_stop,
3659         .add_interface = iwl_mac_add_interface,
3660         .remove_interface = iwl_mac_remove_interface,
3661         .change_interface = iwl_mac_change_interface,
3662         .config = iwlagn_mac_config,
3663         .configure_filter = iwlagn_configure_filter,
3664         .set_key = iwlagn_mac_set_key,
3665         .update_tkip_key = iwlagn_mac_update_tkip_key,
3666         .conf_tx = iwl_mac_conf_tx,
3667         .bss_info_changed = iwlagn_bss_info_changed,
3668         .ampdu_action = iwlagn_mac_ampdu_action,
3669         .hw_scan = iwl_mac_hw_scan,
3670         .sta_notify = iwlagn_mac_sta_notify,
3671         .sta_add = iwlagn_mac_sta_add,
3672         .sta_remove = iwl_mac_sta_remove,
3673         .channel_switch = iwlagn_mac_channel_switch,
3674         .flush = iwlagn_mac_flush,
3675         .tx_last_beacon = iwl_mac_tx_last_beacon,
3676         .remain_on_channel = iwl_mac_remain_on_channel,
3677         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3678         .offchannel_tx = iwl_mac_offchannel_tx,
3679         .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3680 };
3681
3682 static u32 iwl_hw_detect(struct iwl_priv *priv)
3683 {
3684         u8 rev_id;
3685
3686         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
3687         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
3688         return iwl_read32(priv, CSR_HW_REV);
3689 }
3690
3691 static int iwl_set_hw_params(struct iwl_priv *priv)
3692 {
3693         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3694         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3695         if (priv->cfg->mod_params->amsdu_size_8K)
3696                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3697         else
3698                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3699
3700         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3701
3702         if (priv->cfg->mod_params->disable_11n)
3703                 priv->cfg->sku &= ~IWL_SKU_N;
3704
3705         /* Device-specific setup */
3706         return priv->cfg->ops->lib->set_hw_params(priv);
3707 }
3708
3709 static const u8 iwlagn_bss_ac_to_fifo[] = {
3710         IWL_TX_FIFO_VO,
3711         IWL_TX_FIFO_VI,
3712         IWL_TX_FIFO_BE,
3713         IWL_TX_FIFO_BK,
3714 };
3715
3716 static const u8 iwlagn_bss_ac_to_queue[] = {
3717         0, 1, 2, 3,
3718 };
3719
3720 static const u8 iwlagn_pan_ac_to_fifo[] = {
3721         IWL_TX_FIFO_VO_IPAN,
3722         IWL_TX_FIFO_VI_IPAN,
3723         IWL_TX_FIFO_BE_IPAN,
3724         IWL_TX_FIFO_BK_IPAN,
3725 };
3726
3727 static const u8 iwlagn_pan_ac_to_queue[] = {
3728         7, 6, 5, 4,
3729 };
3730
3731 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3732 {
3733         int err = 0, i;
3734         struct iwl_priv *priv;
3735         struct ieee80211_hw *hw;
3736         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3737         unsigned long flags;
3738         u16 pci_cmd, num_mac;
3739         u32 hw_rev;
3740
3741         /************************
3742          * 1. Allocating HW data
3743          ************************/
3744
3745         hw = iwl_alloc_all(cfg);
3746         if (!hw) {
3747                 err = -ENOMEM;
3748                 goto out;
3749         }
3750         priv = hw->priv;
3751         /* At this point both hw and priv are allocated. */
3752
3753         /*
3754          * The default context is always valid,
3755          * more may be discovered when firmware
3756          * is loaded.
3757          */
3758         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3759
3760         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3761                 priv->contexts[i].ctxid = i;
3762
3763         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3764         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3765         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3766         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3767         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3768         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3769         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3770         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3771         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3772         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3773         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3774                 BIT(NL80211_IFTYPE_ADHOC);
3775         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3776                 BIT(NL80211_IFTYPE_STATION);
3777         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3778         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3779         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3780         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3781
3782         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3783         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3784         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3785         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3786         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3787         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3788         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3789         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3790         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3791         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3792         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3793         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3794                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3795 #ifdef CONFIG_IWL_P2P
3796         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3797                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3798 #endif
3799         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3800         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3801         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3802
3803         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3804
3805         SET_IEEE80211_DEV(hw, &pdev->dev);
3806
3807         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3808         priv->cfg = cfg;
3809         priv->pci_dev = pdev;
3810         priv->inta_mask = CSR_INI_SET_MASK;
3811
3812         /* is antenna coupling more than 35dB ? */
3813         priv->bt_ant_couple_ok =
3814                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3815                 true : false;
3816
3817         /* enable/disable bt channel inhibition */
3818         priv->bt_ch_announce = iwlagn_bt_ch_announce;
3819         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3820                        (priv->bt_ch_announce) ? "On" : "Off");
3821
3822         if (iwl_alloc_traffic_mem(priv))
3823                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3824
3825         /**************************
3826          * 2. Initializing PCI bus
3827          **************************/
3828         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3829                                 PCIE_LINK_STATE_CLKPM);
3830
3831         if (pci_enable_device(pdev)) {
3832                 err = -ENODEV;
3833                 goto out_ieee80211_free_hw;
3834         }
3835
3836         pci_set_master(pdev);
3837
3838         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3839         if (!err)
3840                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3841         if (err) {
3842                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3843                 if (!err)
3844                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3845                 /* both attempts failed: */
3846                 if (err) {
3847                         IWL_WARN(priv, "No suitable DMA available.\n");
3848                         goto out_pci_disable_device;
3849                 }
3850         }
3851
3852         err = pci_request_regions(pdev, DRV_NAME);
3853         if (err)
3854                 goto out_pci_disable_device;
3855
3856         pci_set_drvdata(pdev, priv);
3857
3858
3859         /***********************
3860          * 3. Read REV register
3861          ***********************/
3862         priv->hw_base = pci_iomap(pdev, 0, 0);
3863         if (!priv->hw_base) {
3864                 err = -ENODEV;
3865                 goto out_pci_release_regions;
3866         }
3867
3868         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3869                 (unsigned long long) pci_resource_len(pdev, 0));
3870         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3871
3872         /* these spin locks will be used in apm_ops.init and EEPROM access
3873          * we should init now
3874          */
3875         spin_lock_init(&priv->reg_lock);
3876         spin_lock_init(&priv->lock);
3877
3878         /*
3879          * stop and reset the on-board processor just in case it is in a
3880          * strange state ... like being left stranded by a primary kernel
3881          * and this is now the kdump kernel trying to start up
3882          */
3883         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3884
3885         hw_rev = iwl_hw_detect(priv);
3886         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3887                 priv->cfg->name, hw_rev);
3888
3889         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3890          * PCI Tx retries from interfering with C3 CPU state */
3891         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3892
3893         iwl_prepare_card_hw(priv);
3894         if (!priv->hw_ready) {
3895                 IWL_WARN(priv, "Failed, HW not ready\n");
3896                 goto out_iounmap;
3897         }
3898
3899         /*****************
3900          * 4. Read EEPROM
3901          *****************/
3902         /* Read the EEPROM */
3903         err = iwl_eeprom_init(priv, hw_rev);
3904         if (err) {
3905                 IWL_ERR(priv, "Unable to init EEPROM\n");
3906                 goto out_iounmap;
3907         }
3908         err = iwl_eeprom_check_version(priv);
3909         if (err)
3910                 goto out_free_eeprom;
3911
3912         err = iwl_eeprom_check_sku(priv);
3913         if (err)
3914                 goto out_free_eeprom;
3915
3916         /* extract MAC Address */
3917         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3918         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3919         priv->hw->wiphy->addresses = priv->addresses;
3920         priv->hw->wiphy->n_addresses = 1;
3921         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3922         if (num_mac > 1) {
3923                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3924                        ETH_ALEN);
3925                 priv->addresses[1].addr[5]++;
3926                 priv->hw->wiphy->n_addresses++;
3927         }
3928
3929         /************************
3930          * 5. Setup HW constants
3931          ************************/
3932         if (iwl_set_hw_params(priv)) {
3933                 IWL_ERR(priv, "failed to set hw parameters\n");
3934                 goto out_free_eeprom;
3935         }
3936
3937         /*******************
3938          * 6. Setup priv
3939          *******************/
3940
3941         err = iwl_init_drv(priv);
3942         if (err)
3943                 goto out_free_eeprom;
3944         /* At this point both hw and priv are initialized. */
3945
3946         /********************
3947          * 7. Setup services
3948          ********************/
3949         spin_lock_irqsave(&priv->lock, flags);
3950         iwl_disable_interrupts(priv);
3951         spin_unlock_irqrestore(&priv->lock, flags);
3952
3953         pci_enable_msi(priv->pci_dev);
3954
3955         iwl_alloc_isr_ict(priv);
3956
3957         err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
3958                           IRQF_SHARED, DRV_NAME, priv);
3959         if (err) {
3960                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3961                 goto out_disable_msi;
3962         }
3963
3964         iwl_setup_deferred_work(priv);
3965         iwl_setup_rx_handlers(priv);
3966
3967         /*********************************************
3968          * 8. Enable interrupts and read RFKILL state
3969          *********************************************/
3970
3971         /* enable rfkill interrupt: hw bug w/a */
3972         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3973         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3974                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3975                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3976         }
3977
3978         iwl_enable_rfkill_int(priv);
3979
3980         /* If platform's RF_KILL switch is NOT set to KILL */
3981         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3982                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3983         else
3984                 set_bit(STATUS_RF_KILL_HW, &priv->status);
3985
3986         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3987                 test_bit(STATUS_RF_KILL_HW, &priv->status));
3988
3989         iwl_power_initialize(priv);
3990         iwl_tt_initialize(priv);
3991
3992         init_completion(&priv->_agn.firmware_loading_complete);
3993
3994         err = iwl_request_firmware(priv, true);
3995         if (err)
3996                 goto out_destroy_workqueue;
3997
3998         return 0;
3999
4000  out_destroy_workqueue:
4001         destroy_workqueue(priv->workqueue);
4002         priv->workqueue = NULL;
4003         free_irq(priv->pci_dev->irq, priv);
4004         iwl_free_isr_ict(priv);
4005  out_disable_msi:
4006         pci_disable_msi(priv->pci_dev);
4007         iwl_uninit_drv(priv);
4008  out_free_eeprom:
4009         iwl_eeprom_free(priv);
4010  out_iounmap:
4011         pci_iounmap(pdev, priv->hw_base);
4012  out_pci_release_regions:
4013         pci_set_drvdata(pdev, NULL);
4014         pci_release_regions(pdev);
4015  out_pci_disable_device:
4016         pci_disable_device(pdev);
4017  out_ieee80211_free_hw:
4018         iwl_free_traffic_mem(priv);
4019         ieee80211_free_hw(priv->hw);
4020  out:
4021         return err;
4022 }
4023
4024 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4025 {
4026         struct iwl_priv *priv = pci_get_drvdata(pdev);
4027         unsigned long flags;
4028
4029         if (!priv)
4030                 return;
4031
4032         wait_for_completion(&priv->_agn.firmware_loading_complete);
4033
4034         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4035
4036         iwl_dbgfs_unregister(priv);
4037         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4038
4039         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4040          * to be called and iwl_down since we are removing the device
4041          * we need to set STATUS_EXIT_PENDING bit.
4042          */
4043         set_bit(STATUS_EXIT_PENDING, &priv->status);
4044
4045         iwl_leds_exit(priv);
4046
4047         if (priv->mac80211_registered) {
4048                 ieee80211_unregister_hw(priv->hw);
4049                 priv->mac80211_registered = 0;
4050         } else {
4051                 iwl_down(priv);
4052         }
4053
4054         /*
4055          * Make sure device is reset to low power before unloading driver.
4056          * This may be redundant with iwl_down(), but there are paths to
4057          * run iwl_down() without calling apm_ops.stop(), and there are
4058          * paths to avoid running iwl_down() at all before leaving driver.
4059          * This (inexpensive) call *makes sure* device is reset.
4060          */
4061         iwl_apm_stop(priv);
4062
4063         iwl_tt_exit(priv);
4064
4065         /* make sure we flush any pending irq or
4066          * tasklet for the driver
4067          */
4068         spin_lock_irqsave(&priv->lock, flags);
4069         iwl_disable_interrupts(priv);
4070         spin_unlock_irqrestore(&priv->lock, flags);
4071
4072         iwl_synchronize_irq(priv);
4073
4074         iwl_dealloc_ucode_pci(priv);
4075
4076         if (priv->rxq.bd)
4077                 iwlagn_rx_queue_free(priv, &priv->rxq);
4078         iwlagn_hw_txq_ctx_free(priv);
4079
4080         iwl_eeprom_free(priv);
4081
4082
4083         /*netif_stop_queue(dev); */
4084         flush_workqueue(priv->workqueue);
4085
4086         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4087          * priv->workqueue... so we can't take down the workqueue
4088          * until now... */
4089         destroy_workqueue(priv->workqueue);
4090         priv->workqueue = NULL;
4091         iwl_free_traffic_mem(priv);
4092
4093         free_irq(priv->pci_dev->irq, priv);
4094         pci_disable_msi(priv->pci_dev);
4095         pci_iounmap(pdev, priv->hw_base);
4096         pci_release_regions(pdev);
4097         pci_disable_device(pdev);
4098         pci_set_drvdata(pdev, NULL);
4099
4100         iwl_uninit_drv(priv);
4101
4102         iwl_free_isr_ict(priv);
4103
4104         dev_kfree_skb(priv->beacon_skb);
4105
4106         ieee80211_free_hw(priv->hw);
4107 }
4108
4109
4110 /*****************************************************************************
4111  *
4112  * driver and module entry point
4113  *
4114  *****************************************************************************/
4115
4116 /* Hardware specific file defines the PCI IDs table for that hardware module */
4117 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4118         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4119         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4120         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4121         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4122         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4123         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4124         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4125         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4126         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4127         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4128         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4129         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4130         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4131         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4132         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4133         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4134         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4135         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4136         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4137         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4138         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4139         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4140         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4141         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4142
4143 /* 5300 Series WiFi */
4144         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4145         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4146         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4147         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4148         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4149         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4150         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4151         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4152         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4153         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4154         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4155         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4156
4157 /* 5350 Series WiFi/WiMax */
4158         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4159         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4160         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4161
4162 /* 5150 Series Wifi/WiMax */
4163         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4164         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4165         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4166         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4167         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4168         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4169
4170         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4171         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4172         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4173         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4174
4175 /* 6x00 Series */
4176         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4177         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4178         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4179         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4180         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4181         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4182         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4183         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4184         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4185         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4186
4187 /* 6x05 Series */
4188         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4189         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4190         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4191         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4192         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4193         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4194         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4195
4196 /* 6x30 Series */
4197         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4198         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4199         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4200         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4201         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4202         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4203         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4204         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4205         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4206         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4207         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4208         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4209         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4210         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4211         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4212         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4213
4214 /* 6x50 WiFi/WiMax Series */
4215         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4216         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4217         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4218         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4219         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4220         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4221
4222 /* 6150 WiFi/WiMax Series */
4223         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4224         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4225         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4226         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4227         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4228         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4229
4230 /* 1000 Series WiFi */
4231         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4232         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4233         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4234         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4235         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4236         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4237         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4238         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4239         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4240         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4241         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4242         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4243
4244 /* 100 Series WiFi */
4245         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4246         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4247         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4248         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4249         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4250         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4251
4252 /* 130 Series WiFi */
4253         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4254         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4255         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4256         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4257         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4258         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4259
4260 /* 2x00 Series */
4261         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4262         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4263         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4264         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4265         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4266         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4267
4268 /* 2x30 Series */
4269         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4270         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4271         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4272         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4273         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4274         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4275
4276 /* 6x35 Series */
4277         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4278         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4279         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4280         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4281         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4282         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4283         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4284         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4285         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4286
4287 /* 200 Series */
4288         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4289         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4290         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4291         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4292         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4293         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4294
4295 /* 230 Series */
4296         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4297         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4298         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4299         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4300         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4301         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4302
4303         {0}
4304 };
4305 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4306
4307 static struct pci_driver iwl_driver = {
4308         .name = DRV_NAME,
4309         .id_table = iwl_hw_card_ids,
4310         .probe = iwl_pci_probe,
4311         .remove = __devexit_p(iwl_pci_remove),
4312         .driver.pm = IWL_PM_OPS,
4313 };
4314
4315 static int __init iwl_init(void)
4316 {
4317
4318         int ret;
4319         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4320         pr_info(DRV_COPYRIGHT "\n");
4321
4322         ret = iwlagn_rate_control_register();
4323         if (ret) {
4324                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4325                 return ret;
4326         }
4327
4328         ret = pci_register_driver(&iwl_driver);
4329         if (ret) {
4330                 pr_err("Unable to initialize PCI module\n");
4331                 goto error_register;
4332         }
4333
4334         return ret;
4335
4336 error_register:
4337         iwlagn_rate_control_unregister();
4338         return ret;
4339 }
4340
4341 static void __exit iwl_exit(void)
4342 {
4343         pci_unregister_driver(&iwl_driver);
4344         iwlagn_rate_control_unregister();
4345 }
4346
4347 module_exit(iwl_exit);
4348 module_init(iwl_init);
4349
4350 #ifdef CONFIG_IWLWIFI_DEBUG
4351 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4352 MODULE_PARM_DESC(debug, "debug output mask");
4353 #endif
4354
4355 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4356 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4357 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4358 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4359 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4360 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4361 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4362                    int, S_IRUGO);
4363 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4364 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4365 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4366
4367 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4368                    S_IRUGO);
4369 MODULE_PARM_DESC(ucode_alternative,
4370                  "specify ucode alternative to use from ucode file");
4371
4372 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4373 MODULE_PARM_DESC(antenna_coupling,
4374                  "specify antenna coupling in dB (defualt: 0 dB)");
4375
4376 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4377 MODULE_PARM_DESC(bt_ch_inhibition,
4378                  "Disable BT channel inhibition (default: enable)");
4379
4380 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4381 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4382
4383 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4384 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");