iwlwifi: remember the last uCode sysassert error code
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project, as well
6  * as portions of the ieee80211 subsystem header files.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of version 2 of the GNU General Public License as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20  *
21  * The full GNU General Public License is included in this distribution in the
22  * file called LICENSE.
23  *
24  * Contact Information:
25  *  Intel Linux Wireless <ilw@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
47
48 #include <net/mac80211.h>
49
50 #include <asm/div64.h>
51
52 #define DRV_NAME        "iwlagn"
53
54 #include "iwl-eeprom.h"
55 #include "iwl-dev.h"
56 #include "iwl-core.h"
57 #include "iwl-io.h"
58 #include "iwl-helpers.h"
59 #include "iwl-sta.h"
60 #include "iwl-calib.h"
61 #include "iwl-agn.h"
62
63
64 /******************************************************************************
65  *
66  * module boiler plate
67  *
68  ******************************************************************************/
69
70 /*
71  * module name, copyright, version, etc.
72  */
73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
74
75 #ifdef CONFIG_IWLWIFI_DEBUG
76 #define VD "d"
77 #else
78 #define VD
79 #endif
80
81 #define DRV_VERSION     IWLWIFI_VERSION VD
82
83
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88 MODULE_ALIAS("iwl4965");
89
90 static int iwlagn_ant_coupling;
91 static bool iwlagn_bt_ch_announce = 1;
92
93 /**
94  * iwl_commit_rxon - commit staging_rxon to hardware
95  *
96  * The RXON command in staging_rxon is committed to the hardware and
97  * the active_rxon structure is updated with the new data.  This
98  * function correctly transitions out of the RXON_ASSOC_MSK state if
99  * a HW tune is required based on the RXON structure changes.
100  */
101 int iwl_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
102 {
103         /* cast away the const for active_rxon in this function */
104         struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
105         int ret;
106         bool new_assoc =
107                 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
108         bool old_assoc = !!(ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK);
109
110         if (!iwl_is_alive(priv))
111                 return -EBUSY;
112
113         /* always get timestamp with Rx frame */
114         ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
115
116         ret = iwl_check_rxon_cmd(priv, ctx);
117         if (ret) {
118                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
119                 return -EINVAL;
120         }
121
122         /*
123          * receive commit_rxon request
124          * abort any previous channel switch if still in process
125          */
126         if (priv->switch_rxon.switch_in_progress &&
127             (priv->switch_rxon.channel != ctx->staging.channel)) {
128                 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
129                       le16_to_cpu(priv->switch_rxon.channel));
130                 iwl_chswitch_done(priv, false);
131         }
132
133         /* If we don't need to send a full RXON, we can use
134          * iwl_rxon_assoc_cmd which is used to reconfigure filter
135          * and other flags for the current radio configuration. */
136         if (!iwl_full_rxon_required(priv, ctx)) {
137                 ret = iwl_send_rxon_assoc(priv, ctx);
138                 if (ret) {
139                         IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
140                         return ret;
141                 }
142
143                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
144                 iwl_print_rx_config_cmd(priv, ctx);
145                 return 0;
146         }
147
148         /* If we are currently associated and the new config requires
149          * an RXON_ASSOC and the new config wants the associated mask enabled,
150          * we must clear the associated from the active configuration
151          * before we apply the new config */
152         if (iwl_is_associated_ctx(ctx) && new_assoc) {
153                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
154                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
155
156                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
157                                        sizeof(struct iwl_rxon_cmd),
158                                        active_rxon);
159
160                 /* If the mask clearing failed then we set
161                  * active_rxon back to what it was previously */
162                 if (ret) {
163                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
164                         IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
165                         return ret;
166                 }
167                 iwl_clear_ucode_stations(priv, ctx);
168                 iwl_restore_stations(priv, ctx);
169                 ret = iwl_restore_default_wep_keys(priv, ctx);
170                 if (ret) {
171                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
172                         return ret;
173                 }
174         }
175
176         IWL_DEBUG_INFO(priv, "Sending RXON\n"
177                        "* with%s RXON_FILTER_ASSOC_MSK\n"
178                        "* channel = %d\n"
179                        "* bssid = %pM\n",
180                        (new_assoc ? "" : "out"),
181                        le16_to_cpu(ctx->staging.channel),
182                        ctx->staging.bssid_addr);
183
184         iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
185
186         if (!old_assoc) {
187                 /*
188                  * First of all, before setting associated, we need to
189                  * send RXON timing so the device knows about the DTIM
190                  * period and other timing values
191                  */
192                 ret = iwl_send_rxon_timing(priv, ctx);
193                 if (ret) {
194                         IWL_ERR(priv, "Error setting RXON timing!\n");
195                         return ret;
196                 }
197         }
198
199         if (priv->cfg->ops->hcmd->set_pan_params) {
200                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
201                 if (ret)
202                         return ret;
203         }
204
205         /* Apply the new configuration
206          * RXON unassoc clears the station table in uCode so restoration of
207          * stations is needed after it (the RXON command) completes
208          */
209         if (!new_assoc) {
210                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
211                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
212                 if (ret) {
213                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
214                         return ret;
215                 }
216                 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
217                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
218                 iwl_clear_ucode_stations(priv, ctx);
219                 iwl_restore_stations(priv, ctx);
220                 ret = iwl_restore_default_wep_keys(priv, ctx);
221                 if (ret) {
222                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
223                         return ret;
224                 }
225         }
226
227         priv->start_calib = 0;
228         if (new_assoc) {
229                 /* Apply the new configuration
230                  * RXON assoc doesn't clear the station table in uCode,
231                  */
232                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
233                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
234                 if (ret) {
235                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
236                         return ret;
237                 }
238                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
239         }
240         iwl_print_rx_config_cmd(priv, ctx);
241
242         iwl_init_sensitivity(priv);
243
244         /* If we issue a new RXON command which required a tune then we must
245          * send a new TXPOWER command or we won't be able to Tx any frames */
246         ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
247         if (ret) {
248                 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
249                 return ret;
250         }
251
252         return 0;
253 }
254
255 void iwl_update_chain_flags(struct iwl_priv *priv)
256 {
257         struct iwl_rxon_context *ctx;
258
259         if (priv->cfg->ops->hcmd->set_rxon_chain) {
260                 for_each_context(priv, ctx) {
261                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
262                         iwlcore_commit_rxon(priv, ctx);
263                 }
264         }
265 }
266
267 static void iwl_clear_free_frames(struct iwl_priv *priv)
268 {
269         struct list_head *element;
270
271         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
272                        priv->frames_count);
273
274         while (!list_empty(&priv->free_frames)) {
275                 element = priv->free_frames.next;
276                 list_del(element);
277                 kfree(list_entry(element, struct iwl_frame, list));
278                 priv->frames_count--;
279         }
280
281         if (priv->frames_count) {
282                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
283                             priv->frames_count);
284                 priv->frames_count = 0;
285         }
286 }
287
288 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
289 {
290         struct iwl_frame *frame;
291         struct list_head *element;
292         if (list_empty(&priv->free_frames)) {
293                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
294                 if (!frame) {
295                         IWL_ERR(priv, "Could not allocate frame!\n");
296                         return NULL;
297                 }
298
299                 priv->frames_count++;
300                 return frame;
301         }
302
303         element = priv->free_frames.next;
304         list_del(element);
305         return list_entry(element, struct iwl_frame, list);
306 }
307
308 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
309 {
310         memset(frame, 0, sizeof(*frame));
311         list_add(&frame->list, &priv->free_frames);
312 }
313
314 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
315                                           struct ieee80211_hdr *hdr,
316                                           int left)
317 {
318         if (!priv->ibss_beacon)
319                 return 0;
320
321         if (priv->ibss_beacon->len > left)
322                 return 0;
323
324         memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
325
326         return priv->ibss_beacon->len;
327 }
328
329 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
330 static void iwl_set_beacon_tim(struct iwl_priv *priv,
331                 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
332                 u8 *beacon, u32 frame_size)
333 {
334         u16 tim_idx;
335         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
336
337         /*
338          * The index is relative to frame start but we start looking at the
339          * variable-length part of the beacon.
340          */
341         tim_idx = mgmt->u.beacon.variable - beacon;
342
343         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
344         while ((tim_idx < (frame_size - 2)) &&
345                         (beacon[tim_idx] != WLAN_EID_TIM))
346                 tim_idx += beacon[tim_idx+1] + 2;
347
348         /* If TIM field was found, set variables */
349         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
350                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
351                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
352         } else
353                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
354 }
355
356 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
357                                        struct iwl_frame *frame)
358 {
359         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
360         u32 frame_size;
361         u32 rate_flags;
362         u32 rate;
363         /*
364          * We have to set up the TX command, the TX Beacon command, and the
365          * beacon contents.
366          */
367
368         lockdep_assert_held(&priv->mutex);
369
370         if (!priv->beacon_ctx) {
371                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
372                 return 0;
373         }
374
375         /* Initialize memory */
376         tx_beacon_cmd = &frame->u.beacon;
377         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
378
379         /* Set up TX beacon contents */
380         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
381                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
382         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
383                 return 0;
384
385         /* Set up TX command fields */
386         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
387         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
388         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
389         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
390                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
391
392         /* Set up TX beacon command fields */
393         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
394                         frame_size);
395
396         /* Set up packet rate and flags */
397         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
398         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
399                                               priv->hw_params.valid_tx_ant);
400         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
401         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
402                 rate_flags |= RATE_MCS_CCK_MSK;
403         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
404                         rate_flags);
405
406         return sizeof(*tx_beacon_cmd) + frame_size;
407 }
408 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
409 {
410         struct iwl_frame *frame;
411         unsigned int frame_size;
412         int rc;
413
414         frame = iwl_get_free_frame(priv);
415         if (!frame) {
416                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
417                           "command.\n");
418                 return -ENOMEM;
419         }
420
421         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
422         if (!frame_size) {
423                 IWL_ERR(priv, "Error configuring the beacon command\n");
424                 iwl_free_frame(priv, frame);
425                 return -EINVAL;
426         }
427
428         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
429                               &frame->u.cmd[0]);
430
431         iwl_free_frame(priv, frame);
432
433         return rc;
434 }
435
436 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
437 {
438         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
439
440         dma_addr_t addr = get_unaligned_le32(&tb->lo);
441         if (sizeof(dma_addr_t) > sizeof(u32))
442                 addr |=
443                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
444
445         return addr;
446 }
447
448 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
449 {
450         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
451
452         return le16_to_cpu(tb->hi_n_len) >> 4;
453 }
454
455 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
456                                   dma_addr_t addr, u16 len)
457 {
458         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
459         u16 hi_n_len = len << 4;
460
461         put_unaligned_le32(addr, &tb->lo);
462         if (sizeof(dma_addr_t) > sizeof(u32))
463                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
464
465         tb->hi_n_len = cpu_to_le16(hi_n_len);
466
467         tfd->num_tbs = idx + 1;
468 }
469
470 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
471 {
472         return tfd->num_tbs & 0x1f;
473 }
474
475 /**
476  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
477  * @priv - driver private data
478  * @txq - tx queue
479  *
480  * Does NOT advance any TFD circular buffer read/write indexes
481  * Does NOT free the TFD itself (which is within circular buffer)
482  */
483 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
484 {
485         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
486         struct iwl_tfd *tfd;
487         struct pci_dev *dev = priv->pci_dev;
488         int index = txq->q.read_ptr;
489         int i;
490         int num_tbs;
491
492         tfd = &tfd_tmp[index];
493
494         /* Sanity check on number of chunks */
495         num_tbs = iwl_tfd_get_num_tbs(tfd);
496
497         if (num_tbs >= IWL_NUM_OF_TBS) {
498                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
499                 /* @todo issue fatal error, it is quite serious situation */
500                 return;
501         }
502
503         /* Unmap tx_cmd */
504         if (num_tbs)
505                 pci_unmap_single(dev,
506                                 dma_unmap_addr(&txq->meta[index], mapping),
507                                 dma_unmap_len(&txq->meta[index], len),
508                                 PCI_DMA_BIDIRECTIONAL);
509
510         /* Unmap chunks, if any. */
511         for (i = 1; i < num_tbs; i++)
512                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
513                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
514
515         /* free SKB */
516         if (txq->txb) {
517                 struct sk_buff *skb;
518
519                 skb = txq->txb[txq->q.read_ptr].skb;
520
521                 /* can be called from irqs-disabled context */
522                 if (skb) {
523                         dev_kfree_skb_any(skb);
524                         txq->txb[txq->q.read_ptr].skb = NULL;
525                 }
526         }
527 }
528
529 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
530                                  struct iwl_tx_queue *txq,
531                                  dma_addr_t addr, u16 len,
532                                  u8 reset, u8 pad)
533 {
534         struct iwl_queue *q;
535         struct iwl_tfd *tfd, *tfd_tmp;
536         u32 num_tbs;
537
538         q = &txq->q;
539         tfd_tmp = (struct iwl_tfd *)txq->tfds;
540         tfd = &tfd_tmp[q->write_ptr];
541
542         if (reset)
543                 memset(tfd, 0, sizeof(*tfd));
544
545         num_tbs = iwl_tfd_get_num_tbs(tfd);
546
547         /* Each TFD can point to a maximum 20 Tx buffers */
548         if (num_tbs >= IWL_NUM_OF_TBS) {
549                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
550                           IWL_NUM_OF_TBS);
551                 return -EINVAL;
552         }
553
554         BUG_ON(addr & ~DMA_BIT_MASK(36));
555         if (unlikely(addr & ~IWL_TX_DMA_MASK))
556                 IWL_ERR(priv, "Unaligned address = %llx\n",
557                           (unsigned long long)addr);
558
559         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
560
561         return 0;
562 }
563
564 /*
565  * Tell nic where to find circular buffer of Tx Frame Descriptors for
566  * given Tx queue, and enable the DMA channel used for that queue.
567  *
568  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
569  * channels supported in hardware.
570  */
571 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
572                          struct iwl_tx_queue *txq)
573 {
574         int txq_id = txq->q.id;
575
576         /* Circular buffer (TFD queue in DRAM) physical base address */
577         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
578                              txq->q.dma_addr >> 8);
579
580         return 0;
581 }
582
583 /******************************************************************************
584  *
585  * Generic RX handler implementations
586  *
587  ******************************************************************************/
588 static void iwl_rx_reply_alive(struct iwl_priv *priv,
589                                 struct iwl_rx_mem_buffer *rxb)
590 {
591         struct iwl_rx_packet *pkt = rxb_addr(rxb);
592         struct iwl_alive_resp *palive;
593         struct delayed_work *pwork;
594
595         palive = &pkt->u.alive_frame;
596
597         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
598                        "0x%01X 0x%01X\n",
599                        palive->is_valid, palive->ver_type,
600                        palive->ver_subtype);
601
602         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
603                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
604                 memcpy(&priv->card_alive_init,
605                        &pkt->u.alive_frame,
606                        sizeof(struct iwl_init_alive_resp));
607                 pwork = &priv->init_alive_start;
608         } else {
609                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
610                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
611                        sizeof(struct iwl_alive_resp));
612                 pwork = &priv->alive_start;
613         }
614
615         /* We delay the ALIVE response by 5ms to
616          * give the HW RF Kill time to activate... */
617         if (palive->is_valid == UCODE_VALID_OK)
618                 queue_delayed_work(priv->workqueue, pwork,
619                                    msecs_to_jiffies(5));
620         else
621                 IWL_WARN(priv, "uCode did not respond OK.\n");
622 }
623
624 static void iwl_bg_beacon_update(struct work_struct *work)
625 {
626         struct iwl_priv *priv =
627                 container_of(work, struct iwl_priv, beacon_update);
628         struct sk_buff *beacon;
629
630         mutex_lock(&priv->mutex);
631         if (!priv->beacon_ctx) {
632                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
633                 goto out;
634         }
635
636         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
637                 /*
638                  * The ucode will send beacon notifications even in
639                  * IBSS mode, but we don't want to process them. But
640                  * we need to defer the type check to here due to
641                  * requiring locking around the beacon_ctx access.
642                  */
643                 goto out;
644         }
645
646         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
647         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
648         if (!beacon) {
649                 IWL_ERR(priv, "update beacon failed\n");
650                 goto out;
651         }
652
653         /* new beacon skb is allocated every time; dispose previous.*/
654         if (priv->ibss_beacon)
655                 dev_kfree_skb(priv->ibss_beacon);
656
657         priv->ibss_beacon = beacon;
658
659         iwl_send_beacon_cmd(priv);
660  out:
661         mutex_unlock(&priv->mutex);
662 }
663
664 static void iwl_bg_bt_runtime_config(struct work_struct *work)
665 {
666         struct iwl_priv *priv =
667                 container_of(work, struct iwl_priv, bt_runtime_config);
668
669         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
670                 return;
671
672         /* dont send host command if rf-kill is on */
673         if (!iwl_is_ready_rf(priv))
674                 return;
675         priv->cfg->ops->hcmd->send_bt_config(priv);
676 }
677
678 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
679 {
680         struct iwl_priv *priv =
681                 container_of(work, struct iwl_priv, bt_full_concurrency);
682         struct iwl_rxon_context *ctx;
683
684         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
685                 return;
686
687         /* dont send host command if rf-kill is on */
688         if (!iwl_is_ready_rf(priv))
689                 return;
690
691         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
692                        priv->bt_full_concurrent ?
693                        "full concurrency" : "3-wire");
694
695         /*
696          * LQ & RXON updated cmds must be sent before BT Config cmd
697          * to avoid 3-wire collisions
698          */
699         mutex_lock(&priv->mutex);
700         for_each_context(priv, ctx) {
701                 if (priv->cfg->ops->hcmd->set_rxon_chain)
702                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
703                 iwlcore_commit_rxon(priv, ctx);
704         }
705         mutex_unlock(&priv->mutex);
706
707         priv->cfg->ops->hcmd->send_bt_config(priv);
708 }
709
710 /**
711  * iwl_bg_statistics_periodic - Timer callback to queue statistics
712  *
713  * This callback is provided in order to send a statistics request.
714  *
715  * This timer function is continually reset to execute within
716  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
717  * was received.  We need to ensure we receive the statistics in order
718  * to update the temperature used for calibrating the TXPOWER.
719  */
720 static void iwl_bg_statistics_periodic(unsigned long data)
721 {
722         struct iwl_priv *priv = (struct iwl_priv *)data;
723
724         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
725                 return;
726
727         /* dont send host command if rf-kill is on */
728         if (!iwl_is_ready_rf(priv))
729                 return;
730
731         iwl_send_statistics_request(priv, CMD_ASYNC, false);
732 }
733
734
735 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
736                                         u32 start_idx, u32 num_events,
737                                         u32 mode)
738 {
739         u32 i;
740         u32 ptr;        /* SRAM byte address of log data */
741         u32 ev, time, data; /* event log data */
742         unsigned long reg_flags;
743
744         if (mode == 0)
745                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
746         else
747                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
748
749         /* Make sure device is powered up for SRAM reads */
750         spin_lock_irqsave(&priv->reg_lock, reg_flags);
751         if (iwl_grab_nic_access(priv)) {
752                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
753                 return;
754         }
755
756         /* Set starting address; reads will auto-increment */
757         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
758         rmb();
759
760         /*
761          * "time" is actually "data" for mode 0 (no timestamp).
762          * place event id # at far right for easier visual parsing.
763          */
764         for (i = 0; i < num_events; i++) {
765                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
766                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
767                 if (mode == 0) {
768                         trace_iwlwifi_dev_ucode_cont_event(priv,
769                                                         0, time, ev);
770                 } else {
771                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
772                         trace_iwlwifi_dev_ucode_cont_event(priv,
773                                                 time, data, ev);
774                 }
775         }
776         /* Allow device to power down */
777         iwl_release_nic_access(priv);
778         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
779 }
780
781 static void iwl_continuous_event_trace(struct iwl_priv *priv)
782 {
783         u32 capacity;   /* event log capacity in # entries */
784         u32 base;       /* SRAM byte address of event log header */
785         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
786         u32 num_wraps;  /* # times uCode wrapped to top of log */
787         u32 next_entry; /* index of next entry to be written by uCode */
788
789         if (priv->ucode_type == UCODE_INIT)
790                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
791         else
792                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
793         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
794                 capacity = iwl_read_targ_mem(priv, base);
795                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
796                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
797                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
798         } else
799                 return;
800
801         if (num_wraps == priv->event_log.num_wraps) {
802                 iwl_print_cont_event_trace(priv,
803                                        base, priv->event_log.next_entry,
804                                        next_entry - priv->event_log.next_entry,
805                                        mode);
806                 priv->event_log.non_wraps_count++;
807         } else {
808                 if ((num_wraps - priv->event_log.num_wraps) > 1)
809                         priv->event_log.wraps_more_count++;
810                 else
811                         priv->event_log.wraps_once_count++;
812                 trace_iwlwifi_dev_ucode_wrap_event(priv,
813                                 num_wraps - priv->event_log.num_wraps,
814                                 next_entry, priv->event_log.next_entry);
815                 if (next_entry < priv->event_log.next_entry) {
816                         iwl_print_cont_event_trace(priv, base,
817                                priv->event_log.next_entry,
818                                capacity - priv->event_log.next_entry,
819                                mode);
820
821                         iwl_print_cont_event_trace(priv, base, 0,
822                                 next_entry, mode);
823                 } else {
824                         iwl_print_cont_event_trace(priv, base,
825                                next_entry, capacity - next_entry,
826                                mode);
827
828                         iwl_print_cont_event_trace(priv, base, 0,
829                                 next_entry, mode);
830                 }
831         }
832         priv->event_log.num_wraps = num_wraps;
833         priv->event_log.next_entry = next_entry;
834 }
835
836 /**
837  * iwl_bg_ucode_trace - Timer callback to log ucode event
838  *
839  * The timer is continually set to execute every
840  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
841  * this function is to perform continuous uCode event logging operation
842  * if enabled
843  */
844 static void iwl_bg_ucode_trace(unsigned long data)
845 {
846         struct iwl_priv *priv = (struct iwl_priv *)data;
847
848         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
849                 return;
850
851         if (priv->event_log.ucode_trace) {
852                 iwl_continuous_event_trace(priv);
853                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
854                 mod_timer(&priv->ucode_trace,
855                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
856         }
857 }
858
859 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
860                                 struct iwl_rx_mem_buffer *rxb)
861 {
862         struct iwl_rx_packet *pkt = rxb_addr(rxb);
863         struct iwl4965_beacon_notif *beacon =
864                 (struct iwl4965_beacon_notif *)pkt->u.raw;
865 #ifdef CONFIG_IWLWIFI_DEBUG
866         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
867
868         IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
869                 "tsf %d %d rate %d\n",
870                 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
871                 beacon->beacon_notify_hdr.failure_frame,
872                 le32_to_cpu(beacon->ibss_mgr_status),
873                 le32_to_cpu(beacon->high_tsf),
874                 le32_to_cpu(beacon->low_tsf), rate);
875 #endif
876
877         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
878
879         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
880                 queue_work(priv->workqueue, &priv->beacon_update);
881 }
882
883 /* Handle notification from uCode that card's power state is changing
884  * due to software, hardware, or critical temperature RFKILL */
885 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
886                                     struct iwl_rx_mem_buffer *rxb)
887 {
888         struct iwl_rx_packet *pkt = rxb_addr(rxb);
889         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
890         unsigned long status = priv->status;
891
892         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
893                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
894                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
895                           (flags & CT_CARD_DISABLED) ?
896                           "Reached" : "Not reached");
897
898         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
899                      CT_CARD_DISABLED)) {
900
901                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
902                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
903
904                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
905                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
906
907                 if (!(flags & RXON_CARD_DISABLED)) {
908                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
909                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
910                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
911                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
912                 }
913                 if (flags & CT_CARD_DISABLED)
914                         iwl_tt_enter_ct_kill(priv);
915         }
916         if (!(flags & CT_CARD_DISABLED))
917                 iwl_tt_exit_ct_kill(priv);
918
919         if (flags & HW_CARD_DISABLED)
920                 set_bit(STATUS_RF_KILL_HW, &priv->status);
921         else
922                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
923
924
925         if (!(flags & RXON_CARD_DISABLED))
926                 iwl_scan_cancel(priv);
927
928         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
929              test_bit(STATUS_RF_KILL_HW, &priv->status)))
930                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
931                         test_bit(STATUS_RF_KILL_HW, &priv->status));
932         else
933                 wake_up_interruptible(&priv->wait_command_queue);
934 }
935
936 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
937 {
938         if (src == IWL_PWR_SRC_VAUX) {
939                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
940                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
941                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
942                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
943         } else {
944                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
945                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
946                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
947         }
948
949         return 0;
950 }
951
952 static void iwl_bg_tx_flush(struct work_struct *work)
953 {
954         struct iwl_priv *priv =
955                 container_of(work, struct iwl_priv, tx_flush);
956
957         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
958                 return;
959
960         /* do nothing if rf-kill is on */
961         if (!iwl_is_ready_rf(priv))
962                 return;
963
964         if (priv->cfg->ops->lib->txfifo_flush) {
965                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
966                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
967         }
968 }
969
970 /**
971  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
972  *
973  * Setup the RX handlers for each of the reply types sent from the uCode
974  * to the host.
975  *
976  * This function chains into the hardware specific files for them to setup
977  * any hardware specific handlers as well.
978  */
979 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
980 {
981         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
982         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
983         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
984         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
985                         iwl_rx_spectrum_measure_notif;
986         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
987         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
988             iwl_rx_pm_debug_statistics_notif;
989         priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
990
991         /*
992          * The same handler is used for both the REPLY to a discrete
993          * statistics request from the host as well as for the periodic
994          * statistics notifications (after received beacons) from the uCode.
995          */
996         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
997         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
998
999         iwl_setup_rx_scan_handlers(priv);
1000
1001         /* status change handler */
1002         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
1003
1004         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
1005             iwl_rx_missed_beacon_notif;
1006         /* Rx handlers */
1007         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
1008         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
1009         /* block ack */
1010         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
1011         /* Set up hardware specific Rx handlers */
1012         priv->cfg->ops->lib->rx_handler_setup(priv);
1013 }
1014
1015 /**
1016  * iwl_rx_handle - Main entry function for receiving responses from uCode
1017  *
1018  * Uses the priv->rx_handlers callback function array to invoke
1019  * the appropriate handlers, including command responses,
1020  * frame-received notifications, and other notifications.
1021  */
1022 void iwl_rx_handle(struct iwl_priv *priv)
1023 {
1024         struct iwl_rx_mem_buffer *rxb;
1025         struct iwl_rx_packet *pkt;
1026         struct iwl_rx_queue *rxq = &priv->rxq;
1027         u32 r, i;
1028         int reclaim;
1029         unsigned long flags;
1030         u8 fill_rx = 0;
1031         u32 count = 8;
1032         int total_empty;
1033
1034         /* uCode's read index (stored in shared DRAM) indicates the last Rx
1035          * buffer that the driver may process (last buffer filled by ucode). */
1036         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
1037         i = rxq->read;
1038
1039         /* Rx interrupt, but nothing sent from uCode */
1040         if (i == r)
1041                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
1042
1043         /* calculate total frames need to be restock after handling RX */
1044         total_empty = r - rxq->write_actual;
1045         if (total_empty < 0)
1046                 total_empty += RX_QUEUE_SIZE;
1047
1048         if (total_empty > (RX_QUEUE_SIZE / 2))
1049                 fill_rx = 1;
1050
1051         while (i != r) {
1052                 int len;
1053
1054                 rxb = rxq->queue[i];
1055
1056                 /* If an RXB doesn't have a Rx queue slot associated with it,
1057                  * then a bug has been introduced in the queue refilling
1058                  * routines -- catch it here */
1059                 BUG_ON(rxb == NULL);
1060
1061                 rxq->queue[i] = NULL;
1062
1063                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1064                                PAGE_SIZE << priv->hw_params.rx_page_order,
1065                                PCI_DMA_FROMDEVICE);
1066                 pkt = rxb_addr(rxb);
1067
1068                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1069                 len += sizeof(u32); /* account for status word */
1070                 trace_iwlwifi_dev_rx(priv, pkt, len);
1071
1072                 /* Reclaim a command buffer only if this packet is a response
1073                  *   to a (driver-originated) command.
1074                  * If the packet (e.g. Rx frame) originated from uCode,
1075                  *   there is no command buffer to reclaim.
1076                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1077                  *   but apparently a few don't get set; catch them here. */
1078                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1079                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
1080                         (pkt->hdr.cmd != REPLY_RX) &&
1081                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
1082                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
1083                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1084                         (pkt->hdr.cmd != REPLY_TX);
1085
1086                 /* Based on type of command response or notification,
1087                  *   handle those that need handling via function in
1088                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
1089                 if (priv->rx_handlers[pkt->hdr.cmd]) {
1090                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
1091                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1092                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
1093                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
1094                 } else {
1095                         /* No handling needed */
1096                         IWL_DEBUG_RX(priv,
1097                                 "r %d i %d No handler needed for %s, 0x%02x\n",
1098                                 r, i, get_cmd_string(pkt->hdr.cmd),
1099                                 pkt->hdr.cmd);
1100                 }
1101
1102                 /*
1103                  * XXX: After here, we should always check rxb->page
1104                  * against NULL before touching it or its virtual
1105                  * memory (pkt). Because some rx_handler might have
1106                  * already taken or freed the pages.
1107                  */
1108
1109                 if (reclaim) {
1110                         /* Invoke any callbacks, transfer the buffer to caller,
1111                          * and fire off the (possibly) blocking iwl_send_cmd()
1112                          * as we reclaim the driver command queue */
1113                         if (rxb->page)
1114                                 iwl_tx_cmd_complete(priv, rxb);
1115                         else
1116                                 IWL_WARN(priv, "Claim null rxb?\n");
1117                 }
1118
1119                 /* Reuse the page if possible. For notification packets and
1120                  * SKBs that fail to Rx correctly, add them back into the
1121                  * rx_free list for reuse later. */
1122                 spin_lock_irqsave(&rxq->lock, flags);
1123                 if (rxb->page != NULL) {
1124                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1125                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1126                                 PCI_DMA_FROMDEVICE);
1127                         list_add_tail(&rxb->list, &rxq->rx_free);
1128                         rxq->free_count++;
1129                 } else
1130                         list_add_tail(&rxb->list, &rxq->rx_used);
1131
1132                 spin_unlock_irqrestore(&rxq->lock, flags);
1133
1134                 i = (i + 1) & RX_QUEUE_MASK;
1135                 /* If there are a lot of unused frames,
1136                  * restock the Rx queue so ucode wont assert. */
1137                 if (fill_rx) {
1138                         count++;
1139                         if (count >= 8) {
1140                                 rxq->read = i;
1141                                 iwlagn_rx_replenish_now(priv);
1142                                 count = 0;
1143                         }
1144                 }
1145         }
1146
1147         /* Backtrack one entry */
1148         rxq->read = i;
1149         if (fill_rx)
1150                 iwlagn_rx_replenish_now(priv);
1151         else
1152                 iwlagn_rx_queue_restock(priv);
1153 }
1154
1155 /* call this function to flush any scheduled tasklet */
1156 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1157 {
1158         /* wait to make sure we flush pending tasklet*/
1159         synchronize_irq(priv->pci_dev->irq);
1160         tasklet_kill(&priv->irq_tasklet);
1161 }
1162
1163 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1164 {
1165         u32 inta, handled = 0;
1166         u32 inta_fh;
1167         unsigned long flags;
1168         u32 i;
1169 #ifdef CONFIG_IWLWIFI_DEBUG
1170         u32 inta_mask;
1171 #endif
1172
1173         spin_lock_irqsave(&priv->lock, flags);
1174
1175         /* Ack/clear/reset pending uCode interrupts.
1176          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1177          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1178         inta = iwl_read32(priv, CSR_INT);
1179         iwl_write32(priv, CSR_INT, inta);
1180
1181         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1182          * Any new interrupts that happen after this, either while we're
1183          * in this tasklet, or later, will show up in next ISR/tasklet. */
1184         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1185         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1186
1187 #ifdef CONFIG_IWLWIFI_DEBUG
1188         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1189                 /* just for debug */
1190                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1191                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1192                               inta, inta_mask, inta_fh);
1193         }
1194 #endif
1195
1196         spin_unlock_irqrestore(&priv->lock, flags);
1197
1198         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1199          * atomic, make sure that inta covers all the interrupts that
1200          * we've discovered, even if FH interrupt came in just after
1201          * reading CSR_INT. */
1202         if (inta_fh & CSR49_FH_INT_RX_MASK)
1203                 inta |= CSR_INT_BIT_FH_RX;
1204         if (inta_fh & CSR49_FH_INT_TX_MASK)
1205                 inta |= CSR_INT_BIT_FH_TX;
1206
1207         /* Now service all interrupt bits discovered above. */
1208         if (inta & CSR_INT_BIT_HW_ERR) {
1209                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1210
1211                 /* Tell the device to stop sending interrupts */
1212                 iwl_disable_interrupts(priv);
1213
1214                 priv->isr_stats.hw++;
1215                 iwl_irq_handle_error(priv);
1216
1217                 handled |= CSR_INT_BIT_HW_ERR;
1218
1219                 return;
1220         }
1221
1222 #ifdef CONFIG_IWLWIFI_DEBUG
1223         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1224                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1225                 if (inta & CSR_INT_BIT_SCD) {
1226                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1227                                       "the frame/frames.\n");
1228                         priv->isr_stats.sch++;
1229                 }
1230
1231                 /* Alive notification via Rx interrupt will do the real work */
1232                 if (inta & CSR_INT_BIT_ALIVE) {
1233                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1234                         priv->isr_stats.alive++;
1235                 }
1236         }
1237 #endif
1238         /* Safely ignore these bits for debug checks below */
1239         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1240
1241         /* HW RF KILL switch toggled */
1242         if (inta & CSR_INT_BIT_RF_KILL) {
1243                 int hw_rf_kill = 0;
1244                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1245                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1246                         hw_rf_kill = 1;
1247
1248                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1249                                 hw_rf_kill ? "disable radio" : "enable radio");
1250
1251                 priv->isr_stats.rfkill++;
1252
1253                 /* driver only loads ucode once setting the interface up.
1254                  * the driver allows loading the ucode even if the radio
1255                  * is killed. Hence update the killswitch state here. The
1256                  * rfkill handler will care about restarting if needed.
1257                  */
1258                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1259                         if (hw_rf_kill)
1260                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1261                         else
1262                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1263                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1264                 }
1265
1266                 handled |= CSR_INT_BIT_RF_KILL;
1267         }
1268
1269         /* Chip got too hot and stopped itself */
1270         if (inta & CSR_INT_BIT_CT_KILL) {
1271                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1272                 priv->isr_stats.ctkill++;
1273                 handled |= CSR_INT_BIT_CT_KILL;
1274         }
1275
1276         /* Error detected by uCode */
1277         if (inta & CSR_INT_BIT_SW_ERR) {
1278                 IWL_ERR(priv, "Microcode SW error detected. "
1279                         " Restarting 0x%X.\n", inta);
1280                 priv->isr_stats.sw++;
1281                 iwl_irq_handle_error(priv);
1282                 handled |= CSR_INT_BIT_SW_ERR;
1283         }
1284
1285         /*
1286          * uCode wakes up after power-down sleep.
1287          * Tell device about any new tx or host commands enqueued,
1288          * and about any Rx buffers made available while asleep.
1289          */
1290         if (inta & CSR_INT_BIT_WAKEUP) {
1291                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1292                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1293                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1294                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1295                 priv->isr_stats.wakeup++;
1296                 handled |= CSR_INT_BIT_WAKEUP;
1297         }
1298
1299         /* All uCode command responses, including Tx command responses,
1300          * Rx "responses" (frame-received notification), and other
1301          * notifications from uCode come through here*/
1302         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1303                 iwl_rx_handle(priv);
1304                 priv->isr_stats.rx++;
1305                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1306         }
1307
1308         /* This "Tx" DMA channel is used only for loading uCode */
1309         if (inta & CSR_INT_BIT_FH_TX) {
1310                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1311                 priv->isr_stats.tx++;
1312                 handled |= CSR_INT_BIT_FH_TX;
1313                 /* Wake up uCode load routine, now that load is complete */
1314                 priv->ucode_write_complete = 1;
1315                 wake_up_interruptible(&priv->wait_command_queue);
1316         }
1317
1318         if (inta & ~handled) {
1319                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1320                 priv->isr_stats.unhandled++;
1321         }
1322
1323         if (inta & ~(priv->inta_mask)) {
1324                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1325                          inta & ~priv->inta_mask);
1326                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1327         }
1328
1329         /* Re-enable all interrupts */
1330         /* only Re-enable if diabled by irq */
1331         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1332                 iwl_enable_interrupts(priv);
1333
1334 #ifdef CONFIG_IWLWIFI_DEBUG
1335         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1336                 inta = iwl_read32(priv, CSR_INT);
1337                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1338                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1339                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1340                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1341         }
1342 #endif
1343 }
1344
1345 /* tasklet for iwlagn interrupt */
1346 static void iwl_irq_tasklet(struct iwl_priv *priv)
1347 {
1348         u32 inta = 0;
1349         u32 handled = 0;
1350         unsigned long flags;
1351         u32 i;
1352 #ifdef CONFIG_IWLWIFI_DEBUG
1353         u32 inta_mask;
1354 #endif
1355
1356         spin_lock_irqsave(&priv->lock, flags);
1357
1358         /* Ack/clear/reset pending uCode interrupts.
1359          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1360          */
1361         /* There is a hardware bug in the interrupt mask function that some
1362          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1363          * they are disabled in the CSR_INT_MASK register. Furthermore the
1364          * ICT interrupt handling mechanism has another bug that might cause
1365          * these unmasked interrupts fail to be detected. We workaround the
1366          * hardware bugs here by ACKing all the possible interrupts so that
1367          * interrupt coalescing can still be achieved.
1368          */
1369         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1370
1371         inta = priv->_agn.inta;
1372
1373 #ifdef CONFIG_IWLWIFI_DEBUG
1374         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1375                 /* just for debug */
1376                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1377                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1378                                 inta, inta_mask);
1379         }
1380 #endif
1381
1382         spin_unlock_irqrestore(&priv->lock, flags);
1383
1384         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1385         priv->_agn.inta = 0;
1386
1387         /* Now service all interrupt bits discovered above. */
1388         if (inta & CSR_INT_BIT_HW_ERR) {
1389                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1390
1391                 /* Tell the device to stop sending interrupts */
1392                 iwl_disable_interrupts(priv);
1393
1394                 priv->isr_stats.hw++;
1395                 iwl_irq_handle_error(priv);
1396
1397                 handled |= CSR_INT_BIT_HW_ERR;
1398
1399                 return;
1400         }
1401
1402 #ifdef CONFIG_IWLWIFI_DEBUG
1403         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1404                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1405                 if (inta & CSR_INT_BIT_SCD) {
1406                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1407                                       "the frame/frames.\n");
1408                         priv->isr_stats.sch++;
1409                 }
1410
1411                 /* Alive notification via Rx interrupt will do the real work */
1412                 if (inta & CSR_INT_BIT_ALIVE) {
1413                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1414                         priv->isr_stats.alive++;
1415                 }
1416         }
1417 #endif
1418         /* Safely ignore these bits for debug checks below */
1419         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1420
1421         /* HW RF KILL switch toggled */
1422         if (inta & CSR_INT_BIT_RF_KILL) {
1423                 int hw_rf_kill = 0;
1424                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1425                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1426                         hw_rf_kill = 1;
1427
1428                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1429                                 hw_rf_kill ? "disable radio" : "enable radio");
1430
1431                 priv->isr_stats.rfkill++;
1432
1433                 /* driver only loads ucode once setting the interface up.
1434                  * the driver allows loading the ucode even if the radio
1435                  * is killed. Hence update the killswitch state here. The
1436                  * rfkill handler will care about restarting if needed.
1437                  */
1438                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1439                         if (hw_rf_kill)
1440                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1441                         else
1442                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1443                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1444                 }
1445
1446                 handled |= CSR_INT_BIT_RF_KILL;
1447         }
1448
1449         /* Chip got too hot and stopped itself */
1450         if (inta & CSR_INT_BIT_CT_KILL) {
1451                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1452                 priv->isr_stats.ctkill++;
1453                 handled |= CSR_INT_BIT_CT_KILL;
1454         }
1455
1456         /* Error detected by uCode */
1457         if (inta & CSR_INT_BIT_SW_ERR) {
1458                 IWL_ERR(priv, "Microcode SW error detected. "
1459                         " Restarting 0x%X.\n", inta);
1460                 priv->isr_stats.sw++;
1461                 iwl_irq_handle_error(priv);
1462                 handled |= CSR_INT_BIT_SW_ERR;
1463         }
1464
1465         /* uCode wakes up after power-down sleep */
1466         if (inta & CSR_INT_BIT_WAKEUP) {
1467                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1468                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1469                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1470                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1471
1472                 priv->isr_stats.wakeup++;
1473
1474                 handled |= CSR_INT_BIT_WAKEUP;
1475         }
1476
1477         /* All uCode command responses, including Tx command responses,
1478          * Rx "responses" (frame-received notification), and other
1479          * notifications from uCode come through here*/
1480         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1481                         CSR_INT_BIT_RX_PERIODIC)) {
1482                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1483                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1484                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1485                         iwl_write32(priv, CSR_FH_INT_STATUS,
1486                                         CSR49_FH_INT_RX_MASK);
1487                 }
1488                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1489                         handled |= CSR_INT_BIT_RX_PERIODIC;
1490                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1491                 }
1492                 /* Sending RX interrupt require many steps to be done in the
1493                  * the device:
1494                  * 1- write interrupt to current index in ICT table.
1495                  * 2- dma RX frame.
1496                  * 3- update RX shared data to indicate last write index.
1497                  * 4- send interrupt.
1498                  * This could lead to RX race, driver could receive RX interrupt
1499                  * but the shared data changes does not reflect this;
1500                  * periodic interrupt will detect any dangling Rx activity.
1501                  */
1502
1503                 /* Disable periodic interrupt; we use it as just a one-shot. */
1504                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1505                             CSR_INT_PERIODIC_DIS);
1506                 iwl_rx_handle(priv);
1507
1508                 /*
1509                  * Enable periodic interrupt in 8 msec only if we received
1510                  * real RX interrupt (instead of just periodic int), to catch
1511                  * any dangling Rx interrupt.  If it was just the periodic
1512                  * interrupt, there was no dangling Rx activity, and no need
1513                  * to extend the periodic interrupt; one-shot is enough.
1514                  */
1515                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1516                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1517                                     CSR_INT_PERIODIC_ENA);
1518
1519                 priv->isr_stats.rx++;
1520         }
1521
1522         /* This "Tx" DMA channel is used only for loading uCode */
1523         if (inta & CSR_INT_BIT_FH_TX) {
1524                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1525                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1526                 priv->isr_stats.tx++;
1527                 handled |= CSR_INT_BIT_FH_TX;
1528                 /* Wake up uCode load routine, now that load is complete */
1529                 priv->ucode_write_complete = 1;
1530                 wake_up_interruptible(&priv->wait_command_queue);
1531         }
1532
1533         if (inta & ~handled) {
1534                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1535                 priv->isr_stats.unhandled++;
1536         }
1537
1538         if (inta & ~(priv->inta_mask)) {
1539                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1540                          inta & ~priv->inta_mask);
1541         }
1542
1543         /* Re-enable all interrupts */
1544         /* only Re-enable if diabled by irq */
1545         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1546                 iwl_enable_interrupts(priv);
1547 }
1548
1549 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1550 #define ACK_CNT_RATIO (50)
1551 #define BA_TIMEOUT_CNT (5)
1552 #define BA_TIMEOUT_MAX (16)
1553
1554 /**
1555  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1556  *
1557  * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1558  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1559  * operation state.
1560  */
1561 bool iwl_good_ack_health(struct iwl_priv *priv,
1562                                 struct iwl_rx_packet *pkt)
1563 {
1564         bool rc = true;
1565         int actual_ack_cnt_delta, expected_ack_cnt_delta;
1566         int ba_timeout_delta;
1567
1568         actual_ack_cnt_delta =
1569                 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1570                 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1571         expected_ack_cnt_delta =
1572                 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1573                 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1574         ba_timeout_delta =
1575                 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1576                 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1577         if ((priv->_agn.agg_tids_count > 0) &&
1578             (expected_ack_cnt_delta > 0) &&
1579             (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1580                 < ACK_CNT_RATIO) &&
1581             (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1582                 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1583                                 " expected_ack_cnt = %d\n",
1584                                 actual_ack_cnt_delta, expected_ack_cnt_delta);
1585
1586 #ifdef CONFIG_IWLWIFI_DEBUGFS
1587                 /*
1588                  * This is ifdef'ed on DEBUGFS because otherwise the
1589                  * statistics aren't available. If DEBUGFS is set but
1590                  * DEBUG is not, these will just compile out.
1591                  */
1592                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1593                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1594                 IWL_DEBUG_RADIO(priv,
1595                                 "ack_or_ba_timeout_collision delta = %d\n",
1596                                 priv->_agn.delta_statistics.tx.
1597                                 ack_or_ba_timeout_collision);
1598 #endif
1599                 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1600                                 ba_timeout_delta);
1601                 if (!actual_ack_cnt_delta &&
1602                     (ba_timeout_delta >= BA_TIMEOUT_MAX))
1603                         rc = false;
1604         }
1605         return rc;
1606 }
1607
1608
1609 /*****************************************************************************
1610  *
1611  * sysfs attributes
1612  *
1613  *****************************************************************************/
1614
1615 #ifdef CONFIG_IWLWIFI_DEBUG
1616
1617 /*
1618  * The following adds a new attribute to the sysfs representation
1619  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1620  * used for controlling the debug level.
1621  *
1622  * See the level definitions in iwl for details.
1623  *
1624  * The debug_level being managed using sysfs below is a per device debug
1625  * level that is used instead of the global debug level if it (the per
1626  * device debug level) is set.
1627  */
1628 static ssize_t show_debug_level(struct device *d,
1629                                 struct device_attribute *attr, char *buf)
1630 {
1631         struct iwl_priv *priv = dev_get_drvdata(d);
1632         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1633 }
1634 static ssize_t store_debug_level(struct device *d,
1635                                 struct device_attribute *attr,
1636                                  const char *buf, size_t count)
1637 {
1638         struct iwl_priv *priv = dev_get_drvdata(d);
1639         unsigned long val;
1640         int ret;
1641
1642         ret = strict_strtoul(buf, 0, &val);
1643         if (ret)
1644                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1645         else {
1646                 priv->debug_level = val;
1647                 if (iwl_alloc_traffic_mem(priv))
1648                         IWL_ERR(priv,
1649                                 "Not enough memory to generate traffic log\n");
1650         }
1651         return strnlen(buf, count);
1652 }
1653
1654 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1655                         show_debug_level, store_debug_level);
1656
1657
1658 #endif /* CONFIG_IWLWIFI_DEBUG */
1659
1660
1661 static ssize_t show_temperature(struct device *d,
1662                                 struct device_attribute *attr, char *buf)
1663 {
1664         struct iwl_priv *priv = dev_get_drvdata(d);
1665
1666         if (!iwl_is_alive(priv))
1667                 return -EAGAIN;
1668
1669         return sprintf(buf, "%d\n", priv->temperature);
1670 }
1671
1672 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1673
1674 static ssize_t show_tx_power(struct device *d,
1675                              struct device_attribute *attr, char *buf)
1676 {
1677         struct iwl_priv *priv = dev_get_drvdata(d);
1678
1679         if (!iwl_is_ready_rf(priv))
1680                 return sprintf(buf, "off\n");
1681         else
1682                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1683 }
1684
1685 static ssize_t store_tx_power(struct device *d,
1686                               struct device_attribute *attr,
1687                               const char *buf, size_t count)
1688 {
1689         struct iwl_priv *priv = dev_get_drvdata(d);
1690         unsigned long val;
1691         int ret;
1692
1693         ret = strict_strtoul(buf, 10, &val);
1694         if (ret)
1695                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1696         else {
1697                 ret = iwl_set_tx_power(priv, val, false);
1698                 if (ret)
1699                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1700                                 ret);
1701                 else
1702                         ret = count;
1703         }
1704         return ret;
1705 }
1706
1707 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1708
1709 static struct attribute *iwl_sysfs_entries[] = {
1710         &dev_attr_temperature.attr,
1711         &dev_attr_tx_power.attr,
1712 #ifdef CONFIG_IWLWIFI_DEBUG
1713         &dev_attr_debug_level.attr,
1714 #endif
1715         NULL
1716 };
1717
1718 static struct attribute_group iwl_attribute_group = {
1719         .name = NULL,           /* put in device directory */
1720         .attrs = iwl_sysfs_entries,
1721 };
1722
1723 /******************************************************************************
1724  *
1725  * uCode download functions
1726  *
1727  ******************************************************************************/
1728
1729 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1730 {
1731         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1732         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1733         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1734         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1735         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1736         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1737 }
1738
1739 static void iwl_nic_start(struct iwl_priv *priv)
1740 {
1741         /* Remove all resets to allow NIC to operate */
1742         iwl_write32(priv, CSR_RESET, 0);
1743 }
1744
1745 struct iwlagn_ucode_capabilities {
1746         u32 max_probe_length;
1747         u32 standard_phy_calibration_size;
1748         bool pan;
1749 };
1750
1751 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1752 static int iwl_mac_setup_register(struct iwl_priv *priv,
1753                                   struct iwlagn_ucode_capabilities *capa);
1754
1755 #define UCODE_EXPERIMENTAL_INDEX        100
1756 #define UCODE_EXPERIMENTAL_TAG          "exp"
1757
1758 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1759 {
1760         const char *name_pre = priv->cfg->fw_name_pre;
1761         char tag[8];
1762
1763         if (first) {
1764 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1765                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1766                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1767         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1768 #endif
1769                 priv->fw_index = priv->cfg->ucode_api_max;
1770                 sprintf(tag, "%d", priv->fw_index);
1771         } else {
1772                 priv->fw_index--;
1773                 sprintf(tag, "%d", priv->fw_index);
1774         }
1775
1776         if (priv->fw_index < priv->cfg->ucode_api_min) {
1777                 IWL_ERR(priv, "no suitable firmware found!\n");
1778                 return -ENOENT;
1779         }
1780
1781         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1782
1783         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1784                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1785                                 ? "EXPERIMENTAL " : "",
1786                        priv->firmware_name);
1787
1788         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1789                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1790                                        iwl_ucode_callback);
1791 }
1792
1793 struct iwlagn_firmware_pieces {
1794         const void *inst, *data, *init, *init_data, *boot;
1795         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1796
1797         u32 build;
1798
1799         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1800         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1801 };
1802
1803 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1804                                        const struct firmware *ucode_raw,
1805                                        struct iwlagn_firmware_pieces *pieces)
1806 {
1807         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1808         u32 api_ver, hdr_size;
1809         const u8 *src;
1810
1811         priv->ucode_ver = le32_to_cpu(ucode->ver);
1812         api_ver = IWL_UCODE_API(priv->ucode_ver);
1813
1814         switch (api_ver) {
1815         default:
1816                 /*
1817                  * 4965 doesn't revision the firmware file format
1818                  * along with the API version, it always uses v1
1819                  * file format.
1820                  */
1821                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1822                                 CSR_HW_REV_TYPE_4965) {
1823                         hdr_size = 28;
1824                         if (ucode_raw->size < hdr_size) {
1825                                 IWL_ERR(priv, "File size too small!\n");
1826                                 return -EINVAL;
1827                         }
1828                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1829                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1830                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1831                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1832                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1833                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1834                         src = ucode->u.v2.data;
1835                         break;
1836                 }
1837                 /* fall through for 4965 */
1838         case 0:
1839         case 1:
1840         case 2:
1841                 hdr_size = 24;
1842                 if (ucode_raw->size < hdr_size) {
1843                         IWL_ERR(priv, "File size too small!\n");
1844                         return -EINVAL;
1845                 }
1846                 pieces->build = 0;
1847                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1848                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1849                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1850                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1851                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1852                 src = ucode->u.v1.data;
1853                 break;
1854         }
1855
1856         /* Verify size of file vs. image size info in file's header */
1857         if (ucode_raw->size != hdr_size + pieces->inst_size +
1858                                 pieces->data_size + pieces->init_size +
1859                                 pieces->init_data_size + pieces->boot_size) {
1860
1861                 IWL_ERR(priv,
1862                         "uCode file size %d does not match expected size\n",
1863                         (int)ucode_raw->size);
1864                 return -EINVAL;
1865         }
1866
1867         pieces->inst = src;
1868         src += pieces->inst_size;
1869         pieces->data = src;
1870         src += pieces->data_size;
1871         pieces->init = src;
1872         src += pieces->init_size;
1873         pieces->init_data = src;
1874         src += pieces->init_data_size;
1875         pieces->boot = src;
1876         src += pieces->boot_size;
1877
1878         return 0;
1879 }
1880
1881 static int iwlagn_wanted_ucode_alternative = 1;
1882
1883 static int iwlagn_load_firmware(struct iwl_priv *priv,
1884                                 const struct firmware *ucode_raw,
1885                                 struct iwlagn_firmware_pieces *pieces,
1886                                 struct iwlagn_ucode_capabilities *capa)
1887 {
1888         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1889         struct iwl_ucode_tlv *tlv;
1890         size_t len = ucode_raw->size;
1891         const u8 *data;
1892         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1893         u64 alternatives;
1894         u32 tlv_len;
1895         enum iwl_ucode_tlv_type tlv_type;
1896         const u8 *tlv_data;
1897
1898         if (len < sizeof(*ucode)) {
1899                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1900                 return -EINVAL;
1901         }
1902
1903         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1904                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1905                         le32_to_cpu(ucode->magic));
1906                 return -EINVAL;
1907         }
1908
1909         /*
1910          * Check which alternatives are present, and "downgrade"
1911          * when the chosen alternative is not present, warning
1912          * the user when that happens. Some files may not have
1913          * any alternatives, so don't warn in that case.
1914          */
1915         alternatives = le64_to_cpu(ucode->alternatives);
1916         tmp = wanted_alternative;
1917         if (wanted_alternative > 63)
1918                 wanted_alternative = 63;
1919         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1920                 wanted_alternative--;
1921         if (wanted_alternative && wanted_alternative != tmp)
1922                 IWL_WARN(priv,
1923                          "uCode alternative %d not available, choosing %d\n",
1924                          tmp, wanted_alternative);
1925
1926         priv->ucode_ver = le32_to_cpu(ucode->ver);
1927         pieces->build = le32_to_cpu(ucode->build);
1928         data = ucode->data;
1929
1930         len -= sizeof(*ucode);
1931
1932         while (len >= sizeof(*tlv)) {
1933                 u16 tlv_alt;
1934
1935                 len -= sizeof(*tlv);
1936                 tlv = (void *)data;
1937
1938                 tlv_len = le32_to_cpu(tlv->length);
1939                 tlv_type = le16_to_cpu(tlv->type);
1940                 tlv_alt = le16_to_cpu(tlv->alternative);
1941                 tlv_data = tlv->data;
1942
1943                 if (len < tlv_len) {
1944                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1945                                 len, tlv_len);
1946                         return -EINVAL;
1947                 }
1948                 len -= ALIGN(tlv_len, 4);
1949                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1950
1951                 /*
1952                  * Alternative 0 is always valid.
1953                  *
1954                  * Skip alternative TLVs that are not selected.
1955                  */
1956                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1957                         continue;
1958
1959                 switch (tlv_type) {
1960                 case IWL_UCODE_TLV_INST:
1961                         pieces->inst = tlv_data;
1962                         pieces->inst_size = tlv_len;
1963                         break;
1964                 case IWL_UCODE_TLV_DATA:
1965                         pieces->data = tlv_data;
1966                         pieces->data_size = tlv_len;
1967                         break;
1968                 case IWL_UCODE_TLV_INIT:
1969                         pieces->init = tlv_data;
1970                         pieces->init_size = tlv_len;
1971                         break;
1972                 case IWL_UCODE_TLV_INIT_DATA:
1973                         pieces->init_data = tlv_data;
1974                         pieces->init_data_size = tlv_len;
1975                         break;
1976                 case IWL_UCODE_TLV_BOOT:
1977                         pieces->boot = tlv_data;
1978                         pieces->boot_size = tlv_len;
1979                         break;
1980                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1981                         if (tlv_len != sizeof(u32))
1982                                 goto invalid_tlv_len;
1983                         capa->max_probe_length =
1984                                         le32_to_cpup((__le32 *)tlv_data);
1985                         break;
1986                 case IWL_UCODE_TLV_PAN:
1987                         if (tlv_len)
1988                                 goto invalid_tlv_len;
1989                         capa->pan = true;
1990                         break;
1991                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1992                         if (tlv_len != sizeof(u32))
1993                                 goto invalid_tlv_len;
1994                         pieces->init_evtlog_ptr =
1995                                         le32_to_cpup((__le32 *)tlv_data);
1996                         break;
1997                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1998                         if (tlv_len != sizeof(u32))
1999                                 goto invalid_tlv_len;
2000                         pieces->init_evtlog_size =
2001                                         le32_to_cpup((__le32 *)tlv_data);
2002                         break;
2003                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
2004                         if (tlv_len != sizeof(u32))
2005                                 goto invalid_tlv_len;
2006                         pieces->init_errlog_ptr =
2007                                         le32_to_cpup((__le32 *)tlv_data);
2008                         break;
2009                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
2010                         if (tlv_len != sizeof(u32))
2011                                 goto invalid_tlv_len;
2012                         pieces->inst_evtlog_ptr =
2013                                         le32_to_cpup((__le32 *)tlv_data);
2014                         break;
2015                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
2016                         if (tlv_len != sizeof(u32))
2017                                 goto invalid_tlv_len;
2018                         pieces->inst_evtlog_size =
2019                                         le32_to_cpup((__le32 *)tlv_data);
2020                         break;
2021                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
2022                         if (tlv_len != sizeof(u32))
2023                                 goto invalid_tlv_len;
2024                         pieces->inst_errlog_ptr =
2025                                         le32_to_cpup((__le32 *)tlv_data);
2026                         break;
2027                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
2028                         if (tlv_len)
2029                                 goto invalid_tlv_len;
2030                         priv->enhance_sensitivity_table = true;
2031                         break;
2032                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
2033                         if (tlv_len != sizeof(u32))
2034                                 goto invalid_tlv_len;
2035                         capa->standard_phy_calibration_size =
2036                                         le32_to_cpup((__le32 *)tlv_data);
2037                         break;
2038                 default:
2039                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
2040                         break;
2041                 }
2042         }
2043
2044         if (len) {
2045                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2046                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
2047                 return -EINVAL;
2048         }
2049
2050         return 0;
2051
2052  invalid_tlv_len:
2053         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2054         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2055
2056         return -EINVAL;
2057 }
2058
2059 /**
2060  * iwl_ucode_callback - callback when firmware was loaded
2061  *
2062  * If loaded successfully, copies the firmware into buffers
2063  * for the card to fetch (via DMA).
2064  */
2065 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
2066 {
2067         struct iwl_priv *priv = context;
2068         struct iwl_ucode_header *ucode;
2069         int err;
2070         struct iwlagn_firmware_pieces pieces;
2071         const unsigned int api_max = priv->cfg->ucode_api_max;
2072         const unsigned int api_min = priv->cfg->ucode_api_min;
2073         u32 api_ver;
2074         char buildstr[25];
2075         u32 build;
2076         struct iwlagn_ucode_capabilities ucode_capa = {
2077                 .max_probe_length = 200,
2078                 .standard_phy_calibration_size =
2079                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
2080         };
2081
2082         memset(&pieces, 0, sizeof(pieces));
2083
2084         if (!ucode_raw) {
2085                 if (priv->fw_index <= priv->cfg->ucode_api_max)
2086                         IWL_ERR(priv,
2087                                 "request for firmware file '%s' failed.\n",
2088                                 priv->firmware_name);
2089                 goto try_again;
2090         }
2091
2092         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2093                        priv->firmware_name, ucode_raw->size);
2094
2095         /* Make sure that we got at least the API version number */
2096         if (ucode_raw->size < 4) {
2097                 IWL_ERR(priv, "File size way too small!\n");
2098                 goto try_again;
2099         }
2100
2101         /* Data from ucode file:  header followed by uCode images */
2102         ucode = (struct iwl_ucode_header *)ucode_raw->data;
2103
2104         if (ucode->ver)
2105                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2106         else
2107                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2108                                            &ucode_capa);
2109
2110         if (err)
2111                 goto try_again;
2112
2113         api_ver = IWL_UCODE_API(priv->ucode_ver);
2114         build = pieces.build;
2115
2116         /*
2117          * api_ver should match the api version forming part of the
2118          * firmware filename ... but we don't check for that and only rely
2119          * on the API version read from firmware header from here on forward
2120          */
2121         if (api_ver < api_min || api_ver > api_max) {
2122                 IWL_ERR(priv, "Driver unable to support your firmware API. "
2123                           "Driver supports v%u, firmware is v%u.\n",
2124                           api_max, api_ver);
2125                 goto try_again;
2126         }
2127
2128         if (api_ver != api_max)
2129                 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
2130                           "got v%u. New firmware can be obtained "
2131                           "from http://www.intellinuxwireless.org.\n",
2132                           api_max, api_ver);
2133
2134         if (build)
2135                 sprintf(buildstr, " build %u%s", build,
2136                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2137                                 ? " (EXP)" : "");
2138         else
2139                 buildstr[0] = '\0';
2140
2141         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2142                  IWL_UCODE_MAJOR(priv->ucode_ver),
2143                  IWL_UCODE_MINOR(priv->ucode_ver),
2144                  IWL_UCODE_API(priv->ucode_ver),
2145                  IWL_UCODE_SERIAL(priv->ucode_ver),
2146                  buildstr);
2147
2148         snprintf(priv->hw->wiphy->fw_version,
2149                  sizeof(priv->hw->wiphy->fw_version),
2150                  "%u.%u.%u.%u%s",
2151                  IWL_UCODE_MAJOR(priv->ucode_ver),
2152                  IWL_UCODE_MINOR(priv->ucode_ver),
2153                  IWL_UCODE_API(priv->ucode_ver),
2154                  IWL_UCODE_SERIAL(priv->ucode_ver),
2155                  buildstr);
2156
2157         /*
2158          * For any of the failures below (before allocating pci memory)
2159          * we will try to load a version with a smaller API -- maybe the
2160          * user just got a corrupted version of the latest API.
2161          */
2162
2163         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2164                        priv->ucode_ver);
2165         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2166                        pieces.inst_size);
2167         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2168                        pieces.data_size);
2169         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2170                        pieces.init_size);
2171         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2172                        pieces.init_data_size);
2173         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2174                        pieces.boot_size);
2175
2176         /* Verify that uCode images will fit in card's SRAM */
2177         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2178                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2179                         pieces.inst_size);
2180                 goto try_again;
2181         }
2182
2183         if (pieces.data_size > priv->hw_params.max_data_size) {
2184                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2185                         pieces.data_size);
2186                 goto try_again;
2187         }
2188
2189         if (pieces.init_size > priv->hw_params.max_inst_size) {
2190                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2191                         pieces.init_size);
2192                 goto try_again;
2193         }
2194
2195         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2196                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2197                         pieces.init_data_size);
2198                 goto try_again;
2199         }
2200
2201         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2202                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2203                         pieces.boot_size);
2204                 goto try_again;
2205         }
2206
2207         /* Allocate ucode buffers for card's bus-master loading ... */
2208
2209         /* Runtime instructions and 2 copies of data:
2210          * 1) unmodified from disk
2211          * 2) backup cache for save/restore during power-downs */
2212         priv->ucode_code.len = pieces.inst_size;
2213         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2214
2215         priv->ucode_data.len = pieces.data_size;
2216         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2217
2218         priv->ucode_data_backup.len = pieces.data_size;
2219         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2220
2221         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2222             !priv->ucode_data_backup.v_addr)
2223                 goto err_pci_alloc;
2224
2225         /* Initialization instructions and data */
2226         if (pieces.init_size && pieces.init_data_size) {
2227                 priv->ucode_init.len = pieces.init_size;
2228                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2229
2230                 priv->ucode_init_data.len = pieces.init_data_size;
2231                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2232
2233                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2234                         goto err_pci_alloc;
2235         }
2236
2237         /* Bootstrap (instructions only, no data) */
2238         if (pieces.boot_size) {
2239                 priv->ucode_boot.len = pieces.boot_size;
2240                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2241
2242                 if (!priv->ucode_boot.v_addr)
2243                         goto err_pci_alloc;
2244         }
2245
2246         /* Now that we can no longer fail, copy information */
2247
2248         /*
2249          * The (size - 16) / 12 formula is based on the information recorded
2250          * for each event, which is of mode 1 (including timestamp) for all
2251          * new microcodes that include this information.
2252          */
2253         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2254         if (pieces.init_evtlog_size)
2255                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2256         else
2257                 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2258         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2259         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2260         if (pieces.inst_evtlog_size)
2261                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2262         else
2263                 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2264         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2265
2266         if (ucode_capa.pan) {
2267                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2268                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2269         } else
2270                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2271
2272         /* Copy images into buffers for card's bus-master reads ... */
2273
2274         /* Runtime instructions (first block of data in file) */
2275         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2276                         pieces.inst_size);
2277         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2278
2279         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2280                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2281
2282         /*
2283          * Runtime data
2284          * NOTE:  Copy into backup buffer will be done in iwl_up()
2285          */
2286         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2287                         pieces.data_size);
2288         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2289         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2290
2291         /* Initialization instructions */
2292         if (pieces.init_size) {
2293                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2294                                 pieces.init_size);
2295                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2296         }
2297
2298         /* Initialization data */
2299         if (pieces.init_data_size) {
2300                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2301                                pieces.init_data_size);
2302                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2303                        pieces.init_data_size);
2304         }
2305
2306         /* Bootstrap instructions */
2307         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2308                         pieces.boot_size);
2309         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2310
2311         /*
2312          * figure out the offset of chain noise reset and gain commands
2313          * base on the size of standard phy calibration commands table size
2314          */
2315         if (ucode_capa.standard_phy_calibration_size >
2316             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2317                 ucode_capa.standard_phy_calibration_size =
2318                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2319
2320         priv->_agn.phy_calib_chain_noise_reset_cmd =
2321                 ucode_capa.standard_phy_calibration_size;
2322         priv->_agn.phy_calib_chain_noise_gain_cmd =
2323                 ucode_capa.standard_phy_calibration_size + 1;
2324
2325         /**************************************************
2326          * This is still part of probe() in a sense...
2327          *
2328          * 9. Setup and register with mac80211 and debugfs
2329          **************************************************/
2330         err = iwl_mac_setup_register(priv, &ucode_capa);
2331         if (err)
2332                 goto out_unbind;
2333
2334         err = iwl_dbgfs_register(priv, DRV_NAME);
2335         if (err)
2336                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2337
2338         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2339                                         &iwl_attribute_group);
2340         if (err) {
2341                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2342                 goto out_unbind;
2343         }
2344
2345         /* We have our copies now, allow OS release its copies */
2346         release_firmware(ucode_raw);
2347         complete(&priv->_agn.firmware_loading_complete);
2348         return;
2349
2350  try_again:
2351         /* try next, if any */
2352         if (iwl_request_firmware(priv, false))
2353                 goto out_unbind;
2354         release_firmware(ucode_raw);
2355         return;
2356
2357  err_pci_alloc:
2358         IWL_ERR(priv, "failed to allocate pci memory\n");
2359         iwl_dealloc_ucode_pci(priv);
2360  out_unbind:
2361         complete(&priv->_agn.firmware_loading_complete);
2362         device_release_driver(&priv->pci_dev->dev);
2363         release_firmware(ucode_raw);
2364 }
2365
2366 static const char *desc_lookup_text[] = {
2367         "OK",
2368         "FAIL",
2369         "BAD_PARAM",
2370         "BAD_CHECKSUM",
2371         "NMI_INTERRUPT_WDG",
2372         "SYSASSERT",
2373         "FATAL_ERROR",
2374         "BAD_COMMAND",
2375         "HW_ERROR_TUNE_LOCK",
2376         "HW_ERROR_TEMPERATURE",
2377         "ILLEGAL_CHAN_FREQ",
2378         "VCC_NOT_STABLE",
2379         "FH_ERROR",
2380         "NMI_INTERRUPT_HOST",
2381         "NMI_INTERRUPT_ACTION_PT",
2382         "NMI_INTERRUPT_UNKNOWN",
2383         "UCODE_VERSION_MISMATCH",
2384         "HW_ERROR_ABS_LOCK",
2385         "HW_ERROR_CAL_LOCK_FAIL",
2386         "NMI_INTERRUPT_INST_ACTION_PT",
2387         "NMI_INTERRUPT_DATA_ACTION_PT",
2388         "NMI_TRM_HW_ER",
2389         "NMI_INTERRUPT_TRM",
2390         "NMI_INTERRUPT_BREAK_POINT"
2391         "DEBUG_0",
2392         "DEBUG_1",
2393         "DEBUG_2",
2394         "DEBUG_3",
2395 };
2396
2397 static struct { char *name; u8 num; } advanced_lookup[] = {
2398         { "NMI_INTERRUPT_WDG", 0x34 },
2399         { "SYSASSERT", 0x35 },
2400         { "UCODE_VERSION_MISMATCH", 0x37 },
2401         { "BAD_COMMAND", 0x38 },
2402         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2403         { "FATAL_ERROR", 0x3D },
2404         { "NMI_TRM_HW_ERR", 0x46 },
2405         { "NMI_INTERRUPT_TRM", 0x4C },
2406         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2407         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2408         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2409         { "NMI_INTERRUPT_HOST", 0x66 },
2410         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2411         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2412         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2413         { "ADVANCED_SYSASSERT", 0 },
2414 };
2415
2416 static const char *desc_lookup(u32 num)
2417 {
2418         int i;
2419         int max = ARRAY_SIZE(desc_lookup_text);
2420
2421         if (num < max)
2422                 return desc_lookup_text[num];
2423
2424         max = ARRAY_SIZE(advanced_lookup) - 1;
2425         for (i = 0; i < max; i++) {
2426                 if (advanced_lookup[i].num == num)
2427                         break;;
2428         }
2429         return advanced_lookup[i].name;
2430 }
2431
2432 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2433 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2434
2435 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2436 {
2437         u32 data2, line;
2438         u32 desc, time, count, base, data1;
2439         u32 blink1, blink2, ilink1, ilink2;
2440         u32 pc, hcmd;
2441
2442         if (priv->ucode_type == UCODE_INIT) {
2443                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2444                 if (!base)
2445                         base = priv->_agn.init_errlog_ptr;
2446         } else {
2447                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2448                 if (!base)
2449                         base = priv->_agn.inst_errlog_ptr;
2450         }
2451
2452         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2453                 IWL_ERR(priv,
2454                         "Not valid error log pointer 0x%08X for %s uCode\n",
2455                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2456                 return;
2457         }
2458
2459         count = iwl_read_targ_mem(priv, base);
2460
2461         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2462                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2463                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2464                         priv->status, count);
2465         }
2466
2467         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2468         priv->isr_stats.err_code = desc;
2469         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2470         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2471         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2472         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2473         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2474         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2475         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2476         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2477         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2478         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2479
2480         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2481                                       blink1, blink2, ilink1, ilink2);
2482
2483         IWL_ERR(priv, "Desc                                  Time       "
2484                 "data1      data2      line\n");
2485         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2486                 desc_lookup(desc), desc, time, data1, data2, line);
2487         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2488         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2489                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2490 }
2491
2492 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2493
2494 /**
2495  * iwl_print_event_log - Dump error event log to syslog
2496  *
2497  */
2498 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2499                                u32 num_events, u32 mode,
2500                                int pos, char **buf, size_t bufsz)
2501 {
2502         u32 i;
2503         u32 base;       /* SRAM byte address of event log header */
2504         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2505         u32 ptr;        /* SRAM byte address of log data */
2506         u32 ev, time, data; /* event log data */
2507         unsigned long reg_flags;
2508
2509         if (num_events == 0)
2510                 return pos;
2511
2512         if (priv->ucode_type == UCODE_INIT) {
2513                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2514                 if (!base)
2515                         base = priv->_agn.init_evtlog_ptr;
2516         } else {
2517                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2518                 if (!base)
2519                         base = priv->_agn.inst_evtlog_ptr;
2520         }
2521
2522         if (mode == 0)
2523                 event_size = 2 * sizeof(u32);
2524         else
2525                 event_size = 3 * sizeof(u32);
2526
2527         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2528
2529         /* Make sure device is powered up for SRAM reads */
2530         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2531         iwl_grab_nic_access(priv);
2532
2533         /* Set starting address; reads will auto-increment */
2534         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2535         rmb();
2536
2537         /* "time" is actually "data" for mode 0 (no timestamp).
2538         * place event id # at far right for easier visual parsing. */
2539         for (i = 0; i < num_events; i++) {
2540                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2541                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2542                 if (mode == 0) {
2543                         /* data, ev */
2544                         if (bufsz) {
2545                                 pos += scnprintf(*buf + pos, bufsz - pos,
2546                                                 "EVT_LOG:0x%08x:%04u\n",
2547                                                 time, ev);
2548                         } else {
2549                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2550                                         time, ev);
2551                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2552                                         time, ev);
2553                         }
2554                 } else {
2555                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2556                         if (bufsz) {
2557                                 pos += scnprintf(*buf + pos, bufsz - pos,
2558                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2559                                                  time, data, ev);
2560                         } else {
2561                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2562                                         time, data, ev);
2563                                 trace_iwlwifi_dev_ucode_event(priv, time,
2564                                         data, ev);
2565                         }
2566                 }
2567         }
2568
2569         /* Allow device to power down */
2570         iwl_release_nic_access(priv);
2571         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2572         return pos;
2573 }
2574
2575 /**
2576  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2577  */
2578 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2579                                     u32 num_wraps, u32 next_entry,
2580                                     u32 size, u32 mode,
2581                                     int pos, char **buf, size_t bufsz)
2582 {
2583         /*
2584          * display the newest DEFAULT_LOG_ENTRIES entries
2585          * i.e the entries just before the next ont that uCode would fill.
2586          */
2587         if (num_wraps) {
2588                 if (next_entry < size) {
2589                         pos = iwl_print_event_log(priv,
2590                                                 capacity - (size - next_entry),
2591                                                 size - next_entry, mode,
2592                                                 pos, buf, bufsz);
2593                         pos = iwl_print_event_log(priv, 0,
2594                                                   next_entry, mode,
2595                                                   pos, buf, bufsz);
2596                 } else
2597                         pos = iwl_print_event_log(priv, next_entry - size,
2598                                                   size, mode, pos, buf, bufsz);
2599         } else {
2600                 if (next_entry < size) {
2601                         pos = iwl_print_event_log(priv, 0, next_entry,
2602                                                   mode, pos, buf, bufsz);
2603                 } else {
2604                         pos = iwl_print_event_log(priv, next_entry - size,
2605                                                   size, mode, pos, buf, bufsz);
2606                 }
2607         }
2608         return pos;
2609 }
2610
2611 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2612
2613 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2614                             char **buf, bool display)
2615 {
2616         u32 base;       /* SRAM byte address of event log header */
2617         u32 capacity;   /* event log capacity in # entries */
2618         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2619         u32 num_wraps;  /* # times uCode wrapped to top of log */
2620         u32 next_entry; /* index of next entry to be written by uCode */
2621         u32 size;       /* # entries that we'll print */
2622         u32 logsize;
2623         int pos = 0;
2624         size_t bufsz = 0;
2625
2626         if (priv->ucode_type == UCODE_INIT) {
2627                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2628                 logsize = priv->_agn.init_evtlog_size;
2629                 if (!base)
2630                         base = priv->_agn.init_evtlog_ptr;
2631         } else {
2632                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2633                 logsize = priv->_agn.inst_evtlog_size;
2634                 if (!base)
2635                         base = priv->_agn.inst_evtlog_ptr;
2636         }
2637
2638         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2639                 IWL_ERR(priv,
2640                         "Invalid event log pointer 0x%08X for %s uCode\n",
2641                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2642                 return -EINVAL;
2643         }
2644
2645         /* event log header */
2646         capacity = iwl_read_targ_mem(priv, base);
2647         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2648         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2649         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2650
2651         if (capacity > logsize) {
2652                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2653                         capacity, logsize);
2654                 capacity = logsize;
2655         }
2656
2657         if (next_entry > logsize) {
2658                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2659                         next_entry, logsize);
2660                 next_entry = logsize;
2661         }
2662
2663         size = num_wraps ? capacity : next_entry;
2664
2665         /* bail out if nothing in log */
2666         if (size == 0) {
2667                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2668                 return pos;
2669         }
2670
2671         /* enable/disable bt channel announcement */
2672         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2673
2674 #ifdef CONFIG_IWLWIFI_DEBUG
2675         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2676                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2677                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2678 #else
2679         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2680                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2681 #endif
2682         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2683                 size);
2684
2685 #ifdef CONFIG_IWLWIFI_DEBUG
2686         if (display) {
2687                 if (full_log)
2688                         bufsz = capacity * 48;
2689                 else
2690                         bufsz = size * 48;
2691                 *buf = kmalloc(bufsz, GFP_KERNEL);
2692                 if (!*buf)
2693                         return -ENOMEM;
2694         }
2695         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2696                 /*
2697                  * if uCode has wrapped back to top of log,
2698                  * start at the oldest entry,
2699                  * i.e the next one that uCode would fill.
2700                  */
2701                 if (num_wraps)
2702                         pos = iwl_print_event_log(priv, next_entry,
2703                                                 capacity - next_entry, mode,
2704                                                 pos, buf, bufsz);
2705                 /* (then/else) start at top of log */
2706                 pos = iwl_print_event_log(priv, 0,
2707                                           next_entry, mode, pos, buf, bufsz);
2708         } else
2709                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2710                                                 next_entry, size, mode,
2711                                                 pos, buf, bufsz);
2712 #else
2713         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2714                                         next_entry, size, mode,
2715                                         pos, buf, bufsz);
2716 #endif
2717         return pos;
2718 }
2719
2720 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2721 {
2722         struct iwl_ct_kill_config cmd;
2723         struct iwl_ct_kill_throttling_config adv_cmd;
2724         unsigned long flags;
2725         int ret = 0;
2726
2727         spin_lock_irqsave(&priv->lock, flags);
2728         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2729                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2730         spin_unlock_irqrestore(&priv->lock, flags);
2731         priv->thermal_throttle.ct_kill_toggle = false;
2732
2733         if (priv->cfg->support_ct_kill_exit) {
2734                 adv_cmd.critical_temperature_enter =
2735                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2736                 adv_cmd.critical_temperature_exit =
2737                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2738
2739                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2740                                        sizeof(adv_cmd), &adv_cmd);
2741                 if (ret)
2742                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2743                 else
2744                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2745                                         "succeeded, "
2746                                         "critical temperature enter is %d,"
2747                                         "exit is %d\n",
2748                                        priv->hw_params.ct_kill_threshold,
2749                                        priv->hw_params.ct_kill_exit_threshold);
2750         } else {
2751                 cmd.critical_temperature_R =
2752                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2753
2754                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2755                                        sizeof(cmd), &cmd);
2756                 if (ret)
2757                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2758                 else
2759                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2760                                         "succeeded, "
2761                                         "critical temperature is %d\n",
2762                                         priv->hw_params.ct_kill_threshold);
2763         }
2764 }
2765
2766 /**
2767  * iwl_alive_start - called after REPLY_ALIVE notification received
2768  *                   from protocol/runtime uCode (initialization uCode's
2769  *                   Alive gets handled by iwl_init_alive_start()).
2770  */
2771 static void iwl_alive_start(struct iwl_priv *priv)
2772 {
2773         int ret = 0;
2774         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2775
2776         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2777
2778         if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2779                 /* We had an error bringing up the hardware, so take it
2780                  * all the way back down so we can try again */
2781                 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2782                 goto restart;
2783         }
2784
2785         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2786          * This is a paranoid check, because we would not have gotten the
2787          * "runtime" alive if code weren't properly loaded.  */
2788         if (iwl_verify_ucode(priv)) {
2789                 /* Runtime instruction load was bad;
2790                  * take it all the way back down so we can try again */
2791                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2792                 goto restart;
2793         }
2794
2795         ret = priv->cfg->ops->lib->alive_notify(priv);
2796         if (ret) {
2797                 IWL_WARN(priv,
2798                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2799                 goto restart;
2800         }
2801
2802         /* After the ALIVE response, we can send host commands to the uCode */
2803         set_bit(STATUS_ALIVE, &priv->status);
2804
2805         if (priv->cfg->ops->lib->recover_from_tx_stall) {
2806                 /* Enable timer to monitor the driver queues */
2807                 mod_timer(&priv->monitor_recover,
2808                         jiffies +
2809                         msecs_to_jiffies(priv->cfg->monitor_recover_period));
2810         }
2811
2812         if (iwl_is_rfkill(priv))
2813                 return;
2814
2815         if (priv->cfg->advanced_bt_coexist) {
2816                 /* Configure Bluetooth device coexistence support */
2817                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2818                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2819                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2820                 priv->cfg->ops->hcmd->send_bt_config(priv);
2821                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2822                 if (bt_coex_active && priv->iw_mode != NL80211_IFTYPE_ADHOC)
2823                         iwlagn_send_prio_tbl(priv);
2824
2825                 /* FIXME: w/a to force change uCode BT state machine */
2826                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2827                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2828                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2829                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2830         }
2831         ieee80211_wake_queues(priv->hw);
2832
2833         priv->active_rate = IWL_RATES_MASK;
2834
2835         /* Configure Tx antenna selection based on H/W config */
2836         if (priv->cfg->ops->hcmd->set_tx_ant)
2837                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2838
2839         if (iwl_is_associated_ctx(ctx)) {
2840                 struct iwl_rxon_cmd *active_rxon =
2841                                 (struct iwl_rxon_cmd *)&ctx->active;
2842                 /* apply any changes in staging */
2843                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2844                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2845         } else {
2846                 struct iwl_rxon_context *tmp;
2847                 /* Initialize our rx_config data */
2848                 for_each_context(priv, tmp)
2849                         iwl_connection_init_rx_config(priv, tmp);
2850
2851                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2852                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2853         }
2854
2855         if (!priv->cfg->advanced_bt_coexist) {
2856                 /* Configure Bluetooth device coexistence support */
2857                 priv->cfg->ops->hcmd->send_bt_config(priv);
2858         }
2859
2860         iwl_reset_run_time_calib(priv);
2861
2862         /* Configure the adapter for unassociated operation */
2863         iwlcore_commit_rxon(priv, ctx);
2864
2865         /* At this point, the NIC is initialized and operational */
2866         iwl_rf_kill_ct_config(priv);
2867
2868         iwl_leds_init(priv);
2869
2870         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2871         set_bit(STATUS_READY, &priv->status);
2872         wake_up_interruptible(&priv->wait_command_queue);
2873
2874         iwl_power_update_mode(priv, true);
2875         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2876
2877
2878         return;
2879
2880  restart:
2881         queue_work(priv->workqueue, &priv->restart);
2882 }
2883
2884 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2885
2886 static void __iwl_down(struct iwl_priv *priv)
2887 {
2888         unsigned long flags;
2889         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2890
2891         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2892
2893         if (!exit_pending)
2894                 set_bit(STATUS_EXIT_PENDING, &priv->status);
2895
2896         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2897          * to prevent rearm timer */
2898         if (priv->cfg->ops->lib->recover_from_tx_stall)
2899                 del_timer_sync(&priv->monitor_recover);
2900
2901         iwl_clear_ucode_stations(priv, NULL);
2902         iwl_dealloc_bcast_stations(priv);
2903         iwl_clear_driver_stations(priv);
2904
2905         /* reset BT coex data */
2906         priv->bt_status = 0;
2907         priv->bt_traffic_load = priv->cfg->bt_init_traffic_load;
2908         priv->bt_sco_active = false;
2909         priv->bt_full_concurrent = false;
2910         priv->bt_ci_compliance = 0;
2911
2912         /* Unblock any waiting calls */
2913         wake_up_interruptible_all(&priv->wait_command_queue);
2914
2915         /* Wipe out the EXIT_PENDING status bit if we are not actually
2916          * exiting the module */
2917         if (!exit_pending)
2918                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2919
2920         /* stop and reset the on-board processor */
2921         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2922
2923         /* tell the device to stop sending interrupts */
2924         spin_lock_irqsave(&priv->lock, flags);
2925         iwl_disable_interrupts(priv);
2926         spin_unlock_irqrestore(&priv->lock, flags);
2927         iwl_synchronize_irq(priv);
2928
2929         if (priv->mac80211_registered)
2930                 ieee80211_stop_queues(priv->hw);
2931
2932         /* If we have not previously called iwl_init() then
2933          * clear all bits but the RF Kill bit and return */
2934         if (!iwl_is_init(priv)) {
2935                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2936                                         STATUS_RF_KILL_HW |
2937                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2938                                         STATUS_GEO_CONFIGURED |
2939                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2940                                         STATUS_EXIT_PENDING;
2941                 goto exit;
2942         }
2943
2944         /* ...otherwise clear out all the status bits but the RF Kill
2945          * bit and continue taking the NIC down. */
2946         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2947                                 STATUS_RF_KILL_HW |
2948                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2949                                 STATUS_GEO_CONFIGURED |
2950                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2951                                 STATUS_FW_ERROR |
2952                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2953                                 STATUS_EXIT_PENDING;
2954
2955         /* device going down, Stop using ICT table */
2956         iwl_disable_ict(priv);
2957
2958         iwlagn_txq_ctx_stop(priv);
2959         iwlagn_rxq_stop(priv);
2960
2961         /* Power-down device's busmaster DMA clocks */
2962         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2963         udelay(5);
2964
2965         /* Make sure (redundant) we've released our request to stay awake */
2966         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2967
2968         /* Stop the device, and put it in low power state */
2969         priv->cfg->ops->lib->apm_ops.stop(priv);
2970
2971  exit:
2972         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2973
2974         if (priv->ibss_beacon)
2975                 dev_kfree_skb(priv->ibss_beacon);
2976         priv->ibss_beacon = NULL;
2977
2978         /* clear out any free frames */
2979         iwl_clear_free_frames(priv);
2980 }
2981
2982 static void iwl_down(struct iwl_priv *priv)
2983 {
2984         mutex_lock(&priv->mutex);
2985         __iwl_down(priv);
2986         mutex_unlock(&priv->mutex);
2987
2988         iwl_cancel_deferred_work(priv);
2989 }
2990
2991 #define HW_READY_TIMEOUT (50)
2992
2993 static int iwl_set_hw_ready(struct iwl_priv *priv)
2994 {
2995         int ret = 0;
2996
2997         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2998                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2999
3000         /* See if we got it */
3001         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3002                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3003                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3004                                 HW_READY_TIMEOUT);
3005         if (ret != -ETIMEDOUT)
3006                 priv->hw_ready = true;
3007         else
3008                 priv->hw_ready = false;
3009
3010         IWL_DEBUG_INFO(priv, "hardware %s\n",
3011                       (priv->hw_ready == 1) ? "ready" : "not ready");
3012         return ret;
3013 }
3014
3015 static int iwl_prepare_card_hw(struct iwl_priv *priv)
3016 {
3017         int ret = 0;
3018
3019         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
3020
3021         ret = iwl_set_hw_ready(priv);
3022         if (priv->hw_ready)
3023                 return ret;
3024
3025         /* If HW is not ready, prepare the conditions to check again */
3026         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3027                         CSR_HW_IF_CONFIG_REG_PREPARE);
3028
3029         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3030                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
3031                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
3032
3033         /* HW should be ready by now, check again. */
3034         if (ret != -ETIMEDOUT)
3035                 iwl_set_hw_ready(priv);
3036
3037         return ret;
3038 }
3039
3040 #define MAX_HW_RESTARTS 5
3041
3042 static int __iwl_up(struct iwl_priv *priv)
3043 {
3044         struct iwl_rxon_context *ctx;
3045         int i;
3046         int ret;
3047
3048         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3049                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
3050                 return -EIO;
3051         }
3052
3053         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
3054                 IWL_ERR(priv, "ucode not available for device bringup\n");
3055                 return -EIO;
3056         }
3057
3058         for_each_context(priv, ctx) {
3059                 ret = iwl_alloc_bcast_station(priv, ctx, true);
3060                 if (ret) {
3061                         iwl_dealloc_bcast_stations(priv);
3062                         return ret;
3063                 }
3064         }
3065
3066         iwl_prepare_card_hw(priv);
3067
3068         if (!priv->hw_ready) {
3069                 IWL_WARN(priv, "Exit HW not ready\n");
3070                 return -EIO;
3071         }
3072
3073         /* If platform's RF_KILL switch is NOT set to KILL */
3074         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3075                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3076         else
3077                 set_bit(STATUS_RF_KILL_HW, &priv->status);
3078
3079         if (iwl_is_rfkill(priv)) {
3080                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3081
3082                 iwl_enable_interrupts(priv);
3083                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
3084                 return 0;
3085         }
3086
3087         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3088
3089         /* must be initialised before iwl_hw_nic_init */
3090         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3091                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3092         else
3093                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
3094
3095         ret = iwlagn_hw_nic_init(priv);
3096         if (ret) {
3097                 IWL_ERR(priv, "Unable to init nic\n");
3098                 return ret;
3099         }
3100
3101         /* make sure rfkill handshake bits are cleared */
3102         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3103         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
3104                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3105
3106         /* clear (again), then enable host interrupts */
3107         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3108         iwl_enable_interrupts(priv);
3109
3110         /* really make sure rfkill handshake bits are cleared */
3111         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3112         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3113
3114         /* Copy original ucode data image from disk into backup cache.
3115          * This will be used to initialize the on-board processor's
3116          * data SRAM for a clean start when the runtime program first loads. */
3117         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
3118                priv->ucode_data.len);
3119
3120         for (i = 0; i < MAX_HW_RESTARTS; i++) {
3121
3122                 /* load bootstrap state machine,
3123                  * load bootstrap program into processor's memory,
3124                  * prepare to load the "initialize" uCode */
3125                 ret = priv->cfg->ops->lib->load_ucode(priv);
3126
3127                 if (ret) {
3128                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3129                                 ret);
3130                         continue;
3131                 }
3132
3133                 /* start card; "initialize" will load runtime ucode */
3134                 iwl_nic_start(priv);
3135
3136                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3137
3138                 return 0;
3139         }
3140
3141         set_bit(STATUS_EXIT_PENDING, &priv->status);
3142         __iwl_down(priv);
3143         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3144
3145         /* tried to restart and config the device for as long as our
3146          * patience could withstand */
3147         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3148         return -EIO;
3149 }
3150
3151
3152 /*****************************************************************************
3153  *
3154  * Workqueue callbacks
3155  *
3156  *****************************************************************************/
3157
3158 static void iwl_bg_init_alive_start(struct work_struct *data)
3159 {
3160         struct iwl_priv *priv =
3161             container_of(data, struct iwl_priv, init_alive_start.work);
3162
3163         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3164                 return;
3165
3166         mutex_lock(&priv->mutex);
3167         priv->cfg->ops->lib->init_alive_start(priv);
3168         mutex_unlock(&priv->mutex);
3169 }
3170
3171 static void iwl_bg_alive_start(struct work_struct *data)
3172 {
3173         struct iwl_priv *priv =
3174             container_of(data, struct iwl_priv, alive_start.work);
3175
3176         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3177                 return;
3178
3179         /* enable dram interrupt */
3180         iwl_reset_ict(priv);
3181
3182         mutex_lock(&priv->mutex);
3183         iwl_alive_start(priv);
3184         mutex_unlock(&priv->mutex);
3185 }
3186
3187 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3188 {
3189         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3190                         run_time_calib_work);
3191
3192         mutex_lock(&priv->mutex);
3193
3194         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3195             test_bit(STATUS_SCANNING, &priv->status)) {
3196                 mutex_unlock(&priv->mutex);
3197                 return;
3198         }
3199
3200         if (priv->start_calib) {
3201                 if (priv->cfg->bt_statistics) {
3202                         iwl_chain_noise_calibration(priv,
3203                                         (void *)&priv->_agn.statistics_bt);
3204                         iwl_sensitivity_calibration(priv,
3205                                         (void *)&priv->_agn.statistics_bt);
3206                 } else {
3207                         iwl_chain_noise_calibration(priv,
3208                                         (void *)&priv->_agn.statistics);
3209                         iwl_sensitivity_calibration(priv,
3210                                         (void *)&priv->_agn.statistics);
3211                 }
3212         }
3213
3214         mutex_unlock(&priv->mutex);
3215 }
3216
3217 static void iwl_bg_restart(struct work_struct *data)
3218 {
3219         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3220
3221         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3222                 return;
3223
3224         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3225                 struct iwl_rxon_context *ctx;
3226                 bool bt_sco, bt_full_concurrent;
3227                 u8 bt_ci_compliance;
3228                 u8 bt_load;
3229                 u8 bt_status;
3230
3231                 mutex_lock(&priv->mutex);
3232                 for_each_context(priv, ctx)
3233                         ctx->vif = NULL;
3234                 priv->is_open = 0;
3235
3236                 /*
3237                  * __iwl_down() will clear the BT status variables,
3238                  * which is correct, but when we restart we really
3239                  * want to keep them so restore them afterwards.
3240                  *
3241                  * The restart process will later pick them up and
3242                  * re-configure the hw when we reconfigure the BT
3243                  * command.
3244                  */
3245                 bt_sco = priv->bt_sco_active;
3246                 bt_full_concurrent = priv->bt_full_concurrent;
3247                 bt_ci_compliance = priv->bt_ci_compliance;
3248                 bt_load = priv->bt_traffic_load;
3249                 bt_status = priv->bt_status;
3250
3251                 __iwl_down(priv);
3252
3253                 priv->bt_sco_active = bt_sco;
3254                 priv->bt_full_concurrent = bt_full_concurrent;
3255                 priv->bt_ci_compliance = bt_ci_compliance;
3256                 priv->bt_traffic_load = bt_load;
3257                 priv->bt_status = bt_status;
3258
3259                 mutex_unlock(&priv->mutex);
3260                 iwl_cancel_deferred_work(priv);
3261                 ieee80211_restart_hw(priv->hw);
3262         } else {
3263                 iwl_down(priv);
3264
3265                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3266                         return;
3267
3268                 mutex_lock(&priv->mutex);
3269                 __iwl_up(priv);
3270                 mutex_unlock(&priv->mutex);
3271         }
3272 }
3273
3274 static void iwl_bg_rx_replenish(struct work_struct *data)
3275 {
3276         struct iwl_priv *priv =
3277             container_of(data, struct iwl_priv, rx_replenish);
3278
3279         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3280                 return;
3281
3282         mutex_lock(&priv->mutex);
3283         iwlagn_rx_replenish(priv);
3284         mutex_unlock(&priv->mutex);
3285 }
3286
3287 #define IWL_DELAY_NEXT_SCAN (HZ*2)
3288
3289 void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
3290 {
3291         struct iwl_rxon_context *ctx;
3292         struct ieee80211_conf *conf = NULL;
3293         int ret = 0;
3294
3295         if (!vif || !priv->is_open)
3296                 return;
3297
3298         ctx = iwl_rxon_ctx_from_vif(vif);
3299
3300         if (vif->type == NL80211_IFTYPE_AP) {
3301                 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
3302                 return;
3303         }
3304
3305         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3306                 return;
3307
3308         iwl_scan_cancel_timeout(priv, 200);
3309
3310         conf = ieee80211_get_hw_conf(priv->hw);
3311
3312         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3313         iwlcore_commit_rxon(priv, ctx);
3314
3315         ret = iwl_send_rxon_timing(priv, ctx);
3316         if (ret)
3317                 IWL_WARN(priv, "RXON timing - "
3318                             "Attempting to continue.\n");
3319
3320         ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3321
3322         iwl_set_rxon_ht(priv, &priv->current_ht_config);
3323
3324         if (priv->cfg->ops->hcmd->set_rxon_chain)
3325                 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3326
3327         ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
3328
3329         IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
3330                         vif->bss_conf.aid, vif->bss_conf.beacon_int);
3331
3332         if (vif->bss_conf.use_short_preamble)
3333                 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3334         else
3335                 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3336
3337         if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3338                 if (vif->bss_conf.use_short_slot)
3339                         ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
3340                 else
3341                         ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3342         }
3343
3344         iwlcore_commit_rxon(priv, ctx);
3345
3346         IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
3347                         vif->bss_conf.aid, ctx->active.bssid_addr);
3348
3349         switch (vif->type) {
3350         case NL80211_IFTYPE_STATION:
3351                 break;
3352         case NL80211_IFTYPE_ADHOC:
3353                 iwl_send_beacon_cmd(priv);
3354                 break;
3355         default:
3356                 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3357                           __func__, vif->type);
3358                 break;
3359         }
3360
3361         /* the chain noise calibration will enabled PM upon completion
3362          * If chain noise has already been run, then we need to enable
3363          * power management here */
3364         if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
3365                 iwl_power_update_mode(priv, false);
3366
3367         /* Enable Rx differential gain and sensitivity calibrations */
3368         iwl_chain_noise_reset(priv);
3369         priv->start_calib = 1;
3370
3371 }
3372
3373 /*****************************************************************************
3374  *
3375  * mac80211 entry point functions
3376  *
3377  *****************************************************************************/
3378
3379 #define UCODE_READY_TIMEOUT     (4 * HZ)
3380
3381 /*
3382  * Not a mac80211 entry point function, but it fits in with all the
3383  * other mac80211 functions grouped here.
3384  */
3385 static int iwl_mac_setup_register(struct iwl_priv *priv,
3386                                   struct iwlagn_ucode_capabilities *capa)
3387 {
3388         int ret;
3389         struct ieee80211_hw *hw = priv->hw;
3390         struct iwl_rxon_context *ctx;
3391
3392         hw->rate_control_algorithm = "iwl-agn-rs";
3393
3394         /* Tell mac80211 our characteristics */
3395         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3396                     IEEE80211_HW_AMPDU_AGGREGATION |
3397                     IEEE80211_HW_NEED_DTIM_PERIOD |
3398                     IEEE80211_HW_SPECTRUM_MGMT;
3399
3400         if (!priv->cfg->broken_powersave)
3401                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3402                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3403
3404         if (priv->cfg->sku & IWL_SKU_N)
3405                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3406                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3407
3408         hw->sta_data_size = sizeof(struct iwl_station_priv);
3409         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3410
3411         for_each_context(priv, ctx) {
3412                 hw->wiphy->interface_modes |= ctx->interface_modes;
3413                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3414         }
3415
3416         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3417                             WIPHY_FLAG_DISABLE_BEACON_HINTS;
3418
3419         /*
3420          * For now, disable PS by default because it affects
3421          * RX performance significantly.
3422          */
3423         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3424
3425         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3426         /* we create the 802.11 header and a zero-length SSID element */
3427         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3428
3429         /* Default value; 4 EDCA QOS priorities */
3430         hw->queues = 4;
3431
3432         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3433
3434         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3435                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3436                         &priv->bands[IEEE80211_BAND_2GHZ];
3437         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3438                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3439                         &priv->bands[IEEE80211_BAND_5GHZ];
3440
3441         ret = ieee80211_register_hw(priv->hw);
3442         if (ret) {
3443                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3444                 return ret;
3445         }
3446         priv->mac80211_registered = 1;
3447
3448         return 0;
3449 }
3450
3451
3452 static int iwl_mac_start(struct ieee80211_hw *hw)
3453 {
3454         struct iwl_priv *priv = hw->priv;
3455         int ret;
3456
3457         IWL_DEBUG_MAC80211(priv, "enter\n");
3458
3459         /* we should be verifying the device is ready to be opened */
3460         mutex_lock(&priv->mutex);
3461         ret = __iwl_up(priv);
3462         mutex_unlock(&priv->mutex);
3463
3464         if (ret)
3465                 return ret;
3466
3467         if (iwl_is_rfkill(priv))
3468                 goto out;
3469
3470         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3471
3472         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3473          * mac80211 will not be run successfully. */
3474         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3475                         test_bit(STATUS_READY, &priv->status),
3476                         UCODE_READY_TIMEOUT);
3477         if (!ret) {
3478                 if (!test_bit(STATUS_READY, &priv->status)) {
3479                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3480                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3481                         return -ETIMEDOUT;
3482                 }
3483         }
3484
3485         iwl_led_start(priv);
3486
3487 out:
3488         priv->is_open = 1;
3489         IWL_DEBUG_MAC80211(priv, "leave\n");
3490         return 0;
3491 }
3492
3493 static void iwl_mac_stop(struct ieee80211_hw *hw)
3494 {
3495         struct iwl_priv *priv = hw->priv;
3496
3497         IWL_DEBUG_MAC80211(priv, "enter\n");
3498
3499         if (!priv->is_open)
3500                 return;
3501
3502         priv->is_open = 0;
3503
3504         if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
3505                 /* stop mac, cancel any scan request and clear
3506                  * RXON_FILTER_ASSOC_MSK BIT
3507                  */
3508                 mutex_lock(&priv->mutex);
3509                 iwl_scan_cancel_timeout(priv, 100);
3510                 mutex_unlock(&priv->mutex);
3511         }
3512
3513         iwl_down(priv);
3514
3515         flush_workqueue(priv->workqueue);
3516
3517         /* enable interrupts again in order to receive rfkill changes */
3518         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3519         iwl_enable_interrupts(priv);
3520
3521         IWL_DEBUG_MAC80211(priv, "leave\n");
3522 }
3523
3524 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3525 {
3526         struct iwl_priv *priv = hw->priv;
3527
3528         IWL_DEBUG_MACDUMP(priv, "enter\n");
3529
3530         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3531                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3532
3533         if (iwlagn_tx_skb(priv, skb))
3534                 dev_kfree_skb_any(skb);
3535
3536         IWL_DEBUG_MACDUMP(priv, "leave\n");
3537         return NETDEV_TX_OK;
3538 }
3539
3540 void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
3541 {
3542         struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
3543         int ret = 0;
3544
3545         lockdep_assert_held(&priv->mutex);
3546
3547         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3548                 return;
3549
3550         /* The following should be done only at AP bring up */
3551         if (!iwl_is_associated_ctx(ctx)) {
3552
3553                 /* RXON - unassoc (to set timing command) */
3554                 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3555                 iwlcore_commit_rxon(priv, ctx);
3556
3557                 /* RXON Timing */
3558                 ret = iwl_send_rxon_timing(priv, ctx);
3559                 if (ret)
3560                         IWL_WARN(priv, "RXON timing failed - "
3561                                         "Attempting to continue.\n");
3562
3563                 /* AP has all antennas */
3564                 priv->chain_noise_data.active_chains =
3565                         priv->hw_params.valid_rx_ant;
3566                 iwl_set_rxon_ht(priv, &priv->current_ht_config);
3567                 if (priv->cfg->ops->hcmd->set_rxon_chain)
3568                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3569
3570                 ctx->staging.assoc_id = 0;
3571
3572                 if (vif->bss_conf.use_short_preamble)
3573                         ctx->staging.flags |=
3574                                 RXON_FLG_SHORT_PREAMBLE_MSK;
3575                 else
3576                         ctx->staging.flags &=
3577                                 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3578
3579                 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3580                         if (vif->bss_conf.use_short_slot)
3581                                 ctx->staging.flags |=
3582                                         RXON_FLG_SHORT_SLOT_MSK;
3583                         else
3584                                 ctx->staging.flags &=
3585                                         ~RXON_FLG_SHORT_SLOT_MSK;
3586                 }
3587                 /* need to send beacon cmd before committing assoc RXON! */
3588                 iwl_send_beacon_cmd(priv);
3589                 /* restore RXON assoc */
3590                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3591                 iwlcore_commit_rxon(priv, ctx);
3592         }
3593         iwl_send_beacon_cmd(priv);
3594
3595         /* FIXME - we need to add code here to detect a totally new
3596          * configuration, reset the AP, unassoc, rxon timing, assoc,
3597          * clear sta table, add BCAST sta... */
3598 }
3599
3600 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
3601                                     struct ieee80211_vif *vif,
3602                                     struct ieee80211_key_conf *keyconf,
3603                                     struct ieee80211_sta *sta,
3604                                     u32 iv32, u16 *phase1key)
3605 {
3606
3607         struct iwl_priv *priv = hw->priv;
3608         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3609
3610         IWL_DEBUG_MAC80211(priv, "enter\n");
3611
3612         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3613                             iv32, phase1key);
3614
3615         IWL_DEBUG_MAC80211(priv, "leave\n");
3616 }
3617
3618 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3619                            struct ieee80211_vif *vif,
3620                            struct ieee80211_sta *sta,
3621                            struct ieee80211_key_conf *key)
3622 {
3623         struct iwl_priv *priv = hw->priv;
3624         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3625         struct iwl_rxon_context *ctx = vif_priv->ctx;
3626         int ret;
3627         u8 sta_id;
3628         bool is_default_wep_key = false;
3629
3630         IWL_DEBUG_MAC80211(priv, "enter\n");
3631
3632         if (priv->cfg->mod_params->sw_crypto) {
3633                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3634                 return -EOPNOTSUPP;
3635         }
3636
3637         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3638         if (sta_id == IWL_INVALID_STATION)
3639                 return -EINVAL;
3640
3641         mutex_lock(&priv->mutex);
3642         iwl_scan_cancel_timeout(priv, 100);
3643
3644         /*
3645          * If we are getting WEP group key and we didn't receive any key mapping
3646          * so far, we are in legacy wep mode (group key only), otherwise we are
3647          * in 1X mode.
3648          * In legacy wep mode, we use another host command to the uCode.
3649          */
3650         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3651              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3652             !sta) {
3653                 if (cmd == SET_KEY)
3654                         is_default_wep_key = !ctx->key_mapping_keys;
3655                 else
3656                         is_default_wep_key =
3657                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3658         }
3659
3660         switch (cmd) {
3661         case SET_KEY:
3662                 if (is_default_wep_key)
3663                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3664                 else
3665                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3666                                                   key, sta_id);
3667
3668                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3669                 break;
3670         case DISABLE_KEY:
3671                 if (is_default_wep_key)
3672                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3673                 else
3674                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3675
3676                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3677                 break;
3678         default:
3679                 ret = -EINVAL;
3680         }
3681
3682         mutex_unlock(&priv->mutex);
3683         IWL_DEBUG_MAC80211(priv, "leave\n");
3684
3685         return ret;
3686 }
3687
3688 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
3689                                 struct ieee80211_vif *vif,
3690                                 enum ieee80211_ampdu_mlme_action action,
3691                                 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3692 {
3693         struct iwl_priv *priv = hw->priv;
3694         int ret = -EINVAL;
3695
3696         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3697                      sta->addr, tid);
3698
3699         if (!(priv->cfg->sku & IWL_SKU_N))
3700                 return -EACCES;
3701
3702         mutex_lock(&priv->mutex);
3703
3704         switch (action) {
3705         case IEEE80211_AMPDU_RX_START:
3706                 IWL_DEBUG_HT(priv, "start Rx\n");
3707                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3708                 break;
3709         case IEEE80211_AMPDU_RX_STOP:
3710                 IWL_DEBUG_HT(priv, "stop Rx\n");
3711                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3712                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3713                         ret = 0;
3714                 break;
3715         case IEEE80211_AMPDU_TX_START:
3716                 IWL_DEBUG_HT(priv, "start Tx\n");
3717                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3718                 if (ret == 0) {
3719                         priv->_agn.agg_tids_count++;
3720                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3721                                      priv->_agn.agg_tids_count);
3722                 }
3723                 break;
3724         case IEEE80211_AMPDU_TX_STOP:
3725                 IWL_DEBUG_HT(priv, "stop Tx\n");
3726                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3727                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3728                         priv->_agn.agg_tids_count--;
3729                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3730                                      priv->_agn.agg_tids_count);
3731                 }
3732                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3733                         ret = 0;
3734                 if (priv->cfg->use_rts_for_aggregation) {
3735                         struct iwl_station_priv *sta_priv =
3736                                 (void *) sta->drv_priv;
3737                         /*
3738                          * switch off RTS/CTS if it was previously enabled
3739                          */
3740
3741                         sta_priv->lq_sta.lq.general_params.flags &=
3742                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3743                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3744                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3745                 }
3746                 break;
3747         case IEEE80211_AMPDU_TX_OPERATIONAL:
3748                 if (priv->cfg->use_rts_for_aggregation) {
3749                         struct iwl_station_priv *sta_priv =
3750                                 (void *) sta->drv_priv;
3751
3752                         /*
3753                          * switch to RTS/CTS if it is the prefer protection
3754                          * method for HT traffic
3755                          */
3756
3757                         sta_priv->lq_sta.lq.general_params.flags |=
3758                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3759                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3760                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3761                 }
3762                 ret = 0;
3763                 break;
3764         }
3765         mutex_unlock(&priv->mutex);
3766
3767         return ret;
3768 }
3769
3770 static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3771                                struct ieee80211_vif *vif,
3772                                enum sta_notify_cmd cmd,
3773                                struct ieee80211_sta *sta)
3774 {
3775         struct iwl_priv *priv = hw->priv;
3776         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3777         int sta_id;
3778
3779         switch (cmd) {
3780         case STA_NOTIFY_SLEEP:
3781                 WARN_ON(!sta_priv->client);
3782                 sta_priv->asleep = true;
3783                 if (atomic_read(&sta_priv->pending_frames) > 0)
3784                         ieee80211_sta_block_awake(hw, sta, true);
3785                 break;
3786         case STA_NOTIFY_AWAKE:
3787                 WARN_ON(!sta_priv->client);
3788                 if (!sta_priv->asleep)
3789                         break;
3790                 sta_priv->asleep = false;
3791                 sta_id = iwl_sta_id(sta);
3792                 if (sta_id != IWL_INVALID_STATION)
3793                         iwl_sta_modify_ps_wake(priv, sta_id);
3794                 break;
3795         default:
3796                 break;
3797         }
3798 }
3799
3800 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3801                               struct ieee80211_vif *vif,
3802                               struct ieee80211_sta *sta)
3803 {
3804         struct iwl_priv *priv = hw->priv;
3805         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3806         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3807         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3808         int ret;
3809         u8 sta_id;
3810
3811         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3812                         sta->addr);
3813         mutex_lock(&priv->mutex);
3814         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3815                         sta->addr);
3816         sta_priv->common.sta_id = IWL_INVALID_STATION;
3817
3818         atomic_set(&sta_priv->pending_frames, 0);
3819         if (vif->type == NL80211_IFTYPE_AP)
3820                 sta_priv->client = true;
3821
3822         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3823                                      is_ap, sta, &sta_id);
3824         if (ret) {
3825                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3826                         sta->addr, ret);
3827                 /* Should we return success if return code is EEXIST ? */
3828                 mutex_unlock(&priv->mutex);
3829                 return ret;
3830         }
3831
3832         sta_priv->common.sta_id = sta_id;
3833
3834         /* Initialize rate scaling */
3835         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3836                        sta->addr);
3837         iwl_rs_rate_init(priv, sta, sta_id);
3838         mutex_unlock(&priv->mutex);
3839
3840         return 0;
3841 }
3842
3843 static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3844                                    struct ieee80211_channel_switch *ch_switch)
3845 {
3846         struct iwl_priv *priv = hw->priv;
3847         const struct iwl_channel_info *ch_info;
3848         struct ieee80211_conf *conf = &hw->conf;
3849         struct ieee80211_channel *channel = ch_switch->channel;
3850         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3851         /*
3852          * MULTI-FIXME
3853          * When we add support for multiple interfaces, we need to
3854          * revisit this. The channel switch command in the device
3855          * only affects the BSS context, but what does that really
3856          * mean? And what if we get a CSA on the second interface?
3857          * This needs a lot of work.
3858          */
3859         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3860         u16 ch;
3861         unsigned long flags = 0;
3862
3863         IWL_DEBUG_MAC80211(priv, "enter\n");
3864
3865         if (iwl_is_rfkill(priv))
3866                 goto out_exit;
3867
3868         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3869             test_bit(STATUS_SCANNING, &priv->status))
3870                 goto out_exit;
3871
3872         if (!iwl_is_associated_ctx(ctx))
3873                 goto out_exit;
3874
3875         /* channel switch in progress */
3876         if (priv->switch_rxon.switch_in_progress == true)
3877                 goto out_exit;
3878
3879         mutex_lock(&priv->mutex);
3880         if (priv->cfg->ops->lib->set_channel_switch) {
3881
3882                 ch = channel->hw_value;
3883                 if (le16_to_cpu(ctx->active.channel) != ch) {
3884                         ch_info = iwl_get_channel_info(priv,
3885                                                        channel->band,
3886                                                        ch);
3887                         if (!is_channel_valid(ch_info)) {
3888                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3889                                 goto out;
3890                         }
3891                         spin_lock_irqsave(&priv->lock, flags);
3892
3893                         priv->current_ht_config.smps = conf->smps_mode;
3894
3895                         /* Configure HT40 channels */
3896                         ctx->ht.enabled = conf_is_ht(conf);
3897                         if (ctx->ht.enabled) {
3898                                 if (conf_is_ht40_minus(conf)) {
3899                                         ctx->ht.extension_chan_offset =
3900                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3901                                         ctx->ht.is_40mhz = true;
3902                                 } else if (conf_is_ht40_plus(conf)) {
3903                                         ctx->ht.extension_chan_offset =
3904                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3905                                         ctx->ht.is_40mhz = true;
3906                                 } else {
3907                                         ctx->ht.extension_chan_offset =
3908                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3909                                         ctx->ht.is_40mhz = false;
3910                                 }
3911                         } else
3912                                 ctx->ht.is_40mhz = false;
3913
3914                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3915                                 ctx->staging.flags = 0;
3916
3917                         iwl_set_rxon_channel(priv, channel, ctx);
3918                         iwl_set_rxon_ht(priv, ht_conf);
3919                         iwl_set_flags_for_band(priv, ctx, channel->band,
3920                                                ctx->vif);
3921                         spin_unlock_irqrestore(&priv->lock, flags);
3922
3923                         iwl_set_rate(priv);
3924                         /*
3925                          * at this point, staging_rxon has the
3926                          * configuration for channel switch
3927                          */
3928                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3929                                                                     ch_switch))
3930                                 priv->switch_rxon.switch_in_progress = false;
3931                 }
3932         }
3933 out:
3934         mutex_unlock(&priv->mutex);
3935 out_exit:
3936         if (!priv->switch_rxon.switch_in_progress)
3937                 ieee80211_chswitch_done(ctx->vif, false);
3938         IWL_DEBUG_MAC80211(priv, "leave\n");
3939 }
3940
3941 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3942                                     unsigned int changed_flags,
3943                                     unsigned int *total_flags,
3944                                     u64 multicast)
3945 {
3946         struct iwl_priv *priv = hw->priv;
3947         __le32 filter_or = 0, filter_nand = 0;
3948         struct iwl_rxon_context *ctx;
3949
3950 #define CHK(test, flag) do { \
3951         if (*total_flags & (test))              \
3952                 filter_or |= (flag);            \
3953         else                                    \
3954                 filter_nand |= (flag);          \
3955         } while (0)
3956
3957         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3958                         changed_flags, *total_flags);
3959
3960         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3961         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3962         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3963
3964 #undef CHK
3965
3966         mutex_lock(&priv->mutex);
3967
3968         for_each_context(priv, ctx) {
3969                 ctx->staging.filter_flags &= ~filter_nand;
3970                 ctx->staging.filter_flags |= filter_or;
3971                 iwlcore_commit_rxon(priv, ctx);
3972         }
3973
3974         mutex_unlock(&priv->mutex);
3975
3976         /*
3977          * Receiving all multicast frames is always enabled by the
3978          * default flags setup in iwl_connection_init_rx_config()
3979          * since we currently do not support programming multicast
3980          * filters into the device.
3981          */
3982         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3983                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3984 }
3985
3986 static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3987 {
3988         struct iwl_priv *priv = hw->priv;
3989
3990         mutex_lock(&priv->mutex);
3991         IWL_DEBUG_MAC80211(priv, "enter\n");
3992
3993         /* do not support "flush" */
3994         if (!priv->cfg->ops->lib->txfifo_flush)
3995                 goto done;
3996
3997         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3998                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3999                 goto done;
4000         }
4001         if (iwl_is_rfkill(priv)) {
4002                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
4003                 goto done;
4004         }
4005
4006         /*
4007          * mac80211 will not push any more frames for transmit
4008          * until the flush is completed
4009          */
4010         if (drop) {
4011                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
4012                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
4013                         IWL_ERR(priv, "flush request fail\n");
4014                         goto done;
4015                 }
4016         }
4017         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
4018         iwlagn_wait_tx_queue_empty(priv);
4019 done:
4020         mutex_unlock(&priv->mutex);
4021         IWL_DEBUG_MAC80211(priv, "leave\n");
4022 }
4023
4024 /*****************************************************************************
4025  *
4026  * driver setup and teardown
4027  *
4028  *****************************************************************************/
4029
4030 static void iwl_setup_deferred_work(struct iwl_priv *priv)
4031 {
4032         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
4033
4034         init_waitqueue_head(&priv->wait_command_queue);
4035
4036         INIT_WORK(&priv->restart, iwl_bg_restart);
4037         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
4038         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
4039         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4040         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
4041         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
4042         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4043         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
4044         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
4045
4046         iwl_setup_scan_deferred_work(priv);
4047
4048         if (priv->cfg->ops->lib->setup_deferred_work)
4049                 priv->cfg->ops->lib->setup_deferred_work(priv);
4050
4051         init_timer(&priv->statistics_periodic);
4052         priv->statistics_periodic.data = (unsigned long)priv;
4053         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
4054
4055         init_timer(&priv->ucode_trace);
4056         priv->ucode_trace.data = (unsigned long)priv;
4057         priv->ucode_trace.function = iwl_bg_ucode_trace;
4058
4059         if (priv->cfg->ops->lib->recover_from_tx_stall) {
4060                 init_timer(&priv->monitor_recover);
4061                 priv->monitor_recover.data = (unsigned long)priv;
4062                 priv->monitor_recover.function =
4063                         priv->cfg->ops->lib->recover_from_tx_stall;
4064         }
4065
4066         if (!priv->cfg->use_isr_legacy)
4067                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4068                         iwl_irq_tasklet, (unsigned long)priv);
4069         else
4070                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4071                         iwl_irq_tasklet_legacy, (unsigned long)priv);
4072 }
4073
4074 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
4075 {
4076         if (priv->cfg->ops->lib->cancel_deferred_work)
4077                 priv->cfg->ops->lib->cancel_deferred_work(priv);
4078
4079         cancel_delayed_work_sync(&priv->init_alive_start);
4080         cancel_delayed_work(&priv->scan_check);
4081         cancel_work_sync(&priv->start_internal_scan);
4082         cancel_delayed_work(&priv->alive_start);
4083         cancel_work_sync(&priv->run_time_calib_work);
4084         cancel_work_sync(&priv->beacon_update);
4085         cancel_work_sync(&priv->bt_full_concurrency);
4086         cancel_work_sync(&priv->bt_runtime_config);
4087         del_timer_sync(&priv->statistics_periodic);
4088         del_timer_sync(&priv->ucode_trace);
4089 }
4090
4091 static void iwl_init_hw_rates(struct iwl_priv *priv,
4092                               struct ieee80211_rate *rates)
4093 {
4094         int i;
4095
4096         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4097                 rates[i].bitrate = iwl_rates[i].ieee * 5;
4098                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4099                 rates[i].hw_value_short = i;
4100                 rates[i].flags = 0;
4101                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4102                         /*
4103                          * If CCK != 1M then set short preamble rate flag.
4104                          */
4105                         rates[i].flags |=
4106                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4107                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
4108                 }
4109         }
4110 }
4111
4112 static int iwl_init_drv(struct iwl_priv *priv)
4113 {
4114         int ret;
4115
4116         priv->ibss_beacon = NULL;
4117
4118         spin_lock_init(&priv->sta_lock);
4119         spin_lock_init(&priv->hcmd_lock);
4120
4121         INIT_LIST_HEAD(&priv->free_frames);
4122
4123         mutex_init(&priv->mutex);
4124         mutex_init(&priv->sync_cmd_mutex);
4125
4126         priv->ieee_channels = NULL;
4127         priv->ieee_rates = NULL;
4128         priv->band = IEEE80211_BAND_2GHZ;
4129
4130         priv->iw_mode = NL80211_IFTYPE_STATION;
4131         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
4132         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
4133         priv->_agn.agg_tids_count = 0;
4134
4135         /* initialize force reset */
4136         priv->force_reset[IWL_RF_RESET].reset_duration =
4137                 IWL_DELAY_NEXT_FORCE_RF_RESET;
4138         priv->force_reset[IWL_FW_RESET].reset_duration =
4139                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
4140
4141         /* Choose which receivers/antennas to use */
4142         if (priv->cfg->ops->hcmd->set_rxon_chain)
4143                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4144                                         &priv->contexts[IWL_RXON_CTX_BSS]);
4145
4146         iwl_init_scan_params(priv);
4147
4148         /* init bt coex */
4149         if (priv->cfg->advanced_bt_coexist) {
4150                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4151                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4152                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
4153                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4154                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4155                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4156                 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4157         }
4158
4159         /* Set the tx_power_user_lmt to the lowest power level
4160          * this value will get overwritten by channel max power avg
4161          * from eeprom */
4162         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
4163
4164         ret = iwl_init_channel_map(priv);
4165         if (ret) {
4166                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4167                 goto err;
4168         }
4169
4170         ret = iwlcore_init_geos(priv);
4171         if (ret) {
4172                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4173                 goto err_free_channel_map;
4174         }
4175         iwl_init_hw_rates(priv, priv->ieee_rates);
4176
4177         return 0;
4178
4179 err_free_channel_map:
4180         iwl_free_channel_map(priv);
4181 err:
4182         return ret;
4183 }
4184
4185 static void iwl_uninit_drv(struct iwl_priv *priv)
4186 {
4187         iwl_calib_free_results(priv);
4188         iwlcore_free_geos(priv);
4189         iwl_free_channel_map(priv);
4190         kfree(priv->scan_cmd);
4191 }
4192
4193 static struct ieee80211_ops iwl_hw_ops = {
4194         .tx = iwl_mac_tx,
4195         .start = iwl_mac_start,
4196         .stop = iwl_mac_stop,
4197         .add_interface = iwl_mac_add_interface,
4198         .remove_interface = iwl_mac_remove_interface,
4199         .config = iwl_mac_config,
4200         .configure_filter = iwlagn_configure_filter,
4201         .set_key = iwl_mac_set_key,
4202         .update_tkip_key = iwl_mac_update_tkip_key,
4203         .conf_tx = iwl_mac_conf_tx,
4204         .reset_tsf = iwl_mac_reset_tsf,
4205         .bss_info_changed = iwl_bss_info_changed,
4206         .ampdu_action = iwl_mac_ampdu_action,
4207         .hw_scan = iwl_mac_hw_scan,
4208         .sta_notify = iwl_mac_sta_notify,
4209         .sta_add = iwlagn_mac_sta_add,
4210         .sta_remove = iwl_mac_sta_remove,
4211         .channel_switch = iwl_mac_channel_switch,
4212         .flush = iwl_mac_flush,
4213         .tx_last_beacon = iwl_mac_tx_last_beacon,
4214 };
4215
4216 static void iwl_hw_detect(struct iwl_priv *priv)
4217 {
4218         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4219         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4220         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4221         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4222 }
4223
4224 static int iwl_set_hw_params(struct iwl_priv *priv)
4225 {
4226         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4227         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4228         if (priv->cfg->mod_params->amsdu_size_8K)
4229                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4230         else
4231                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4232
4233         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4234
4235         if (priv->cfg->mod_params->disable_11n)
4236                 priv->cfg->sku &= ~IWL_SKU_N;
4237
4238         /* Device-specific setup */
4239         return priv->cfg->ops->lib->set_hw_params(priv);
4240 }
4241
4242 static const u8 iwlagn_bss_ac_to_fifo[] = {
4243         IWL_TX_FIFO_VO,
4244         IWL_TX_FIFO_VI,
4245         IWL_TX_FIFO_BE,
4246         IWL_TX_FIFO_BK,
4247 };
4248
4249 static const u8 iwlagn_bss_ac_to_queue[] = {
4250         0, 1, 2, 3,
4251 };
4252
4253 static const u8 iwlagn_pan_ac_to_fifo[] = {
4254         IWL_TX_FIFO_VO_IPAN,
4255         IWL_TX_FIFO_VI_IPAN,
4256         IWL_TX_FIFO_BE_IPAN,
4257         IWL_TX_FIFO_BK_IPAN,
4258 };
4259
4260 static const u8 iwlagn_pan_ac_to_queue[] = {
4261         7, 6, 5, 4,
4262 };
4263
4264 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4265 {
4266         int err = 0, i;
4267         struct iwl_priv *priv;
4268         struct ieee80211_hw *hw;
4269         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4270         unsigned long flags;
4271         u16 pci_cmd, num_mac;
4272
4273         /************************
4274          * 1. Allocating HW data
4275          ************************/
4276
4277         /* Disabling hardware scan means that mac80211 will perform scans
4278          * "the hard way", rather than using device's scan. */
4279         if (cfg->mod_params->disable_hw_scan) {
4280                 if (iwl_debug_level & IWL_DL_INFO)
4281                         dev_printk(KERN_DEBUG, &(pdev->dev),
4282                                    "Disabling hw_scan\n");
4283                 iwl_hw_ops.hw_scan = NULL;
4284         }
4285
4286         hw = iwl_alloc_all(cfg, &iwl_hw_ops);
4287         if (!hw) {
4288                 err = -ENOMEM;
4289                 goto out;
4290         }
4291         priv = hw->priv;
4292         /* At this point both hw and priv are allocated. */
4293
4294         /*
4295          * The default context is always valid,
4296          * more may be discovered when firmware
4297          * is loaded.
4298          */
4299         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4300
4301         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4302                 priv->contexts[i].ctxid = i;
4303
4304         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4305         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4306         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4307         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4308         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4309         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4310         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4311         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4312         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4313                 BIT(NL80211_IFTYPE_ADHOC);
4314         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4315                 BIT(NL80211_IFTYPE_STATION);
4316         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4317         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4318         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4319
4320         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4321         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4322         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4323         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4324         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4325         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4326         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4327         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4328         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4329         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4330         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4331         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4332                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4333         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4334         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4335         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4336
4337         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4338
4339         SET_IEEE80211_DEV(hw, &pdev->dev);
4340
4341         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4342         priv->cfg = cfg;
4343         priv->pci_dev = pdev;
4344         priv->inta_mask = CSR_INI_SET_MASK;
4345
4346         /* is antenna coupling more than 35dB ? */
4347         priv->bt_ant_couple_ok =
4348                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4349                 true : false;
4350
4351         /* enable/disable bt channel announcement */
4352         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4353
4354         if (iwl_alloc_traffic_mem(priv))
4355                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4356
4357         /**************************
4358          * 2. Initializing PCI bus
4359          **************************/
4360         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4361                                 PCIE_LINK_STATE_CLKPM);
4362
4363         if (pci_enable_device(pdev)) {
4364                 err = -ENODEV;
4365                 goto out_ieee80211_free_hw;
4366         }
4367
4368         pci_set_master(pdev);
4369
4370         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4371         if (!err)
4372                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4373         if (err) {
4374                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4375                 if (!err)
4376                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4377                 /* both attempts failed: */
4378                 if (err) {
4379                         IWL_WARN(priv, "No suitable DMA available.\n");
4380                         goto out_pci_disable_device;
4381                 }
4382         }
4383
4384         err = pci_request_regions(pdev, DRV_NAME);
4385         if (err)
4386                 goto out_pci_disable_device;
4387
4388         pci_set_drvdata(pdev, priv);
4389
4390
4391         /***********************
4392          * 3. Read REV register
4393          ***********************/
4394         priv->hw_base = pci_iomap(pdev, 0, 0);
4395         if (!priv->hw_base) {
4396                 err = -ENODEV;
4397                 goto out_pci_release_regions;
4398         }
4399
4400         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4401                 (unsigned long long) pci_resource_len(pdev, 0));
4402         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4403
4404         /* these spin locks will be used in apm_ops.init and EEPROM access
4405          * we should init now
4406          */
4407         spin_lock_init(&priv->reg_lock);
4408         spin_lock_init(&priv->lock);
4409
4410         /*
4411          * stop and reset the on-board processor just in case it is in a
4412          * strange state ... like being left stranded by a primary kernel
4413          * and this is now the kdump kernel trying to start up
4414          */
4415         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4416
4417         iwl_hw_detect(priv);
4418         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4419                 priv->cfg->name, priv->hw_rev);
4420
4421         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4422          * PCI Tx retries from interfering with C3 CPU state */
4423         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4424
4425         iwl_prepare_card_hw(priv);
4426         if (!priv->hw_ready) {
4427                 IWL_WARN(priv, "Failed, HW not ready\n");
4428                 goto out_iounmap;
4429         }
4430
4431         /*****************
4432          * 4. Read EEPROM
4433          *****************/
4434         /* Read the EEPROM */
4435         err = iwl_eeprom_init(priv);
4436         if (err) {
4437                 IWL_ERR(priv, "Unable to init EEPROM\n");
4438                 goto out_iounmap;
4439         }
4440         err = iwl_eeprom_check_version(priv);
4441         if (err)
4442                 goto out_free_eeprom;
4443
4444         /* extract MAC Address */
4445         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4446         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4447         priv->hw->wiphy->addresses = priv->addresses;
4448         priv->hw->wiphy->n_addresses = 1;
4449         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4450         if (num_mac > 1) {
4451                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4452                        ETH_ALEN);
4453                 priv->addresses[1].addr[5]++;
4454                 priv->hw->wiphy->n_addresses++;
4455         }
4456
4457         /************************
4458          * 5. Setup HW constants
4459          ************************/
4460         if (iwl_set_hw_params(priv)) {
4461                 IWL_ERR(priv, "failed to set hw parameters\n");
4462                 goto out_free_eeprom;
4463         }
4464
4465         /*******************
4466          * 6. Setup priv
4467          *******************/
4468
4469         err = iwl_init_drv(priv);
4470         if (err)
4471                 goto out_free_eeprom;
4472         /* At this point both hw and priv are initialized. */
4473
4474         /********************
4475          * 7. Setup services
4476          ********************/
4477         spin_lock_irqsave(&priv->lock, flags);
4478         iwl_disable_interrupts(priv);
4479         spin_unlock_irqrestore(&priv->lock, flags);
4480
4481         pci_enable_msi(priv->pci_dev);
4482
4483         iwl_alloc_isr_ict(priv);
4484         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4485                           IRQF_SHARED, DRV_NAME, priv);
4486         if (err) {
4487                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4488                 goto out_disable_msi;
4489         }
4490
4491         iwl_setup_deferred_work(priv);
4492         iwl_setup_rx_handlers(priv);
4493
4494         /*********************************************
4495          * 8. Enable interrupts and read RFKILL state
4496          *********************************************/
4497
4498         /* enable interrupts if needed: hw bug w/a */
4499         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4500         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4501                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4502                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4503         }
4504
4505         iwl_enable_interrupts(priv);
4506
4507         /* If platform's RF_KILL switch is NOT set to KILL */
4508         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4509                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4510         else
4511                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4512
4513         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4514                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4515
4516         iwl_power_initialize(priv);
4517         iwl_tt_initialize(priv);
4518
4519         init_completion(&priv->_agn.firmware_loading_complete);
4520
4521         err = iwl_request_firmware(priv, true);
4522         if (err)
4523                 goto out_destroy_workqueue;
4524
4525         return 0;
4526
4527  out_destroy_workqueue:
4528         destroy_workqueue(priv->workqueue);
4529         priv->workqueue = NULL;
4530         free_irq(priv->pci_dev->irq, priv);
4531         iwl_free_isr_ict(priv);
4532  out_disable_msi:
4533         pci_disable_msi(priv->pci_dev);
4534         iwl_uninit_drv(priv);
4535  out_free_eeprom:
4536         iwl_eeprom_free(priv);
4537  out_iounmap:
4538         pci_iounmap(pdev, priv->hw_base);
4539  out_pci_release_regions:
4540         pci_set_drvdata(pdev, NULL);
4541         pci_release_regions(pdev);
4542  out_pci_disable_device:
4543         pci_disable_device(pdev);
4544  out_ieee80211_free_hw:
4545         iwl_free_traffic_mem(priv);
4546         ieee80211_free_hw(priv->hw);
4547  out:
4548         return err;
4549 }
4550
4551 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4552 {
4553         struct iwl_priv *priv = pci_get_drvdata(pdev);
4554         unsigned long flags;
4555
4556         if (!priv)
4557                 return;
4558
4559         wait_for_completion(&priv->_agn.firmware_loading_complete);
4560
4561         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4562
4563         iwl_dbgfs_unregister(priv);
4564         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4565
4566         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4567          * to be called and iwl_down since we are removing the device
4568          * we need to set STATUS_EXIT_PENDING bit.
4569          */
4570         set_bit(STATUS_EXIT_PENDING, &priv->status);
4571         if (priv->mac80211_registered) {
4572                 ieee80211_unregister_hw(priv->hw);
4573                 priv->mac80211_registered = 0;
4574         } else {
4575                 iwl_down(priv);
4576         }
4577
4578         /*
4579          * Make sure device is reset to low power before unloading driver.
4580          * This may be redundant with iwl_down(), but there are paths to
4581          * run iwl_down() without calling apm_ops.stop(), and there are
4582          * paths to avoid running iwl_down() at all before leaving driver.
4583          * This (inexpensive) call *makes sure* device is reset.
4584          */
4585         priv->cfg->ops->lib->apm_ops.stop(priv);
4586
4587         iwl_tt_exit(priv);
4588
4589         /* make sure we flush any pending irq or
4590          * tasklet for the driver
4591          */
4592         spin_lock_irqsave(&priv->lock, flags);
4593         iwl_disable_interrupts(priv);
4594         spin_unlock_irqrestore(&priv->lock, flags);
4595
4596         iwl_synchronize_irq(priv);
4597
4598         iwl_dealloc_ucode_pci(priv);
4599
4600         if (priv->rxq.bd)
4601                 iwlagn_rx_queue_free(priv, &priv->rxq);
4602         iwlagn_hw_txq_ctx_free(priv);
4603
4604         iwl_eeprom_free(priv);
4605
4606
4607         /*netif_stop_queue(dev); */
4608         flush_workqueue(priv->workqueue);
4609
4610         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4611          * priv->workqueue... so we can't take down the workqueue
4612          * until now... */
4613         destroy_workqueue(priv->workqueue);
4614         priv->workqueue = NULL;
4615         iwl_free_traffic_mem(priv);
4616
4617         free_irq(priv->pci_dev->irq, priv);
4618         pci_disable_msi(priv->pci_dev);
4619         pci_iounmap(pdev, priv->hw_base);
4620         pci_release_regions(pdev);
4621         pci_disable_device(pdev);
4622         pci_set_drvdata(pdev, NULL);
4623
4624         iwl_uninit_drv(priv);
4625
4626         iwl_free_isr_ict(priv);
4627
4628         if (priv->ibss_beacon)
4629                 dev_kfree_skb(priv->ibss_beacon);
4630
4631         ieee80211_free_hw(priv->hw);
4632 }
4633
4634
4635 /*****************************************************************************
4636  *
4637  * driver and module entry point
4638  *
4639  *****************************************************************************/
4640
4641 /* Hardware specific file defines the PCI IDs table for that hardware module */
4642 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4643 #ifdef CONFIG_IWL4965
4644         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4645         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4646 #endif /* CONFIG_IWL4965 */
4647 #ifdef CONFIG_IWL5000
4648 /* 5100 Series WiFi */
4649         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4650         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4651         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4652         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4653         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4654         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4655         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4656         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4657         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4658         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4659         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4660         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4661         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4662         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4663         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4664         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4665         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4666         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4667         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4668         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4669         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4670         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4671         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4672         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4673
4674 /* 5300 Series WiFi */
4675         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4676         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4677         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4678         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4679         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4680         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4681         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4682         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4683         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4684         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4685         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4686         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4687
4688 /* 5350 Series WiFi/WiMax */
4689         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4690         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4691         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4692
4693 /* 5150 Series Wifi/WiMax */
4694         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4695         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4696         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4697         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4698         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4699         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4700
4701         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4702         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4703         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4704         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4705
4706 /* 6x00 Series */
4707         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4708         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4709         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4710         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4711         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4712         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4713         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4714         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4715         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4716         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4717
4718 /* 6x00 Series Gen2a */
4719         {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4720         {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4721         {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
4722         {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4723         {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4724         {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4725         {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
4726         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4727         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4728         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4729         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4730         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4731         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4732         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
4733
4734 /* 6x00 Series Gen2b */
4735         {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4736         {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4737         {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4738         {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4739         {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4740         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4741         {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4742         {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4743         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4744         {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4745         {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
4746         {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4747         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4748         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4749         {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4750         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4751         {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4752         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4753         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4754         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4755         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4756         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4757         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4758         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4759         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4760         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4761         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4762         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
4763
4764 /* 6x50 WiFi/WiMax Series */
4765         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4766         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4767         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4768         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4769         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4770         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4771
4772 /* 6x50 WiFi/WiMax Series Gen2 */
4773         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4774         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4775         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4776         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4777         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4778         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4779
4780 /* 1000 Series WiFi */
4781         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4782         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4783         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4784         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4785         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4786         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4787         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4788         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4789         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4790         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4791         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4792         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4793 #endif /* CONFIG_IWL5000 */
4794
4795         {0}
4796 };
4797 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4798
4799 static struct pci_driver iwl_driver = {
4800         .name = DRV_NAME,
4801         .id_table = iwl_hw_card_ids,
4802         .probe = iwl_pci_probe,
4803         .remove = __devexit_p(iwl_pci_remove),
4804 #ifdef CONFIG_PM
4805         .suspend = iwl_pci_suspend,
4806         .resume = iwl_pci_resume,
4807 #endif
4808 };
4809
4810 static int __init iwl_init(void)
4811 {
4812
4813         int ret;
4814         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4815         pr_info(DRV_COPYRIGHT "\n");
4816
4817         ret = iwlagn_rate_control_register();
4818         if (ret) {
4819                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4820                 return ret;
4821         }
4822
4823         ret = pci_register_driver(&iwl_driver);
4824         if (ret) {
4825                 pr_err("Unable to initialize PCI module\n");
4826                 goto error_register;
4827         }
4828
4829         return ret;
4830
4831 error_register:
4832         iwlagn_rate_control_unregister();
4833         return ret;
4834 }
4835
4836 static void __exit iwl_exit(void)
4837 {
4838         pci_unregister_driver(&iwl_driver);
4839         iwlagn_rate_control_unregister();
4840 }
4841
4842 module_exit(iwl_exit);
4843 module_init(iwl_init);
4844
4845 #ifdef CONFIG_IWLWIFI_DEBUG
4846 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4847 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4848 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4849 MODULE_PARM_DESC(debug, "debug output mask");
4850 #endif
4851
4852 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4853 MODULE_PARM_DESC(swcrypto50,
4854                  "using crypto in software (default 0 [hardware]) (deprecated)");
4855 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4856 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4857 module_param_named(queues_num50,
4858                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4859 MODULE_PARM_DESC(queues_num50,
4860                  "number of hw queues in 50xx series (deprecated)");
4861 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4862 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4863 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4864 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4865 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4866 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4867 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4868                    int, S_IRUGO);
4869 MODULE_PARM_DESC(amsdu_size_8K50,
4870                  "enable 8K amsdu size in 50XX series (deprecated)");
4871 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4872                    int, S_IRUGO);
4873 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4874 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4875 MODULE_PARM_DESC(fw_restart50,
4876                  "restart firmware in case of error (deprecated)");
4877 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4878 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4879 module_param_named(
4880         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4881 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4882
4883 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4884                    S_IRUGO);
4885 MODULE_PARM_DESC(ucode_alternative,
4886                  "specify ucode alternative to use from ucode file");
4887
4888 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4889 MODULE_PARM_DESC(antenna_coupling,
4890                  "specify antenna coupling in dB (defualt: 0 dB)");
4891
4892 module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4893 MODULE_PARM_DESC(bt_ch_announce,
4894                  "Enable BT channel announcement mode (default: enable)");