iwlagn: add feature flags
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project, as well
6  * as portions of the ieee80211 subsystem header files.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of version 2 of the GNU General Public License as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20  *
21  * The full GNU General Public License is included in this distribution in the
22  * file called LICENSE.
23  *
24  * Contact Information:
25  *  Intel Linux Wireless <ilw@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
47
48 #include <net/mac80211.h>
49
50 #include <asm/div64.h>
51
52 #define DRV_NAME        "iwlagn"
53
54 #include "iwl-eeprom.h"
55 #include "iwl-dev.h"
56 #include "iwl-core.h"
57 #include "iwl-io.h"
58 #include "iwl-helpers.h"
59 #include "iwl-sta.h"
60 #include "iwl-agn-calib.h"
61 #include "iwl-agn.h"
62 #include "iwl-agn-led.h"
63
64
65 /******************************************************************************
66  *
67  * module boiler plate
68  *
69  ******************************************************************************/
70
71 /*
72  * module name, copyright, version, etc.
73  */
74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
75
76 #ifdef CONFIG_IWLWIFI_DEBUG
77 #define VD "d"
78 #else
79 #define VD
80 #endif
81
82 #define DRV_VERSION     IWLWIFI_VERSION VD
83
84
85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
86 MODULE_VERSION(DRV_VERSION);
87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
88 MODULE_LICENSE("GPL");
89
90 static int iwlagn_ant_coupling;
91 static bool iwlagn_bt_ch_announce = 1;
92
93 void iwl_update_chain_flags(struct iwl_priv *priv)
94 {
95         struct iwl_rxon_context *ctx;
96
97         if (priv->cfg->ops->hcmd->set_rxon_chain) {
98                 for_each_context(priv, ctx) {
99                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
100                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
101                                 iwlcore_commit_rxon(priv, ctx);
102                 }
103         }
104 }
105
106 static void iwl_clear_free_frames(struct iwl_priv *priv)
107 {
108         struct list_head *element;
109
110         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
111                        priv->frames_count);
112
113         while (!list_empty(&priv->free_frames)) {
114                 element = priv->free_frames.next;
115                 list_del(element);
116                 kfree(list_entry(element, struct iwl_frame, list));
117                 priv->frames_count--;
118         }
119
120         if (priv->frames_count) {
121                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
122                             priv->frames_count);
123                 priv->frames_count = 0;
124         }
125 }
126
127 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
128 {
129         struct iwl_frame *frame;
130         struct list_head *element;
131         if (list_empty(&priv->free_frames)) {
132                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
133                 if (!frame) {
134                         IWL_ERR(priv, "Could not allocate frame!\n");
135                         return NULL;
136                 }
137
138                 priv->frames_count++;
139                 return frame;
140         }
141
142         element = priv->free_frames.next;
143         list_del(element);
144         return list_entry(element, struct iwl_frame, list);
145 }
146
147 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
148 {
149         memset(frame, 0, sizeof(*frame));
150         list_add(&frame->list, &priv->free_frames);
151 }
152
153 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
154                                  struct ieee80211_hdr *hdr,
155                                  int left)
156 {
157         lockdep_assert_held(&priv->mutex);
158
159         if (!priv->beacon_skb)
160                 return 0;
161
162         if (priv->beacon_skb->len > left)
163                 return 0;
164
165         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
166
167         return priv->beacon_skb->len;
168 }
169
170 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
171 static void iwl_set_beacon_tim(struct iwl_priv *priv,
172                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
173                                u8 *beacon, u32 frame_size)
174 {
175         u16 tim_idx;
176         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
177
178         /*
179          * The index is relative to frame start but we start looking at the
180          * variable-length part of the beacon.
181          */
182         tim_idx = mgmt->u.beacon.variable - beacon;
183
184         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
185         while ((tim_idx < (frame_size - 2)) &&
186                         (beacon[tim_idx] != WLAN_EID_TIM))
187                 tim_idx += beacon[tim_idx+1] + 2;
188
189         /* If TIM field was found, set variables */
190         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
191                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
192                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
193         } else
194                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
195 }
196
197 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
198                                        struct iwl_frame *frame)
199 {
200         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
201         u32 frame_size;
202         u32 rate_flags;
203         u32 rate;
204         /*
205          * We have to set up the TX command, the TX Beacon command, and the
206          * beacon contents.
207          */
208
209         lockdep_assert_held(&priv->mutex);
210
211         if (!priv->beacon_ctx) {
212                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
213                 return 0;
214         }
215
216         /* Initialize memory */
217         tx_beacon_cmd = &frame->u.beacon;
218         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
219
220         /* Set up TX beacon contents */
221         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
222                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
223         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
224                 return 0;
225         if (!frame_size)
226                 return 0;
227
228         /* Set up TX command fields */
229         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
230         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
231         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
232         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
233                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
234
235         /* Set up TX beacon command fields */
236         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
237                            frame_size);
238
239         /* Set up packet rate and flags */
240         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
241         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
242                                               priv->hw_params.valid_tx_ant);
243         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
244         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
245                 rate_flags |= RATE_MCS_CCK_MSK;
246         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
247                         rate_flags);
248
249         return sizeof(*tx_beacon_cmd) + frame_size;
250 }
251
252 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
253 {
254         struct iwl_frame *frame;
255         unsigned int frame_size;
256         int rc;
257
258         frame = iwl_get_free_frame(priv);
259         if (!frame) {
260                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
261                           "command.\n");
262                 return -ENOMEM;
263         }
264
265         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
266         if (!frame_size) {
267                 IWL_ERR(priv, "Error configuring the beacon command\n");
268                 iwl_free_frame(priv, frame);
269                 return -EINVAL;
270         }
271
272         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
273                               &frame->u.cmd[0]);
274
275         iwl_free_frame(priv, frame);
276
277         return rc;
278 }
279
280 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
281 {
282         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
283
284         dma_addr_t addr = get_unaligned_le32(&tb->lo);
285         if (sizeof(dma_addr_t) > sizeof(u32))
286                 addr |=
287                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
288
289         return addr;
290 }
291
292 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
293 {
294         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
295
296         return le16_to_cpu(tb->hi_n_len) >> 4;
297 }
298
299 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
300                                   dma_addr_t addr, u16 len)
301 {
302         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
303         u16 hi_n_len = len << 4;
304
305         put_unaligned_le32(addr, &tb->lo);
306         if (sizeof(dma_addr_t) > sizeof(u32))
307                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
308
309         tb->hi_n_len = cpu_to_le16(hi_n_len);
310
311         tfd->num_tbs = idx + 1;
312 }
313
314 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
315 {
316         return tfd->num_tbs & 0x1f;
317 }
318
319 /**
320  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
321  * @priv - driver private data
322  * @txq - tx queue
323  *
324  * Does NOT advance any TFD circular buffer read/write indexes
325  * Does NOT free the TFD itself (which is within circular buffer)
326  */
327 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
328 {
329         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
330         struct iwl_tfd *tfd;
331         struct pci_dev *dev = priv->pci_dev;
332         int index = txq->q.read_ptr;
333         int i;
334         int num_tbs;
335
336         tfd = &tfd_tmp[index];
337
338         /* Sanity check on number of chunks */
339         num_tbs = iwl_tfd_get_num_tbs(tfd);
340
341         if (num_tbs >= IWL_NUM_OF_TBS) {
342                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
343                 /* @todo issue fatal error, it is quite serious situation */
344                 return;
345         }
346
347         /* Unmap tx_cmd */
348         if (num_tbs)
349                 pci_unmap_single(dev,
350                                 dma_unmap_addr(&txq->meta[index], mapping),
351                                 dma_unmap_len(&txq->meta[index], len),
352                                 PCI_DMA_BIDIRECTIONAL);
353
354         /* Unmap chunks, if any. */
355         for (i = 1; i < num_tbs; i++)
356                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
357                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
358
359         /* free SKB */
360         if (txq->txb) {
361                 struct sk_buff *skb;
362
363                 skb = txq->txb[txq->q.read_ptr].skb;
364
365                 /* can be called from irqs-disabled context */
366                 if (skb) {
367                         dev_kfree_skb_any(skb);
368                         txq->txb[txq->q.read_ptr].skb = NULL;
369                 }
370         }
371 }
372
373 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
374                                  struct iwl_tx_queue *txq,
375                                  dma_addr_t addr, u16 len,
376                                  u8 reset, u8 pad)
377 {
378         struct iwl_queue *q;
379         struct iwl_tfd *tfd, *tfd_tmp;
380         u32 num_tbs;
381
382         q = &txq->q;
383         tfd_tmp = (struct iwl_tfd *)txq->tfds;
384         tfd = &tfd_tmp[q->write_ptr];
385
386         if (reset)
387                 memset(tfd, 0, sizeof(*tfd));
388
389         num_tbs = iwl_tfd_get_num_tbs(tfd);
390
391         /* Each TFD can point to a maximum 20 Tx buffers */
392         if (num_tbs >= IWL_NUM_OF_TBS) {
393                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
394                           IWL_NUM_OF_TBS);
395                 return -EINVAL;
396         }
397
398         BUG_ON(addr & ~DMA_BIT_MASK(36));
399         if (unlikely(addr & ~IWL_TX_DMA_MASK))
400                 IWL_ERR(priv, "Unaligned address = %llx\n",
401                           (unsigned long long)addr);
402
403         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
404
405         return 0;
406 }
407
408 /*
409  * Tell nic where to find circular buffer of Tx Frame Descriptors for
410  * given Tx queue, and enable the DMA channel used for that queue.
411  *
412  * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
413  * channels supported in hardware.
414  */
415 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
416                          struct iwl_tx_queue *txq)
417 {
418         int txq_id = txq->q.id;
419
420         /* Circular buffer (TFD queue in DRAM) physical base address */
421         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
422                              txq->q.dma_addr >> 8);
423
424         return 0;
425 }
426
427 static void iwl_bg_beacon_update(struct work_struct *work)
428 {
429         struct iwl_priv *priv =
430                 container_of(work, struct iwl_priv, beacon_update);
431         struct sk_buff *beacon;
432
433         mutex_lock(&priv->mutex);
434         if (!priv->beacon_ctx) {
435                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
436                 goto out;
437         }
438
439         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
440                 /*
441                  * The ucode will send beacon notifications even in
442                  * IBSS mode, but we don't want to process them. But
443                  * we need to defer the type check to here due to
444                  * requiring locking around the beacon_ctx access.
445                  */
446                 goto out;
447         }
448
449         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
450         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
451         if (!beacon) {
452                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
453                 goto out;
454         }
455
456         /* new beacon skb is allocated every time; dispose previous.*/
457         dev_kfree_skb(priv->beacon_skb);
458
459         priv->beacon_skb = beacon;
460
461         iwlagn_send_beacon_cmd(priv);
462  out:
463         mutex_unlock(&priv->mutex);
464 }
465
466 static void iwl_bg_bt_runtime_config(struct work_struct *work)
467 {
468         struct iwl_priv *priv =
469                 container_of(work, struct iwl_priv, bt_runtime_config);
470
471         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
472                 return;
473
474         /* dont send host command if rf-kill is on */
475         if (!iwl_is_ready_rf(priv))
476                 return;
477         priv->cfg->ops->hcmd->send_bt_config(priv);
478 }
479
480 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
481 {
482         struct iwl_priv *priv =
483                 container_of(work, struct iwl_priv, bt_full_concurrency);
484         struct iwl_rxon_context *ctx;
485
486         mutex_lock(&priv->mutex);
487
488         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
489                 goto out;
490
491         /* dont send host command if rf-kill is on */
492         if (!iwl_is_ready_rf(priv))
493                 goto out;
494
495         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
496                        priv->bt_full_concurrent ?
497                        "full concurrency" : "3-wire");
498
499         /*
500          * LQ & RXON updated cmds must be sent before BT Config cmd
501          * to avoid 3-wire collisions
502          */
503         for_each_context(priv, ctx) {
504                 if (priv->cfg->ops->hcmd->set_rxon_chain)
505                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
506                 iwlcore_commit_rxon(priv, ctx);
507         }
508
509         priv->cfg->ops->hcmd->send_bt_config(priv);
510 out:
511         mutex_unlock(&priv->mutex);
512 }
513
514 /**
515  * iwl_bg_statistics_periodic - Timer callback to queue statistics
516  *
517  * This callback is provided in order to send a statistics request.
518  *
519  * This timer function is continually reset to execute within
520  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
521  * was received.  We need to ensure we receive the statistics in order
522  * to update the temperature used for calibrating the TXPOWER.
523  */
524 static void iwl_bg_statistics_periodic(unsigned long data)
525 {
526         struct iwl_priv *priv = (struct iwl_priv *)data;
527
528         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
529                 return;
530
531         /* dont send host command if rf-kill is on */
532         if (!iwl_is_ready_rf(priv))
533                 return;
534
535         iwl_send_statistics_request(priv, CMD_ASYNC, false);
536 }
537
538
539 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
540                                         u32 start_idx, u32 num_events,
541                                         u32 mode)
542 {
543         u32 i;
544         u32 ptr;        /* SRAM byte address of log data */
545         u32 ev, time, data; /* event log data */
546         unsigned long reg_flags;
547
548         if (mode == 0)
549                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
550         else
551                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
552
553         /* Make sure device is powered up for SRAM reads */
554         spin_lock_irqsave(&priv->reg_lock, reg_flags);
555         if (iwl_grab_nic_access(priv)) {
556                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
557                 return;
558         }
559
560         /* Set starting address; reads will auto-increment */
561         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
562         rmb();
563
564         /*
565          * "time" is actually "data" for mode 0 (no timestamp).
566          * place event id # at far right for easier visual parsing.
567          */
568         for (i = 0; i < num_events; i++) {
569                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
570                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
571                 if (mode == 0) {
572                         trace_iwlwifi_dev_ucode_cont_event(priv,
573                                                         0, time, ev);
574                 } else {
575                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
576                         trace_iwlwifi_dev_ucode_cont_event(priv,
577                                                 time, data, ev);
578                 }
579         }
580         /* Allow device to power down */
581         iwl_release_nic_access(priv);
582         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
583 }
584
585 static void iwl_continuous_event_trace(struct iwl_priv *priv)
586 {
587         u32 capacity;   /* event log capacity in # entries */
588         u32 base;       /* SRAM byte address of event log header */
589         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
590         u32 num_wraps;  /* # times uCode wrapped to top of log */
591         u32 next_entry; /* index of next entry to be written by uCode */
592
593         if (priv->ucode_type == UCODE_INIT)
594                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
595         else
596                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
597         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
598                 capacity = iwl_read_targ_mem(priv, base);
599                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
600                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
601                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
602         } else
603                 return;
604
605         if (num_wraps == priv->event_log.num_wraps) {
606                 iwl_print_cont_event_trace(priv,
607                                        base, priv->event_log.next_entry,
608                                        next_entry - priv->event_log.next_entry,
609                                        mode);
610                 priv->event_log.non_wraps_count++;
611         } else {
612                 if ((num_wraps - priv->event_log.num_wraps) > 1)
613                         priv->event_log.wraps_more_count++;
614                 else
615                         priv->event_log.wraps_once_count++;
616                 trace_iwlwifi_dev_ucode_wrap_event(priv,
617                                 num_wraps - priv->event_log.num_wraps,
618                                 next_entry, priv->event_log.next_entry);
619                 if (next_entry < priv->event_log.next_entry) {
620                         iwl_print_cont_event_trace(priv, base,
621                                priv->event_log.next_entry,
622                                capacity - priv->event_log.next_entry,
623                                mode);
624
625                         iwl_print_cont_event_trace(priv, base, 0,
626                                 next_entry, mode);
627                 } else {
628                         iwl_print_cont_event_trace(priv, base,
629                                next_entry, capacity - next_entry,
630                                mode);
631
632                         iwl_print_cont_event_trace(priv, base, 0,
633                                 next_entry, mode);
634                 }
635         }
636         priv->event_log.num_wraps = num_wraps;
637         priv->event_log.next_entry = next_entry;
638 }
639
640 /**
641  * iwl_bg_ucode_trace - Timer callback to log ucode event
642  *
643  * The timer is continually set to execute every
644  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
645  * this function is to perform continuous uCode event logging operation
646  * if enabled
647  */
648 static void iwl_bg_ucode_trace(unsigned long data)
649 {
650         struct iwl_priv *priv = (struct iwl_priv *)data;
651
652         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
653                 return;
654
655         if (priv->event_log.ucode_trace) {
656                 iwl_continuous_event_trace(priv);
657                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
658                 mod_timer(&priv->ucode_trace,
659                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
660         }
661 }
662
663 static void iwl_bg_tx_flush(struct work_struct *work)
664 {
665         struct iwl_priv *priv =
666                 container_of(work, struct iwl_priv, tx_flush);
667
668         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
669                 return;
670
671         /* do nothing if rf-kill is on */
672         if (!iwl_is_ready_rf(priv))
673                 return;
674
675         if (priv->cfg->ops->lib->txfifo_flush) {
676                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
677                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
678         }
679 }
680
681 /**
682  * iwl_rx_handle - Main entry function for receiving responses from uCode
683  *
684  * Uses the priv->rx_handlers callback function array to invoke
685  * the appropriate handlers, including command responses,
686  * frame-received notifications, and other notifications.
687  */
688 static void iwl_rx_handle(struct iwl_priv *priv)
689 {
690         struct iwl_rx_mem_buffer *rxb;
691         struct iwl_rx_packet *pkt;
692         struct iwl_rx_queue *rxq = &priv->rxq;
693         u32 r, i;
694         int reclaim;
695         unsigned long flags;
696         u8 fill_rx = 0;
697         u32 count = 8;
698         int total_empty;
699
700         /* uCode's read index (stored in shared DRAM) indicates the last Rx
701          * buffer that the driver may process (last buffer filled by ucode). */
702         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
703         i = rxq->read;
704
705         /* Rx interrupt, but nothing sent from uCode */
706         if (i == r)
707                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
708
709         /* calculate total frames need to be restock after handling RX */
710         total_empty = r - rxq->write_actual;
711         if (total_empty < 0)
712                 total_empty += RX_QUEUE_SIZE;
713
714         if (total_empty > (RX_QUEUE_SIZE / 2))
715                 fill_rx = 1;
716
717         while (i != r) {
718                 int len;
719
720                 rxb = rxq->queue[i];
721
722                 /* If an RXB doesn't have a Rx queue slot associated with it,
723                  * then a bug has been introduced in the queue refilling
724                  * routines -- catch it here */
725                 BUG_ON(rxb == NULL);
726
727                 rxq->queue[i] = NULL;
728
729                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
730                                PAGE_SIZE << priv->hw_params.rx_page_order,
731                                PCI_DMA_FROMDEVICE);
732                 pkt = rxb_addr(rxb);
733
734                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
735                 len += sizeof(u32); /* account for status word */
736                 trace_iwlwifi_dev_rx(priv, pkt, len);
737
738                 /* Reclaim a command buffer only if this packet is a response
739                  *   to a (driver-originated) command.
740                  * If the packet (e.g. Rx frame) originated from uCode,
741                  *   there is no command buffer to reclaim.
742                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
743                  *   but apparently a few don't get set; catch them here. */
744                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
745                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
746                         (pkt->hdr.cmd != REPLY_RX) &&
747                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
748                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
749                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
750                         (pkt->hdr.cmd != REPLY_TX);
751
752                 /*
753                  * Do the notification wait before RX handlers so
754                  * even if the RX handler consumes the RXB we have
755                  * access to it in the notification wait entry.
756                  */
757                 if (!list_empty(&priv->_agn.notif_waits)) {
758                         struct iwl_notification_wait *w;
759
760                         spin_lock(&priv->_agn.notif_wait_lock);
761                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
762                                 if (w->cmd == pkt->hdr.cmd) {
763                                         w->triggered = true;
764                                         if (w->fn)
765                                                 w->fn(priv, pkt);
766                                 }
767                         }
768                         spin_unlock(&priv->_agn.notif_wait_lock);
769
770                         wake_up_all(&priv->_agn.notif_waitq);
771                 }
772
773                 /* Based on type of command response or notification,
774                  *   handle those that need handling via function in
775                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
776                 if (priv->rx_handlers[pkt->hdr.cmd]) {
777                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
778                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
779                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
780                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
781                 } else {
782                         /* No handling needed */
783                         IWL_DEBUG_RX(priv,
784                                 "r %d i %d No handler needed for %s, 0x%02x\n",
785                                 r, i, get_cmd_string(pkt->hdr.cmd),
786                                 pkt->hdr.cmd);
787                 }
788
789                 /*
790                  * XXX: After here, we should always check rxb->page
791                  * against NULL before touching it or its virtual
792                  * memory (pkt). Because some rx_handler might have
793                  * already taken or freed the pages.
794                  */
795
796                 if (reclaim) {
797                         /* Invoke any callbacks, transfer the buffer to caller,
798                          * and fire off the (possibly) blocking iwl_send_cmd()
799                          * as we reclaim the driver command queue */
800                         if (rxb->page)
801                                 iwl_tx_cmd_complete(priv, rxb);
802                         else
803                                 IWL_WARN(priv, "Claim null rxb?\n");
804                 }
805
806                 /* Reuse the page if possible. For notification packets and
807                  * SKBs that fail to Rx correctly, add them back into the
808                  * rx_free list for reuse later. */
809                 spin_lock_irqsave(&rxq->lock, flags);
810                 if (rxb->page != NULL) {
811                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
812                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
813                                 PCI_DMA_FROMDEVICE);
814                         list_add_tail(&rxb->list, &rxq->rx_free);
815                         rxq->free_count++;
816                 } else
817                         list_add_tail(&rxb->list, &rxq->rx_used);
818
819                 spin_unlock_irqrestore(&rxq->lock, flags);
820
821                 i = (i + 1) & RX_QUEUE_MASK;
822                 /* If there are a lot of unused frames,
823                  * restock the Rx queue so ucode wont assert. */
824                 if (fill_rx) {
825                         count++;
826                         if (count >= 8) {
827                                 rxq->read = i;
828                                 iwlagn_rx_replenish_now(priv);
829                                 count = 0;
830                         }
831                 }
832         }
833
834         /* Backtrack one entry */
835         rxq->read = i;
836         if (fill_rx)
837                 iwlagn_rx_replenish_now(priv);
838         else
839                 iwlagn_rx_queue_restock(priv);
840 }
841
842 /* call this function to flush any scheduled tasklet */
843 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
844 {
845         /* wait to make sure we flush pending tasklet*/
846         synchronize_irq(priv->pci_dev->irq);
847         tasklet_kill(&priv->irq_tasklet);
848 }
849
850 /* tasklet for iwlagn interrupt */
851 static void iwl_irq_tasklet(struct iwl_priv *priv)
852 {
853         u32 inta = 0;
854         u32 handled = 0;
855         unsigned long flags;
856         u32 i;
857 #ifdef CONFIG_IWLWIFI_DEBUG
858         u32 inta_mask;
859 #endif
860
861         spin_lock_irqsave(&priv->lock, flags);
862
863         /* Ack/clear/reset pending uCode interrupts.
864          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
865          */
866         /* There is a hardware bug in the interrupt mask function that some
867          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
868          * they are disabled in the CSR_INT_MASK register. Furthermore the
869          * ICT interrupt handling mechanism has another bug that might cause
870          * these unmasked interrupts fail to be detected. We workaround the
871          * hardware bugs here by ACKing all the possible interrupts so that
872          * interrupt coalescing can still be achieved.
873          */
874         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
875
876         inta = priv->_agn.inta;
877
878 #ifdef CONFIG_IWLWIFI_DEBUG
879         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
880                 /* just for debug */
881                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
882                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
883                                 inta, inta_mask);
884         }
885 #endif
886
887         spin_unlock_irqrestore(&priv->lock, flags);
888
889         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
890         priv->_agn.inta = 0;
891
892         /* Now service all interrupt bits discovered above. */
893         if (inta & CSR_INT_BIT_HW_ERR) {
894                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
895
896                 /* Tell the device to stop sending interrupts */
897                 iwl_disable_interrupts(priv);
898
899                 priv->isr_stats.hw++;
900                 iwl_irq_handle_error(priv);
901
902                 handled |= CSR_INT_BIT_HW_ERR;
903
904                 return;
905         }
906
907 #ifdef CONFIG_IWLWIFI_DEBUG
908         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
909                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
910                 if (inta & CSR_INT_BIT_SCD) {
911                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
912                                       "the frame/frames.\n");
913                         priv->isr_stats.sch++;
914                 }
915
916                 /* Alive notification via Rx interrupt will do the real work */
917                 if (inta & CSR_INT_BIT_ALIVE) {
918                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
919                         priv->isr_stats.alive++;
920                 }
921         }
922 #endif
923         /* Safely ignore these bits for debug checks below */
924         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
925
926         /* HW RF KILL switch toggled */
927         if (inta & CSR_INT_BIT_RF_KILL) {
928                 int hw_rf_kill = 0;
929                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
930                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
931                         hw_rf_kill = 1;
932
933                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
934                                 hw_rf_kill ? "disable radio" : "enable radio");
935
936                 priv->isr_stats.rfkill++;
937
938                 /* driver only loads ucode once setting the interface up.
939                  * the driver allows loading the ucode even if the radio
940                  * is killed. Hence update the killswitch state here. The
941                  * rfkill handler will care about restarting if needed.
942                  */
943                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
944                         if (hw_rf_kill)
945                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
946                         else
947                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
948                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
949                 }
950
951                 handled |= CSR_INT_BIT_RF_KILL;
952         }
953
954         /* Chip got too hot and stopped itself */
955         if (inta & CSR_INT_BIT_CT_KILL) {
956                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
957                 priv->isr_stats.ctkill++;
958                 handled |= CSR_INT_BIT_CT_KILL;
959         }
960
961         /* Error detected by uCode */
962         if (inta & CSR_INT_BIT_SW_ERR) {
963                 IWL_ERR(priv, "Microcode SW error detected. "
964                         " Restarting 0x%X.\n", inta);
965                 priv->isr_stats.sw++;
966                 iwl_irq_handle_error(priv);
967                 handled |= CSR_INT_BIT_SW_ERR;
968         }
969
970         /* uCode wakes up after power-down sleep */
971         if (inta & CSR_INT_BIT_WAKEUP) {
972                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
973                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
974                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
975                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
976
977                 priv->isr_stats.wakeup++;
978
979                 handled |= CSR_INT_BIT_WAKEUP;
980         }
981
982         /* All uCode command responses, including Tx command responses,
983          * Rx "responses" (frame-received notification), and other
984          * notifications from uCode come through here*/
985         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
986                         CSR_INT_BIT_RX_PERIODIC)) {
987                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
988                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
989                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
990                         iwl_write32(priv, CSR_FH_INT_STATUS,
991                                         CSR_FH_INT_RX_MASK);
992                 }
993                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
994                         handled |= CSR_INT_BIT_RX_PERIODIC;
995                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
996                 }
997                 /* Sending RX interrupt require many steps to be done in the
998                  * the device:
999                  * 1- write interrupt to current index in ICT table.
1000                  * 2- dma RX frame.
1001                  * 3- update RX shared data to indicate last write index.
1002                  * 4- send interrupt.
1003                  * This could lead to RX race, driver could receive RX interrupt
1004                  * but the shared data changes does not reflect this;
1005                  * periodic interrupt will detect any dangling Rx activity.
1006                  */
1007
1008                 /* Disable periodic interrupt; we use it as just a one-shot. */
1009                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1010                             CSR_INT_PERIODIC_DIS);
1011                 iwl_rx_handle(priv);
1012
1013                 /*
1014                  * Enable periodic interrupt in 8 msec only if we received
1015                  * real RX interrupt (instead of just periodic int), to catch
1016                  * any dangling Rx interrupt.  If it was just the periodic
1017                  * interrupt, there was no dangling Rx activity, and no need
1018                  * to extend the periodic interrupt; one-shot is enough.
1019                  */
1020                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1021                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1022                                     CSR_INT_PERIODIC_ENA);
1023
1024                 priv->isr_stats.rx++;
1025         }
1026
1027         /* This "Tx" DMA channel is used only for loading uCode */
1028         if (inta & CSR_INT_BIT_FH_TX) {
1029                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1030                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1031                 priv->isr_stats.tx++;
1032                 handled |= CSR_INT_BIT_FH_TX;
1033                 /* Wake up uCode load routine, now that load is complete */
1034                 priv->ucode_write_complete = 1;
1035                 wake_up_interruptible(&priv->wait_command_queue);
1036         }
1037
1038         if (inta & ~handled) {
1039                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1040                 priv->isr_stats.unhandled++;
1041         }
1042
1043         if (inta & ~(priv->inta_mask)) {
1044                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1045                          inta & ~priv->inta_mask);
1046         }
1047
1048         /* Re-enable all interrupts */
1049         /* only Re-enable if disabled by irq */
1050         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1051                 iwl_enable_interrupts(priv);
1052         /* Re-enable RF_KILL if it occurred */
1053         else if (handled & CSR_INT_BIT_RF_KILL)
1054                 iwl_enable_rfkill_int(priv);
1055 }
1056
1057 /*****************************************************************************
1058  *
1059  * sysfs attributes
1060  *
1061  *****************************************************************************/
1062
1063 #ifdef CONFIG_IWLWIFI_DEBUG
1064
1065 /*
1066  * The following adds a new attribute to the sysfs representation
1067  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1068  * used for controlling the debug level.
1069  *
1070  * See the level definitions in iwl for details.
1071  *
1072  * The debug_level being managed using sysfs below is a per device debug
1073  * level that is used instead of the global debug level if it (the per
1074  * device debug level) is set.
1075  */
1076 static ssize_t show_debug_level(struct device *d,
1077                                 struct device_attribute *attr, char *buf)
1078 {
1079         struct iwl_priv *priv = dev_get_drvdata(d);
1080         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1081 }
1082 static ssize_t store_debug_level(struct device *d,
1083                                 struct device_attribute *attr,
1084                                  const char *buf, size_t count)
1085 {
1086         struct iwl_priv *priv = dev_get_drvdata(d);
1087         unsigned long val;
1088         int ret;
1089
1090         ret = strict_strtoul(buf, 0, &val);
1091         if (ret)
1092                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1093         else {
1094                 priv->debug_level = val;
1095                 if (iwl_alloc_traffic_mem(priv))
1096                         IWL_ERR(priv,
1097                                 "Not enough memory to generate traffic log\n");
1098         }
1099         return strnlen(buf, count);
1100 }
1101
1102 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1103                         show_debug_level, store_debug_level);
1104
1105
1106 #endif /* CONFIG_IWLWIFI_DEBUG */
1107
1108
1109 static ssize_t show_temperature(struct device *d,
1110                                 struct device_attribute *attr, char *buf)
1111 {
1112         struct iwl_priv *priv = dev_get_drvdata(d);
1113
1114         if (!iwl_is_alive(priv))
1115                 return -EAGAIN;
1116
1117         return sprintf(buf, "%d\n", priv->temperature);
1118 }
1119
1120 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1121
1122 static ssize_t show_tx_power(struct device *d,
1123                              struct device_attribute *attr, char *buf)
1124 {
1125         struct iwl_priv *priv = dev_get_drvdata(d);
1126
1127         if (!iwl_is_ready_rf(priv))
1128                 return sprintf(buf, "off\n");
1129         else
1130                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1131 }
1132
1133 static ssize_t store_tx_power(struct device *d,
1134                               struct device_attribute *attr,
1135                               const char *buf, size_t count)
1136 {
1137         struct iwl_priv *priv = dev_get_drvdata(d);
1138         unsigned long val;
1139         int ret;
1140
1141         ret = strict_strtoul(buf, 10, &val);
1142         if (ret)
1143                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1144         else {
1145                 ret = iwl_set_tx_power(priv, val, false);
1146                 if (ret)
1147                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1148                                 ret);
1149                 else
1150                         ret = count;
1151         }
1152         return ret;
1153 }
1154
1155 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1156
1157 static struct attribute *iwl_sysfs_entries[] = {
1158         &dev_attr_temperature.attr,
1159         &dev_attr_tx_power.attr,
1160 #ifdef CONFIG_IWLWIFI_DEBUG
1161         &dev_attr_debug_level.attr,
1162 #endif
1163         NULL
1164 };
1165
1166 static struct attribute_group iwl_attribute_group = {
1167         .name = NULL,           /* put in device directory */
1168         .attrs = iwl_sysfs_entries,
1169 };
1170
1171 /******************************************************************************
1172  *
1173  * uCode download functions
1174  *
1175  ******************************************************************************/
1176
1177 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1178 {
1179         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1180         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1181         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1182         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1183 }
1184
1185 static void iwl_nic_start(struct iwl_priv *priv)
1186 {
1187         /* Remove all resets to allow NIC to operate */
1188         iwl_write32(priv, CSR_RESET, 0);
1189 }
1190
1191 struct iwlagn_ucode_capabilities {
1192         u32 max_probe_length;
1193         u32 standard_phy_calibration_size;
1194         u32 flags;
1195 };
1196
1197 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1198 static int iwl_mac_setup_register(struct iwl_priv *priv,
1199                                   struct iwlagn_ucode_capabilities *capa);
1200
1201 #define UCODE_EXPERIMENTAL_INDEX        100
1202 #define UCODE_EXPERIMENTAL_TAG          "exp"
1203
1204 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1205 {
1206         const char *name_pre = priv->cfg->fw_name_pre;
1207         char tag[8];
1208
1209         if (first) {
1210 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1211                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1212                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1213         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1214 #endif
1215                 priv->fw_index = priv->cfg->ucode_api_max;
1216                 sprintf(tag, "%d", priv->fw_index);
1217         } else {
1218                 priv->fw_index--;
1219                 sprintf(tag, "%d", priv->fw_index);
1220         }
1221
1222         if (priv->fw_index < priv->cfg->ucode_api_min) {
1223                 IWL_ERR(priv, "no suitable firmware found!\n");
1224                 return -ENOENT;
1225         }
1226
1227         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1228
1229         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1230                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1231                                 ? "EXPERIMENTAL " : "",
1232                        priv->firmware_name);
1233
1234         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1235                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1236                                        iwl_ucode_callback);
1237 }
1238
1239 struct iwlagn_firmware_pieces {
1240         const void *inst, *data, *init, *init_data;
1241         size_t inst_size, data_size, init_size, init_data_size;
1242
1243         u32 build;
1244
1245         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1246         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1247 };
1248
1249 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1250                                        const struct firmware *ucode_raw,
1251                                        struct iwlagn_firmware_pieces *pieces)
1252 {
1253         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1254         u32 api_ver, hdr_size;
1255         const u8 *src;
1256
1257         priv->ucode_ver = le32_to_cpu(ucode->ver);
1258         api_ver = IWL_UCODE_API(priv->ucode_ver);
1259
1260         switch (api_ver) {
1261         default:
1262                 hdr_size = 28;
1263                 if (ucode_raw->size < hdr_size) {
1264                         IWL_ERR(priv, "File size too small!\n");
1265                         return -EINVAL;
1266                 }
1267                 pieces->build = le32_to_cpu(ucode->u.v2.build);
1268                 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1269                 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1270                 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1271                 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1272                 src = ucode->u.v2.data;
1273                 break;
1274         case 0:
1275         case 1:
1276         case 2:
1277                 hdr_size = 24;
1278                 if (ucode_raw->size < hdr_size) {
1279                         IWL_ERR(priv, "File size too small!\n");
1280                         return -EINVAL;
1281                 }
1282                 pieces->build = 0;
1283                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1284                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1285                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1286                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1287                 src = ucode->u.v1.data;
1288                 break;
1289         }
1290
1291         /* Verify size of file vs. image size info in file's header */
1292         if (ucode_raw->size != hdr_size + pieces->inst_size +
1293                                 pieces->data_size + pieces->init_size +
1294                                 pieces->init_data_size) {
1295
1296                 IWL_ERR(priv,
1297                         "uCode file size %d does not match expected size\n",
1298                         (int)ucode_raw->size);
1299                 return -EINVAL;
1300         }
1301
1302         pieces->inst = src;
1303         src += pieces->inst_size;
1304         pieces->data = src;
1305         src += pieces->data_size;
1306         pieces->init = src;
1307         src += pieces->init_size;
1308         pieces->init_data = src;
1309         src += pieces->init_data_size;
1310
1311         return 0;
1312 }
1313
1314 static int iwlagn_wanted_ucode_alternative = 1;
1315
1316 static int iwlagn_load_firmware(struct iwl_priv *priv,
1317                                 const struct firmware *ucode_raw,
1318                                 struct iwlagn_firmware_pieces *pieces,
1319                                 struct iwlagn_ucode_capabilities *capa)
1320 {
1321         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1322         struct iwl_ucode_tlv *tlv;
1323         size_t len = ucode_raw->size;
1324         const u8 *data;
1325         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1326         u64 alternatives;
1327         u32 tlv_len;
1328         enum iwl_ucode_tlv_type tlv_type;
1329         const u8 *tlv_data;
1330
1331         if (len < sizeof(*ucode)) {
1332                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1333                 return -EINVAL;
1334         }
1335
1336         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1337                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1338                         le32_to_cpu(ucode->magic));
1339                 return -EINVAL;
1340         }
1341
1342         /*
1343          * Check which alternatives are present, and "downgrade"
1344          * when the chosen alternative is not present, warning
1345          * the user when that happens. Some files may not have
1346          * any alternatives, so don't warn in that case.
1347          */
1348         alternatives = le64_to_cpu(ucode->alternatives);
1349         tmp = wanted_alternative;
1350         if (wanted_alternative > 63)
1351                 wanted_alternative = 63;
1352         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1353                 wanted_alternative--;
1354         if (wanted_alternative && wanted_alternative != tmp)
1355                 IWL_WARN(priv,
1356                          "uCode alternative %d not available, choosing %d\n",
1357                          tmp, wanted_alternative);
1358
1359         priv->ucode_ver = le32_to_cpu(ucode->ver);
1360         pieces->build = le32_to_cpu(ucode->build);
1361         data = ucode->data;
1362
1363         len -= sizeof(*ucode);
1364
1365         while (len >= sizeof(*tlv)) {
1366                 u16 tlv_alt;
1367
1368                 len -= sizeof(*tlv);
1369                 tlv = (void *)data;
1370
1371                 tlv_len = le32_to_cpu(tlv->length);
1372                 tlv_type = le16_to_cpu(tlv->type);
1373                 tlv_alt = le16_to_cpu(tlv->alternative);
1374                 tlv_data = tlv->data;
1375
1376                 if (len < tlv_len) {
1377                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1378                                 len, tlv_len);
1379                         return -EINVAL;
1380                 }
1381                 len -= ALIGN(tlv_len, 4);
1382                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1383
1384                 /*
1385                  * Alternative 0 is always valid.
1386                  *
1387                  * Skip alternative TLVs that are not selected.
1388                  */
1389                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1390                         continue;
1391
1392                 switch (tlv_type) {
1393                 case IWL_UCODE_TLV_INST:
1394                         pieces->inst = tlv_data;
1395                         pieces->inst_size = tlv_len;
1396                         break;
1397                 case IWL_UCODE_TLV_DATA:
1398                         pieces->data = tlv_data;
1399                         pieces->data_size = tlv_len;
1400                         break;
1401                 case IWL_UCODE_TLV_INIT:
1402                         pieces->init = tlv_data;
1403                         pieces->init_size = tlv_len;
1404                         break;
1405                 case IWL_UCODE_TLV_INIT_DATA:
1406                         pieces->init_data = tlv_data;
1407                         pieces->init_data_size = tlv_len;
1408                         break;
1409                 case IWL_UCODE_TLV_BOOT:
1410                         IWL_ERR(priv, "Found unexpected BOOT ucode\n");
1411                         break;
1412                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1413                         if (tlv_len != sizeof(u32))
1414                                 goto invalid_tlv_len;
1415                         capa->max_probe_length =
1416                                         le32_to_cpup((__le32 *)tlv_data);
1417                         break;
1418                 case IWL_UCODE_TLV_PAN:
1419                         if (tlv_len)
1420                                 goto invalid_tlv_len;
1421                         capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
1422                         break;
1423                 case IWL_UCODE_TLV_FLAGS:
1424                         /* must be at least one u32 */
1425                         if (tlv_len < sizeof(u32))
1426                                 goto invalid_tlv_len;
1427                         /* and a proper number of u32s */
1428                         if (tlv_len % sizeof(u32))
1429                                 goto invalid_tlv_len;
1430                         /*
1431                          * This driver only reads the first u32 as
1432                          * right now no more features are defined,
1433                          * if that changes then either the driver
1434                          * will not work with the new firmware, or
1435                          * it'll not take advantage of new features.
1436                          */
1437                         capa->flags = le32_to_cpup((__le32 *)tlv_data);
1438                         break;
1439                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1440                         if (tlv_len != sizeof(u32))
1441                                 goto invalid_tlv_len;
1442                         pieces->init_evtlog_ptr =
1443                                         le32_to_cpup((__le32 *)tlv_data);
1444                         break;
1445                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1446                         if (tlv_len != sizeof(u32))
1447                                 goto invalid_tlv_len;
1448                         pieces->init_evtlog_size =
1449                                         le32_to_cpup((__le32 *)tlv_data);
1450                         break;
1451                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1452                         if (tlv_len != sizeof(u32))
1453                                 goto invalid_tlv_len;
1454                         pieces->init_errlog_ptr =
1455                                         le32_to_cpup((__le32 *)tlv_data);
1456                         break;
1457                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1458                         if (tlv_len != sizeof(u32))
1459                                 goto invalid_tlv_len;
1460                         pieces->inst_evtlog_ptr =
1461                                         le32_to_cpup((__le32 *)tlv_data);
1462                         break;
1463                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1464                         if (tlv_len != sizeof(u32))
1465                                 goto invalid_tlv_len;
1466                         pieces->inst_evtlog_size =
1467                                         le32_to_cpup((__le32 *)tlv_data);
1468                         break;
1469                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1470                         if (tlv_len != sizeof(u32))
1471                                 goto invalid_tlv_len;
1472                         pieces->inst_errlog_ptr =
1473                                         le32_to_cpup((__le32 *)tlv_data);
1474                         break;
1475                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1476                         if (tlv_len)
1477                                 goto invalid_tlv_len;
1478                         priv->enhance_sensitivity_table = true;
1479                         break;
1480                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1481                         if (tlv_len != sizeof(u32))
1482                                 goto invalid_tlv_len;
1483                         capa->standard_phy_calibration_size =
1484                                         le32_to_cpup((__le32 *)tlv_data);
1485                         break;
1486                 default:
1487                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1488                         break;
1489                 }
1490         }
1491
1492         if (len) {
1493                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1494                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1495                 return -EINVAL;
1496         }
1497
1498         return 0;
1499
1500  invalid_tlv_len:
1501         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1502         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1503
1504         return -EINVAL;
1505 }
1506
1507 /**
1508  * iwl_ucode_callback - callback when firmware was loaded
1509  *
1510  * If loaded successfully, copies the firmware into buffers
1511  * for the card to fetch (via DMA).
1512  */
1513 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1514 {
1515         struct iwl_priv *priv = context;
1516         struct iwl_ucode_header *ucode;
1517         int err;
1518         struct iwlagn_firmware_pieces pieces;
1519         const unsigned int api_max = priv->cfg->ucode_api_max;
1520         const unsigned int api_min = priv->cfg->ucode_api_min;
1521         u32 api_ver;
1522         char buildstr[25];
1523         u32 build;
1524         struct iwlagn_ucode_capabilities ucode_capa = {
1525                 .max_probe_length = 200,
1526                 .standard_phy_calibration_size =
1527                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1528         };
1529
1530         memset(&pieces, 0, sizeof(pieces));
1531
1532         if (!ucode_raw) {
1533                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1534                         IWL_ERR(priv,
1535                                 "request for firmware file '%s' failed.\n",
1536                                 priv->firmware_name);
1537                 goto try_again;
1538         }
1539
1540         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1541                        priv->firmware_name, ucode_raw->size);
1542
1543         /* Make sure that we got at least the API version number */
1544         if (ucode_raw->size < 4) {
1545                 IWL_ERR(priv, "File size way too small!\n");
1546                 goto try_again;
1547         }
1548
1549         /* Data from ucode file:  header followed by uCode images */
1550         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1551
1552         if (ucode->ver)
1553                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1554         else
1555                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1556                                            &ucode_capa);
1557
1558         if (err)
1559                 goto try_again;
1560
1561         api_ver = IWL_UCODE_API(priv->ucode_ver);
1562         build = pieces.build;
1563
1564         /*
1565          * api_ver should match the api version forming part of the
1566          * firmware filename ... but we don't check for that and only rely
1567          * on the API version read from firmware header from here on forward
1568          */
1569         /* no api version check required for experimental uCode */
1570         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1571                 if (api_ver < api_min || api_ver > api_max) {
1572                         IWL_ERR(priv,
1573                                 "Driver unable to support your firmware API. "
1574                                 "Driver supports v%u, firmware is v%u.\n",
1575                                 api_max, api_ver);
1576                         goto try_again;
1577                 }
1578
1579                 if (api_ver != api_max)
1580                         IWL_ERR(priv,
1581                                 "Firmware has old API version. Expected v%u, "
1582                                 "got v%u. New firmware can be obtained "
1583                                 "from http://www.intellinuxwireless.org.\n",
1584                                 api_max, api_ver);
1585         }
1586
1587         if (build)
1588                 sprintf(buildstr, " build %u%s", build,
1589                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1590                                 ? " (EXP)" : "");
1591         else
1592                 buildstr[0] = '\0';
1593
1594         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1595                  IWL_UCODE_MAJOR(priv->ucode_ver),
1596                  IWL_UCODE_MINOR(priv->ucode_ver),
1597                  IWL_UCODE_API(priv->ucode_ver),
1598                  IWL_UCODE_SERIAL(priv->ucode_ver),
1599                  buildstr);
1600
1601         snprintf(priv->hw->wiphy->fw_version,
1602                  sizeof(priv->hw->wiphy->fw_version),
1603                  "%u.%u.%u.%u%s",
1604                  IWL_UCODE_MAJOR(priv->ucode_ver),
1605                  IWL_UCODE_MINOR(priv->ucode_ver),
1606                  IWL_UCODE_API(priv->ucode_ver),
1607                  IWL_UCODE_SERIAL(priv->ucode_ver),
1608                  buildstr);
1609
1610         /*
1611          * For any of the failures below (before allocating pci memory)
1612          * we will try to load a version with a smaller API -- maybe the
1613          * user just got a corrupted version of the latest API.
1614          */
1615
1616         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1617                        priv->ucode_ver);
1618         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1619                        pieces.inst_size);
1620         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1621                        pieces.data_size);
1622         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1623                        pieces.init_size);
1624         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1625                        pieces.init_data_size);
1626
1627         /* Verify that uCode images will fit in card's SRAM */
1628         if (pieces.inst_size > priv->hw_params.max_inst_size) {
1629                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1630                         pieces.inst_size);
1631                 goto try_again;
1632         }
1633
1634         if (pieces.data_size > priv->hw_params.max_data_size) {
1635                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1636                         pieces.data_size);
1637                 goto try_again;
1638         }
1639
1640         if (pieces.init_size > priv->hw_params.max_inst_size) {
1641                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1642                         pieces.init_size);
1643                 goto try_again;
1644         }
1645
1646         if (pieces.init_data_size > priv->hw_params.max_data_size) {
1647                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1648                         pieces.init_data_size);
1649                 goto try_again;
1650         }
1651
1652         /* Allocate ucode buffers for card's bus-master loading ... */
1653
1654         /* Runtime instructions and 2 copies of data:
1655          * 1) unmodified from disk
1656          * 2) backup cache for save/restore during power-downs */
1657         priv->ucode_code.len = pieces.inst_size;
1658         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1659
1660         priv->ucode_data.len = pieces.data_size;
1661         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1662
1663         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr)
1664                 goto err_pci_alloc;
1665
1666         /* Initialization instructions and data */
1667         if (pieces.init_size && pieces.init_data_size) {
1668                 priv->ucode_init.len = pieces.init_size;
1669                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1670
1671                 priv->ucode_init_data.len = pieces.init_data_size;
1672                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1673
1674                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1675                         goto err_pci_alloc;
1676         }
1677
1678         /* Now that we can no longer fail, copy information */
1679
1680         /*
1681          * The (size - 16) / 12 formula is based on the information recorded
1682          * for each event, which is of mode 1 (including timestamp) for all
1683          * new microcodes that include this information.
1684          */
1685         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1686         if (pieces.init_evtlog_size)
1687                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1688         else
1689                 priv->_agn.init_evtlog_size =
1690                         priv->cfg->base_params->max_event_log_size;
1691         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1692         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1693         if (pieces.inst_evtlog_size)
1694                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1695         else
1696                 priv->_agn.inst_evtlog_size =
1697                         priv->cfg->base_params->max_event_log_size;
1698         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1699
1700         if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) {
1701                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1702                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1703         } else
1704                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1705
1706         if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_BTSTATS ||
1707             (priv->cfg->bt_params && priv->cfg->bt_params->bt_statistics))
1708                 priv->bt_statistics = true;
1709
1710         /* Copy images into buffers for card's bus-master reads ... */
1711
1712         /* Runtime instructions (first block of data in file) */
1713         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1714                         pieces.inst_size);
1715         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1716
1717         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1718                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1719
1720         /*
1721          * Runtime data
1722          * NOTE:  Copy into backup buffer will be done in iwl_up()
1723          */
1724         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1725                         pieces.data_size);
1726         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1727
1728         /* Initialization instructions */
1729         if (pieces.init_size) {
1730                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1731                                 pieces.init_size);
1732                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1733         }
1734
1735         /* Initialization data */
1736         if (pieces.init_data_size) {
1737                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1738                                pieces.init_data_size);
1739                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1740                        pieces.init_data_size);
1741         }
1742
1743         /*
1744          * figure out the offset of chain noise reset and gain commands
1745          * base on the size of standard phy calibration commands table size
1746          */
1747         if (ucode_capa.standard_phy_calibration_size >
1748             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1749                 ucode_capa.standard_phy_calibration_size =
1750                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1751
1752         priv->_agn.phy_calib_chain_noise_reset_cmd =
1753                 ucode_capa.standard_phy_calibration_size;
1754         priv->_agn.phy_calib_chain_noise_gain_cmd =
1755                 ucode_capa.standard_phy_calibration_size + 1;
1756
1757         /**************************************************
1758          * This is still part of probe() in a sense...
1759          *
1760          * 9. Setup and register with mac80211 and debugfs
1761          **************************************************/
1762         err = iwl_mac_setup_register(priv, &ucode_capa);
1763         if (err)
1764                 goto out_unbind;
1765
1766         err = iwl_dbgfs_register(priv, DRV_NAME);
1767         if (err)
1768                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1769
1770         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1771                                         &iwl_attribute_group);
1772         if (err) {
1773                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1774                 goto out_unbind;
1775         }
1776
1777         /* We have our copies now, allow OS release its copies */
1778         release_firmware(ucode_raw);
1779         complete(&priv->_agn.firmware_loading_complete);
1780         return;
1781
1782  try_again:
1783         /* try next, if any */
1784         if (iwl_request_firmware(priv, false))
1785                 goto out_unbind;
1786         release_firmware(ucode_raw);
1787         return;
1788
1789  err_pci_alloc:
1790         IWL_ERR(priv, "failed to allocate pci memory\n");
1791         iwl_dealloc_ucode_pci(priv);
1792  out_unbind:
1793         complete(&priv->_agn.firmware_loading_complete);
1794         device_release_driver(&priv->pci_dev->dev);
1795         release_firmware(ucode_raw);
1796 }
1797
1798 static const char *desc_lookup_text[] = {
1799         "OK",
1800         "FAIL",
1801         "BAD_PARAM",
1802         "BAD_CHECKSUM",
1803         "NMI_INTERRUPT_WDG",
1804         "SYSASSERT",
1805         "FATAL_ERROR",
1806         "BAD_COMMAND",
1807         "HW_ERROR_TUNE_LOCK",
1808         "HW_ERROR_TEMPERATURE",
1809         "ILLEGAL_CHAN_FREQ",
1810         "VCC_NOT_STABLE",
1811         "FH_ERROR",
1812         "NMI_INTERRUPT_HOST",
1813         "NMI_INTERRUPT_ACTION_PT",
1814         "NMI_INTERRUPT_UNKNOWN",
1815         "UCODE_VERSION_MISMATCH",
1816         "HW_ERROR_ABS_LOCK",
1817         "HW_ERROR_CAL_LOCK_FAIL",
1818         "NMI_INTERRUPT_INST_ACTION_PT",
1819         "NMI_INTERRUPT_DATA_ACTION_PT",
1820         "NMI_TRM_HW_ER",
1821         "NMI_INTERRUPT_TRM",
1822         "NMI_INTERRUPT_BREAK_POINT"
1823         "DEBUG_0",
1824         "DEBUG_1",
1825         "DEBUG_2",
1826         "DEBUG_3",
1827 };
1828
1829 static struct { char *name; u8 num; } advanced_lookup[] = {
1830         { "NMI_INTERRUPT_WDG", 0x34 },
1831         { "SYSASSERT", 0x35 },
1832         { "UCODE_VERSION_MISMATCH", 0x37 },
1833         { "BAD_COMMAND", 0x38 },
1834         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1835         { "FATAL_ERROR", 0x3D },
1836         { "NMI_TRM_HW_ERR", 0x46 },
1837         { "NMI_INTERRUPT_TRM", 0x4C },
1838         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1839         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1840         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1841         { "NMI_INTERRUPT_HOST", 0x66 },
1842         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1843         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1844         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1845         { "ADVANCED_SYSASSERT", 0 },
1846 };
1847
1848 static const char *desc_lookup(u32 num)
1849 {
1850         int i;
1851         int max = ARRAY_SIZE(desc_lookup_text);
1852
1853         if (num < max)
1854                 return desc_lookup_text[num];
1855
1856         max = ARRAY_SIZE(advanced_lookup) - 1;
1857         for (i = 0; i < max; i++) {
1858                 if (advanced_lookup[i].num == num)
1859                         break;;
1860         }
1861         return advanced_lookup[i].name;
1862 }
1863
1864 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1865 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1866
1867 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1868 {
1869         u32 data2, line;
1870         u32 desc, time, count, base, data1;
1871         u32 blink1, blink2, ilink1, ilink2;
1872         u32 pc, hcmd;
1873
1874         if (priv->ucode_type == UCODE_INIT) {
1875                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1876                 if (!base)
1877                         base = priv->_agn.init_errlog_ptr;
1878         } else {
1879                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1880                 if (!base)
1881                         base = priv->_agn.inst_errlog_ptr;
1882         }
1883
1884         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1885                 IWL_ERR(priv,
1886                         "Not valid error log pointer 0x%08X for %s uCode\n",
1887                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1888                 return;
1889         }
1890
1891         count = iwl_read_targ_mem(priv, base);
1892
1893         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1894                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1895                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1896                         priv->status, count);
1897         }
1898
1899         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1900         priv->isr_stats.err_code = desc;
1901         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
1902         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1903         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1904         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1905         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1906         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1907         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1908         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1909         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1910         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
1911
1912         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1913                                       blink1, blink2, ilink1, ilink2);
1914
1915         IWL_ERR(priv, "Desc                                  Time       "
1916                 "data1      data2      line\n");
1917         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1918                 desc_lookup(desc), desc, time, data1, data2, line);
1919         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
1920         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1921                 pc, blink1, blink2, ilink1, ilink2, hcmd);
1922 }
1923
1924 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1925
1926 /**
1927  * iwl_print_event_log - Dump error event log to syslog
1928  *
1929  */
1930 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1931                                u32 num_events, u32 mode,
1932                                int pos, char **buf, size_t bufsz)
1933 {
1934         u32 i;
1935         u32 base;       /* SRAM byte address of event log header */
1936         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1937         u32 ptr;        /* SRAM byte address of log data */
1938         u32 ev, time, data; /* event log data */
1939         unsigned long reg_flags;
1940
1941         if (num_events == 0)
1942                 return pos;
1943
1944         if (priv->ucode_type == UCODE_INIT) {
1945                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1946                 if (!base)
1947                         base = priv->_agn.init_evtlog_ptr;
1948         } else {
1949                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1950                 if (!base)
1951                         base = priv->_agn.inst_evtlog_ptr;
1952         }
1953
1954         if (mode == 0)
1955                 event_size = 2 * sizeof(u32);
1956         else
1957                 event_size = 3 * sizeof(u32);
1958
1959         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1960
1961         /* Make sure device is powered up for SRAM reads */
1962         spin_lock_irqsave(&priv->reg_lock, reg_flags);
1963         iwl_grab_nic_access(priv);
1964
1965         /* Set starting address; reads will auto-increment */
1966         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1967         rmb();
1968
1969         /* "time" is actually "data" for mode 0 (no timestamp).
1970         * place event id # at far right for easier visual parsing. */
1971         for (i = 0; i < num_events; i++) {
1972                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1973                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1974                 if (mode == 0) {
1975                         /* data, ev */
1976                         if (bufsz) {
1977                                 pos += scnprintf(*buf + pos, bufsz - pos,
1978                                                 "EVT_LOG:0x%08x:%04u\n",
1979                                                 time, ev);
1980                         } else {
1981                                 trace_iwlwifi_dev_ucode_event(priv, 0,
1982                                         time, ev);
1983                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1984                                         time, ev);
1985                         }
1986                 } else {
1987                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1988                         if (bufsz) {
1989                                 pos += scnprintf(*buf + pos, bufsz - pos,
1990                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
1991                                                  time, data, ev);
1992                         } else {
1993                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1994                                         time, data, ev);
1995                                 trace_iwlwifi_dev_ucode_event(priv, time,
1996                                         data, ev);
1997                         }
1998                 }
1999         }
2000
2001         /* Allow device to power down */
2002         iwl_release_nic_access(priv);
2003         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2004         return pos;
2005 }
2006
2007 /**
2008  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2009  */
2010 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2011                                     u32 num_wraps, u32 next_entry,
2012                                     u32 size, u32 mode,
2013                                     int pos, char **buf, size_t bufsz)
2014 {
2015         /*
2016          * display the newest DEFAULT_LOG_ENTRIES entries
2017          * i.e the entries just before the next ont that uCode would fill.
2018          */
2019         if (num_wraps) {
2020                 if (next_entry < size) {
2021                         pos = iwl_print_event_log(priv,
2022                                                 capacity - (size - next_entry),
2023                                                 size - next_entry, mode,
2024                                                 pos, buf, bufsz);
2025                         pos = iwl_print_event_log(priv, 0,
2026                                                   next_entry, mode,
2027                                                   pos, buf, bufsz);
2028                 } else
2029                         pos = iwl_print_event_log(priv, next_entry - size,
2030                                                   size, mode, pos, buf, bufsz);
2031         } else {
2032                 if (next_entry < size) {
2033                         pos = iwl_print_event_log(priv, 0, next_entry,
2034                                                   mode, pos, buf, bufsz);
2035                 } else {
2036                         pos = iwl_print_event_log(priv, next_entry - size,
2037                                                   size, mode, pos, buf, bufsz);
2038                 }
2039         }
2040         return pos;
2041 }
2042
2043 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2044
2045 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2046                             char **buf, bool display)
2047 {
2048         u32 base;       /* SRAM byte address of event log header */
2049         u32 capacity;   /* event log capacity in # entries */
2050         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2051         u32 num_wraps;  /* # times uCode wrapped to top of log */
2052         u32 next_entry; /* index of next entry to be written by uCode */
2053         u32 size;       /* # entries that we'll print */
2054         u32 logsize;
2055         int pos = 0;
2056         size_t bufsz = 0;
2057
2058         if (priv->ucode_type == UCODE_INIT) {
2059                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2060                 logsize = priv->_agn.init_evtlog_size;
2061                 if (!base)
2062                         base = priv->_agn.init_evtlog_ptr;
2063         } else {
2064                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2065                 logsize = priv->_agn.inst_evtlog_size;
2066                 if (!base)
2067                         base = priv->_agn.inst_evtlog_ptr;
2068         }
2069
2070         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2071                 IWL_ERR(priv,
2072                         "Invalid event log pointer 0x%08X for %s uCode\n",
2073                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2074                 return -EINVAL;
2075         }
2076
2077         /* event log header */
2078         capacity = iwl_read_targ_mem(priv, base);
2079         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2080         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2081         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2082
2083         if (capacity > logsize) {
2084                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2085                         capacity, logsize);
2086                 capacity = logsize;
2087         }
2088
2089         if (next_entry > logsize) {
2090                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2091                         next_entry, logsize);
2092                 next_entry = logsize;
2093         }
2094
2095         size = num_wraps ? capacity : next_entry;
2096
2097         /* bail out if nothing in log */
2098         if (size == 0) {
2099                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2100                 return pos;
2101         }
2102
2103         /* enable/disable bt channel inhibition */
2104         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2105
2106 #ifdef CONFIG_IWLWIFI_DEBUG
2107         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2108                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2109                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2110 #else
2111         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2112                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2113 #endif
2114         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2115                 size);
2116
2117 #ifdef CONFIG_IWLWIFI_DEBUG
2118         if (display) {
2119                 if (full_log)
2120                         bufsz = capacity * 48;
2121                 else
2122                         bufsz = size * 48;
2123                 *buf = kmalloc(bufsz, GFP_KERNEL);
2124                 if (!*buf)
2125                         return -ENOMEM;
2126         }
2127         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2128                 /*
2129                  * if uCode has wrapped back to top of log,
2130                  * start at the oldest entry,
2131                  * i.e the next one that uCode would fill.
2132                  */
2133                 if (num_wraps)
2134                         pos = iwl_print_event_log(priv, next_entry,
2135                                                 capacity - next_entry, mode,
2136                                                 pos, buf, bufsz);
2137                 /* (then/else) start at top of log */
2138                 pos = iwl_print_event_log(priv, 0,
2139                                           next_entry, mode, pos, buf, bufsz);
2140         } else
2141                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2142                                                 next_entry, size, mode,
2143                                                 pos, buf, bufsz);
2144 #else
2145         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2146                                         next_entry, size, mode,
2147                                         pos, buf, bufsz);
2148 #endif
2149         return pos;
2150 }
2151
2152 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2153 {
2154         struct iwl_ct_kill_config cmd;
2155         struct iwl_ct_kill_throttling_config adv_cmd;
2156         unsigned long flags;
2157         int ret = 0;
2158
2159         spin_lock_irqsave(&priv->lock, flags);
2160         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2161                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2162         spin_unlock_irqrestore(&priv->lock, flags);
2163         priv->thermal_throttle.ct_kill_toggle = false;
2164
2165         if (priv->cfg->base_params->support_ct_kill_exit) {
2166                 adv_cmd.critical_temperature_enter =
2167                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2168                 adv_cmd.critical_temperature_exit =
2169                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2170
2171                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2172                                        sizeof(adv_cmd), &adv_cmd);
2173                 if (ret)
2174                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2175                 else
2176                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2177                                         "succeeded, "
2178                                         "critical temperature enter is %d,"
2179                                         "exit is %d\n",
2180                                        priv->hw_params.ct_kill_threshold,
2181                                        priv->hw_params.ct_kill_exit_threshold);
2182         } else {
2183                 cmd.critical_temperature_R =
2184                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2185
2186                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2187                                        sizeof(cmd), &cmd);
2188                 if (ret)
2189                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2190                 else
2191                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2192                                         "succeeded, "
2193                                         "critical temperature is %d\n",
2194                                         priv->hw_params.ct_kill_threshold);
2195         }
2196 }
2197
2198 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2199 {
2200         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2201         struct iwl_host_cmd cmd = {
2202                 .id = CALIBRATION_CFG_CMD,
2203                 .len = sizeof(struct iwl_calib_cfg_cmd),
2204                 .data = &calib_cfg_cmd,
2205         };
2206
2207         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2208         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2209         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2210
2211         return iwl_send_cmd(priv, &cmd);
2212 }
2213
2214
2215 /**
2216  * iwl_alive_start - called after REPLY_ALIVE notification received
2217  *                   from protocol/runtime uCode (initialization uCode's
2218  *                   Alive gets handled by iwl_init_alive_start()).
2219  */
2220 static void iwl_alive_start(struct iwl_priv *priv)
2221 {
2222         int ret = 0;
2223         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2224
2225         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2226
2227         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2228          * This is a paranoid check, because we would not have gotten the
2229          * "runtime" alive if code weren't properly loaded.  */
2230         if (iwl_verify_ucode(priv, &priv->ucode_code)) {
2231                 /* Runtime instruction load was bad;
2232                  * take it all the way back down so we can try again */
2233                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2234                 goto restart;
2235         }
2236
2237         ret = iwlagn_alive_notify(priv);
2238         if (ret) {
2239                 IWL_WARN(priv,
2240                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2241                 goto restart;
2242         }
2243
2244
2245         /* After the ALIVE response, we can send host commands to the uCode */
2246         set_bit(STATUS_ALIVE, &priv->status);
2247
2248         /* Enable watchdog to monitor the driver tx queues */
2249         iwl_setup_watchdog(priv);
2250
2251         if (iwl_is_rfkill(priv))
2252                 return;
2253
2254         /* download priority table before any calibration request */
2255         if (priv->cfg->bt_params &&
2256             priv->cfg->bt_params->advanced_bt_coexist) {
2257                 /* Configure Bluetooth device coexistence support */
2258                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2259                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2260                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2261                 priv->cfg->ops->hcmd->send_bt_config(priv);
2262                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2263                 iwlagn_send_prio_tbl(priv);
2264
2265                 /* FIXME: w/a to force change uCode BT state machine */
2266                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2267                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2268                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2269                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2270         }
2271         if (priv->hw_params.calib_rt_cfg)
2272                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2273
2274         ieee80211_wake_queues(priv->hw);
2275
2276         priv->active_rate = IWL_RATES_MASK;
2277
2278         /* Configure Tx antenna selection based on H/W config */
2279         if (priv->cfg->ops->hcmd->set_tx_ant)
2280                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2281
2282         if (iwl_is_associated_ctx(ctx)) {
2283                 struct iwl_rxon_cmd *active_rxon =
2284                                 (struct iwl_rxon_cmd *)&ctx->active;
2285                 /* apply any changes in staging */
2286                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2287                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2288         } else {
2289                 struct iwl_rxon_context *tmp;
2290                 /* Initialize our rx_config data */
2291                 for_each_context(priv, tmp)
2292                         iwl_connection_init_rx_config(priv, tmp);
2293
2294                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2295                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2296         }
2297
2298         if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2299             !priv->cfg->bt_params->advanced_bt_coexist)) {
2300                 /*
2301                  * default is 2-wire BT coexexistence support
2302                  */
2303                 priv->cfg->ops->hcmd->send_bt_config(priv);
2304         }
2305
2306         iwl_reset_run_time_calib(priv);
2307
2308         set_bit(STATUS_READY, &priv->status);
2309
2310         /* Configure the adapter for unassociated operation */
2311         iwlcore_commit_rxon(priv, ctx);
2312
2313         /* At this point, the NIC is initialized and operational */
2314         iwl_rf_kill_ct_config(priv);
2315
2316         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2317         wake_up_interruptible(&priv->wait_command_queue);
2318
2319         iwl_power_update_mode(priv, true);
2320         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2321
2322
2323         return;
2324
2325  restart:
2326         queue_work(priv->workqueue, &priv->restart);
2327 }
2328
2329 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2330
2331 static void __iwl_down(struct iwl_priv *priv)
2332 {
2333         unsigned long flags;
2334         int exit_pending;
2335
2336         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2337
2338         iwl_scan_cancel_timeout(priv, 200);
2339
2340         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2341
2342         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2343          * to prevent rearm timer */
2344         del_timer_sync(&priv->watchdog);
2345
2346         iwl_clear_ucode_stations(priv, NULL);
2347         iwl_dealloc_bcast_stations(priv);
2348         iwl_clear_driver_stations(priv);
2349
2350         /* reset BT coex data */
2351         priv->bt_status = 0;
2352         if (priv->cfg->bt_params)
2353                 priv->bt_traffic_load =
2354                          priv->cfg->bt_params->bt_init_traffic_load;
2355         else
2356                 priv->bt_traffic_load = 0;
2357         priv->bt_full_concurrent = false;
2358         priv->bt_ci_compliance = 0;
2359
2360         /* Wipe out the EXIT_PENDING status bit if we are not actually
2361          * exiting the module */
2362         if (!exit_pending)
2363                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2364
2365         /* stop and reset the on-board processor */
2366         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2367
2368         /* tell the device to stop sending interrupts */
2369         spin_lock_irqsave(&priv->lock, flags);
2370         iwl_disable_interrupts(priv);
2371         spin_unlock_irqrestore(&priv->lock, flags);
2372         iwl_synchronize_irq(priv);
2373
2374         if (priv->mac80211_registered)
2375                 ieee80211_stop_queues(priv->hw);
2376
2377         /* If we have not previously called iwl_init() then
2378          * clear all bits but the RF Kill bit and return */
2379         if (!iwl_is_init(priv)) {
2380                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2381                                         STATUS_RF_KILL_HW |
2382                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2383                                         STATUS_GEO_CONFIGURED |
2384                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2385                                         STATUS_EXIT_PENDING;
2386                 goto exit;
2387         }
2388
2389         /* ...otherwise clear out all the status bits but the RF Kill
2390          * bit and continue taking the NIC down. */
2391         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2392                                 STATUS_RF_KILL_HW |
2393                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2394                                 STATUS_GEO_CONFIGURED |
2395                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2396                                 STATUS_FW_ERROR |
2397                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2398                                 STATUS_EXIT_PENDING;
2399
2400         /* device going down, Stop using ICT table */
2401         if (priv->cfg->ops->lib->isr_ops.disable)
2402                 priv->cfg->ops->lib->isr_ops.disable(priv);
2403
2404         iwlagn_txq_ctx_stop(priv);
2405         iwlagn_rxq_stop(priv);
2406
2407         /* Power-down device's busmaster DMA clocks */
2408         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2409         udelay(5);
2410
2411         /* Make sure (redundant) we've released our request to stay awake */
2412         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2413
2414         /* Stop the device, and put it in low power state */
2415         iwl_apm_stop(priv);
2416
2417  exit:
2418         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2419
2420         dev_kfree_skb(priv->beacon_skb);
2421         priv->beacon_skb = NULL;
2422
2423         /* clear out any free frames */
2424         iwl_clear_free_frames(priv);
2425 }
2426
2427 static void iwl_down(struct iwl_priv *priv)
2428 {
2429         mutex_lock(&priv->mutex);
2430         __iwl_down(priv);
2431         mutex_unlock(&priv->mutex);
2432
2433         iwl_cancel_deferred_work(priv);
2434 }
2435
2436 #define HW_READY_TIMEOUT (50)
2437
2438 static int iwl_set_hw_ready(struct iwl_priv *priv)
2439 {
2440         int ret = 0;
2441
2442         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2443                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2444
2445         /* See if we got it */
2446         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2447                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2448                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2449                                 HW_READY_TIMEOUT);
2450         if (ret != -ETIMEDOUT)
2451                 priv->hw_ready = true;
2452         else
2453                 priv->hw_ready = false;
2454
2455         IWL_DEBUG_INFO(priv, "hardware %s\n",
2456                       (priv->hw_ready == 1) ? "ready" : "not ready");
2457         return ret;
2458 }
2459
2460 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2461 {
2462         int ret = 0;
2463
2464         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2465
2466         ret = iwl_set_hw_ready(priv);
2467         if (priv->hw_ready)
2468                 return ret;
2469
2470         /* If HW is not ready, prepare the conditions to check again */
2471         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2472                         CSR_HW_IF_CONFIG_REG_PREPARE);
2473
2474         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2475                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2476                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2477
2478         /* HW should be ready by now, check again. */
2479         if (ret != -ETIMEDOUT)
2480                 iwl_set_hw_ready(priv);
2481
2482         return ret;
2483 }
2484
2485 #define MAX_HW_RESTARTS 5
2486
2487 static int __iwl_up(struct iwl_priv *priv)
2488 {
2489         struct iwl_rxon_context *ctx;
2490         int i;
2491         int ret;
2492
2493         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2494                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2495                 return -EIO;
2496         }
2497
2498         for_each_context(priv, ctx) {
2499                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2500                 if (ret) {
2501                         iwl_dealloc_bcast_stations(priv);
2502                         return ret;
2503                 }
2504         }
2505
2506         iwl_prepare_card_hw(priv);
2507
2508         if (!priv->hw_ready) {
2509                 IWL_WARN(priv, "Exit HW not ready\n");
2510                 return -EIO;
2511         }
2512
2513         /* If platform's RF_KILL switch is NOT set to KILL */
2514         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2515                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2516         else
2517                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2518
2519         if (iwl_is_rfkill(priv)) {
2520                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2521
2522                 iwl_enable_interrupts(priv);
2523                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2524                 return 0;
2525         }
2526
2527         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2528
2529         /* must be initialised before iwl_hw_nic_init */
2530         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2531                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2532         else
2533                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2534
2535         ret = iwlagn_hw_nic_init(priv);
2536         if (ret) {
2537                 IWL_ERR(priv, "Unable to init nic\n");
2538                 return ret;
2539         }
2540
2541         /* make sure rfkill handshake bits are cleared */
2542         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2543         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2544                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2545
2546         /* clear (again), then enable host interrupts */
2547         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2548         iwl_enable_interrupts(priv);
2549
2550         /* really make sure rfkill handshake bits are cleared */
2551         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2552         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2553
2554         for (i = 0; i < MAX_HW_RESTARTS; i++) {
2555
2556                 /* load bootstrap state machine,
2557                  * load bootstrap program into processor's memory,
2558                  * prepare to load the "initialize" uCode */
2559                 ret = iwlagn_load_ucode(priv);
2560
2561                 if (ret) {
2562                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2563                                 ret);
2564                         continue;
2565                 }
2566
2567                 /* start card; "initialize" will load runtime ucode */
2568                 iwl_nic_start(priv);
2569
2570                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2571
2572                 return 0;
2573         }
2574
2575         set_bit(STATUS_EXIT_PENDING, &priv->status);
2576         __iwl_down(priv);
2577         clear_bit(STATUS_EXIT_PENDING, &priv->status);
2578
2579         /* tried to restart and config the device for as long as our
2580          * patience could withstand */
2581         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2582         return -EIO;
2583 }
2584
2585
2586 /*****************************************************************************
2587  *
2588  * Workqueue callbacks
2589  *
2590  *****************************************************************************/
2591
2592 static void iwl_bg_init_alive_start(struct work_struct *data)
2593 {
2594         struct iwl_priv *priv =
2595             container_of(data, struct iwl_priv, init_alive_start.work);
2596
2597         mutex_lock(&priv->mutex);
2598
2599         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2600                 mutex_unlock(&priv->mutex);
2601                 return;
2602         }
2603
2604         iwlagn_init_alive_start(priv);
2605         mutex_unlock(&priv->mutex);
2606 }
2607
2608 static void iwl_bg_alive_start(struct work_struct *data)
2609 {
2610         struct iwl_priv *priv =
2611             container_of(data, struct iwl_priv, alive_start.work);
2612
2613         mutex_lock(&priv->mutex);
2614         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2615                 goto unlock;
2616
2617         /* enable dram interrupt */
2618         if (priv->cfg->ops->lib->isr_ops.reset)
2619                 priv->cfg->ops->lib->isr_ops.reset(priv);
2620
2621         iwl_alive_start(priv);
2622 unlock:
2623         mutex_unlock(&priv->mutex);
2624 }
2625
2626 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2627 {
2628         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2629                         run_time_calib_work);
2630
2631         mutex_lock(&priv->mutex);
2632
2633         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2634             test_bit(STATUS_SCANNING, &priv->status)) {
2635                 mutex_unlock(&priv->mutex);
2636                 return;
2637         }
2638
2639         if (priv->start_calib) {
2640                 if (iwl_bt_statistics(priv)) {
2641                         iwl_chain_noise_calibration(priv,
2642                                         (void *)&priv->_agn.statistics_bt);
2643                         iwl_sensitivity_calibration(priv,
2644                                         (void *)&priv->_agn.statistics_bt);
2645                 } else {
2646                         iwl_chain_noise_calibration(priv,
2647                                         (void *)&priv->_agn.statistics);
2648                         iwl_sensitivity_calibration(priv,
2649                                         (void *)&priv->_agn.statistics);
2650                 }
2651         }
2652
2653         mutex_unlock(&priv->mutex);
2654 }
2655
2656 static void iwl_bg_restart(struct work_struct *data)
2657 {
2658         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2659
2660         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2661                 return;
2662
2663         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2664                 struct iwl_rxon_context *ctx;
2665                 bool bt_full_concurrent;
2666                 u8 bt_ci_compliance;
2667                 u8 bt_load;
2668                 u8 bt_status;
2669
2670                 mutex_lock(&priv->mutex);
2671                 for_each_context(priv, ctx)
2672                         ctx->vif = NULL;
2673                 priv->is_open = 0;
2674
2675                 /*
2676                  * __iwl_down() will clear the BT status variables,
2677                  * which is correct, but when we restart we really
2678                  * want to keep them so restore them afterwards.
2679                  *
2680                  * The restart process will later pick them up and
2681                  * re-configure the hw when we reconfigure the BT
2682                  * command.
2683                  */
2684                 bt_full_concurrent = priv->bt_full_concurrent;
2685                 bt_ci_compliance = priv->bt_ci_compliance;
2686                 bt_load = priv->bt_traffic_load;
2687                 bt_status = priv->bt_status;
2688
2689                 __iwl_down(priv);
2690
2691                 priv->bt_full_concurrent = bt_full_concurrent;
2692                 priv->bt_ci_compliance = bt_ci_compliance;
2693                 priv->bt_traffic_load = bt_load;
2694                 priv->bt_status = bt_status;
2695
2696                 mutex_unlock(&priv->mutex);
2697                 iwl_cancel_deferred_work(priv);
2698                 ieee80211_restart_hw(priv->hw);
2699         } else {
2700                 iwl_down(priv);
2701
2702                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2703                         return;
2704
2705                 mutex_lock(&priv->mutex);
2706                 __iwl_up(priv);
2707                 mutex_unlock(&priv->mutex);
2708         }
2709 }
2710
2711 static void iwl_bg_rx_replenish(struct work_struct *data)
2712 {
2713         struct iwl_priv *priv =
2714             container_of(data, struct iwl_priv, rx_replenish);
2715
2716         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2717                 return;
2718
2719         mutex_lock(&priv->mutex);
2720         iwlagn_rx_replenish(priv);
2721         mutex_unlock(&priv->mutex);
2722 }
2723
2724 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2725                                  struct ieee80211_channel *chan,
2726                                  enum nl80211_channel_type channel_type,
2727                                  unsigned int wait)
2728 {
2729         struct iwl_priv *priv = hw->priv;
2730         int ret;
2731
2732         /* Not supported if we don't have PAN */
2733         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2734                 ret = -EOPNOTSUPP;
2735                 goto free;
2736         }
2737
2738         /* Not supported on pre-P2P firmware */
2739         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2740                                         BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2741                 ret = -EOPNOTSUPP;
2742                 goto free;
2743         }
2744
2745         mutex_lock(&priv->mutex);
2746
2747         if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2748                 /*
2749                  * If the PAN context is free, use the normal
2750                  * way of doing remain-on-channel offload + TX.
2751                  */
2752                 ret = 1;
2753                 goto out;
2754         }
2755
2756         /* TODO: queue up if scanning? */
2757         if (test_bit(STATUS_SCANNING, &priv->status) ||
2758             priv->_agn.offchan_tx_skb) {
2759                 ret = -EBUSY;
2760                 goto out;
2761         }
2762
2763         /*
2764          * max_scan_ie_len doesn't include the blank SSID or the header,
2765          * so need to add that again here.
2766          */
2767         if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2768                 ret = -ENOBUFS;
2769                 goto out;
2770         }
2771
2772         priv->_agn.offchan_tx_skb = skb;
2773         priv->_agn.offchan_tx_timeout = wait;
2774         priv->_agn.offchan_tx_chan = chan;
2775
2776         ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2777                                 IWL_SCAN_OFFCH_TX, chan->band);
2778         if (ret)
2779                 priv->_agn.offchan_tx_skb = NULL;
2780  out:
2781         mutex_unlock(&priv->mutex);
2782  free:
2783         if (ret < 0)
2784                 kfree_skb(skb);
2785
2786         return ret;
2787 }
2788
2789 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2790 {
2791         struct iwl_priv *priv = hw->priv;
2792         int ret;
2793
2794         mutex_lock(&priv->mutex);
2795
2796         if (!priv->_agn.offchan_tx_skb) {
2797                 ret = -EINVAL;
2798                 goto unlock;
2799         }
2800
2801         priv->_agn.offchan_tx_skb = NULL;
2802
2803         ret = iwl_scan_cancel_timeout(priv, 200);
2804         if (ret)
2805                 ret = -EIO;
2806 unlock:
2807         mutex_unlock(&priv->mutex);
2808
2809         return ret;
2810 }
2811
2812 /*****************************************************************************
2813  *
2814  * mac80211 entry point functions
2815  *
2816  *****************************************************************************/
2817
2818 #define UCODE_READY_TIMEOUT     (4 * HZ)
2819
2820 /*
2821  * Not a mac80211 entry point function, but it fits in with all the
2822  * other mac80211 functions grouped here.
2823  */
2824 static int iwl_mac_setup_register(struct iwl_priv *priv,
2825                                   struct iwlagn_ucode_capabilities *capa)
2826 {
2827         int ret;
2828         struct ieee80211_hw *hw = priv->hw;
2829         struct iwl_rxon_context *ctx;
2830
2831         hw->rate_control_algorithm = "iwl-agn-rs";
2832
2833         /* Tell mac80211 our characteristics */
2834         hw->flags = IEEE80211_HW_SIGNAL_DBM |
2835                     IEEE80211_HW_AMPDU_AGGREGATION |
2836                     IEEE80211_HW_NEED_DTIM_PERIOD |
2837                     IEEE80211_HW_SPECTRUM_MGMT |
2838                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2839
2840         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2841
2842         if (!priv->cfg->base_params->broken_powersave)
2843                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2844                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2845
2846         if (priv->cfg->sku & IWL_SKU_N)
2847                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2848                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2849
2850         if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
2851                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
2852
2853         hw->sta_data_size = sizeof(struct iwl_station_priv);
2854         hw->vif_data_size = sizeof(struct iwl_vif_priv);
2855
2856         for_each_context(priv, ctx) {
2857                 hw->wiphy->interface_modes |= ctx->interface_modes;
2858                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2859         }
2860
2861         hw->wiphy->max_remain_on_channel_duration = 1000;
2862
2863         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2864                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
2865                             WIPHY_FLAG_IBSS_RSN;
2866
2867         /*
2868          * For now, disable PS by default because it affects
2869          * RX performance significantly.
2870          */
2871         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2872
2873         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2874         /* we create the 802.11 header and a zero-length SSID element */
2875         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2876
2877         /* Default value; 4 EDCA QOS priorities */
2878         hw->queues = 4;
2879
2880         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2881
2882         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2883                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2884                         &priv->bands[IEEE80211_BAND_2GHZ];
2885         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2886                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2887                         &priv->bands[IEEE80211_BAND_5GHZ];
2888
2889         iwl_leds_init(priv);
2890
2891         ret = ieee80211_register_hw(priv->hw);
2892         if (ret) {
2893                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2894                 return ret;
2895         }
2896         priv->mac80211_registered = 1;
2897
2898         return 0;
2899 }
2900
2901
2902 static int iwlagn_mac_start(struct ieee80211_hw *hw)
2903 {
2904         struct iwl_priv *priv = hw->priv;
2905         int ret;
2906
2907         IWL_DEBUG_MAC80211(priv, "enter\n");
2908
2909         /* we should be verifying the device is ready to be opened */
2910         mutex_lock(&priv->mutex);
2911         ret = __iwl_up(priv);
2912         mutex_unlock(&priv->mutex);
2913
2914         if (ret)
2915                 return ret;
2916
2917         if (iwl_is_rfkill(priv))
2918                 goto out;
2919
2920         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2921
2922         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2923          * mac80211 will not be run successfully. */
2924         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2925                         test_bit(STATUS_READY, &priv->status),
2926                         UCODE_READY_TIMEOUT);
2927         if (!ret) {
2928                 if (!test_bit(STATUS_READY, &priv->status)) {
2929                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2930                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2931                         return -ETIMEDOUT;
2932                 }
2933         }
2934
2935         iwlagn_led_enable(priv);
2936
2937 out:
2938         priv->is_open = 1;
2939         IWL_DEBUG_MAC80211(priv, "leave\n");
2940         return 0;
2941 }
2942
2943 static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2944 {
2945         struct iwl_priv *priv = hw->priv;
2946
2947         IWL_DEBUG_MAC80211(priv, "enter\n");
2948
2949         if (!priv->is_open)
2950                 return;
2951
2952         priv->is_open = 0;
2953
2954         iwl_down(priv);
2955
2956         flush_workqueue(priv->workqueue);
2957
2958         /* User space software may expect getting rfkill changes
2959          * even if interface is down */
2960         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2961         iwl_enable_rfkill_int(priv);
2962
2963         IWL_DEBUG_MAC80211(priv, "leave\n");
2964 }
2965
2966 static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2967 {
2968         struct iwl_priv *priv = hw->priv;
2969
2970         IWL_DEBUG_MACDUMP(priv, "enter\n");
2971
2972         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2973                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2974
2975         if (iwlagn_tx_skb(priv, skb))
2976                 dev_kfree_skb_any(skb);
2977
2978         IWL_DEBUG_MACDUMP(priv, "leave\n");
2979 }
2980
2981 static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2982                                        struct ieee80211_vif *vif,
2983                                        struct ieee80211_key_conf *keyconf,
2984                                        struct ieee80211_sta *sta,
2985                                        u32 iv32, u16 *phase1key)
2986 {
2987         struct iwl_priv *priv = hw->priv;
2988         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2989
2990         IWL_DEBUG_MAC80211(priv, "enter\n");
2991
2992         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2993                             iv32, phase1key);
2994
2995         IWL_DEBUG_MAC80211(priv, "leave\n");
2996 }
2997
2998 static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2999                               struct ieee80211_vif *vif,
3000                               struct ieee80211_sta *sta,
3001                               struct ieee80211_key_conf *key)
3002 {
3003         struct iwl_priv *priv = hw->priv;
3004         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3005         struct iwl_rxon_context *ctx = vif_priv->ctx;
3006         int ret;
3007         u8 sta_id;
3008         bool is_default_wep_key = false;
3009
3010         IWL_DEBUG_MAC80211(priv, "enter\n");
3011
3012         if (priv->cfg->mod_params->sw_crypto) {
3013                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3014                 return -EOPNOTSUPP;
3015         }
3016
3017         /*
3018          * To support IBSS RSN, don't program group keys in IBSS, the
3019          * hardware will then not attempt to decrypt the frames.
3020          */
3021         if (vif->type == NL80211_IFTYPE_ADHOC &&
3022             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3023                 return -EOPNOTSUPP;
3024
3025         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3026         if (sta_id == IWL_INVALID_STATION)
3027                 return -EINVAL;
3028
3029         mutex_lock(&priv->mutex);
3030         iwl_scan_cancel_timeout(priv, 100);
3031
3032         /*
3033          * If we are getting WEP group key and we didn't receive any key mapping
3034          * so far, we are in legacy wep mode (group key only), otherwise we are
3035          * in 1X mode.
3036          * In legacy wep mode, we use another host command to the uCode.
3037          */
3038         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3039              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3040             !sta) {
3041                 if (cmd == SET_KEY)
3042                         is_default_wep_key = !ctx->key_mapping_keys;
3043                 else
3044                         is_default_wep_key =
3045                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3046         }
3047
3048         switch (cmd) {
3049         case SET_KEY:
3050                 if (is_default_wep_key)
3051                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3052                 else
3053                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3054                                                   key, sta_id);
3055
3056                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3057                 break;
3058         case DISABLE_KEY:
3059                 if (is_default_wep_key)
3060                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3061                 else
3062                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3063
3064                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3065                 break;
3066         default:
3067                 ret = -EINVAL;
3068         }
3069
3070         mutex_unlock(&priv->mutex);
3071         IWL_DEBUG_MAC80211(priv, "leave\n");
3072
3073         return ret;
3074 }
3075
3076 static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3077                                    struct ieee80211_vif *vif,
3078                                    enum ieee80211_ampdu_mlme_action action,
3079                                    struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3080                                    u8 buf_size)
3081 {
3082         struct iwl_priv *priv = hw->priv;
3083         int ret = -EINVAL;
3084         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3085
3086         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3087                      sta->addr, tid);
3088
3089         if (!(priv->cfg->sku & IWL_SKU_N))
3090                 return -EACCES;
3091
3092         mutex_lock(&priv->mutex);
3093
3094         switch (action) {
3095         case IEEE80211_AMPDU_RX_START:
3096                 IWL_DEBUG_HT(priv, "start Rx\n");
3097                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3098                 break;
3099         case IEEE80211_AMPDU_RX_STOP:
3100                 IWL_DEBUG_HT(priv, "stop Rx\n");
3101                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3102                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3103                         ret = 0;
3104                 break;
3105         case IEEE80211_AMPDU_TX_START:
3106                 IWL_DEBUG_HT(priv, "start Tx\n");
3107                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3108                 if (ret == 0) {
3109                         priv->_agn.agg_tids_count++;
3110                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3111                                      priv->_agn.agg_tids_count);
3112                 }
3113                 break;
3114         case IEEE80211_AMPDU_TX_STOP:
3115                 IWL_DEBUG_HT(priv, "stop Tx\n");
3116                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3117                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3118                         priv->_agn.agg_tids_count--;
3119                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3120                                      priv->_agn.agg_tids_count);
3121                 }
3122                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3123                         ret = 0;
3124                 if (priv->cfg->ht_params &&
3125                     priv->cfg->ht_params->use_rts_for_aggregation) {
3126                         struct iwl_station_priv *sta_priv =
3127                                 (void *) sta->drv_priv;
3128                         /*
3129                          * switch off RTS/CTS if it was previously enabled
3130                          */
3131
3132                         sta_priv->lq_sta.lq.general_params.flags &=
3133                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3134                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3135                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3136                 }
3137                 break;
3138         case IEEE80211_AMPDU_TX_OPERATIONAL:
3139                 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
3140
3141                 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
3142
3143                 /*
3144                  * If the limit is 0, then it wasn't initialised yet,
3145                  * use the default. We can do that since we take the
3146                  * minimum below, and we don't want to go above our
3147                  * default due to hardware restrictions.
3148                  */
3149                 if (sta_priv->max_agg_bufsize == 0)
3150                         sta_priv->max_agg_bufsize =
3151                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3152
3153                 /*
3154                  * Even though in theory the peer could have different
3155                  * aggregation reorder buffer sizes for different sessions,
3156                  * our ucode doesn't allow for that and has a global limit
3157                  * for each station. Therefore, use the minimum of all the
3158                  * aggregation sessions and our default value.
3159                  */
3160                 sta_priv->max_agg_bufsize =
3161                         min(sta_priv->max_agg_bufsize, buf_size);
3162
3163                 if (priv->cfg->ht_params &&
3164                     priv->cfg->ht_params->use_rts_for_aggregation) {
3165                         /*
3166                          * switch to RTS/CTS if it is the prefer protection
3167                          * method for HT traffic
3168                          */
3169
3170                         sta_priv->lq_sta.lq.general_params.flags |=
3171                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3172                 }
3173
3174                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3175                         sta_priv->max_agg_bufsize;
3176
3177                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3178                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3179                 ret = 0;
3180                 break;
3181         }
3182         mutex_unlock(&priv->mutex);
3183
3184         return ret;
3185 }
3186
3187 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3188                               struct ieee80211_vif *vif,
3189                               struct ieee80211_sta *sta)
3190 {
3191         struct iwl_priv *priv = hw->priv;
3192         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3193         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3194         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3195         int ret;
3196         u8 sta_id;
3197
3198         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3199                         sta->addr);
3200         mutex_lock(&priv->mutex);
3201         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3202                         sta->addr);
3203         sta_priv->common.sta_id = IWL_INVALID_STATION;
3204
3205         atomic_set(&sta_priv->pending_frames, 0);
3206         if (vif->type == NL80211_IFTYPE_AP)
3207                 sta_priv->client = true;
3208
3209         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3210                                      is_ap, sta, &sta_id);
3211         if (ret) {
3212                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3213                         sta->addr, ret);
3214                 /* Should we return success if return code is EEXIST ? */
3215                 mutex_unlock(&priv->mutex);
3216                 return ret;
3217         }
3218
3219         sta_priv->common.sta_id = sta_id;
3220
3221         /* Initialize rate scaling */
3222         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3223                        sta->addr);
3224         iwl_rs_rate_init(priv, sta, sta_id);
3225         mutex_unlock(&priv->mutex);
3226
3227         return 0;
3228 }
3229
3230 static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3231                                 struct ieee80211_channel_switch *ch_switch)
3232 {
3233         struct iwl_priv *priv = hw->priv;
3234         const struct iwl_channel_info *ch_info;
3235         struct ieee80211_conf *conf = &hw->conf;
3236         struct ieee80211_channel *channel = ch_switch->channel;
3237         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3238         /*
3239          * MULTI-FIXME
3240          * When we add support for multiple interfaces, we need to
3241          * revisit this. The channel switch command in the device
3242          * only affects the BSS context, but what does that really
3243          * mean? And what if we get a CSA on the second interface?
3244          * This needs a lot of work.
3245          */
3246         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3247         u16 ch;
3248         unsigned long flags = 0;
3249
3250         IWL_DEBUG_MAC80211(priv, "enter\n");
3251
3252         mutex_lock(&priv->mutex);
3253
3254         if (iwl_is_rfkill(priv))
3255                 goto out;
3256
3257         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3258             test_bit(STATUS_SCANNING, &priv->status))
3259                 goto out;
3260
3261         if (!iwl_is_associated_ctx(ctx))
3262                 goto out;
3263
3264         /* channel switch in progress */
3265         if (priv->switch_rxon.switch_in_progress == true)
3266                 goto out;
3267
3268         if (priv->cfg->ops->lib->set_channel_switch) {
3269
3270                 ch = channel->hw_value;
3271                 if (le16_to_cpu(ctx->active.channel) != ch) {
3272                         ch_info = iwl_get_channel_info(priv,
3273                                                        channel->band,
3274                                                        ch);
3275                         if (!is_channel_valid(ch_info)) {
3276                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3277                                 goto out;
3278                         }
3279                         spin_lock_irqsave(&priv->lock, flags);
3280
3281                         priv->current_ht_config.smps = conf->smps_mode;
3282
3283                         /* Configure HT40 channels */
3284                         ctx->ht.enabled = conf_is_ht(conf);
3285                         if (ctx->ht.enabled) {
3286                                 if (conf_is_ht40_minus(conf)) {
3287                                         ctx->ht.extension_chan_offset =
3288                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3289                                         ctx->ht.is_40mhz = true;
3290                                 } else if (conf_is_ht40_plus(conf)) {
3291                                         ctx->ht.extension_chan_offset =
3292                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3293                                         ctx->ht.is_40mhz = true;
3294                                 } else {
3295                                         ctx->ht.extension_chan_offset =
3296                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3297                                         ctx->ht.is_40mhz = false;
3298                                 }
3299                         } else
3300                                 ctx->ht.is_40mhz = false;
3301
3302                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3303                                 ctx->staging.flags = 0;
3304
3305                         iwl_set_rxon_channel(priv, channel, ctx);
3306                         iwl_set_rxon_ht(priv, ht_conf);
3307                         iwl_set_flags_for_band(priv, ctx, channel->band,
3308                                                ctx->vif);
3309                         spin_unlock_irqrestore(&priv->lock, flags);
3310
3311                         iwl_set_rate(priv);
3312                         /*
3313                          * at this point, staging_rxon has the
3314                          * configuration for channel switch
3315                          */
3316                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3317                                                                     ch_switch))
3318                                 priv->switch_rxon.switch_in_progress = false;
3319                 }
3320         }
3321 out:
3322         mutex_unlock(&priv->mutex);
3323         if (!priv->switch_rxon.switch_in_progress)
3324                 ieee80211_chswitch_done(ctx->vif, false);
3325         IWL_DEBUG_MAC80211(priv, "leave\n");
3326 }
3327
3328 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3329                                     unsigned int changed_flags,
3330                                     unsigned int *total_flags,
3331                                     u64 multicast)
3332 {
3333         struct iwl_priv *priv = hw->priv;
3334         __le32 filter_or = 0, filter_nand = 0;
3335         struct iwl_rxon_context *ctx;
3336
3337 #define CHK(test, flag) do { \
3338         if (*total_flags & (test))              \
3339                 filter_or |= (flag);            \
3340         else                                    \
3341                 filter_nand |= (flag);          \
3342         } while (0)
3343
3344         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3345                         changed_flags, *total_flags);
3346
3347         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3348         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3349         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3350         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3351
3352 #undef CHK
3353
3354         mutex_lock(&priv->mutex);
3355
3356         for_each_context(priv, ctx) {
3357                 ctx->staging.filter_flags &= ~filter_nand;
3358                 ctx->staging.filter_flags |= filter_or;
3359
3360                 /*
3361                  * Not committing directly because hardware can perform a scan,
3362                  * but we'll eventually commit the filter flags change anyway.
3363                  */
3364         }
3365
3366         mutex_unlock(&priv->mutex);
3367
3368         /*
3369          * Receiving all multicast frames is always enabled by the
3370          * default flags setup in iwl_connection_init_rx_config()
3371          * since we currently do not support programming multicast
3372          * filters into the device.
3373          */
3374         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3375                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3376 }
3377
3378 static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3379 {
3380         struct iwl_priv *priv = hw->priv;
3381
3382         mutex_lock(&priv->mutex);
3383         IWL_DEBUG_MAC80211(priv, "enter\n");
3384
3385         /* do not support "flush" */
3386         if (!priv->cfg->ops->lib->txfifo_flush)
3387                 goto done;
3388
3389         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3390                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3391                 goto done;
3392         }
3393         if (iwl_is_rfkill(priv)) {
3394                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3395                 goto done;
3396         }
3397
3398         /*
3399          * mac80211 will not push any more frames for transmit
3400          * until the flush is completed
3401          */
3402         if (drop) {
3403                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3404                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3405                         IWL_ERR(priv, "flush request fail\n");
3406                         goto done;
3407                 }
3408         }
3409         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3410         iwlagn_wait_tx_queue_empty(priv);
3411 done:
3412         mutex_unlock(&priv->mutex);
3413         IWL_DEBUG_MAC80211(priv, "leave\n");
3414 }
3415
3416 static void iwlagn_disable_roc(struct iwl_priv *priv)
3417 {
3418         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3419         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3420
3421         lockdep_assert_held(&priv->mutex);
3422
3423         if (!ctx->is_active)
3424                 return;
3425
3426         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3427         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3428         iwl_set_rxon_channel(priv, chan, ctx);
3429         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3430
3431         priv->_agn.hw_roc_channel = NULL;
3432
3433         iwlcore_commit_rxon(priv, ctx);
3434
3435         ctx->is_active = false;
3436 }
3437
3438 static void iwlagn_bg_roc_done(struct work_struct *work)
3439 {
3440         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3441                                              _agn.hw_roc_work.work);
3442
3443         mutex_lock(&priv->mutex);
3444         ieee80211_remain_on_channel_expired(priv->hw);
3445         iwlagn_disable_roc(priv);
3446         mutex_unlock(&priv->mutex);
3447 }
3448
3449 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3450                                      struct ieee80211_channel *channel,
3451                                      enum nl80211_channel_type channel_type,
3452                                      int duration)
3453 {
3454         struct iwl_priv *priv = hw->priv;
3455         int err = 0;
3456
3457         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3458                 return -EOPNOTSUPP;
3459
3460         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3461                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3462                 return -EOPNOTSUPP;
3463
3464         mutex_lock(&priv->mutex);
3465
3466         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3467             test_bit(STATUS_SCAN_HW, &priv->status)) {
3468                 err = -EBUSY;
3469                 goto out;
3470         }
3471
3472         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3473         priv->_agn.hw_roc_channel = channel;
3474         priv->_agn.hw_roc_chantype = channel_type;
3475         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3476         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3477         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3478                            msecs_to_jiffies(duration + 20));
3479
3480         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3481         ieee80211_ready_on_channel(priv->hw);
3482
3483  out:
3484         mutex_unlock(&priv->mutex);
3485
3486         return err;
3487 }
3488
3489 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3490 {
3491         struct iwl_priv *priv = hw->priv;
3492
3493         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3494                 return -EOPNOTSUPP;
3495
3496         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3497
3498         mutex_lock(&priv->mutex);
3499         iwlagn_disable_roc(priv);
3500         mutex_unlock(&priv->mutex);
3501
3502         return 0;
3503 }
3504
3505 /*****************************************************************************
3506  *
3507  * driver setup and teardown
3508  *
3509  *****************************************************************************/
3510
3511 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3512 {
3513         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3514
3515         init_waitqueue_head(&priv->wait_command_queue);
3516
3517         INIT_WORK(&priv->restart, iwl_bg_restart);
3518         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3519         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3520         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3521         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3522         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3523         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3524         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3525         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3526         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3527
3528         iwl_setup_scan_deferred_work(priv);
3529
3530         if (priv->cfg->ops->lib->setup_deferred_work)
3531                 priv->cfg->ops->lib->setup_deferred_work(priv);
3532
3533         init_timer(&priv->statistics_periodic);
3534         priv->statistics_periodic.data = (unsigned long)priv;
3535         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3536
3537         init_timer(&priv->ucode_trace);
3538         priv->ucode_trace.data = (unsigned long)priv;
3539         priv->ucode_trace.function = iwl_bg_ucode_trace;
3540
3541         init_timer(&priv->watchdog);
3542         priv->watchdog.data = (unsigned long)priv;
3543         priv->watchdog.function = iwl_bg_watchdog;
3544
3545         tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3546                 iwl_irq_tasklet, (unsigned long)priv);
3547 }
3548
3549 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3550 {
3551         if (priv->cfg->ops->lib->cancel_deferred_work)
3552                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3553
3554         cancel_delayed_work_sync(&priv->init_alive_start);
3555         cancel_delayed_work(&priv->alive_start);
3556         cancel_work_sync(&priv->run_time_calib_work);
3557         cancel_work_sync(&priv->beacon_update);
3558
3559         iwl_cancel_scan_deferred_work(priv);
3560
3561         cancel_work_sync(&priv->bt_full_concurrency);
3562         cancel_work_sync(&priv->bt_runtime_config);
3563
3564         del_timer_sync(&priv->statistics_periodic);
3565         del_timer_sync(&priv->ucode_trace);
3566 }
3567
3568 static void iwl_init_hw_rates(struct iwl_priv *priv,
3569                               struct ieee80211_rate *rates)
3570 {
3571         int i;
3572
3573         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3574                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3575                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3576                 rates[i].hw_value_short = i;
3577                 rates[i].flags = 0;
3578                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3579                         /*
3580                          * If CCK != 1M then set short preamble rate flag.
3581                          */
3582                         rates[i].flags |=
3583                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3584                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3585                 }
3586         }
3587 }
3588
3589 static int iwl_init_drv(struct iwl_priv *priv)
3590 {
3591         int ret;
3592
3593         spin_lock_init(&priv->sta_lock);
3594         spin_lock_init(&priv->hcmd_lock);
3595
3596         INIT_LIST_HEAD(&priv->free_frames);
3597
3598         mutex_init(&priv->mutex);
3599
3600         priv->ieee_channels = NULL;
3601         priv->ieee_rates = NULL;
3602         priv->band = IEEE80211_BAND_2GHZ;
3603
3604         priv->iw_mode = NL80211_IFTYPE_STATION;
3605         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3606         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3607         priv->_agn.agg_tids_count = 0;
3608
3609         /* initialize force reset */
3610         priv->force_reset[IWL_RF_RESET].reset_duration =
3611                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3612         priv->force_reset[IWL_FW_RESET].reset_duration =
3613                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3614
3615         priv->rx_statistics_jiffies = jiffies;
3616
3617         /* Choose which receivers/antennas to use */
3618         if (priv->cfg->ops->hcmd->set_rxon_chain)
3619                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3620                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3621
3622         iwl_init_scan_params(priv);
3623
3624         /* init bt coex */
3625         if (priv->cfg->bt_params &&
3626             priv->cfg->bt_params->advanced_bt_coexist) {
3627                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3628                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3629                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3630                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3631                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3632                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3633         }
3634
3635         /* Set the tx_power_user_lmt to the lowest power level
3636          * this value will get overwritten by channel max power avg
3637          * from eeprom */
3638         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3639         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3640
3641         ret = iwl_init_channel_map(priv);
3642         if (ret) {
3643                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3644                 goto err;
3645         }
3646
3647         ret = iwlcore_init_geos(priv);
3648         if (ret) {
3649                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3650                 goto err_free_channel_map;
3651         }
3652         iwl_init_hw_rates(priv, priv->ieee_rates);
3653
3654         return 0;
3655
3656 err_free_channel_map:
3657         iwl_free_channel_map(priv);
3658 err:
3659         return ret;
3660 }
3661
3662 static void iwl_uninit_drv(struct iwl_priv *priv)
3663 {
3664         iwl_calib_free_results(priv);
3665         iwlcore_free_geos(priv);
3666         iwl_free_channel_map(priv);
3667         kfree(priv->scan_cmd);
3668 }
3669
3670 struct ieee80211_ops iwlagn_hw_ops = {
3671         .tx = iwlagn_mac_tx,
3672         .start = iwlagn_mac_start,
3673         .stop = iwlagn_mac_stop,
3674         .add_interface = iwl_mac_add_interface,
3675         .remove_interface = iwl_mac_remove_interface,
3676         .change_interface = iwl_mac_change_interface,
3677         .config = iwlagn_mac_config,
3678         .configure_filter = iwlagn_configure_filter,
3679         .set_key = iwlagn_mac_set_key,
3680         .update_tkip_key = iwlagn_mac_update_tkip_key,
3681         .conf_tx = iwl_mac_conf_tx,
3682         .bss_info_changed = iwlagn_bss_info_changed,
3683         .ampdu_action = iwlagn_mac_ampdu_action,
3684         .hw_scan = iwl_mac_hw_scan,
3685         .sta_notify = iwlagn_mac_sta_notify,
3686         .sta_add = iwlagn_mac_sta_add,
3687         .sta_remove = iwl_mac_sta_remove,
3688         .channel_switch = iwlagn_mac_channel_switch,
3689         .flush = iwlagn_mac_flush,
3690         .tx_last_beacon = iwl_mac_tx_last_beacon,
3691         .remain_on_channel = iwl_mac_remain_on_channel,
3692         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3693         .offchannel_tx = iwl_mac_offchannel_tx,
3694         .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3695 };
3696
3697 static void iwl_hw_detect(struct iwl_priv *priv)
3698 {
3699         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
3700         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
3701         priv->rev_id = priv->pci_dev->revision;
3702         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3703 }
3704
3705 static int iwl_set_hw_params(struct iwl_priv *priv)
3706 {
3707         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3708         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3709         if (priv->cfg->mod_params->amsdu_size_8K)
3710                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3711         else
3712                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3713
3714         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3715
3716         if (priv->cfg->mod_params->disable_11n)
3717                 priv->cfg->sku &= ~IWL_SKU_N;
3718
3719         /* Device-specific setup */
3720         return priv->cfg->ops->lib->set_hw_params(priv);
3721 }
3722
3723 static const u8 iwlagn_bss_ac_to_fifo[] = {
3724         IWL_TX_FIFO_VO,
3725         IWL_TX_FIFO_VI,
3726         IWL_TX_FIFO_BE,
3727         IWL_TX_FIFO_BK,
3728 };
3729
3730 static const u8 iwlagn_bss_ac_to_queue[] = {
3731         0, 1, 2, 3,
3732 };
3733
3734 static const u8 iwlagn_pan_ac_to_fifo[] = {
3735         IWL_TX_FIFO_VO_IPAN,
3736         IWL_TX_FIFO_VI_IPAN,
3737         IWL_TX_FIFO_BE_IPAN,
3738         IWL_TX_FIFO_BK_IPAN,
3739 };
3740
3741 static const u8 iwlagn_pan_ac_to_queue[] = {
3742         7, 6, 5, 4,
3743 };
3744
3745 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3746 {
3747         int err = 0, i;
3748         struct iwl_priv *priv;
3749         struct ieee80211_hw *hw;
3750         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3751         unsigned long flags;
3752         u16 pci_cmd, num_mac;
3753
3754         /************************
3755          * 1. Allocating HW data
3756          ************************/
3757
3758         hw = iwl_alloc_all(cfg);
3759         if (!hw) {
3760                 err = -ENOMEM;
3761                 goto out;
3762         }
3763         priv = hw->priv;
3764         /* At this point both hw and priv are allocated. */
3765
3766         /*
3767          * The default context is always valid,
3768          * more may be discovered when firmware
3769          * is loaded.
3770          */
3771         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3772
3773         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3774                 priv->contexts[i].ctxid = i;
3775
3776         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3777         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3778         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3779         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3780         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3781         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3782         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3783         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3784         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3785         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3786         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3787                 BIT(NL80211_IFTYPE_ADHOC);
3788         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3789                 BIT(NL80211_IFTYPE_STATION);
3790         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3791         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3792         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3793         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3794
3795         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3796         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3797         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3798         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3799         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3800         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3801         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3802         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3803         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3804         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3805         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3806         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3807                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3808 #ifdef CONFIG_IWL_P2P
3809         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3810                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3811 #endif
3812         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3813         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3814         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3815
3816         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3817
3818         SET_IEEE80211_DEV(hw, &pdev->dev);
3819
3820         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3821         priv->cfg = cfg;
3822         priv->pci_dev = pdev;
3823         priv->inta_mask = CSR_INI_SET_MASK;
3824
3825         /* is antenna coupling more than 35dB ? */
3826         priv->bt_ant_couple_ok =
3827                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3828                 true : false;
3829
3830         /* enable/disable bt channel inhibition */
3831         priv->bt_ch_announce = iwlagn_bt_ch_announce;
3832         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3833                        (priv->bt_ch_announce) ? "On" : "Off");
3834
3835         if (iwl_alloc_traffic_mem(priv))
3836                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3837
3838         /**************************
3839          * 2. Initializing PCI bus
3840          **************************/
3841         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3842                                 PCIE_LINK_STATE_CLKPM);
3843
3844         if (pci_enable_device(pdev)) {
3845                 err = -ENODEV;
3846                 goto out_ieee80211_free_hw;
3847         }
3848
3849         pci_set_master(pdev);
3850
3851         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3852         if (!err)
3853                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3854         if (err) {
3855                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3856                 if (!err)
3857                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3858                 /* both attempts failed: */
3859                 if (err) {
3860                         IWL_WARN(priv, "No suitable DMA available.\n");
3861                         goto out_pci_disable_device;
3862                 }
3863         }
3864
3865         err = pci_request_regions(pdev, DRV_NAME);
3866         if (err)
3867                 goto out_pci_disable_device;
3868
3869         pci_set_drvdata(pdev, priv);
3870
3871
3872         /***********************
3873          * 3. Read REV register
3874          ***********************/
3875         priv->hw_base = pci_iomap(pdev, 0, 0);
3876         if (!priv->hw_base) {
3877                 err = -ENODEV;
3878                 goto out_pci_release_regions;
3879         }
3880
3881         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3882                 (unsigned long long) pci_resource_len(pdev, 0));
3883         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3884
3885         /* these spin locks will be used in apm_ops.init and EEPROM access
3886          * we should init now
3887          */
3888         spin_lock_init(&priv->reg_lock);
3889         spin_lock_init(&priv->lock);
3890
3891         /*
3892          * stop and reset the on-board processor just in case it is in a
3893          * strange state ... like being left stranded by a primary kernel
3894          * and this is now the kdump kernel trying to start up
3895          */
3896         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3897
3898         iwl_hw_detect(priv);
3899         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3900                 priv->cfg->name, priv->hw_rev);
3901
3902         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3903          * PCI Tx retries from interfering with C3 CPU state */
3904         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3905
3906         iwl_prepare_card_hw(priv);
3907         if (!priv->hw_ready) {
3908                 IWL_WARN(priv, "Failed, HW not ready\n");
3909                 goto out_iounmap;
3910         }
3911
3912         /*****************
3913          * 4. Read EEPROM
3914          *****************/
3915         /* Read the EEPROM */
3916         err = iwl_eeprom_init(priv);
3917         if (err) {
3918                 IWL_ERR(priv, "Unable to init EEPROM\n");
3919                 goto out_iounmap;
3920         }
3921         err = iwl_eeprom_check_version(priv);
3922         if (err)
3923                 goto out_free_eeprom;
3924
3925         err = iwl_eeprom_check_sku(priv);
3926         if (err)
3927                 goto out_free_eeprom;
3928
3929         /* extract MAC Address */
3930         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3931         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3932         priv->hw->wiphy->addresses = priv->addresses;
3933         priv->hw->wiphy->n_addresses = 1;
3934         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3935         if (num_mac > 1) {
3936                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3937                        ETH_ALEN);
3938                 priv->addresses[1].addr[5]++;
3939                 priv->hw->wiphy->n_addresses++;
3940         }
3941
3942         /************************
3943          * 5. Setup HW constants
3944          ************************/
3945         if (iwl_set_hw_params(priv)) {
3946                 IWL_ERR(priv, "failed to set hw parameters\n");
3947                 goto out_free_eeprom;
3948         }
3949
3950         /*******************
3951          * 6. Setup priv
3952          *******************/
3953
3954         err = iwl_init_drv(priv);
3955         if (err)
3956                 goto out_free_eeprom;
3957         /* At this point both hw and priv are initialized. */
3958
3959         /********************
3960          * 7. Setup services
3961          ********************/
3962         spin_lock_irqsave(&priv->lock, flags);
3963         iwl_disable_interrupts(priv);
3964         spin_unlock_irqrestore(&priv->lock, flags);
3965
3966         pci_enable_msi(priv->pci_dev);
3967
3968         if (priv->cfg->ops->lib->isr_ops.alloc)
3969                 priv->cfg->ops->lib->isr_ops.alloc(priv);
3970
3971         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
3972                           IRQF_SHARED, DRV_NAME, priv);
3973         if (err) {
3974                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3975                 goto out_disable_msi;
3976         }
3977
3978         iwl_setup_deferred_work(priv);
3979         iwl_setup_rx_handlers(priv);
3980
3981         /*********************************************
3982          * 8. Enable interrupts and read RFKILL state
3983          *********************************************/
3984
3985         /* enable rfkill interrupt: hw bug w/a */
3986         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3987         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3988                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3989                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3990         }
3991
3992         iwl_enable_rfkill_int(priv);
3993
3994         /* If platform's RF_KILL switch is NOT set to KILL */
3995         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3996                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3997         else
3998                 set_bit(STATUS_RF_KILL_HW, &priv->status);
3999
4000         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4001                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4002
4003         iwl_power_initialize(priv);
4004         iwl_tt_initialize(priv);
4005
4006         init_completion(&priv->_agn.firmware_loading_complete);
4007
4008         err = iwl_request_firmware(priv, true);
4009         if (err)
4010                 goto out_destroy_workqueue;
4011
4012         return 0;
4013
4014  out_destroy_workqueue:
4015         destroy_workqueue(priv->workqueue);
4016         priv->workqueue = NULL;
4017         free_irq(priv->pci_dev->irq, priv);
4018         if (priv->cfg->ops->lib->isr_ops.free)
4019                 priv->cfg->ops->lib->isr_ops.free(priv);
4020  out_disable_msi:
4021         pci_disable_msi(priv->pci_dev);
4022         iwl_uninit_drv(priv);
4023  out_free_eeprom:
4024         iwl_eeprom_free(priv);
4025  out_iounmap:
4026         pci_iounmap(pdev, priv->hw_base);
4027  out_pci_release_regions:
4028         pci_set_drvdata(pdev, NULL);
4029         pci_release_regions(pdev);
4030  out_pci_disable_device:
4031         pci_disable_device(pdev);
4032  out_ieee80211_free_hw:
4033         iwl_free_traffic_mem(priv);
4034         ieee80211_free_hw(priv->hw);
4035  out:
4036         return err;
4037 }
4038
4039 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4040 {
4041         struct iwl_priv *priv = pci_get_drvdata(pdev);
4042         unsigned long flags;
4043
4044         if (!priv)
4045                 return;
4046
4047         wait_for_completion(&priv->_agn.firmware_loading_complete);
4048
4049         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4050
4051         iwl_dbgfs_unregister(priv);
4052         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4053
4054         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4055          * to be called and iwl_down since we are removing the device
4056          * we need to set STATUS_EXIT_PENDING bit.
4057          */
4058         set_bit(STATUS_EXIT_PENDING, &priv->status);
4059
4060         iwl_leds_exit(priv);
4061
4062         if (priv->mac80211_registered) {
4063                 ieee80211_unregister_hw(priv->hw);
4064                 priv->mac80211_registered = 0;
4065         } else {
4066                 iwl_down(priv);
4067         }
4068
4069         /*
4070          * Make sure device is reset to low power before unloading driver.
4071          * This may be redundant with iwl_down(), but there are paths to
4072          * run iwl_down() without calling apm_ops.stop(), and there are
4073          * paths to avoid running iwl_down() at all before leaving driver.
4074          * This (inexpensive) call *makes sure* device is reset.
4075          */
4076         iwl_apm_stop(priv);
4077
4078         iwl_tt_exit(priv);
4079
4080         /* make sure we flush any pending irq or
4081          * tasklet for the driver
4082          */
4083         spin_lock_irqsave(&priv->lock, flags);
4084         iwl_disable_interrupts(priv);
4085         spin_unlock_irqrestore(&priv->lock, flags);
4086
4087         iwl_synchronize_irq(priv);
4088
4089         iwl_dealloc_ucode_pci(priv);
4090
4091         if (priv->rxq.bd)
4092                 iwlagn_rx_queue_free(priv, &priv->rxq);
4093         iwlagn_hw_txq_ctx_free(priv);
4094
4095         iwl_eeprom_free(priv);
4096
4097
4098         /*netif_stop_queue(dev); */
4099         flush_workqueue(priv->workqueue);
4100
4101         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4102          * priv->workqueue... so we can't take down the workqueue
4103          * until now... */
4104         destroy_workqueue(priv->workqueue);
4105         priv->workqueue = NULL;
4106         iwl_free_traffic_mem(priv);
4107
4108         free_irq(priv->pci_dev->irq, priv);
4109         pci_disable_msi(priv->pci_dev);
4110         pci_iounmap(pdev, priv->hw_base);
4111         pci_release_regions(pdev);
4112         pci_disable_device(pdev);
4113         pci_set_drvdata(pdev, NULL);
4114
4115         iwl_uninit_drv(priv);
4116
4117         if (priv->cfg->ops->lib->isr_ops.free)
4118                 priv->cfg->ops->lib->isr_ops.free(priv);
4119
4120         dev_kfree_skb(priv->beacon_skb);
4121
4122         ieee80211_free_hw(priv->hw);
4123 }
4124
4125
4126 /*****************************************************************************
4127  *
4128  * driver and module entry point
4129  *
4130  *****************************************************************************/
4131
4132 /* Hardware specific file defines the PCI IDs table for that hardware module */
4133 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4134         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4135         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4136         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4137         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4138         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4139         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4140         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4141         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4142         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4143         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4144         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4145         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4146         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4147         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4148         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4149         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4150         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4151         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4152         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4153         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4154         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4155         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4156         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4157         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4158
4159 /* 5300 Series WiFi */
4160         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4161         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4162         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4163         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4164         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4165         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4166         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4167         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4168         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4169         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4170         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4171         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4172
4173 /* 5350 Series WiFi/WiMax */
4174         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4175         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4176         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4177
4178 /* 5150 Series Wifi/WiMax */
4179         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4180         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4181         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4182         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4183         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4184         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4185
4186         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4187         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4188         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4189         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4190
4191 /* 6x00 Series */
4192         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4193         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4194         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4195         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4196         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4197         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4198         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4199         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4200         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4201         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4202
4203 /* 6x05 Series */
4204         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4205         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4206         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4207         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4208         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4209         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4210         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4211
4212 /* 6x30 Series */
4213         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4214         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4215         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4216         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4217         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4218         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4219         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4220         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4221         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4222         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4223         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4224         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4225         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4226         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4227         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4228         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4229
4230 /* 6x50 WiFi/WiMax Series */
4231         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4232         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4233         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4234         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4235         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4236         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4237
4238 /* 6150 WiFi/WiMax Series */
4239         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4240         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4241         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4242         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4243         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4244         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4245
4246 /* 1000 Series WiFi */
4247         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4248         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4249         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4250         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4251         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4252         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4253         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4254         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4255         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4256         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4257         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4258         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4259
4260 /* 100 Series WiFi */
4261         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4262         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4263         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4264         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4265         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4266         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4267
4268 /* 130 Series WiFi */
4269         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4270         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4271         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4272         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4273         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4274         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4275
4276 /* 2x00 Series */
4277         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4278         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4279         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4280         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4281         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4282         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4283
4284 /* 2x30 Series */
4285         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4286         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4287         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4288         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4289         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4290         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4291
4292 /* 6x35 Series */
4293         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4294         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4295         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4296         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4297         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4298         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4299         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4300         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4301         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4302
4303 /* 200 Series */
4304         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4305         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4306         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4307         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4308         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4309         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4310
4311 /* 230 Series */
4312         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4313         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4314         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4315         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4316         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4317         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4318
4319         {0}
4320 };
4321 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4322
4323 static struct pci_driver iwl_driver = {
4324         .name = DRV_NAME,
4325         .id_table = iwl_hw_card_ids,
4326         .probe = iwl_pci_probe,
4327         .remove = __devexit_p(iwl_pci_remove),
4328         .driver.pm = IWL_PM_OPS,
4329 };
4330
4331 static int __init iwl_init(void)
4332 {
4333
4334         int ret;
4335         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4336         pr_info(DRV_COPYRIGHT "\n");
4337
4338         ret = iwlagn_rate_control_register();
4339         if (ret) {
4340                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4341                 return ret;
4342         }
4343
4344         ret = pci_register_driver(&iwl_driver);
4345         if (ret) {
4346                 pr_err("Unable to initialize PCI module\n");
4347                 goto error_register;
4348         }
4349
4350         return ret;
4351
4352 error_register:
4353         iwlagn_rate_control_unregister();
4354         return ret;
4355 }
4356
4357 static void __exit iwl_exit(void)
4358 {
4359         pci_unregister_driver(&iwl_driver);
4360         iwlagn_rate_control_unregister();
4361 }
4362
4363 module_exit(iwl_exit);
4364 module_init(iwl_init);
4365
4366 #ifdef CONFIG_IWLWIFI_DEBUG
4367 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4368 MODULE_PARM_DESC(debug, "debug output mask");
4369 #endif
4370
4371 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4372 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4373 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4374 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4375 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4376 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4377 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4378                    int, S_IRUGO);
4379 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4380 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4381 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4382
4383 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4384                    S_IRUGO);
4385 MODULE_PARM_DESC(ucode_alternative,
4386                  "specify ucode alternative to use from ucode file");
4387
4388 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4389 MODULE_PARM_DESC(antenna_coupling,
4390                  "specify antenna coupling in dB (defualt: 0 dB)");
4391
4392 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4393 MODULE_PARM_DESC(bt_ch_inhibition,
4394                  "Disable BT channel inhibition (default: enable)");
4395
4396 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4397 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4398
4399 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4400 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");