iwlwifi: add context pointer to station
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project, as well
6  * as portions of the ieee80211 subsystem header files.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of version 2 of the GNU General Public License as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20  *
21  * The full GNU General Public License is included in this distribution in the
22  * file called LICENSE.
23  *
24  * Contact Information:
25  *  Intel Linux Wireless <ilw@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
47
48 #include <net/mac80211.h>
49
50 #include <asm/div64.h>
51
52 #define DRV_NAME        "iwlagn"
53
54 #include "iwl-eeprom.h"
55 #include "iwl-dev.h"
56 #include "iwl-core.h"
57 #include "iwl-io.h"
58 #include "iwl-helpers.h"
59 #include "iwl-sta.h"
60 #include "iwl-calib.h"
61 #include "iwl-agn.h"
62
63
64 /******************************************************************************
65  *
66  * module boiler plate
67  *
68  ******************************************************************************/
69
70 /*
71  * module name, copyright, version, etc.
72  */
73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
74
75 #ifdef CONFIG_IWLWIFI_DEBUG
76 #define VD "d"
77 #else
78 #define VD
79 #endif
80
81 #define DRV_VERSION     IWLWIFI_VERSION VD
82
83
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88 MODULE_ALIAS("iwl4965");
89
90 static int iwlagn_ant_coupling;
91 static bool iwlagn_bt_ch_announce = 1;
92
93 /**
94  * iwl_commit_rxon - commit staging_rxon to hardware
95  *
96  * The RXON command in staging_rxon is committed to the hardware and
97  * the active_rxon structure is updated with the new data.  This
98  * function correctly transitions out of the RXON_ASSOC_MSK state if
99  * a HW tune is required based on the RXON structure changes.
100  */
101 int iwl_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
102 {
103         /* cast away the const for active_rxon in this function */
104         struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
105         int ret;
106         bool new_assoc =
107                 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
108
109         if (!iwl_is_alive(priv))
110                 return -EBUSY;
111
112         /* always get timestamp with Rx frame */
113         ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
114
115         ret = iwl_check_rxon_cmd(priv, ctx);
116         if (ret) {
117                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
118                 return -EINVAL;
119         }
120
121         /*
122          * receive commit_rxon request
123          * abort any previous channel switch if still in process
124          */
125         if (priv->switch_rxon.switch_in_progress &&
126             (priv->switch_rxon.channel != ctx->staging.channel)) {
127                 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
128                       le16_to_cpu(priv->switch_rxon.channel));
129                 iwl_chswitch_done(priv, false);
130         }
131
132         /* If we don't need to send a full RXON, we can use
133          * iwl_rxon_assoc_cmd which is used to reconfigure filter
134          * and other flags for the current radio configuration. */
135         if (!iwl_full_rxon_required(priv, ctx)) {
136                 ret = iwl_send_rxon_assoc(priv, ctx);
137                 if (ret) {
138                         IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
139                         return ret;
140                 }
141
142                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
143                 iwl_print_rx_config_cmd(priv, ctx);
144                 return 0;
145         }
146
147         /* If we are currently associated and the new config requires
148          * an RXON_ASSOC and the new config wants the associated mask enabled,
149          * we must clear the associated from the active configuration
150          * before we apply the new config */
151         if (iwl_is_associated_ctx(ctx) && new_assoc) {
152                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
153                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
154
155                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
156                                        sizeof(struct iwl_rxon_cmd),
157                                        active_rxon);
158
159                 /* If the mask clearing failed then we set
160                  * active_rxon back to what it was previously */
161                 if (ret) {
162                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
163                         IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
164                         return ret;
165                 }
166                 iwl_clear_ucode_stations(priv, ctx);
167                 iwl_restore_stations(priv, ctx);
168                 ret = iwl_restore_default_wep_keys(priv, ctx);
169                 if (ret) {
170                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
171                         return ret;
172                 }
173         }
174
175         IWL_DEBUG_INFO(priv, "Sending RXON\n"
176                        "* with%s RXON_FILTER_ASSOC_MSK\n"
177                        "* channel = %d\n"
178                        "* bssid = %pM\n",
179                        (new_assoc ? "" : "out"),
180                        le16_to_cpu(ctx->staging.channel),
181                        ctx->staging.bssid_addr);
182
183         iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
184
185         /* Apply the new configuration
186          * RXON unassoc clears the station table in uCode so restoration of
187          * stations is needed after it (the RXON command) completes
188          */
189         if (!new_assoc) {
190                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
191                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
192                 if (ret) {
193                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
194                         return ret;
195                 }
196                 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
197                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
198                 iwl_clear_ucode_stations(priv, ctx);
199                 iwl_restore_stations(priv, ctx);
200                 ret = iwl_restore_default_wep_keys(priv, ctx);
201                 if (ret) {
202                         IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
203                         return ret;
204                 }
205         }
206
207         priv->start_calib = 0;
208         if (new_assoc) {
209                 /* Apply the new configuration
210                  * RXON assoc doesn't clear the station table in uCode,
211                  */
212                 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
213                               sizeof(struct iwl_rxon_cmd), &ctx->staging);
214                 if (ret) {
215                         IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
216                         return ret;
217                 }
218                 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
219         }
220         iwl_print_rx_config_cmd(priv, ctx);
221
222         iwl_init_sensitivity(priv);
223
224         /* If we issue a new RXON command which required a tune then we must
225          * send a new TXPOWER command or we won't be able to Tx any frames */
226         ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
227         if (ret) {
228                 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
229                 return ret;
230         }
231
232         return 0;
233 }
234
235 void iwl_update_chain_flags(struct iwl_priv *priv)
236 {
237         struct iwl_rxon_context *ctx;
238
239         if (priv->cfg->ops->hcmd->set_rxon_chain) {
240                 for_each_context(priv, ctx) {
241                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
242                         iwlcore_commit_rxon(priv, ctx);
243                 }
244         }
245 }
246
247 static void iwl_clear_free_frames(struct iwl_priv *priv)
248 {
249         struct list_head *element;
250
251         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
252                        priv->frames_count);
253
254         while (!list_empty(&priv->free_frames)) {
255                 element = priv->free_frames.next;
256                 list_del(element);
257                 kfree(list_entry(element, struct iwl_frame, list));
258                 priv->frames_count--;
259         }
260
261         if (priv->frames_count) {
262                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
263                             priv->frames_count);
264                 priv->frames_count = 0;
265         }
266 }
267
268 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
269 {
270         struct iwl_frame *frame;
271         struct list_head *element;
272         if (list_empty(&priv->free_frames)) {
273                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
274                 if (!frame) {
275                         IWL_ERR(priv, "Could not allocate frame!\n");
276                         return NULL;
277                 }
278
279                 priv->frames_count++;
280                 return frame;
281         }
282
283         element = priv->free_frames.next;
284         list_del(element);
285         return list_entry(element, struct iwl_frame, list);
286 }
287
288 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
289 {
290         memset(frame, 0, sizeof(*frame));
291         list_add(&frame->list, &priv->free_frames);
292 }
293
294 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
295                                           struct ieee80211_hdr *hdr,
296                                           int left)
297 {
298         if (!priv->ibss_beacon)
299                 return 0;
300
301         if (priv->ibss_beacon->len > left)
302                 return 0;
303
304         memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
305
306         return priv->ibss_beacon->len;
307 }
308
309 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
310 static void iwl_set_beacon_tim(struct iwl_priv *priv,
311                 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
312                 u8 *beacon, u32 frame_size)
313 {
314         u16 tim_idx;
315         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
316
317         /*
318          * The index is relative to frame start but we start looking at the
319          * variable-length part of the beacon.
320          */
321         tim_idx = mgmt->u.beacon.variable - beacon;
322
323         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
324         while ((tim_idx < (frame_size - 2)) &&
325                         (beacon[tim_idx] != WLAN_EID_TIM))
326                 tim_idx += beacon[tim_idx+1] + 2;
327
328         /* If TIM field was found, set variables */
329         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
330                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
331                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
332         } else
333                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
334 }
335
336 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
337                                        struct iwl_frame *frame)
338 {
339         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
340         u32 frame_size;
341         u32 rate_flags;
342         u32 rate;
343         /*
344          * We have to set up the TX command, the TX Beacon command, and the
345          * beacon contents.
346          */
347
348         /* Initialize memory */
349         tx_beacon_cmd = &frame->u.beacon;
350         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
351
352         /* Set up TX beacon contents */
353         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
354                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
355         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
356                 return 0;
357
358         /* Set up TX command fields */
359         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
360 #warning "Use proper STA ID"
361         tx_beacon_cmd->tx.sta_id =
362                 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
363         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
364         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
365                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
366
367         /* Set up TX beacon command fields */
368         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
369                         frame_size);
370
371         /* Set up packet rate and flags */
372         rate = iwl_rate_get_lowest_plcp(priv);
373         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
374                                               priv->hw_params.valid_tx_ant);
375         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
376         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
377                 rate_flags |= RATE_MCS_CCK_MSK;
378         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
379                         rate_flags);
380
381         return sizeof(*tx_beacon_cmd) + frame_size;
382 }
383 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
384 {
385         struct iwl_frame *frame;
386         unsigned int frame_size;
387         int rc;
388
389         frame = iwl_get_free_frame(priv);
390         if (!frame) {
391                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
392                           "command.\n");
393                 return -ENOMEM;
394         }
395
396         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
397         if (!frame_size) {
398                 IWL_ERR(priv, "Error configuring the beacon command\n");
399                 iwl_free_frame(priv, frame);
400                 return -EINVAL;
401         }
402
403         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
404                               &frame->u.cmd[0]);
405
406         iwl_free_frame(priv, frame);
407
408         return rc;
409 }
410
411 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
412 {
413         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
414
415         dma_addr_t addr = get_unaligned_le32(&tb->lo);
416         if (sizeof(dma_addr_t) > sizeof(u32))
417                 addr |=
418                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
419
420         return addr;
421 }
422
423 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
424 {
425         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
426
427         return le16_to_cpu(tb->hi_n_len) >> 4;
428 }
429
430 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
431                                   dma_addr_t addr, u16 len)
432 {
433         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
434         u16 hi_n_len = len << 4;
435
436         put_unaligned_le32(addr, &tb->lo);
437         if (sizeof(dma_addr_t) > sizeof(u32))
438                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
439
440         tb->hi_n_len = cpu_to_le16(hi_n_len);
441
442         tfd->num_tbs = idx + 1;
443 }
444
445 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
446 {
447         return tfd->num_tbs & 0x1f;
448 }
449
450 /**
451  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
452  * @priv - driver private data
453  * @txq - tx queue
454  *
455  * Does NOT advance any TFD circular buffer read/write indexes
456  * Does NOT free the TFD itself (which is within circular buffer)
457  */
458 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
459 {
460         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
461         struct iwl_tfd *tfd;
462         struct pci_dev *dev = priv->pci_dev;
463         int index = txq->q.read_ptr;
464         int i;
465         int num_tbs;
466
467         tfd = &tfd_tmp[index];
468
469         /* Sanity check on number of chunks */
470         num_tbs = iwl_tfd_get_num_tbs(tfd);
471
472         if (num_tbs >= IWL_NUM_OF_TBS) {
473                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
474                 /* @todo issue fatal error, it is quite serious situation */
475                 return;
476         }
477
478         /* Unmap tx_cmd */
479         if (num_tbs)
480                 pci_unmap_single(dev,
481                                 dma_unmap_addr(&txq->meta[index], mapping),
482                                 dma_unmap_len(&txq->meta[index], len),
483                                 PCI_DMA_BIDIRECTIONAL);
484
485         /* Unmap chunks, if any. */
486         for (i = 1; i < num_tbs; i++)
487                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
488                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
489
490         /* free SKB */
491         if (txq->txb) {
492                 struct sk_buff *skb;
493
494                 skb = txq->txb[txq->q.read_ptr].skb;
495
496                 /* can be called from irqs-disabled context */
497                 if (skb) {
498                         dev_kfree_skb_any(skb);
499                         txq->txb[txq->q.read_ptr].skb = NULL;
500                 }
501         }
502 }
503
504 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
505                                  struct iwl_tx_queue *txq,
506                                  dma_addr_t addr, u16 len,
507                                  u8 reset, u8 pad)
508 {
509         struct iwl_queue *q;
510         struct iwl_tfd *tfd, *tfd_tmp;
511         u32 num_tbs;
512
513         q = &txq->q;
514         tfd_tmp = (struct iwl_tfd *)txq->tfds;
515         tfd = &tfd_tmp[q->write_ptr];
516
517         if (reset)
518                 memset(tfd, 0, sizeof(*tfd));
519
520         num_tbs = iwl_tfd_get_num_tbs(tfd);
521
522         /* Each TFD can point to a maximum 20 Tx buffers */
523         if (num_tbs >= IWL_NUM_OF_TBS) {
524                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
525                           IWL_NUM_OF_TBS);
526                 return -EINVAL;
527         }
528
529         BUG_ON(addr & ~DMA_BIT_MASK(36));
530         if (unlikely(addr & ~IWL_TX_DMA_MASK))
531                 IWL_ERR(priv, "Unaligned address = %llx\n",
532                           (unsigned long long)addr);
533
534         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
535
536         return 0;
537 }
538
539 /*
540  * Tell nic where to find circular buffer of Tx Frame Descriptors for
541  * given Tx queue, and enable the DMA channel used for that queue.
542  *
543  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
544  * channels supported in hardware.
545  */
546 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
547                          struct iwl_tx_queue *txq)
548 {
549         int txq_id = txq->q.id;
550
551         /* Circular buffer (TFD queue in DRAM) physical base address */
552         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
553                              txq->q.dma_addr >> 8);
554
555         return 0;
556 }
557
558 /******************************************************************************
559  *
560  * Generic RX handler implementations
561  *
562  ******************************************************************************/
563 static void iwl_rx_reply_alive(struct iwl_priv *priv,
564                                 struct iwl_rx_mem_buffer *rxb)
565 {
566         struct iwl_rx_packet *pkt = rxb_addr(rxb);
567         struct iwl_alive_resp *palive;
568         struct delayed_work *pwork;
569
570         palive = &pkt->u.alive_frame;
571
572         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
573                        "0x%01X 0x%01X\n",
574                        palive->is_valid, palive->ver_type,
575                        palive->ver_subtype);
576
577         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
578                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
579                 memcpy(&priv->card_alive_init,
580                        &pkt->u.alive_frame,
581                        sizeof(struct iwl_init_alive_resp));
582                 pwork = &priv->init_alive_start;
583         } else {
584                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
585                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
586                        sizeof(struct iwl_alive_resp));
587                 pwork = &priv->alive_start;
588         }
589
590         /* We delay the ALIVE response by 5ms to
591          * give the HW RF Kill time to activate... */
592         if (palive->is_valid == UCODE_VALID_OK)
593                 queue_delayed_work(priv->workqueue, pwork,
594                                    msecs_to_jiffies(5));
595         else
596                 IWL_WARN(priv, "uCode did not respond OK.\n");
597 }
598
599 static void iwl_bg_beacon_update(struct work_struct *work)
600 {
601         struct iwl_priv *priv =
602                 container_of(work, struct iwl_priv, beacon_update);
603         struct sk_buff *beacon;
604
605         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
606 #warning "introduce and use beacon context"
607         beacon = ieee80211_beacon_get(priv->hw,
608                         priv->contexts[IWL_RXON_CTX_BSS].vif);
609
610         if (!beacon) {
611                 IWL_ERR(priv, "update beacon failed\n");
612                 return;
613         }
614
615         mutex_lock(&priv->mutex);
616         /* new beacon skb is allocated every time; dispose previous.*/
617         if (priv->ibss_beacon)
618                 dev_kfree_skb(priv->ibss_beacon);
619
620         priv->ibss_beacon = beacon;
621         mutex_unlock(&priv->mutex);
622
623         iwl_send_beacon_cmd(priv);
624 }
625
626 static void iwl_bg_bt_runtime_config(struct work_struct *work)
627 {
628         struct iwl_priv *priv =
629                 container_of(work, struct iwl_priv, bt_runtime_config);
630
631         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
632                 return;
633
634         /* dont send host command if rf-kill is on */
635         if (!iwl_is_ready_rf(priv))
636                 return;
637         priv->cfg->ops->hcmd->send_bt_config(priv);
638 }
639
640 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
641 {
642         struct iwl_priv *priv =
643                 container_of(work, struct iwl_priv, bt_full_concurrency);
644         struct iwl_rxon_context *ctx;
645
646         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
647                 return;
648
649         /* dont send host command if rf-kill is on */
650         if (!iwl_is_ready_rf(priv))
651                 return;
652
653         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
654                        priv->bt_full_concurrent ?
655                        "full concurrency" : "3-wire");
656
657         /*
658          * LQ & RXON updated cmds must be sent before BT Config cmd
659          * to avoid 3-wire collisions
660          */
661         mutex_lock(&priv->mutex);
662         for_each_context(priv, ctx) {
663                 if (priv->cfg->ops->hcmd->set_rxon_chain)
664                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
665                 iwlcore_commit_rxon(priv, ctx);
666         }
667         mutex_unlock(&priv->mutex);
668
669         priv->cfg->ops->hcmd->send_bt_config(priv);
670 }
671
672 /**
673  * iwl_bg_statistics_periodic - Timer callback to queue statistics
674  *
675  * This callback is provided in order to send a statistics request.
676  *
677  * This timer function is continually reset to execute within
678  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
679  * was received.  We need to ensure we receive the statistics in order
680  * to update the temperature used for calibrating the TXPOWER.
681  */
682 static void iwl_bg_statistics_periodic(unsigned long data)
683 {
684         struct iwl_priv *priv = (struct iwl_priv *)data;
685
686         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
687                 return;
688
689         /* dont send host command if rf-kill is on */
690         if (!iwl_is_ready_rf(priv))
691                 return;
692
693         iwl_send_statistics_request(priv, CMD_ASYNC, false);
694 }
695
696
697 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
698                                         u32 start_idx, u32 num_events,
699                                         u32 mode)
700 {
701         u32 i;
702         u32 ptr;        /* SRAM byte address of log data */
703         u32 ev, time, data; /* event log data */
704         unsigned long reg_flags;
705
706         if (mode == 0)
707                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
708         else
709                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
710
711         /* Make sure device is powered up for SRAM reads */
712         spin_lock_irqsave(&priv->reg_lock, reg_flags);
713         if (iwl_grab_nic_access(priv)) {
714                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
715                 return;
716         }
717
718         /* Set starting address; reads will auto-increment */
719         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
720         rmb();
721
722         /*
723          * "time" is actually "data" for mode 0 (no timestamp).
724          * place event id # at far right for easier visual parsing.
725          */
726         for (i = 0; i < num_events; i++) {
727                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
728                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
729                 if (mode == 0) {
730                         trace_iwlwifi_dev_ucode_cont_event(priv,
731                                                         0, time, ev);
732                 } else {
733                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
734                         trace_iwlwifi_dev_ucode_cont_event(priv,
735                                                 time, data, ev);
736                 }
737         }
738         /* Allow device to power down */
739         iwl_release_nic_access(priv);
740         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
741 }
742
743 static void iwl_continuous_event_trace(struct iwl_priv *priv)
744 {
745         u32 capacity;   /* event log capacity in # entries */
746         u32 base;       /* SRAM byte address of event log header */
747         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
748         u32 num_wraps;  /* # times uCode wrapped to top of log */
749         u32 next_entry; /* index of next entry to be written by uCode */
750
751         if (priv->ucode_type == UCODE_INIT)
752                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
753         else
754                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
755         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
756                 capacity = iwl_read_targ_mem(priv, base);
757                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
758                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
759                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
760         } else
761                 return;
762
763         if (num_wraps == priv->event_log.num_wraps) {
764                 iwl_print_cont_event_trace(priv,
765                                        base, priv->event_log.next_entry,
766                                        next_entry - priv->event_log.next_entry,
767                                        mode);
768                 priv->event_log.non_wraps_count++;
769         } else {
770                 if ((num_wraps - priv->event_log.num_wraps) > 1)
771                         priv->event_log.wraps_more_count++;
772                 else
773                         priv->event_log.wraps_once_count++;
774                 trace_iwlwifi_dev_ucode_wrap_event(priv,
775                                 num_wraps - priv->event_log.num_wraps,
776                                 next_entry, priv->event_log.next_entry);
777                 if (next_entry < priv->event_log.next_entry) {
778                         iwl_print_cont_event_trace(priv, base,
779                                priv->event_log.next_entry,
780                                capacity - priv->event_log.next_entry,
781                                mode);
782
783                         iwl_print_cont_event_trace(priv, base, 0,
784                                 next_entry, mode);
785                 } else {
786                         iwl_print_cont_event_trace(priv, base,
787                                next_entry, capacity - next_entry,
788                                mode);
789
790                         iwl_print_cont_event_trace(priv, base, 0,
791                                 next_entry, mode);
792                 }
793         }
794         priv->event_log.num_wraps = num_wraps;
795         priv->event_log.next_entry = next_entry;
796 }
797
798 /**
799  * iwl_bg_ucode_trace - Timer callback to log ucode event
800  *
801  * The timer is continually set to execute every
802  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
803  * this function is to perform continuous uCode event logging operation
804  * if enabled
805  */
806 static void iwl_bg_ucode_trace(unsigned long data)
807 {
808         struct iwl_priv *priv = (struct iwl_priv *)data;
809
810         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
811                 return;
812
813         if (priv->event_log.ucode_trace) {
814                 iwl_continuous_event_trace(priv);
815                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
816                 mod_timer(&priv->ucode_trace,
817                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
818         }
819 }
820
821 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
822                                 struct iwl_rx_mem_buffer *rxb)
823 {
824         struct iwl_rx_packet *pkt = rxb_addr(rxb);
825         struct iwl4965_beacon_notif *beacon =
826                 (struct iwl4965_beacon_notif *)pkt->u.raw;
827 #ifdef CONFIG_IWLWIFI_DEBUG
828         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
829
830         IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
831                 "tsf %d %d rate %d\n",
832                 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
833                 beacon->beacon_notify_hdr.failure_frame,
834                 le32_to_cpu(beacon->ibss_mgr_status),
835                 le32_to_cpu(beacon->high_tsf),
836                 le32_to_cpu(beacon->low_tsf), rate);
837 #endif
838
839         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
840
841         if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
842             (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
843                 queue_work(priv->workqueue, &priv->beacon_update);
844 }
845
846 /* Handle notification from uCode that card's power state is changing
847  * due to software, hardware, or critical temperature RFKILL */
848 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
849                                     struct iwl_rx_mem_buffer *rxb)
850 {
851         struct iwl_rx_packet *pkt = rxb_addr(rxb);
852         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
853         unsigned long status = priv->status;
854
855         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
856                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
857                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
858                           (flags & CT_CARD_DISABLED) ?
859                           "Reached" : "Not reached");
860
861         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
862                      CT_CARD_DISABLED)) {
863
864                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
865                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
866
867                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
868                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
869
870                 if (!(flags & RXON_CARD_DISABLED)) {
871                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
872                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
873                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
874                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
875                 }
876                 if (flags & CT_CARD_DISABLED)
877                         iwl_tt_enter_ct_kill(priv);
878         }
879         if (!(flags & CT_CARD_DISABLED))
880                 iwl_tt_exit_ct_kill(priv);
881
882         if (flags & HW_CARD_DISABLED)
883                 set_bit(STATUS_RF_KILL_HW, &priv->status);
884         else
885                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
886
887
888         if (!(flags & RXON_CARD_DISABLED))
889                 iwl_scan_cancel(priv);
890
891         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
892              test_bit(STATUS_RF_KILL_HW, &priv->status)))
893                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
894                         test_bit(STATUS_RF_KILL_HW, &priv->status));
895         else
896                 wake_up_interruptible(&priv->wait_command_queue);
897 }
898
899 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
900 {
901         if (src == IWL_PWR_SRC_VAUX) {
902                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
903                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
904                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
905                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
906         } else {
907                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
908                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
909                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
910         }
911
912         return 0;
913 }
914
915 static void iwl_bg_tx_flush(struct work_struct *work)
916 {
917         struct iwl_priv *priv =
918                 container_of(work, struct iwl_priv, tx_flush);
919
920         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
921                 return;
922
923         /* do nothing if rf-kill is on */
924         if (!iwl_is_ready_rf(priv))
925                 return;
926
927         if (priv->cfg->ops->lib->txfifo_flush) {
928                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
929                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
930         }
931 }
932
933 /**
934  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
935  *
936  * Setup the RX handlers for each of the reply types sent from the uCode
937  * to the host.
938  *
939  * This function chains into the hardware specific files for them to setup
940  * any hardware specific handlers as well.
941  */
942 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
943 {
944         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
945         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
946         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
947         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
948                         iwl_rx_spectrum_measure_notif;
949         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
950         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
951             iwl_rx_pm_debug_statistics_notif;
952         priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
953
954         /*
955          * The same handler is used for both the REPLY to a discrete
956          * statistics request from the host as well as for the periodic
957          * statistics notifications (after received beacons) from the uCode.
958          */
959         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
960         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
961
962         iwl_setup_rx_scan_handlers(priv);
963
964         /* status change handler */
965         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
966
967         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
968             iwl_rx_missed_beacon_notif;
969         /* Rx handlers */
970         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
971         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
972         /* block ack */
973         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
974         /* Set up hardware specific Rx handlers */
975         priv->cfg->ops->lib->rx_handler_setup(priv);
976 }
977
978 /**
979  * iwl_rx_handle - Main entry function for receiving responses from uCode
980  *
981  * Uses the priv->rx_handlers callback function array to invoke
982  * the appropriate handlers, including command responses,
983  * frame-received notifications, and other notifications.
984  */
985 void iwl_rx_handle(struct iwl_priv *priv)
986 {
987         struct iwl_rx_mem_buffer *rxb;
988         struct iwl_rx_packet *pkt;
989         struct iwl_rx_queue *rxq = &priv->rxq;
990         u32 r, i;
991         int reclaim;
992         unsigned long flags;
993         u8 fill_rx = 0;
994         u32 count = 8;
995         int total_empty;
996
997         /* uCode's read index (stored in shared DRAM) indicates the last Rx
998          * buffer that the driver may process (last buffer filled by ucode). */
999         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
1000         i = rxq->read;
1001
1002         /* Rx interrupt, but nothing sent from uCode */
1003         if (i == r)
1004                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
1005
1006         /* calculate total frames need to be restock after handling RX */
1007         total_empty = r - rxq->write_actual;
1008         if (total_empty < 0)
1009                 total_empty += RX_QUEUE_SIZE;
1010
1011         if (total_empty > (RX_QUEUE_SIZE / 2))
1012                 fill_rx = 1;
1013
1014         while (i != r) {
1015                 int len;
1016
1017                 rxb = rxq->queue[i];
1018
1019                 /* If an RXB doesn't have a Rx queue slot associated with it,
1020                  * then a bug has been introduced in the queue refilling
1021                  * routines -- catch it here */
1022                 BUG_ON(rxb == NULL);
1023
1024                 rxq->queue[i] = NULL;
1025
1026                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1027                                PAGE_SIZE << priv->hw_params.rx_page_order,
1028                                PCI_DMA_FROMDEVICE);
1029                 pkt = rxb_addr(rxb);
1030
1031                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1032                 len += sizeof(u32); /* account for status word */
1033                 trace_iwlwifi_dev_rx(priv, pkt, len);
1034
1035                 /* Reclaim a command buffer only if this packet is a response
1036                  *   to a (driver-originated) command.
1037                  * If the packet (e.g. Rx frame) originated from uCode,
1038                  *   there is no command buffer to reclaim.
1039                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1040                  *   but apparently a few don't get set; catch them here. */
1041                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1042                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
1043                         (pkt->hdr.cmd != REPLY_RX) &&
1044                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
1045                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
1046                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1047                         (pkt->hdr.cmd != REPLY_TX);
1048
1049                 /* Based on type of command response or notification,
1050                  *   handle those that need handling via function in
1051                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
1052                 if (priv->rx_handlers[pkt->hdr.cmd]) {
1053                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
1054                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1055                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
1056                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
1057                 } else {
1058                         /* No handling needed */
1059                         IWL_DEBUG_RX(priv,
1060                                 "r %d i %d No handler needed for %s, 0x%02x\n",
1061                                 r, i, get_cmd_string(pkt->hdr.cmd),
1062                                 pkt->hdr.cmd);
1063                 }
1064
1065                 /*
1066                  * XXX: After here, we should always check rxb->page
1067                  * against NULL before touching it or its virtual
1068                  * memory (pkt). Because some rx_handler might have
1069                  * already taken or freed the pages.
1070                  */
1071
1072                 if (reclaim) {
1073                         /* Invoke any callbacks, transfer the buffer to caller,
1074                          * and fire off the (possibly) blocking iwl_send_cmd()
1075                          * as we reclaim the driver command queue */
1076                         if (rxb->page)
1077                                 iwl_tx_cmd_complete(priv, rxb);
1078                         else
1079                                 IWL_WARN(priv, "Claim null rxb?\n");
1080                 }
1081
1082                 /* Reuse the page if possible. For notification packets and
1083                  * SKBs that fail to Rx correctly, add them back into the
1084                  * rx_free list for reuse later. */
1085                 spin_lock_irqsave(&rxq->lock, flags);
1086                 if (rxb->page != NULL) {
1087                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1088                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1089                                 PCI_DMA_FROMDEVICE);
1090                         list_add_tail(&rxb->list, &rxq->rx_free);
1091                         rxq->free_count++;
1092                 } else
1093                         list_add_tail(&rxb->list, &rxq->rx_used);
1094
1095                 spin_unlock_irqrestore(&rxq->lock, flags);
1096
1097                 i = (i + 1) & RX_QUEUE_MASK;
1098                 /* If there are a lot of unused frames,
1099                  * restock the Rx queue so ucode wont assert. */
1100                 if (fill_rx) {
1101                         count++;
1102                         if (count >= 8) {
1103                                 rxq->read = i;
1104                                 iwlagn_rx_replenish_now(priv);
1105                                 count = 0;
1106                         }
1107                 }
1108         }
1109
1110         /* Backtrack one entry */
1111         rxq->read = i;
1112         if (fill_rx)
1113                 iwlagn_rx_replenish_now(priv);
1114         else
1115                 iwlagn_rx_queue_restock(priv);
1116 }
1117
1118 /* call this function to flush any scheduled tasklet */
1119 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1120 {
1121         /* wait to make sure we flush pending tasklet*/
1122         synchronize_irq(priv->pci_dev->irq);
1123         tasklet_kill(&priv->irq_tasklet);
1124 }
1125
1126 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1127 {
1128         u32 inta, handled = 0;
1129         u32 inta_fh;
1130         unsigned long flags;
1131         u32 i;
1132 #ifdef CONFIG_IWLWIFI_DEBUG
1133         u32 inta_mask;
1134 #endif
1135
1136         spin_lock_irqsave(&priv->lock, flags);
1137
1138         /* Ack/clear/reset pending uCode interrupts.
1139          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1140          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1141         inta = iwl_read32(priv, CSR_INT);
1142         iwl_write32(priv, CSR_INT, inta);
1143
1144         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1145          * Any new interrupts that happen after this, either while we're
1146          * in this tasklet, or later, will show up in next ISR/tasklet. */
1147         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1148         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1149
1150 #ifdef CONFIG_IWLWIFI_DEBUG
1151         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1152                 /* just for debug */
1153                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1154                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1155                               inta, inta_mask, inta_fh);
1156         }
1157 #endif
1158
1159         spin_unlock_irqrestore(&priv->lock, flags);
1160
1161         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1162          * atomic, make sure that inta covers all the interrupts that
1163          * we've discovered, even if FH interrupt came in just after
1164          * reading CSR_INT. */
1165         if (inta_fh & CSR49_FH_INT_RX_MASK)
1166                 inta |= CSR_INT_BIT_FH_RX;
1167         if (inta_fh & CSR49_FH_INT_TX_MASK)
1168                 inta |= CSR_INT_BIT_FH_TX;
1169
1170         /* Now service all interrupt bits discovered above. */
1171         if (inta & CSR_INT_BIT_HW_ERR) {
1172                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1173
1174                 /* Tell the device to stop sending interrupts */
1175                 iwl_disable_interrupts(priv);
1176
1177                 priv->isr_stats.hw++;
1178                 iwl_irq_handle_error(priv);
1179
1180                 handled |= CSR_INT_BIT_HW_ERR;
1181
1182                 return;
1183         }
1184
1185 #ifdef CONFIG_IWLWIFI_DEBUG
1186         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1187                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1188                 if (inta & CSR_INT_BIT_SCD) {
1189                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1190                                       "the frame/frames.\n");
1191                         priv->isr_stats.sch++;
1192                 }
1193
1194                 /* Alive notification via Rx interrupt will do the real work */
1195                 if (inta & CSR_INT_BIT_ALIVE) {
1196                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1197                         priv->isr_stats.alive++;
1198                 }
1199         }
1200 #endif
1201         /* Safely ignore these bits for debug checks below */
1202         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1203
1204         /* HW RF KILL switch toggled */
1205         if (inta & CSR_INT_BIT_RF_KILL) {
1206                 int hw_rf_kill = 0;
1207                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1208                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1209                         hw_rf_kill = 1;
1210
1211                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1212                                 hw_rf_kill ? "disable radio" : "enable radio");
1213
1214                 priv->isr_stats.rfkill++;
1215
1216                 /* driver only loads ucode once setting the interface up.
1217                  * the driver allows loading the ucode even if the radio
1218                  * is killed. Hence update the killswitch state here. The
1219                  * rfkill handler will care about restarting if needed.
1220                  */
1221                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1222                         if (hw_rf_kill)
1223                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1224                         else
1225                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1226                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1227                 }
1228
1229                 handled |= CSR_INT_BIT_RF_KILL;
1230         }
1231
1232         /* Chip got too hot and stopped itself */
1233         if (inta & CSR_INT_BIT_CT_KILL) {
1234                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1235                 priv->isr_stats.ctkill++;
1236                 handled |= CSR_INT_BIT_CT_KILL;
1237         }
1238
1239         /* Error detected by uCode */
1240         if (inta & CSR_INT_BIT_SW_ERR) {
1241                 IWL_ERR(priv, "Microcode SW error detected. "
1242                         " Restarting 0x%X.\n", inta);
1243                 priv->isr_stats.sw++;
1244                 priv->isr_stats.sw_err = inta;
1245                 iwl_irq_handle_error(priv);
1246                 handled |= CSR_INT_BIT_SW_ERR;
1247         }
1248
1249         /*
1250          * uCode wakes up after power-down sleep.
1251          * Tell device about any new tx or host commands enqueued,
1252          * and about any Rx buffers made available while asleep.
1253          */
1254         if (inta & CSR_INT_BIT_WAKEUP) {
1255                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1256                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1257                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1258                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1259                 priv->isr_stats.wakeup++;
1260                 handled |= CSR_INT_BIT_WAKEUP;
1261         }
1262
1263         /* All uCode command responses, including Tx command responses,
1264          * Rx "responses" (frame-received notification), and other
1265          * notifications from uCode come through here*/
1266         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1267                 iwl_rx_handle(priv);
1268                 priv->isr_stats.rx++;
1269                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1270         }
1271
1272         /* This "Tx" DMA channel is used only for loading uCode */
1273         if (inta & CSR_INT_BIT_FH_TX) {
1274                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1275                 priv->isr_stats.tx++;
1276                 handled |= CSR_INT_BIT_FH_TX;
1277                 /* Wake up uCode load routine, now that load is complete */
1278                 priv->ucode_write_complete = 1;
1279                 wake_up_interruptible(&priv->wait_command_queue);
1280         }
1281
1282         if (inta & ~handled) {
1283                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1284                 priv->isr_stats.unhandled++;
1285         }
1286
1287         if (inta & ~(priv->inta_mask)) {
1288                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1289                          inta & ~priv->inta_mask);
1290                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1291         }
1292
1293         /* Re-enable all interrupts */
1294         /* only Re-enable if diabled by irq */
1295         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1296                 iwl_enable_interrupts(priv);
1297
1298 #ifdef CONFIG_IWLWIFI_DEBUG
1299         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1300                 inta = iwl_read32(priv, CSR_INT);
1301                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1302                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1303                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1304                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1305         }
1306 #endif
1307 }
1308
1309 /* tasklet for iwlagn interrupt */
1310 static void iwl_irq_tasklet(struct iwl_priv *priv)
1311 {
1312         u32 inta = 0;
1313         u32 handled = 0;
1314         unsigned long flags;
1315         u32 i;
1316 #ifdef CONFIG_IWLWIFI_DEBUG
1317         u32 inta_mask;
1318 #endif
1319
1320         spin_lock_irqsave(&priv->lock, flags);
1321
1322         /* Ack/clear/reset pending uCode interrupts.
1323          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1324          */
1325         /* There is a hardware bug in the interrupt mask function that some
1326          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1327          * they are disabled in the CSR_INT_MASK register. Furthermore the
1328          * ICT interrupt handling mechanism has another bug that might cause
1329          * these unmasked interrupts fail to be detected. We workaround the
1330          * hardware bugs here by ACKing all the possible interrupts so that
1331          * interrupt coalescing can still be achieved.
1332          */
1333         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1334
1335         inta = priv->_agn.inta;
1336
1337 #ifdef CONFIG_IWLWIFI_DEBUG
1338         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1339                 /* just for debug */
1340                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1341                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1342                                 inta, inta_mask);
1343         }
1344 #endif
1345
1346         spin_unlock_irqrestore(&priv->lock, flags);
1347
1348         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1349         priv->_agn.inta = 0;
1350
1351         /* Now service all interrupt bits discovered above. */
1352         if (inta & CSR_INT_BIT_HW_ERR) {
1353                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1354
1355                 /* Tell the device to stop sending interrupts */
1356                 iwl_disable_interrupts(priv);
1357
1358                 priv->isr_stats.hw++;
1359                 iwl_irq_handle_error(priv);
1360
1361                 handled |= CSR_INT_BIT_HW_ERR;
1362
1363                 return;
1364         }
1365
1366 #ifdef CONFIG_IWLWIFI_DEBUG
1367         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1368                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1369                 if (inta & CSR_INT_BIT_SCD) {
1370                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1371                                       "the frame/frames.\n");
1372                         priv->isr_stats.sch++;
1373                 }
1374
1375                 /* Alive notification via Rx interrupt will do the real work */
1376                 if (inta & CSR_INT_BIT_ALIVE) {
1377                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1378                         priv->isr_stats.alive++;
1379                 }
1380         }
1381 #endif
1382         /* Safely ignore these bits for debug checks below */
1383         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1384
1385         /* HW RF KILL switch toggled */
1386         if (inta & CSR_INT_BIT_RF_KILL) {
1387                 int hw_rf_kill = 0;
1388                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1389                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1390                         hw_rf_kill = 1;
1391
1392                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1393                                 hw_rf_kill ? "disable radio" : "enable radio");
1394
1395                 priv->isr_stats.rfkill++;
1396
1397                 /* driver only loads ucode once setting the interface up.
1398                  * the driver allows loading the ucode even if the radio
1399                  * is killed. Hence update the killswitch state here. The
1400                  * rfkill handler will care about restarting if needed.
1401                  */
1402                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1403                         if (hw_rf_kill)
1404                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1405                         else
1406                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1407                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1408                 }
1409
1410                 handled |= CSR_INT_BIT_RF_KILL;
1411         }
1412
1413         /* Chip got too hot and stopped itself */
1414         if (inta & CSR_INT_BIT_CT_KILL) {
1415                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1416                 priv->isr_stats.ctkill++;
1417                 handled |= CSR_INT_BIT_CT_KILL;
1418         }
1419
1420         /* Error detected by uCode */
1421         if (inta & CSR_INT_BIT_SW_ERR) {
1422                 IWL_ERR(priv, "Microcode SW error detected. "
1423                         " Restarting 0x%X.\n", inta);
1424                 priv->isr_stats.sw++;
1425                 priv->isr_stats.sw_err = inta;
1426                 iwl_irq_handle_error(priv);
1427                 handled |= CSR_INT_BIT_SW_ERR;
1428         }
1429
1430         /* uCode wakes up after power-down sleep */
1431         if (inta & CSR_INT_BIT_WAKEUP) {
1432                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1433                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1434                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1435                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1436
1437                 priv->isr_stats.wakeup++;
1438
1439                 handled |= CSR_INT_BIT_WAKEUP;
1440         }
1441
1442         /* All uCode command responses, including Tx command responses,
1443          * Rx "responses" (frame-received notification), and other
1444          * notifications from uCode come through here*/
1445         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1446                         CSR_INT_BIT_RX_PERIODIC)) {
1447                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1448                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1449                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1450                         iwl_write32(priv, CSR_FH_INT_STATUS,
1451                                         CSR49_FH_INT_RX_MASK);
1452                 }
1453                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1454                         handled |= CSR_INT_BIT_RX_PERIODIC;
1455                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1456                 }
1457                 /* Sending RX interrupt require many steps to be done in the
1458                  * the device:
1459                  * 1- write interrupt to current index in ICT table.
1460                  * 2- dma RX frame.
1461                  * 3- update RX shared data to indicate last write index.
1462                  * 4- send interrupt.
1463                  * This could lead to RX race, driver could receive RX interrupt
1464                  * but the shared data changes does not reflect this;
1465                  * periodic interrupt will detect any dangling Rx activity.
1466                  */
1467
1468                 /* Disable periodic interrupt; we use it as just a one-shot. */
1469                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1470                             CSR_INT_PERIODIC_DIS);
1471                 iwl_rx_handle(priv);
1472
1473                 /*
1474                  * Enable periodic interrupt in 8 msec only if we received
1475                  * real RX interrupt (instead of just periodic int), to catch
1476                  * any dangling Rx interrupt.  If it was just the periodic
1477                  * interrupt, there was no dangling Rx activity, and no need
1478                  * to extend the periodic interrupt; one-shot is enough.
1479                  */
1480                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1481                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1482                                     CSR_INT_PERIODIC_ENA);
1483
1484                 priv->isr_stats.rx++;
1485         }
1486
1487         /* This "Tx" DMA channel is used only for loading uCode */
1488         if (inta & CSR_INT_BIT_FH_TX) {
1489                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1490                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1491                 priv->isr_stats.tx++;
1492                 handled |= CSR_INT_BIT_FH_TX;
1493                 /* Wake up uCode load routine, now that load is complete */
1494                 priv->ucode_write_complete = 1;
1495                 wake_up_interruptible(&priv->wait_command_queue);
1496         }
1497
1498         if (inta & ~handled) {
1499                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1500                 priv->isr_stats.unhandled++;
1501         }
1502
1503         if (inta & ~(priv->inta_mask)) {
1504                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1505                          inta & ~priv->inta_mask);
1506         }
1507
1508         /* Re-enable all interrupts */
1509         /* only Re-enable if diabled by irq */
1510         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1511                 iwl_enable_interrupts(priv);
1512 }
1513
1514 /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1515 #define ACK_CNT_RATIO (50)
1516 #define BA_TIMEOUT_CNT (5)
1517 #define BA_TIMEOUT_MAX (16)
1518
1519 /**
1520  * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1521  *
1522  * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1523  * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1524  * operation state.
1525  */
1526 bool iwl_good_ack_health(struct iwl_priv *priv,
1527                                 struct iwl_rx_packet *pkt)
1528 {
1529         bool rc = true;
1530         int actual_ack_cnt_delta, expected_ack_cnt_delta;
1531         int ba_timeout_delta;
1532
1533         actual_ack_cnt_delta =
1534                 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
1535                 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
1536         expected_ack_cnt_delta =
1537                 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
1538                 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
1539         ba_timeout_delta =
1540                 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
1541                 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
1542         if ((priv->_agn.agg_tids_count > 0) &&
1543             (expected_ack_cnt_delta > 0) &&
1544             (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1545                 < ACK_CNT_RATIO) &&
1546             (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1547                 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1548                                 " expected_ack_cnt = %d\n",
1549                                 actual_ack_cnt_delta, expected_ack_cnt_delta);
1550
1551 #ifdef CONFIG_IWLWIFI_DEBUGFS
1552                 /*
1553                  * This is ifdef'ed on DEBUGFS because otherwise the
1554                  * statistics aren't available. If DEBUGFS is set but
1555                  * DEBUG is not, these will just compile out.
1556                  */
1557                 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
1558                                 priv->_agn.delta_statistics.tx.rx_detected_cnt);
1559                 IWL_DEBUG_RADIO(priv,
1560                                 "ack_or_ba_timeout_collision delta = %d\n",
1561                                 priv->_agn.delta_statistics.tx.
1562                                 ack_or_ba_timeout_collision);
1563 #endif
1564                 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1565                                 ba_timeout_delta);
1566                 if (!actual_ack_cnt_delta &&
1567                     (ba_timeout_delta >= BA_TIMEOUT_MAX))
1568                         rc = false;
1569         }
1570         return rc;
1571 }
1572
1573
1574 /*****************************************************************************
1575  *
1576  * sysfs attributes
1577  *
1578  *****************************************************************************/
1579
1580 #ifdef CONFIG_IWLWIFI_DEBUG
1581
1582 /*
1583  * The following adds a new attribute to the sysfs representation
1584  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1585  * used for controlling the debug level.
1586  *
1587  * See the level definitions in iwl for details.
1588  *
1589  * The debug_level being managed using sysfs below is a per device debug
1590  * level that is used instead of the global debug level if it (the per
1591  * device debug level) is set.
1592  */
1593 static ssize_t show_debug_level(struct device *d,
1594                                 struct device_attribute *attr, char *buf)
1595 {
1596         struct iwl_priv *priv = dev_get_drvdata(d);
1597         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1598 }
1599 static ssize_t store_debug_level(struct device *d,
1600                                 struct device_attribute *attr,
1601                                  const char *buf, size_t count)
1602 {
1603         struct iwl_priv *priv = dev_get_drvdata(d);
1604         unsigned long val;
1605         int ret;
1606
1607         ret = strict_strtoul(buf, 0, &val);
1608         if (ret)
1609                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1610         else {
1611                 priv->debug_level = val;
1612                 if (iwl_alloc_traffic_mem(priv))
1613                         IWL_ERR(priv,
1614                                 "Not enough memory to generate traffic log\n");
1615         }
1616         return strnlen(buf, count);
1617 }
1618
1619 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1620                         show_debug_level, store_debug_level);
1621
1622
1623 #endif /* CONFIG_IWLWIFI_DEBUG */
1624
1625
1626 static ssize_t show_temperature(struct device *d,
1627                                 struct device_attribute *attr, char *buf)
1628 {
1629         struct iwl_priv *priv = dev_get_drvdata(d);
1630
1631         if (!iwl_is_alive(priv))
1632                 return -EAGAIN;
1633
1634         return sprintf(buf, "%d\n", priv->temperature);
1635 }
1636
1637 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1638
1639 static ssize_t show_tx_power(struct device *d,
1640                              struct device_attribute *attr, char *buf)
1641 {
1642         struct iwl_priv *priv = dev_get_drvdata(d);
1643
1644         if (!iwl_is_ready_rf(priv))
1645                 return sprintf(buf, "off\n");
1646         else
1647                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1648 }
1649
1650 static ssize_t store_tx_power(struct device *d,
1651                               struct device_attribute *attr,
1652                               const char *buf, size_t count)
1653 {
1654         struct iwl_priv *priv = dev_get_drvdata(d);
1655         unsigned long val;
1656         int ret;
1657
1658         ret = strict_strtoul(buf, 10, &val);
1659         if (ret)
1660                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1661         else {
1662                 ret = iwl_set_tx_power(priv, val, false);
1663                 if (ret)
1664                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1665                                 ret);
1666                 else
1667                         ret = count;
1668         }
1669         return ret;
1670 }
1671
1672 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1673
1674 static struct attribute *iwl_sysfs_entries[] = {
1675         &dev_attr_temperature.attr,
1676         &dev_attr_tx_power.attr,
1677 #ifdef CONFIG_IWLWIFI_DEBUG
1678         &dev_attr_debug_level.attr,
1679 #endif
1680         NULL
1681 };
1682
1683 static struct attribute_group iwl_attribute_group = {
1684         .name = NULL,           /* put in device directory */
1685         .attrs = iwl_sysfs_entries,
1686 };
1687
1688 /******************************************************************************
1689  *
1690  * uCode download functions
1691  *
1692  ******************************************************************************/
1693
1694 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1695 {
1696         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1697         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1698         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1699         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1700         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1701         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1702 }
1703
1704 static void iwl_nic_start(struct iwl_priv *priv)
1705 {
1706         /* Remove all resets to allow NIC to operate */
1707         iwl_write32(priv, CSR_RESET, 0);
1708 }
1709
1710 struct iwlagn_ucode_capabilities {
1711         u32 max_probe_length;
1712         u32 standard_phy_calibration_size;
1713 };
1714
1715 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1716 static int iwl_mac_setup_register(struct iwl_priv *priv,
1717                                   struct iwlagn_ucode_capabilities *capa);
1718
1719 #define UCODE_EXPERIMENTAL_INDEX        100
1720 #define UCODE_EXPERIMENTAL_TAG          "exp"
1721
1722 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1723 {
1724         const char *name_pre = priv->cfg->fw_name_pre;
1725         char tag[8];
1726
1727         if (first) {
1728 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1729                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1730                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1731         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1732 #endif
1733                 priv->fw_index = priv->cfg->ucode_api_max;
1734                 sprintf(tag, "%d", priv->fw_index);
1735         } else {
1736                 priv->fw_index--;
1737                 sprintf(tag, "%d", priv->fw_index);
1738         }
1739
1740         if (priv->fw_index < priv->cfg->ucode_api_min) {
1741                 IWL_ERR(priv, "no suitable firmware found!\n");
1742                 return -ENOENT;
1743         }
1744
1745         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1746
1747         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1748                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1749                                 ? "EXPERIMENTAL " : "",
1750                        priv->firmware_name);
1751
1752         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1753                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1754                                        iwl_ucode_callback);
1755 }
1756
1757 struct iwlagn_firmware_pieces {
1758         const void *inst, *data, *init, *init_data, *boot;
1759         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1760
1761         u32 build;
1762
1763         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1764         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1765 };
1766
1767 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1768                                        const struct firmware *ucode_raw,
1769                                        struct iwlagn_firmware_pieces *pieces)
1770 {
1771         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1772         u32 api_ver, hdr_size;
1773         const u8 *src;
1774
1775         priv->ucode_ver = le32_to_cpu(ucode->ver);
1776         api_ver = IWL_UCODE_API(priv->ucode_ver);
1777
1778         switch (api_ver) {
1779         default:
1780                 /*
1781                  * 4965 doesn't revision the firmware file format
1782                  * along with the API version, it always uses v1
1783                  * file format.
1784                  */
1785                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1786                                 CSR_HW_REV_TYPE_4965) {
1787                         hdr_size = 28;
1788                         if (ucode_raw->size < hdr_size) {
1789                                 IWL_ERR(priv, "File size too small!\n");
1790                                 return -EINVAL;
1791                         }
1792                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1793                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1794                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1795                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1796                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1797                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1798                         src = ucode->u.v2.data;
1799                         break;
1800                 }
1801                 /* fall through for 4965 */
1802         case 0:
1803         case 1:
1804         case 2:
1805                 hdr_size = 24;
1806                 if (ucode_raw->size < hdr_size) {
1807                         IWL_ERR(priv, "File size too small!\n");
1808                         return -EINVAL;
1809                 }
1810                 pieces->build = 0;
1811                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1812                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1813                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1814                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1815                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1816                 src = ucode->u.v1.data;
1817                 break;
1818         }
1819
1820         /* Verify size of file vs. image size info in file's header */
1821         if (ucode_raw->size != hdr_size + pieces->inst_size +
1822                                 pieces->data_size + pieces->init_size +
1823                                 pieces->init_data_size + pieces->boot_size) {
1824
1825                 IWL_ERR(priv,
1826                         "uCode file size %d does not match expected size\n",
1827                         (int)ucode_raw->size);
1828                 return -EINVAL;
1829         }
1830
1831         pieces->inst = src;
1832         src += pieces->inst_size;
1833         pieces->data = src;
1834         src += pieces->data_size;
1835         pieces->init = src;
1836         src += pieces->init_size;
1837         pieces->init_data = src;
1838         src += pieces->init_data_size;
1839         pieces->boot = src;
1840         src += pieces->boot_size;
1841
1842         return 0;
1843 }
1844
1845 static int iwlagn_wanted_ucode_alternative = 1;
1846
1847 static int iwlagn_load_firmware(struct iwl_priv *priv,
1848                                 const struct firmware *ucode_raw,
1849                                 struct iwlagn_firmware_pieces *pieces,
1850                                 struct iwlagn_ucode_capabilities *capa)
1851 {
1852         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1853         struct iwl_ucode_tlv *tlv;
1854         size_t len = ucode_raw->size;
1855         const u8 *data;
1856         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1857         u64 alternatives;
1858         u32 tlv_len;
1859         enum iwl_ucode_tlv_type tlv_type;
1860         const u8 *tlv_data;
1861
1862         if (len < sizeof(*ucode)) {
1863                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1864                 return -EINVAL;
1865         }
1866
1867         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1868                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1869                         le32_to_cpu(ucode->magic));
1870                 return -EINVAL;
1871         }
1872
1873         /*
1874          * Check which alternatives are present, and "downgrade"
1875          * when the chosen alternative is not present, warning
1876          * the user when that happens. Some files may not have
1877          * any alternatives, so don't warn in that case.
1878          */
1879         alternatives = le64_to_cpu(ucode->alternatives);
1880         tmp = wanted_alternative;
1881         if (wanted_alternative > 63)
1882                 wanted_alternative = 63;
1883         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1884                 wanted_alternative--;
1885         if (wanted_alternative && wanted_alternative != tmp)
1886                 IWL_WARN(priv,
1887                          "uCode alternative %d not available, choosing %d\n",
1888                          tmp, wanted_alternative);
1889
1890         priv->ucode_ver = le32_to_cpu(ucode->ver);
1891         pieces->build = le32_to_cpu(ucode->build);
1892         data = ucode->data;
1893
1894         len -= sizeof(*ucode);
1895
1896         while (len >= sizeof(*tlv)) {
1897                 u16 tlv_alt;
1898
1899                 len -= sizeof(*tlv);
1900                 tlv = (void *)data;
1901
1902                 tlv_len = le32_to_cpu(tlv->length);
1903                 tlv_type = le16_to_cpu(tlv->type);
1904                 tlv_alt = le16_to_cpu(tlv->alternative);
1905                 tlv_data = tlv->data;
1906
1907                 if (len < tlv_len) {
1908                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1909                                 len, tlv_len);
1910                         return -EINVAL;
1911                 }
1912                 len -= ALIGN(tlv_len, 4);
1913                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1914
1915                 /*
1916                  * Alternative 0 is always valid.
1917                  *
1918                  * Skip alternative TLVs that are not selected.
1919                  */
1920                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1921                         continue;
1922
1923                 switch (tlv_type) {
1924                 case IWL_UCODE_TLV_INST:
1925                         pieces->inst = tlv_data;
1926                         pieces->inst_size = tlv_len;
1927                         break;
1928                 case IWL_UCODE_TLV_DATA:
1929                         pieces->data = tlv_data;
1930                         pieces->data_size = tlv_len;
1931                         break;
1932                 case IWL_UCODE_TLV_INIT:
1933                         pieces->init = tlv_data;
1934                         pieces->init_size = tlv_len;
1935                         break;
1936                 case IWL_UCODE_TLV_INIT_DATA:
1937                         pieces->init_data = tlv_data;
1938                         pieces->init_data_size = tlv_len;
1939                         break;
1940                 case IWL_UCODE_TLV_BOOT:
1941                         pieces->boot = tlv_data;
1942                         pieces->boot_size = tlv_len;
1943                         break;
1944                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1945                         if (tlv_len != sizeof(u32))
1946                                 goto invalid_tlv_len;
1947                         capa->max_probe_length =
1948                                         le32_to_cpup((__le32 *)tlv_data);
1949                         break;
1950                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1951                         if (tlv_len != sizeof(u32))
1952                                 goto invalid_tlv_len;
1953                         pieces->init_evtlog_ptr =
1954                                         le32_to_cpup((__le32 *)tlv_data);
1955                         break;
1956                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1957                         if (tlv_len != sizeof(u32))
1958                                 goto invalid_tlv_len;
1959                         pieces->init_evtlog_size =
1960                                         le32_to_cpup((__le32 *)tlv_data);
1961                         break;
1962                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1963                         if (tlv_len != sizeof(u32))
1964                                 goto invalid_tlv_len;
1965                         pieces->init_errlog_ptr =
1966                                         le32_to_cpup((__le32 *)tlv_data);
1967                         break;
1968                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1969                         if (tlv_len != sizeof(u32))
1970                                 goto invalid_tlv_len;
1971                         pieces->inst_evtlog_ptr =
1972                                         le32_to_cpup((__le32 *)tlv_data);
1973                         break;
1974                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1975                         if (tlv_len != sizeof(u32))
1976                                 goto invalid_tlv_len;
1977                         pieces->inst_evtlog_size =
1978                                         le32_to_cpup((__le32 *)tlv_data);
1979                         break;
1980                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1981                         if (tlv_len != sizeof(u32))
1982                                 goto invalid_tlv_len;
1983                         pieces->inst_errlog_ptr =
1984                                         le32_to_cpup((__le32 *)tlv_data);
1985                         break;
1986                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1987                         if (tlv_len)
1988                                 goto invalid_tlv_len;
1989                         priv->enhance_sensitivity_table = true;
1990                         break;
1991                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1992                         if (tlv_len != sizeof(u32))
1993                                 goto invalid_tlv_len;
1994                         capa->standard_phy_calibration_size =
1995                                         le32_to_cpup((__le32 *)tlv_data);
1996                         break;
1997                 default:
1998                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1999                         break;
2000                 }
2001         }
2002
2003         if (len) {
2004                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2005                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
2006                 return -EINVAL;
2007         }
2008
2009         return 0;
2010
2011  invalid_tlv_len:
2012         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2013         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2014
2015         return -EINVAL;
2016 }
2017
2018 /**
2019  * iwl_ucode_callback - callback when firmware was loaded
2020  *
2021  * If loaded successfully, copies the firmware into buffers
2022  * for the card to fetch (via DMA).
2023  */
2024 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
2025 {
2026         struct iwl_priv *priv = context;
2027         struct iwl_ucode_header *ucode;
2028         int err;
2029         struct iwlagn_firmware_pieces pieces;
2030         const unsigned int api_max = priv->cfg->ucode_api_max;
2031         const unsigned int api_min = priv->cfg->ucode_api_min;
2032         u32 api_ver;
2033         char buildstr[25];
2034         u32 build;
2035         struct iwlagn_ucode_capabilities ucode_capa = {
2036                 .max_probe_length = 200,
2037                 .standard_phy_calibration_size =
2038                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
2039         };
2040
2041         memset(&pieces, 0, sizeof(pieces));
2042
2043         if (!ucode_raw) {
2044                 if (priv->fw_index <= priv->cfg->ucode_api_max)
2045                         IWL_ERR(priv,
2046                                 "request for firmware file '%s' failed.\n",
2047                                 priv->firmware_name);
2048                 goto try_again;
2049         }
2050
2051         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2052                        priv->firmware_name, ucode_raw->size);
2053
2054         /* Make sure that we got at least the API version number */
2055         if (ucode_raw->size < 4) {
2056                 IWL_ERR(priv, "File size way too small!\n");
2057                 goto try_again;
2058         }
2059
2060         /* Data from ucode file:  header followed by uCode images */
2061         ucode = (struct iwl_ucode_header *)ucode_raw->data;
2062
2063         if (ucode->ver)
2064                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2065         else
2066                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2067                                            &ucode_capa);
2068
2069         if (err)
2070                 goto try_again;
2071
2072         api_ver = IWL_UCODE_API(priv->ucode_ver);
2073         build = pieces.build;
2074
2075         /*
2076          * api_ver should match the api version forming part of the
2077          * firmware filename ... but we don't check for that and only rely
2078          * on the API version read from firmware header from here on forward
2079          */
2080         if (api_ver < api_min || api_ver > api_max) {
2081                 IWL_ERR(priv, "Driver unable to support your firmware API. "
2082                           "Driver supports v%u, firmware is v%u.\n",
2083                           api_max, api_ver);
2084                 goto try_again;
2085         }
2086
2087         if (api_ver != api_max)
2088                 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
2089                           "got v%u. New firmware can be obtained "
2090                           "from http://www.intellinuxwireless.org.\n",
2091                           api_max, api_ver);
2092
2093         if (build)
2094                 sprintf(buildstr, " build %u%s", build,
2095                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2096                                 ? " (EXP)" : "");
2097         else
2098                 buildstr[0] = '\0';
2099
2100         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2101                  IWL_UCODE_MAJOR(priv->ucode_ver),
2102                  IWL_UCODE_MINOR(priv->ucode_ver),
2103                  IWL_UCODE_API(priv->ucode_ver),
2104                  IWL_UCODE_SERIAL(priv->ucode_ver),
2105                  buildstr);
2106
2107         snprintf(priv->hw->wiphy->fw_version,
2108                  sizeof(priv->hw->wiphy->fw_version),
2109                  "%u.%u.%u.%u%s",
2110                  IWL_UCODE_MAJOR(priv->ucode_ver),
2111                  IWL_UCODE_MINOR(priv->ucode_ver),
2112                  IWL_UCODE_API(priv->ucode_ver),
2113                  IWL_UCODE_SERIAL(priv->ucode_ver),
2114                  buildstr);
2115
2116         /*
2117          * For any of the failures below (before allocating pci memory)
2118          * we will try to load a version with a smaller API -- maybe the
2119          * user just got a corrupted version of the latest API.
2120          */
2121
2122         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2123                        priv->ucode_ver);
2124         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2125                        pieces.inst_size);
2126         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2127                        pieces.data_size);
2128         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2129                        pieces.init_size);
2130         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2131                        pieces.init_data_size);
2132         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2133                        pieces.boot_size);
2134
2135         /* Verify that uCode images will fit in card's SRAM */
2136         if (pieces.inst_size > priv->hw_params.max_inst_size) {
2137                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2138                         pieces.inst_size);
2139                 goto try_again;
2140         }
2141
2142         if (pieces.data_size > priv->hw_params.max_data_size) {
2143                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2144                         pieces.data_size);
2145                 goto try_again;
2146         }
2147
2148         if (pieces.init_size > priv->hw_params.max_inst_size) {
2149                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2150                         pieces.init_size);
2151                 goto try_again;
2152         }
2153
2154         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2155                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2156                         pieces.init_data_size);
2157                 goto try_again;
2158         }
2159
2160         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2161                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2162                         pieces.boot_size);
2163                 goto try_again;
2164         }
2165
2166         /* Allocate ucode buffers for card's bus-master loading ... */
2167
2168         /* Runtime instructions and 2 copies of data:
2169          * 1) unmodified from disk
2170          * 2) backup cache for save/restore during power-downs */
2171         priv->ucode_code.len = pieces.inst_size;
2172         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2173
2174         priv->ucode_data.len = pieces.data_size;
2175         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2176
2177         priv->ucode_data_backup.len = pieces.data_size;
2178         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2179
2180         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2181             !priv->ucode_data_backup.v_addr)
2182                 goto err_pci_alloc;
2183
2184         /* Initialization instructions and data */
2185         if (pieces.init_size && pieces.init_data_size) {
2186                 priv->ucode_init.len = pieces.init_size;
2187                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2188
2189                 priv->ucode_init_data.len = pieces.init_data_size;
2190                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2191
2192                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2193                         goto err_pci_alloc;
2194         }
2195
2196         /* Bootstrap (instructions only, no data) */
2197         if (pieces.boot_size) {
2198                 priv->ucode_boot.len = pieces.boot_size;
2199                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2200
2201                 if (!priv->ucode_boot.v_addr)
2202                         goto err_pci_alloc;
2203         }
2204
2205         /* Now that we can no longer fail, copy information */
2206
2207         /*
2208          * The (size - 16) / 12 formula is based on the information recorded
2209          * for each event, which is of mode 1 (including timestamp) for all
2210          * new microcodes that include this information.
2211          */
2212         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2213         if (pieces.init_evtlog_size)
2214                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2215         else
2216                 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2217         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2218         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2219         if (pieces.inst_evtlog_size)
2220                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2221         else
2222                 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2223         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2224
2225         if (priv->valid_contexts == BIT(IWL_RXON_CTX_BSS))
2226                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2227         else
2228                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2229
2230         /* Copy images into buffers for card's bus-master reads ... */
2231
2232         /* Runtime instructions (first block of data in file) */
2233         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2234                         pieces.inst_size);
2235         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2236
2237         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2238                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2239
2240         /*
2241          * Runtime data
2242          * NOTE:  Copy into backup buffer will be done in iwl_up()
2243          */
2244         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2245                         pieces.data_size);
2246         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2247         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2248
2249         /* Initialization instructions */
2250         if (pieces.init_size) {
2251                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2252                                 pieces.init_size);
2253                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2254         }
2255
2256         /* Initialization data */
2257         if (pieces.init_data_size) {
2258                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2259                                pieces.init_data_size);
2260                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2261                        pieces.init_data_size);
2262         }
2263
2264         /* Bootstrap instructions */
2265         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2266                         pieces.boot_size);
2267         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2268
2269         /*
2270          * figure out the offset of chain noise reset and gain commands
2271          * base on the size of standard phy calibration commands table size
2272          */
2273         if (ucode_capa.standard_phy_calibration_size >
2274             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2275                 ucode_capa.standard_phy_calibration_size =
2276                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2277
2278         priv->_agn.phy_calib_chain_noise_reset_cmd =
2279                 ucode_capa.standard_phy_calibration_size;
2280         priv->_agn.phy_calib_chain_noise_gain_cmd =
2281                 ucode_capa.standard_phy_calibration_size + 1;
2282
2283         /**************************************************
2284          * This is still part of probe() in a sense...
2285          *
2286          * 9. Setup and register with mac80211 and debugfs
2287          **************************************************/
2288         err = iwl_mac_setup_register(priv, &ucode_capa);
2289         if (err)
2290                 goto out_unbind;
2291
2292         err = iwl_dbgfs_register(priv, DRV_NAME);
2293         if (err)
2294                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2295
2296         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2297                                         &iwl_attribute_group);
2298         if (err) {
2299                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2300                 goto out_unbind;
2301         }
2302
2303         /* We have our copies now, allow OS release its copies */
2304         release_firmware(ucode_raw);
2305         complete(&priv->_agn.firmware_loading_complete);
2306         return;
2307
2308  try_again:
2309         /* try next, if any */
2310         if (iwl_request_firmware(priv, false))
2311                 goto out_unbind;
2312         release_firmware(ucode_raw);
2313         return;
2314
2315  err_pci_alloc:
2316         IWL_ERR(priv, "failed to allocate pci memory\n");
2317         iwl_dealloc_ucode_pci(priv);
2318  out_unbind:
2319         complete(&priv->_agn.firmware_loading_complete);
2320         device_release_driver(&priv->pci_dev->dev);
2321         release_firmware(ucode_raw);
2322 }
2323
2324 static const char *desc_lookup_text[] = {
2325         "OK",
2326         "FAIL",
2327         "BAD_PARAM",
2328         "BAD_CHECKSUM",
2329         "NMI_INTERRUPT_WDG",
2330         "SYSASSERT",
2331         "FATAL_ERROR",
2332         "BAD_COMMAND",
2333         "HW_ERROR_TUNE_LOCK",
2334         "HW_ERROR_TEMPERATURE",
2335         "ILLEGAL_CHAN_FREQ",
2336         "VCC_NOT_STABLE",
2337         "FH_ERROR",
2338         "NMI_INTERRUPT_HOST",
2339         "NMI_INTERRUPT_ACTION_PT",
2340         "NMI_INTERRUPT_UNKNOWN",
2341         "UCODE_VERSION_MISMATCH",
2342         "HW_ERROR_ABS_LOCK",
2343         "HW_ERROR_CAL_LOCK_FAIL",
2344         "NMI_INTERRUPT_INST_ACTION_PT",
2345         "NMI_INTERRUPT_DATA_ACTION_PT",
2346         "NMI_TRM_HW_ER",
2347         "NMI_INTERRUPT_TRM",
2348         "NMI_INTERRUPT_BREAK_POINT"
2349         "DEBUG_0",
2350         "DEBUG_1",
2351         "DEBUG_2",
2352         "DEBUG_3",
2353 };
2354
2355 static struct { char *name; u8 num; } advanced_lookup[] = {
2356         { "NMI_INTERRUPT_WDG", 0x34 },
2357         { "SYSASSERT", 0x35 },
2358         { "UCODE_VERSION_MISMATCH", 0x37 },
2359         { "BAD_COMMAND", 0x38 },
2360         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2361         { "FATAL_ERROR", 0x3D },
2362         { "NMI_TRM_HW_ERR", 0x46 },
2363         { "NMI_INTERRUPT_TRM", 0x4C },
2364         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2365         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2366         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2367         { "NMI_INTERRUPT_HOST", 0x66 },
2368         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2369         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2370         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2371         { "ADVANCED_SYSASSERT", 0 },
2372 };
2373
2374 static const char *desc_lookup(u32 num)
2375 {
2376         int i;
2377         int max = ARRAY_SIZE(desc_lookup_text);
2378
2379         if (num < max)
2380                 return desc_lookup_text[num];
2381
2382         max = ARRAY_SIZE(advanced_lookup) - 1;
2383         for (i = 0; i < max; i++) {
2384                 if (advanced_lookup[i].num == num)
2385                         break;;
2386         }
2387         return advanced_lookup[i].name;
2388 }
2389
2390 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2391 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2392
2393 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2394 {
2395         u32 data2, line;
2396         u32 desc, time, count, base, data1;
2397         u32 blink1, blink2, ilink1, ilink2;
2398         u32 pc, hcmd;
2399
2400         if (priv->ucode_type == UCODE_INIT) {
2401                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2402                 if (!base)
2403                         base = priv->_agn.init_errlog_ptr;
2404         } else {
2405                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2406                 if (!base)
2407                         base = priv->_agn.inst_errlog_ptr;
2408         }
2409
2410         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2411                 IWL_ERR(priv,
2412                         "Not valid error log pointer 0x%08X for %s uCode\n",
2413                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2414                 return;
2415         }
2416
2417         count = iwl_read_targ_mem(priv, base);
2418
2419         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2420                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2421                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2422                         priv->status, count);
2423         }
2424
2425         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2426         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2427         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2428         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2429         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2430         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2431         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2432         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2433         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2434         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2435         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2436
2437         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2438                                       blink1, blink2, ilink1, ilink2);
2439
2440         IWL_ERR(priv, "Desc                                  Time       "
2441                 "data1      data2      line\n");
2442         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2443                 desc_lookup(desc), desc, time, data1, data2, line);
2444         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2445         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2446                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2447 }
2448
2449 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2450
2451 /**
2452  * iwl_print_event_log - Dump error event log to syslog
2453  *
2454  */
2455 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2456                                u32 num_events, u32 mode,
2457                                int pos, char **buf, size_t bufsz)
2458 {
2459         u32 i;
2460         u32 base;       /* SRAM byte address of event log header */
2461         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2462         u32 ptr;        /* SRAM byte address of log data */
2463         u32 ev, time, data; /* event log data */
2464         unsigned long reg_flags;
2465
2466         if (num_events == 0)
2467                 return pos;
2468
2469         if (priv->ucode_type == UCODE_INIT) {
2470                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2471                 if (!base)
2472                         base = priv->_agn.init_evtlog_ptr;
2473         } else {
2474                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2475                 if (!base)
2476                         base = priv->_agn.inst_evtlog_ptr;
2477         }
2478
2479         if (mode == 0)
2480                 event_size = 2 * sizeof(u32);
2481         else
2482                 event_size = 3 * sizeof(u32);
2483
2484         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2485
2486         /* Make sure device is powered up for SRAM reads */
2487         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2488         iwl_grab_nic_access(priv);
2489
2490         /* Set starting address; reads will auto-increment */
2491         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2492         rmb();
2493
2494         /* "time" is actually "data" for mode 0 (no timestamp).
2495         * place event id # at far right for easier visual parsing. */
2496         for (i = 0; i < num_events; i++) {
2497                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2498                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2499                 if (mode == 0) {
2500                         /* data, ev */
2501                         if (bufsz) {
2502                                 pos += scnprintf(*buf + pos, bufsz - pos,
2503                                                 "EVT_LOG:0x%08x:%04u\n",
2504                                                 time, ev);
2505                         } else {
2506                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2507                                         time, ev);
2508                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2509                                         time, ev);
2510                         }
2511                 } else {
2512                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2513                         if (bufsz) {
2514                                 pos += scnprintf(*buf + pos, bufsz - pos,
2515                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2516                                                  time, data, ev);
2517                         } else {
2518                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2519                                         time, data, ev);
2520                                 trace_iwlwifi_dev_ucode_event(priv, time,
2521                                         data, ev);
2522                         }
2523                 }
2524         }
2525
2526         /* Allow device to power down */
2527         iwl_release_nic_access(priv);
2528         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2529         return pos;
2530 }
2531
2532 /**
2533  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2534  */
2535 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2536                                     u32 num_wraps, u32 next_entry,
2537                                     u32 size, u32 mode,
2538                                     int pos, char **buf, size_t bufsz)
2539 {
2540         /*
2541          * display the newest DEFAULT_LOG_ENTRIES entries
2542          * i.e the entries just before the next ont that uCode would fill.
2543          */
2544         if (num_wraps) {
2545                 if (next_entry < size) {
2546                         pos = iwl_print_event_log(priv,
2547                                                 capacity - (size - next_entry),
2548                                                 size - next_entry, mode,
2549                                                 pos, buf, bufsz);
2550                         pos = iwl_print_event_log(priv, 0,
2551                                                   next_entry, mode,
2552                                                   pos, buf, bufsz);
2553                 } else
2554                         pos = iwl_print_event_log(priv, next_entry - size,
2555                                                   size, mode, pos, buf, bufsz);
2556         } else {
2557                 if (next_entry < size) {
2558                         pos = iwl_print_event_log(priv, 0, next_entry,
2559                                                   mode, pos, buf, bufsz);
2560                 } else {
2561                         pos = iwl_print_event_log(priv, next_entry - size,
2562                                                   size, mode, pos, buf, bufsz);
2563                 }
2564         }
2565         return pos;
2566 }
2567
2568 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2569
2570 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2571                             char **buf, bool display)
2572 {
2573         u32 base;       /* SRAM byte address of event log header */
2574         u32 capacity;   /* event log capacity in # entries */
2575         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2576         u32 num_wraps;  /* # times uCode wrapped to top of log */
2577         u32 next_entry; /* index of next entry to be written by uCode */
2578         u32 size;       /* # entries that we'll print */
2579         u32 logsize;
2580         int pos = 0;
2581         size_t bufsz = 0;
2582
2583         if (priv->ucode_type == UCODE_INIT) {
2584                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2585                 logsize = priv->_agn.init_evtlog_size;
2586                 if (!base)
2587                         base = priv->_agn.init_evtlog_ptr;
2588         } else {
2589                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2590                 logsize = priv->_agn.inst_evtlog_size;
2591                 if (!base)
2592                         base = priv->_agn.inst_evtlog_ptr;
2593         }
2594
2595         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2596                 IWL_ERR(priv,
2597                         "Invalid event log pointer 0x%08X for %s uCode\n",
2598                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2599                 return -EINVAL;
2600         }
2601
2602         /* event log header */
2603         capacity = iwl_read_targ_mem(priv, base);
2604         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2605         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2606         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2607
2608         if (capacity > logsize) {
2609                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2610                         capacity, logsize);
2611                 capacity = logsize;
2612         }
2613
2614         if (next_entry > logsize) {
2615                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2616                         next_entry, logsize);
2617                 next_entry = logsize;
2618         }
2619
2620         size = num_wraps ? capacity : next_entry;
2621
2622         /* bail out if nothing in log */
2623         if (size == 0) {
2624                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2625                 return pos;
2626         }
2627
2628         /* enable/disable bt channel announcement */
2629         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2630
2631 #ifdef CONFIG_IWLWIFI_DEBUG
2632         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2633                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2634                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2635 #else
2636         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2637                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2638 #endif
2639         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2640                 size);
2641
2642 #ifdef CONFIG_IWLWIFI_DEBUG
2643         if (display) {
2644                 if (full_log)
2645                         bufsz = capacity * 48;
2646                 else
2647                         bufsz = size * 48;
2648                 *buf = kmalloc(bufsz, GFP_KERNEL);
2649                 if (!*buf)
2650                         return -ENOMEM;
2651         }
2652         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2653                 /*
2654                  * if uCode has wrapped back to top of log,
2655                  * start at the oldest entry,
2656                  * i.e the next one that uCode would fill.
2657                  */
2658                 if (num_wraps)
2659                         pos = iwl_print_event_log(priv, next_entry,
2660                                                 capacity - next_entry, mode,
2661                                                 pos, buf, bufsz);
2662                 /* (then/else) start at top of log */
2663                 pos = iwl_print_event_log(priv, 0,
2664                                           next_entry, mode, pos, buf, bufsz);
2665         } else
2666                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2667                                                 next_entry, size, mode,
2668                                                 pos, buf, bufsz);
2669 #else
2670         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2671                                         next_entry, size, mode,
2672                                         pos, buf, bufsz);
2673 #endif
2674         return pos;
2675 }
2676
2677 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2678 {
2679         struct iwl_ct_kill_config cmd;
2680         struct iwl_ct_kill_throttling_config adv_cmd;
2681         unsigned long flags;
2682         int ret = 0;
2683
2684         spin_lock_irqsave(&priv->lock, flags);
2685         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2686                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2687         spin_unlock_irqrestore(&priv->lock, flags);
2688         priv->thermal_throttle.ct_kill_toggle = false;
2689
2690         if (priv->cfg->support_ct_kill_exit) {
2691                 adv_cmd.critical_temperature_enter =
2692                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2693                 adv_cmd.critical_temperature_exit =
2694                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2695
2696                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2697                                        sizeof(adv_cmd), &adv_cmd);
2698                 if (ret)
2699                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2700                 else
2701                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2702                                         "succeeded, "
2703                                         "critical temperature enter is %d,"
2704                                         "exit is %d\n",
2705                                        priv->hw_params.ct_kill_threshold,
2706                                        priv->hw_params.ct_kill_exit_threshold);
2707         } else {
2708                 cmd.critical_temperature_R =
2709                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2710
2711                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2712                                        sizeof(cmd), &cmd);
2713                 if (ret)
2714                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2715                 else
2716                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2717                                         "succeeded, "
2718                                         "critical temperature is %d\n",
2719                                         priv->hw_params.ct_kill_threshold);
2720         }
2721 }
2722
2723 /**
2724  * iwl_alive_start - called after REPLY_ALIVE notification received
2725  *                   from protocol/runtime uCode (initialization uCode's
2726  *                   Alive gets handled by iwl_init_alive_start()).
2727  */
2728 static void iwl_alive_start(struct iwl_priv *priv)
2729 {
2730         int ret = 0;
2731         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2732
2733         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2734
2735         if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2736                 /* We had an error bringing up the hardware, so take it
2737                  * all the way back down so we can try again */
2738                 IWL_DEBUG_INFO(priv, "Alive failed.\n");
2739                 goto restart;
2740         }
2741
2742         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2743          * This is a paranoid check, because we would not have gotten the
2744          * "runtime" alive if code weren't properly loaded.  */
2745         if (iwl_verify_ucode(priv)) {
2746                 /* Runtime instruction load was bad;
2747                  * take it all the way back down so we can try again */
2748                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2749                 goto restart;
2750         }
2751
2752         ret = priv->cfg->ops->lib->alive_notify(priv);
2753         if (ret) {
2754                 IWL_WARN(priv,
2755                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2756                 goto restart;
2757         }
2758
2759         /* After the ALIVE response, we can send host commands to the uCode */
2760         set_bit(STATUS_ALIVE, &priv->status);
2761
2762         if (priv->cfg->ops->lib->recover_from_tx_stall) {
2763                 /* Enable timer to monitor the driver queues */
2764                 mod_timer(&priv->monitor_recover,
2765                         jiffies +
2766                         msecs_to_jiffies(priv->cfg->monitor_recover_period));
2767         }
2768
2769         if (iwl_is_rfkill(priv))
2770                 return;
2771
2772         ieee80211_wake_queues(priv->hw);
2773
2774         priv->active_rate = IWL_RATES_MASK;
2775
2776         /* Configure Tx antenna selection based on H/W config */
2777         if (priv->cfg->ops->hcmd->set_tx_ant)
2778                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2779
2780         if (iwl_is_associated_ctx(ctx)) {
2781                 struct iwl_rxon_cmd *active_rxon =
2782                                 (struct iwl_rxon_cmd *)&ctx->active;
2783                 /* apply any changes in staging */
2784                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2785                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2786         } else {
2787                 /* Initialize our rx_config data */
2788                 iwl_connection_init_rx_config(priv, NULL);
2789
2790                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2791                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2792         }
2793
2794         if (!priv->cfg->advanced_bt_coexist) {
2795                 /* Configure Bluetooth device coexistence support */
2796                 priv->cfg->ops->hcmd->send_bt_config(priv);
2797         }
2798
2799         iwl_reset_run_time_calib(priv);
2800
2801         /* Configure the adapter for unassociated operation */
2802         iwlcore_commit_rxon(priv, ctx);
2803
2804         /* At this point, the NIC is initialized and operational */
2805         iwl_rf_kill_ct_config(priv);
2806
2807         iwl_leds_init(priv);
2808
2809         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2810         set_bit(STATUS_READY, &priv->status);
2811         wake_up_interruptible(&priv->wait_command_queue);
2812
2813         iwl_power_update_mode(priv, true);
2814         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2815
2816
2817         return;
2818
2819  restart:
2820         queue_work(priv->workqueue, &priv->restart);
2821 }
2822
2823 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2824
2825 static void __iwl_down(struct iwl_priv *priv)
2826 {
2827         unsigned long flags;
2828         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2829
2830         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2831
2832         if (!exit_pending)
2833                 set_bit(STATUS_EXIT_PENDING, &priv->status);
2834
2835         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2836          * to prevent rearm timer */
2837         if (priv->cfg->ops->lib->recover_from_tx_stall)
2838                 del_timer_sync(&priv->monitor_recover);
2839
2840         iwl_clear_ucode_stations(priv, NULL);
2841         iwl_dealloc_bcast_stations(priv);
2842         iwl_clear_driver_stations(priv);
2843
2844         /* reset BT coex data */
2845         priv->bt_status = 0;
2846         priv->bt_traffic_load = priv->cfg->bt_init_traffic_load;
2847         priv->bt_sco_active = false;
2848         priv->bt_full_concurrent = false;
2849         priv->bt_ci_compliance = 0;
2850
2851         /* Unblock any waiting calls */
2852         wake_up_interruptible_all(&priv->wait_command_queue);
2853
2854         /* Wipe out the EXIT_PENDING status bit if we are not actually
2855          * exiting the module */
2856         if (!exit_pending)
2857                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2858
2859         /* stop and reset the on-board processor */
2860         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2861
2862         /* tell the device to stop sending interrupts */
2863         spin_lock_irqsave(&priv->lock, flags);
2864         iwl_disable_interrupts(priv);
2865         spin_unlock_irqrestore(&priv->lock, flags);
2866         iwl_synchronize_irq(priv);
2867
2868         if (priv->mac80211_registered)
2869                 ieee80211_stop_queues(priv->hw);
2870
2871         /* If we have not previously called iwl_init() then
2872          * clear all bits but the RF Kill bit and return */
2873         if (!iwl_is_init(priv)) {
2874                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2875                                         STATUS_RF_KILL_HW |
2876                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2877                                         STATUS_GEO_CONFIGURED |
2878                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2879                                         STATUS_EXIT_PENDING;
2880                 goto exit;
2881         }
2882
2883         /* ...otherwise clear out all the status bits but the RF Kill
2884          * bit and continue taking the NIC down. */
2885         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2886                                 STATUS_RF_KILL_HW |
2887                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2888                                 STATUS_GEO_CONFIGURED |
2889                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2890                                 STATUS_FW_ERROR |
2891                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2892                                 STATUS_EXIT_PENDING;
2893
2894         /* device going down, Stop using ICT table */
2895         iwl_disable_ict(priv);
2896
2897         iwlagn_txq_ctx_stop(priv);
2898         iwlagn_rxq_stop(priv);
2899
2900         /* Power-down device's busmaster DMA clocks */
2901         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2902         udelay(5);
2903
2904         /* Make sure (redundant) we've released our request to stay awake */
2905         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2906
2907         /* Stop the device, and put it in low power state */
2908         priv->cfg->ops->lib->apm_ops.stop(priv);
2909
2910  exit:
2911         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2912
2913         if (priv->ibss_beacon)
2914                 dev_kfree_skb(priv->ibss_beacon);
2915         priv->ibss_beacon = NULL;
2916
2917         /* clear out any free frames */
2918         iwl_clear_free_frames(priv);
2919 }
2920
2921 static void iwl_down(struct iwl_priv *priv)
2922 {
2923         mutex_lock(&priv->mutex);
2924         __iwl_down(priv);
2925         mutex_unlock(&priv->mutex);
2926
2927         iwl_cancel_deferred_work(priv);
2928 }
2929
2930 #define HW_READY_TIMEOUT (50)
2931
2932 static int iwl_set_hw_ready(struct iwl_priv *priv)
2933 {
2934         int ret = 0;
2935
2936         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2937                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2938
2939         /* See if we got it */
2940         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2941                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2942                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2943                                 HW_READY_TIMEOUT);
2944         if (ret != -ETIMEDOUT)
2945                 priv->hw_ready = true;
2946         else
2947                 priv->hw_ready = false;
2948
2949         IWL_DEBUG_INFO(priv, "hardware %s\n",
2950                       (priv->hw_ready == 1) ? "ready" : "not ready");
2951         return ret;
2952 }
2953
2954 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2955 {
2956         int ret = 0;
2957
2958         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2959
2960         ret = iwl_set_hw_ready(priv);
2961         if (priv->hw_ready)
2962                 return ret;
2963
2964         /* If HW is not ready, prepare the conditions to check again */
2965         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2966                         CSR_HW_IF_CONFIG_REG_PREPARE);
2967
2968         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2969                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2970                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2971
2972         /* HW should be ready by now, check again. */
2973         if (ret != -ETIMEDOUT)
2974                 iwl_set_hw_ready(priv);
2975
2976         return ret;
2977 }
2978
2979 #define MAX_HW_RESTARTS 5
2980
2981 static int __iwl_up(struct iwl_priv *priv)
2982 {
2983         struct iwl_rxon_context *ctx;
2984         int i;
2985         int ret;
2986
2987         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2988                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2989                 return -EIO;
2990         }
2991
2992         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2993                 IWL_ERR(priv, "ucode not available for device bringup\n");
2994                 return -EIO;
2995         }
2996
2997         for_each_context(priv, ctx) {
2998                 ret = iwl_alloc_bcast_station(priv, ctx, true);
2999                 if (ret) {
3000                         iwl_dealloc_bcast_stations(priv);
3001                         return ret;
3002                 }
3003         }
3004
3005         iwl_prepare_card_hw(priv);
3006
3007         if (!priv->hw_ready) {
3008                 IWL_WARN(priv, "Exit HW not ready\n");
3009                 return -EIO;
3010         }
3011
3012         /* If platform's RF_KILL switch is NOT set to KILL */
3013         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3014                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3015         else
3016                 set_bit(STATUS_RF_KILL_HW, &priv->status);
3017
3018         if (iwl_is_rfkill(priv)) {
3019                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3020
3021                 iwl_enable_interrupts(priv);
3022                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
3023                 return 0;
3024         }
3025
3026         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3027
3028         /* must be initialised before iwl_hw_nic_init */
3029         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3030                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3031         else
3032                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
3033
3034         ret = iwlagn_hw_nic_init(priv);
3035         if (ret) {
3036                 IWL_ERR(priv, "Unable to init nic\n");
3037                 return ret;
3038         }
3039
3040         /* make sure rfkill handshake bits are cleared */
3041         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3042         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
3043                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3044
3045         /* clear (again), then enable host interrupts */
3046         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3047         iwl_enable_interrupts(priv);
3048
3049         /* really make sure rfkill handshake bits are cleared */
3050         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3051         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3052
3053         /* Copy original ucode data image from disk into backup cache.
3054          * This will be used to initialize the on-board processor's
3055          * data SRAM for a clean start when the runtime program first loads. */
3056         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
3057                priv->ucode_data.len);
3058
3059         for (i = 0; i < MAX_HW_RESTARTS; i++) {
3060
3061                 /* load bootstrap state machine,
3062                  * load bootstrap program into processor's memory,
3063                  * prepare to load the "initialize" uCode */
3064                 ret = priv->cfg->ops->lib->load_ucode(priv);
3065
3066                 if (ret) {
3067                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3068                                 ret);
3069                         continue;
3070                 }
3071
3072                 /* start card; "initialize" will load runtime ucode */
3073                 iwl_nic_start(priv);
3074
3075                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
3076
3077                 return 0;
3078         }
3079
3080         set_bit(STATUS_EXIT_PENDING, &priv->status);
3081         __iwl_down(priv);
3082         clear_bit(STATUS_EXIT_PENDING, &priv->status);
3083
3084         /* tried to restart and config the device for as long as our
3085          * patience could withstand */
3086         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
3087         return -EIO;
3088 }
3089
3090
3091 /*****************************************************************************
3092  *
3093  * Workqueue callbacks
3094  *
3095  *****************************************************************************/
3096
3097 static void iwl_bg_init_alive_start(struct work_struct *data)
3098 {
3099         struct iwl_priv *priv =
3100             container_of(data, struct iwl_priv, init_alive_start.work);
3101
3102         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3103                 return;
3104
3105         mutex_lock(&priv->mutex);
3106         priv->cfg->ops->lib->init_alive_start(priv);
3107         mutex_unlock(&priv->mutex);
3108 }
3109
3110 static void iwl_bg_alive_start(struct work_struct *data)
3111 {
3112         struct iwl_priv *priv =
3113             container_of(data, struct iwl_priv, alive_start.work);
3114
3115         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3116                 return;
3117
3118         /* enable dram interrupt */
3119         iwl_reset_ict(priv);
3120
3121         mutex_lock(&priv->mutex);
3122         iwl_alive_start(priv);
3123         mutex_unlock(&priv->mutex);
3124 }
3125
3126 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3127 {
3128         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3129                         run_time_calib_work);
3130
3131         mutex_lock(&priv->mutex);
3132
3133         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3134             test_bit(STATUS_SCANNING, &priv->status)) {
3135                 mutex_unlock(&priv->mutex);
3136                 return;
3137         }
3138
3139         if (priv->start_calib) {
3140                 if (priv->cfg->bt_statistics) {
3141                         iwl_chain_noise_calibration(priv,
3142                                         (void *)&priv->_agn.statistics_bt);
3143                         iwl_sensitivity_calibration(priv,
3144                                         (void *)&priv->_agn.statistics_bt);
3145                 } else {
3146                         iwl_chain_noise_calibration(priv,
3147                                         (void *)&priv->_agn.statistics);
3148                         iwl_sensitivity_calibration(priv,
3149                                         (void *)&priv->_agn.statistics);
3150                 }
3151         }
3152
3153         mutex_unlock(&priv->mutex);
3154 }
3155
3156 static void iwl_bg_restart(struct work_struct *data)
3157 {
3158         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3159
3160         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3161                 return;
3162
3163         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3164                 struct iwl_rxon_context *ctx;
3165                 bool bt_sco, bt_full_concurrent;
3166                 u8 bt_ci_compliance;
3167                 u8 bt_load;
3168                 u8 bt_status;
3169
3170                 mutex_lock(&priv->mutex);
3171                 for_each_context(priv, ctx)
3172                         ctx->vif = NULL;
3173                 priv->is_open = 0;
3174
3175                 /*
3176                  * __iwl_down() will clear the BT status variables,
3177                  * which is correct, but when we restart we really
3178                  * want to keep them so restore them afterwards.
3179                  *
3180                  * The restart process will later pick them up and
3181                  * re-configure the hw when we reconfigure the BT
3182                  * command.
3183                  */
3184                 bt_sco = priv->bt_sco_active;
3185                 bt_full_concurrent = priv->bt_full_concurrent;
3186                 bt_ci_compliance = priv->bt_ci_compliance;
3187                 bt_load = priv->bt_traffic_load;
3188                 bt_status = priv->bt_status;
3189
3190                 __iwl_down(priv);
3191
3192                 priv->bt_sco_active = bt_sco;
3193                 priv->bt_full_concurrent = bt_full_concurrent;
3194                 priv->bt_ci_compliance = bt_ci_compliance;
3195                 priv->bt_traffic_load = bt_load;
3196                 priv->bt_status = bt_status;
3197
3198                 mutex_unlock(&priv->mutex);
3199                 iwl_cancel_deferred_work(priv);
3200                 ieee80211_restart_hw(priv->hw);
3201         } else {
3202                 iwl_down(priv);
3203
3204                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3205                         return;
3206
3207                 mutex_lock(&priv->mutex);
3208                 __iwl_up(priv);
3209                 mutex_unlock(&priv->mutex);
3210         }
3211 }
3212
3213 static void iwl_bg_rx_replenish(struct work_struct *data)
3214 {
3215         struct iwl_priv *priv =
3216             container_of(data, struct iwl_priv, rx_replenish);
3217
3218         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3219                 return;
3220
3221         mutex_lock(&priv->mutex);
3222         iwlagn_rx_replenish(priv);
3223         mutex_unlock(&priv->mutex);
3224 }
3225
3226 #define IWL_DELAY_NEXT_SCAN (HZ*2)
3227
3228 void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
3229 {
3230         struct iwl_rxon_context *ctx;
3231         struct ieee80211_conf *conf = NULL;
3232         int ret = 0;
3233
3234         if (!vif || !priv->is_open)
3235                 return;
3236
3237         ctx = iwl_rxon_ctx_from_vif(vif);
3238
3239         if (vif->type == NL80211_IFTYPE_AP) {
3240                 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
3241                 return;
3242         }
3243
3244         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3245                 return;
3246
3247         iwl_scan_cancel_timeout(priv, 200);
3248
3249         conf = ieee80211_get_hw_conf(priv->hw);
3250
3251         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3252         iwlcore_commit_rxon(priv, ctx);
3253
3254         ret = iwl_send_rxon_timing(priv, vif);
3255         if (ret)
3256                 IWL_WARN(priv, "RXON timing - "
3257                             "Attempting to continue.\n");
3258
3259         ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3260
3261         iwl_set_rxon_ht(priv, &priv->current_ht_config);
3262
3263         if (priv->cfg->ops->hcmd->set_rxon_chain)
3264                 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3265
3266         ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
3267
3268         IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
3269                         vif->bss_conf.aid, vif->bss_conf.beacon_int);
3270
3271         if (vif->bss_conf.use_short_preamble)
3272                 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3273         else
3274                 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3275
3276         if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3277                 if (vif->bss_conf.use_short_slot)
3278                         ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
3279                 else
3280                         ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3281         }
3282
3283         iwlcore_commit_rxon(priv, ctx);
3284
3285         IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
3286                         vif->bss_conf.aid, ctx->active.bssid_addr);
3287
3288         switch (vif->type) {
3289         case NL80211_IFTYPE_STATION:
3290                 break;
3291         case NL80211_IFTYPE_ADHOC:
3292                 iwl_send_beacon_cmd(priv);
3293                 break;
3294         default:
3295                 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3296                           __func__, vif->type);
3297                 break;
3298         }
3299
3300         /* the chain noise calibration will enabled PM upon completion
3301          * If chain noise has already been run, then we need to enable
3302          * power management here */
3303         if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
3304                 iwl_power_update_mode(priv, false);
3305
3306         /* Enable Rx differential gain and sensitivity calibrations */
3307         iwl_chain_noise_reset(priv);
3308         priv->start_calib = 1;
3309
3310 }
3311
3312 /*****************************************************************************
3313  *
3314  * mac80211 entry point functions
3315  *
3316  *****************************************************************************/
3317
3318 #define UCODE_READY_TIMEOUT     (4 * HZ)
3319
3320 /*
3321  * Not a mac80211 entry point function, but it fits in with all the
3322  * other mac80211 functions grouped here.
3323  */
3324 static int iwl_mac_setup_register(struct iwl_priv *priv,
3325                                   struct iwlagn_ucode_capabilities *capa)
3326 {
3327         int ret;
3328         struct ieee80211_hw *hw = priv->hw;
3329         hw->rate_control_algorithm = "iwl-agn-rs";
3330
3331         /* Tell mac80211 our characteristics */
3332         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3333                     IEEE80211_HW_AMPDU_AGGREGATION |
3334                     IEEE80211_HW_SPECTRUM_MGMT;
3335
3336         if (!priv->cfg->broken_powersave)
3337                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3338                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3339
3340         if (priv->cfg->sku & IWL_SKU_N)
3341                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3342                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3343
3344         hw->sta_data_size = sizeof(struct iwl_station_priv);
3345         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3346
3347         hw->wiphy->interface_modes =
3348                 BIT(NL80211_IFTYPE_STATION) |
3349                 BIT(NL80211_IFTYPE_ADHOC);
3350
3351         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3352                             WIPHY_FLAG_DISABLE_BEACON_HINTS;
3353
3354         /*
3355          * For now, disable PS by default because it affects
3356          * RX performance significantly.
3357          */
3358         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3359
3360         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3361         /* we create the 802.11 header and a zero-length SSID element */
3362         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3363
3364         /* Default value; 4 EDCA QOS priorities */
3365         hw->queues = 4;
3366
3367         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3368
3369         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3370                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3371                         &priv->bands[IEEE80211_BAND_2GHZ];
3372         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3373                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3374                         &priv->bands[IEEE80211_BAND_5GHZ];
3375
3376         ret = ieee80211_register_hw(priv->hw);
3377         if (ret) {
3378                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3379                 return ret;
3380         }
3381         priv->mac80211_registered = 1;
3382
3383         return 0;
3384 }
3385
3386
3387 static int iwl_mac_start(struct ieee80211_hw *hw)
3388 {
3389         struct iwl_priv *priv = hw->priv;
3390         int ret;
3391
3392         IWL_DEBUG_MAC80211(priv, "enter\n");
3393
3394         /* we should be verifying the device is ready to be opened */
3395         mutex_lock(&priv->mutex);
3396         ret = __iwl_up(priv);
3397         mutex_unlock(&priv->mutex);
3398
3399         if (ret)
3400                 return ret;
3401
3402         if (iwl_is_rfkill(priv))
3403                 goto out;
3404
3405         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3406
3407         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3408          * mac80211 will not be run successfully. */
3409         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3410                         test_bit(STATUS_READY, &priv->status),
3411                         UCODE_READY_TIMEOUT);
3412         if (!ret) {
3413                 if (!test_bit(STATUS_READY, &priv->status)) {
3414                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3415                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3416                         return -ETIMEDOUT;
3417                 }
3418         }
3419
3420         iwl_led_start(priv);
3421
3422 out:
3423         priv->is_open = 1;
3424         IWL_DEBUG_MAC80211(priv, "leave\n");
3425         return 0;
3426 }
3427
3428 static void iwl_mac_stop(struct ieee80211_hw *hw)
3429 {
3430         struct iwl_priv *priv = hw->priv;
3431
3432         IWL_DEBUG_MAC80211(priv, "enter\n");
3433
3434         if (!priv->is_open)
3435                 return;
3436
3437         priv->is_open = 0;
3438
3439         if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
3440                 /* stop mac, cancel any scan request and clear
3441                  * RXON_FILTER_ASSOC_MSK BIT
3442                  */
3443                 mutex_lock(&priv->mutex);
3444                 iwl_scan_cancel_timeout(priv, 100);
3445                 mutex_unlock(&priv->mutex);
3446         }
3447
3448         iwl_down(priv);
3449
3450         flush_workqueue(priv->workqueue);
3451
3452         /* enable interrupts again in order to receive rfkill changes */
3453         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3454         iwl_enable_interrupts(priv);
3455
3456         IWL_DEBUG_MAC80211(priv, "leave\n");
3457 }
3458
3459 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3460 {
3461         struct iwl_priv *priv = hw->priv;
3462
3463         IWL_DEBUG_MACDUMP(priv, "enter\n");
3464
3465         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3466                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3467
3468         if (iwlagn_tx_skb(priv, skb))
3469                 dev_kfree_skb_any(skb);
3470
3471         IWL_DEBUG_MACDUMP(priv, "leave\n");
3472         return NETDEV_TX_OK;
3473 }
3474
3475 void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
3476 {
3477         struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
3478         int ret = 0;
3479
3480         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3481                 return;
3482
3483         /* The following should be done only at AP bring up */
3484         if (!iwl_is_associated_ctx(ctx)) {
3485
3486                 /* RXON - unassoc (to set timing command) */
3487                 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3488                 iwlcore_commit_rxon(priv, ctx);
3489
3490                 /* RXON Timing */
3491                 ret = iwl_send_rxon_timing(priv, vif);
3492                 if (ret)
3493                         IWL_WARN(priv, "RXON timing failed - "
3494                                         "Attempting to continue.\n");
3495
3496                 /* AP has all antennas */
3497                 priv->chain_noise_data.active_chains =
3498                         priv->hw_params.valid_rx_ant;
3499                 iwl_set_rxon_ht(priv, &priv->current_ht_config);
3500                 if (priv->cfg->ops->hcmd->set_rxon_chain)
3501                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
3502
3503                 ctx->staging.assoc_id = 0;
3504
3505                 if (vif->bss_conf.use_short_preamble)
3506                         ctx->staging.flags |=
3507                                 RXON_FLG_SHORT_PREAMBLE_MSK;
3508                 else
3509                         ctx->staging.flags &=
3510                                 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3511
3512                 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
3513                         if (vif->bss_conf.use_short_slot)
3514                                 ctx->staging.flags |=
3515                                         RXON_FLG_SHORT_SLOT_MSK;
3516                         else
3517                                 ctx->staging.flags &=
3518                                         ~RXON_FLG_SHORT_SLOT_MSK;
3519                 }
3520                 /* restore RXON assoc */
3521                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3522                 iwlcore_commit_rxon(priv, ctx);
3523         }
3524         iwl_send_beacon_cmd(priv);
3525
3526         /* FIXME - we need to add code here to detect a totally new
3527          * configuration, reset the AP, unassoc, rxon timing, assoc,
3528          * clear sta table, add BCAST sta... */
3529 }
3530
3531 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
3532                                     struct ieee80211_vif *vif,
3533                                     struct ieee80211_key_conf *keyconf,
3534                                     struct ieee80211_sta *sta,
3535                                     u32 iv32, u16 *phase1key)
3536 {
3537
3538         struct iwl_priv *priv = hw->priv;
3539         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3540
3541         IWL_DEBUG_MAC80211(priv, "enter\n");
3542
3543         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3544                             iv32, phase1key);
3545
3546         IWL_DEBUG_MAC80211(priv, "leave\n");
3547 }
3548
3549 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3550                            struct ieee80211_vif *vif,
3551                            struct ieee80211_sta *sta,
3552                            struct ieee80211_key_conf *key)
3553 {
3554         struct iwl_priv *priv = hw->priv;
3555         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3556         struct iwl_rxon_context *ctx = vif_priv->ctx;
3557         int ret;
3558         u8 sta_id;
3559         bool is_default_wep_key = false;
3560
3561         IWL_DEBUG_MAC80211(priv, "enter\n");
3562
3563         if (priv->cfg->mod_params->sw_crypto) {
3564                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3565                 return -EOPNOTSUPP;
3566         }
3567
3568         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3569         if (sta_id == IWL_INVALID_STATION)
3570                 return -EINVAL;
3571
3572         mutex_lock(&priv->mutex);
3573         iwl_scan_cancel_timeout(priv, 100);
3574
3575         /*
3576          * If we are getting WEP group key and we didn't receive any key mapping
3577          * so far, we are in legacy wep mode (group key only), otherwise we are
3578          * in 1X mode.
3579          * In legacy wep mode, we use another host command to the uCode.
3580          */
3581         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3582              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3583             !sta) {
3584                 if (cmd == SET_KEY)
3585                         is_default_wep_key = !ctx->key_mapping_keys;
3586                 else
3587                         is_default_wep_key =
3588                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3589         }
3590
3591         switch (cmd) {
3592         case SET_KEY:
3593                 if (is_default_wep_key)
3594                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3595                 else
3596                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3597                                                   key, sta_id);
3598
3599                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3600                 break;
3601         case DISABLE_KEY:
3602                 if (is_default_wep_key)
3603                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3604                 else
3605                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3606
3607                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3608                 break;
3609         default:
3610                 ret = -EINVAL;
3611         }
3612
3613         mutex_unlock(&priv->mutex);
3614         IWL_DEBUG_MAC80211(priv, "leave\n");
3615
3616         return ret;
3617 }
3618
3619 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
3620                                 struct ieee80211_vif *vif,
3621                                 enum ieee80211_ampdu_mlme_action action,
3622                                 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3623 {
3624         struct iwl_priv *priv = hw->priv;
3625         int ret = -EINVAL;
3626
3627         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3628                      sta->addr, tid);
3629
3630         if (!(priv->cfg->sku & IWL_SKU_N))
3631                 return -EACCES;
3632
3633         mutex_lock(&priv->mutex);
3634
3635         switch (action) {
3636         case IEEE80211_AMPDU_RX_START:
3637                 IWL_DEBUG_HT(priv, "start Rx\n");
3638                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3639                 break;
3640         case IEEE80211_AMPDU_RX_STOP:
3641                 IWL_DEBUG_HT(priv, "stop Rx\n");
3642                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3643                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3644                         ret = 0;
3645                 break;
3646         case IEEE80211_AMPDU_TX_START:
3647                 IWL_DEBUG_HT(priv, "start Tx\n");
3648                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3649                 if (ret == 0) {
3650                         priv->_agn.agg_tids_count++;
3651                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3652                                      priv->_agn.agg_tids_count);
3653                 }
3654                 break;
3655         case IEEE80211_AMPDU_TX_STOP:
3656                 IWL_DEBUG_HT(priv, "stop Tx\n");
3657                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3658                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3659                         priv->_agn.agg_tids_count--;
3660                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3661                                      priv->_agn.agg_tids_count);
3662                 }
3663                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3664                         ret = 0;
3665                 if (priv->cfg->use_rts_for_aggregation) {
3666                         struct iwl_station_priv *sta_priv =
3667                                 (void *) sta->drv_priv;
3668                         /*
3669                          * switch off RTS/CTS if it was previously enabled
3670                          */
3671
3672                         sta_priv->lq_sta.lq.general_params.flags &=
3673                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3674                         iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
3675                                 CMD_ASYNC, false);
3676                 }
3677                 break;
3678         case IEEE80211_AMPDU_TX_OPERATIONAL:
3679                 if (priv->cfg->use_rts_for_aggregation) {
3680                         struct iwl_station_priv *sta_priv =
3681                                 (void *) sta->drv_priv;
3682
3683                         /*
3684                          * switch to RTS/CTS if it is the prefer protection
3685                          * method for HT traffic
3686                          */
3687
3688                         sta_priv->lq_sta.lq.general_params.flags |=
3689                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3690                         iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
3691                                 CMD_ASYNC, false);
3692                 }
3693                 ret = 0;
3694                 break;
3695         }
3696         mutex_unlock(&priv->mutex);
3697
3698         return ret;
3699 }
3700
3701 static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3702                                struct ieee80211_vif *vif,
3703                                enum sta_notify_cmd cmd,
3704                                struct ieee80211_sta *sta)
3705 {
3706         struct iwl_priv *priv = hw->priv;
3707         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3708         int sta_id;
3709
3710         switch (cmd) {
3711         case STA_NOTIFY_SLEEP:
3712                 WARN_ON(!sta_priv->client);
3713                 sta_priv->asleep = true;
3714                 if (atomic_read(&sta_priv->pending_frames) > 0)
3715                         ieee80211_sta_block_awake(hw, sta, true);
3716                 break;
3717         case STA_NOTIFY_AWAKE:
3718                 WARN_ON(!sta_priv->client);
3719                 if (!sta_priv->asleep)
3720                         break;
3721                 sta_priv->asleep = false;
3722                 sta_id = iwl_sta_id(sta);
3723                 if (sta_id != IWL_INVALID_STATION)
3724                         iwl_sta_modify_ps_wake(priv, sta_id);
3725                 break;
3726         default:
3727                 break;
3728         }
3729 }
3730
3731 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3732                               struct ieee80211_vif *vif,
3733                               struct ieee80211_sta *sta)
3734 {
3735         struct iwl_priv *priv = hw->priv;
3736         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3737         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3738         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3739         int ret;
3740         u8 sta_id;
3741
3742         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3743                         sta->addr);
3744         mutex_lock(&priv->mutex);
3745         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3746                         sta->addr);
3747         sta_priv->common.sta_id = IWL_INVALID_STATION;
3748
3749         atomic_set(&sta_priv->pending_frames, 0);
3750         if (vif->type == NL80211_IFTYPE_AP)
3751                 sta_priv->client = true;
3752
3753         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3754                                      is_ap, sta, &sta_id);
3755         if (ret) {
3756                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3757                         sta->addr, ret);
3758                 /* Should we return success if return code is EEXIST ? */
3759                 mutex_unlock(&priv->mutex);
3760                 return ret;
3761         }
3762
3763         sta_priv->common.sta_id = sta_id;
3764
3765         /* Initialize rate scaling */
3766         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3767                        sta->addr);
3768         iwl_rs_rate_init(priv, sta, sta_id);
3769         mutex_unlock(&priv->mutex);
3770
3771         return 0;
3772 }
3773
3774 static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3775                                    struct ieee80211_channel_switch *ch_switch)
3776 {
3777         struct iwl_priv *priv = hw->priv;
3778         const struct iwl_channel_info *ch_info;
3779         struct ieee80211_conf *conf = &hw->conf;
3780         struct ieee80211_channel *channel = ch_switch->channel;
3781         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3782         /*
3783          * MULTI-FIXME
3784          * When we add support for multiple interfaces, we need to
3785          * revisit this. The channel switch command in the device
3786          * only affects the BSS context, but what does that really
3787          * mean? And what if we get a CSA on the second interface?
3788          * This needs a lot of work.
3789          */
3790         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3791         u16 ch;
3792         unsigned long flags = 0;
3793
3794         IWL_DEBUG_MAC80211(priv, "enter\n");
3795
3796         if (iwl_is_rfkill(priv))
3797                 goto out_exit;
3798
3799         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3800             test_bit(STATUS_SCANNING, &priv->status))
3801                 goto out_exit;
3802
3803         if (!iwl_is_associated_ctx(ctx))
3804                 goto out_exit;
3805
3806         /* channel switch in progress */
3807         if (priv->switch_rxon.switch_in_progress == true)
3808                 goto out_exit;
3809
3810         mutex_lock(&priv->mutex);
3811         if (priv->cfg->ops->lib->set_channel_switch) {
3812
3813                 ch = channel->hw_value;
3814                 if (le16_to_cpu(ctx->active.channel) != ch) {
3815                         ch_info = iwl_get_channel_info(priv,
3816                                                        channel->band,
3817                                                        ch);
3818                         if (!is_channel_valid(ch_info)) {
3819                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3820                                 goto out;
3821                         }
3822                         spin_lock_irqsave(&priv->lock, flags);
3823
3824                         priv->current_ht_config.smps = conf->smps_mode;
3825
3826                         /* Configure HT40 channels */
3827                         ht_conf->is_ht = conf_is_ht(conf);
3828                         if (ht_conf->is_ht) {
3829                                 if (conf_is_ht40_minus(conf)) {
3830                                         ht_conf->extension_chan_offset =
3831                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3832                                         ht_conf->is_40mhz = true;
3833                                 } else if (conf_is_ht40_plus(conf)) {
3834                                         ht_conf->extension_chan_offset =
3835                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3836                                         ht_conf->is_40mhz = true;
3837                                 } else {
3838                                         ht_conf->extension_chan_offset =
3839                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3840                                         ht_conf->is_40mhz = false;
3841                                 }
3842                         } else
3843                                 ht_conf->is_40mhz = false;
3844
3845                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3846                                 ctx->staging.flags = 0;
3847
3848                         iwl_set_rxon_channel(priv, channel, ctx);
3849                         iwl_set_rxon_ht(priv, ht_conf);
3850                         iwl_set_flags_for_band(priv, ctx, channel->band,
3851                                                ctx->vif);
3852                         spin_unlock_irqrestore(&priv->lock, flags);
3853
3854                         iwl_set_rate(priv);
3855                         /*
3856                          * at this point, staging_rxon has the
3857                          * configuration for channel switch
3858                          */
3859                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3860                                                                     ch_switch))
3861                                 priv->switch_rxon.switch_in_progress = false;
3862                 }
3863         }
3864 out:
3865         mutex_unlock(&priv->mutex);
3866 out_exit:
3867         if (!priv->switch_rxon.switch_in_progress)
3868                 ieee80211_chswitch_done(ctx->vif, false);
3869         IWL_DEBUG_MAC80211(priv, "leave\n");
3870 }
3871
3872 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3873                                     unsigned int changed_flags,
3874                                     unsigned int *total_flags,
3875                                     u64 multicast)
3876 {
3877         struct iwl_priv *priv = hw->priv;
3878         __le32 filter_or = 0, filter_nand = 0;
3879         struct iwl_rxon_context *ctx;
3880
3881 #define CHK(test, flag) do { \
3882         if (*total_flags & (test))              \
3883                 filter_or |= (flag);            \
3884         else                                    \
3885                 filter_nand |= (flag);          \
3886         } while (0)
3887
3888         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3889                         changed_flags, *total_flags);
3890
3891         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3892         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3893         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3894
3895 #undef CHK
3896
3897         mutex_lock(&priv->mutex);
3898
3899         for_each_context(priv, ctx) {
3900                 ctx->staging.filter_flags &= ~filter_nand;
3901                 ctx->staging.filter_flags |= filter_or;
3902                 iwlcore_commit_rxon(priv, ctx);
3903         }
3904
3905         mutex_unlock(&priv->mutex);
3906
3907         /*
3908          * Receiving all multicast frames is always enabled by the
3909          * default flags setup in iwl_connection_init_rx_config()
3910          * since we currently do not support programming multicast
3911          * filters into the device.
3912          */
3913         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3914                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3915 }
3916
3917 static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3918 {
3919         struct iwl_priv *priv = hw->priv;
3920
3921         mutex_lock(&priv->mutex);
3922         IWL_DEBUG_MAC80211(priv, "enter\n");
3923
3924         /* do not support "flush" */
3925         if (!priv->cfg->ops->lib->txfifo_flush)
3926                 goto done;
3927
3928         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3929                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3930                 goto done;
3931         }
3932         if (iwl_is_rfkill(priv)) {
3933                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3934                 goto done;
3935         }
3936
3937         /*
3938          * mac80211 will not push any more frames for transmit
3939          * until the flush is completed
3940          */
3941         if (drop) {
3942                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3943                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3944                         IWL_ERR(priv, "flush request fail\n");
3945                         goto done;
3946                 }
3947         }
3948         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3949         iwlagn_wait_tx_queue_empty(priv);
3950 done:
3951         mutex_unlock(&priv->mutex);
3952         IWL_DEBUG_MAC80211(priv, "leave\n");
3953 }
3954
3955 /*****************************************************************************
3956  *
3957  * driver setup and teardown
3958  *
3959  *****************************************************************************/
3960
3961 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3962 {
3963         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3964
3965         init_waitqueue_head(&priv->wait_command_queue);
3966
3967         INIT_WORK(&priv->restart, iwl_bg_restart);
3968         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3969         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3970         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3971         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3972         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3973         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3974         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3975         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3976
3977         iwl_setup_scan_deferred_work(priv);
3978
3979         if (priv->cfg->ops->lib->setup_deferred_work)
3980                 priv->cfg->ops->lib->setup_deferred_work(priv);
3981
3982         init_timer(&priv->statistics_periodic);
3983         priv->statistics_periodic.data = (unsigned long)priv;
3984         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3985
3986         init_timer(&priv->ucode_trace);
3987         priv->ucode_trace.data = (unsigned long)priv;
3988         priv->ucode_trace.function = iwl_bg_ucode_trace;
3989
3990         if (priv->cfg->ops->lib->recover_from_tx_stall) {
3991                 init_timer(&priv->monitor_recover);
3992                 priv->monitor_recover.data = (unsigned long)priv;
3993                 priv->monitor_recover.function =
3994                         priv->cfg->ops->lib->recover_from_tx_stall;
3995         }
3996
3997         if (!priv->cfg->use_isr_legacy)
3998                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3999                         iwl_irq_tasklet, (unsigned long)priv);
4000         else
4001                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4002                         iwl_irq_tasklet_legacy, (unsigned long)priv);
4003 }
4004
4005 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
4006 {
4007         if (priv->cfg->ops->lib->cancel_deferred_work)
4008                 priv->cfg->ops->lib->cancel_deferred_work(priv);
4009
4010         cancel_delayed_work_sync(&priv->init_alive_start);
4011         cancel_delayed_work(&priv->scan_check);
4012         cancel_work_sync(&priv->start_internal_scan);
4013         cancel_delayed_work(&priv->alive_start);
4014         cancel_work_sync(&priv->run_time_calib_work);
4015         cancel_work_sync(&priv->beacon_update);
4016         cancel_work_sync(&priv->bt_full_concurrency);
4017         cancel_work_sync(&priv->bt_runtime_config);
4018         del_timer_sync(&priv->statistics_periodic);
4019         del_timer_sync(&priv->ucode_trace);
4020 }
4021
4022 static void iwl_init_hw_rates(struct iwl_priv *priv,
4023                               struct ieee80211_rate *rates)
4024 {
4025         int i;
4026
4027         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4028                 rates[i].bitrate = iwl_rates[i].ieee * 5;
4029                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4030                 rates[i].hw_value_short = i;
4031                 rates[i].flags = 0;
4032                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4033                         /*
4034                          * If CCK != 1M then set short preamble rate flag.
4035                          */
4036                         rates[i].flags |=
4037                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4038                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
4039                 }
4040         }
4041 }
4042
4043 static int iwl_init_drv(struct iwl_priv *priv)
4044 {
4045         int ret;
4046
4047         priv->ibss_beacon = NULL;
4048
4049         spin_lock_init(&priv->sta_lock);
4050         spin_lock_init(&priv->hcmd_lock);
4051
4052         INIT_LIST_HEAD(&priv->free_frames);
4053
4054         mutex_init(&priv->mutex);
4055         mutex_init(&priv->sync_cmd_mutex);
4056
4057         priv->ieee_channels = NULL;
4058         priv->ieee_rates = NULL;
4059         priv->band = IEEE80211_BAND_2GHZ;
4060
4061         priv->iw_mode = NL80211_IFTYPE_STATION;
4062         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
4063         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
4064         priv->_agn.agg_tids_count = 0;
4065
4066         /* initialize force reset */
4067         priv->force_reset[IWL_RF_RESET].reset_duration =
4068                 IWL_DELAY_NEXT_FORCE_RF_RESET;
4069         priv->force_reset[IWL_FW_RESET].reset_duration =
4070                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
4071
4072         /* Choose which receivers/antennas to use */
4073         if (priv->cfg->ops->hcmd->set_rxon_chain)
4074                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4075                                         &priv->contexts[IWL_RXON_CTX_BSS]);
4076
4077         iwl_init_scan_params(priv);
4078
4079         /* init bt coex */
4080         if (priv->cfg->advanced_bt_coexist) {
4081                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4082                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4083                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
4084                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4085                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4086                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4087                 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4088         }
4089
4090         /* Set the tx_power_user_lmt to the lowest power level
4091          * this value will get overwritten by channel max power avg
4092          * from eeprom */
4093         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
4094
4095         ret = iwl_init_channel_map(priv);
4096         if (ret) {
4097                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4098                 goto err;
4099         }
4100
4101         ret = iwlcore_init_geos(priv);
4102         if (ret) {
4103                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4104                 goto err_free_channel_map;
4105         }
4106         iwl_init_hw_rates(priv, priv->ieee_rates);
4107
4108         return 0;
4109
4110 err_free_channel_map:
4111         iwl_free_channel_map(priv);
4112 err:
4113         return ret;
4114 }
4115
4116 static void iwl_uninit_drv(struct iwl_priv *priv)
4117 {
4118         iwl_calib_free_results(priv);
4119         iwlcore_free_geos(priv);
4120         iwl_free_channel_map(priv);
4121         kfree(priv->scan_cmd);
4122 }
4123
4124 static struct ieee80211_ops iwl_hw_ops = {
4125         .tx = iwl_mac_tx,
4126         .start = iwl_mac_start,
4127         .stop = iwl_mac_stop,
4128         .add_interface = iwl_mac_add_interface,
4129         .remove_interface = iwl_mac_remove_interface,
4130         .config = iwl_mac_config,
4131         .configure_filter = iwlagn_configure_filter,
4132         .set_key = iwl_mac_set_key,
4133         .update_tkip_key = iwl_mac_update_tkip_key,
4134         .conf_tx = iwl_mac_conf_tx,
4135         .reset_tsf = iwl_mac_reset_tsf,
4136         .bss_info_changed = iwl_bss_info_changed,
4137         .ampdu_action = iwl_mac_ampdu_action,
4138         .hw_scan = iwl_mac_hw_scan,
4139         .sta_notify = iwl_mac_sta_notify,
4140         .sta_add = iwlagn_mac_sta_add,
4141         .sta_remove = iwl_mac_sta_remove,
4142         .channel_switch = iwl_mac_channel_switch,
4143         .flush = iwl_mac_flush,
4144         .tx_last_beacon = iwl_mac_tx_last_beacon,
4145 };
4146
4147 static void iwl_hw_detect(struct iwl_priv *priv)
4148 {
4149         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4150         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4151         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
4152         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4153 }
4154
4155 static int iwl_set_hw_params(struct iwl_priv *priv)
4156 {
4157         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4158         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4159         if (priv->cfg->mod_params->amsdu_size_8K)
4160                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4161         else
4162                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4163
4164         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4165
4166         if (priv->cfg->mod_params->disable_11n)
4167                 priv->cfg->sku &= ~IWL_SKU_N;
4168
4169         /* Device-specific setup */
4170         return priv->cfg->ops->lib->set_hw_params(priv);
4171 }
4172
4173 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4174 {
4175         int err = 0, i;
4176         struct iwl_priv *priv;
4177         struct ieee80211_hw *hw;
4178         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4179         unsigned long flags;
4180         u16 pci_cmd, num_mac;
4181
4182         /************************
4183          * 1. Allocating HW data
4184          ************************/
4185
4186         /* Disabling hardware scan means that mac80211 will perform scans
4187          * "the hard way", rather than using device's scan. */
4188         if (cfg->mod_params->disable_hw_scan) {
4189                 if (iwl_debug_level & IWL_DL_INFO)
4190                         dev_printk(KERN_DEBUG, &(pdev->dev),
4191                                    "Disabling hw_scan\n");
4192                 iwl_hw_ops.hw_scan = NULL;
4193         }
4194
4195         hw = iwl_alloc_all(cfg, &iwl_hw_ops);
4196         if (!hw) {
4197                 err = -ENOMEM;
4198                 goto out;
4199         }
4200         priv = hw->priv;
4201         /* At this point both hw and priv are allocated. */
4202
4203         /*
4204          * The default context is always valid,
4205          * more may be discovered when firmware
4206          * is loaded.
4207          */
4208         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4209
4210         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4211                 priv->contexts[i].ctxid = i;
4212
4213         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4214         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4215         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4216         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4217         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4218         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4219         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 1);
4220
4221         SET_IEEE80211_DEV(hw, &pdev->dev);
4222
4223         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4224         priv->cfg = cfg;
4225         priv->pci_dev = pdev;
4226         priv->inta_mask = CSR_INI_SET_MASK;
4227
4228         /* is antenna coupling more than 35dB ? */
4229         priv->bt_ant_couple_ok =
4230                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4231                 true : false;
4232
4233         /* enable/disable bt channel announcement */
4234         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4235
4236         if (iwl_alloc_traffic_mem(priv))
4237                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4238
4239         /**************************
4240          * 2. Initializing PCI bus
4241          **************************/
4242         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4243                                 PCIE_LINK_STATE_CLKPM);
4244
4245         if (pci_enable_device(pdev)) {
4246                 err = -ENODEV;
4247                 goto out_ieee80211_free_hw;
4248         }
4249
4250         pci_set_master(pdev);
4251
4252         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4253         if (!err)
4254                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4255         if (err) {
4256                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4257                 if (!err)
4258                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4259                 /* both attempts failed: */
4260                 if (err) {
4261                         IWL_WARN(priv, "No suitable DMA available.\n");
4262                         goto out_pci_disable_device;
4263                 }
4264         }
4265
4266         err = pci_request_regions(pdev, DRV_NAME);
4267         if (err)
4268                 goto out_pci_disable_device;
4269
4270         pci_set_drvdata(pdev, priv);
4271
4272
4273         /***********************
4274          * 3. Read REV register
4275          ***********************/
4276         priv->hw_base = pci_iomap(pdev, 0, 0);
4277         if (!priv->hw_base) {
4278                 err = -ENODEV;
4279                 goto out_pci_release_regions;
4280         }
4281
4282         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4283                 (unsigned long long) pci_resource_len(pdev, 0));
4284         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4285
4286         /* these spin locks will be used in apm_ops.init and EEPROM access
4287          * we should init now
4288          */
4289         spin_lock_init(&priv->reg_lock);
4290         spin_lock_init(&priv->lock);
4291
4292         /*
4293          * stop and reset the on-board processor just in case it is in a
4294          * strange state ... like being left stranded by a primary kernel
4295          * and this is now the kdump kernel trying to start up
4296          */
4297         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4298
4299         iwl_hw_detect(priv);
4300         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4301                 priv->cfg->name, priv->hw_rev);
4302
4303         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4304          * PCI Tx retries from interfering with C3 CPU state */
4305         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4306
4307         iwl_prepare_card_hw(priv);
4308         if (!priv->hw_ready) {
4309                 IWL_WARN(priv, "Failed, HW not ready\n");
4310                 goto out_iounmap;
4311         }
4312
4313         /*****************
4314          * 4. Read EEPROM
4315          *****************/
4316         /* Read the EEPROM */
4317         err = iwl_eeprom_init(priv);
4318         if (err) {
4319                 IWL_ERR(priv, "Unable to init EEPROM\n");
4320                 goto out_iounmap;
4321         }
4322         err = iwl_eeprom_check_version(priv);
4323         if (err)
4324                 goto out_free_eeprom;
4325
4326         /* extract MAC Address */
4327         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4328         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4329         priv->hw->wiphy->addresses = priv->addresses;
4330         priv->hw->wiphy->n_addresses = 1;
4331         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4332         if (num_mac > 1) {
4333                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4334                        ETH_ALEN);
4335                 priv->addresses[1].addr[5]++;
4336                 priv->hw->wiphy->n_addresses++;
4337         }
4338
4339         /************************
4340          * 5. Setup HW constants
4341          ************************/
4342         if (iwl_set_hw_params(priv)) {
4343                 IWL_ERR(priv, "failed to set hw parameters\n");
4344                 goto out_free_eeprom;
4345         }
4346
4347         /*******************
4348          * 6. Setup priv
4349          *******************/
4350
4351         err = iwl_init_drv(priv);
4352         if (err)
4353                 goto out_free_eeprom;
4354         /* At this point both hw and priv are initialized. */
4355
4356         /********************
4357          * 7. Setup services
4358          ********************/
4359         spin_lock_irqsave(&priv->lock, flags);
4360         iwl_disable_interrupts(priv);
4361         spin_unlock_irqrestore(&priv->lock, flags);
4362
4363         pci_enable_msi(priv->pci_dev);
4364
4365         iwl_alloc_isr_ict(priv);
4366         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4367                           IRQF_SHARED, DRV_NAME, priv);
4368         if (err) {
4369                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4370                 goto out_disable_msi;
4371         }
4372
4373         iwl_setup_deferred_work(priv);
4374         iwl_setup_rx_handlers(priv);
4375
4376         /*********************************************
4377          * 8. Enable interrupts and read RFKILL state
4378          *********************************************/
4379
4380         /* enable interrupts if needed: hw bug w/a */
4381         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4382         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4383                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4384                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4385         }
4386
4387         iwl_enable_interrupts(priv);
4388
4389         /* If platform's RF_KILL switch is NOT set to KILL */
4390         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4391                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4392         else
4393                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4394
4395         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4396                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4397
4398         iwl_power_initialize(priv);
4399         iwl_tt_initialize(priv);
4400
4401         init_completion(&priv->_agn.firmware_loading_complete);
4402
4403         err = iwl_request_firmware(priv, true);
4404         if (err)
4405                 goto out_destroy_workqueue;
4406
4407         return 0;
4408
4409  out_destroy_workqueue:
4410         destroy_workqueue(priv->workqueue);
4411         priv->workqueue = NULL;
4412         free_irq(priv->pci_dev->irq, priv);
4413         iwl_free_isr_ict(priv);
4414  out_disable_msi:
4415         pci_disable_msi(priv->pci_dev);
4416         iwl_uninit_drv(priv);
4417  out_free_eeprom:
4418         iwl_eeprom_free(priv);
4419  out_iounmap:
4420         pci_iounmap(pdev, priv->hw_base);
4421  out_pci_release_regions:
4422         pci_set_drvdata(pdev, NULL);
4423         pci_release_regions(pdev);
4424  out_pci_disable_device:
4425         pci_disable_device(pdev);
4426  out_ieee80211_free_hw:
4427         iwl_free_traffic_mem(priv);
4428         ieee80211_free_hw(priv->hw);
4429  out:
4430         return err;
4431 }
4432
4433 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4434 {
4435         struct iwl_priv *priv = pci_get_drvdata(pdev);
4436         unsigned long flags;
4437
4438         if (!priv)
4439                 return;
4440
4441         wait_for_completion(&priv->_agn.firmware_loading_complete);
4442
4443         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4444
4445         iwl_dbgfs_unregister(priv);
4446         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4447
4448         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4449          * to be called and iwl_down since we are removing the device
4450          * we need to set STATUS_EXIT_PENDING bit.
4451          */
4452         set_bit(STATUS_EXIT_PENDING, &priv->status);
4453         if (priv->mac80211_registered) {
4454                 ieee80211_unregister_hw(priv->hw);
4455                 priv->mac80211_registered = 0;
4456         } else {
4457                 iwl_down(priv);
4458         }
4459
4460         /*
4461          * Make sure device is reset to low power before unloading driver.
4462          * This may be redundant with iwl_down(), but there are paths to
4463          * run iwl_down() without calling apm_ops.stop(), and there are
4464          * paths to avoid running iwl_down() at all before leaving driver.
4465          * This (inexpensive) call *makes sure* device is reset.
4466          */
4467         priv->cfg->ops->lib->apm_ops.stop(priv);
4468
4469         iwl_tt_exit(priv);
4470
4471         /* make sure we flush any pending irq or
4472          * tasklet for the driver
4473          */
4474         spin_lock_irqsave(&priv->lock, flags);
4475         iwl_disable_interrupts(priv);
4476         spin_unlock_irqrestore(&priv->lock, flags);
4477
4478         iwl_synchronize_irq(priv);
4479
4480         iwl_dealloc_ucode_pci(priv);
4481
4482         if (priv->rxq.bd)
4483                 iwlagn_rx_queue_free(priv, &priv->rxq);
4484         iwlagn_hw_txq_ctx_free(priv);
4485
4486         iwl_eeprom_free(priv);
4487
4488
4489         /*netif_stop_queue(dev); */
4490         flush_workqueue(priv->workqueue);
4491
4492         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4493          * priv->workqueue... so we can't take down the workqueue
4494          * until now... */
4495         destroy_workqueue(priv->workqueue);
4496         priv->workqueue = NULL;
4497         iwl_free_traffic_mem(priv);
4498
4499         free_irq(priv->pci_dev->irq, priv);
4500         pci_disable_msi(priv->pci_dev);
4501         pci_iounmap(pdev, priv->hw_base);
4502         pci_release_regions(pdev);
4503         pci_disable_device(pdev);
4504         pci_set_drvdata(pdev, NULL);
4505
4506         iwl_uninit_drv(priv);
4507
4508         iwl_free_isr_ict(priv);
4509
4510         if (priv->ibss_beacon)
4511                 dev_kfree_skb(priv->ibss_beacon);
4512
4513         ieee80211_free_hw(priv->hw);
4514 }
4515
4516
4517 /*****************************************************************************
4518  *
4519  * driver and module entry point
4520  *
4521  *****************************************************************************/
4522
4523 /* Hardware specific file defines the PCI IDs table for that hardware module */
4524 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4525 #ifdef CONFIG_IWL4965
4526         {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4527         {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4528 #endif /* CONFIG_IWL4965 */
4529 #ifdef CONFIG_IWL5000
4530 /* 5100 Series WiFi */
4531         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4532         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4533         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4534         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4535         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4536         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4537         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4538         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4539         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4540         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4541         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4542         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4543         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4544         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4545         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4546         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4547         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4548         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4549         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4550         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4551         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4552         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4553         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4554         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4555
4556 /* 5300 Series WiFi */
4557         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4558         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4559         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4560         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4561         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4562         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4563         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4564         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4565         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4566         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4567         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4568         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4569
4570 /* 5350 Series WiFi/WiMax */
4571         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4572         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4573         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4574
4575 /* 5150 Series Wifi/WiMax */
4576         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4577         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4578         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4579         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4580         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4581         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4582
4583         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4584         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4585         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4586         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4587
4588 /* 6x00 Series */
4589         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4590         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4591         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4592         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4593         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4594         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4595         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4596         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4597         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4598         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4599
4600 /* 6x00 Series Gen2a */
4601         {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4602         {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4603         {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
4604         {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4605         {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4606         {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4607         {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
4608         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4609         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4610         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4611         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4612         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4613         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4614         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
4615
4616 /* 6x00 Series Gen2b */
4617         {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4618         {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4619         {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4620         {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4621         {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4622         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4623         {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4624         {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4625         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4626         {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4627         {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
4628         {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4629         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4630         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4631         {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4632         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4633         {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4634         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4635         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4636         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4637         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4638         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4639         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4640         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4641         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4642         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4643         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4644         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
4645
4646 /* 6x50 WiFi/WiMax Series */
4647         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4648         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4649         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4650         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4651         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4652         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4653
4654 /* 6x50 WiFi/WiMax Series Gen2 */
4655         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4656         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4657         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4658         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4659         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4660         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4661
4662 /* 1000 Series WiFi */
4663         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4664         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4665         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4666         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4667         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4668         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4669         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4670         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4671         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4672         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4673         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4674         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4675 #endif /* CONFIG_IWL5000 */
4676
4677         {0}
4678 };
4679 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4680
4681 static struct pci_driver iwl_driver = {
4682         .name = DRV_NAME,
4683         .id_table = iwl_hw_card_ids,
4684         .probe = iwl_pci_probe,
4685         .remove = __devexit_p(iwl_pci_remove),
4686 #ifdef CONFIG_PM
4687         .suspend = iwl_pci_suspend,
4688         .resume = iwl_pci_resume,
4689 #endif
4690 };
4691
4692 static int __init iwl_init(void)
4693 {
4694
4695         int ret;
4696         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4697         pr_info(DRV_COPYRIGHT "\n");
4698
4699         ret = iwlagn_rate_control_register();
4700         if (ret) {
4701                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4702                 return ret;
4703         }
4704
4705         ret = pci_register_driver(&iwl_driver);
4706         if (ret) {
4707                 pr_err("Unable to initialize PCI module\n");
4708                 goto error_register;
4709         }
4710
4711         return ret;
4712
4713 error_register:
4714         iwlagn_rate_control_unregister();
4715         return ret;
4716 }
4717
4718 static void __exit iwl_exit(void)
4719 {
4720         pci_unregister_driver(&iwl_driver);
4721         iwlagn_rate_control_unregister();
4722 }
4723
4724 module_exit(iwl_exit);
4725 module_init(iwl_init);
4726
4727 #ifdef CONFIG_IWLWIFI_DEBUG
4728 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4729 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4730 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4731 MODULE_PARM_DESC(debug, "debug output mask");
4732 #endif
4733
4734 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4735 MODULE_PARM_DESC(swcrypto50,
4736                  "using crypto in software (default 0 [hardware]) (deprecated)");
4737 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4738 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4739 module_param_named(queues_num50,
4740                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4741 MODULE_PARM_DESC(queues_num50,
4742                  "number of hw queues in 50xx series (deprecated)");
4743 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4744 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4745 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4746 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4747 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4748 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4749 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4750                    int, S_IRUGO);
4751 MODULE_PARM_DESC(amsdu_size_8K50,
4752                  "enable 8K amsdu size in 50XX series (deprecated)");
4753 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4754                    int, S_IRUGO);
4755 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4756 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4757 MODULE_PARM_DESC(fw_restart50,
4758                  "restart firmware in case of error (deprecated)");
4759 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4760 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4761 module_param_named(
4762         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4763 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4764
4765 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4766                    S_IRUGO);
4767 MODULE_PARM_DESC(ucode_alternative,
4768                  "specify ucode alternative to use from ucode file");
4769
4770 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4771 MODULE_PARM_DESC(antenna_coupling,
4772                  "specify antenna coupling in dB (defualt: 0 dB)");
4773
4774 module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4775 MODULE_PARM_DESC(bt_ch_announce,
4776                  "Enable BT channel announcement mode (default: enable)");