iwlagn: verify specific ucode
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
4  *
5  * Portions of this file are derived from the ipw3945 project, as well
6  * as portions of the ieee80211 subsystem header files.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of version 2 of the GNU General Public License as
10  * published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc.,
19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20  *
21  * The full GNU General Public License is included in this distribution in the
22  * file called LICENSE.
23  *
24  * Contact Information:
25  *  Intel Linux Wireless <ilw@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
47
48 #include <net/mac80211.h>
49
50 #include <asm/div64.h>
51
52 #define DRV_NAME        "iwlagn"
53
54 #include "iwl-eeprom.h"
55 #include "iwl-dev.h"
56 #include "iwl-core.h"
57 #include "iwl-io.h"
58 #include "iwl-helpers.h"
59 #include "iwl-sta.h"
60 #include "iwl-agn-calib.h"
61 #include "iwl-agn.h"
62 #include "iwl-agn-led.h"
63
64
65 /******************************************************************************
66  *
67  * module boiler plate
68  *
69  ******************************************************************************/
70
71 /*
72  * module name, copyright, version, etc.
73  */
74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
75
76 #ifdef CONFIG_IWLWIFI_DEBUG
77 #define VD "d"
78 #else
79 #define VD
80 #endif
81
82 #define DRV_VERSION     IWLWIFI_VERSION VD
83
84
85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
86 MODULE_VERSION(DRV_VERSION);
87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
88 MODULE_LICENSE("GPL");
89
90 static int iwlagn_ant_coupling;
91 static bool iwlagn_bt_ch_announce = 1;
92
93 void iwl_update_chain_flags(struct iwl_priv *priv)
94 {
95         struct iwl_rxon_context *ctx;
96
97         if (priv->cfg->ops->hcmd->set_rxon_chain) {
98                 for_each_context(priv, ctx) {
99                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
100                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
101                                 iwlcore_commit_rxon(priv, ctx);
102                 }
103         }
104 }
105
106 static void iwl_clear_free_frames(struct iwl_priv *priv)
107 {
108         struct list_head *element;
109
110         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
111                        priv->frames_count);
112
113         while (!list_empty(&priv->free_frames)) {
114                 element = priv->free_frames.next;
115                 list_del(element);
116                 kfree(list_entry(element, struct iwl_frame, list));
117                 priv->frames_count--;
118         }
119
120         if (priv->frames_count) {
121                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
122                             priv->frames_count);
123                 priv->frames_count = 0;
124         }
125 }
126
127 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
128 {
129         struct iwl_frame *frame;
130         struct list_head *element;
131         if (list_empty(&priv->free_frames)) {
132                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
133                 if (!frame) {
134                         IWL_ERR(priv, "Could not allocate frame!\n");
135                         return NULL;
136                 }
137
138                 priv->frames_count++;
139                 return frame;
140         }
141
142         element = priv->free_frames.next;
143         list_del(element);
144         return list_entry(element, struct iwl_frame, list);
145 }
146
147 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
148 {
149         memset(frame, 0, sizeof(*frame));
150         list_add(&frame->list, &priv->free_frames);
151 }
152
153 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
154                                  struct ieee80211_hdr *hdr,
155                                  int left)
156 {
157         lockdep_assert_held(&priv->mutex);
158
159         if (!priv->beacon_skb)
160                 return 0;
161
162         if (priv->beacon_skb->len > left)
163                 return 0;
164
165         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
166
167         return priv->beacon_skb->len;
168 }
169
170 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
171 static void iwl_set_beacon_tim(struct iwl_priv *priv,
172                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
173                                u8 *beacon, u32 frame_size)
174 {
175         u16 tim_idx;
176         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
177
178         /*
179          * The index is relative to frame start but we start looking at the
180          * variable-length part of the beacon.
181          */
182         tim_idx = mgmt->u.beacon.variable - beacon;
183
184         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
185         while ((tim_idx < (frame_size - 2)) &&
186                         (beacon[tim_idx] != WLAN_EID_TIM))
187                 tim_idx += beacon[tim_idx+1] + 2;
188
189         /* If TIM field was found, set variables */
190         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
191                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
192                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
193         } else
194                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
195 }
196
197 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
198                                        struct iwl_frame *frame)
199 {
200         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
201         u32 frame_size;
202         u32 rate_flags;
203         u32 rate;
204         /*
205          * We have to set up the TX command, the TX Beacon command, and the
206          * beacon contents.
207          */
208
209         lockdep_assert_held(&priv->mutex);
210
211         if (!priv->beacon_ctx) {
212                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
213                 return 0;
214         }
215
216         /* Initialize memory */
217         tx_beacon_cmd = &frame->u.beacon;
218         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
219
220         /* Set up TX beacon contents */
221         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
222                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
223         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
224                 return 0;
225         if (!frame_size)
226                 return 0;
227
228         /* Set up TX command fields */
229         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
230         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
231         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
232         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
233                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
234
235         /* Set up TX beacon command fields */
236         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
237                            frame_size);
238
239         /* Set up packet rate and flags */
240         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
241         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
242                                               priv->hw_params.valid_tx_ant);
243         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
244         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
245                 rate_flags |= RATE_MCS_CCK_MSK;
246         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
247                         rate_flags);
248
249         return sizeof(*tx_beacon_cmd) + frame_size;
250 }
251
252 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
253 {
254         struct iwl_frame *frame;
255         unsigned int frame_size;
256         int rc;
257
258         frame = iwl_get_free_frame(priv);
259         if (!frame) {
260                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
261                           "command.\n");
262                 return -ENOMEM;
263         }
264
265         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
266         if (!frame_size) {
267                 IWL_ERR(priv, "Error configuring the beacon command\n");
268                 iwl_free_frame(priv, frame);
269                 return -EINVAL;
270         }
271
272         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
273                               &frame->u.cmd[0]);
274
275         iwl_free_frame(priv, frame);
276
277         return rc;
278 }
279
280 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
281 {
282         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
283
284         dma_addr_t addr = get_unaligned_le32(&tb->lo);
285         if (sizeof(dma_addr_t) > sizeof(u32))
286                 addr |=
287                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
288
289         return addr;
290 }
291
292 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
293 {
294         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
295
296         return le16_to_cpu(tb->hi_n_len) >> 4;
297 }
298
299 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
300                                   dma_addr_t addr, u16 len)
301 {
302         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
303         u16 hi_n_len = len << 4;
304
305         put_unaligned_le32(addr, &tb->lo);
306         if (sizeof(dma_addr_t) > sizeof(u32))
307                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
308
309         tb->hi_n_len = cpu_to_le16(hi_n_len);
310
311         tfd->num_tbs = idx + 1;
312 }
313
314 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
315 {
316         return tfd->num_tbs & 0x1f;
317 }
318
319 /**
320  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
321  * @priv - driver private data
322  * @txq - tx queue
323  *
324  * Does NOT advance any TFD circular buffer read/write indexes
325  * Does NOT free the TFD itself (which is within circular buffer)
326  */
327 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
328 {
329         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
330         struct iwl_tfd *tfd;
331         struct pci_dev *dev = priv->pci_dev;
332         int index = txq->q.read_ptr;
333         int i;
334         int num_tbs;
335
336         tfd = &tfd_tmp[index];
337
338         /* Sanity check on number of chunks */
339         num_tbs = iwl_tfd_get_num_tbs(tfd);
340
341         if (num_tbs >= IWL_NUM_OF_TBS) {
342                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
343                 /* @todo issue fatal error, it is quite serious situation */
344                 return;
345         }
346
347         /* Unmap tx_cmd */
348         if (num_tbs)
349                 pci_unmap_single(dev,
350                                 dma_unmap_addr(&txq->meta[index], mapping),
351                                 dma_unmap_len(&txq->meta[index], len),
352                                 PCI_DMA_BIDIRECTIONAL);
353
354         /* Unmap chunks, if any. */
355         for (i = 1; i < num_tbs; i++)
356                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
357                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
358
359         /* free SKB */
360         if (txq->txb) {
361                 struct sk_buff *skb;
362
363                 skb = txq->txb[txq->q.read_ptr].skb;
364
365                 /* can be called from irqs-disabled context */
366                 if (skb) {
367                         dev_kfree_skb_any(skb);
368                         txq->txb[txq->q.read_ptr].skb = NULL;
369                 }
370         }
371 }
372
373 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
374                                  struct iwl_tx_queue *txq,
375                                  dma_addr_t addr, u16 len,
376                                  u8 reset, u8 pad)
377 {
378         struct iwl_queue *q;
379         struct iwl_tfd *tfd, *tfd_tmp;
380         u32 num_tbs;
381
382         q = &txq->q;
383         tfd_tmp = (struct iwl_tfd *)txq->tfds;
384         tfd = &tfd_tmp[q->write_ptr];
385
386         if (reset)
387                 memset(tfd, 0, sizeof(*tfd));
388
389         num_tbs = iwl_tfd_get_num_tbs(tfd);
390
391         /* Each TFD can point to a maximum 20 Tx buffers */
392         if (num_tbs >= IWL_NUM_OF_TBS) {
393                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
394                           IWL_NUM_OF_TBS);
395                 return -EINVAL;
396         }
397
398         BUG_ON(addr & ~DMA_BIT_MASK(36));
399         if (unlikely(addr & ~IWL_TX_DMA_MASK))
400                 IWL_ERR(priv, "Unaligned address = %llx\n",
401                           (unsigned long long)addr);
402
403         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
404
405         return 0;
406 }
407
408 /*
409  * Tell nic where to find circular buffer of Tx Frame Descriptors for
410  * given Tx queue, and enable the DMA channel used for that queue.
411  *
412  * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
413  * channels supported in hardware.
414  */
415 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
416                          struct iwl_tx_queue *txq)
417 {
418         int txq_id = txq->q.id;
419
420         /* Circular buffer (TFD queue in DRAM) physical base address */
421         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
422                              txq->q.dma_addr >> 8);
423
424         return 0;
425 }
426
427 static void iwl_bg_beacon_update(struct work_struct *work)
428 {
429         struct iwl_priv *priv =
430                 container_of(work, struct iwl_priv, beacon_update);
431         struct sk_buff *beacon;
432
433         mutex_lock(&priv->mutex);
434         if (!priv->beacon_ctx) {
435                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
436                 goto out;
437         }
438
439         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
440                 /*
441                  * The ucode will send beacon notifications even in
442                  * IBSS mode, but we don't want to process them. But
443                  * we need to defer the type check to here due to
444                  * requiring locking around the beacon_ctx access.
445                  */
446                 goto out;
447         }
448
449         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
450         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
451         if (!beacon) {
452                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
453                 goto out;
454         }
455
456         /* new beacon skb is allocated every time; dispose previous.*/
457         dev_kfree_skb(priv->beacon_skb);
458
459         priv->beacon_skb = beacon;
460
461         iwlagn_send_beacon_cmd(priv);
462  out:
463         mutex_unlock(&priv->mutex);
464 }
465
466 static void iwl_bg_bt_runtime_config(struct work_struct *work)
467 {
468         struct iwl_priv *priv =
469                 container_of(work, struct iwl_priv, bt_runtime_config);
470
471         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
472                 return;
473
474         /* dont send host command if rf-kill is on */
475         if (!iwl_is_ready_rf(priv))
476                 return;
477         priv->cfg->ops->hcmd->send_bt_config(priv);
478 }
479
480 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
481 {
482         struct iwl_priv *priv =
483                 container_of(work, struct iwl_priv, bt_full_concurrency);
484         struct iwl_rxon_context *ctx;
485
486         mutex_lock(&priv->mutex);
487
488         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
489                 goto out;
490
491         /* dont send host command if rf-kill is on */
492         if (!iwl_is_ready_rf(priv))
493                 goto out;
494
495         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
496                        priv->bt_full_concurrent ?
497                        "full concurrency" : "3-wire");
498
499         /*
500          * LQ & RXON updated cmds must be sent before BT Config cmd
501          * to avoid 3-wire collisions
502          */
503         for_each_context(priv, ctx) {
504                 if (priv->cfg->ops->hcmd->set_rxon_chain)
505                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
506                 iwlcore_commit_rxon(priv, ctx);
507         }
508
509         priv->cfg->ops->hcmd->send_bt_config(priv);
510 out:
511         mutex_unlock(&priv->mutex);
512 }
513
514 /**
515  * iwl_bg_statistics_periodic - Timer callback to queue statistics
516  *
517  * This callback is provided in order to send a statistics request.
518  *
519  * This timer function is continually reset to execute within
520  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
521  * was received.  We need to ensure we receive the statistics in order
522  * to update the temperature used for calibrating the TXPOWER.
523  */
524 static void iwl_bg_statistics_periodic(unsigned long data)
525 {
526         struct iwl_priv *priv = (struct iwl_priv *)data;
527
528         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
529                 return;
530
531         /* dont send host command if rf-kill is on */
532         if (!iwl_is_ready_rf(priv))
533                 return;
534
535         iwl_send_statistics_request(priv, CMD_ASYNC, false);
536 }
537
538
539 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
540                                         u32 start_idx, u32 num_events,
541                                         u32 mode)
542 {
543         u32 i;
544         u32 ptr;        /* SRAM byte address of log data */
545         u32 ev, time, data; /* event log data */
546         unsigned long reg_flags;
547
548         if (mode == 0)
549                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
550         else
551                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
552
553         /* Make sure device is powered up for SRAM reads */
554         spin_lock_irqsave(&priv->reg_lock, reg_flags);
555         if (iwl_grab_nic_access(priv)) {
556                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
557                 return;
558         }
559
560         /* Set starting address; reads will auto-increment */
561         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
562         rmb();
563
564         /*
565          * "time" is actually "data" for mode 0 (no timestamp).
566          * place event id # at far right for easier visual parsing.
567          */
568         for (i = 0; i < num_events; i++) {
569                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
570                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
571                 if (mode == 0) {
572                         trace_iwlwifi_dev_ucode_cont_event(priv,
573                                                         0, time, ev);
574                 } else {
575                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
576                         trace_iwlwifi_dev_ucode_cont_event(priv,
577                                                 time, data, ev);
578                 }
579         }
580         /* Allow device to power down */
581         iwl_release_nic_access(priv);
582         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
583 }
584
585 static void iwl_continuous_event_trace(struct iwl_priv *priv)
586 {
587         u32 capacity;   /* event log capacity in # entries */
588         u32 base;       /* SRAM byte address of event log header */
589         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
590         u32 num_wraps;  /* # times uCode wrapped to top of log */
591         u32 next_entry; /* index of next entry to be written by uCode */
592
593         if (priv->ucode_type == UCODE_INIT)
594                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
595         else
596                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
597         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
598                 capacity = iwl_read_targ_mem(priv, base);
599                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
600                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
601                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
602         } else
603                 return;
604
605         if (num_wraps == priv->event_log.num_wraps) {
606                 iwl_print_cont_event_trace(priv,
607                                        base, priv->event_log.next_entry,
608                                        next_entry - priv->event_log.next_entry,
609                                        mode);
610                 priv->event_log.non_wraps_count++;
611         } else {
612                 if ((num_wraps - priv->event_log.num_wraps) > 1)
613                         priv->event_log.wraps_more_count++;
614                 else
615                         priv->event_log.wraps_once_count++;
616                 trace_iwlwifi_dev_ucode_wrap_event(priv,
617                                 num_wraps - priv->event_log.num_wraps,
618                                 next_entry, priv->event_log.next_entry);
619                 if (next_entry < priv->event_log.next_entry) {
620                         iwl_print_cont_event_trace(priv, base,
621                                priv->event_log.next_entry,
622                                capacity - priv->event_log.next_entry,
623                                mode);
624
625                         iwl_print_cont_event_trace(priv, base, 0,
626                                 next_entry, mode);
627                 } else {
628                         iwl_print_cont_event_trace(priv, base,
629                                next_entry, capacity - next_entry,
630                                mode);
631
632                         iwl_print_cont_event_trace(priv, base, 0,
633                                 next_entry, mode);
634                 }
635         }
636         priv->event_log.num_wraps = num_wraps;
637         priv->event_log.next_entry = next_entry;
638 }
639
640 /**
641  * iwl_bg_ucode_trace - Timer callback to log ucode event
642  *
643  * The timer is continually set to execute every
644  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
645  * this function is to perform continuous uCode event logging operation
646  * if enabled
647  */
648 static void iwl_bg_ucode_trace(unsigned long data)
649 {
650         struct iwl_priv *priv = (struct iwl_priv *)data;
651
652         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
653                 return;
654
655         if (priv->event_log.ucode_trace) {
656                 iwl_continuous_event_trace(priv);
657                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
658                 mod_timer(&priv->ucode_trace,
659                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
660         }
661 }
662
663 static void iwl_bg_tx_flush(struct work_struct *work)
664 {
665         struct iwl_priv *priv =
666                 container_of(work, struct iwl_priv, tx_flush);
667
668         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
669                 return;
670
671         /* do nothing if rf-kill is on */
672         if (!iwl_is_ready_rf(priv))
673                 return;
674
675         if (priv->cfg->ops->lib->txfifo_flush) {
676                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
677                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
678         }
679 }
680
681 /**
682  * iwl_rx_handle - Main entry function for receiving responses from uCode
683  *
684  * Uses the priv->rx_handlers callback function array to invoke
685  * the appropriate handlers, including command responses,
686  * frame-received notifications, and other notifications.
687  */
688 static void iwl_rx_handle(struct iwl_priv *priv)
689 {
690         struct iwl_rx_mem_buffer *rxb;
691         struct iwl_rx_packet *pkt;
692         struct iwl_rx_queue *rxq = &priv->rxq;
693         u32 r, i;
694         int reclaim;
695         unsigned long flags;
696         u8 fill_rx = 0;
697         u32 count = 8;
698         int total_empty;
699
700         /* uCode's read index (stored in shared DRAM) indicates the last Rx
701          * buffer that the driver may process (last buffer filled by ucode). */
702         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
703         i = rxq->read;
704
705         /* Rx interrupt, but nothing sent from uCode */
706         if (i == r)
707                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
708
709         /* calculate total frames need to be restock after handling RX */
710         total_empty = r - rxq->write_actual;
711         if (total_empty < 0)
712                 total_empty += RX_QUEUE_SIZE;
713
714         if (total_empty > (RX_QUEUE_SIZE / 2))
715                 fill_rx = 1;
716
717         while (i != r) {
718                 int len;
719
720                 rxb = rxq->queue[i];
721
722                 /* If an RXB doesn't have a Rx queue slot associated with it,
723                  * then a bug has been introduced in the queue refilling
724                  * routines -- catch it here */
725                 BUG_ON(rxb == NULL);
726
727                 rxq->queue[i] = NULL;
728
729                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
730                                PAGE_SIZE << priv->hw_params.rx_page_order,
731                                PCI_DMA_FROMDEVICE);
732                 pkt = rxb_addr(rxb);
733
734                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
735                 len += sizeof(u32); /* account for status word */
736                 trace_iwlwifi_dev_rx(priv, pkt, len);
737
738                 /* Reclaim a command buffer only if this packet is a response
739                  *   to a (driver-originated) command.
740                  * If the packet (e.g. Rx frame) originated from uCode,
741                  *   there is no command buffer to reclaim.
742                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
743                  *   but apparently a few don't get set; catch them here. */
744                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
745                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
746                         (pkt->hdr.cmd != REPLY_RX) &&
747                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
748                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
749                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
750                         (pkt->hdr.cmd != REPLY_TX);
751
752                 /*
753                  * Do the notification wait before RX handlers so
754                  * even if the RX handler consumes the RXB we have
755                  * access to it in the notification wait entry.
756                  */
757                 if (!list_empty(&priv->_agn.notif_waits)) {
758                         struct iwl_notification_wait *w;
759
760                         spin_lock(&priv->_agn.notif_wait_lock);
761                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
762                                 if (w->cmd == pkt->hdr.cmd) {
763                                         w->triggered = true;
764                                         if (w->fn)
765                                                 w->fn(priv, pkt);
766                                 }
767                         }
768                         spin_unlock(&priv->_agn.notif_wait_lock);
769
770                         wake_up_all(&priv->_agn.notif_waitq);
771                 }
772
773                 /* Based on type of command response or notification,
774                  *   handle those that need handling via function in
775                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
776                 if (priv->rx_handlers[pkt->hdr.cmd]) {
777                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
778                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
779                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
780                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
781                 } else {
782                         /* No handling needed */
783                         IWL_DEBUG_RX(priv,
784                                 "r %d i %d No handler needed for %s, 0x%02x\n",
785                                 r, i, get_cmd_string(pkt->hdr.cmd),
786                                 pkt->hdr.cmd);
787                 }
788
789                 /*
790                  * XXX: After here, we should always check rxb->page
791                  * against NULL before touching it or its virtual
792                  * memory (pkt). Because some rx_handler might have
793                  * already taken or freed the pages.
794                  */
795
796                 if (reclaim) {
797                         /* Invoke any callbacks, transfer the buffer to caller,
798                          * and fire off the (possibly) blocking iwl_send_cmd()
799                          * as we reclaim the driver command queue */
800                         if (rxb->page)
801                                 iwl_tx_cmd_complete(priv, rxb);
802                         else
803                                 IWL_WARN(priv, "Claim null rxb?\n");
804                 }
805
806                 /* Reuse the page if possible. For notification packets and
807                  * SKBs that fail to Rx correctly, add them back into the
808                  * rx_free list for reuse later. */
809                 spin_lock_irqsave(&rxq->lock, flags);
810                 if (rxb->page != NULL) {
811                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
812                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
813                                 PCI_DMA_FROMDEVICE);
814                         list_add_tail(&rxb->list, &rxq->rx_free);
815                         rxq->free_count++;
816                 } else
817                         list_add_tail(&rxb->list, &rxq->rx_used);
818
819                 spin_unlock_irqrestore(&rxq->lock, flags);
820
821                 i = (i + 1) & RX_QUEUE_MASK;
822                 /* If there are a lot of unused frames,
823                  * restock the Rx queue so ucode wont assert. */
824                 if (fill_rx) {
825                         count++;
826                         if (count >= 8) {
827                                 rxq->read = i;
828                                 iwlagn_rx_replenish_now(priv);
829                                 count = 0;
830                         }
831                 }
832         }
833
834         /* Backtrack one entry */
835         rxq->read = i;
836         if (fill_rx)
837                 iwlagn_rx_replenish_now(priv);
838         else
839                 iwlagn_rx_queue_restock(priv);
840 }
841
842 /* call this function to flush any scheduled tasklet */
843 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
844 {
845         /* wait to make sure we flush pending tasklet*/
846         synchronize_irq(priv->pci_dev->irq);
847         tasklet_kill(&priv->irq_tasklet);
848 }
849
850 /* tasklet for iwlagn interrupt */
851 static void iwl_irq_tasklet(struct iwl_priv *priv)
852 {
853         u32 inta = 0;
854         u32 handled = 0;
855         unsigned long flags;
856         u32 i;
857 #ifdef CONFIG_IWLWIFI_DEBUG
858         u32 inta_mask;
859 #endif
860
861         spin_lock_irqsave(&priv->lock, flags);
862
863         /* Ack/clear/reset pending uCode interrupts.
864          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
865          */
866         /* There is a hardware bug in the interrupt mask function that some
867          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
868          * they are disabled in the CSR_INT_MASK register. Furthermore the
869          * ICT interrupt handling mechanism has another bug that might cause
870          * these unmasked interrupts fail to be detected. We workaround the
871          * hardware bugs here by ACKing all the possible interrupts so that
872          * interrupt coalescing can still be achieved.
873          */
874         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
875
876         inta = priv->_agn.inta;
877
878 #ifdef CONFIG_IWLWIFI_DEBUG
879         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
880                 /* just for debug */
881                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
882                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
883                                 inta, inta_mask);
884         }
885 #endif
886
887         spin_unlock_irqrestore(&priv->lock, flags);
888
889         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
890         priv->_agn.inta = 0;
891
892         /* Now service all interrupt bits discovered above. */
893         if (inta & CSR_INT_BIT_HW_ERR) {
894                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
895
896                 /* Tell the device to stop sending interrupts */
897                 iwl_disable_interrupts(priv);
898
899                 priv->isr_stats.hw++;
900                 iwl_irq_handle_error(priv);
901
902                 handled |= CSR_INT_BIT_HW_ERR;
903
904                 return;
905         }
906
907 #ifdef CONFIG_IWLWIFI_DEBUG
908         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
909                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
910                 if (inta & CSR_INT_BIT_SCD) {
911                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
912                                       "the frame/frames.\n");
913                         priv->isr_stats.sch++;
914                 }
915
916                 /* Alive notification via Rx interrupt will do the real work */
917                 if (inta & CSR_INT_BIT_ALIVE) {
918                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
919                         priv->isr_stats.alive++;
920                 }
921         }
922 #endif
923         /* Safely ignore these bits for debug checks below */
924         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
925
926         /* HW RF KILL switch toggled */
927         if (inta & CSR_INT_BIT_RF_KILL) {
928                 int hw_rf_kill = 0;
929                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
930                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
931                         hw_rf_kill = 1;
932
933                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
934                                 hw_rf_kill ? "disable radio" : "enable radio");
935
936                 priv->isr_stats.rfkill++;
937
938                 /* driver only loads ucode once setting the interface up.
939                  * the driver allows loading the ucode even if the radio
940                  * is killed. Hence update the killswitch state here. The
941                  * rfkill handler will care about restarting if needed.
942                  */
943                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
944                         if (hw_rf_kill)
945                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
946                         else
947                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
948                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
949                 }
950
951                 handled |= CSR_INT_BIT_RF_KILL;
952         }
953
954         /* Chip got too hot and stopped itself */
955         if (inta & CSR_INT_BIT_CT_KILL) {
956                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
957                 priv->isr_stats.ctkill++;
958                 handled |= CSR_INT_BIT_CT_KILL;
959         }
960
961         /* Error detected by uCode */
962         if (inta & CSR_INT_BIT_SW_ERR) {
963                 IWL_ERR(priv, "Microcode SW error detected. "
964                         " Restarting 0x%X.\n", inta);
965                 priv->isr_stats.sw++;
966                 iwl_irq_handle_error(priv);
967                 handled |= CSR_INT_BIT_SW_ERR;
968         }
969
970         /* uCode wakes up after power-down sleep */
971         if (inta & CSR_INT_BIT_WAKEUP) {
972                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
973                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
974                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
975                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
976
977                 priv->isr_stats.wakeup++;
978
979                 handled |= CSR_INT_BIT_WAKEUP;
980         }
981
982         /* All uCode command responses, including Tx command responses,
983          * Rx "responses" (frame-received notification), and other
984          * notifications from uCode come through here*/
985         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
986                         CSR_INT_BIT_RX_PERIODIC)) {
987                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
988                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
989                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
990                         iwl_write32(priv, CSR_FH_INT_STATUS,
991                                         CSR_FH_INT_RX_MASK);
992                 }
993                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
994                         handled |= CSR_INT_BIT_RX_PERIODIC;
995                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
996                 }
997                 /* Sending RX interrupt require many steps to be done in the
998                  * the device:
999                  * 1- write interrupt to current index in ICT table.
1000                  * 2- dma RX frame.
1001                  * 3- update RX shared data to indicate last write index.
1002                  * 4- send interrupt.
1003                  * This could lead to RX race, driver could receive RX interrupt
1004                  * but the shared data changes does not reflect this;
1005                  * periodic interrupt will detect any dangling Rx activity.
1006                  */
1007
1008                 /* Disable periodic interrupt; we use it as just a one-shot. */
1009                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1010                             CSR_INT_PERIODIC_DIS);
1011                 iwl_rx_handle(priv);
1012
1013                 /*
1014                  * Enable periodic interrupt in 8 msec only if we received
1015                  * real RX interrupt (instead of just periodic int), to catch
1016                  * any dangling Rx interrupt.  If it was just the periodic
1017                  * interrupt, there was no dangling Rx activity, and no need
1018                  * to extend the periodic interrupt; one-shot is enough.
1019                  */
1020                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1021                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1022                                     CSR_INT_PERIODIC_ENA);
1023
1024                 priv->isr_stats.rx++;
1025         }
1026
1027         /* This "Tx" DMA channel is used only for loading uCode */
1028         if (inta & CSR_INT_BIT_FH_TX) {
1029                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1030                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1031                 priv->isr_stats.tx++;
1032                 handled |= CSR_INT_BIT_FH_TX;
1033                 /* Wake up uCode load routine, now that load is complete */
1034                 priv->ucode_write_complete = 1;
1035                 wake_up_interruptible(&priv->wait_command_queue);
1036         }
1037
1038         if (inta & ~handled) {
1039                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1040                 priv->isr_stats.unhandled++;
1041         }
1042
1043         if (inta & ~(priv->inta_mask)) {
1044                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1045                          inta & ~priv->inta_mask);
1046         }
1047
1048         /* Re-enable all interrupts */
1049         /* only Re-enable if disabled by irq */
1050         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1051                 iwl_enable_interrupts(priv);
1052         /* Re-enable RF_KILL if it occurred */
1053         else if (handled & CSR_INT_BIT_RF_KILL)
1054                 iwl_enable_rfkill_int(priv);
1055 }
1056
1057 /*****************************************************************************
1058  *
1059  * sysfs attributes
1060  *
1061  *****************************************************************************/
1062
1063 #ifdef CONFIG_IWLWIFI_DEBUG
1064
1065 /*
1066  * The following adds a new attribute to the sysfs representation
1067  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1068  * used for controlling the debug level.
1069  *
1070  * See the level definitions in iwl for details.
1071  *
1072  * The debug_level being managed using sysfs below is a per device debug
1073  * level that is used instead of the global debug level if it (the per
1074  * device debug level) is set.
1075  */
1076 static ssize_t show_debug_level(struct device *d,
1077                                 struct device_attribute *attr, char *buf)
1078 {
1079         struct iwl_priv *priv = dev_get_drvdata(d);
1080         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1081 }
1082 static ssize_t store_debug_level(struct device *d,
1083                                 struct device_attribute *attr,
1084                                  const char *buf, size_t count)
1085 {
1086         struct iwl_priv *priv = dev_get_drvdata(d);
1087         unsigned long val;
1088         int ret;
1089
1090         ret = strict_strtoul(buf, 0, &val);
1091         if (ret)
1092                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1093         else {
1094                 priv->debug_level = val;
1095                 if (iwl_alloc_traffic_mem(priv))
1096                         IWL_ERR(priv,
1097                                 "Not enough memory to generate traffic log\n");
1098         }
1099         return strnlen(buf, count);
1100 }
1101
1102 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1103                         show_debug_level, store_debug_level);
1104
1105
1106 #endif /* CONFIG_IWLWIFI_DEBUG */
1107
1108
1109 static ssize_t show_temperature(struct device *d,
1110                                 struct device_attribute *attr, char *buf)
1111 {
1112         struct iwl_priv *priv = dev_get_drvdata(d);
1113
1114         if (!iwl_is_alive(priv))
1115                 return -EAGAIN;
1116
1117         return sprintf(buf, "%d\n", priv->temperature);
1118 }
1119
1120 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1121
1122 static ssize_t show_tx_power(struct device *d,
1123                              struct device_attribute *attr, char *buf)
1124 {
1125         struct iwl_priv *priv = dev_get_drvdata(d);
1126
1127         if (!iwl_is_ready_rf(priv))
1128                 return sprintf(buf, "off\n");
1129         else
1130                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1131 }
1132
1133 static ssize_t store_tx_power(struct device *d,
1134                               struct device_attribute *attr,
1135                               const char *buf, size_t count)
1136 {
1137         struct iwl_priv *priv = dev_get_drvdata(d);
1138         unsigned long val;
1139         int ret;
1140
1141         ret = strict_strtoul(buf, 10, &val);
1142         if (ret)
1143                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1144         else {
1145                 ret = iwl_set_tx_power(priv, val, false);
1146                 if (ret)
1147                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1148                                 ret);
1149                 else
1150                         ret = count;
1151         }
1152         return ret;
1153 }
1154
1155 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1156
1157 static struct attribute *iwl_sysfs_entries[] = {
1158         &dev_attr_temperature.attr,
1159         &dev_attr_tx_power.attr,
1160 #ifdef CONFIG_IWLWIFI_DEBUG
1161         &dev_attr_debug_level.attr,
1162 #endif
1163         NULL
1164 };
1165
1166 static struct attribute_group iwl_attribute_group = {
1167         .name = NULL,           /* put in device directory */
1168         .attrs = iwl_sysfs_entries,
1169 };
1170
1171 /******************************************************************************
1172  *
1173  * uCode download functions
1174  *
1175  ******************************************************************************/
1176
1177 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1178 {
1179         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1180         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1181         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1182         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1183         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1184         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1185 }
1186
1187 static void iwl_nic_start(struct iwl_priv *priv)
1188 {
1189         /* Remove all resets to allow NIC to operate */
1190         iwl_write32(priv, CSR_RESET, 0);
1191 }
1192
1193 struct iwlagn_ucode_capabilities {
1194         u32 max_probe_length;
1195         u32 standard_phy_calibration_size;
1196         bool pan;
1197 };
1198
1199 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1200 static int iwl_mac_setup_register(struct iwl_priv *priv,
1201                                   struct iwlagn_ucode_capabilities *capa);
1202
1203 #define UCODE_EXPERIMENTAL_INDEX        100
1204 #define UCODE_EXPERIMENTAL_TAG          "exp"
1205
1206 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1207 {
1208         const char *name_pre = priv->cfg->fw_name_pre;
1209         char tag[8];
1210
1211         if (first) {
1212 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1213                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1214                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1215         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1216 #endif
1217                 priv->fw_index = priv->cfg->ucode_api_max;
1218                 sprintf(tag, "%d", priv->fw_index);
1219         } else {
1220                 priv->fw_index--;
1221                 sprintf(tag, "%d", priv->fw_index);
1222         }
1223
1224         if (priv->fw_index < priv->cfg->ucode_api_min) {
1225                 IWL_ERR(priv, "no suitable firmware found!\n");
1226                 return -ENOENT;
1227         }
1228
1229         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1230
1231         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1232                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1233                                 ? "EXPERIMENTAL " : "",
1234                        priv->firmware_name);
1235
1236         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1237                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1238                                        iwl_ucode_callback);
1239 }
1240
1241 struct iwlagn_firmware_pieces {
1242         const void *inst, *data, *init, *init_data, *boot;
1243         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1244
1245         u32 build;
1246
1247         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1248         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1249 };
1250
1251 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1252                                        const struct firmware *ucode_raw,
1253                                        struct iwlagn_firmware_pieces *pieces)
1254 {
1255         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1256         u32 api_ver, hdr_size;
1257         const u8 *src;
1258
1259         priv->ucode_ver = le32_to_cpu(ucode->ver);
1260         api_ver = IWL_UCODE_API(priv->ucode_ver);
1261
1262         switch (api_ver) {
1263         default:
1264                 hdr_size = 28;
1265                 if (ucode_raw->size < hdr_size) {
1266                         IWL_ERR(priv, "File size too small!\n");
1267                         return -EINVAL;
1268                 }
1269                 pieces->build = le32_to_cpu(ucode->u.v2.build);
1270                 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1271                 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1272                 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1273                 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1274                 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1275                 src = ucode->u.v2.data;
1276                 break;
1277         case 0:
1278         case 1:
1279         case 2:
1280                 hdr_size = 24;
1281                 if (ucode_raw->size < hdr_size) {
1282                         IWL_ERR(priv, "File size too small!\n");
1283                         return -EINVAL;
1284                 }
1285                 pieces->build = 0;
1286                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1287                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1288                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1289                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1290                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1291                 src = ucode->u.v1.data;
1292                 break;
1293         }
1294
1295         /* Verify size of file vs. image size info in file's header */
1296         if (ucode_raw->size != hdr_size + pieces->inst_size +
1297                                 pieces->data_size + pieces->init_size +
1298                                 pieces->init_data_size + pieces->boot_size) {
1299
1300                 IWL_ERR(priv,
1301                         "uCode file size %d does not match expected size\n",
1302                         (int)ucode_raw->size);
1303                 return -EINVAL;
1304         }
1305
1306         pieces->inst = src;
1307         src += pieces->inst_size;
1308         pieces->data = src;
1309         src += pieces->data_size;
1310         pieces->init = src;
1311         src += pieces->init_size;
1312         pieces->init_data = src;
1313         src += pieces->init_data_size;
1314         pieces->boot = src;
1315         src += pieces->boot_size;
1316
1317         return 0;
1318 }
1319
1320 static int iwlagn_wanted_ucode_alternative = 1;
1321
1322 static int iwlagn_load_firmware(struct iwl_priv *priv,
1323                                 const struct firmware *ucode_raw,
1324                                 struct iwlagn_firmware_pieces *pieces,
1325                                 struct iwlagn_ucode_capabilities *capa)
1326 {
1327         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1328         struct iwl_ucode_tlv *tlv;
1329         size_t len = ucode_raw->size;
1330         const u8 *data;
1331         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1332         u64 alternatives;
1333         u32 tlv_len;
1334         enum iwl_ucode_tlv_type tlv_type;
1335         const u8 *tlv_data;
1336
1337         if (len < sizeof(*ucode)) {
1338                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1339                 return -EINVAL;
1340         }
1341
1342         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1343                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1344                         le32_to_cpu(ucode->magic));
1345                 return -EINVAL;
1346         }
1347
1348         /*
1349          * Check which alternatives are present, and "downgrade"
1350          * when the chosen alternative is not present, warning
1351          * the user when that happens. Some files may not have
1352          * any alternatives, so don't warn in that case.
1353          */
1354         alternatives = le64_to_cpu(ucode->alternatives);
1355         tmp = wanted_alternative;
1356         if (wanted_alternative > 63)
1357                 wanted_alternative = 63;
1358         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1359                 wanted_alternative--;
1360         if (wanted_alternative && wanted_alternative != tmp)
1361                 IWL_WARN(priv,
1362                          "uCode alternative %d not available, choosing %d\n",
1363                          tmp, wanted_alternative);
1364
1365         priv->ucode_ver = le32_to_cpu(ucode->ver);
1366         pieces->build = le32_to_cpu(ucode->build);
1367         data = ucode->data;
1368
1369         len -= sizeof(*ucode);
1370
1371         while (len >= sizeof(*tlv)) {
1372                 u16 tlv_alt;
1373
1374                 len -= sizeof(*tlv);
1375                 tlv = (void *)data;
1376
1377                 tlv_len = le32_to_cpu(tlv->length);
1378                 tlv_type = le16_to_cpu(tlv->type);
1379                 tlv_alt = le16_to_cpu(tlv->alternative);
1380                 tlv_data = tlv->data;
1381
1382                 if (len < tlv_len) {
1383                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1384                                 len, tlv_len);
1385                         return -EINVAL;
1386                 }
1387                 len -= ALIGN(tlv_len, 4);
1388                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1389
1390                 /*
1391                  * Alternative 0 is always valid.
1392                  *
1393                  * Skip alternative TLVs that are not selected.
1394                  */
1395                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1396                         continue;
1397
1398                 switch (tlv_type) {
1399                 case IWL_UCODE_TLV_INST:
1400                         pieces->inst = tlv_data;
1401                         pieces->inst_size = tlv_len;
1402                         break;
1403                 case IWL_UCODE_TLV_DATA:
1404                         pieces->data = tlv_data;
1405                         pieces->data_size = tlv_len;
1406                         break;
1407                 case IWL_UCODE_TLV_INIT:
1408                         pieces->init = tlv_data;
1409                         pieces->init_size = tlv_len;
1410                         break;
1411                 case IWL_UCODE_TLV_INIT_DATA:
1412                         pieces->init_data = tlv_data;
1413                         pieces->init_data_size = tlv_len;
1414                         break;
1415                 case IWL_UCODE_TLV_BOOT:
1416                         pieces->boot = tlv_data;
1417                         pieces->boot_size = tlv_len;
1418                         break;
1419                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1420                         if (tlv_len != sizeof(u32))
1421                                 goto invalid_tlv_len;
1422                         capa->max_probe_length =
1423                                         le32_to_cpup((__le32 *)tlv_data);
1424                         break;
1425                 case IWL_UCODE_TLV_PAN:
1426                         if (tlv_len)
1427                                 goto invalid_tlv_len;
1428                         capa->pan = true;
1429                         break;
1430                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1431                         if (tlv_len != sizeof(u32))
1432                                 goto invalid_tlv_len;
1433                         pieces->init_evtlog_ptr =
1434                                         le32_to_cpup((__le32 *)tlv_data);
1435                         break;
1436                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1437                         if (tlv_len != sizeof(u32))
1438                                 goto invalid_tlv_len;
1439                         pieces->init_evtlog_size =
1440                                         le32_to_cpup((__le32 *)tlv_data);
1441                         break;
1442                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1443                         if (tlv_len != sizeof(u32))
1444                                 goto invalid_tlv_len;
1445                         pieces->init_errlog_ptr =
1446                                         le32_to_cpup((__le32 *)tlv_data);
1447                         break;
1448                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1449                         if (tlv_len != sizeof(u32))
1450                                 goto invalid_tlv_len;
1451                         pieces->inst_evtlog_ptr =
1452                                         le32_to_cpup((__le32 *)tlv_data);
1453                         break;
1454                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1455                         if (tlv_len != sizeof(u32))
1456                                 goto invalid_tlv_len;
1457                         pieces->inst_evtlog_size =
1458                                         le32_to_cpup((__le32 *)tlv_data);
1459                         break;
1460                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1461                         if (tlv_len != sizeof(u32))
1462                                 goto invalid_tlv_len;
1463                         pieces->inst_errlog_ptr =
1464                                         le32_to_cpup((__le32 *)tlv_data);
1465                         break;
1466                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1467                         if (tlv_len)
1468                                 goto invalid_tlv_len;
1469                         priv->enhance_sensitivity_table = true;
1470                         break;
1471                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1472                         if (tlv_len != sizeof(u32))
1473                                 goto invalid_tlv_len;
1474                         capa->standard_phy_calibration_size =
1475                                         le32_to_cpup((__le32 *)tlv_data);
1476                         break;
1477                 default:
1478                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1479                         break;
1480                 }
1481         }
1482
1483         if (len) {
1484                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1485                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1486                 return -EINVAL;
1487         }
1488
1489         return 0;
1490
1491  invalid_tlv_len:
1492         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1493         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1494
1495         return -EINVAL;
1496 }
1497
1498 /**
1499  * iwl_ucode_callback - callback when firmware was loaded
1500  *
1501  * If loaded successfully, copies the firmware into buffers
1502  * for the card to fetch (via DMA).
1503  */
1504 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1505 {
1506         struct iwl_priv *priv = context;
1507         struct iwl_ucode_header *ucode;
1508         int err;
1509         struct iwlagn_firmware_pieces pieces;
1510         const unsigned int api_max = priv->cfg->ucode_api_max;
1511         const unsigned int api_min = priv->cfg->ucode_api_min;
1512         u32 api_ver;
1513         char buildstr[25];
1514         u32 build;
1515         struct iwlagn_ucode_capabilities ucode_capa = {
1516                 .max_probe_length = 200,
1517                 .standard_phy_calibration_size =
1518                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1519         };
1520
1521         memset(&pieces, 0, sizeof(pieces));
1522
1523         if (!ucode_raw) {
1524                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1525                         IWL_ERR(priv,
1526                                 "request for firmware file '%s' failed.\n",
1527                                 priv->firmware_name);
1528                 goto try_again;
1529         }
1530
1531         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1532                        priv->firmware_name, ucode_raw->size);
1533
1534         /* Make sure that we got at least the API version number */
1535         if (ucode_raw->size < 4) {
1536                 IWL_ERR(priv, "File size way too small!\n");
1537                 goto try_again;
1538         }
1539
1540         /* Data from ucode file:  header followed by uCode images */
1541         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1542
1543         if (ucode->ver)
1544                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1545         else
1546                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1547                                            &ucode_capa);
1548
1549         if (err)
1550                 goto try_again;
1551
1552         api_ver = IWL_UCODE_API(priv->ucode_ver);
1553         build = pieces.build;
1554
1555         /*
1556          * api_ver should match the api version forming part of the
1557          * firmware filename ... but we don't check for that and only rely
1558          * on the API version read from firmware header from here on forward
1559          */
1560         /* no api version check required for experimental uCode */
1561         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1562                 if (api_ver < api_min || api_ver > api_max) {
1563                         IWL_ERR(priv,
1564                                 "Driver unable to support your firmware API. "
1565                                 "Driver supports v%u, firmware is v%u.\n",
1566                                 api_max, api_ver);
1567                         goto try_again;
1568                 }
1569
1570                 if (api_ver != api_max)
1571                         IWL_ERR(priv,
1572                                 "Firmware has old API version. Expected v%u, "
1573                                 "got v%u. New firmware can be obtained "
1574                                 "from http://www.intellinuxwireless.org.\n",
1575                                 api_max, api_ver);
1576         }
1577
1578         if (build)
1579                 sprintf(buildstr, " build %u%s", build,
1580                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1581                                 ? " (EXP)" : "");
1582         else
1583                 buildstr[0] = '\0';
1584
1585         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1586                  IWL_UCODE_MAJOR(priv->ucode_ver),
1587                  IWL_UCODE_MINOR(priv->ucode_ver),
1588                  IWL_UCODE_API(priv->ucode_ver),
1589                  IWL_UCODE_SERIAL(priv->ucode_ver),
1590                  buildstr);
1591
1592         snprintf(priv->hw->wiphy->fw_version,
1593                  sizeof(priv->hw->wiphy->fw_version),
1594                  "%u.%u.%u.%u%s",
1595                  IWL_UCODE_MAJOR(priv->ucode_ver),
1596                  IWL_UCODE_MINOR(priv->ucode_ver),
1597                  IWL_UCODE_API(priv->ucode_ver),
1598                  IWL_UCODE_SERIAL(priv->ucode_ver),
1599                  buildstr);
1600
1601         /*
1602          * For any of the failures below (before allocating pci memory)
1603          * we will try to load a version with a smaller API -- maybe the
1604          * user just got a corrupted version of the latest API.
1605          */
1606
1607         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1608                        priv->ucode_ver);
1609         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1610                        pieces.inst_size);
1611         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1612                        pieces.data_size);
1613         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1614                        pieces.init_size);
1615         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1616                        pieces.init_data_size);
1617         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
1618                        pieces.boot_size);
1619
1620         /* Verify that uCode images will fit in card's SRAM */
1621         if (pieces.inst_size > priv->hw_params.max_inst_size) {
1622                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1623                         pieces.inst_size);
1624                 goto try_again;
1625         }
1626
1627         if (pieces.data_size > priv->hw_params.max_data_size) {
1628                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1629                         pieces.data_size);
1630                 goto try_again;
1631         }
1632
1633         if (pieces.init_size > priv->hw_params.max_inst_size) {
1634                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1635                         pieces.init_size);
1636                 goto try_again;
1637         }
1638
1639         if (pieces.init_data_size > priv->hw_params.max_data_size) {
1640                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1641                         pieces.init_data_size);
1642                 goto try_again;
1643         }
1644
1645         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
1646                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
1647                         pieces.boot_size);
1648                 goto try_again;
1649         }
1650
1651         /* Allocate ucode buffers for card's bus-master loading ... */
1652
1653         /* Runtime instructions and 2 copies of data:
1654          * 1) unmodified from disk
1655          * 2) backup cache for save/restore during power-downs */
1656         priv->ucode_code.len = pieces.inst_size;
1657         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1658
1659         priv->ucode_data.len = pieces.data_size;
1660         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1661
1662         priv->ucode_data_backup.len = pieces.data_size;
1663         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1664
1665         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1666             !priv->ucode_data_backup.v_addr)
1667                 goto err_pci_alloc;
1668
1669         /* Initialization instructions and data */
1670         if (pieces.init_size && pieces.init_data_size) {
1671                 priv->ucode_init.len = pieces.init_size;
1672                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1673
1674                 priv->ucode_init_data.len = pieces.init_data_size;
1675                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1676
1677                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1678                         goto err_pci_alloc;
1679         }
1680
1681         /* Bootstrap (instructions only, no data) */
1682         if (pieces.boot_size) {
1683                 priv->ucode_boot.len = pieces.boot_size;
1684                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1685
1686                 if (!priv->ucode_boot.v_addr)
1687                         goto err_pci_alloc;
1688         }
1689
1690         /* Now that we can no longer fail, copy information */
1691
1692         /*
1693          * The (size - 16) / 12 formula is based on the information recorded
1694          * for each event, which is of mode 1 (including timestamp) for all
1695          * new microcodes that include this information.
1696          */
1697         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1698         if (pieces.init_evtlog_size)
1699                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1700         else
1701                 priv->_agn.init_evtlog_size =
1702                         priv->cfg->base_params->max_event_log_size;
1703         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1704         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1705         if (pieces.inst_evtlog_size)
1706                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1707         else
1708                 priv->_agn.inst_evtlog_size =
1709                         priv->cfg->base_params->max_event_log_size;
1710         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1711
1712         if (ucode_capa.pan) {
1713                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1714                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1715         } else
1716                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1717
1718         /* Copy images into buffers for card's bus-master reads ... */
1719
1720         /* Runtime instructions (first block of data in file) */
1721         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
1722                         pieces.inst_size);
1723         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
1724
1725         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1726                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1727
1728         /*
1729          * Runtime data
1730          * NOTE:  Copy into backup buffer will be done in iwl_up()
1731          */
1732         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
1733                         pieces.data_size);
1734         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
1735         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
1736
1737         /* Initialization instructions */
1738         if (pieces.init_size) {
1739                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1740                                 pieces.init_size);
1741                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
1742         }
1743
1744         /* Initialization data */
1745         if (pieces.init_data_size) {
1746                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1747                                pieces.init_data_size);
1748                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
1749                        pieces.init_data_size);
1750         }
1751
1752         /* Bootstrap instructions */
1753         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
1754                         pieces.boot_size);
1755         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
1756
1757         /*
1758          * figure out the offset of chain noise reset and gain commands
1759          * base on the size of standard phy calibration commands table size
1760          */
1761         if (ucode_capa.standard_phy_calibration_size >
1762             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1763                 ucode_capa.standard_phy_calibration_size =
1764                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1765
1766         priv->_agn.phy_calib_chain_noise_reset_cmd =
1767                 ucode_capa.standard_phy_calibration_size;
1768         priv->_agn.phy_calib_chain_noise_gain_cmd =
1769                 ucode_capa.standard_phy_calibration_size + 1;
1770
1771         /**************************************************
1772          * This is still part of probe() in a sense...
1773          *
1774          * 9. Setup and register with mac80211 and debugfs
1775          **************************************************/
1776         err = iwl_mac_setup_register(priv, &ucode_capa);
1777         if (err)
1778                 goto out_unbind;
1779
1780         err = iwl_dbgfs_register(priv, DRV_NAME);
1781         if (err)
1782                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1783
1784         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1785                                         &iwl_attribute_group);
1786         if (err) {
1787                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1788                 goto out_unbind;
1789         }
1790
1791         /* We have our copies now, allow OS release its copies */
1792         release_firmware(ucode_raw);
1793         complete(&priv->_agn.firmware_loading_complete);
1794         return;
1795
1796  try_again:
1797         /* try next, if any */
1798         if (iwl_request_firmware(priv, false))
1799                 goto out_unbind;
1800         release_firmware(ucode_raw);
1801         return;
1802
1803  err_pci_alloc:
1804         IWL_ERR(priv, "failed to allocate pci memory\n");
1805         iwl_dealloc_ucode_pci(priv);
1806  out_unbind:
1807         complete(&priv->_agn.firmware_loading_complete);
1808         device_release_driver(&priv->pci_dev->dev);
1809         release_firmware(ucode_raw);
1810 }
1811
1812 static const char *desc_lookup_text[] = {
1813         "OK",
1814         "FAIL",
1815         "BAD_PARAM",
1816         "BAD_CHECKSUM",
1817         "NMI_INTERRUPT_WDG",
1818         "SYSASSERT",
1819         "FATAL_ERROR",
1820         "BAD_COMMAND",
1821         "HW_ERROR_TUNE_LOCK",
1822         "HW_ERROR_TEMPERATURE",
1823         "ILLEGAL_CHAN_FREQ",
1824         "VCC_NOT_STABLE",
1825         "FH_ERROR",
1826         "NMI_INTERRUPT_HOST",
1827         "NMI_INTERRUPT_ACTION_PT",
1828         "NMI_INTERRUPT_UNKNOWN",
1829         "UCODE_VERSION_MISMATCH",
1830         "HW_ERROR_ABS_LOCK",
1831         "HW_ERROR_CAL_LOCK_FAIL",
1832         "NMI_INTERRUPT_INST_ACTION_PT",
1833         "NMI_INTERRUPT_DATA_ACTION_PT",
1834         "NMI_TRM_HW_ER",
1835         "NMI_INTERRUPT_TRM",
1836         "NMI_INTERRUPT_BREAK_POINT"
1837         "DEBUG_0",
1838         "DEBUG_1",
1839         "DEBUG_2",
1840         "DEBUG_3",
1841 };
1842
1843 static struct { char *name; u8 num; } advanced_lookup[] = {
1844         { "NMI_INTERRUPT_WDG", 0x34 },
1845         { "SYSASSERT", 0x35 },
1846         { "UCODE_VERSION_MISMATCH", 0x37 },
1847         { "BAD_COMMAND", 0x38 },
1848         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1849         { "FATAL_ERROR", 0x3D },
1850         { "NMI_TRM_HW_ERR", 0x46 },
1851         { "NMI_INTERRUPT_TRM", 0x4C },
1852         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1853         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1854         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1855         { "NMI_INTERRUPT_HOST", 0x66 },
1856         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1857         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1858         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1859         { "ADVANCED_SYSASSERT", 0 },
1860 };
1861
1862 static const char *desc_lookup(u32 num)
1863 {
1864         int i;
1865         int max = ARRAY_SIZE(desc_lookup_text);
1866
1867         if (num < max)
1868                 return desc_lookup_text[num];
1869
1870         max = ARRAY_SIZE(advanced_lookup) - 1;
1871         for (i = 0; i < max; i++) {
1872                 if (advanced_lookup[i].num == num)
1873                         break;;
1874         }
1875         return advanced_lookup[i].name;
1876 }
1877
1878 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1879 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1880
1881 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1882 {
1883         u32 data2, line;
1884         u32 desc, time, count, base, data1;
1885         u32 blink1, blink2, ilink1, ilink2;
1886         u32 pc, hcmd;
1887
1888         if (priv->ucode_type == UCODE_INIT) {
1889                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1890                 if (!base)
1891                         base = priv->_agn.init_errlog_ptr;
1892         } else {
1893                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1894                 if (!base)
1895                         base = priv->_agn.inst_errlog_ptr;
1896         }
1897
1898         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1899                 IWL_ERR(priv,
1900                         "Not valid error log pointer 0x%08X for %s uCode\n",
1901                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1902                 return;
1903         }
1904
1905         count = iwl_read_targ_mem(priv, base);
1906
1907         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1908                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1909                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1910                         priv->status, count);
1911         }
1912
1913         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1914         priv->isr_stats.err_code = desc;
1915         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
1916         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1917         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1918         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1919         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1920         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1921         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1922         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1923         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1924         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
1925
1926         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1927                                       blink1, blink2, ilink1, ilink2);
1928
1929         IWL_ERR(priv, "Desc                                  Time       "
1930                 "data1      data2      line\n");
1931         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1932                 desc_lookup(desc), desc, time, data1, data2, line);
1933         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
1934         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1935                 pc, blink1, blink2, ilink1, ilink2, hcmd);
1936 }
1937
1938 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1939
1940 /**
1941  * iwl_print_event_log - Dump error event log to syslog
1942  *
1943  */
1944 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1945                                u32 num_events, u32 mode,
1946                                int pos, char **buf, size_t bufsz)
1947 {
1948         u32 i;
1949         u32 base;       /* SRAM byte address of event log header */
1950         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1951         u32 ptr;        /* SRAM byte address of log data */
1952         u32 ev, time, data; /* event log data */
1953         unsigned long reg_flags;
1954
1955         if (num_events == 0)
1956                 return pos;
1957
1958         if (priv->ucode_type == UCODE_INIT) {
1959                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1960                 if (!base)
1961                         base = priv->_agn.init_evtlog_ptr;
1962         } else {
1963                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1964                 if (!base)
1965                         base = priv->_agn.inst_evtlog_ptr;
1966         }
1967
1968         if (mode == 0)
1969                 event_size = 2 * sizeof(u32);
1970         else
1971                 event_size = 3 * sizeof(u32);
1972
1973         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1974
1975         /* Make sure device is powered up for SRAM reads */
1976         spin_lock_irqsave(&priv->reg_lock, reg_flags);
1977         iwl_grab_nic_access(priv);
1978
1979         /* Set starting address; reads will auto-increment */
1980         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1981         rmb();
1982
1983         /* "time" is actually "data" for mode 0 (no timestamp).
1984         * place event id # at far right for easier visual parsing. */
1985         for (i = 0; i < num_events; i++) {
1986                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1987                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1988                 if (mode == 0) {
1989                         /* data, ev */
1990                         if (bufsz) {
1991                                 pos += scnprintf(*buf + pos, bufsz - pos,
1992                                                 "EVT_LOG:0x%08x:%04u\n",
1993                                                 time, ev);
1994                         } else {
1995                                 trace_iwlwifi_dev_ucode_event(priv, 0,
1996                                         time, ev);
1997                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1998                                         time, ev);
1999                         }
2000                 } else {
2001                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2002                         if (bufsz) {
2003                                 pos += scnprintf(*buf + pos, bufsz - pos,
2004                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2005                                                  time, data, ev);
2006                         } else {
2007                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2008                                         time, data, ev);
2009                                 trace_iwlwifi_dev_ucode_event(priv, time,
2010                                         data, ev);
2011                         }
2012                 }
2013         }
2014
2015         /* Allow device to power down */
2016         iwl_release_nic_access(priv);
2017         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2018         return pos;
2019 }
2020
2021 /**
2022  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2023  */
2024 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2025                                     u32 num_wraps, u32 next_entry,
2026                                     u32 size, u32 mode,
2027                                     int pos, char **buf, size_t bufsz)
2028 {
2029         /*
2030          * display the newest DEFAULT_LOG_ENTRIES entries
2031          * i.e the entries just before the next ont that uCode would fill.
2032          */
2033         if (num_wraps) {
2034                 if (next_entry < size) {
2035                         pos = iwl_print_event_log(priv,
2036                                                 capacity - (size - next_entry),
2037                                                 size - next_entry, mode,
2038                                                 pos, buf, bufsz);
2039                         pos = iwl_print_event_log(priv, 0,
2040                                                   next_entry, mode,
2041                                                   pos, buf, bufsz);
2042                 } else
2043                         pos = iwl_print_event_log(priv, next_entry - size,
2044                                                   size, mode, pos, buf, bufsz);
2045         } else {
2046                 if (next_entry < size) {
2047                         pos = iwl_print_event_log(priv, 0, next_entry,
2048                                                   mode, pos, buf, bufsz);
2049                 } else {
2050                         pos = iwl_print_event_log(priv, next_entry - size,
2051                                                   size, mode, pos, buf, bufsz);
2052                 }
2053         }
2054         return pos;
2055 }
2056
2057 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2058
2059 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2060                             char **buf, bool display)
2061 {
2062         u32 base;       /* SRAM byte address of event log header */
2063         u32 capacity;   /* event log capacity in # entries */
2064         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2065         u32 num_wraps;  /* # times uCode wrapped to top of log */
2066         u32 next_entry; /* index of next entry to be written by uCode */
2067         u32 size;       /* # entries that we'll print */
2068         u32 logsize;
2069         int pos = 0;
2070         size_t bufsz = 0;
2071
2072         if (priv->ucode_type == UCODE_INIT) {
2073                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2074                 logsize = priv->_agn.init_evtlog_size;
2075                 if (!base)
2076                         base = priv->_agn.init_evtlog_ptr;
2077         } else {
2078                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2079                 logsize = priv->_agn.inst_evtlog_size;
2080                 if (!base)
2081                         base = priv->_agn.inst_evtlog_ptr;
2082         }
2083
2084         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2085                 IWL_ERR(priv,
2086                         "Invalid event log pointer 0x%08X for %s uCode\n",
2087                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2088                 return -EINVAL;
2089         }
2090
2091         /* event log header */
2092         capacity = iwl_read_targ_mem(priv, base);
2093         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2094         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2095         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2096
2097         if (capacity > logsize) {
2098                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2099                         capacity, logsize);
2100                 capacity = logsize;
2101         }
2102
2103         if (next_entry > logsize) {
2104                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2105                         next_entry, logsize);
2106                 next_entry = logsize;
2107         }
2108
2109         size = num_wraps ? capacity : next_entry;
2110
2111         /* bail out if nothing in log */
2112         if (size == 0) {
2113                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2114                 return pos;
2115         }
2116
2117         /* enable/disable bt channel inhibition */
2118         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2119
2120 #ifdef CONFIG_IWLWIFI_DEBUG
2121         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2122                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2123                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2124 #else
2125         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2126                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2127 #endif
2128         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2129                 size);
2130
2131 #ifdef CONFIG_IWLWIFI_DEBUG
2132         if (display) {
2133                 if (full_log)
2134                         bufsz = capacity * 48;
2135                 else
2136                         bufsz = size * 48;
2137                 *buf = kmalloc(bufsz, GFP_KERNEL);
2138                 if (!*buf)
2139                         return -ENOMEM;
2140         }
2141         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2142                 /*
2143                  * if uCode has wrapped back to top of log,
2144                  * start at the oldest entry,
2145                  * i.e the next one that uCode would fill.
2146                  */
2147                 if (num_wraps)
2148                         pos = iwl_print_event_log(priv, next_entry,
2149                                                 capacity - next_entry, mode,
2150                                                 pos, buf, bufsz);
2151                 /* (then/else) start at top of log */
2152                 pos = iwl_print_event_log(priv, 0,
2153                                           next_entry, mode, pos, buf, bufsz);
2154         } else
2155                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2156                                                 next_entry, size, mode,
2157                                                 pos, buf, bufsz);
2158 #else
2159         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2160                                         next_entry, size, mode,
2161                                         pos, buf, bufsz);
2162 #endif
2163         return pos;
2164 }
2165
2166 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2167 {
2168         struct iwl_ct_kill_config cmd;
2169         struct iwl_ct_kill_throttling_config adv_cmd;
2170         unsigned long flags;
2171         int ret = 0;
2172
2173         spin_lock_irqsave(&priv->lock, flags);
2174         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2175                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2176         spin_unlock_irqrestore(&priv->lock, flags);
2177         priv->thermal_throttle.ct_kill_toggle = false;
2178
2179         if (priv->cfg->base_params->support_ct_kill_exit) {
2180                 adv_cmd.critical_temperature_enter =
2181                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2182                 adv_cmd.critical_temperature_exit =
2183                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2184
2185                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2186                                        sizeof(adv_cmd), &adv_cmd);
2187                 if (ret)
2188                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2189                 else
2190                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2191                                         "succeeded, "
2192                                         "critical temperature enter is %d,"
2193                                         "exit is %d\n",
2194                                        priv->hw_params.ct_kill_threshold,
2195                                        priv->hw_params.ct_kill_exit_threshold);
2196         } else {
2197                 cmd.critical_temperature_R =
2198                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2199
2200                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2201                                        sizeof(cmd), &cmd);
2202                 if (ret)
2203                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2204                 else
2205                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2206                                         "succeeded, "
2207                                         "critical temperature is %d\n",
2208                                         priv->hw_params.ct_kill_threshold);
2209         }
2210 }
2211
2212 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2213 {
2214         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2215         struct iwl_host_cmd cmd = {
2216                 .id = CALIBRATION_CFG_CMD,
2217                 .len = sizeof(struct iwl_calib_cfg_cmd),
2218                 .data = &calib_cfg_cmd,
2219         };
2220
2221         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2222         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2223         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2224
2225         return iwl_send_cmd(priv, &cmd);
2226 }
2227
2228
2229 /**
2230  * iwl_alive_start - called after REPLY_ALIVE notification received
2231  *                   from protocol/runtime uCode (initialization uCode's
2232  *                   Alive gets handled by iwl_init_alive_start()).
2233  */
2234 static void iwl_alive_start(struct iwl_priv *priv)
2235 {
2236         int ret = 0;
2237         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2238
2239         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2240
2241         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2242          * This is a paranoid check, because we would not have gotten the
2243          * "runtime" alive if code weren't properly loaded.  */
2244         if (iwl_verify_ucode(priv, &priv->ucode_code)) {
2245                 /* Runtime instruction load was bad;
2246                  * take it all the way back down so we can try again */
2247                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2248                 goto restart;
2249         }
2250
2251         ret = iwlagn_alive_notify(priv);
2252         if (ret) {
2253                 IWL_WARN(priv,
2254                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2255                 goto restart;
2256         }
2257
2258
2259         /* After the ALIVE response, we can send host commands to the uCode */
2260         set_bit(STATUS_ALIVE, &priv->status);
2261
2262         /* Enable watchdog to monitor the driver tx queues */
2263         iwl_setup_watchdog(priv);
2264
2265         if (iwl_is_rfkill(priv))
2266                 return;
2267
2268         /* download priority table before any calibration request */
2269         if (priv->cfg->bt_params &&
2270             priv->cfg->bt_params->advanced_bt_coexist) {
2271                 /* Configure Bluetooth device coexistence support */
2272                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2273                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2274                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2275                 priv->cfg->ops->hcmd->send_bt_config(priv);
2276                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2277                 iwlagn_send_prio_tbl(priv);
2278
2279                 /* FIXME: w/a to force change uCode BT state machine */
2280                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2281                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2282                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2283                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2284         }
2285         if (priv->hw_params.calib_rt_cfg)
2286                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2287
2288         ieee80211_wake_queues(priv->hw);
2289
2290         priv->active_rate = IWL_RATES_MASK;
2291
2292         /* Configure Tx antenna selection based on H/W config */
2293         if (priv->cfg->ops->hcmd->set_tx_ant)
2294                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2295
2296         if (iwl_is_associated_ctx(ctx)) {
2297                 struct iwl_rxon_cmd *active_rxon =
2298                                 (struct iwl_rxon_cmd *)&ctx->active;
2299                 /* apply any changes in staging */
2300                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2301                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2302         } else {
2303                 struct iwl_rxon_context *tmp;
2304                 /* Initialize our rx_config data */
2305                 for_each_context(priv, tmp)
2306                         iwl_connection_init_rx_config(priv, tmp);
2307
2308                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2309                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2310         }
2311
2312         if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2313             !priv->cfg->bt_params->advanced_bt_coexist)) {
2314                 /*
2315                  * default is 2-wire BT coexexistence support
2316                  */
2317                 priv->cfg->ops->hcmd->send_bt_config(priv);
2318         }
2319
2320         iwl_reset_run_time_calib(priv);
2321
2322         set_bit(STATUS_READY, &priv->status);
2323
2324         /* Configure the adapter for unassociated operation */
2325         iwlcore_commit_rxon(priv, ctx);
2326
2327         /* At this point, the NIC is initialized and operational */
2328         iwl_rf_kill_ct_config(priv);
2329
2330         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2331         wake_up_interruptible(&priv->wait_command_queue);
2332
2333         iwl_power_update_mode(priv, true);
2334         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2335
2336
2337         return;
2338
2339  restart:
2340         queue_work(priv->workqueue, &priv->restart);
2341 }
2342
2343 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2344
2345 static void __iwl_down(struct iwl_priv *priv)
2346 {
2347         unsigned long flags;
2348         int exit_pending;
2349
2350         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2351
2352         iwl_scan_cancel_timeout(priv, 200);
2353
2354         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2355
2356         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2357          * to prevent rearm timer */
2358         del_timer_sync(&priv->watchdog);
2359
2360         iwl_clear_ucode_stations(priv, NULL);
2361         iwl_dealloc_bcast_stations(priv);
2362         iwl_clear_driver_stations(priv);
2363
2364         /* reset BT coex data */
2365         priv->bt_status = 0;
2366         if (priv->cfg->bt_params)
2367                 priv->bt_traffic_load =
2368                          priv->cfg->bt_params->bt_init_traffic_load;
2369         else
2370                 priv->bt_traffic_load = 0;
2371         priv->bt_full_concurrent = false;
2372         priv->bt_ci_compliance = 0;
2373
2374         /* Wipe out the EXIT_PENDING status bit if we are not actually
2375          * exiting the module */
2376         if (!exit_pending)
2377                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2378
2379         /* stop and reset the on-board processor */
2380         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2381
2382         /* tell the device to stop sending interrupts */
2383         spin_lock_irqsave(&priv->lock, flags);
2384         iwl_disable_interrupts(priv);
2385         spin_unlock_irqrestore(&priv->lock, flags);
2386         iwl_synchronize_irq(priv);
2387
2388         if (priv->mac80211_registered)
2389                 ieee80211_stop_queues(priv->hw);
2390
2391         /* If we have not previously called iwl_init() then
2392          * clear all bits but the RF Kill bit and return */
2393         if (!iwl_is_init(priv)) {
2394                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2395                                         STATUS_RF_KILL_HW |
2396                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2397                                         STATUS_GEO_CONFIGURED |
2398                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2399                                         STATUS_EXIT_PENDING;
2400                 goto exit;
2401         }
2402
2403         /* ...otherwise clear out all the status bits but the RF Kill
2404          * bit and continue taking the NIC down. */
2405         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2406                                 STATUS_RF_KILL_HW |
2407                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2408                                 STATUS_GEO_CONFIGURED |
2409                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2410                                 STATUS_FW_ERROR |
2411                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2412                                 STATUS_EXIT_PENDING;
2413
2414         /* device going down, Stop using ICT table */
2415         if (priv->cfg->ops->lib->isr_ops.disable)
2416                 priv->cfg->ops->lib->isr_ops.disable(priv);
2417
2418         iwlagn_txq_ctx_stop(priv);
2419         iwlagn_rxq_stop(priv);
2420
2421         /* Power-down device's busmaster DMA clocks */
2422         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2423         udelay(5);
2424
2425         /* Make sure (redundant) we've released our request to stay awake */
2426         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2427
2428         /* Stop the device, and put it in low power state */
2429         iwl_apm_stop(priv);
2430
2431  exit:
2432         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2433
2434         dev_kfree_skb(priv->beacon_skb);
2435         priv->beacon_skb = NULL;
2436
2437         /* clear out any free frames */
2438         iwl_clear_free_frames(priv);
2439 }
2440
2441 static void iwl_down(struct iwl_priv *priv)
2442 {
2443         mutex_lock(&priv->mutex);
2444         __iwl_down(priv);
2445         mutex_unlock(&priv->mutex);
2446
2447         iwl_cancel_deferred_work(priv);
2448 }
2449
2450 #define HW_READY_TIMEOUT (50)
2451
2452 static int iwl_set_hw_ready(struct iwl_priv *priv)
2453 {
2454         int ret = 0;
2455
2456         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2457                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2458
2459         /* See if we got it */
2460         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2461                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2462                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2463                                 HW_READY_TIMEOUT);
2464         if (ret != -ETIMEDOUT)
2465                 priv->hw_ready = true;
2466         else
2467                 priv->hw_ready = false;
2468
2469         IWL_DEBUG_INFO(priv, "hardware %s\n",
2470                       (priv->hw_ready == 1) ? "ready" : "not ready");
2471         return ret;
2472 }
2473
2474 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2475 {
2476         int ret = 0;
2477
2478         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2479
2480         ret = iwl_set_hw_ready(priv);
2481         if (priv->hw_ready)
2482                 return ret;
2483
2484         /* If HW is not ready, prepare the conditions to check again */
2485         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2486                         CSR_HW_IF_CONFIG_REG_PREPARE);
2487
2488         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2489                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2490                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2491
2492         /* HW should be ready by now, check again. */
2493         if (ret != -ETIMEDOUT)
2494                 iwl_set_hw_ready(priv);
2495
2496         return ret;
2497 }
2498
2499 #define MAX_HW_RESTARTS 5
2500
2501 static int __iwl_up(struct iwl_priv *priv)
2502 {
2503         struct iwl_rxon_context *ctx;
2504         int i;
2505         int ret;
2506
2507         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2508                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2509                 return -EIO;
2510         }
2511
2512         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2513                 IWL_ERR(priv, "ucode not available for device bringup\n");
2514                 return -EIO;
2515         }
2516
2517         for_each_context(priv, ctx) {
2518                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2519                 if (ret) {
2520                         iwl_dealloc_bcast_stations(priv);
2521                         return ret;
2522                 }
2523         }
2524
2525         iwl_prepare_card_hw(priv);
2526
2527         if (!priv->hw_ready) {
2528                 IWL_WARN(priv, "Exit HW not ready\n");
2529                 return -EIO;
2530         }
2531
2532         /* If platform's RF_KILL switch is NOT set to KILL */
2533         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2534                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2535         else
2536                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2537
2538         if (iwl_is_rfkill(priv)) {
2539                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2540
2541                 iwl_enable_interrupts(priv);
2542                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2543                 return 0;
2544         }
2545
2546         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2547
2548         /* must be initialised before iwl_hw_nic_init */
2549         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2550                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2551         else
2552                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2553
2554         ret = iwlagn_hw_nic_init(priv);
2555         if (ret) {
2556                 IWL_ERR(priv, "Unable to init nic\n");
2557                 return ret;
2558         }
2559
2560         /* make sure rfkill handshake bits are cleared */
2561         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2562         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2563                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2564
2565         /* clear (again), then enable host interrupts */
2566         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2567         iwl_enable_interrupts(priv);
2568
2569         /* really make sure rfkill handshake bits are cleared */
2570         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2571         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2572
2573         /* Copy original ucode data image from disk into backup cache.
2574          * This will be used to initialize the on-board processor's
2575          * data SRAM for a clean start when the runtime program first loads. */
2576         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2577                priv->ucode_data.len);
2578
2579         for (i = 0; i < MAX_HW_RESTARTS; i++) {
2580
2581                 /* load bootstrap state machine,
2582                  * load bootstrap program into processor's memory,
2583                  * prepare to load the "initialize" uCode */
2584                 ret = iwlagn_load_ucode(priv);
2585
2586                 if (ret) {
2587                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2588                                 ret);
2589                         continue;
2590                 }
2591
2592                 /* start card; "initialize" will load runtime ucode */
2593                 iwl_nic_start(priv);
2594
2595                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2596
2597                 return 0;
2598         }
2599
2600         set_bit(STATUS_EXIT_PENDING, &priv->status);
2601         __iwl_down(priv);
2602         clear_bit(STATUS_EXIT_PENDING, &priv->status);
2603
2604         /* tried to restart and config the device for as long as our
2605          * patience could withstand */
2606         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2607         return -EIO;
2608 }
2609
2610
2611 /*****************************************************************************
2612  *
2613  * Workqueue callbacks
2614  *
2615  *****************************************************************************/
2616
2617 static void iwl_bg_init_alive_start(struct work_struct *data)
2618 {
2619         struct iwl_priv *priv =
2620             container_of(data, struct iwl_priv, init_alive_start.work);
2621
2622         mutex_lock(&priv->mutex);
2623
2624         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2625                 mutex_unlock(&priv->mutex);
2626                 return;
2627         }
2628
2629         iwlagn_init_alive_start(priv);
2630         mutex_unlock(&priv->mutex);
2631 }
2632
2633 static void iwl_bg_alive_start(struct work_struct *data)
2634 {
2635         struct iwl_priv *priv =
2636             container_of(data, struct iwl_priv, alive_start.work);
2637
2638         mutex_lock(&priv->mutex);
2639         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2640                 goto unlock;
2641
2642         /* enable dram interrupt */
2643         if (priv->cfg->ops->lib->isr_ops.reset)
2644                 priv->cfg->ops->lib->isr_ops.reset(priv);
2645
2646         iwl_alive_start(priv);
2647 unlock:
2648         mutex_unlock(&priv->mutex);
2649 }
2650
2651 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2652 {
2653         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2654                         run_time_calib_work);
2655
2656         mutex_lock(&priv->mutex);
2657
2658         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2659             test_bit(STATUS_SCANNING, &priv->status)) {
2660                 mutex_unlock(&priv->mutex);
2661                 return;
2662         }
2663
2664         if (priv->start_calib) {
2665                 if (iwl_bt_statistics(priv)) {
2666                         iwl_chain_noise_calibration(priv,
2667                                         (void *)&priv->_agn.statistics_bt);
2668                         iwl_sensitivity_calibration(priv,
2669                                         (void *)&priv->_agn.statistics_bt);
2670                 } else {
2671                         iwl_chain_noise_calibration(priv,
2672                                         (void *)&priv->_agn.statistics);
2673                         iwl_sensitivity_calibration(priv,
2674                                         (void *)&priv->_agn.statistics);
2675                 }
2676         }
2677
2678         mutex_unlock(&priv->mutex);
2679 }
2680
2681 static void iwl_bg_restart(struct work_struct *data)
2682 {
2683         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2684
2685         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2686                 return;
2687
2688         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2689                 struct iwl_rxon_context *ctx;
2690                 bool bt_full_concurrent;
2691                 u8 bt_ci_compliance;
2692                 u8 bt_load;
2693                 u8 bt_status;
2694
2695                 mutex_lock(&priv->mutex);
2696                 for_each_context(priv, ctx)
2697                         ctx->vif = NULL;
2698                 priv->is_open = 0;
2699
2700                 /*
2701                  * __iwl_down() will clear the BT status variables,
2702                  * which is correct, but when we restart we really
2703                  * want to keep them so restore them afterwards.
2704                  *
2705                  * The restart process will later pick them up and
2706                  * re-configure the hw when we reconfigure the BT
2707                  * command.
2708                  */
2709                 bt_full_concurrent = priv->bt_full_concurrent;
2710                 bt_ci_compliance = priv->bt_ci_compliance;
2711                 bt_load = priv->bt_traffic_load;
2712                 bt_status = priv->bt_status;
2713
2714                 __iwl_down(priv);
2715
2716                 priv->bt_full_concurrent = bt_full_concurrent;
2717                 priv->bt_ci_compliance = bt_ci_compliance;
2718                 priv->bt_traffic_load = bt_load;
2719                 priv->bt_status = bt_status;
2720
2721                 mutex_unlock(&priv->mutex);
2722                 iwl_cancel_deferred_work(priv);
2723                 ieee80211_restart_hw(priv->hw);
2724         } else {
2725                 iwl_down(priv);
2726
2727                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2728                         return;
2729
2730                 mutex_lock(&priv->mutex);
2731                 __iwl_up(priv);
2732                 mutex_unlock(&priv->mutex);
2733         }
2734 }
2735
2736 static void iwl_bg_rx_replenish(struct work_struct *data)
2737 {
2738         struct iwl_priv *priv =
2739             container_of(data, struct iwl_priv, rx_replenish);
2740
2741         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2742                 return;
2743
2744         mutex_lock(&priv->mutex);
2745         iwlagn_rx_replenish(priv);
2746         mutex_unlock(&priv->mutex);
2747 }
2748
2749 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2750                                  struct ieee80211_channel *chan,
2751                                  enum nl80211_channel_type channel_type,
2752                                  unsigned int wait)
2753 {
2754         struct iwl_priv *priv = hw->priv;
2755         int ret;
2756
2757         /* Not supported if we don't have PAN */
2758         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2759                 ret = -EOPNOTSUPP;
2760                 goto free;
2761         }
2762
2763         /* Not supported on pre-P2P firmware */
2764         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2765                                         BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2766                 ret = -EOPNOTSUPP;
2767                 goto free;
2768         }
2769
2770         mutex_lock(&priv->mutex);
2771
2772         if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2773                 /*
2774                  * If the PAN context is free, use the normal
2775                  * way of doing remain-on-channel offload + TX.
2776                  */
2777                 ret = 1;
2778                 goto out;
2779         }
2780
2781         /* TODO: queue up if scanning? */
2782         if (test_bit(STATUS_SCANNING, &priv->status) ||
2783             priv->_agn.offchan_tx_skb) {
2784                 ret = -EBUSY;
2785                 goto out;
2786         }
2787
2788         /*
2789          * max_scan_ie_len doesn't include the blank SSID or the header,
2790          * so need to add that again here.
2791          */
2792         if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2793                 ret = -ENOBUFS;
2794                 goto out;
2795         }
2796
2797         priv->_agn.offchan_tx_skb = skb;
2798         priv->_agn.offchan_tx_timeout = wait;
2799         priv->_agn.offchan_tx_chan = chan;
2800
2801         ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2802                                 IWL_SCAN_OFFCH_TX, chan->band);
2803         if (ret)
2804                 priv->_agn.offchan_tx_skb = NULL;
2805  out:
2806         mutex_unlock(&priv->mutex);
2807  free:
2808         if (ret < 0)
2809                 kfree_skb(skb);
2810
2811         return ret;
2812 }
2813
2814 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2815 {
2816         struct iwl_priv *priv = hw->priv;
2817         int ret;
2818
2819         mutex_lock(&priv->mutex);
2820
2821         if (!priv->_agn.offchan_tx_skb) {
2822                 ret = -EINVAL;
2823                 goto unlock;
2824         }
2825
2826         priv->_agn.offchan_tx_skb = NULL;
2827
2828         ret = iwl_scan_cancel_timeout(priv, 200);
2829         if (ret)
2830                 ret = -EIO;
2831 unlock:
2832         mutex_unlock(&priv->mutex);
2833
2834         return ret;
2835 }
2836
2837 /*****************************************************************************
2838  *
2839  * mac80211 entry point functions
2840  *
2841  *****************************************************************************/
2842
2843 #define UCODE_READY_TIMEOUT     (4 * HZ)
2844
2845 /*
2846  * Not a mac80211 entry point function, but it fits in with all the
2847  * other mac80211 functions grouped here.
2848  */
2849 static int iwl_mac_setup_register(struct iwl_priv *priv,
2850                                   struct iwlagn_ucode_capabilities *capa)
2851 {
2852         int ret;
2853         struct ieee80211_hw *hw = priv->hw;
2854         struct iwl_rxon_context *ctx;
2855
2856         hw->rate_control_algorithm = "iwl-agn-rs";
2857
2858         /* Tell mac80211 our characteristics */
2859         hw->flags = IEEE80211_HW_SIGNAL_DBM |
2860                     IEEE80211_HW_AMPDU_AGGREGATION |
2861                     IEEE80211_HW_NEED_DTIM_PERIOD |
2862                     IEEE80211_HW_SPECTRUM_MGMT |
2863                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2864
2865         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2866
2867         if (!priv->cfg->base_params->broken_powersave)
2868                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2869                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2870
2871         if (priv->cfg->sku & IWL_SKU_N)
2872                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2873                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2874
2875         hw->sta_data_size = sizeof(struct iwl_station_priv);
2876         hw->vif_data_size = sizeof(struct iwl_vif_priv);
2877
2878         for_each_context(priv, ctx) {
2879                 hw->wiphy->interface_modes |= ctx->interface_modes;
2880                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2881         }
2882
2883         hw->wiphy->max_remain_on_channel_duration = 1000;
2884
2885         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2886                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
2887                             WIPHY_FLAG_IBSS_RSN;
2888
2889         /*
2890          * For now, disable PS by default because it affects
2891          * RX performance significantly.
2892          */
2893         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2894
2895         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2896         /* we create the 802.11 header and a zero-length SSID element */
2897         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2898
2899         /* Default value; 4 EDCA QOS priorities */
2900         hw->queues = 4;
2901
2902         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2903
2904         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2905                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2906                         &priv->bands[IEEE80211_BAND_2GHZ];
2907         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2908                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2909                         &priv->bands[IEEE80211_BAND_5GHZ];
2910
2911         iwl_leds_init(priv);
2912
2913         ret = ieee80211_register_hw(priv->hw);
2914         if (ret) {
2915                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2916                 return ret;
2917         }
2918         priv->mac80211_registered = 1;
2919
2920         return 0;
2921 }
2922
2923
2924 static int iwlagn_mac_start(struct ieee80211_hw *hw)
2925 {
2926         struct iwl_priv *priv = hw->priv;
2927         int ret;
2928
2929         IWL_DEBUG_MAC80211(priv, "enter\n");
2930
2931         /* we should be verifying the device is ready to be opened */
2932         mutex_lock(&priv->mutex);
2933         ret = __iwl_up(priv);
2934         mutex_unlock(&priv->mutex);
2935
2936         if (ret)
2937                 return ret;
2938
2939         if (iwl_is_rfkill(priv))
2940                 goto out;
2941
2942         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2943
2944         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2945          * mac80211 will not be run successfully. */
2946         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2947                         test_bit(STATUS_READY, &priv->status),
2948                         UCODE_READY_TIMEOUT);
2949         if (!ret) {
2950                 if (!test_bit(STATUS_READY, &priv->status)) {
2951                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2952                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2953                         return -ETIMEDOUT;
2954                 }
2955         }
2956
2957         iwlagn_led_enable(priv);
2958
2959 out:
2960         priv->is_open = 1;
2961         IWL_DEBUG_MAC80211(priv, "leave\n");
2962         return 0;
2963 }
2964
2965 static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2966 {
2967         struct iwl_priv *priv = hw->priv;
2968
2969         IWL_DEBUG_MAC80211(priv, "enter\n");
2970
2971         if (!priv->is_open)
2972                 return;
2973
2974         priv->is_open = 0;
2975
2976         iwl_down(priv);
2977
2978         flush_workqueue(priv->workqueue);
2979
2980         /* User space software may expect getting rfkill changes
2981          * even if interface is down */
2982         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2983         iwl_enable_rfkill_int(priv);
2984
2985         IWL_DEBUG_MAC80211(priv, "leave\n");
2986 }
2987
2988 static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2989 {
2990         struct iwl_priv *priv = hw->priv;
2991
2992         IWL_DEBUG_MACDUMP(priv, "enter\n");
2993
2994         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2995                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2996
2997         if (iwlagn_tx_skb(priv, skb))
2998                 dev_kfree_skb_any(skb);
2999
3000         IWL_DEBUG_MACDUMP(priv, "leave\n");
3001 }
3002
3003 static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3004                                        struct ieee80211_vif *vif,
3005                                        struct ieee80211_key_conf *keyconf,
3006                                        struct ieee80211_sta *sta,
3007                                        u32 iv32, u16 *phase1key)
3008 {
3009         struct iwl_priv *priv = hw->priv;
3010         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3011
3012         IWL_DEBUG_MAC80211(priv, "enter\n");
3013
3014         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3015                             iv32, phase1key);
3016
3017         IWL_DEBUG_MAC80211(priv, "leave\n");
3018 }
3019
3020 static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3021                               struct ieee80211_vif *vif,
3022                               struct ieee80211_sta *sta,
3023                               struct ieee80211_key_conf *key)
3024 {
3025         struct iwl_priv *priv = hw->priv;
3026         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3027         struct iwl_rxon_context *ctx = vif_priv->ctx;
3028         int ret;
3029         u8 sta_id;
3030         bool is_default_wep_key = false;
3031
3032         IWL_DEBUG_MAC80211(priv, "enter\n");
3033
3034         if (priv->cfg->mod_params->sw_crypto) {
3035                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3036                 return -EOPNOTSUPP;
3037         }
3038
3039         /*
3040          * To support IBSS RSN, don't program group keys in IBSS, the
3041          * hardware will then not attempt to decrypt the frames.
3042          */
3043         if (vif->type == NL80211_IFTYPE_ADHOC &&
3044             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3045                 return -EOPNOTSUPP;
3046
3047         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3048         if (sta_id == IWL_INVALID_STATION)
3049                 return -EINVAL;
3050
3051         mutex_lock(&priv->mutex);
3052         iwl_scan_cancel_timeout(priv, 100);
3053
3054         /*
3055          * If we are getting WEP group key and we didn't receive any key mapping
3056          * so far, we are in legacy wep mode (group key only), otherwise we are
3057          * in 1X mode.
3058          * In legacy wep mode, we use another host command to the uCode.
3059          */
3060         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3061              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3062             !sta) {
3063                 if (cmd == SET_KEY)
3064                         is_default_wep_key = !ctx->key_mapping_keys;
3065                 else
3066                         is_default_wep_key =
3067                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3068         }
3069
3070         switch (cmd) {
3071         case SET_KEY:
3072                 if (is_default_wep_key)
3073                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3074                 else
3075                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3076                                                   key, sta_id);
3077
3078                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3079                 break;
3080         case DISABLE_KEY:
3081                 if (is_default_wep_key)
3082                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3083                 else
3084                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3085
3086                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3087                 break;
3088         default:
3089                 ret = -EINVAL;
3090         }
3091
3092         mutex_unlock(&priv->mutex);
3093         IWL_DEBUG_MAC80211(priv, "leave\n");
3094
3095         return ret;
3096 }
3097
3098 static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3099                                    struct ieee80211_vif *vif,
3100                                    enum ieee80211_ampdu_mlme_action action,
3101                                    struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3102                                    u8 buf_size)
3103 {
3104         struct iwl_priv *priv = hw->priv;
3105         int ret = -EINVAL;
3106         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3107
3108         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3109                      sta->addr, tid);
3110
3111         if (!(priv->cfg->sku & IWL_SKU_N))
3112                 return -EACCES;
3113
3114         mutex_lock(&priv->mutex);
3115
3116         switch (action) {
3117         case IEEE80211_AMPDU_RX_START:
3118                 IWL_DEBUG_HT(priv, "start Rx\n");
3119                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3120                 break;
3121         case IEEE80211_AMPDU_RX_STOP:
3122                 IWL_DEBUG_HT(priv, "stop Rx\n");
3123                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3124                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3125                         ret = 0;
3126                 break;
3127         case IEEE80211_AMPDU_TX_START:
3128                 IWL_DEBUG_HT(priv, "start Tx\n");
3129                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3130                 if (ret == 0) {
3131                         priv->_agn.agg_tids_count++;
3132                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3133                                      priv->_agn.agg_tids_count);
3134                 }
3135                 break;
3136         case IEEE80211_AMPDU_TX_STOP:
3137                 IWL_DEBUG_HT(priv, "stop Tx\n");
3138                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3139                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3140                         priv->_agn.agg_tids_count--;
3141                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3142                                      priv->_agn.agg_tids_count);
3143                 }
3144                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3145                         ret = 0;
3146                 if (priv->cfg->ht_params &&
3147                     priv->cfg->ht_params->use_rts_for_aggregation) {
3148                         struct iwl_station_priv *sta_priv =
3149                                 (void *) sta->drv_priv;
3150                         /*
3151                          * switch off RTS/CTS if it was previously enabled
3152                          */
3153
3154                         sta_priv->lq_sta.lq.general_params.flags &=
3155                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3156                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3157                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3158                 }
3159                 break;
3160         case IEEE80211_AMPDU_TX_OPERATIONAL:
3161                 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
3162
3163                 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
3164
3165                 /*
3166                  * If the limit is 0, then it wasn't initialised yet,
3167                  * use the default. We can do that since we take the
3168                  * minimum below, and we don't want to go above our
3169                  * default due to hardware restrictions.
3170                  */
3171                 if (sta_priv->max_agg_bufsize == 0)
3172                         sta_priv->max_agg_bufsize =
3173                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3174
3175                 /*
3176                  * Even though in theory the peer could have different
3177                  * aggregation reorder buffer sizes for different sessions,
3178                  * our ucode doesn't allow for that and has a global limit
3179                  * for each station. Therefore, use the minimum of all the
3180                  * aggregation sessions and our default value.
3181                  */
3182                 sta_priv->max_agg_bufsize =
3183                         min(sta_priv->max_agg_bufsize, buf_size);
3184
3185                 if (priv->cfg->ht_params &&
3186                     priv->cfg->ht_params->use_rts_for_aggregation) {
3187                         /*
3188                          * switch to RTS/CTS if it is the prefer protection
3189                          * method for HT traffic
3190                          */
3191
3192                         sta_priv->lq_sta.lq.general_params.flags |=
3193                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3194                 }
3195
3196                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3197                         sta_priv->max_agg_bufsize;
3198
3199                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3200                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3201                 ret = 0;
3202                 break;
3203         }
3204         mutex_unlock(&priv->mutex);
3205
3206         return ret;
3207 }
3208
3209 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3210                               struct ieee80211_vif *vif,
3211                               struct ieee80211_sta *sta)
3212 {
3213         struct iwl_priv *priv = hw->priv;
3214         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3215         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3216         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3217         int ret;
3218         u8 sta_id;
3219
3220         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3221                         sta->addr);
3222         mutex_lock(&priv->mutex);
3223         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3224                         sta->addr);
3225         sta_priv->common.sta_id = IWL_INVALID_STATION;
3226
3227         atomic_set(&sta_priv->pending_frames, 0);
3228         if (vif->type == NL80211_IFTYPE_AP)
3229                 sta_priv->client = true;
3230
3231         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3232                                      is_ap, sta, &sta_id);
3233         if (ret) {
3234                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3235                         sta->addr, ret);
3236                 /* Should we return success if return code is EEXIST ? */
3237                 mutex_unlock(&priv->mutex);
3238                 return ret;
3239         }
3240
3241         sta_priv->common.sta_id = sta_id;
3242
3243         /* Initialize rate scaling */
3244         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3245                        sta->addr);
3246         iwl_rs_rate_init(priv, sta, sta_id);
3247         mutex_unlock(&priv->mutex);
3248
3249         return 0;
3250 }
3251
3252 static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3253                                 struct ieee80211_channel_switch *ch_switch)
3254 {
3255         struct iwl_priv *priv = hw->priv;
3256         const struct iwl_channel_info *ch_info;
3257         struct ieee80211_conf *conf = &hw->conf;
3258         struct ieee80211_channel *channel = ch_switch->channel;
3259         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3260         /*
3261          * MULTI-FIXME
3262          * When we add support for multiple interfaces, we need to
3263          * revisit this. The channel switch command in the device
3264          * only affects the BSS context, but what does that really
3265          * mean? And what if we get a CSA on the second interface?
3266          * This needs a lot of work.
3267          */
3268         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3269         u16 ch;
3270         unsigned long flags = 0;
3271
3272         IWL_DEBUG_MAC80211(priv, "enter\n");
3273
3274         mutex_lock(&priv->mutex);
3275
3276         if (iwl_is_rfkill(priv))
3277                 goto out;
3278
3279         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3280             test_bit(STATUS_SCANNING, &priv->status))
3281                 goto out;
3282
3283         if (!iwl_is_associated_ctx(ctx))
3284                 goto out;
3285
3286         /* channel switch in progress */
3287         if (priv->switch_rxon.switch_in_progress == true)
3288                 goto out;
3289
3290         if (priv->cfg->ops->lib->set_channel_switch) {
3291
3292                 ch = channel->hw_value;
3293                 if (le16_to_cpu(ctx->active.channel) != ch) {
3294                         ch_info = iwl_get_channel_info(priv,
3295                                                        channel->band,
3296                                                        ch);
3297                         if (!is_channel_valid(ch_info)) {
3298                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3299                                 goto out;
3300                         }
3301                         spin_lock_irqsave(&priv->lock, flags);
3302
3303                         priv->current_ht_config.smps = conf->smps_mode;
3304
3305                         /* Configure HT40 channels */
3306                         ctx->ht.enabled = conf_is_ht(conf);
3307                         if (ctx->ht.enabled) {
3308                                 if (conf_is_ht40_minus(conf)) {
3309                                         ctx->ht.extension_chan_offset =
3310                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3311                                         ctx->ht.is_40mhz = true;
3312                                 } else if (conf_is_ht40_plus(conf)) {
3313                                         ctx->ht.extension_chan_offset =
3314                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3315                                         ctx->ht.is_40mhz = true;
3316                                 } else {
3317                                         ctx->ht.extension_chan_offset =
3318                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3319                                         ctx->ht.is_40mhz = false;
3320                                 }
3321                         } else
3322                                 ctx->ht.is_40mhz = false;
3323
3324                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3325                                 ctx->staging.flags = 0;
3326
3327                         iwl_set_rxon_channel(priv, channel, ctx);
3328                         iwl_set_rxon_ht(priv, ht_conf);
3329                         iwl_set_flags_for_band(priv, ctx, channel->band,
3330                                                ctx->vif);
3331                         spin_unlock_irqrestore(&priv->lock, flags);
3332
3333                         iwl_set_rate(priv);
3334                         /*
3335                          * at this point, staging_rxon has the
3336                          * configuration for channel switch
3337                          */
3338                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3339                                                                     ch_switch))
3340                                 priv->switch_rxon.switch_in_progress = false;
3341                 }
3342         }
3343 out:
3344         mutex_unlock(&priv->mutex);
3345         if (!priv->switch_rxon.switch_in_progress)
3346                 ieee80211_chswitch_done(ctx->vif, false);
3347         IWL_DEBUG_MAC80211(priv, "leave\n");
3348 }
3349
3350 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3351                                     unsigned int changed_flags,
3352                                     unsigned int *total_flags,
3353                                     u64 multicast)
3354 {
3355         struct iwl_priv *priv = hw->priv;
3356         __le32 filter_or = 0, filter_nand = 0;
3357         struct iwl_rxon_context *ctx;
3358
3359 #define CHK(test, flag) do { \
3360         if (*total_flags & (test))              \
3361                 filter_or |= (flag);            \
3362         else                                    \
3363                 filter_nand |= (flag);          \
3364         } while (0)
3365
3366         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3367                         changed_flags, *total_flags);
3368
3369         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3370         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3371         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3372         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3373
3374 #undef CHK
3375
3376         mutex_lock(&priv->mutex);
3377
3378         for_each_context(priv, ctx) {
3379                 ctx->staging.filter_flags &= ~filter_nand;
3380                 ctx->staging.filter_flags |= filter_or;
3381
3382                 /*
3383                  * Not committing directly because hardware can perform a scan,
3384                  * but we'll eventually commit the filter flags change anyway.
3385                  */
3386         }
3387
3388         mutex_unlock(&priv->mutex);
3389
3390         /*
3391          * Receiving all multicast frames is always enabled by the
3392          * default flags setup in iwl_connection_init_rx_config()
3393          * since we currently do not support programming multicast
3394          * filters into the device.
3395          */
3396         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3397                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3398 }
3399
3400 static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3401 {
3402         struct iwl_priv *priv = hw->priv;
3403
3404         mutex_lock(&priv->mutex);
3405         IWL_DEBUG_MAC80211(priv, "enter\n");
3406
3407         /* do not support "flush" */
3408         if (!priv->cfg->ops->lib->txfifo_flush)
3409                 goto done;
3410
3411         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3412                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3413                 goto done;
3414         }
3415         if (iwl_is_rfkill(priv)) {
3416                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3417                 goto done;
3418         }
3419
3420         /*
3421          * mac80211 will not push any more frames for transmit
3422          * until the flush is completed
3423          */
3424         if (drop) {
3425                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3426                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3427                         IWL_ERR(priv, "flush request fail\n");
3428                         goto done;
3429                 }
3430         }
3431         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3432         iwlagn_wait_tx_queue_empty(priv);
3433 done:
3434         mutex_unlock(&priv->mutex);
3435         IWL_DEBUG_MAC80211(priv, "leave\n");
3436 }
3437
3438 static void iwlagn_disable_roc(struct iwl_priv *priv)
3439 {
3440         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3441         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3442
3443         lockdep_assert_held(&priv->mutex);
3444
3445         if (!ctx->is_active)
3446                 return;
3447
3448         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3449         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3450         iwl_set_rxon_channel(priv, chan, ctx);
3451         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3452
3453         priv->_agn.hw_roc_channel = NULL;
3454
3455         iwlcore_commit_rxon(priv, ctx);
3456
3457         ctx->is_active = false;
3458 }
3459
3460 static void iwlagn_bg_roc_done(struct work_struct *work)
3461 {
3462         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3463                                              _agn.hw_roc_work.work);
3464
3465         mutex_lock(&priv->mutex);
3466         ieee80211_remain_on_channel_expired(priv->hw);
3467         iwlagn_disable_roc(priv);
3468         mutex_unlock(&priv->mutex);
3469 }
3470
3471 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3472                                      struct ieee80211_channel *channel,
3473                                      enum nl80211_channel_type channel_type,
3474                                      int duration)
3475 {
3476         struct iwl_priv *priv = hw->priv;
3477         int err = 0;
3478
3479         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3480                 return -EOPNOTSUPP;
3481
3482         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3483                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3484                 return -EOPNOTSUPP;
3485
3486         mutex_lock(&priv->mutex);
3487
3488         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3489             test_bit(STATUS_SCAN_HW, &priv->status)) {
3490                 err = -EBUSY;
3491                 goto out;
3492         }
3493
3494         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3495         priv->_agn.hw_roc_channel = channel;
3496         priv->_agn.hw_roc_chantype = channel_type;
3497         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3498         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3499         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3500                            msecs_to_jiffies(duration + 20));
3501
3502         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3503         ieee80211_ready_on_channel(priv->hw);
3504
3505  out:
3506         mutex_unlock(&priv->mutex);
3507
3508         return err;
3509 }
3510
3511 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3512 {
3513         struct iwl_priv *priv = hw->priv;
3514
3515         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3516                 return -EOPNOTSUPP;
3517
3518         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3519
3520         mutex_lock(&priv->mutex);
3521         iwlagn_disable_roc(priv);
3522         mutex_unlock(&priv->mutex);
3523
3524         return 0;
3525 }
3526
3527 /*****************************************************************************
3528  *
3529  * driver setup and teardown
3530  *
3531  *****************************************************************************/
3532
3533 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3534 {
3535         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3536
3537         init_waitqueue_head(&priv->wait_command_queue);
3538
3539         INIT_WORK(&priv->restart, iwl_bg_restart);
3540         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3541         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3542         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3543         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3544         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3545         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3546         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3547         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3548         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3549
3550         iwl_setup_scan_deferred_work(priv);
3551
3552         if (priv->cfg->ops->lib->setup_deferred_work)
3553                 priv->cfg->ops->lib->setup_deferred_work(priv);
3554
3555         init_timer(&priv->statistics_periodic);
3556         priv->statistics_periodic.data = (unsigned long)priv;
3557         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3558
3559         init_timer(&priv->ucode_trace);
3560         priv->ucode_trace.data = (unsigned long)priv;
3561         priv->ucode_trace.function = iwl_bg_ucode_trace;
3562
3563         init_timer(&priv->watchdog);
3564         priv->watchdog.data = (unsigned long)priv;
3565         priv->watchdog.function = iwl_bg_watchdog;
3566
3567         tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3568                 iwl_irq_tasklet, (unsigned long)priv);
3569 }
3570
3571 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3572 {
3573         if (priv->cfg->ops->lib->cancel_deferred_work)
3574                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3575
3576         cancel_delayed_work_sync(&priv->init_alive_start);
3577         cancel_delayed_work(&priv->alive_start);
3578         cancel_work_sync(&priv->run_time_calib_work);
3579         cancel_work_sync(&priv->beacon_update);
3580
3581         iwl_cancel_scan_deferred_work(priv);
3582
3583         cancel_work_sync(&priv->bt_full_concurrency);
3584         cancel_work_sync(&priv->bt_runtime_config);
3585
3586         del_timer_sync(&priv->statistics_periodic);
3587         del_timer_sync(&priv->ucode_trace);
3588 }
3589
3590 static void iwl_init_hw_rates(struct iwl_priv *priv,
3591                               struct ieee80211_rate *rates)
3592 {
3593         int i;
3594
3595         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3596                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3597                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3598                 rates[i].hw_value_short = i;
3599                 rates[i].flags = 0;
3600                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3601                         /*
3602                          * If CCK != 1M then set short preamble rate flag.
3603                          */
3604                         rates[i].flags |=
3605                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3606                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3607                 }
3608         }
3609 }
3610
3611 static int iwl_init_drv(struct iwl_priv *priv)
3612 {
3613         int ret;
3614
3615         spin_lock_init(&priv->sta_lock);
3616         spin_lock_init(&priv->hcmd_lock);
3617
3618         INIT_LIST_HEAD(&priv->free_frames);
3619
3620         mutex_init(&priv->mutex);
3621
3622         priv->ieee_channels = NULL;
3623         priv->ieee_rates = NULL;
3624         priv->band = IEEE80211_BAND_2GHZ;
3625
3626         priv->iw_mode = NL80211_IFTYPE_STATION;
3627         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3628         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3629         priv->_agn.agg_tids_count = 0;
3630
3631         /* initialize force reset */
3632         priv->force_reset[IWL_RF_RESET].reset_duration =
3633                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3634         priv->force_reset[IWL_FW_RESET].reset_duration =
3635                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3636
3637         priv->rx_statistics_jiffies = jiffies;
3638
3639         /* Choose which receivers/antennas to use */
3640         if (priv->cfg->ops->hcmd->set_rxon_chain)
3641                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3642                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3643
3644         iwl_init_scan_params(priv);
3645
3646         /* init bt coex */
3647         if (priv->cfg->bt_params &&
3648             priv->cfg->bt_params->advanced_bt_coexist) {
3649                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3650                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3651                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3652                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3653                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3654                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3655         }
3656
3657         /* Set the tx_power_user_lmt to the lowest power level
3658          * this value will get overwritten by channel max power avg
3659          * from eeprom */
3660         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3661         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3662
3663         ret = iwl_init_channel_map(priv);
3664         if (ret) {
3665                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3666                 goto err;
3667         }
3668
3669         ret = iwlcore_init_geos(priv);
3670         if (ret) {
3671                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3672                 goto err_free_channel_map;
3673         }
3674         iwl_init_hw_rates(priv, priv->ieee_rates);
3675
3676         return 0;
3677
3678 err_free_channel_map:
3679         iwl_free_channel_map(priv);
3680 err:
3681         return ret;
3682 }
3683
3684 static void iwl_uninit_drv(struct iwl_priv *priv)
3685 {
3686         iwl_calib_free_results(priv);
3687         iwlcore_free_geos(priv);
3688         iwl_free_channel_map(priv);
3689         kfree(priv->scan_cmd);
3690 }
3691
3692 struct ieee80211_ops iwlagn_hw_ops = {
3693         .tx = iwlagn_mac_tx,
3694         .start = iwlagn_mac_start,
3695         .stop = iwlagn_mac_stop,
3696         .add_interface = iwl_mac_add_interface,
3697         .remove_interface = iwl_mac_remove_interface,
3698         .change_interface = iwl_mac_change_interface,
3699         .config = iwlagn_mac_config,
3700         .configure_filter = iwlagn_configure_filter,
3701         .set_key = iwlagn_mac_set_key,
3702         .update_tkip_key = iwlagn_mac_update_tkip_key,
3703         .conf_tx = iwl_mac_conf_tx,
3704         .bss_info_changed = iwlagn_bss_info_changed,
3705         .ampdu_action = iwlagn_mac_ampdu_action,
3706         .hw_scan = iwl_mac_hw_scan,
3707         .sta_notify = iwlagn_mac_sta_notify,
3708         .sta_add = iwlagn_mac_sta_add,
3709         .sta_remove = iwl_mac_sta_remove,
3710         .channel_switch = iwlagn_mac_channel_switch,
3711         .flush = iwlagn_mac_flush,
3712         .tx_last_beacon = iwl_mac_tx_last_beacon,
3713         .remain_on_channel = iwl_mac_remain_on_channel,
3714         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3715         .offchannel_tx = iwl_mac_offchannel_tx,
3716         .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3717 };
3718
3719 static void iwl_hw_detect(struct iwl_priv *priv)
3720 {
3721         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
3722         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
3723         priv->rev_id = priv->pci_dev->revision;
3724         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3725 }
3726
3727 static int iwl_set_hw_params(struct iwl_priv *priv)
3728 {
3729         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3730         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3731         if (priv->cfg->mod_params->amsdu_size_8K)
3732                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3733         else
3734                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3735
3736         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3737
3738         if (priv->cfg->mod_params->disable_11n)
3739                 priv->cfg->sku &= ~IWL_SKU_N;
3740
3741         /* Device-specific setup */
3742         return priv->cfg->ops->lib->set_hw_params(priv);
3743 }
3744
3745 static const u8 iwlagn_bss_ac_to_fifo[] = {
3746         IWL_TX_FIFO_VO,
3747         IWL_TX_FIFO_VI,
3748         IWL_TX_FIFO_BE,
3749         IWL_TX_FIFO_BK,
3750 };
3751
3752 static const u8 iwlagn_bss_ac_to_queue[] = {
3753         0, 1, 2, 3,
3754 };
3755
3756 static const u8 iwlagn_pan_ac_to_fifo[] = {
3757         IWL_TX_FIFO_VO_IPAN,
3758         IWL_TX_FIFO_VI_IPAN,
3759         IWL_TX_FIFO_BE_IPAN,
3760         IWL_TX_FIFO_BK_IPAN,
3761 };
3762
3763 static const u8 iwlagn_pan_ac_to_queue[] = {
3764         7, 6, 5, 4,
3765 };
3766
3767 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3768 {
3769         int err = 0, i;
3770         struct iwl_priv *priv;
3771         struct ieee80211_hw *hw;
3772         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3773         unsigned long flags;
3774         u16 pci_cmd, num_mac;
3775
3776         /************************
3777          * 1. Allocating HW data
3778          ************************/
3779
3780         hw = iwl_alloc_all(cfg);
3781         if (!hw) {
3782                 err = -ENOMEM;
3783                 goto out;
3784         }
3785         priv = hw->priv;
3786         /* At this point both hw and priv are allocated. */
3787
3788         /*
3789          * The default context is always valid,
3790          * more may be discovered when firmware
3791          * is loaded.
3792          */
3793         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3794
3795         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3796                 priv->contexts[i].ctxid = i;
3797
3798         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3799         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3800         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3801         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3802         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3803         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3804         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3805         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3806         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3807         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3808         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3809                 BIT(NL80211_IFTYPE_ADHOC);
3810         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3811                 BIT(NL80211_IFTYPE_STATION);
3812         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3813         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3814         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3815         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3816
3817         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3818         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3819         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3820         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3821         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3822         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3823         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3824         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3825         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3826         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3827         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3828         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3829                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3830 #ifdef CONFIG_IWL_P2P
3831         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3832                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3833 #endif
3834         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3835         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3836         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3837
3838         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3839
3840         SET_IEEE80211_DEV(hw, &pdev->dev);
3841
3842         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3843         priv->cfg = cfg;
3844         priv->pci_dev = pdev;
3845         priv->inta_mask = CSR_INI_SET_MASK;
3846
3847         /* is antenna coupling more than 35dB ? */
3848         priv->bt_ant_couple_ok =
3849                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3850                 true : false;
3851
3852         /* enable/disable bt channel inhibition */
3853         priv->bt_ch_announce = iwlagn_bt_ch_announce;
3854         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3855                        (priv->bt_ch_announce) ? "On" : "Off");
3856
3857         if (iwl_alloc_traffic_mem(priv))
3858                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3859
3860         /**************************
3861          * 2. Initializing PCI bus
3862          **************************/
3863         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3864                                 PCIE_LINK_STATE_CLKPM);
3865
3866         if (pci_enable_device(pdev)) {
3867                 err = -ENODEV;
3868                 goto out_ieee80211_free_hw;
3869         }
3870
3871         pci_set_master(pdev);
3872
3873         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3874         if (!err)
3875                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3876         if (err) {
3877                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3878                 if (!err)
3879                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3880                 /* both attempts failed: */
3881                 if (err) {
3882                         IWL_WARN(priv, "No suitable DMA available.\n");
3883                         goto out_pci_disable_device;
3884                 }
3885         }
3886
3887         err = pci_request_regions(pdev, DRV_NAME);
3888         if (err)
3889                 goto out_pci_disable_device;
3890
3891         pci_set_drvdata(pdev, priv);
3892
3893
3894         /***********************
3895          * 3. Read REV register
3896          ***********************/
3897         priv->hw_base = pci_iomap(pdev, 0, 0);
3898         if (!priv->hw_base) {
3899                 err = -ENODEV;
3900                 goto out_pci_release_regions;
3901         }
3902
3903         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3904                 (unsigned long long) pci_resource_len(pdev, 0));
3905         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3906
3907         /* these spin locks will be used in apm_ops.init and EEPROM access
3908          * we should init now
3909          */
3910         spin_lock_init(&priv->reg_lock);
3911         spin_lock_init(&priv->lock);
3912
3913         /*
3914          * stop and reset the on-board processor just in case it is in a
3915          * strange state ... like being left stranded by a primary kernel
3916          * and this is now the kdump kernel trying to start up
3917          */
3918         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3919
3920         iwl_hw_detect(priv);
3921         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3922                 priv->cfg->name, priv->hw_rev);
3923
3924         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3925          * PCI Tx retries from interfering with C3 CPU state */
3926         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3927
3928         iwl_prepare_card_hw(priv);
3929         if (!priv->hw_ready) {
3930                 IWL_WARN(priv, "Failed, HW not ready\n");
3931                 goto out_iounmap;
3932         }
3933
3934         /*****************
3935          * 4. Read EEPROM
3936          *****************/
3937         /* Read the EEPROM */
3938         err = iwl_eeprom_init(priv);
3939         if (err) {
3940                 IWL_ERR(priv, "Unable to init EEPROM\n");
3941                 goto out_iounmap;
3942         }
3943         err = iwl_eeprom_check_version(priv);
3944         if (err)
3945                 goto out_free_eeprom;
3946
3947         err = iwl_eeprom_check_sku(priv);
3948         if (err)
3949                 goto out_free_eeprom;
3950
3951         /* extract MAC Address */
3952         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3953         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3954         priv->hw->wiphy->addresses = priv->addresses;
3955         priv->hw->wiphy->n_addresses = 1;
3956         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3957         if (num_mac > 1) {
3958                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3959                        ETH_ALEN);
3960                 priv->addresses[1].addr[5]++;
3961                 priv->hw->wiphy->n_addresses++;
3962         }
3963
3964         /************************
3965          * 5. Setup HW constants
3966          ************************/
3967         if (iwl_set_hw_params(priv)) {
3968                 IWL_ERR(priv, "failed to set hw parameters\n");
3969                 goto out_free_eeprom;
3970         }
3971
3972         /*******************
3973          * 6. Setup priv
3974          *******************/
3975
3976         err = iwl_init_drv(priv);
3977         if (err)
3978                 goto out_free_eeprom;
3979         /* At this point both hw and priv are initialized. */
3980
3981         /********************
3982          * 7. Setup services
3983          ********************/
3984         spin_lock_irqsave(&priv->lock, flags);
3985         iwl_disable_interrupts(priv);
3986         spin_unlock_irqrestore(&priv->lock, flags);
3987
3988         pci_enable_msi(priv->pci_dev);
3989
3990         if (priv->cfg->ops->lib->isr_ops.alloc)
3991                 priv->cfg->ops->lib->isr_ops.alloc(priv);
3992
3993         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
3994                           IRQF_SHARED, DRV_NAME, priv);
3995         if (err) {
3996                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3997                 goto out_disable_msi;
3998         }
3999
4000         iwl_setup_deferred_work(priv);
4001         iwl_setup_rx_handlers(priv);
4002
4003         /*********************************************
4004          * 8. Enable interrupts and read RFKILL state
4005          *********************************************/
4006
4007         /* enable rfkill interrupt: hw bug w/a */
4008         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4009         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4010                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4011                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4012         }
4013
4014         iwl_enable_rfkill_int(priv);
4015
4016         /* If platform's RF_KILL switch is NOT set to KILL */
4017         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4018                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4019         else
4020                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4021
4022         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4023                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4024
4025         iwl_power_initialize(priv);
4026         iwl_tt_initialize(priv);
4027
4028         init_completion(&priv->_agn.firmware_loading_complete);
4029
4030         err = iwl_request_firmware(priv, true);
4031         if (err)
4032                 goto out_destroy_workqueue;
4033
4034         return 0;
4035
4036  out_destroy_workqueue:
4037         destroy_workqueue(priv->workqueue);
4038         priv->workqueue = NULL;
4039         free_irq(priv->pci_dev->irq, priv);
4040         if (priv->cfg->ops->lib->isr_ops.free)
4041                 priv->cfg->ops->lib->isr_ops.free(priv);
4042  out_disable_msi:
4043         pci_disable_msi(priv->pci_dev);
4044         iwl_uninit_drv(priv);
4045  out_free_eeprom:
4046         iwl_eeprom_free(priv);
4047  out_iounmap:
4048         pci_iounmap(pdev, priv->hw_base);
4049  out_pci_release_regions:
4050         pci_set_drvdata(pdev, NULL);
4051         pci_release_regions(pdev);
4052  out_pci_disable_device:
4053         pci_disable_device(pdev);
4054  out_ieee80211_free_hw:
4055         iwl_free_traffic_mem(priv);
4056         ieee80211_free_hw(priv->hw);
4057  out:
4058         return err;
4059 }
4060
4061 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4062 {
4063         struct iwl_priv *priv = pci_get_drvdata(pdev);
4064         unsigned long flags;
4065
4066         if (!priv)
4067                 return;
4068
4069         wait_for_completion(&priv->_agn.firmware_loading_complete);
4070
4071         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4072
4073         iwl_dbgfs_unregister(priv);
4074         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4075
4076         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4077          * to be called and iwl_down since we are removing the device
4078          * we need to set STATUS_EXIT_PENDING bit.
4079          */
4080         set_bit(STATUS_EXIT_PENDING, &priv->status);
4081
4082         iwl_leds_exit(priv);
4083
4084         if (priv->mac80211_registered) {
4085                 ieee80211_unregister_hw(priv->hw);
4086                 priv->mac80211_registered = 0;
4087         } else {
4088                 iwl_down(priv);
4089         }
4090
4091         /*
4092          * Make sure device is reset to low power before unloading driver.
4093          * This may be redundant with iwl_down(), but there are paths to
4094          * run iwl_down() without calling apm_ops.stop(), and there are
4095          * paths to avoid running iwl_down() at all before leaving driver.
4096          * This (inexpensive) call *makes sure* device is reset.
4097          */
4098         iwl_apm_stop(priv);
4099
4100         iwl_tt_exit(priv);
4101
4102         /* make sure we flush any pending irq or
4103          * tasklet for the driver
4104          */
4105         spin_lock_irqsave(&priv->lock, flags);
4106         iwl_disable_interrupts(priv);
4107         spin_unlock_irqrestore(&priv->lock, flags);
4108
4109         iwl_synchronize_irq(priv);
4110
4111         iwl_dealloc_ucode_pci(priv);
4112
4113         if (priv->rxq.bd)
4114                 iwlagn_rx_queue_free(priv, &priv->rxq);
4115         iwlagn_hw_txq_ctx_free(priv);
4116
4117         iwl_eeprom_free(priv);
4118
4119
4120         /*netif_stop_queue(dev); */
4121         flush_workqueue(priv->workqueue);
4122
4123         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4124          * priv->workqueue... so we can't take down the workqueue
4125          * until now... */
4126         destroy_workqueue(priv->workqueue);
4127         priv->workqueue = NULL;
4128         iwl_free_traffic_mem(priv);
4129
4130         free_irq(priv->pci_dev->irq, priv);
4131         pci_disable_msi(priv->pci_dev);
4132         pci_iounmap(pdev, priv->hw_base);
4133         pci_release_regions(pdev);
4134         pci_disable_device(pdev);
4135         pci_set_drvdata(pdev, NULL);
4136
4137         iwl_uninit_drv(priv);
4138
4139         if (priv->cfg->ops->lib->isr_ops.free)
4140                 priv->cfg->ops->lib->isr_ops.free(priv);
4141
4142         dev_kfree_skb(priv->beacon_skb);
4143
4144         ieee80211_free_hw(priv->hw);
4145 }
4146
4147
4148 /*****************************************************************************
4149  *
4150  * driver and module entry point
4151  *
4152  *****************************************************************************/
4153
4154 /* Hardware specific file defines the PCI IDs table for that hardware module */
4155 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4156         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4157         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4158         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4159         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4160         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4161         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4162         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4163         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4164         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4165         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4166         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4167         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4168         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4169         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4170         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4171         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4172         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4173         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4174         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4175         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4176         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4177         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4178         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4179         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4180
4181 /* 5300 Series WiFi */
4182         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4183         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4184         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4185         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4186         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4187         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4188         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4189         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4190         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4191         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4192         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4193         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4194
4195 /* 5350 Series WiFi/WiMax */
4196         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4197         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4198         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4199
4200 /* 5150 Series Wifi/WiMax */
4201         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4202         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4203         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4204         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4205         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4206         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4207
4208         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4209         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4210         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4211         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4212
4213 /* 6x00 Series */
4214         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4215         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4216         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4217         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4218         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4219         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4220         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4221         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4222         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4223         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4224
4225 /* 6x05 Series */
4226         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4227         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4228         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4229         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4230         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4231         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4232         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4233
4234 /* 6x30 Series */
4235         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4236         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4237         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4238         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4239         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4240         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4241         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4242         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4243         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4244         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4245         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4246         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4247         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4248         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4249         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4250         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4251
4252 /* 6x50 WiFi/WiMax Series */
4253         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4254         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4255         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4256         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4257         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4258         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4259
4260 /* 6150 WiFi/WiMax Series */
4261         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4262         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4263         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4264         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4265         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4266         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4267
4268 /* 1000 Series WiFi */
4269         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4270         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4271         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4272         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4273         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4274         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4275         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4276         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4277         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4278         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4279         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4280         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4281
4282 /* 100 Series WiFi */
4283         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4284         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4285         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4286         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4287         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4288         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4289
4290 /* 130 Series WiFi */
4291         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4292         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4293         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4294         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4295         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4296         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4297
4298 /* 2x00 Series */
4299         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4300         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4301         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4302         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4303         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4304         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4305
4306 /* 2x30 Series */
4307         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4308         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4309         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4310         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4311         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4312         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4313
4314 /* 6x35 Series */
4315         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4316         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4317         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4318         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4319         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4320         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4321         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4322         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4323         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4324
4325 /* 200 Series */
4326         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4327         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4328         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4329         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4330         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4331         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4332
4333 /* 230 Series */
4334         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4335         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4336         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4337         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4338         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4339         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4340
4341         {0}
4342 };
4343 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4344
4345 static struct pci_driver iwl_driver = {
4346         .name = DRV_NAME,
4347         .id_table = iwl_hw_card_ids,
4348         .probe = iwl_pci_probe,
4349         .remove = __devexit_p(iwl_pci_remove),
4350         .driver.pm = IWL_PM_OPS,
4351 };
4352
4353 static int __init iwl_init(void)
4354 {
4355
4356         int ret;
4357         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4358         pr_info(DRV_COPYRIGHT "\n");
4359
4360         ret = iwlagn_rate_control_register();
4361         if (ret) {
4362                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4363                 return ret;
4364         }
4365
4366         ret = pci_register_driver(&iwl_driver);
4367         if (ret) {
4368                 pr_err("Unable to initialize PCI module\n");
4369                 goto error_register;
4370         }
4371
4372         return ret;
4373
4374 error_register:
4375         iwlagn_rate_control_unregister();
4376         return ret;
4377 }
4378
4379 static void __exit iwl_exit(void)
4380 {
4381         pci_unregister_driver(&iwl_driver);
4382         iwlagn_rate_control_unregister();
4383 }
4384
4385 module_exit(iwl_exit);
4386 module_init(iwl_init);
4387
4388 #ifdef CONFIG_IWLWIFI_DEBUG
4389 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4390 MODULE_PARM_DESC(debug, "debug output mask");
4391 #endif
4392
4393 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4394 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4395 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4396 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4397 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4398 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4399 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4400                    int, S_IRUGO);
4401 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4402 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4403 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4404
4405 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4406                    S_IRUGO);
4407 MODULE_PARM_DESC(ucode_alternative,
4408                  "specify ucode alternative to use from ucode file");
4409
4410 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4411 MODULE_PARM_DESC(antenna_coupling,
4412                  "specify antenna coupling in dB (defualt: 0 dB)");
4413
4414 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4415 MODULE_PARM_DESC(bt_ch_inhibition,
4416                  "Disable BT channel inhibition (default: enable)");
4417
4418 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4419 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4420
4421 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4422 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");