iwlagn: use sku capabilities information from EEPROM
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
1 /******************************************************************************
2  *
3  * GPL LICENSE SUMMARY
4  *
5  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of version 2 of the GNU General Public License as
9  * published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but
12  * WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19  * USA
20  *
21  * The full GNU General Public License is included in this distribution
22  * in the file called LICENSE.GPL.
23  *
24  * Contact Information:
25  *  Intel Linux Wireless <ilw@linux.intel.com>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-agn.h"
41 #include "iwl-sta.h"
42
43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
44 {
45         return le32_to_cpup((__le32 *)&tx_resp->status +
46                             tx_resp->frame_count) & MAX_SN;
47 }
48
49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
50 {
51         status &= TX_STATUS_MSK;
52
53         switch (status) {
54         case TX_STATUS_POSTPONE_DELAY:
55                 priv->_agn.reply_tx_stats.pp_delay++;
56                 break;
57         case TX_STATUS_POSTPONE_FEW_BYTES:
58                 priv->_agn.reply_tx_stats.pp_few_bytes++;
59                 break;
60         case TX_STATUS_POSTPONE_BT_PRIO:
61                 priv->_agn.reply_tx_stats.pp_bt_prio++;
62                 break;
63         case TX_STATUS_POSTPONE_QUIET_PERIOD:
64                 priv->_agn.reply_tx_stats.pp_quiet_period++;
65                 break;
66         case TX_STATUS_POSTPONE_CALC_TTAK:
67                 priv->_agn.reply_tx_stats.pp_calc_ttak++;
68                 break;
69         case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70                 priv->_agn.reply_tx_stats.int_crossed_retry++;
71                 break;
72         case TX_STATUS_FAIL_SHORT_LIMIT:
73                 priv->_agn.reply_tx_stats.short_limit++;
74                 break;
75         case TX_STATUS_FAIL_LONG_LIMIT:
76                 priv->_agn.reply_tx_stats.long_limit++;
77                 break;
78         case TX_STATUS_FAIL_FIFO_UNDERRUN:
79                 priv->_agn.reply_tx_stats.fifo_underrun++;
80                 break;
81         case TX_STATUS_FAIL_DRAIN_FLOW:
82                 priv->_agn.reply_tx_stats.drain_flow++;
83                 break;
84         case TX_STATUS_FAIL_RFKILL_FLUSH:
85                 priv->_agn.reply_tx_stats.rfkill_flush++;
86                 break;
87         case TX_STATUS_FAIL_LIFE_EXPIRE:
88                 priv->_agn.reply_tx_stats.life_expire++;
89                 break;
90         case TX_STATUS_FAIL_DEST_PS:
91                 priv->_agn.reply_tx_stats.dest_ps++;
92                 break;
93         case TX_STATUS_FAIL_HOST_ABORTED:
94                 priv->_agn.reply_tx_stats.host_abort++;
95                 break;
96         case TX_STATUS_FAIL_BT_RETRY:
97                 priv->_agn.reply_tx_stats.bt_retry++;
98                 break;
99         case TX_STATUS_FAIL_STA_INVALID:
100                 priv->_agn.reply_tx_stats.sta_invalid++;
101                 break;
102         case TX_STATUS_FAIL_FRAG_DROPPED:
103                 priv->_agn.reply_tx_stats.frag_drop++;
104                 break;
105         case TX_STATUS_FAIL_TID_DISABLE:
106                 priv->_agn.reply_tx_stats.tid_disable++;
107                 break;
108         case TX_STATUS_FAIL_FIFO_FLUSHED:
109                 priv->_agn.reply_tx_stats.fifo_flush++;
110                 break;
111         case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112                 priv->_agn.reply_tx_stats.insuff_cf_poll++;
113                 break;
114         case TX_STATUS_FAIL_PASSIVE_NO_RX:
115                 priv->_agn.reply_tx_stats.fail_hw_drop++;
116                 break;
117         case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
118                 priv->_agn.reply_tx_stats.sta_color_mismatch++;
119                 break;
120         default:
121                 priv->_agn.reply_tx_stats.unknown++;
122                 break;
123         }
124 }
125
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
127 {
128         status &= AGG_TX_STATUS_MSK;
129
130         switch (status) {
131         case AGG_TX_STATE_UNDERRUN_MSK:
132                 priv->_agn.reply_agg_tx_stats.underrun++;
133                 break;
134         case AGG_TX_STATE_BT_PRIO_MSK:
135                 priv->_agn.reply_agg_tx_stats.bt_prio++;
136                 break;
137         case AGG_TX_STATE_FEW_BYTES_MSK:
138                 priv->_agn.reply_agg_tx_stats.few_bytes++;
139                 break;
140         case AGG_TX_STATE_ABORT_MSK:
141                 priv->_agn.reply_agg_tx_stats.abort++;
142                 break;
143         case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144                 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
145                 break;
146         case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147                 priv->_agn.reply_agg_tx_stats.last_sent_try++;
148                 break;
149         case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150                 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
151                 break;
152         case AGG_TX_STATE_SCD_QUERY_MSK:
153                 priv->_agn.reply_agg_tx_stats.scd_query++;
154                 break;
155         case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156                 priv->_agn.reply_agg_tx_stats.bad_crc32++;
157                 break;
158         case AGG_TX_STATE_RESPONSE_MSK:
159                 priv->_agn.reply_agg_tx_stats.response++;
160                 break;
161         case AGG_TX_STATE_DUMP_TX_MSK:
162                 priv->_agn.reply_agg_tx_stats.dump_tx++;
163                 break;
164         case AGG_TX_STATE_DELAY_TX_MSK:
165                 priv->_agn.reply_agg_tx_stats.delay_tx++;
166                 break;
167         default:
168                 priv->_agn.reply_agg_tx_stats.unknown++;
169                 break;
170         }
171 }
172
173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
174                                  struct ieee80211_tx_info *info,
175                                  struct iwl_rxon_context *ctx,
176                                  struct iwlagn_tx_resp *tx_resp,
177                                  int txq_id, bool is_agg)
178 {
179         u16  status = le16_to_cpu(tx_resp->status.status);
180
181         info->status.rates[0].count = tx_resp->failure_frame + 1;
182         if (is_agg)
183                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
184         info->flags |= iwl_tx_status_to_mac80211(status);
185         iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
186                                     info);
187         if (!iwl_is_tx_success(status))
188                 iwlagn_count_tx_err_status(priv, status);
189
190         if (status == TX_STATUS_FAIL_PASSIVE_NO_RX &&
191             iwl_is_associated_ctx(ctx) && ctx->vif &&
192             ctx->vif->type == NL80211_IFTYPE_STATION) {
193                 ctx->last_tx_rejected = true;
194                 iwl_stop_queue(priv, &priv->txq[txq_id]);
195         }
196
197         IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
198                            "0x%x retries %d\n",
199                            txq_id,
200                            iwl_get_tx_fail_reason(status), status,
201                            le32_to_cpu(tx_resp->rate_n_flags),
202                            tx_resp->failure_frame);
203 }
204
205 #ifdef CONFIG_IWLWIFI_DEBUG
206 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
207
208 const char *iwl_get_agg_tx_fail_reason(u16 status)
209 {
210         status &= AGG_TX_STATUS_MSK;
211         switch (status) {
212         case AGG_TX_STATE_TRANSMITTED:
213                 return "SUCCESS";
214                 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
215                 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
216                 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
217                 AGG_TX_STATE_FAIL(ABORT_MSK);
218                 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
219                 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
220                 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
221                 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
222                 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
223                 AGG_TX_STATE_FAIL(RESPONSE_MSK);
224                 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
225                 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
226         }
227
228         return "UNKNOWN";
229 }
230 #endif /* CONFIG_IWLWIFI_DEBUG */
231
232 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
233                                       struct iwl_ht_agg *agg,
234                                       struct iwlagn_tx_resp *tx_resp,
235                                       int txq_id, u16 start_idx)
236 {
237         u16 status;
238         struct agg_tx_status *frame_status = &tx_resp->status;
239         struct ieee80211_hdr *hdr = NULL;
240         int i, sh, idx;
241         u16 seq;
242
243         if (agg->wait_for_ba)
244                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
245
246         agg->frame_count = tx_resp->frame_count;
247         agg->start_idx = start_idx;
248         agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
249         agg->bitmap = 0;
250
251         /* # frames attempted by Tx command */
252         if (agg->frame_count == 1) {
253                 struct iwl_tx_info *txb;
254
255                 /* Only one frame was attempted; no block-ack will arrive */
256                 idx = start_idx;
257
258                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
259                                    agg->frame_count, agg->start_idx, idx);
260                 txb = &priv->txq[txq_id].txb[idx];
261                 iwlagn_set_tx_status(priv, IEEE80211_SKB_CB(txb->skb),
262                                      txb->ctx, tx_resp, txq_id, true);
263                 agg->wait_for_ba = 0;
264         } else {
265                 /* Two or more frames were attempted; expect block-ack */
266                 u64 bitmap = 0;
267
268                 /*
269                  * Start is the lowest frame sent. It may not be the first
270                  * frame in the batch; we figure this out dynamically during
271                  * the following loop.
272                  */
273                 int start = agg->start_idx;
274
275                 /* Construct bit-map of pending frames within Tx window */
276                 for (i = 0; i < agg->frame_count; i++) {
277                         u16 sc;
278                         status = le16_to_cpu(frame_status[i].status);
279                         seq  = le16_to_cpu(frame_status[i].sequence);
280                         idx = SEQ_TO_INDEX(seq);
281                         txq_id = SEQ_TO_QUEUE(seq);
282
283                         if (status & AGG_TX_STATUS_MSK)
284                                 iwlagn_count_agg_tx_err_status(priv, status);
285
286                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
287                                       AGG_TX_STATE_ABORT_MSK))
288                                 continue;
289
290                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
291                                            agg->frame_count, txq_id, idx);
292                         IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
293                                            "try-count (0x%08x)\n",
294                                            iwl_get_agg_tx_fail_reason(status),
295                                            status & AGG_TX_STATUS_MSK,
296                                            status & AGG_TX_TRY_MSK);
297
298                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
299                         if (!hdr) {
300                                 IWL_ERR(priv,
301                                         "BUG_ON idx doesn't point to valid skb"
302                                         " idx=%d, txq_id=%d\n", idx, txq_id);
303                                 return -1;
304                         }
305
306                         sc = le16_to_cpu(hdr->seq_ctrl);
307                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
308                                 IWL_ERR(priv,
309                                         "BUG_ON idx doesn't match seq control"
310                                         " idx=%d, seq_idx=%d, seq=%d\n",
311                                           idx, SEQ_TO_SN(sc),
312                                           hdr->seq_ctrl);
313                                 return -1;
314                         }
315
316                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
317                                            i, idx, SEQ_TO_SN(sc));
318
319                         /*
320                          * sh -> how many frames ahead of the starting frame is
321                          * the current one?
322                          *
323                          * Note that all frames sent in the batch must be in a
324                          * 64-frame window, so this number should be in [0,63].
325                          * If outside of this window, then we've found a new
326                          * "first" frame in the batch and need to change start.
327                          */
328                         sh = idx - start;
329
330                         /*
331                          * If >= 64, out of window. start must be at the front
332                          * of the circular buffer, idx must be near the end of
333                          * the buffer, and idx is the new "first" frame. Shift
334                          * the indices around.
335                          */
336                         if (sh >= 64) {
337                                 /* Shift bitmap by start - idx, wrapped */
338                                 sh = 0x100 - idx + start;
339                                 bitmap = bitmap << sh;
340                                 /* Now idx is the new start so sh = 0 */
341                                 sh = 0;
342                                 start = idx;
343                         /*
344                          * If <= -64 then wraps the 256-pkt circular buffer
345                          * (e.g., start = 255 and idx = 0, sh should be 1)
346                          */
347                         } else if (sh <= -64) {
348                                 sh  = 0x100 - start + idx;
349                         /*
350                          * If < 0 but > -64, out of window. idx is before start
351                          * but not wrapped. Shift the indices around.
352                          */
353                         } else if (sh < 0) {
354                                 /* Shift by how far start is ahead of idx */
355                                 sh = start - idx;
356                                 bitmap = bitmap << sh;
357                                 /* Now idx is the new start so sh = 0 */
358                                 start = idx;
359                                 sh = 0;
360                         }
361                         /* Sequence number start + sh was sent in this batch */
362                         bitmap |= 1ULL << sh;
363                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
364                                            start, (unsigned long long)bitmap);
365                 }
366
367                 /*
368                  * Store the bitmap and possibly the new start, if we wrapped
369                  * the buffer above
370                  */
371                 agg->bitmap = bitmap;
372                 agg->start_idx = start;
373                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
374                                    agg->frame_count, agg->start_idx,
375                                    (unsigned long long)agg->bitmap);
376
377                 if (bitmap)
378                         agg->wait_for_ba = 1;
379         }
380         return 0;
381 }
382
383 void iwl_check_abort_status(struct iwl_priv *priv,
384                             u8 frame_count, u32 status)
385 {
386         if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
387                 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
388                 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
389                         queue_work(priv->workqueue, &priv->tx_flush);
390         }
391 }
392
393 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
394                                 struct iwl_rx_mem_buffer *rxb)
395 {
396         struct iwl_rx_packet *pkt = rxb_addr(rxb);
397         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
398         int txq_id = SEQ_TO_QUEUE(sequence);
399         int index = SEQ_TO_INDEX(sequence);
400         struct iwl_tx_queue *txq = &priv->txq[txq_id];
401         struct ieee80211_tx_info *info;
402         struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
403         struct iwl_tx_info *txb;
404         u32 status = le16_to_cpu(tx_resp->status.status);
405         int tid;
406         int sta_id;
407         int freed;
408         unsigned long flags;
409
410         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
411                 IWL_ERR(priv, "%s: Read index for DMA queue txq_id (%d) "
412                           "index %d is out of range [0-%d] %d %d\n", __func__,
413                           txq_id, index, txq->q.n_bd, txq->q.write_ptr,
414                           txq->q.read_ptr);
415                 return;
416         }
417
418         txq->time_stamp = jiffies;
419         txb = &txq->txb[txq->q.read_ptr];
420         info = IEEE80211_SKB_CB(txb->skb);
421         memset(&info->status, 0, sizeof(info->status));
422
423         tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
424                 IWLAGN_TX_RES_TID_POS;
425         sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
426                 IWLAGN_TX_RES_RA_POS;
427
428         spin_lock_irqsave(&priv->sta_lock, flags);
429         if (txq->sched_retry) {
430                 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
431                 struct iwl_ht_agg *agg;
432
433                 agg = &priv->stations[sta_id].tid[tid].agg;
434                 /*
435                  * If the BT kill count is non-zero, we'll get this
436                  * notification again.
437                  */
438                 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
439                     priv->cfg->bt_params &&
440                     priv->cfg->bt_params->advanced_bt_coexist) {
441                         IWL_WARN(priv, "receive reply tx with bt_kill\n");
442                 }
443                 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
444
445                 /* check if BAR is needed */
446                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
447                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
448
449                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
450                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
451                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
452                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
453                                         scd_ssn , index, txq_id, txq->swq_id);
454
455                         freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
456                         iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
457
458                         if (priv->mac80211_registered &&
459                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
460                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
461                                 iwl_wake_queue(priv, txq);
462                 }
463         } else {
464                 iwlagn_set_tx_status(priv, info, txb->ctx, tx_resp,
465                                      txq_id, false);
466                 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
467                 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
468
469                 if (priv->mac80211_registered &&
470                     iwl_queue_space(&txq->q) > txq->q.low_mark &&
471                     status != TX_STATUS_FAIL_PASSIVE_NO_RX)
472                         iwl_wake_queue(priv, txq);
473         }
474
475         iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
476
477         iwl_check_abort_status(priv, tx_resp->frame_count, status);
478         spin_unlock_irqrestore(&priv->sta_lock, flags);
479 }
480
481 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
482 {
483         /* init calibration handlers */
484         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
485                                         iwlagn_rx_calib_result;
486         priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
487
488         /* set up notification wait support */
489         spin_lock_init(&priv->_agn.notif_wait_lock);
490         INIT_LIST_HEAD(&priv->_agn.notif_waits);
491         init_waitqueue_head(&priv->_agn.notif_waitq);
492 }
493
494 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
495 {
496         /*
497          * nothing need to be done here anymore
498          * still keep for future use if needed
499          */
500 }
501
502 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
503 {
504         return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
505                 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
506 }
507
508 int iwlagn_send_tx_power(struct iwl_priv *priv)
509 {
510         struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
511         u8 tx_ant_cfg_cmd;
512
513         if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
514                       "TX Power requested while scanning!\n"))
515                 return -EAGAIN;
516
517         /* half dBm need to multiply */
518         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
519
520         if (priv->tx_power_lmt_in_half_dbm &&
521             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
522                 /*
523                  * For the newer devices which using enhanced/extend tx power
524                  * table in EEPROM, the format is in half dBm. driver need to
525                  * convert to dBm format before report to mac80211.
526                  * By doing so, there is a possibility of 1/2 dBm resolution
527                  * lost. driver will perform "round-up" operation before
528                  * reporting, but it will cause 1/2 dBm tx power over the
529                  * regulatory limit. Perform the checking here, if the
530                  * "tx_power_user_lmt" is higher than EEPROM value (in
531                  * half-dBm format), lower the tx power based on EEPROM
532                  */
533                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
534         }
535         tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
536         tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
537
538         if (IWL_UCODE_API(priv->ucode_ver) == 1)
539                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
540         else
541                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
542
543         return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
544                                 &tx_power_cmd);
545 }
546
547 void iwlagn_temperature(struct iwl_priv *priv)
548 {
549         /* store temperature from correct statistics (in Celsius) */
550         priv->temperature = le32_to_cpu(priv->statistics.common.temperature);
551         iwl_tt_handler(priv);
552 }
553
554 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
555 {
556         struct iwl_eeprom_calib_hdr {
557                 u8 version;
558                 u8 pa_type;
559                 u16 voltage;
560         } *hdr;
561
562         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
563                                                         EEPROM_CALIB_ALL);
564         return hdr->version;
565
566 }
567
568 /*
569  * EEPROM
570  */
571 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
572 {
573         u16 offset = 0;
574
575         if ((address & INDIRECT_ADDRESS) == 0)
576                 return address;
577
578         switch (address & INDIRECT_TYPE_MSK) {
579         case INDIRECT_HOST:
580                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
581                 break;
582         case INDIRECT_GENERAL:
583                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
584                 break;
585         case INDIRECT_REGULATORY:
586                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
587                 break;
588         case INDIRECT_TXP_LIMIT:
589                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
590                 break;
591         case INDIRECT_TXP_LIMIT_SIZE:
592                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
593                 break;
594         case INDIRECT_CALIBRATION:
595                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
596                 break;
597         case INDIRECT_PROCESS_ADJST:
598                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
599                 break;
600         case INDIRECT_OTHERS:
601                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
602                 break;
603         default:
604                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
605                 address & INDIRECT_TYPE_MSK);
606                 break;
607         }
608
609         /* translate the offset from words to byte */
610         return (address & ADDRESS_MSK) + (offset << 1);
611 }
612
613 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
614                                            size_t offset)
615 {
616         u32 address = eeprom_indirect_address(priv, offset);
617         BUG_ON(address >= priv->cfg->base_params->eeprom_size);
618         return &priv->eeprom[address];
619 }
620
621 struct iwl_mod_params iwlagn_mod_params = {
622         .amsdu_size_8K = 1,
623         .restart_fw = 1,
624         .plcp_check = true,
625         .bt_coex_active = true,
626         .no_sleep_autoadjust = true,
627         /* the rest are 0 by default */
628 };
629
630 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
631 {
632         unsigned long flags;
633         int i;
634         spin_lock_irqsave(&rxq->lock, flags);
635         INIT_LIST_HEAD(&rxq->rx_free);
636         INIT_LIST_HEAD(&rxq->rx_used);
637         /* Fill the rx_used queue with _all_ of the Rx buffers */
638         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
639                 /* In the reset function, these buffers may have been allocated
640                  * to an SKB, so we need to unmap and free potential storage */
641                 if (rxq->pool[i].page != NULL) {
642                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
643                                 PAGE_SIZE << priv->hw_params.rx_page_order,
644                                 PCI_DMA_FROMDEVICE);
645                         __iwl_free_pages(priv, rxq->pool[i].page);
646                         rxq->pool[i].page = NULL;
647                 }
648                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
649         }
650
651         for (i = 0; i < RX_QUEUE_SIZE; i++)
652                 rxq->queue[i] = NULL;
653
654         /* Set us so that we have processed and used all buffers, but have
655          * not restocked the Rx queue with fresh buffers */
656         rxq->read = rxq->write = 0;
657         rxq->write_actual = 0;
658         rxq->free_count = 0;
659         spin_unlock_irqrestore(&rxq->lock, flags);
660 }
661
662 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
663 {
664         u32 rb_size;
665         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
666         u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
667
668         rb_timeout = RX_RB_TIMEOUT;
669
670         if (iwlagn_mod_params.amsdu_size_8K)
671                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
672         else
673                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
674
675         /* Stop Rx DMA */
676         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
677
678         /* Reset driver's Rx queue write index */
679         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
680
681         /* Tell device where to find RBD circular buffer in DRAM */
682         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
683                            (u32)(rxq->bd_dma >> 8));
684
685         /* Tell device where in DRAM to update its Rx status */
686         iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
687                            rxq->rb_stts_dma >> 4);
688
689         /* Enable Rx DMA
690          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
691          *      the credit mechanism in 5000 HW RX FIFO
692          * Direct rx interrupts to hosts
693          * Rx buffer size 4 or 8k
694          * RB timeout 0x10
695          * 256 RBDs
696          */
697         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
698                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
699                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
700                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
701                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
702                            rb_size|
703                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
704                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
705
706         /* Set interrupt coalescing timer to default (2048 usecs) */
707         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
708
709         return 0;
710 }
711
712 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
713 {
714 /*
715  * (for documentation purposes)
716  * to set power to V_AUX, do:
717
718                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
719                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
720                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
721                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
722  */
723
724         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
725                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
726                                ~APMG_PS_CTRL_MSK_PWR_SRC);
727 }
728
729 int iwlagn_hw_nic_init(struct iwl_priv *priv)
730 {
731         unsigned long flags;
732         struct iwl_rx_queue *rxq = &priv->rxq;
733         int ret;
734
735         /* nic_init */
736         spin_lock_irqsave(&priv->lock, flags);
737         priv->cfg->ops->lib->apm_ops.init(priv);
738
739         /* Set interrupt coalescing calibration timer to default (512 usecs) */
740         iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
741
742         spin_unlock_irqrestore(&priv->lock, flags);
743
744         iwlagn_set_pwr_vmain(priv);
745
746         priv->cfg->ops->lib->apm_ops.config(priv);
747
748         /* Allocate the RX queue, or reset if it is already allocated */
749         if (!rxq->bd) {
750                 ret = iwl_rx_queue_alloc(priv);
751                 if (ret) {
752                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
753                         return -ENOMEM;
754                 }
755         } else
756                 iwlagn_rx_queue_reset(priv, rxq);
757
758         iwlagn_rx_replenish(priv);
759
760         iwlagn_rx_init(priv, rxq);
761
762         spin_lock_irqsave(&priv->lock, flags);
763
764         rxq->need_update = 1;
765         iwl_rx_queue_update_write_ptr(priv, rxq);
766
767         spin_unlock_irqrestore(&priv->lock, flags);
768
769         /* Allocate or reset and init all Tx and Command queues */
770         if (!priv->txq) {
771                 ret = iwlagn_txq_ctx_alloc(priv);
772                 if (ret)
773                         return ret;
774         } else
775                 iwlagn_txq_ctx_reset(priv);
776
777         if (priv->cfg->base_params->shadow_reg_enable) {
778                 /* enable shadow regs in HW */
779                 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
780                         0x800FFFFF);
781         }
782
783         set_bit(STATUS_INIT, &priv->status);
784
785         return 0;
786 }
787
788 /**
789  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
790  */
791 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
792                                           dma_addr_t dma_addr)
793 {
794         return cpu_to_le32((u32)(dma_addr >> 8));
795 }
796
797 /**
798  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
799  *
800  * If there are slots in the RX queue that need to be restocked,
801  * and we have free pre-allocated buffers, fill the ranks as much
802  * as we can, pulling from rx_free.
803  *
804  * This moves the 'write' index forward to catch up with 'processed', and
805  * also updates the memory address in the firmware to reference the new
806  * target buffer.
807  */
808 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
809 {
810         struct iwl_rx_queue *rxq = &priv->rxq;
811         struct list_head *element;
812         struct iwl_rx_mem_buffer *rxb;
813         unsigned long flags;
814
815         spin_lock_irqsave(&rxq->lock, flags);
816         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
817                 /* The overwritten rxb must be a used one */
818                 rxb = rxq->queue[rxq->write];
819                 BUG_ON(rxb && rxb->page);
820
821                 /* Get next free Rx buffer, remove from free list */
822                 element = rxq->rx_free.next;
823                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
824                 list_del(element);
825
826                 /* Point to Rx buffer via next RBD in circular buffer */
827                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
828                                                               rxb->page_dma);
829                 rxq->queue[rxq->write] = rxb;
830                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
831                 rxq->free_count--;
832         }
833         spin_unlock_irqrestore(&rxq->lock, flags);
834         /* If the pre-allocated buffer pool is dropping low, schedule to
835          * refill it */
836         if (rxq->free_count <= RX_LOW_WATERMARK)
837                 queue_work(priv->workqueue, &priv->rx_replenish);
838
839
840         /* If we've added more space for the firmware to place data, tell it.
841          * Increment device's write pointer in multiples of 8. */
842         if (rxq->write_actual != (rxq->write & ~0x7)) {
843                 spin_lock_irqsave(&rxq->lock, flags);
844                 rxq->need_update = 1;
845                 spin_unlock_irqrestore(&rxq->lock, flags);
846                 iwl_rx_queue_update_write_ptr(priv, rxq);
847         }
848 }
849
850 /**
851  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
852  *
853  * When moving to rx_free an SKB is allocated for the slot.
854  *
855  * Also restock the Rx queue via iwl_rx_queue_restock.
856  * This is called as a scheduled work item (except for during initialization)
857  */
858 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
859 {
860         struct iwl_rx_queue *rxq = &priv->rxq;
861         struct list_head *element;
862         struct iwl_rx_mem_buffer *rxb;
863         struct page *page;
864         unsigned long flags;
865         gfp_t gfp_mask = priority;
866
867         while (1) {
868                 spin_lock_irqsave(&rxq->lock, flags);
869                 if (list_empty(&rxq->rx_used)) {
870                         spin_unlock_irqrestore(&rxq->lock, flags);
871                         return;
872                 }
873                 spin_unlock_irqrestore(&rxq->lock, flags);
874
875                 if (rxq->free_count > RX_LOW_WATERMARK)
876                         gfp_mask |= __GFP_NOWARN;
877
878                 if (priv->hw_params.rx_page_order > 0)
879                         gfp_mask |= __GFP_COMP;
880
881                 /* Alloc a new receive buffer */
882                 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
883                 if (!page) {
884                         if (net_ratelimit())
885                                 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
886                                                "order: %d\n",
887                                                priv->hw_params.rx_page_order);
888
889                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
890                             net_ratelimit())
891                                 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
892                                          priority == GFP_ATOMIC ?  "GFP_ATOMIC" : "GFP_KERNEL",
893                                          rxq->free_count);
894                         /* We don't reschedule replenish work here -- we will
895                          * call the restock method and if it still needs
896                          * more buffers it will schedule replenish */
897                         return;
898                 }
899
900                 spin_lock_irqsave(&rxq->lock, flags);
901
902                 if (list_empty(&rxq->rx_used)) {
903                         spin_unlock_irqrestore(&rxq->lock, flags);
904                         __free_pages(page, priv->hw_params.rx_page_order);
905                         return;
906                 }
907                 element = rxq->rx_used.next;
908                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
909                 list_del(element);
910
911                 spin_unlock_irqrestore(&rxq->lock, flags);
912
913                 BUG_ON(rxb->page);
914                 rxb->page = page;
915                 /* Get physical address of the RB */
916                 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
917                                 PAGE_SIZE << priv->hw_params.rx_page_order,
918                                 PCI_DMA_FROMDEVICE);
919                 /* dma address must be no more than 36 bits */
920                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
921                 /* and also 256 byte aligned! */
922                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
923
924                 spin_lock_irqsave(&rxq->lock, flags);
925
926                 list_add_tail(&rxb->list, &rxq->rx_free);
927                 rxq->free_count++;
928
929                 spin_unlock_irqrestore(&rxq->lock, flags);
930         }
931 }
932
933 void iwlagn_rx_replenish(struct iwl_priv *priv)
934 {
935         unsigned long flags;
936
937         iwlagn_rx_allocate(priv, GFP_KERNEL);
938
939         spin_lock_irqsave(&priv->lock, flags);
940         iwlagn_rx_queue_restock(priv);
941         spin_unlock_irqrestore(&priv->lock, flags);
942 }
943
944 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
945 {
946         iwlagn_rx_allocate(priv, GFP_ATOMIC);
947
948         iwlagn_rx_queue_restock(priv);
949 }
950
951 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
952  * If an SKB has been detached, the POOL needs to have its SKB set to NULL
953  * This free routine walks the list of POOL entries and if SKB is set to
954  * non NULL it is unmapped and freed
955  */
956 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
957 {
958         int i;
959         for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
960                 if (rxq->pool[i].page != NULL) {
961                         pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
962                                 PAGE_SIZE << priv->hw_params.rx_page_order,
963                                 PCI_DMA_FROMDEVICE);
964                         __iwl_free_pages(priv, rxq->pool[i].page);
965                         rxq->pool[i].page = NULL;
966                 }
967         }
968
969         dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
970                           rxq->bd_dma);
971         dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
972                           rxq->rb_stts, rxq->rb_stts_dma);
973         rxq->bd = NULL;
974         rxq->rb_stts  = NULL;
975 }
976
977 int iwlagn_rxq_stop(struct iwl_priv *priv)
978 {
979
980         /* stop Rx DMA */
981         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
982         iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
983                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
984
985         return 0;
986 }
987
988 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
989 {
990         int idx = 0;
991         int band_offset = 0;
992
993         /* HT rate format: mac80211 wants an MCS number, which is just LSB */
994         if (rate_n_flags & RATE_MCS_HT_MSK) {
995                 idx = (rate_n_flags & 0xff);
996                 return idx;
997         /* Legacy rate format, search for match in table */
998         } else {
999                 if (band == IEEE80211_BAND_5GHZ)
1000                         band_offset = IWL_FIRST_OFDM_RATE;
1001                 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
1002                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
1003                                 return idx - band_offset;
1004         }
1005
1006         return -1;
1007 }
1008
1009 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1010                                            struct ieee80211_vif *vif,
1011                                            enum ieee80211_band band,
1012                                            struct iwl_scan_channel *scan_ch)
1013 {
1014         const struct ieee80211_supported_band *sband;
1015         u16 passive_dwell = 0;
1016         u16 active_dwell = 0;
1017         int added = 0;
1018         u16 channel = 0;
1019
1020         sband = iwl_get_hw_mode(priv, band);
1021         if (!sband) {
1022                 IWL_ERR(priv, "invalid band\n");
1023                 return added;
1024         }
1025
1026         active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1027         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1028
1029         if (passive_dwell <= active_dwell)
1030                 passive_dwell = active_dwell + 1;
1031
1032         channel = iwl_get_single_channel_number(priv, band);
1033         if (channel) {
1034                 scan_ch->channel = cpu_to_le16(channel);
1035                 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1036                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1037                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1038                 /* Set txpower levels to defaults */
1039                 scan_ch->dsp_atten = 110;
1040                 if (band == IEEE80211_BAND_5GHZ)
1041                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1042                 else
1043                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1044                 added++;
1045         } else
1046                 IWL_ERR(priv, "no valid channel found\n");
1047         return added;
1048 }
1049
1050 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1051                                      struct ieee80211_vif *vif,
1052                                      enum ieee80211_band band,
1053                                      u8 is_active, u8 n_probes,
1054                                      struct iwl_scan_channel *scan_ch)
1055 {
1056         struct ieee80211_channel *chan;
1057         const struct ieee80211_supported_band *sband;
1058         const struct iwl_channel_info *ch_info;
1059         u16 passive_dwell = 0;
1060         u16 active_dwell = 0;
1061         int added, i;
1062         u16 channel;
1063
1064         sband = iwl_get_hw_mode(priv, band);
1065         if (!sband)
1066                 return 0;
1067
1068         active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1069         passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1070
1071         if (passive_dwell <= active_dwell)
1072                 passive_dwell = active_dwell + 1;
1073
1074         for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1075                 chan = priv->scan_request->channels[i];
1076
1077                 if (chan->band != band)
1078                         continue;
1079
1080                 channel = chan->hw_value;
1081                 scan_ch->channel = cpu_to_le16(channel);
1082
1083                 ch_info = iwl_get_channel_info(priv, band, channel);
1084                 if (!is_channel_valid(ch_info)) {
1085                         IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1086                                         channel);
1087                         continue;
1088                 }
1089
1090                 if (!is_active || is_channel_passive(ch_info) ||
1091                     (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1092                         scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1093                 else
1094                         scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1095
1096                 if (n_probes)
1097                         scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1098
1099                 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1100                 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1101
1102                 /* Set txpower levels to defaults */
1103                 scan_ch->dsp_atten = 110;
1104
1105                 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1106                  * power level:
1107                  * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1108                  */
1109                 if (band == IEEE80211_BAND_5GHZ)
1110                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1111                 else
1112                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1113
1114                 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1115                                channel, le32_to_cpu(scan_ch->type),
1116                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1117                                 "ACTIVE" : "PASSIVE",
1118                                (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1119                                active_dwell : passive_dwell);
1120
1121                 scan_ch++;
1122                 added++;
1123         }
1124
1125         IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1126         return added;
1127 }
1128
1129 static int iwl_fill_offch_tx(struct iwl_priv *priv, void *data, size_t maxlen)
1130 {
1131         struct sk_buff *skb = priv->_agn.offchan_tx_skb;
1132
1133         if (skb->len < maxlen)
1134                 maxlen = skb->len;
1135
1136         memcpy(data, skb->data, maxlen);
1137
1138         return maxlen;
1139 }
1140
1141 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1142 {
1143         struct iwl_host_cmd cmd = {
1144                 .id = REPLY_SCAN_CMD,
1145                 .len = { sizeof(struct iwl_scan_cmd), },
1146         };
1147         struct iwl_scan_cmd *scan;
1148         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1149         u32 rate_flags = 0;
1150         u16 cmd_len;
1151         u16 rx_chain = 0;
1152         enum ieee80211_band band;
1153         u8 n_probes = 0;
1154         u8 rx_ant = priv->hw_params.valid_rx_ant;
1155         u8 rate;
1156         bool is_active = false;
1157         int  chan_mod;
1158         u8 active_chains;
1159         u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1160         int ret;
1161
1162         lockdep_assert_held(&priv->mutex);
1163
1164         if (vif)
1165                 ctx = iwl_rxon_ctx_from_vif(vif);
1166
1167         if (!priv->scan_cmd) {
1168                 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1169                                          IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1170                 if (!priv->scan_cmd) {
1171                         IWL_DEBUG_SCAN(priv,
1172                                        "fail to allocate memory for scan\n");
1173                         return -ENOMEM;
1174                 }
1175         }
1176         scan = priv->scan_cmd;
1177         memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1178
1179         scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1180         scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1181
1182         if (priv->scan_type != IWL_SCAN_OFFCH_TX &&
1183             iwl_is_any_associated(priv)) {
1184                 u16 interval = 0;
1185                 u32 extra;
1186                 u32 suspend_time = 100;
1187                 u32 scan_suspend_time = 100;
1188
1189                 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1190                 switch (priv->scan_type) {
1191                 case IWL_SCAN_OFFCH_TX:
1192                         WARN_ON(1);
1193                         break;
1194                 case IWL_SCAN_RADIO_RESET:
1195                         interval = 0;
1196                         break;
1197                 case IWL_SCAN_NORMAL:
1198                         interval = vif->bss_conf.beacon_int;
1199                         break;
1200                 }
1201
1202                 scan->suspend_time = 0;
1203                 scan->max_out_time = cpu_to_le32(200 * 1024);
1204                 if (!interval)
1205                         interval = suspend_time;
1206
1207                 extra = (suspend_time / interval) << 22;
1208                 scan_suspend_time = (extra |
1209                     ((suspend_time % interval) * 1024));
1210                 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1211                 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1212                                scan_suspend_time, interval);
1213         } else if (priv->scan_type == IWL_SCAN_OFFCH_TX) {
1214                 scan->suspend_time = 0;
1215                 scan->max_out_time =
1216                         cpu_to_le32(1024 * priv->_agn.offchan_tx_timeout);
1217         }
1218
1219         switch (priv->scan_type) {
1220         case IWL_SCAN_RADIO_RESET:
1221                 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1222                 break;
1223         case IWL_SCAN_NORMAL:
1224                 if (priv->scan_request->n_ssids) {
1225                         int i, p = 0;
1226                         IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1227                         for (i = 0; i < priv->scan_request->n_ssids; i++) {
1228                                 /* always does wildcard anyway */
1229                                 if (!priv->scan_request->ssids[i].ssid_len)
1230                                         continue;
1231                                 scan->direct_scan[p].id = WLAN_EID_SSID;
1232                                 scan->direct_scan[p].len =
1233                                         priv->scan_request->ssids[i].ssid_len;
1234                                 memcpy(scan->direct_scan[p].ssid,
1235                                        priv->scan_request->ssids[i].ssid,
1236                                        priv->scan_request->ssids[i].ssid_len);
1237                                 n_probes++;
1238                                 p++;
1239                         }
1240                         is_active = true;
1241                 } else
1242                         IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1243                 break;
1244         case IWL_SCAN_OFFCH_TX:
1245                 IWL_DEBUG_SCAN(priv, "Start offchannel TX scan.\n");
1246                 break;
1247         }
1248
1249         scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1250         scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1251         scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1252
1253         switch (priv->scan_band) {
1254         case IEEE80211_BAND_2GHZ:
1255                 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1256                 chan_mod = le32_to_cpu(
1257                         priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1258                                                 RXON_FLG_CHANNEL_MODE_MSK)
1259                                        >> RXON_FLG_CHANNEL_MODE_POS;
1260                 if (chan_mod == CHANNEL_MODE_PURE_40) {
1261                         rate = IWL_RATE_6M_PLCP;
1262                 } else {
1263                         rate = IWL_RATE_1M_PLCP;
1264                         rate_flags = RATE_MCS_CCK_MSK;
1265                 }
1266                 /*
1267                  * Internal scans are passive, so we can indiscriminately set
1268                  * the BT ignore flag on 2.4 GHz since it applies to TX only.
1269                  */
1270                 if (priv->cfg->bt_params &&
1271                     priv->cfg->bt_params->advanced_bt_coexist)
1272                         scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1273                 break;
1274         case IEEE80211_BAND_5GHZ:
1275                 rate = IWL_RATE_6M_PLCP;
1276                 break;
1277         default:
1278                 IWL_WARN(priv, "Invalid scan band\n");
1279                 return -EIO;
1280         }
1281
1282         /*
1283          * If active scanning is requested but a certain channel is
1284          * marked passive, we can do active scanning if we detect
1285          * transmissions.
1286          *
1287          * There is an issue with some firmware versions that triggers
1288          * a sysassert on a "good CRC threshold" of zero (== disabled),
1289          * on a radar channel even though this means that we should NOT
1290          * send probes.
1291          *
1292          * The "good CRC threshold" is the number of frames that we
1293          * need to receive during our dwell time on a channel before
1294          * sending out probes -- setting this to a huge value will
1295          * mean we never reach it, but at the same time work around
1296          * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1297          * here instead of IWL_GOOD_CRC_TH_DISABLED.
1298          *
1299          * This was fixed in later versions along with some other
1300          * scan changes, and the threshold behaves as a flag in those
1301          * versions.
1302          */
1303         if (priv->new_scan_threshold_behaviour)
1304                 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1305                                                 IWL_GOOD_CRC_TH_DISABLED;
1306         else
1307                 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1308                                                 IWL_GOOD_CRC_TH_NEVER;
1309
1310         band = priv->scan_band;
1311
1312         if (priv->cfg->scan_rx_antennas[band])
1313                 rx_ant = priv->cfg->scan_rx_antennas[band];
1314
1315         if (band == IEEE80211_BAND_2GHZ &&
1316             priv->cfg->bt_params &&
1317             priv->cfg->bt_params->advanced_bt_coexist) {
1318                 /* transmit 2.4 GHz probes only on first antenna */
1319                 scan_tx_antennas = first_antenna(scan_tx_antennas);
1320         }
1321
1322         priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1323                                                     scan_tx_antennas);
1324         rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1325         scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1326
1327         /* In power save mode use one chain, otherwise use all chains */
1328         if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1329                 /* rx_ant has been set to all valid chains previously */
1330                 active_chains = rx_ant &
1331                                 ((u8)(priv->chain_noise_data.active_chains));
1332                 if (!active_chains)
1333                         active_chains = rx_ant;
1334
1335                 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1336                                 priv->chain_noise_data.active_chains);
1337
1338                 rx_ant = first_antenna(active_chains);
1339         }
1340         if (priv->cfg->bt_params &&
1341             priv->cfg->bt_params->advanced_bt_coexist &&
1342             priv->bt_full_concurrent) {
1343                 /* operated as 1x1 in full concurrency mode */
1344                 rx_ant = first_antenna(rx_ant);
1345         }
1346
1347         /* MIMO is not used here, but value is required */
1348         rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1349         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1350         rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1351         rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1352         scan->rx_chain = cpu_to_le16(rx_chain);
1353         switch (priv->scan_type) {
1354         case IWL_SCAN_NORMAL:
1355                 cmd_len = iwl_fill_probe_req(priv,
1356                                         (struct ieee80211_mgmt *)scan->data,
1357                                         vif->addr,
1358                                         priv->scan_request->ie,
1359                                         priv->scan_request->ie_len,
1360                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1361                 break;
1362         case IWL_SCAN_RADIO_RESET:
1363                 /* use bcast addr, will not be transmitted but must be valid */
1364                 cmd_len = iwl_fill_probe_req(priv,
1365                                         (struct ieee80211_mgmt *)scan->data,
1366                                         iwl_bcast_addr, NULL, 0,
1367                                         IWL_MAX_SCAN_SIZE - sizeof(*scan));
1368                 break;
1369         case IWL_SCAN_OFFCH_TX:
1370                 cmd_len = iwl_fill_offch_tx(priv, scan->data,
1371                                             IWL_MAX_SCAN_SIZE
1372                                              - sizeof(*scan)
1373                                              - sizeof(struct iwl_scan_channel));
1374                 scan->scan_flags |= IWL_SCAN_FLAGS_ACTION_FRAME_TX;
1375                 break;
1376         default:
1377                 BUG();
1378         }
1379         scan->tx_cmd.len = cpu_to_le16(cmd_len);
1380
1381         scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1382                                RXON_FILTER_BCON_AWARE_MSK);
1383
1384         switch (priv->scan_type) {
1385         case IWL_SCAN_RADIO_RESET:
1386                 scan->channel_count =
1387                         iwl_get_single_channel_for_scan(priv, vif, band,
1388                                 (void *)&scan->data[cmd_len]);
1389                 break;
1390         case IWL_SCAN_NORMAL:
1391                 scan->channel_count =
1392                         iwl_get_channels_for_scan(priv, vif, band,
1393                                 is_active, n_probes,
1394                                 (void *)&scan->data[cmd_len]);
1395                 break;
1396         case IWL_SCAN_OFFCH_TX: {
1397                 struct iwl_scan_channel *scan_ch;
1398
1399                 scan->channel_count = 1;
1400
1401                 scan_ch = (void *)&scan->data[cmd_len];
1402                 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1403                 scan_ch->channel =
1404                         cpu_to_le16(priv->_agn.offchan_tx_chan->hw_value);
1405                 scan_ch->active_dwell =
1406                         cpu_to_le16(priv->_agn.offchan_tx_timeout);
1407                 scan_ch->passive_dwell = 0;
1408
1409                 /* Set txpower levels to defaults */
1410                 scan_ch->dsp_atten = 110;
1411
1412                 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1413                  * power level:
1414                  * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1415                  */
1416                 if (priv->_agn.offchan_tx_chan->band == IEEE80211_BAND_5GHZ)
1417                         scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1418                 else
1419                         scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1420                 }
1421                 break;
1422         }
1423
1424         if (scan->channel_count == 0) {
1425                 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1426                 return -EIO;
1427         }
1428
1429         cmd.len[0] += le16_to_cpu(scan->tx_cmd.len) +
1430             scan->channel_count * sizeof(struct iwl_scan_channel);
1431         cmd.data[0] = scan;
1432         cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
1433         scan->len = cpu_to_le16(cmd.len[0]);
1434
1435         /* set scan bit here for PAN params */
1436         set_bit(STATUS_SCAN_HW, &priv->status);
1437
1438         if (priv->cfg->ops->hcmd->set_pan_params) {
1439                 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1440                 if (ret)
1441                         return ret;
1442         }
1443
1444         ret = iwl_send_cmd_sync(priv, &cmd);
1445         if (ret) {
1446                 clear_bit(STATUS_SCAN_HW, &priv->status);
1447                 if (priv->cfg->ops->hcmd->set_pan_params)
1448                         priv->cfg->ops->hcmd->set_pan_params(priv);
1449         }
1450
1451         return ret;
1452 }
1453
1454 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1455                                struct ieee80211_vif *vif, bool add)
1456 {
1457         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1458
1459         if (add)
1460                 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1461                                                 vif->bss_conf.bssid,
1462                                                 &vif_priv->ibss_bssid_sta_id);
1463         return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1464                                   vif->bss_conf.bssid);
1465 }
1466
1467 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1468                             int sta_id, int tid, int freed)
1469 {
1470         lockdep_assert_held(&priv->sta_lock);
1471
1472         if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1473                 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1474         else {
1475                 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1476                         priv->stations[sta_id].tid[tid].tfds_in_queue,
1477                         freed);
1478                 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1479         }
1480 }
1481
1482 #define IWL_FLUSH_WAIT_MS       2000
1483
1484 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1485 {
1486         struct iwl_tx_queue *txq;
1487         struct iwl_queue *q;
1488         int cnt;
1489         unsigned long now = jiffies;
1490         int ret = 0;
1491
1492         /* waiting for all the tx frames complete might take a while */
1493         for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1494                 if (cnt == priv->cmd_queue)
1495                         continue;
1496                 txq = &priv->txq[cnt];
1497                 q = &txq->q;
1498                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1499                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1500                                 msleep(1);
1501
1502                 if (q->read_ptr != q->write_ptr) {
1503                         IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1504                         ret = -ETIMEDOUT;
1505                         break;
1506                 }
1507         }
1508         return ret;
1509 }
1510
1511 #define IWL_TX_QUEUE_MSK        0xfffff
1512
1513 /**
1514  * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1515  *
1516  * pre-requirements:
1517  *  1. acquire mutex before calling
1518  *  2. make sure rf is on and not in exit state
1519  */
1520 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1521 {
1522         struct iwl_txfifo_flush_cmd flush_cmd;
1523         struct iwl_host_cmd cmd = {
1524                 .id = REPLY_TXFIFO_FLUSH,
1525                 .len = { sizeof(struct iwl_txfifo_flush_cmd), },
1526                 .flags = CMD_SYNC,
1527                 .data = { &flush_cmd, },
1528         };
1529
1530         might_sleep();
1531
1532         memset(&flush_cmd, 0, sizeof(flush_cmd));
1533         flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1534                                  IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1535         if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
1536                 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1537
1538         IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1539                        flush_cmd.fifo_control);
1540         flush_cmd.flush_control = cpu_to_le16(flush_control);
1541
1542         return iwl_send_cmd(priv, &cmd);
1543 }
1544
1545 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1546 {
1547         mutex_lock(&priv->mutex);
1548         ieee80211_stop_queues(priv->hw);
1549         if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1550                 IWL_ERR(priv, "flush request fail\n");
1551                 goto done;
1552         }
1553         IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1554         iwlagn_wait_tx_queue_empty(priv);
1555 done:
1556         ieee80211_wake_queues(priv->hw);
1557         mutex_unlock(&priv->mutex);
1558 }
1559
1560 /*
1561  * BT coex
1562  */
1563 /*
1564  * Macros to access the lookup table.
1565  *
1566  * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1567 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1568  *
1569  * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1570  *
1571  * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1572  * one after another in 32-bit registers, and "registers" 0 through 7 contain
1573  * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1574  *
1575  * These macros encode that format.
1576  */
1577 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1578                   wifi_txrx, wifi_sh_ant_req) \
1579         (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1580         (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1581
1582 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1583         lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1584 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1585                                  wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1586         (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1587                                    bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1588                                    wifi_sh_ant_req))))
1589 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1590                                 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1591         LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1592                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1593                                wifi_sh_ant_req))
1594 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1595                                   wifi_req, wifi_prio, wifi_txrx, \
1596                                   wifi_sh_ant_req) \
1597         LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1598                                bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1599                                wifi_sh_ant_req))
1600
1601 #define LUT_WLAN_KILL_OP(lut, op, val) \
1602         lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1603 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1604                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1605         (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1606                              wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1607 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1608                           wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1609         LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1610                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1611 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1612                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1613         LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1614                          wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1615
1616 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1617         lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1618 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1619                             wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1620         (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1621                               wifi_req, wifi_prio, wifi_txrx, \
1622                               wifi_sh_ant_req))))
1623 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1624                            wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1625         LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1626                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1627 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1628                              wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1629         LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1630                           wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1631
1632 static const __le32 iwlagn_def_3w_lookup[12] = {
1633         cpu_to_le32(0xaaaaaaaa),
1634         cpu_to_le32(0xaaaaaaaa),
1635         cpu_to_le32(0xaeaaaaaa),
1636         cpu_to_le32(0xaaaaaaaa),
1637         cpu_to_le32(0xcc00ff28),
1638         cpu_to_le32(0x0000aaaa),
1639         cpu_to_le32(0xcc00aaaa),
1640         cpu_to_le32(0x0000aaaa),
1641         cpu_to_le32(0xc0004000),
1642         cpu_to_le32(0x00004000),
1643         cpu_to_le32(0xf0005000),
1644         cpu_to_le32(0xf0005000),
1645 };
1646
1647 static const __le32 iwlagn_concurrent_lookup[12] = {
1648         cpu_to_le32(0xaaaaaaaa),
1649         cpu_to_le32(0xaaaaaaaa),
1650         cpu_to_le32(0xaaaaaaaa),
1651         cpu_to_le32(0xaaaaaaaa),
1652         cpu_to_le32(0xaaaaaaaa),
1653         cpu_to_le32(0xaaaaaaaa),
1654         cpu_to_le32(0xaaaaaaaa),
1655         cpu_to_le32(0xaaaaaaaa),
1656         cpu_to_le32(0x00000000),
1657         cpu_to_le32(0x00000000),
1658         cpu_to_le32(0x00000000),
1659         cpu_to_le32(0x00000000),
1660 };
1661
1662 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1663 {
1664         struct iwl_basic_bt_cmd basic = {
1665                 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1666                 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1667                 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1668                 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1669         };
1670         struct iwl6000_bt_cmd bt_cmd_6000;
1671         struct iwl2000_bt_cmd bt_cmd_2000;
1672         int ret;
1673
1674         BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1675                         sizeof(basic.bt3_lookup_table));
1676
1677         if (priv->cfg->bt_params) {
1678                 if (priv->cfg->bt_params->bt_session_2) {
1679                         bt_cmd_2000.prio_boost = cpu_to_le32(
1680                                 priv->cfg->bt_params->bt_prio_boost);
1681                         bt_cmd_2000.tx_prio_boost = 0;
1682                         bt_cmd_2000.rx_prio_boost = 0;
1683                 } else {
1684                         bt_cmd_6000.prio_boost =
1685                                 priv->cfg->bt_params->bt_prio_boost;
1686                         bt_cmd_6000.tx_prio_boost = 0;
1687                         bt_cmd_6000.rx_prio_boost = 0;
1688                 }
1689         } else {
1690                 IWL_ERR(priv, "failed to construct BT Coex Config\n");
1691                 return;
1692         }
1693
1694         basic.kill_ack_mask = priv->kill_ack_mask;
1695         basic.kill_cts_mask = priv->kill_cts_mask;
1696         basic.valid = priv->bt_valid;
1697
1698         /*
1699          * Configure BT coex mode to "no coexistence" when the
1700          * user disabled BT coexistence, we have no interface
1701          * (might be in monitor mode), or the interface is in
1702          * IBSS mode (no proper uCode support for coex then).
1703          */
1704         if (!iwlagn_mod_params.bt_coex_active ||
1705             priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1706                 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED;
1707         } else {
1708                 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1709                                         IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1710                 if (priv->cfg->bt_params &&
1711                     priv->cfg->bt_params->bt_sco_disable)
1712                         basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1713
1714                 if (priv->bt_ch_announce)
1715                         basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1716                 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", basic.flags);
1717         }
1718         priv->bt_enable_flag = basic.flags;
1719         if (priv->bt_full_concurrent)
1720                 memcpy(basic.bt3_lookup_table, iwlagn_concurrent_lookup,
1721                         sizeof(iwlagn_concurrent_lookup));
1722         else
1723                 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup,
1724                         sizeof(iwlagn_def_3w_lookup));
1725
1726         IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1727                        basic.flags ? "active" : "disabled",
1728                        priv->bt_full_concurrent ?
1729                        "full concurrency" : "3-wire");
1730
1731         if (priv->cfg->bt_params->bt_session_2) {
1732                 memcpy(&bt_cmd_2000.basic, &basic,
1733                         sizeof(basic));
1734                 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1735                         sizeof(bt_cmd_2000), &bt_cmd_2000);
1736         } else {
1737                 memcpy(&bt_cmd_6000.basic, &basic,
1738                         sizeof(basic));
1739                 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1740                         sizeof(bt_cmd_6000), &bt_cmd_6000);
1741         }
1742         if (ret)
1743                 IWL_ERR(priv, "failed to send BT Coex Config\n");
1744
1745 }
1746
1747 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1748 {
1749         struct iwl_priv *priv =
1750                 container_of(work, struct iwl_priv, bt_traffic_change_work);
1751         struct iwl_rxon_context *ctx;
1752         int smps_request = -1;
1753
1754         if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1755                 /* bt coex disabled */
1756                 return;
1757         }
1758
1759         /*
1760          * Note: bt_traffic_load can be overridden by scan complete and
1761          * coex profile notifications. Ignore that since only bad consequence
1762          * can be not matching debug print with actual state.
1763          */
1764         IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1765                        priv->bt_traffic_load);
1766
1767         switch (priv->bt_traffic_load) {
1768         case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1769                 if (priv->bt_status)
1770                         smps_request = IEEE80211_SMPS_DYNAMIC;
1771                 else
1772                         smps_request = IEEE80211_SMPS_AUTOMATIC;
1773                 break;
1774         case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1775                 smps_request = IEEE80211_SMPS_DYNAMIC;
1776                 break;
1777         case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1778         case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1779                 smps_request = IEEE80211_SMPS_STATIC;
1780                 break;
1781         default:
1782                 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1783                         priv->bt_traffic_load);
1784                 break;
1785         }
1786
1787         mutex_lock(&priv->mutex);
1788
1789         /*
1790          * We can not send command to firmware while scanning. When the scan
1791          * complete we will schedule this work again. We do check with mutex
1792          * locked to prevent new scan request to arrive. We do not check
1793          * STATUS_SCANNING to avoid race when queue_work two times from
1794          * different notifications, but quit and not perform any work at all.
1795          */
1796         if (test_bit(STATUS_SCAN_HW, &priv->status))
1797                 goto out;
1798
1799         if (priv->cfg->ops->lib->update_chain_flags)
1800                 priv->cfg->ops->lib->update_chain_flags(priv);
1801
1802         if (smps_request != -1) {
1803                 priv->current_ht_config.smps = smps_request;
1804                 for_each_context(priv, ctx) {
1805                         if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1806                                 ieee80211_request_smps(ctx->vif, smps_request);
1807                 }
1808         }
1809 out:
1810         mutex_unlock(&priv->mutex);
1811 }
1812
1813 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1814                                 struct iwl_bt_uart_msg *uart_msg)
1815 {
1816         IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1817                         "Update Req = 0x%X",
1818                 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1819                         BT_UART_MSG_FRAME1MSGTYPE_POS,
1820                 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1821                         BT_UART_MSG_FRAME1SSN_POS,
1822                 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1823                         BT_UART_MSG_FRAME1UPDATEREQ_POS);
1824
1825         IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1826                         "Chl_SeqN = 0x%X, In band = 0x%X",
1827                 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1828                         BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1829                 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1830                         BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1831                 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1832                         BT_UART_MSG_FRAME2CHLSEQN_POS,
1833                 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1834                         BT_UART_MSG_FRAME2INBAND_POS);
1835
1836         IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1837                         "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1838                 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1839                         BT_UART_MSG_FRAME3SCOESCO_POS,
1840                 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1841                         BT_UART_MSG_FRAME3SNIFF_POS,
1842                 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1843                         BT_UART_MSG_FRAME3A2DP_POS,
1844                 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1845                         BT_UART_MSG_FRAME3ACL_POS,
1846                 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1847                         BT_UART_MSG_FRAME3MASTER_POS,
1848                 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1849                         BT_UART_MSG_FRAME3OBEX_POS);
1850
1851         IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1852                 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1853                         BT_UART_MSG_FRAME4IDLEDURATION_POS);
1854
1855         IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1856                         "eSCO Retransmissions = 0x%X",
1857                 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1858                         BT_UART_MSG_FRAME5TXACTIVITY_POS,
1859                 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1860                         BT_UART_MSG_FRAME5RXACTIVITY_POS,
1861                 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1862                         BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1863
1864         IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1865                 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1866                         BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1867                 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1868                         BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1869
1870         IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Page = "
1871                         "0x%X, Inquiry = 0x%X, Connectable = 0x%X",
1872                 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1873                         BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1874                 (BT_UART_MSG_FRAME7PAGE_MSK & uart_msg->frame7) >>
1875                         BT_UART_MSG_FRAME7PAGE_POS,
1876                 (BT_UART_MSG_FRAME7INQUIRY_MSK & uart_msg->frame7) >>
1877                         BT_UART_MSG_FRAME7INQUIRY_POS,
1878                 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1879                         BT_UART_MSG_FRAME7CONNECTABLE_POS);
1880 }
1881
1882 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
1883                                 struct iwl_bt_uart_msg *uart_msg)
1884 {
1885         u8 kill_msk;
1886         static const __le32 bt_kill_ack_msg[2] = {
1887                 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
1888                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1889         static const __le32 bt_kill_cts_msg[2] = {
1890                 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
1891                 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1892
1893         kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
1894                 ? 1 : 0;
1895         if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
1896             priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
1897                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1898                 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
1899                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
1900                 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
1901
1902                 /* schedule to send runtime bt_config */
1903                 queue_work(priv->workqueue, &priv->bt_runtime_config);
1904         }
1905 }
1906
1907 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1908                                              struct iwl_rx_mem_buffer *rxb)
1909 {
1910         unsigned long flags;
1911         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1912         struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1913         struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1914
1915         if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1916                 /* bt coex disabled */
1917                 return;
1918         }
1919
1920         IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
1921         IWL_DEBUG_NOTIF(priv, "    status: %d\n", coex->bt_status);
1922         IWL_DEBUG_NOTIF(priv, "    traffic load: %d\n", coex->bt_traffic_load);
1923         IWL_DEBUG_NOTIF(priv, "    CI compliance: %d\n",
1924                         coex->bt_ci_compliance);
1925         iwlagn_print_uartmsg(priv, uart_msg);
1926
1927         priv->last_bt_traffic_load = priv->bt_traffic_load;
1928         if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1929                 if (priv->bt_status != coex->bt_status ||
1930                     priv->last_bt_traffic_load != coex->bt_traffic_load) {
1931                         if (coex->bt_status) {
1932                                 /* BT on */
1933                                 if (!priv->bt_ch_announce)
1934                                         priv->bt_traffic_load =
1935                                                 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1936                                 else
1937                                         priv->bt_traffic_load =
1938                                                 coex->bt_traffic_load;
1939                         } else {
1940                                 /* BT off */
1941                                 priv->bt_traffic_load =
1942                                         IWL_BT_COEX_TRAFFIC_LOAD_NONE;
1943                         }
1944                         priv->bt_status = coex->bt_status;
1945                         queue_work(priv->workqueue,
1946                                    &priv->bt_traffic_change_work);
1947                 }
1948         }
1949
1950         iwlagn_set_kill_msk(priv, uart_msg);
1951
1952         /* FIXME: based on notification, adjust the prio_boost */
1953
1954         spin_lock_irqsave(&priv->lock, flags);
1955         priv->bt_ci_compliance = coex->bt_ci_compliance;
1956         spin_unlock_irqrestore(&priv->lock, flags);
1957 }
1958
1959 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1960 {
1961         iwlagn_rx_handler_setup(priv);
1962         priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1963                 iwlagn_bt_coex_profile_notif;
1964 }
1965
1966 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1967 {
1968         iwlagn_setup_deferred_work(priv);
1969
1970         INIT_WORK(&priv->bt_traffic_change_work,
1971                   iwlagn_bt_traffic_change_work);
1972 }
1973
1974 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
1975 {
1976         cancel_work_sync(&priv->bt_traffic_change_work);
1977 }
1978
1979 static bool is_single_rx_stream(struct iwl_priv *priv)
1980 {
1981         return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1982                priv->current_ht_config.single_chain_sufficient;
1983 }
1984
1985 #define IWL_NUM_RX_CHAINS_MULTIPLE      3
1986 #define IWL_NUM_RX_CHAINS_SINGLE        2
1987 #define IWL_NUM_IDLE_CHAINS_DUAL        2
1988 #define IWL_NUM_IDLE_CHAINS_SINGLE      1
1989
1990 /*
1991  * Determine how many receiver/antenna chains to use.
1992  *
1993  * More provides better reception via diversity.  Fewer saves power
1994  * at the expense of throughput, but only when not in powersave to
1995  * start with.
1996  *
1997  * MIMO (dual stream) requires at least 2, but works better with 3.
1998  * This does not determine *which* chains to use, just how many.
1999  */
2000 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
2001 {
2002         if (priv->cfg->bt_params &&
2003             priv->cfg->bt_params->advanced_bt_coexist &&
2004             (priv->bt_full_concurrent ||
2005              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2006                 /*
2007                  * only use chain 'A' in bt high traffic load or
2008                  * full concurrency mode
2009                  */
2010                 return IWL_NUM_RX_CHAINS_SINGLE;
2011         }
2012         /* # of Rx chains to use when expecting MIMO. */
2013         if (is_single_rx_stream(priv))
2014                 return IWL_NUM_RX_CHAINS_SINGLE;
2015         else
2016                 return IWL_NUM_RX_CHAINS_MULTIPLE;
2017 }
2018
2019 /*
2020  * When we are in power saving mode, unless device support spatial
2021  * multiplexing power save, use the active count for rx chain count.
2022  */
2023 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
2024 {
2025         /* # Rx chains when idling, depending on SMPS mode */
2026         switch (priv->current_ht_config.smps) {
2027         case IEEE80211_SMPS_STATIC:
2028         case IEEE80211_SMPS_DYNAMIC:
2029                 return IWL_NUM_IDLE_CHAINS_SINGLE;
2030         case IEEE80211_SMPS_OFF:
2031                 return active_cnt;
2032         default:
2033                 WARN(1, "invalid SMPS mode %d",
2034                      priv->current_ht_config.smps);
2035                 return active_cnt;
2036         }
2037 }
2038
2039 /* up to 4 chains */
2040 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
2041 {
2042         u8 res;
2043         res = (chain_bitmap & BIT(0)) >> 0;
2044         res += (chain_bitmap & BIT(1)) >> 1;
2045         res += (chain_bitmap & BIT(2)) >> 2;
2046         res += (chain_bitmap & BIT(3)) >> 3;
2047         return res;
2048 }
2049
2050 /**
2051  * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2052  *
2053  * Selects how many and which Rx receivers/antennas/chains to use.
2054  * This should not be used for scan command ... it puts data in wrong place.
2055  */
2056 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
2057 {
2058         bool is_single = is_single_rx_stream(priv);
2059         bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
2060         u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
2061         u32 active_chains;
2062         u16 rx_chain;
2063
2064         /* Tell uCode which antennas are actually connected.
2065          * Before first association, we assume all antennas are connected.
2066          * Just after first association, iwl_chain_noise_calibration()
2067          *    checks which antennas actually *are* connected. */
2068         if (priv->chain_noise_data.active_chains)
2069                 active_chains = priv->chain_noise_data.active_chains;
2070         else
2071                 active_chains = priv->hw_params.valid_rx_ant;
2072
2073         if (priv->cfg->bt_params &&
2074             priv->cfg->bt_params->advanced_bt_coexist &&
2075             (priv->bt_full_concurrent ||
2076              priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
2077                 /*
2078                  * only use chain 'A' in bt high traffic load or
2079                  * full concurrency mode
2080                  */
2081                 active_chains = first_antenna(active_chains);
2082         }
2083
2084         rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
2085
2086         /* How many receivers should we use? */
2087         active_rx_cnt = iwl_get_active_rx_chain_count(priv);
2088         idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
2089
2090
2091         /* correct rx chain count according hw settings
2092          * and chain noise calibration
2093          */
2094         valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2095         if (valid_rx_cnt < active_rx_cnt)
2096                 active_rx_cnt = valid_rx_cnt;
2097
2098         if (valid_rx_cnt < idle_rx_cnt)
2099                 idle_rx_cnt = valid_rx_cnt;
2100
2101         rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2102         rx_chain |= idle_rx_cnt  << RXON_RX_CHAIN_CNT_POS;
2103
2104         ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2105
2106         if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2107                 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2108         else
2109                 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2110
2111         IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2112                         ctx->staging.rx_chain,
2113                         active_rx_cnt, idle_rx_cnt);
2114
2115         WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2116                 active_rx_cnt < idle_rx_cnt);
2117 }
2118
2119 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2120 {
2121         int i;
2122         u8 ind = ant;
2123
2124         if (priv->band == IEEE80211_BAND_2GHZ &&
2125             priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2126                 return 0;
2127
2128         for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2129                 ind = (ind + 1) < RATE_ANT_NUM ?  ind + 1 : 0;
2130                 if (valid & BIT(ind))
2131                         return ind;
2132         }
2133         return ant;
2134 }
2135
2136 static const char *get_csr_string(int cmd)
2137 {
2138         switch (cmd) {
2139         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2140         IWL_CMD(CSR_INT_COALESCING);
2141         IWL_CMD(CSR_INT);
2142         IWL_CMD(CSR_INT_MASK);
2143         IWL_CMD(CSR_FH_INT_STATUS);
2144         IWL_CMD(CSR_GPIO_IN);
2145         IWL_CMD(CSR_RESET);
2146         IWL_CMD(CSR_GP_CNTRL);
2147         IWL_CMD(CSR_HW_REV);
2148         IWL_CMD(CSR_EEPROM_REG);
2149         IWL_CMD(CSR_EEPROM_GP);
2150         IWL_CMD(CSR_OTP_GP_REG);
2151         IWL_CMD(CSR_GIO_REG);
2152         IWL_CMD(CSR_GP_UCODE_REG);
2153         IWL_CMD(CSR_GP_DRIVER_REG);
2154         IWL_CMD(CSR_UCODE_DRV_GP1);
2155         IWL_CMD(CSR_UCODE_DRV_GP2);
2156         IWL_CMD(CSR_LED_REG);
2157         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2158         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2159         IWL_CMD(CSR_ANA_PLL_CFG);
2160         IWL_CMD(CSR_HW_REV_WA_REG);
2161         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2162         default:
2163                 return "UNKNOWN";
2164         }
2165 }
2166
2167 void iwl_dump_csr(struct iwl_priv *priv)
2168 {
2169         int i;
2170         static const u32 csr_tbl[] = {
2171                 CSR_HW_IF_CONFIG_REG,
2172                 CSR_INT_COALESCING,
2173                 CSR_INT,
2174                 CSR_INT_MASK,
2175                 CSR_FH_INT_STATUS,
2176                 CSR_GPIO_IN,
2177                 CSR_RESET,
2178                 CSR_GP_CNTRL,
2179                 CSR_HW_REV,
2180                 CSR_EEPROM_REG,
2181                 CSR_EEPROM_GP,
2182                 CSR_OTP_GP_REG,
2183                 CSR_GIO_REG,
2184                 CSR_GP_UCODE_REG,
2185                 CSR_GP_DRIVER_REG,
2186                 CSR_UCODE_DRV_GP1,
2187                 CSR_UCODE_DRV_GP2,
2188                 CSR_LED_REG,
2189                 CSR_DRAM_INT_TBL_REG,
2190                 CSR_GIO_CHICKEN_BITS,
2191                 CSR_ANA_PLL_CFG,
2192                 CSR_HW_REV_WA_REG,
2193                 CSR_DBG_HPET_MEM_REG
2194         };
2195         IWL_ERR(priv, "CSR values:\n");
2196         IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2197                 "CSR_INT_PERIODIC_REG)\n");
2198         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2199                 IWL_ERR(priv, "  %25s: 0X%08x\n",
2200                         get_csr_string(csr_tbl[i]),
2201                         iwl_read32(priv, csr_tbl[i]));
2202         }
2203 }
2204
2205 static const char *get_fh_string(int cmd)
2206 {
2207         switch (cmd) {
2208         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2209         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2210         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2211         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2212         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2213         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2214         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2215         IWL_CMD(FH_TSSR_TX_STATUS_REG);
2216         IWL_CMD(FH_TSSR_TX_ERROR_REG);
2217         default:
2218                 return "UNKNOWN";
2219         }
2220 }
2221
2222 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2223 {
2224         int i;
2225 #ifdef CONFIG_IWLWIFI_DEBUG
2226         int pos = 0;
2227         size_t bufsz = 0;
2228 #endif
2229         static const u32 fh_tbl[] = {
2230                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2231                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2232                 FH_RSCSR_CHNL0_WPTR,
2233                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2234                 FH_MEM_RSSR_SHARED_CTRL_REG,
2235                 FH_MEM_RSSR_RX_STATUS_REG,
2236                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2237                 FH_TSSR_TX_STATUS_REG,
2238                 FH_TSSR_TX_ERROR_REG
2239         };
2240 #ifdef CONFIG_IWLWIFI_DEBUG
2241         if (display) {
2242                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2243                 *buf = kmalloc(bufsz, GFP_KERNEL);
2244                 if (!*buf)
2245                         return -ENOMEM;
2246                 pos += scnprintf(*buf + pos, bufsz - pos,
2247                                 "FH register values:\n");
2248                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2249                         pos += scnprintf(*buf + pos, bufsz - pos,
2250                                 "  %34s: 0X%08x\n",
2251                                 get_fh_string(fh_tbl[i]),
2252                                 iwl_read_direct32(priv, fh_tbl[i]));
2253                 }
2254                 return pos;
2255         }
2256 #endif
2257         IWL_ERR(priv, "FH register values:\n");
2258         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
2259                 IWL_ERR(priv, "  %34s: 0X%08x\n",
2260                         get_fh_string(fh_tbl[i]),
2261                         iwl_read_direct32(priv, fh_tbl[i]));
2262         }
2263         return 0;
2264 }
2265
2266 /* notification wait support */
2267 void iwlagn_init_notification_wait(struct iwl_priv *priv,
2268                                    struct iwl_notification_wait *wait_entry,
2269                                    u8 cmd,
2270                                    void (*fn)(struct iwl_priv *priv,
2271                                               struct iwl_rx_packet *pkt,
2272                                               void *data),
2273                                    void *fn_data)
2274 {
2275         wait_entry->fn = fn;
2276         wait_entry->fn_data = fn_data;
2277         wait_entry->cmd = cmd;
2278         wait_entry->triggered = false;
2279         wait_entry->aborted = false;
2280
2281         spin_lock_bh(&priv->_agn.notif_wait_lock);
2282         list_add(&wait_entry->list, &priv->_agn.notif_waits);
2283         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2284 }
2285
2286 int iwlagn_wait_notification(struct iwl_priv *priv,
2287                              struct iwl_notification_wait *wait_entry,
2288                              unsigned long timeout)
2289 {
2290         int ret;
2291
2292         ret = wait_event_timeout(priv->_agn.notif_waitq,
2293                                  wait_entry->triggered || wait_entry->aborted,
2294                                  timeout);
2295
2296         spin_lock_bh(&priv->_agn.notif_wait_lock);
2297         list_del(&wait_entry->list);
2298         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2299
2300         if (wait_entry->aborted)
2301                 return -EIO;
2302
2303         /* return value is always >= 0 */
2304         if (ret <= 0)
2305                 return -ETIMEDOUT;
2306         return 0;
2307 }
2308
2309 void iwlagn_remove_notification(struct iwl_priv *priv,
2310                                 struct iwl_notification_wait *wait_entry)
2311 {
2312         spin_lock_bh(&priv->_agn.notif_wait_lock);
2313         list_del(&wait_entry->list);
2314         spin_unlock_bh(&priv->_agn.notif_wait_lock);
2315 }
2316
2317 int iwlagn_start_device(struct iwl_priv *priv)
2318 {
2319         int ret;
2320
2321         if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
2322              iwl_prepare_card_hw(priv)) {
2323                 IWL_WARN(priv, "Exit HW not ready\n");
2324                 return -EIO;
2325         }
2326
2327         /* If platform's RF_KILL switch is NOT set to KILL */
2328         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2329                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2330         else
2331                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2332
2333         if (iwl_is_rfkill(priv)) {
2334                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2335                 iwl_enable_interrupts(priv);
2336                 return -ERFKILL;
2337         }
2338
2339         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2340
2341         ret = iwlagn_hw_nic_init(priv);
2342         if (ret) {
2343                 IWL_ERR(priv, "Unable to init nic\n");
2344                 return ret;
2345         }
2346
2347         /* make sure rfkill handshake bits are cleared */
2348         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2349         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2350                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2351
2352         /* clear (again), then enable host interrupts */
2353         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2354         iwl_enable_interrupts(priv);
2355
2356         /* really make sure rfkill handshake bits are cleared */
2357         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2358         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2359
2360         return 0;
2361 }
2362
2363 void iwlagn_stop_device(struct iwl_priv *priv)
2364 {
2365         unsigned long flags;
2366
2367         /* stop and reset the on-board processor */
2368         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2369
2370         /* tell the device to stop sending interrupts */
2371         spin_lock_irqsave(&priv->lock, flags);
2372         iwl_disable_interrupts(priv);
2373         spin_unlock_irqrestore(&priv->lock, flags);
2374         iwl_synchronize_irq(priv);
2375
2376         /* device going down, Stop using ICT table */
2377         iwl_disable_ict(priv);
2378
2379         /*
2380          * If a HW restart happens during firmware loading,
2381          * then the firmware loading might call this function
2382          * and later it might be called again due to the
2383          * restart. So don't process again if the device is
2384          * already dead.
2385          */
2386         if (test_bit(STATUS_DEVICE_ENABLED, &priv->status)) {
2387                 iwlagn_txq_ctx_stop(priv);
2388                 iwlagn_rxq_stop(priv);
2389
2390                 /* Power-down device's busmaster DMA clocks */
2391                 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2392                 udelay(5);
2393         }
2394
2395         /* Make sure (redundant) we've released our request to stay awake */
2396         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2397
2398         /* Stop the device, and put it in low power state */
2399         iwl_apm_stop(priv);
2400 }