iwlwifi: add TX aggregation code for 5000 HW
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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12  * more details.
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25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/version.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <net/mac80211.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39
40 #include "iwl-eeprom.h"
41 #include "iwl-dev.h"
42 #include "iwl-core.h"
43 #include "iwl-io.h"
44 #include "iwl-sta.h"
45 #include "iwl-helpers.h"
46 #include "iwl-5000-hw.h"
47
48 #define IWL5000_UCODE_API  "-1"
49
50 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
51         IWL_TX_FIFO_AC3,
52         IWL_TX_FIFO_AC2,
53         IWL_TX_FIFO_AC1,
54         IWL_TX_FIFO_AC0,
55         IWL50_CMD_FIFO_NUM,
56         IWL_TX_FIFO_HCCA_1,
57         IWL_TX_FIFO_HCCA_2
58 };
59
60 /* FIXME: same implementation as 4965 */
61 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
62 {
63         int ret = 0;
64         unsigned long flags;
65
66         spin_lock_irqsave(&priv->lock, flags);
67
68         /* set stop master bit */
69         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
70
71         ret = iwl_poll_bit(priv, CSR_RESET,
72                                   CSR_RESET_REG_FLAG_MASTER_DISABLED,
73                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
74         if (ret < 0)
75                 goto out;
76
77 out:
78         spin_unlock_irqrestore(&priv->lock, flags);
79         IWL_DEBUG_INFO("stop master\n");
80
81         return ret;
82 }
83
84
85 static int iwl5000_apm_init(struct iwl_priv *priv)
86 {
87         int ret = 0;
88
89         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
90                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
91
92         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
93         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
94                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
95
96         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
97
98         /* set "initialization complete" bit to move adapter
99          * D0U* --> D0A* state */
100         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
101
102         /* wait for clock stabilization */
103         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
104                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
105                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
106         if (ret < 0) {
107                 IWL_DEBUG_INFO("Failed to init the card\n");
108                 return ret;
109         }
110
111         ret = iwl_grab_nic_access(priv);
112         if (ret)
113                 return ret;
114
115         /* enable DMA */
116         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
117
118         udelay(20);
119
120         /* disable L1-Active */
121         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
122                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
123
124         iwl_release_nic_access(priv);
125
126         return ret;
127 }
128
129 /* FIXME: this is indentical to 4965 */
130 static void iwl5000_apm_stop(struct iwl_priv *priv)
131 {
132         unsigned long flags;
133
134         iwl5000_apm_stop_master(priv);
135
136         spin_lock_irqsave(&priv->lock, flags);
137
138         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
139
140         udelay(10);
141
142         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
143
144         spin_unlock_irqrestore(&priv->lock, flags);
145 }
146
147
148 static int iwl5000_apm_reset(struct iwl_priv *priv)
149 {
150         int ret = 0;
151         unsigned long flags;
152
153         iwl5000_apm_stop_master(priv);
154
155         spin_lock_irqsave(&priv->lock, flags);
156
157         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
158
159         udelay(10);
160
161
162         /* FIXME: put here L1A -L0S w/a */
163
164         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
165
166         /* set "initialization complete" bit to move adapter
167          * D0U* --> D0A* state */
168         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
169
170         /* wait for clock stabilization */
171         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
172                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
173                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
174         if (ret < 0) {
175                 IWL_DEBUG_INFO("Failed to init the card\n");
176                 goto out;
177         }
178
179         ret = iwl_grab_nic_access(priv);
180         if (ret)
181                 goto out;
182
183         /* enable DMA */
184         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
185
186         udelay(20);
187
188         /* disable L1-Active */
189         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
190                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
191
192         iwl_release_nic_access(priv);
193
194 out:
195         spin_unlock_irqrestore(&priv->lock, flags);
196
197         return ret;
198 }
199
200
201 static void iwl5000_nic_config(struct iwl_priv *priv)
202 {
203         unsigned long flags;
204         u16 radio_cfg;
205         u8 val_link;
206
207         spin_lock_irqsave(&priv->lock, flags);
208
209         pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
210
211         /* L1 is enabled by BIOS */
212         if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
213                 /* diable L0S disabled L1A enabled */
214                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
215         else
216                 /* L0S enabled L1A disabled */
217                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
218
219         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
220
221         /* write radio config values to register */
222         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
223                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
224                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
225                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
226                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
227
228         /* set CSR_HW_CONFIG_REG for uCode use */
229         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
230                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
231                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
232
233         spin_unlock_irqrestore(&priv->lock, flags);
234 }
235
236
237
238 /*
239  * EEPROM
240  */
241 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
242 {
243         u16 offset = 0;
244
245         if ((address & INDIRECT_ADDRESS) == 0)
246                 return address;
247
248         switch (address & INDIRECT_TYPE_MSK) {
249         case INDIRECT_HOST:
250                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
251                 break;
252         case INDIRECT_GENERAL:
253                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
254                 break;
255         case INDIRECT_REGULATORY:
256                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
257                 break;
258         case INDIRECT_CALIBRATION:
259                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
260                 break;
261         case INDIRECT_PROCESS_ADJST:
262                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
263                 break;
264         case INDIRECT_OTHERS:
265                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
266                 break;
267         default:
268                 IWL_ERROR("illegal indirect type: 0x%X\n",
269                 address & INDIRECT_TYPE_MSK);
270                 break;
271         }
272
273         /* translate the offset from words to byte */
274         return (address & ADDRESS_MSK) + (offset << 1);
275 }
276
277 static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
278 {
279         u16 eeprom_ver;
280         struct iwl_eeprom_calib_hdr {
281                 u8 version;
282                 u8 pa_type;
283                 u16 voltage;
284         } *hdr;
285
286         eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
287
288         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
289                                                         EEPROM_5000_CALIB_ALL);
290
291         if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
292             hdr->version < EEPROM_5000_TX_POWER_VERSION)
293                 goto err;
294
295         return 0;
296 err:
297         IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
298                   eeprom_ver, EEPROM_5000_EEPROM_VERSION,
299                   hdr->version, EEPROM_5000_TX_POWER_VERSION);
300         return -EINVAL;
301
302 }
303
304 static void iwl5000_gain_computation(struct iwl_priv *priv,
305                 u32 average_noise[NUM_RX_CHAINS],
306                 u16 min_average_noise_antenna_i,
307                 u32 min_average_noise)
308 {
309         int i;
310         s32 delta_g;
311         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
312
313         /* Find Gain Code for the antennas B and C */
314         for (i = 1; i < NUM_RX_CHAINS; i++) {
315                 if ((data->disconn_array[i])) {
316                         data->delta_gain_code[i] = 0;
317                         continue;
318                 }
319                 delta_g = (1000 * ((s32)average_noise[0] -
320                         (s32)average_noise[i])) / 1500;
321                 /* bound gain by 2 bits value max, 3rd bit is sign */
322                 data->delta_gain_code[i] =
323                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
324
325                 if (delta_g < 0)
326                         /* set negative sign */
327                         data->delta_gain_code[i] |= (1 << 2);
328         }
329
330         IWL_DEBUG_CALIB("Delta gains: ANT_B = %d  ANT_C = %d\n",
331                         data->delta_gain_code[1], data->delta_gain_code[2]);
332
333         if (!data->radio_write) {
334                 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
335                 memset(&cmd, 0, sizeof(cmd));
336
337                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
338                 cmd.delta_gain_1 = data->delta_gain_code[1];
339                 cmd.delta_gain_2 = data->delta_gain_code[2];
340                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
341                         sizeof(cmd), &cmd, NULL);
342
343                 data->radio_write = 1;
344                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
345         }
346
347         data->chain_noise_a = 0;
348         data->chain_noise_b = 0;
349         data->chain_noise_c = 0;
350         data->chain_signal_a = 0;
351         data->chain_signal_b = 0;
352         data->chain_signal_c = 0;
353         data->beacon_count = 0;
354 }
355
356 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
357 {
358         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
359
360         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
361                 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
362
363                 memset(&cmd, 0, sizeof(cmd));
364                 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
365                 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
366                         sizeof(cmd), &cmd))
367                         IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
368                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
369                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
370         }
371 }
372
373 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
374         .min_nrg_cck = 95,
375         .max_nrg_cck = 0,
376         .auto_corr_min_ofdm = 90,
377         .auto_corr_min_ofdm_mrc = 170,
378         .auto_corr_min_ofdm_x1 = 120,
379         .auto_corr_min_ofdm_mrc_x1 = 240,
380
381         .auto_corr_max_ofdm = 120,
382         .auto_corr_max_ofdm_mrc = 210,
383         .auto_corr_max_ofdm_x1 = 155,
384         .auto_corr_max_ofdm_mrc_x1 = 290,
385
386         .auto_corr_min_cck = 125,
387         .auto_corr_max_cck = 200,
388         .auto_corr_min_cck_mrc = 170,
389         .auto_corr_max_cck_mrc = 400,
390         .nrg_th_cck = 95,
391         .nrg_th_ofdm = 95,
392 };
393
394 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
395                                            size_t offset)
396 {
397         u32 address = eeprom_indirect_address(priv, offset);
398         BUG_ON(address >= priv->cfg->eeprom_size);
399         return &priv->eeprom[address];
400 }
401
402 /*
403  *  Calibration
404  */
405 static int iwl5000_send_Xtal_calib(struct iwl_priv *priv)
406 {
407         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
408
409         struct iwl5000_calibration cal_cmd = {
410                 .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD,
411                 .data = {
412                         (u8)xtal_calib[0],
413                         (u8)xtal_calib[1],
414                 }
415         };
416
417         return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
418                                 sizeof(cal_cmd), &cal_cmd);
419 }
420
421 static int iwl5000_send_calib_results(struct iwl_priv *priv)
422 {
423         int ret = 0;
424
425         struct iwl_host_cmd hcmd = {
426                 .id = REPLY_PHY_CALIBRATION_CMD,
427                 .meta.flags = CMD_SIZE_HUGE,
428         };
429
430         if (priv->calib_results.lo_res) {
431                 hcmd.len = priv->calib_results.lo_res_len;
432                 hcmd.data = priv->calib_results.lo_res;
433                 ret = iwl_send_cmd_sync(priv, &hcmd);
434
435                 if (ret)
436                         goto err;
437         }
438
439         if (priv->calib_results.tx_iq_res) {
440                 hcmd.len = priv->calib_results.tx_iq_res_len;
441                 hcmd.data = priv->calib_results.tx_iq_res;
442                 ret = iwl_send_cmd_sync(priv, &hcmd);
443
444                 if (ret)
445                         goto err;
446         }
447
448         if (priv->calib_results.tx_iq_perd_res) {
449                 hcmd.len = priv->calib_results.tx_iq_perd_res_len;
450                 hcmd.data = priv->calib_results.tx_iq_perd_res;
451                 ret = iwl_send_cmd_sync(priv, &hcmd);
452
453                 if (ret)
454                         goto err;
455         }
456
457         return 0;
458 err:
459         IWL_ERROR("Error %d\n", ret);
460         return ret;
461 }
462
463 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
464 {
465         struct iwl5000_calib_cfg_cmd calib_cfg_cmd;
466         struct iwl_host_cmd cmd = {
467                 .id = CALIBRATION_CFG_CMD,
468                 .len = sizeof(struct iwl5000_calib_cfg_cmd),
469                 .data = &calib_cfg_cmd,
470         };
471
472         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
473         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
474         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
475         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
476         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
477
478         return iwl_send_cmd(priv, &cmd);
479 }
480
481 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
482                              struct iwl_rx_mem_buffer *rxb)
483 {
484         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
485         struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw;
486         int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
487
488         iwl_free_calib_results(priv);
489
490         /* reduce the size of the length field itself */
491         len -= 4;
492
493         switch (hdr->op_code) {
494         case IWL5000_PHY_CALIBRATE_LO_CMD:
495                 priv->calib_results.lo_res = kzalloc(len, GFP_ATOMIC);
496                 priv->calib_results.lo_res_len = len;
497                 memcpy(priv->calib_results.lo_res, pkt->u.raw, len);
498                 break;
499         case IWL5000_PHY_CALIBRATE_TX_IQ_CMD:
500                 priv->calib_results.tx_iq_res = kzalloc(len, GFP_ATOMIC);
501                 priv->calib_results.tx_iq_res_len = len;
502                 memcpy(priv->calib_results.tx_iq_res, pkt->u.raw, len);
503                 break;
504         case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD:
505                 priv->calib_results.tx_iq_perd_res = kzalloc(len, GFP_ATOMIC);
506                 priv->calib_results.tx_iq_perd_res_len = len;
507                 memcpy(priv->calib_results.tx_iq_perd_res, pkt->u.raw, len);
508                 break;
509         default:
510                 IWL_ERROR("Unknown calibration notification %d\n",
511                           hdr->op_code);
512                 return;
513         }
514 }
515
516 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
517                                struct iwl_rx_mem_buffer *rxb)
518 {
519         IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
520         queue_work(priv->workqueue, &priv->restart);
521 }
522
523 /*
524  * ucode
525  */
526 static int iwl5000_load_section(struct iwl_priv *priv,
527                                 struct fw_desc *image,
528                                 u32 dst_addr)
529 {
530         int ret = 0;
531         unsigned long flags;
532
533         dma_addr_t phy_addr = image->p_addr;
534         u32 byte_cnt = image->len;
535
536         spin_lock_irqsave(&priv->lock, flags);
537         ret = iwl_grab_nic_access(priv);
538         if (ret) {
539                 spin_unlock_irqrestore(&priv->lock, flags);
540                 return ret;
541         }
542
543         iwl_write_direct32(priv,
544                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
545                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
546
547         iwl_write_direct32(priv,
548                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
549
550         iwl_write_direct32(priv,
551                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
552                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
553
554         /* FIME: write the MSB of the phy_addr in CTRL1
555          * iwl_write_direct32(priv,
556                 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
557                 ((phy_addr & MSB_MSK)
558                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
559          */
560         iwl_write_direct32(priv,
561                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
562         iwl_write_direct32(priv,
563                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
564                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
565                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
566                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
567
568         iwl_write_direct32(priv,
569                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
570                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
571                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
572                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
573
574         iwl_release_nic_access(priv);
575         spin_unlock_irqrestore(&priv->lock, flags);
576         return 0;
577 }
578
579 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
580                 struct fw_desc *inst_image,
581                 struct fw_desc *data_image)
582 {
583         int ret = 0;
584
585         ret = iwl5000_load_section(
586                 priv, inst_image, RTC_INST_LOWER_BOUND);
587         if (ret)
588                 return ret;
589
590         IWL_DEBUG_INFO("INST uCode section being loaded...\n");
591         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
592                                 priv->ucode_write_complete, 5 * HZ);
593         if (ret == -ERESTARTSYS) {
594                 IWL_ERROR("Could not load the INST uCode section due "
595                         "to interrupt\n");
596                 return ret;
597         }
598         if (!ret) {
599                 IWL_ERROR("Could not load the INST uCode section\n");
600                 return -ETIMEDOUT;
601         }
602
603         priv->ucode_write_complete = 0;
604
605         ret = iwl5000_load_section(
606                 priv, data_image, RTC_DATA_LOWER_BOUND);
607         if (ret)
608                 return ret;
609
610         IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
611
612         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
613                                 priv->ucode_write_complete, 5 * HZ);
614         if (ret == -ERESTARTSYS) {
615                 IWL_ERROR("Could not load the INST uCode section due "
616                         "to interrupt\n");
617                 return ret;
618         } else if (!ret) {
619                 IWL_ERROR("Could not load the DATA uCode section\n");
620                 return -ETIMEDOUT;
621         } else
622                 ret = 0;
623
624         priv->ucode_write_complete = 0;
625
626         return ret;
627 }
628
629 static int iwl5000_load_ucode(struct iwl_priv *priv)
630 {
631         int ret = 0;
632
633         /* check whether init ucode should be loaded, or rather runtime ucode */
634         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
635                 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
636                 ret = iwl5000_load_given_ucode(priv,
637                         &priv->ucode_init, &priv->ucode_init_data);
638                 if (!ret) {
639                         IWL_DEBUG_INFO("Init ucode load complete.\n");
640                         priv->ucode_type = UCODE_INIT;
641                 }
642         } else {
643                 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
644                         "Loading runtime ucode...\n");
645                 ret = iwl5000_load_given_ucode(priv,
646                         &priv->ucode_code, &priv->ucode_data);
647                 if (!ret) {
648                         IWL_DEBUG_INFO("Runtime ucode load complete.\n");
649                         priv->ucode_type = UCODE_RT;
650                 }
651         }
652
653         return ret;
654 }
655
656 static void iwl5000_init_alive_start(struct iwl_priv *priv)
657 {
658         int ret = 0;
659
660         /* Check alive response for "valid" sign from uCode */
661         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
662                 /* We had an error bringing up the hardware, so take it
663                  * all the way back down so we can try again */
664                 IWL_DEBUG_INFO("Initialize Alive failed.\n");
665                 goto restart;
666         }
667
668         /* initialize uCode was loaded... verify inst image.
669          * This is a paranoid check, because we would not have gotten the
670          * "initialize" alive if code weren't properly loaded.  */
671         if (iwl_verify_ucode(priv)) {
672                 /* Runtime instruction load was bad;
673                  * take it all the way back down so we can try again */
674                 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
675                 goto restart;
676         }
677
678         iwlcore_clear_stations_table(priv);
679         ret = priv->cfg->ops->lib->alive_notify(priv);
680         if (ret) {
681                 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
682                 goto restart;
683         }
684
685         iwl5000_send_calib_cfg(priv);
686         return;
687
688 restart:
689         /* real restart (first load init_ucode) */
690         queue_work(priv->workqueue, &priv->restart);
691 }
692
693 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
694                                 int txq_id, u32 index)
695 {
696         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
697                         (index & 0xff) | (txq_id << 8));
698         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
699 }
700
701 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
702                                         struct iwl_tx_queue *txq,
703                                         int tx_fifo_id, int scd_retry)
704 {
705         int txq_id = txq->q.id;
706         int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
707
708         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
709                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
710                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
711                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
712                         IWL50_SCD_QUEUE_STTS_REG_MSK);
713
714         txq->sched_retry = scd_retry;
715
716         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
717                        active ? "Activate" : "Deactivate",
718                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
719 }
720
721 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
722 {
723         struct iwl_wimax_coex_cmd coex_cmd;
724
725         memset(&coex_cmd, 0, sizeof(coex_cmd));
726
727         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
728                                 sizeof(coex_cmd), &coex_cmd);
729 }
730
731 static int iwl5000_alive_notify(struct iwl_priv *priv)
732 {
733         u32 a;
734         int i = 0;
735         unsigned long flags;
736         int ret;
737
738         spin_lock_irqsave(&priv->lock, flags);
739
740         ret = iwl_grab_nic_access(priv);
741         if (ret) {
742                 spin_unlock_irqrestore(&priv->lock, flags);
743                 return ret;
744         }
745
746         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
747         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
748         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
749                 a += 4)
750                 iwl_write_targ_mem(priv, a, 0);
751         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
752                 a += 4)
753                 iwl_write_targ_mem(priv, a, 0);
754         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
755                 iwl_write_targ_mem(priv, a, 0);
756
757         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
758                 (priv->shared_phys +
759                  offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
760         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
761                 IWL50_SCD_QUEUECHAIN_SEL_ALL(
762                         priv->hw_params.max_txq_num));
763         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
764
765         /* initiate the queues */
766         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
767                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
768                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
769                 iwl_write_targ_mem(priv, priv->scd_base_addr +
770                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
771                 iwl_write_targ_mem(priv, priv->scd_base_addr +
772                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
773                                 sizeof(u32),
774                                 ((SCD_WIN_SIZE <<
775                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
776                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
777                                 ((SCD_FRAME_LIMIT <<
778                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
779                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
780         }
781
782         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
783                         IWL_MASK(0, priv->hw_params.max_txq_num));
784
785         /* Activate all Tx DMA/FIFO channels */
786         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
787
788         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
789         /* map qos queues to fifos one-to-one */
790         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
791                 int ac = iwl5000_default_queue_to_tx_fifo[i];
792                 iwl_txq_ctx_activate(priv, i);
793                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
794         }
795         /* TODO - need to initialize those FIFOs inside the loop above,
796          * not only mark them as active */
797         iwl_txq_ctx_activate(priv, 4);
798         iwl_txq_ctx_activate(priv, 7);
799         iwl_txq_ctx_activate(priv, 8);
800         iwl_txq_ctx_activate(priv, 9);
801
802         iwl_release_nic_access(priv);
803         spin_unlock_irqrestore(&priv->lock, flags);
804
805
806         iwl5000_send_wimax_coex(priv);
807
808         iwl5000_send_Xtal_calib(priv);
809
810         if (priv->ucode_type == UCODE_RT) {
811                 iwl5000_send_calib_results(priv);
812                 set_bit(STATUS_READY, &priv->status);
813                 priv->is_open = 1;
814         }
815
816         return 0;
817 }
818
819 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
820 {
821         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
822             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
823                 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
824                           IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
825                 return -EINVAL;
826         }
827
828         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
829         priv->hw_params.first_ampdu_q = IWL50_FIRST_AMPDU_QUEUE;
830         priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
831         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
832         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
833         if (priv->cfg->mod_params->amsdu_size_8K)
834                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
835         else
836                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
837         priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
838         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
839         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
840         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
841         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
842         priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
843         priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
844                                         BIT(IEEE80211_BAND_5GHZ);
845         priv->hw_params.sens = &iwl5000_sensitivity;
846
847         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
848         case CSR_HW_REV_TYPE_5100:
849         case CSR_HW_REV_TYPE_5150:
850                 priv->hw_params.tx_chains_num = 1;
851                 priv->hw_params.rx_chains_num = 2;
852                 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
853                 priv->hw_params.valid_tx_ant = ANT_A;
854                 priv->hw_params.valid_rx_ant = ANT_AB;
855                 break;
856         case CSR_HW_REV_TYPE_5300:
857         case CSR_HW_REV_TYPE_5350:
858                 priv->hw_params.tx_chains_num = 3;
859                 priv->hw_params.rx_chains_num = 3;
860                 priv->hw_params.valid_tx_ant = ANT_ABC;
861                 priv->hw_params.valid_rx_ant = ANT_ABC;
862                 break;
863         }
864
865         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
866         case CSR_HW_REV_TYPE_5100:
867         case CSR_HW_REV_TYPE_5300:
868                 /* 5X00 wants in Celsius */
869                 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
870                 break;
871         case CSR_HW_REV_TYPE_5150:
872         case CSR_HW_REV_TYPE_5350:
873                 /* 5X50 wants in Kelvin */
874                 priv->hw_params.ct_kill_threshold =
875                                 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
876                 break;
877         }
878
879         return 0;
880 }
881
882 static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
883 {
884         priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
885                                         sizeof(struct iwl5000_shared),
886                                         &priv->shared_phys);
887         if (!priv->shared_virt)
888                 return -ENOMEM;
889
890         memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
891
892         priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
893
894         return 0;
895 }
896
897 static void iwl5000_free_shared_mem(struct iwl_priv *priv)
898 {
899         if (priv->shared_virt)
900                 pci_free_consistent(priv->pci_dev,
901                                     sizeof(struct iwl5000_shared),
902                                     priv->shared_virt,
903                                     priv->shared_phys);
904 }
905
906 static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
907 {
908         struct iwl5000_shared *s = priv->shared_virt;
909         return le32_to_cpu(s->rb_closed) & 0xFFF;
910 }
911
912 /**
913  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
914  */
915 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
916                                             struct iwl_tx_queue *txq,
917                                             u16 byte_cnt)
918 {
919         struct iwl5000_shared *shared_data = priv->shared_virt;
920         int txq_id = txq->q.id;
921         u8 sec_ctl = 0;
922         u8 sta = 0;
923         int len;
924
925         len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
926
927         if (txq_id != IWL_CMD_QUEUE_NUM) {
928                 sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id;
929                 sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl;
930
931                 switch (sec_ctl & TX_CMD_SEC_MSK) {
932                 case TX_CMD_SEC_CCM:
933                         len += CCMP_MIC_LEN;
934                         break;
935                 case TX_CMD_SEC_TKIP:
936                         len += TKIP_ICV_LEN;
937                         break;
938                 case TX_CMD_SEC_WEP:
939                         len += WEP_IV_LEN + WEP_ICV_LEN;
940                         break;
941                 }
942         }
943
944         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
945                        tfd_offset[txq->q.write_ptr], byte_cnt, len);
946
947         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
948                        tfd_offset[txq->q.write_ptr], sta_id, sta);
949
950         if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
951                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
952                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
953                         byte_cnt, len);
954                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
955                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
956                         sta_id, sta);
957         }
958 }
959
960 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
961                                            struct iwl_tx_queue *txq)
962 {
963         int txq_id = txq->q.id;
964         struct iwl5000_shared *shared_data = priv->shared_virt;
965         u8 sta = 0;
966
967         if (txq_id != IWL_CMD_QUEUE_NUM)
968                 sta = txq->cmd[txq->q.read_ptr].cmd.tx.sta_id;
969
970         shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr].
971                                         val = cpu_to_le16(1 | (sta << 12));
972
973         if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
974                 shared_data->queues_byte_cnt_tbls[txq_id].
975                         tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr].
976                                 val = cpu_to_le16(1 | (sta << 12));
977         }
978 }
979
980 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
981                                         u16 txq_id)
982 {
983         u32 tbl_dw_addr;
984         u32 tbl_dw;
985         u16 scd_q2ratid;
986
987         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
988
989         tbl_dw_addr = priv->scd_base_addr +
990                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
991
992         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
993
994         if (txq_id & 0x1)
995                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
996         else
997                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
998
999         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1000
1001         return 0;
1002 }
1003 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
1004 {
1005         /* Simply stop the queue, but don't change any configuration;
1006          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1007         iwl_write_prph(priv,
1008                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
1009                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1010                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1011 }
1012
1013 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1014                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1015 {
1016         unsigned long flags;
1017         int ret;
1018         u16 ra_tid;
1019
1020         if (IWL50_FIRST_AMPDU_QUEUE > txq_id)
1021                 IWL_WARNING("queue number too small: %d, must be > %d\n",
1022                         txq_id, IWL50_FIRST_AMPDU_QUEUE);
1023
1024         ra_tid = BUILD_RAxTID(sta_id, tid);
1025
1026         /* Modify device's station table to Tx this TID */
1027         iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
1028
1029         spin_lock_irqsave(&priv->lock, flags);
1030         ret = iwl_grab_nic_access(priv);
1031         if (ret) {
1032                 spin_unlock_irqrestore(&priv->lock, flags);
1033                 return ret;
1034         }
1035
1036         /* Stop this Tx queue before configuring it */
1037         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1038
1039         /* Map receiver-address / traffic-ID to this queue */
1040         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1041
1042         /* Set this queue as a chain-building queue */
1043         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1044
1045         /* enable aggregations for the queue */
1046         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1047
1048         /* Place first TFD at index corresponding to start sequence number.
1049          * Assumes that ssn_idx is valid (!= 0xFFF) */
1050         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1051         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1052         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1053
1054         /* Set up Tx window size and frame limit for this queue */
1055         iwl_write_targ_mem(priv, priv->scd_base_addr +
1056                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1057                         sizeof(u32),
1058                         ((SCD_WIN_SIZE <<
1059                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1060                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1061                         ((SCD_FRAME_LIMIT <<
1062                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1063                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1064
1065         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1066
1067         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1068         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1069
1070         iwl_release_nic_access(priv);
1071         spin_unlock_irqrestore(&priv->lock, flags);
1072
1073         return 0;
1074 }
1075
1076 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1077                                    u16 ssn_idx, u8 tx_fifo)
1078 {
1079         int ret;
1080
1081         if (IWL50_FIRST_AMPDU_QUEUE > txq_id) {
1082                 IWL_WARNING("queue number too small: %d, must be > %d\n",
1083                                 txq_id, IWL50_FIRST_AMPDU_QUEUE);
1084                 return -EINVAL;
1085         }
1086
1087         ret = iwl_grab_nic_access(priv);
1088         if (ret)
1089                 return ret;
1090
1091         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1092
1093         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1094
1095         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1096         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1097         /* supposes that ssn_idx is valid (!= 0xFFF) */
1098         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1099
1100         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1101         iwl_txq_ctx_deactivate(priv, txq_id);
1102         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1103
1104         iwl_release_nic_access(priv);
1105
1106         return 0;
1107 }
1108
1109 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1110 {
1111         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1112         memcpy(data, cmd, size);
1113         return size;
1114 }
1115
1116
1117 /*
1118  * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
1119  * must be called under priv->lock and mac access
1120  */
1121 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1122 {
1123         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1124 }
1125
1126
1127 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1128 {
1129         __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status +
1130                                 tx_resp->frame_count);
1131         return le32_to_cpu(*scd_ssn) & MAX_SN;
1132
1133 }
1134
1135 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1136                                       struct iwl_ht_agg *agg,
1137                                       struct iwl5000_tx_resp *tx_resp,
1138                                       u16 start_idx)
1139 {
1140         u16 status;
1141         struct agg_tx_status *frame_status = &tx_resp->status;
1142         struct ieee80211_tx_info *info = NULL;
1143         struct ieee80211_hdr *hdr = NULL;
1144         int i, sh;
1145         int txq_id, idx;
1146         u16 seq;
1147
1148         if (agg->wait_for_ba)
1149                 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1150
1151         agg->frame_count = tx_resp->frame_count;
1152         agg->start_idx = start_idx;
1153         agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1154         agg->bitmap = 0;
1155
1156         /* # frames attempted by Tx command */
1157         if (agg->frame_count == 1) {
1158                 /* Only one frame was attempted; no block-ack will arrive */
1159                 status = le16_to_cpu(frame_status[0].status);
1160                 seq  = le16_to_cpu(frame_status[0].sequence);
1161                 idx = SEQ_TO_INDEX(seq);
1162                 txq_id = SEQ_TO_QUEUE(seq);
1163
1164                 /* FIXME: code repetition */
1165                 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1166                                    agg->frame_count, agg->start_idx, idx);
1167
1168                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1169                 info->status.retry_count = tx_resp->failure_frame;
1170                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1171                 info->flags |= iwl_is_tx_success(status)?
1172                         IEEE80211_TX_STAT_ACK : 0;
1173                 iwl4965_hwrate_to_tx_control(priv,
1174                                              le32_to_cpu(tx_resp->rate_n_flags),
1175                                              info);
1176                 /* FIXME: code repetition end */
1177
1178                 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1179                                     status & 0xff, tx_resp->failure_frame);
1180                 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
1181                         iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
1182
1183                 agg->wait_for_ba = 0;
1184         } else {
1185                 /* Two or more frames were attempted; expect block-ack */
1186                 u64 bitmap = 0;
1187                 int start = agg->start_idx;
1188
1189                 /* Construct bit-map of pending frames within Tx window */
1190                 for (i = 0; i < agg->frame_count; i++) {
1191                         u16 sc;
1192                         status = le16_to_cpu(frame_status[i].status);
1193                         seq  = le16_to_cpu(frame_status[i].sequence);
1194                         idx = SEQ_TO_INDEX(seq);
1195                         txq_id = SEQ_TO_QUEUE(seq);
1196
1197                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1198                                       AGG_TX_STATE_ABORT_MSK))
1199                                 continue;
1200
1201                         IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1202                                            agg->frame_count, txq_id, idx);
1203
1204                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1205
1206                         sc = le16_to_cpu(hdr->seq_ctrl);
1207                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1208                                 IWL_ERROR("BUG_ON idx doesn't match seq control"
1209                                           " idx=%d, seq_idx=%d, seq=%d\n",
1210                                           idx, SEQ_TO_SN(sc),
1211                                           hdr->seq_ctrl);
1212                                 return -1;
1213                         }
1214
1215                         IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1216                                            i, idx, SEQ_TO_SN(sc));
1217
1218                         sh = idx - start;
1219                         if (sh > 64) {
1220                                 sh = (start - idx) + 0xff;
1221                                 bitmap = bitmap << sh;
1222                                 sh = 0;
1223                                 start = idx;
1224                         } else if (sh < -64)
1225                                 sh  = 0xff - (start - idx);
1226                         else if (sh < 0) {
1227                                 sh = start - idx;
1228                                 start = idx;
1229                                 bitmap = bitmap << sh;
1230                                 sh = 0;
1231                         }
1232                         bitmap |= (1 << sh);
1233                         IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
1234                                            start, (u32)(bitmap & 0xFFFFFFFF));
1235                 }
1236
1237                 agg->bitmap = bitmap;
1238                 agg->start_idx = start;
1239                 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1240                 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1241                                    agg->frame_count, agg->start_idx,
1242                                    (unsigned long long)agg->bitmap);
1243
1244                 if (bitmap)
1245                         agg->wait_for_ba = 1;
1246         }
1247         return 0;
1248 }
1249
1250 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1251                                 struct iwl_rx_mem_buffer *rxb)
1252 {
1253         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1254         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1255         int txq_id = SEQ_TO_QUEUE(sequence);
1256         int index = SEQ_TO_INDEX(sequence);
1257         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1258         struct ieee80211_tx_info *info;
1259         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1260         u32  status = le16_to_cpu(tx_resp->status.status);
1261         int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
1262         u16 fc;
1263         struct ieee80211_hdr *hdr;
1264         u8 *qc = NULL;
1265
1266         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1267                 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1268                           "is out of range [0-%d] %d %d\n", txq_id,
1269                           index, txq->q.n_bd, txq->q.write_ptr,
1270                           txq->q.read_ptr);
1271                 return;
1272         }
1273
1274         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1275         memset(&info->status, 0, sizeof(info->status));
1276
1277         hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
1278         fc = le16_to_cpu(hdr->frame_control);
1279         if (ieee80211_is_qos_data(fc)) {
1280                 qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
1281                 tid = qc[0] & 0xf;
1282         }
1283
1284         sta_id = iwl_get_ra_sta_id(priv, hdr);
1285         if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
1286                 IWL_ERROR("Station not known\n");
1287                 return;
1288         }
1289
1290         if (txq->sched_retry) {
1291                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1292                 struct iwl_ht_agg *agg = NULL;
1293
1294                 if (!qc)
1295                         return;
1296
1297                 agg = &priv->stations[sta_id].tid[tid].agg;
1298
1299                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, index);
1300
1301                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) {
1302                         /* TODO: send BAR */
1303                 }
1304
1305                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1306                         int freed, ampdu_q;
1307                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1308                         IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
1309                                            "%d index %d\n", scd_ssn , index);
1310                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1311                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1312
1313                         if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1314                             txq_id >= 0 && priv->mac80211_registered &&
1315                             agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
1316                                 /* calculate mac80211 ampdu sw queue to wake */
1317                                 ampdu_q = txq_id - IWL50_FIRST_AMPDU_QUEUE +
1318                                           priv->hw->queues;
1319                                 if (agg->state == IWL_AGG_OFF)
1320                                         ieee80211_wake_queue(priv->hw, txq_id);
1321                                 else
1322                                         ieee80211_wake_queue(priv->hw, ampdu_q);
1323                         }
1324                         iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1325                 }
1326         } else {
1327                 info->status.retry_count = tx_resp->failure_frame;
1328                 info->flags =
1329                         iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
1330                 iwl4965_hwrate_to_tx_control(priv,
1331                                         le32_to_cpu(tx_resp->rate_n_flags),
1332                                         info);
1333
1334                 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
1335                              "0x%x retries %d\n", txq_id,
1336                                 iwl_get_tx_fail_reason(status),
1337                                 status, le32_to_cpu(tx_resp->rate_n_flags),
1338                                 tx_resp->failure_frame);
1339
1340                 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
1341                 if (index != -1) {
1342                     int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1343                     if (tid != MAX_TID_COUNT)
1344                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1345                     if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1346                         (txq_id >= 0) && priv->mac80211_registered)
1347                         ieee80211_wake_queue(priv->hw, txq_id);
1348                     if (tid != MAX_TID_COUNT)
1349                         iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1350                 }
1351         }
1352
1353         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1354                 IWL_ERROR("TODO:  Implement Tx ABORT REQUIRED!!!\n");
1355 }
1356
1357 /* Currently 5000 is the supperset of everything */
1358 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1359 {
1360         return len;
1361 }
1362
1363 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1364 {
1365         /* in 5000 the tx power calibration is done in uCode */
1366         priv->disable_tx_power_cal = 1;
1367 }
1368
1369 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1370 {
1371         /* init calibration handlers */
1372         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1373                                         iwl5000_rx_calib_result;
1374         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1375                                         iwl5000_rx_calib_complete;
1376         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1377 }
1378
1379
1380 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1381 {
1382         return (addr >= RTC_DATA_LOWER_BOUND) &&
1383                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1384 }
1385
1386 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1387 {
1388         int ret = 0;
1389         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1390         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1391         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1392
1393         if ((rxon1->flags == rxon2->flags) &&
1394             (rxon1->filter_flags == rxon2->filter_flags) &&
1395             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1396             (rxon1->ofdm_ht_single_stream_basic_rates ==
1397              rxon2->ofdm_ht_single_stream_basic_rates) &&
1398             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1399              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1400             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1401              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1402             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1403             (rxon1->rx_chain == rxon2->rx_chain) &&
1404             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1405                 IWL_DEBUG_INFO("Using current RXON_ASSOC.  Not resending.\n");
1406                 return 0;
1407         }
1408
1409         rxon_assoc.flags = priv->staging_rxon.flags;
1410         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1411         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1412         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1413         rxon_assoc.reserved1 = 0;
1414         rxon_assoc.reserved2 = 0;
1415         rxon_assoc.reserved3 = 0;
1416         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1417             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1418         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1419             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1420         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1421         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1422                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1423         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1424
1425         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1426                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1427         if (ret)
1428                 return ret;
1429
1430         return ret;
1431 }
1432
1433 static struct iwl_hcmd_ops iwl5000_hcmd = {
1434         .rxon_assoc = iwl5000_send_rxon_assoc,
1435 };
1436
1437 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1438         .get_hcmd_size = iwl5000_get_hcmd_size,
1439         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1440         .gain_computation = iwl5000_gain_computation,
1441         .chain_noise_reset = iwl5000_chain_noise_reset,
1442 };
1443
1444 static struct iwl_lib_ops iwl5000_lib = {
1445         .set_hw_params = iwl5000_hw_set_hw_params,
1446         .alloc_shared_mem = iwl5000_alloc_shared_mem,
1447         .free_shared_mem = iwl5000_free_shared_mem,
1448         .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
1449         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1450         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1451         .txq_set_sched = iwl5000_txq_set_sched,
1452         .txq_agg_enable = iwl5000_txq_agg_enable,
1453         .txq_agg_disable = iwl5000_txq_agg_disable,
1454         .rx_handler_setup = iwl5000_rx_handler_setup,
1455         .setup_deferred_work = iwl5000_setup_deferred_work,
1456         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1457         .load_ucode = iwl5000_load_ucode,
1458         .init_alive_start = iwl5000_init_alive_start,
1459         .alive_notify = iwl5000_alive_notify,
1460         .apm_ops = {
1461                 .init = iwl5000_apm_init,
1462                 .reset = iwl5000_apm_reset,
1463                 .stop = iwl5000_apm_stop,
1464                 .config = iwl5000_nic_config,
1465                 .set_pwr_src = iwl4965_set_pwr_src,
1466         },
1467         .eeprom_ops = {
1468                 .regulatory_bands = {
1469                         EEPROM_5000_REG_BAND_1_CHANNELS,
1470                         EEPROM_5000_REG_BAND_2_CHANNELS,
1471                         EEPROM_5000_REG_BAND_3_CHANNELS,
1472                         EEPROM_5000_REG_BAND_4_CHANNELS,
1473                         EEPROM_5000_REG_BAND_5_CHANNELS,
1474                         EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1475                         EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1476                 },
1477                 .verify_signature  = iwlcore_eeprom_verify_signature,
1478                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1479                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1480                 .check_version  = iwl5000_eeprom_check_version,
1481                 .query_addr = iwl5000_eeprom_query_addr,
1482         },
1483 };
1484
1485 static struct iwl_ops iwl5000_ops = {
1486         .lib = &iwl5000_lib,
1487         .hcmd = &iwl5000_hcmd,
1488         .utils = &iwl5000_hcmd_utils,
1489 };
1490
1491 static struct iwl_mod_params iwl50_mod_params = {
1492         .num_of_queues = IWL50_NUM_QUEUES,
1493         .enable_qos = 1,
1494         .amsdu_size_8K = 1,
1495         .restart_fw = 1,
1496         /* the rest are 0 by default */
1497 };
1498
1499
1500 struct iwl_cfg iwl5300_agn_cfg = {
1501         .name = "5300AGN",
1502         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1503         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1504         .ops = &iwl5000_ops,
1505         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1506         .mod_params = &iwl50_mod_params,
1507 };
1508
1509 struct iwl_cfg iwl5100_agn_cfg = {
1510         .name = "5100AGN",
1511         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1512         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1513         .ops = &iwl5000_ops,
1514         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1515         .mod_params = &iwl50_mod_params,
1516 };
1517
1518 struct iwl_cfg iwl5350_agn_cfg = {
1519         .name = "5350AGN",
1520         .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1521         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1522         .ops = &iwl5000_ops,
1523         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1524         .mod_params = &iwl50_mod_params,
1525 };
1526
1527 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1528 MODULE_PARM_DESC(disable50,
1529                   "manually disable the 50XX radio (default 0 [radio on])");
1530 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1531 MODULE_PARM_DESC(swcrypto50,
1532                   "using software crypto engine (default 0 [hardware])\n");
1533 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1534 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1535 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1536 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1537 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1538 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
1539 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1540 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1541 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1542 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");