mwl8k: convert to new station add/remove callbacks
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23  *
24  *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/sched.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <net/mac80211.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39
40 #include "iwl-eeprom.h"
41 #include "iwl-dev.h"
42 #include "iwl-core.h"
43 #include "iwl-io.h"
44 #include "iwl-sta.h"
45 #include "iwl-helpers.h"
46 #include "iwl-agn-led.h"
47 #include "iwl-5000-hw.h"
48 #include "iwl-6000-hw.h"
49
50 /* Highest firmware API version supported */
51 #define IWL5000_UCODE_API_MAX 2
52 #define IWL5150_UCODE_API_MAX 2
53
54 /* Lowest firmware API version supported */
55 #define IWL5000_UCODE_API_MIN 1
56 #define IWL5150_UCODE_API_MIN 1
57
58 #define IWL5000_FW_PRE "iwlwifi-5000-"
59 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
60 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
61
62 #define IWL5150_FW_PRE "iwlwifi-5150-"
63 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
64 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
65
66 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
67         IWL_TX_FIFO_AC3,
68         IWL_TX_FIFO_AC2,
69         IWL_TX_FIFO_AC1,
70         IWL_TX_FIFO_AC0,
71         IWL50_CMD_FIFO_NUM,
72         IWL_TX_FIFO_HCCA_1,
73         IWL_TX_FIFO_HCCA_2
74 };
75
76 /* NIC configuration for 5000 series */
77 void iwl5000_nic_config(struct iwl_priv *priv)
78 {
79         unsigned long flags;
80         u16 radio_cfg;
81
82         spin_lock_irqsave(&priv->lock, flags);
83
84         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
85
86         /* write radio config values to register */
87         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
88                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
89                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
90                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
91                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
92
93         /* set CSR_HW_CONFIG_REG for uCode use */
94         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
95                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
96                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
97
98         /* W/A : NIC is stuck in a reset state after Early PCIe power off
99          * (PCIe power is lost before PERST# is asserted),
100          * causing ME FW to lose ownership and not being able to obtain it back.
101          */
102         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
103                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
104                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
105
106
107         spin_unlock_irqrestore(&priv->lock, flags);
108 }
109
110
111 /*
112  * EEPROM
113  */
114 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
115 {
116         u16 offset = 0;
117
118         if ((address & INDIRECT_ADDRESS) == 0)
119                 return address;
120
121         switch (address & INDIRECT_TYPE_MSK) {
122         case INDIRECT_HOST:
123                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
124                 break;
125         case INDIRECT_GENERAL:
126                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
127                 break;
128         case INDIRECT_REGULATORY:
129                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
130                 break;
131         case INDIRECT_CALIBRATION:
132                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
133                 break;
134         case INDIRECT_PROCESS_ADJST:
135                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
136                 break;
137         case INDIRECT_OTHERS:
138                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
139                 break;
140         default:
141                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
142                 address & INDIRECT_TYPE_MSK);
143                 break;
144         }
145
146         /* translate the offset from words to byte */
147         return (address & ADDRESS_MSK) + (offset << 1);
148 }
149
150 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
151 {
152         struct iwl_eeprom_calib_hdr {
153                 u8 version;
154                 u8 pa_type;
155                 u16 voltage;
156         } *hdr;
157
158         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
159                                                         EEPROM_5000_CALIB_ALL);
160         return hdr->version;
161
162 }
163
164 static void iwl5000_gain_computation(struct iwl_priv *priv,
165                 u32 average_noise[NUM_RX_CHAINS],
166                 u16 min_average_noise_antenna_i,
167                 u32 min_average_noise,
168                 u8 default_chain)
169 {
170         int i;
171         s32 delta_g;
172         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
173
174         /*
175          * Find Gain Code for the chains based on "default chain"
176          */
177         for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
178                 if ((data->disconn_array[i])) {
179                         data->delta_gain_code[i] = 0;
180                         continue;
181                 }
182
183                 delta_g = (priv->cfg->chain_noise_scale *
184                         ((s32)average_noise[default_chain] -
185                         (s32)average_noise[i])) / 1500;
186
187                 /* bound gain by 2 bits value max, 3rd bit is sign */
188                 data->delta_gain_code[i] =
189                         min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
190
191                 if (delta_g < 0)
192                         /*
193                          * set negative sign ...
194                          * note to Intel developers:  This is uCode API format,
195                          *   not the format of any internal device registers.
196                          *   Do not change this format for e.g. 6050 or similar
197                          *   devices.  Change format only if more resolution
198                          *   (i.e. more than 2 bits magnitude) is needed.
199                          */
200                         data->delta_gain_code[i] |= (1 << 2);
201         }
202
203         IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d  ANT_C = %d\n",
204                         data->delta_gain_code[1], data->delta_gain_code[2]);
205
206         if (!data->radio_write) {
207                 struct iwl_calib_chain_noise_gain_cmd cmd;
208
209                 memset(&cmd, 0, sizeof(cmd));
210
211                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
212                 cmd.hdr.first_group = 0;
213                 cmd.hdr.groups_num = 1;
214                 cmd.hdr.data_valid = 1;
215                 cmd.delta_gain_1 = data->delta_gain_code[1];
216                 cmd.delta_gain_2 = data->delta_gain_code[2];
217                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
218                         sizeof(cmd), &cmd, NULL);
219
220                 data->radio_write = 1;
221                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
222         }
223
224         data->chain_noise_a = 0;
225         data->chain_noise_b = 0;
226         data->chain_noise_c = 0;
227         data->chain_signal_a = 0;
228         data->chain_signal_b = 0;
229         data->chain_signal_c = 0;
230         data->beacon_count = 0;
231 }
232
233 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
234 {
235         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
236         int ret;
237
238         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
239                 struct iwl_calib_chain_noise_reset_cmd cmd;
240                 memset(&cmd, 0, sizeof(cmd));
241
242                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
243                 cmd.hdr.first_group = 0;
244                 cmd.hdr.groups_num = 1;
245                 cmd.hdr.data_valid = 1;
246                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
247                                         sizeof(cmd), &cmd);
248                 if (ret)
249                         IWL_ERR(priv,
250                                 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
251                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
252                 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
253         }
254 }
255
256 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
257                         __le32 *tx_flags)
258 {
259         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
260             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
261                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
262         else
263                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
264 }
265
266 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
267         .min_nrg_cck = 95,
268         .max_nrg_cck = 0, /* not used, set to 0 */
269         .auto_corr_min_ofdm = 90,
270         .auto_corr_min_ofdm_mrc = 170,
271         .auto_corr_min_ofdm_x1 = 120,
272         .auto_corr_min_ofdm_mrc_x1 = 240,
273
274         .auto_corr_max_ofdm = 120,
275         .auto_corr_max_ofdm_mrc = 210,
276         .auto_corr_max_ofdm_x1 = 120,
277         .auto_corr_max_ofdm_mrc_x1 = 240,
278
279         .auto_corr_min_cck = 125,
280         .auto_corr_max_cck = 200,
281         .auto_corr_min_cck_mrc = 170,
282         .auto_corr_max_cck_mrc = 400,
283         .nrg_th_cck = 95,
284         .nrg_th_ofdm = 95,
285
286         .barker_corr_th_min = 190,
287         .barker_corr_th_min_mrc = 390,
288         .nrg_th_cca = 62,
289 };
290
291 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
292         .min_nrg_cck = 95,
293         .max_nrg_cck = 0, /* not used, set to 0 */
294         .auto_corr_min_ofdm = 90,
295         .auto_corr_min_ofdm_mrc = 170,
296         .auto_corr_min_ofdm_x1 = 105,
297         .auto_corr_min_ofdm_mrc_x1 = 220,
298
299         .auto_corr_max_ofdm = 120,
300         .auto_corr_max_ofdm_mrc = 210,
301         /* max = min for performance bug in 5150 DSP */
302         .auto_corr_max_ofdm_x1 = 105,
303         .auto_corr_max_ofdm_mrc_x1 = 220,
304
305         .auto_corr_min_cck = 125,
306         .auto_corr_max_cck = 200,
307         .auto_corr_min_cck_mrc = 170,
308         .auto_corr_max_cck_mrc = 400,
309         .nrg_th_cck = 95,
310         .nrg_th_ofdm = 95,
311
312         .barker_corr_th_min = 190,
313         .barker_corr_th_min_mrc = 390,
314         .nrg_th_cca = 62,
315 };
316
317 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
318                                            size_t offset)
319 {
320         u32 address = eeprom_indirect_address(priv, offset);
321         BUG_ON(address >= priv->cfg->eeprom_size);
322         return &priv->eeprom[address];
323 }
324
325 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
326 {
327         const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
328         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
329                         iwl_temp_calib_to_offset(priv);
330
331         priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
332 }
333
334 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
335 {
336         /* want Celsius */
337         priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
338 }
339
340 /*
341  *  Calibration
342  */
343 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
344 {
345         struct iwl_calib_xtal_freq_cmd cmd;
346         __le16 *xtal_calib =
347                 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
348
349         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
350         cmd.hdr.first_group = 0;
351         cmd.hdr.groups_num = 1;
352         cmd.hdr.data_valid = 1;
353         cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
354         cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
355         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
356                              (u8 *)&cmd, sizeof(cmd));
357 }
358
359 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
360 {
361         struct iwl_calib_cfg_cmd calib_cfg_cmd;
362         struct iwl_host_cmd cmd = {
363                 .id = CALIBRATION_CFG_CMD,
364                 .len = sizeof(struct iwl_calib_cfg_cmd),
365                 .data = &calib_cfg_cmd,
366         };
367
368         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
369         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
370         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
371         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
372         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
373
374         return iwl_send_cmd(priv, &cmd);
375 }
376
377 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
378                              struct iwl_rx_mem_buffer *rxb)
379 {
380         struct iwl_rx_packet *pkt = rxb_addr(rxb);
381         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
382         int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
383         int index;
384
385         /* reduce the size of the length field itself */
386         len -= 4;
387
388         /* Define the order in which the results will be sent to the runtime
389          * uCode. iwl_send_calib_results sends them in a row according to their
390          * index. We sort them here */
391         switch (hdr->op_code) {
392         case IWL_PHY_CALIBRATE_DC_CMD:
393                 index = IWL_CALIB_DC;
394                 break;
395         case IWL_PHY_CALIBRATE_LO_CMD:
396                 index = IWL_CALIB_LO;
397                 break;
398         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
399                 index = IWL_CALIB_TX_IQ;
400                 break;
401         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
402                 index = IWL_CALIB_TX_IQ_PERD;
403                 break;
404         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
405                 index = IWL_CALIB_BASE_BAND;
406                 break;
407         default:
408                 IWL_ERR(priv, "Unknown calibration notification %d\n",
409                           hdr->op_code);
410                 return;
411         }
412         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
413 }
414
415 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
416                                struct iwl_rx_mem_buffer *rxb)
417 {
418         IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
419         queue_work(priv->workqueue, &priv->restart);
420 }
421
422 /*
423  * ucode
424  */
425 static int iwl5000_load_section(struct iwl_priv *priv, const char *name,
426                                 struct fw_desc *image, u32 dst_addr)
427 {
428         dma_addr_t phy_addr = image->p_addr;
429         u32 byte_cnt = image->len;
430         int ret;
431
432         priv->ucode_write_complete = 0;
433
434         iwl_write_direct32(priv,
435                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
436                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
437
438         iwl_write_direct32(priv,
439                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
440
441         iwl_write_direct32(priv,
442                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
443                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
444
445         iwl_write_direct32(priv,
446                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
447                 (iwl_get_dma_hi_addr(phy_addr)
448                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
449
450         iwl_write_direct32(priv,
451                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
452                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
453                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
454                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
455
456         iwl_write_direct32(priv,
457                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
458                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
459                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
460                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
461
462         IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
463         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
464                                         priv->ucode_write_complete, 5 * HZ);
465         if (ret == -ERESTARTSYS) {
466                 IWL_ERR(priv, "Could not load the %s uCode section due "
467                         "to interrupt\n", name);
468                 return ret;
469         }
470         if (!ret) {
471                 IWL_ERR(priv, "Could not load the %s uCode section\n",
472                         name);
473                 return -ETIMEDOUT;
474         }
475
476         return 0;
477 }
478
479 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
480                 struct fw_desc *inst_image,
481                 struct fw_desc *data_image)
482 {
483         int ret = 0;
484
485         ret = iwl5000_load_section(priv, "INST", inst_image,
486                                    IWL50_RTC_INST_LOWER_BOUND);
487         if (ret)
488                 return ret;
489
490         return iwl5000_load_section(priv, "DATA", data_image,
491                                     IWL50_RTC_DATA_LOWER_BOUND);
492 }
493
494 int iwl5000_load_ucode(struct iwl_priv *priv)
495 {
496         int ret = 0;
497
498         /* check whether init ucode should be loaded, or rather runtime ucode */
499         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
500                 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
501                 ret = iwl5000_load_given_ucode(priv,
502                         &priv->ucode_init, &priv->ucode_init_data);
503                 if (!ret) {
504                         IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
505                         priv->ucode_type = UCODE_INIT;
506                 }
507         } else {
508                 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
509                         "Loading runtime ucode...\n");
510                 ret = iwl5000_load_given_ucode(priv,
511                         &priv->ucode_code, &priv->ucode_data);
512                 if (!ret) {
513                         IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
514                         priv->ucode_type = UCODE_RT;
515                 }
516         }
517
518         return ret;
519 }
520
521 void iwl5000_init_alive_start(struct iwl_priv *priv)
522 {
523         int ret = 0;
524
525         /* Check alive response for "valid" sign from uCode */
526         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
527                 /* We had an error bringing up the hardware, so take it
528                  * all the way back down so we can try again */
529                 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
530                 goto restart;
531         }
532
533         /* initialize uCode was loaded... verify inst image.
534          * This is a paranoid check, because we would not have gotten the
535          * "initialize" alive if code weren't properly loaded.  */
536         if (iwl_verify_ucode(priv)) {
537                 /* Runtime instruction load was bad;
538                  * take it all the way back down so we can try again */
539                 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
540                 goto restart;
541         }
542
543         iwl_clear_stations_table(priv);
544         ret = priv->cfg->ops->lib->alive_notify(priv);
545         if (ret) {
546                 IWL_WARN(priv,
547                         "Could not complete ALIVE transition: %d\n", ret);
548                 goto restart;
549         }
550
551         iwl5000_send_calib_cfg(priv);
552         return;
553
554 restart:
555         /* real restart (first load init_ucode) */
556         queue_work(priv->workqueue, &priv->restart);
557 }
558
559 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
560                                 int txq_id, u32 index)
561 {
562         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
563                         (index & 0xff) | (txq_id << 8));
564         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
565 }
566
567 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
568                                         struct iwl_tx_queue *txq,
569                                         int tx_fifo_id, int scd_retry)
570 {
571         int txq_id = txq->q.id;
572         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
573
574         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
575                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
576                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
577                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
578                         IWL50_SCD_QUEUE_STTS_REG_MSK);
579
580         txq->sched_retry = scd_retry;
581
582         IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
583                        active ? "Activate" : "Deactivate",
584                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
585 }
586
587 int iwl5000_alive_notify(struct iwl_priv *priv)
588 {
589         u32 a;
590         unsigned long flags;
591         int i, chan;
592         u32 reg_val;
593
594         spin_lock_irqsave(&priv->lock, flags);
595
596         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
597         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
598         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
599                 a += 4)
600                 iwl_write_targ_mem(priv, a, 0);
601         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
602                 a += 4)
603                 iwl_write_targ_mem(priv, a, 0);
604         for (; a < priv->scd_base_addr +
605                IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
606                 iwl_write_targ_mem(priv, a, 0);
607
608         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
609                        priv->scd_bc_tbls.dma >> 10);
610
611         /* Enable DMA channel */
612         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
613                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
614                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
615                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
616
617         /* Update FH chicken bits */
618         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
619         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
620                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
621
622         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
623                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
624         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
625
626         /* initiate the queues */
627         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
628                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
629                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
630                 iwl_write_targ_mem(priv, priv->scd_base_addr +
631                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
632                 iwl_write_targ_mem(priv, priv->scd_base_addr +
633                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
634                                 sizeof(u32),
635                                 ((SCD_WIN_SIZE <<
636                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
637                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
638                                 ((SCD_FRAME_LIMIT <<
639                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
640                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
641         }
642
643         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
644                         IWL_MASK(0, priv->hw_params.max_txq_num));
645
646         /* Activate all Tx DMA/FIFO channels */
647         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
648
649         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
650
651         /* make sure all queue are not stopped */
652         memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
653         for (i = 0; i < 4; i++)
654                 atomic_set(&priv->queue_stop_count[i], 0);
655
656         /* reset to 0 to enable all the queue first */
657         priv->txq_ctx_active_msk = 0;
658         /* map qos queues to fifos one-to-one */
659         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
660                 int ac = iwl5000_default_queue_to_tx_fifo[i];
661                 iwl_txq_ctx_activate(priv, i);
662                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
663         }
664
665         /*
666          * TODO - need to initialize these queues and map them to FIFOs
667          * in the loop above, not only mark them as active. We do this
668          * because we want the first aggregation queue to be queue #10,
669          * but do not use 8 or 9 otherwise yet.
670          */
671         iwl_txq_ctx_activate(priv, 7);
672         iwl_txq_ctx_activate(priv, 8);
673         iwl_txq_ctx_activate(priv, 9);
674
675         spin_unlock_irqrestore(&priv->lock, flags);
676
677
678         iwl_send_wimax_coex(priv);
679
680         iwl5000_set_Xtal_calib(priv);
681         iwl_send_calib_results(priv);
682
683         return 0;
684 }
685
686 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
687 {
688         if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
689             priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
690                 priv->cfg->num_of_queues =
691                         priv->cfg->mod_params->num_of_queues;
692
693         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
694         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
695         priv->hw_params.scd_bc_tbls_size =
696                         priv->cfg->num_of_queues *
697                         sizeof(struct iwl5000_scd_bc_tbl);
698         priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
699         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
700         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
701
702         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
703         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
704
705         priv->hw_params.max_bsm_size = 0;
706         priv->hw_params.ht40_channel =  BIT(IEEE80211_BAND_2GHZ) |
707                                         BIT(IEEE80211_BAND_5GHZ);
708         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
709
710         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
711         priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
712         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
713         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
714
715         if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
716                 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
717
718         /* Set initial sensitivity parameters */
719         /* Set initial calibration set */
720         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
721         case CSR_HW_REV_TYPE_5150:
722                 priv->hw_params.sens = &iwl5150_sensitivity;
723                 priv->hw_params.calib_init_cfg =
724                         BIT(IWL_CALIB_DC)               |
725                         BIT(IWL_CALIB_LO)               |
726                         BIT(IWL_CALIB_TX_IQ)            |
727                         BIT(IWL_CALIB_BASE_BAND);
728
729                 break;
730         default:
731                 priv->hw_params.sens = &iwl5000_sensitivity;
732                 priv->hw_params.calib_init_cfg =
733                         BIT(IWL_CALIB_XTAL)             |
734                         BIT(IWL_CALIB_LO)               |
735                         BIT(IWL_CALIB_TX_IQ)            |
736                         BIT(IWL_CALIB_TX_IQ_PERD)       |
737                         BIT(IWL_CALIB_BASE_BAND);
738                 break;
739         }
740
741         return 0;
742 }
743
744 /**
745  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
746  */
747 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
748                                             struct iwl_tx_queue *txq,
749                                             u16 byte_cnt)
750 {
751         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
752         int write_ptr = txq->q.write_ptr;
753         int txq_id = txq->q.id;
754         u8 sec_ctl = 0;
755         u8 sta_id = 0;
756         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
757         __le16 bc_ent;
758
759         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
760
761         if (txq_id != IWL_CMD_QUEUE_NUM) {
762                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
763                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
764
765                 switch (sec_ctl & TX_CMD_SEC_MSK) {
766                 case TX_CMD_SEC_CCM:
767                         len += CCMP_MIC_LEN;
768                         break;
769                 case TX_CMD_SEC_TKIP:
770                         len += TKIP_ICV_LEN;
771                         break;
772                 case TX_CMD_SEC_WEP:
773                         len += WEP_IV_LEN + WEP_ICV_LEN;
774                         break;
775                 }
776         }
777
778         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
779
780         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
781
782         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
783                 scd_bc_tbl[txq_id].
784                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
785 }
786
787 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
788                                            struct iwl_tx_queue *txq)
789 {
790         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
791         int txq_id = txq->q.id;
792         int read_ptr = txq->q.read_ptr;
793         u8 sta_id = 0;
794         __le16 bc_ent;
795
796         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
797
798         if (txq_id != IWL_CMD_QUEUE_NUM)
799                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
800
801         bc_ent = cpu_to_le16(1 | (sta_id << 12));
802         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
803
804         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
805                 scd_bc_tbl[txq_id].
806                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
807 }
808
809 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
810                                         u16 txq_id)
811 {
812         u32 tbl_dw_addr;
813         u32 tbl_dw;
814         u16 scd_q2ratid;
815
816         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
817
818         tbl_dw_addr = priv->scd_base_addr +
819                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
820
821         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
822
823         if (txq_id & 0x1)
824                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
825         else
826                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
827
828         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
829
830         return 0;
831 }
832 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
833 {
834         /* Simply stop the queue, but don't change any configuration;
835          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
836         iwl_write_prph(priv,
837                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
838                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
839                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
840 }
841
842 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
843                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
844 {
845         unsigned long flags;
846         u16 ra_tid;
847
848         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
849             (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
850              <= txq_id)) {
851                 IWL_WARN(priv,
852                         "queue number out of range: %d, must be %d to %d\n",
853                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
854                         IWL50_FIRST_AMPDU_QUEUE +
855                         priv->cfg->num_of_ampdu_queues - 1);
856                 return -EINVAL;
857         }
858
859         ra_tid = BUILD_RAxTID(sta_id, tid);
860
861         /* Modify device's station table to Tx this TID */
862         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
863
864         spin_lock_irqsave(&priv->lock, flags);
865
866         /* Stop this Tx queue before configuring it */
867         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
868
869         /* Map receiver-address / traffic-ID to this queue */
870         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
871
872         /* Set this queue as a chain-building queue */
873         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
874
875         /* enable aggregations for the queue */
876         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
877
878         /* Place first TFD at index corresponding to start sequence number.
879          * Assumes that ssn_idx is valid (!= 0xFFF) */
880         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
881         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
882         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
883
884         /* Set up Tx window size and frame limit for this queue */
885         iwl_write_targ_mem(priv, priv->scd_base_addr +
886                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
887                         sizeof(u32),
888                         ((SCD_WIN_SIZE <<
889                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
890                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
891                         ((SCD_FRAME_LIMIT <<
892                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
893                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
894
895         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
896
897         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
898         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
899
900         spin_unlock_irqrestore(&priv->lock, flags);
901
902         return 0;
903 }
904
905 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
906                                    u16 ssn_idx, u8 tx_fifo)
907 {
908         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
909             (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
910              <= txq_id)) {
911                 IWL_ERR(priv,
912                         "queue number out of range: %d, must be %d to %d\n",
913                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
914                         IWL50_FIRST_AMPDU_QUEUE +
915                         priv->cfg->num_of_ampdu_queues - 1);
916                 return -EINVAL;
917         }
918
919         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
920
921         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
922
923         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
924         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
925         /* supposes that ssn_idx is valid (!= 0xFFF) */
926         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
927
928         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
929         iwl_txq_ctx_deactivate(priv, txq_id);
930         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
931
932         return 0;
933 }
934
935 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
936 {
937         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
938         struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
939         memcpy(addsta, cmd, size);
940         /* resrved in 5000 */
941         addsta->rate_n_flags = cpu_to_le16(0);
942         return size;
943 }
944
945
946 /*
947  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
948  * must be called under priv->lock and mac access
949  */
950 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
951 {
952         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
953 }
954
955
956 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
957 {
958         return le32_to_cpup((__le32 *)&tx_resp->status +
959                             tx_resp->frame_count) & MAX_SN;
960 }
961
962 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
963                                       struct iwl_ht_agg *agg,
964                                       struct iwl5000_tx_resp *tx_resp,
965                                       int txq_id, u16 start_idx)
966 {
967         u16 status;
968         struct agg_tx_status *frame_status = &tx_resp->status;
969         struct ieee80211_tx_info *info = NULL;
970         struct ieee80211_hdr *hdr = NULL;
971         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
972         int i, sh, idx;
973         u16 seq;
974
975         if (agg->wait_for_ba)
976                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
977
978         agg->frame_count = tx_resp->frame_count;
979         agg->start_idx = start_idx;
980         agg->rate_n_flags = rate_n_flags;
981         agg->bitmap = 0;
982
983         /* # frames attempted by Tx command */
984         if (agg->frame_count == 1) {
985                 /* Only one frame was attempted; no block-ack will arrive */
986                 status = le16_to_cpu(frame_status[0].status);
987                 idx = start_idx;
988
989                 /* FIXME: code repetition */
990                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
991                                    agg->frame_count, agg->start_idx, idx);
992
993                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
994                 info->status.rates[0].count = tx_resp->failure_frame + 1;
995                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
996                 info->flags |= iwl_tx_status_to_mac80211(status);
997                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
998
999                 /* FIXME: code repetition end */
1000
1001                 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1002                                     status & 0xff, tx_resp->failure_frame);
1003                 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1004
1005                 agg->wait_for_ba = 0;
1006         } else {
1007                 /* Two or more frames were attempted; expect block-ack */
1008                 u64 bitmap = 0;
1009                 int start = agg->start_idx;
1010
1011                 /* Construct bit-map of pending frames within Tx window */
1012                 for (i = 0; i < agg->frame_count; i++) {
1013                         u16 sc;
1014                         status = le16_to_cpu(frame_status[i].status);
1015                         seq  = le16_to_cpu(frame_status[i].sequence);
1016                         idx = SEQ_TO_INDEX(seq);
1017                         txq_id = SEQ_TO_QUEUE(seq);
1018
1019                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1020                                       AGG_TX_STATE_ABORT_MSK))
1021                                 continue;
1022
1023                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1024                                            agg->frame_count, txq_id, idx);
1025
1026                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1027                         if (!hdr) {
1028                                 IWL_ERR(priv,
1029                                         "BUG_ON idx doesn't point to valid skb"
1030                                         " idx=%d, txq_id=%d\n", idx, txq_id);
1031                                 return -1;
1032                         }
1033
1034                         sc = le16_to_cpu(hdr->seq_ctrl);
1035                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1036                                 IWL_ERR(priv,
1037                                         "BUG_ON idx doesn't match seq control"
1038                                         " idx=%d, seq_idx=%d, seq=%d\n",
1039                                           idx, SEQ_TO_SN(sc),
1040                                           hdr->seq_ctrl);
1041                                 return -1;
1042                         }
1043
1044                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1045                                            i, idx, SEQ_TO_SN(sc));
1046
1047                         sh = idx - start;
1048                         if (sh > 64) {
1049                                 sh = (start - idx) + 0xff;
1050                                 bitmap = bitmap << sh;
1051                                 sh = 0;
1052                                 start = idx;
1053                         } else if (sh < -64)
1054                                 sh  = 0xff - (start - idx);
1055                         else if (sh < 0) {
1056                                 sh = start - idx;
1057                                 start = idx;
1058                                 bitmap = bitmap << sh;
1059                                 sh = 0;
1060                         }
1061                         bitmap |= 1ULL << sh;
1062                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1063                                            start, (unsigned long long)bitmap);
1064                 }
1065
1066                 agg->bitmap = bitmap;
1067                 agg->start_idx = start;
1068                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1069                                    agg->frame_count, agg->start_idx,
1070                                    (unsigned long long)agg->bitmap);
1071
1072                 if (bitmap)
1073                         agg->wait_for_ba = 1;
1074         }
1075         return 0;
1076 }
1077
1078 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1079                                 struct iwl_rx_mem_buffer *rxb)
1080 {
1081         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1082         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1083         int txq_id = SEQ_TO_QUEUE(sequence);
1084         int index = SEQ_TO_INDEX(sequence);
1085         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1086         struct ieee80211_tx_info *info;
1087         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1088         u32  status = le16_to_cpu(tx_resp->status.status);
1089         int tid;
1090         int sta_id;
1091         int freed;
1092
1093         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1094                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1095                           "is out of range [0-%d] %d %d\n", txq_id,
1096                           index, txq->q.n_bd, txq->q.write_ptr,
1097                           txq->q.read_ptr);
1098                 return;
1099         }
1100
1101         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1102         memset(&info->status, 0, sizeof(info->status));
1103
1104         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1105         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1106
1107         if (txq->sched_retry) {
1108                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1109                 struct iwl_ht_agg *agg = NULL;
1110
1111                 agg = &priv->stations[sta_id].tid[tid].agg;
1112
1113                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1114
1115                 /* check if BAR is needed */
1116                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1117                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1118
1119                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1120                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1121                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1122                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1123                                         scd_ssn , index, txq_id, txq->swq_id);
1124
1125                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1126                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1127
1128                         if (priv->mac80211_registered &&
1129                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1130                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1131                                 if (agg->state == IWL_AGG_OFF)
1132                                         iwl_wake_queue(priv, txq_id);
1133                                 else
1134                                         iwl_wake_queue(priv, txq->swq_id);
1135                         }
1136                 }
1137         } else {
1138                 BUG_ON(txq_id != txq->swq_id);
1139
1140                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1141                 info->flags |= iwl_tx_status_to_mac80211(status);
1142                 iwl_hwrate_to_tx_control(priv,
1143                                         le32_to_cpu(tx_resp->rate_n_flags),
1144                                         info);
1145
1146                 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1147                                    "0x%x retries %d\n",
1148                                    txq_id,
1149                                    iwl_get_tx_fail_reason(status), status,
1150                                    le32_to_cpu(tx_resp->rate_n_flags),
1151                                    tx_resp->failure_frame);
1152
1153                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1154                 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1155                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1156
1157                 if (priv->mac80211_registered &&
1158                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1159                         iwl_wake_queue(priv, txq_id);
1160         }
1161
1162         if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1163                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1164
1165         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1166                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
1167 }
1168
1169 /* Currently 5000 is the superset of everything */
1170 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1171 {
1172         return len;
1173 }
1174
1175 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1176 {
1177         /* in 5000 the tx power calibration is done in uCode */
1178         priv->disable_tx_power_cal = 1;
1179 }
1180
1181 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1182 {
1183         /* init calibration handlers */
1184         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1185                                         iwl5000_rx_calib_result;
1186         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1187                                         iwl5000_rx_calib_complete;
1188         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1189 }
1190
1191
1192 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1193 {
1194         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1195                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1196 }
1197
1198 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1199 {
1200         int ret = 0;
1201         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1202         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1203         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1204
1205         if ((rxon1->flags == rxon2->flags) &&
1206             (rxon1->filter_flags == rxon2->filter_flags) &&
1207             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1208             (rxon1->ofdm_ht_single_stream_basic_rates ==
1209              rxon2->ofdm_ht_single_stream_basic_rates) &&
1210             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1211              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1212             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1213              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1214             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1215             (rxon1->rx_chain == rxon2->rx_chain) &&
1216             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1217                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1218                 return 0;
1219         }
1220
1221         rxon_assoc.flags = priv->staging_rxon.flags;
1222         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1223         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1224         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1225         rxon_assoc.reserved1 = 0;
1226         rxon_assoc.reserved2 = 0;
1227         rxon_assoc.reserved3 = 0;
1228         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1229             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1230         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1231             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1232         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1233         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1234                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1235         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1236
1237         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1238                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1239         if (ret)
1240                 return ret;
1241
1242         return ret;
1243 }
1244 int  iwl5000_send_tx_power(struct iwl_priv *priv)
1245 {
1246         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1247         u8 tx_ant_cfg_cmd;
1248
1249         /* half dBm need to multiply */
1250         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1251
1252         if (priv->tx_power_lmt_in_half_dbm &&
1253             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
1254                 /*
1255                  * For the newer devices which using enhanced/extend tx power
1256                  * table in EEPROM, the format is in half dBm. driver need to
1257                  * convert to dBm format before report to mac80211.
1258                  * By doing so, there is a possibility of 1/2 dBm resolution
1259                  * lost. driver will perform "round-up" operation before
1260                  * reporting, but it will cause 1/2 dBm tx power over the
1261                  * regulatory limit. Perform the checking here, if the
1262                  * "tx_power_user_lmt" is higher than EEPROM value (in
1263                  * half-dBm format), lower the tx power based on EEPROM
1264                  */
1265                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
1266         }
1267         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1268         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1269
1270         if (IWL_UCODE_API(priv->ucode_ver) == 1)
1271                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1272         else
1273                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1274
1275         return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1276                                        sizeof(tx_power_cmd), &tx_power_cmd,
1277                                        NULL);
1278 }
1279
1280 void iwl5000_temperature(struct iwl_priv *priv)
1281 {
1282         /* store temperature from statistics (in Celsius) */
1283         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1284         iwl_tt_handler(priv);
1285 }
1286
1287 static void iwl5150_temperature(struct iwl_priv *priv)
1288 {
1289         u32 vt = 0;
1290         s32 offset =  iwl_temp_calib_to_offset(priv);
1291
1292         vt = le32_to_cpu(priv->statistics.general.temperature);
1293         vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1294         /* now vt hold the temperature in Kelvin */
1295         priv->temperature = KELVIN_TO_CELSIUS(vt);
1296         iwl_tt_handler(priv);
1297 }
1298
1299 /* Calc max signal level (dBm) among 3 possible receivers */
1300 int iwl5000_calc_rssi(struct iwl_priv *priv,
1301                              struct iwl_rx_phy_res *rx_resp)
1302 {
1303         /* data from PHY/DSP regarding signal strength, etc.,
1304          *   contents are always there, not configurable by host
1305          */
1306         struct iwl5000_non_cfg_phy *ncphy =
1307                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1308         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1309         u8 agc;
1310
1311         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1312         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1313
1314         /* Find max rssi among 3 possible receivers.
1315          * These values are measured by the digital signal processor (DSP).
1316          * They should stay fairly constant even as the signal strength varies,
1317          *   if the radio's automatic gain control (AGC) is working right.
1318          * AGC value (see below) will provide the "interesting" info.
1319          */
1320         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1321         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1322         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1323         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1324         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1325
1326         max_rssi = max_t(u32, rssi_a, rssi_b);
1327         max_rssi = max_t(u32, max_rssi, rssi_c);
1328
1329         IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1330                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1331
1332         /* dBm = max_rssi dB - agc dB - constant.
1333          * Higher AGC (higher radio gain) means lower signal. */
1334         return max_rssi - agc - IWL49_RSSI_OFFSET;
1335 }
1336
1337 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1338 {
1339         struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1340           .valid = cpu_to_le32(valid_tx_ant),
1341         };
1342
1343         if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1344                 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1345                 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1346                                         sizeof(struct iwl_tx_ant_config_cmd),
1347                                         &tx_ant_cmd);
1348         } else {
1349                 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1350                 return -EOPNOTSUPP;
1351         }
1352 }
1353
1354
1355 #define IWL5000_UCODE_GET(item)                                         \
1356 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1357                                     u32 api_ver)                        \
1358 {                                                                       \
1359         if (api_ver <= 2)                                               \
1360                 return le32_to_cpu(ucode->u.v1.item);                   \
1361         return le32_to_cpu(ucode->u.v2.item);                           \
1362 }
1363
1364 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1365 {
1366         if (api_ver <= 2)
1367                 return UCODE_HEADER_SIZE(1);
1368         return UCODE_HEADER_SIZE(2);
1369 }
1370
1371 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1372                                    u32 api_ver)
1373 {
1374         if (api_ver <= 2)
1375                 return 0;
1376         return le32_to_cpu(ucode->u.v2.build);
1377 }
1378
1379 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1380                                   u32 api_ver)
1381 {
1382         if (api_ver <= 2)
1383                 return (u8 *) ucode->u.v1.data;
1384         return (u8 *) ucode->u.v2.data;
1385 }
1386
1387 IWL5000_UCODE_GET(inst_size);
1388 IWL5000_UCODE_GET(data_size);
1389 IWL5000_UCODE_GET(init_size);
1390 IWL5000_UCODE_GET(init_data_size);
1391 IWL5000_UCODE_GET(boot_size);
1392
1393 static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1394 {
1395         struct iwl5000_channel_switch_cmd cmd;
1396         const struct iwl_channel_info *ch_info;
1397         struct iwl_host_cmd hcmd = {
1398                 .id = REPLY_CHANNEL_SWITCH,
1399                 .len = sizeof(cmd),
1400                 .flags = CMD_SIZE_HUGE,
1401                 .data = &cmd,
1402         };
1403
1404         IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
1405                 priv->active_rxon.channel, channel);
1406         cmd.band = priv->band == IEEE80211_BAND_2GHZ;
1407         cmd.channel = cpu_to_le16(channel);
1408         cmd.rxon_flags = priv->staging_rxon.flags;
1409         cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
1410         cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1411         ch_info = iwl_get_channel_info(priv, priv->band, channel);
1412         if (ch_info)
1413                 cmd.expect_beacon = is_channel_radar(ch_info);
1414         else {
1415                 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1416                         priv->active_rxon.channel, channel);
1417                 return -EFAULT;
1418         }
1419         priv->switch_rxon.channel = cpu_to_le16(channel);
1420         priv->switch_rxon.switch_in_progress = true;
1421
1422         return iwl_send_cmd_sync(priv, &hcmd);
1423 }
1424
1425 struct iwl_hcmd_ops iwl5000_hcmd = {
1426         .rxon_assoc = iwl5000_send_rxon_assoc,
1427         .commit_rxon = iwl_commit_rxon,
1428         .set_rxon_chain = iwl_set_rxon_chain,
1429         .set_tx_ant = iwl5000_send_tx_ant_config,
1430 };
1431
1432 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1433         .get_hcmd_size = iwl5000_get_hcmd_size,
1434         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1435         .gain_computation = iwl5000_gain_computation,
1436         .chain_noise_reset = iwl5000_chain_noise_reset,
1437         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1438         .calc_rssi = iwl5000_calc_rssi,
1439 };
1440
1441 struct iwl_ucode_ops iwl5000_ucode = {
1442         .get_header_size = iwl5000_ucode_get_header_size,
1443         .get_build = iwl5000_ucode_get_build,
1444         .get_inst_size = iwl5000_ucode_get_inst_size,
1445         .get_data_size = iwl5000_ucode_get_data_size,
1446         .get_init_size = iwl5000_ucode_get_init_size,
1447         .get_init_data_size = iwl5000_ucode_get_init_data_size,
1448         .get_boot_size = iwl5000_ucode_get_boot_size,
1449         .get_data = iwl5000_ucode_get_data,
1450 };
1451
1452 struct iwl_lib_ops iwl5000_lib = {
1453         .set_hw_params = iwl5000_hw_set_hw_params,
1454         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1455         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1456         .txq_set_sched = iwl5000_txq_set_sched,
1457         .txq_agg_enable = iwl5000_txq_agg_enable,
1458         .txq_agg_disable = iwl5000_txq_agg_disable,
1459         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1460         .txq_free_tfd = iwl_hw_txq_free_tfd,
1461         .txq_init = iwl_hw_tx_queue_init,
1462         .rx_handler_setup = iwl5000_rx_handler_setup,
1463         .setup_deferred_work = iwl5000_setup_deferred_work,
1464         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1465         .dump_nic_event_log = iwl_dump_nic_event_log,
1466         .dump_nic_error_log = iwl_dump_nic_error_log,
1467         .dump_csr = iwl_dump_csr,
1468         .dump_fh = iwl_dump_fh,
1469         .load_ucode = iwl5000_load_ucode,
1470         .init_alive_start = iwl5000_init_alive_start,
1471         .alive_notify = iwl5000_alive_notify,
1472         .send_tx_power = iwl5000_send_tx_power,
1473         .update_chain_flags = iwl_update_chain_flags,
1474         .set_channel_switch = iwl5000_hw_channel_switch,
1475         .apm_ops = {
1476                 .init = iwl_apm_init,
1477                 .stop = iwl_apm_stop,
1478                 .config = iwl5000_nic_config,
1479                 .set_pwr_src = iwl_set_pwr_src,
1480         },
1481         .eeprom_ops = {
1482                 .regulatory_bands = {
1483                         EEPROM_5000_REG_BAND_1_CHANNELS,
1484                         EEPROM_5000_REG_BAND_2_CHANNELS,
1485                         EEPROM_5000_REG_BAND_3_CHANNELS,
1486                         EEPROM_5000_REG_BAND_4_CHANNELS,
1487                         EEPROM_5000_REG_BAND_5_CHANNELS,
1488                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1489                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1490                 },
1491                 .verify_signature  = iwlcore_eeprom_verify_signature,
1492                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1493                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1494                 .calib_version  = iwl5000_eeprom_calib_version,
1495                 .query_addr = iwl5000_eeprom_query_addr,
1496         },
1497         .post_associate = iwl_post_associate,
1498         .isr = iwl_isr_ict,
1499         .config_ap = iwl_config_ap,
1500         .temp_ops = {
1501                 .temperature = iwl5000_temperature,
1502                 .set_ct_kill = iwl5000_set_ct_threshold,
1503          },
1504         .add_bcast_station = iwl_add_bcast_station,
1505 };
1506
1507 static struct iwl_lib_ops iwl5150_lib = {
1508         .set_hw_params = iwl5000_hw_set_hw_params,
1509         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1510         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1511         .txq_set_sched = iwl5000_txq_set_sched,
1512         .txq_agg_enable = iwl5000_txq_agg_enable,
1513         .txq_agg_disable = iwl5000_txq_agg_disable,
1514         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1515         .txq_free_tfd = iwl_hw_txq_free_tfd,
1516         .txq_init = iwl_hw_tx_queue_init,
1517         .rx_handler_setup = iwl5000_rx_handler_setup,
1518         .setup_deferred_work = iwl5000_setup_deferred_work,
1519         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1520         .dump_nic_event_log = iwl_dump_nic_event_log,
1521         .dump_nic_error_log = iwl_dump_nic_error_log,
1522         .dump_csr = iwl_dump_csr,
1523         .load_ucode = iwl5000_load_ucode,
1524         .init_alive_start = iwl5000_init_alive_start,
1525         .alive_notify = iwl5000_alive_notify,
1526         .send_tx_power = iwl5000_send_tx_power,
1527         .update_chain_flags = iwl_update_chain_flags,
1528         .set_channel_switch = iwl5000_hw_channel_switch,
1529         .apm_ops = {
1530                 .init = iwl_apm_init,
1531                 .stop = iwl_apm_stop,
1532                 .config = iwl5000_nic_config,
1533                 .set_pwr_src = iwl_set_pwr_src,
1534         },
1535         .eeprom_ops = {
1536                 .regulatory_bands = {
1537                         EEPROM_5000_REG_BAND_1_CHANNELS,
1538                         EEPROM_5000_REG_BAND_2_CHANNELS,
1539                         EEPROM_5000_REG_BAND_3_CHANNELS,
1540                         EEPROM_5000_REG_BAND_4_CHANNELS,
1541                         EEPROM_5000_REG_BAND_5_CHANNELS,
1542                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1543                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1544                 },
1545                 .verify_signature  = iwlcore_eeprom_verify_signature,
1546                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1547                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1548                 .calib_version  = iwl5000_eeprom_calib_version,
1549                 .query_addr = iwl5000_eeprom_query_addr,
1550         },
1551         .post_associate = iwl_post_associate,
1552         .isr = iwl_isr_ict,
1553         .config_ap = iwl_config_ap,
1554         .temp_ops = {
1555                 .temperature = iwl5150_temperature,
1556                 .set_ct_kill = iwl5150_set_ct_threshold,
1557          },
1558         .add_bcast_station = iwl_add_bcast_station,
1559 };
1560
1561 static const struct iwl_ops iwl5000_ops = {
1562         .ucode = &iwl5000_ucode,
1563         .lib = &iwl5000_lib,
1564         .hcmd = &iwl5000_hcmd,
1565         .utils = &iwl5000_hcmd_utils,
1566         .led = &iwlagn_led_ops,
1567 };
1568
1569 static const struct iwl_ops iwl5150_ops = {
1570         .ucode = &iwl5000_ucode,
1571         .lib = &iwl5150_lib,
1572         .hcmd = &iwl5000_hcmd,
1573         .utils = &iwl5000_hcmd_utils,
1574         .led = &iwlagn_led_ops,
1575 };
1576
1577 struct iwl_mod_params iwl50_mod_params = {
1578         .amsdu_size_8K = 1,
1579         .restart_fw = 1,
1580         /* the rest are 0 by default */
1581 };
1582
1583
1584 struct iwl_cfg iwl5300_agn_cfg = {
1585         .name = "5300AGN",
1586         .fw_name_pre = IWL5000_FW_PRE,
1587         .ucode_api_max = IWL5000_UCODE_API_MAX,
1588         .ucode_api_min = IWL5000_UCODE_API_MIN,
1589         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1590         .ops = &iwl5000_ops,
1591         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1592         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1593         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1594         .num_of_queues = IWL50_NUM_QUEUES,
1595         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1596         .mod_params = &iwl50_mod_params,
1597         .valid_tx_ant = ANT_ABC,
1598         .valid_rx_ant = ANT_ABC,
1599         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1600         .set_l0s = true,
1601         .use_bsm = false,
1602         .ht_greenfield_support = true,
1603         .led_compensation = 51,
1604         .use_rts_for_ht = true, /* use rts/cts protection */
1605         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1606         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1607         .chain_noise_scale = 1000,
1608 };
1609
1610 struct iwl_cfg iwl5100_bgn_cfg = {
1611         .name = "5100BGN",
1612         .fw_name_pre = IWL5000_FW_PRE,
1613         .ucode_api_max = IWL5000_UCODE_API_MAX,
1614         .ucode_api_min = IWL5000_UCODE_API_MIN,
1615         .sku = IWL_SKU_G|IWL_SKU_N,
1616         .ops = &iwl5000_ops,
1617         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1618         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1619         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1620         .num_of_queues = IWL50_NUM_QUEUES,
1621         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1622         .mod_params = &iwl50_mod_params,
1623         .valid_tx_ant = ANT_B,
1624         .valid_rx_ant = ANT_AB,
1625         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1626         .set_l0s = true,
1627         .use_bsm = false,
1628         .ht_greenfield_support = true,
1629         .led_compensation = 51,
1630         .use_rts_for_ht = true, /* use rts/cts protection */
1631         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1632         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1633         .chain_noise_scale = 1000,
1634 };
1635
1636 struct iwl_cfg iwl5100_abg_cfg = {
1637         .name = "5100ABG",
1638         .fw_name_pre = IWL5000_FW_PRE,
1639         .ucode_api_max = IWL5000_UCODE_API_MAX,
1640         .ucode_api_min = IWL5000_UCODE_API_MIN,
1641         .sku = IWL_SKU_A|IWL_SKU_G,
1642         .ops = &iwl5000_ops,
1643         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1644         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1645         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1646         .num_of_queues = IWL50_NUM_QUEUES,
1647         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1648         .mod_params = &iwl50_mod_params,
1649         .valid_tx_ant = ANT_B,
1650         .valid_rx_ant = ANT_AB,
1651         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1652         .set_l0s = true,
1653         .use_bsm = false,
1654         .led_compensation = 51,
1655         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1656         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1657         .chain_noise_scale = 1000,
1658 };
1659
1660 struct iwl_cfg iwl5100_agn_cfg = {
1661         .name = "5100AGN",
1662         .fw_name_pre = IWL5000_FW_PRE,
1663         .ucode_api_max = IWL5000_UCODE_API_MAX,
1664         .ucode_api_min = IWL5000_UCODE_API_MIN,
1665         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1666         .ops = &iwl5000_ops,
1667         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1668         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1669         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1670         .num_of_queues = IWL50_NUM_QUEUES,
1671         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1672         .mod_params = &iwl50_mod_params,
1673         .valid_tx_ant = ANT_B,
1674         .valid_rx_ant = ANT_AB,
1675         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1676         .set_l0s = true,
1677         .use_bsm = false,
1678         .ht_greenfield_support = true,
1679         .led_compensation = 51,
1680         .use_rts_for_ht = true, /* use rts/cts protection */
1681         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1682         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1683         .chain_noise_scale = 1000,
1684 };
1685
1686 struct iwl_cfg iwl5350_agn_cfg = {
1687         .name = "5350AGN",
1688         .fw_name_pre = IWL5000_FW_PRE,
1689         .ucode_api_max = IWL5000_UCODE_API_MAX,
1690         .ucode_api_min = IWL5000_UCODE_API_MIN,
1691         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1692         .ops = &iwl5000_ops,
1693         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1694         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1695         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1696         .num_of_queues = IWL50_NUM_QUEUES,
1697         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1698         .mod_params = &iwl50_mod_params,
1699         .valid_tx_ant = ANT_ABC,
1700         .valid_rx_ant = ANT_ABC,
1701         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1702         .set_l0s = true,
1703         .use_bsm = false,
1704         .ht_greenfield_support = true,
1705         .led_compensation = 51,
1706         .use_rts_for_ht = true, /* use rts/cts protection */
1707         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1708         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1709         .chain_noise_scale = 1000,
1710 };
1711
1712 struct iwl_cfg iwl5150_agn_cfg = {
1713         .name = "5150AGN",
1714         .fw_name_pre = IWL5150_FW_PRE,
1715         .ucode_api_max = IWL5150_UCODE_API_MAX,
1716         .ucode_api_min = IWL5150_UCODE_API_MIN,
1717         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1718         .ops = &iwl5150_ops,
1719         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1720         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1721         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1722         .num_of_queues = IWL50_NUM_QUEUES,
1723         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1724         .mod_params = &iwl50_mod_params,
1725         .valid_tx_ant = ANT_A,
1726         .valid_rx_ant = ANT_AB,
1727         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1728         .set_l0s = true,
1729         .use_bsm = false,
1730         .ht_greenfield_support = true,
1731         .led_compensation = 51,
1732         .use_rts_for_ht = true, /* use rts/cts protection */
1733         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1734         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1735         .chain_noise_scale = 1000,
1736 };
1737
1738 struct iwl_cfg iwl5150_abg_cfg = {
1739         .name = "5150ABG",
1740         .fw_name_pre = IWL5150_FW_PRE,
1741         .ucode_api_max = IWL5150_UCODE_API_MAX,
1742         .ucode_api_min = IWL5150_UCODE_API_MIN,
1743         .sku = IWL_SKU_A|IWL_SKU_G,
1744         .ops = &iwl5150_ops,
1745         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1746         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1747         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1748         .num_of_queues = IWL50_NUM_QUEUES,
1749         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1750         .mod_params = &iwl50_mod_params,
1751         .valid_tx_ant = ANT_A,
1752         .valid_rx_ant = ANT_AB,
1753         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1754         .set_l0s = true,
1755         .use_bsm = false,
1756         .led_compensation = 51,
1757         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1758         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1759         .chain_noise_scale = 1000,
1760 };
1761
1762 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1763 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1764
1765 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1766 MODULE_PARM_DESC(swcrypto50,
1767                   "using software crypto engine (default 0 [hardware])\n");
1768 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1769 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1770 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1771 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1772 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1773                    int, S_IRUGO);
1774 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1775 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1776 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");