iwlwifi: LED cleanup
[linux-2.6.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
1 /******************************************************************************
2  *
3  * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23  *
24  *****************************************************************************/
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
38
39 #include "iwl-eeprom.h"
40 #include "iwl-dev.h"
41 #include "iwl-core.h"
42 #include "iwl-io.h"
43 #include "iwl-sta.h"
44 #include "iwl-helpers.h"
45 #include "iwl-agn-led.h"
46 #include "iwl-5000-hw.h"
47 #include "iwl-6000-hw.h"
48
49 /* Highest firmware API version supported */
50 #define IWL5000_UCODE_API_MAX 2
51 #define IWL5150_UCODE_API_MAX 2
52
53 /* Lowest firmware API version supported */
54 #define IWL5000_UCODE_API_MIN 1
55 #define IWL5150_UCODE_API_MIN 1
56
57 #define IWL5000_FW_PRE "iwlwifi-5000-"
58 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
59 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
60
61 #define IWL5150_FW_PRE "iwlwifi-5150-"
62 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
63 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
64
65 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
66         IWL_TX_FIFO_AC3,
67         IWL_TX_FIFO_AC2,
68         IWL_TX_FIFO_AC1,
69         IWL_TX_FIFO_AC0,
70         IWL50_CMD_FIFO_NUM,
71         IWL_TX_FIFO_HCCA_1,
72         IWL_TX_FIFO_HCCA_2
73 };
74
75 /* FIXME: same implementation as 4965 */
76 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
77 {
78         unsigned long flags;
79
80         spin_lock_irqsave(&priv->lock, flags);
81
82         /* set stop master bit */
83         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
84
85         iwl_poll_direct_bit(priv, CSR_RESET,
86                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
87
88         spin_unlock_irqrestore(&priv->lock, flags);
89         IWL_DEBUG_INFO(priv, "stop master\n");
90
91         return 0;
92 }
93
94
95 int iwl5000_apm_init(struct iwl_priv *priv)
96 {
97         int ret = 0;
98
99         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
100                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
101
102         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
103         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
104                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
105
106         /* Set FH wait threshold to maximum (HW error during stress W/A) */
107         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
108
109         /* enable HAP INTA to move device L1a -> L0s */
110         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
111                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
112
113         if (priv->cfg->need_pll_cfg)
114                 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
115
116         /* set "initialization complete" bit to move adapter
117          * D0U* --> D0A* state */
118         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
119
120         /* wait for clock stabilization */
121         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
122                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
123         if (ret < 0) {
124                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
125                 return ret;
126         }
127
128         /* enable DMA */
129         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
130
131         udelay(20);
132
133         /* disable L1-Active */
134         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
135                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
136
137         return ret;
138 }
139
140 /* FIXME: this is identical to 4965 */
141 void iwl5000_apm_stop(struct iwl_priv *priv)
142 {
143         unsigned long flags;
144
145         iwl5000_apm_stop_master(priv);
146
147         spin_lock_irqsave(&priv->lock, flags);
148
149         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
150
151         udelay(10);
152
153         /* clear "init complete"  move adapter D0A* --> D0U state */
154         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
155
156         spin_unlock_irqrestore(&priv->lock, flags);
157 }
158
159
160 int iwl5000_apm_reset(struct iwl_priv *priv)
161 {
162         int ret = 0;
163
164         iwl5000_apm_stop_master(priv);
165
166         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
167
168         udelay(10);
169
170
171         /* FIXME: put here L1A -L0S w/a */
172
173         if (priv->cfg->need_pll_cfg)
174                 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
175
176         /* set "initialization complete" bit to move adapter
177          * D0U* --> D0A* state */
178         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
179
180         /* wait for clock stabilization */
181         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
182                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
183         if (ret < 0) {
184                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
185                 goto out;
186         }
187
188         /* enable DMA */
189         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
190
191         udelay(20);
192
193         /* disable L1-Active */
194         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
195                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
196 out:
197
198         return ret;
199 }
200
201
202 /* NIC configuration for 5000 series */
203 void iwl5000_nic_config(struct iwl_priv *priv)
204 {
205         unsigned long flags;
206         u16 radio_cfg;
207         u16 lctl;
208
209         spin_lock_irqsave(&priv->lock, flags);
210
211         lctl = iwl_pcie_link_ctl(priv);
212
213         /* HW bug W/A */
214         /* L1-ASPM is enabled by BIOS */
215         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
216                 /* L1-APSM enabled: disable L0S  */
217                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
218         else
219                 /* L1-ASPM disabled: enable L0S */
220                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
221
222         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
223
224         /* write radio config values to register */
225         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
226                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
227                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
228                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
229                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
230
231         /* set CSR_HW_CONFIG_REG for uCode use */
232         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
233                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
234                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
235
236         /* W/A : NIC is stuck in a reset state after Early PCIe power off
237          * (PCIe power is lost before PERST# is asserted),
238          * causing ME FW to lose ownership and not being able to obtain it back.
239          */
240         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
241                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
242                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
243
244
245         spin_unlock_irqrestore(&priv->lock, flags);
246 }
247
248
249 /*
250  * EEPROM
251  */
252 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
253 {
254         u16 offset = 0;
255
256         if ((address & INDIRECT_ADDRESS) == 0)
257                 return address;
258
259         switch (address & INDIRECT_TYPE_MSK) {
260         case INDIRECT_HOST:
261                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
262                 break;
263         case INDIRECT_GENERAL:
264                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
265                 break;
266         case INDIRECT_REGULATORY:
267                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
268                 break;
269         case INDIRECT_CALIBRATION:
270                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
271                 break;
272         case INDIRECT_PROCESS_ADJST:
273                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
274                 break;
275         case INDIRECT_OTHERS:
276                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
277                 break;
278         default:
279                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
280                 address & INDIRECT_TYPE_MSK);
281                 break;
282         }
283
284         /* translate the offset from words to byte */
285         return (address & ADDRESS_MSK) + (offset << 1);
286 }
287
288 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
289 {
290         struct iwl_eeprom_calib_hdr {
291                 u8 version;
292                 u8 pa_type;
293                 u16 voltage;
294         } *hdr;
295
296         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
297                                                         EEPROM_5000_CALIB_ALL);
298         return hdr->version;
299
300 }
301
302 static void iwl5000_gain_computation(struct iwl_priv *priv,
303                 u32 average_noise[NUM_RX_CHAINS],
304                 u16 min_average_noise_antenna_i,
305                 u32 min_average_noise,
306                 u8 default_chain)
307 {
308         int i;
309         s32 delta_g;
310         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
311
312         /*
313          * Find Gain Code for the chains based on "default chain"
314          */
315         for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
316                 if ((data->disconn_array[i])) {
317                         data->delta_gain_code[i] = 0;
318                         continue;
319                 }
320                 delta_g = (1000 * ((s32)average_noise[0] -
321                         (s32)average_noise[i])) / 1500;
322                 /* bound gain by 2 bits value max, 3rd bit is sign */
323                 data->delta_gain_code[i] =
324                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
325
326                 if (delta_g < 0)
327                         /* set negative sign */
328                         data->delta_gain_code[i] |= (1 << 2);
329         }
330
331         IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d  ANT_C = %d\n",
332                         data->delta_gain_code[1], data->delta_gain_code[2]);
333
334         if (!data->radio_write) {
335                 struct iwl_calib_chain_noise_gain_cmd cmd;
336
337                 memset(&cmd, 0, sizeof(cmd));
338
339                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
340                 cmd.hdr.first_group = 0;
341                 cmd.hdr.groups_num = 1;
342                 cmd.hdr.data_valid = 1;
343                 cmd.delta_gain_1 = data->delta_gain_code[1];
344                 cmd.delta_gain_2 = data->delta_gain_code[2];
345                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
346                         sizeof(cmd), &cmd, NULL);
347
348                 data->radio_write = 1;
349                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
350         }
351
352         data->chain_noise_a = 0;
353         data->chain_noise_b = 0;
354         data->chain_noise_c = 0;
355         data->chain_signal_a = 0;
356         data->chain_signal_b = 0;
357         data->chain_signal_c = 0;
358         data->beacon_count = 0;
359 }
360
361 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
362 {
363         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
364         int ret;
365
366         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
367                 struct iwl_calib_chain_noise_reset_cmd cmd;
368                 memset(&cmd, 0, sizeof(cmd));
369
370                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
371                 cmd.hdr.first_group = 0;
372                 cmd.hdr.groups_num = 1;
373                 cmd.hdr.data_valid = 1;
374                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
375                                         sizeof(cmd), &cmd);
376                 if (ret)
377                         IWL_ERR(priv,
378                                 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
379                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
380                 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
381         }
382 }
383
384 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
385                         __le32 *tx_flags)
386 {
387         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
388             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
389                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
390         else
391                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
392 }
393
394 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
395         .min_nrg_cck = 95,
396         .max_nrg_cck = 0, /* not used, set to 0 */
397         .auto_corr_min_ofdm = 90,
398         .auto_corr_min_ofdm_mrc = 170,
399         .auto_corr_min_ofdm_x1 = 120,
400         .auto_corr_min_ofdm_mrc_x1 = 240,
401
402         .auto_corr_max_ofdm = 120,
403         .auto_corr_max_ofdm_mrc = 210,
404         .auto_corr_max_ofdm_x1 = 155,
405         .auto_corr_max_ofdm_mrc_x1 = 290,
406
407         .auto_corr_min_cck = 125,
408         .auto_corr_max_cck = 200,
409         .auto_corr_min_cck_mrc = 170,
410         .auto_corr_max_cck_mrc = 400,
411         .nrg_th_cck = 95,
412         .nrg_th_ofdm = 95,
413 };
414
415 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
416         .min_nrg_cck = 95,
417         .max_nrg_cck = 0, /* not used, set to 0 */
418         .auto_corr_min_ofdm = 90,
419         .auto_corr_min_ofdm_mrc = 170,
420         .auto_corr_min_ofdm_x1 = 105,
421         .auto_corr_min_ofdm_mrc_x1 = 220,
422
423         .auto_corr_max_ofdm = 120,
424         .auto_corr_max_ofdm_mrc = 210,
425         /* max = min for performance bug in 5150 DSP */
426         .auto_corr_max_ofdm_x1 = 105,
427         .auto_corr_max_ofdm_mrc_x1 = 220,
428
429         .auto_corr_min_cck = 125,
430         .auto_corr_max_cck = 200,
431         .auto_corr_min_cck_mrc = 170,
432         .auto_corr_max_cck_mrc = 400,
433         .nrg_th_cck = 95,
434         .nrg_th_ofdm = 95,
435 };
436
437 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
438                                            size_t offset)
439 {
440         u32 address = eeprom_indirect_address(priv, offset);
441         BUG_ON(address >= priv->cfg->eeprom_size);
442         return &priv->eeprom[address];
443 }
444
445 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
446 {
447         const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
448         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
449                         iwl_temp_calib_to_offset(priv);
450
451         priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
452 }
453
454 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
455 {
456         /* want Celsius */
457         priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
458 }
459
460 /*
461  *  Calibration
462  */
463 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
464 {
465         struct iwl_calib_xtal_freq_cmd cmd;
466         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
467
468         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
469         cmd.hdr.first_group = 0;
470         cmd.hdr.groups_num = 1;
471         cmd.hdr.data_valid = 1;
472         cmd.cap_pin1 = (u8)xtal_calib[0];
473         cmd.cap_pin2 = (u8)xtal_calib[1];
474         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
475                              (u8 *)&cmd, sizeof(cmd));
476 }
477
478 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
479 {
480         struct iwl_calib_cfg_cmd calib_cfg_cmd;
481         struct iwl_host_cmd cmd = {
482                 .id = CALIBRATION_CFG_CMD,
483                 .len = sizeof(struct iwl_calib_cfg_cmd),
484                 .data = &calib_cfg_cmd,
485         };
486
487         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
488         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
489         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
490         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
491         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
492
493         return iwl_send_cmd(priv, &cmd);
494 }
495
496 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
497                              struct iwl_rx_mem_buffer *rxb)
498 {
499         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
500         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
501         int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
502         int index;
503
504         /* reduce the size of the length field itself */
505         len -= 4;
506
507         /* Define the order in which the results will be sent to the runtime
508          * uCode. iwl_send_calib_results sends them in a row according to their
509          * index. We sort them here */
510         switch (hdr->op_code) {
511         case IWL_PHY_CALIBRATE_DC_CMD:
512                 index = IWL_CALIB_DC;
513                 break;
514         case IWL_PHY_CALIBRATE_LO_CMD:
515                 index = IWL_CALIB_LO;
516                 break;
517         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
518                 index = IWL_CALIB_TX_IQ;
519                 break;
520         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
521                 index = IWL_CALIB_TX_IQ_PERD;
522                 break;
523         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
524                 index = IWL_CALIB_BASE_BAND;
525                 break;
526         default:
527                 IWL_ERR(priv, "Unknown calibration notification %d\n",
528                           hdr->op_code);
529                 return;
530         }
531         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
532 }
533
534 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
535                                struct iwl_rx_mem_buffer *rxb)
536 {
537         IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
538         queue_work(priv->workqueue, &priv->restart);
539 }
540
541 /*
542  * ucode
543  */
544 static int iwl5000_load_section(struct iwl_priv *priv,
545                                 struct fw_desc *image,
546                                 u32 dst_addr)
547 {
548         dma_addr_t phy_addr = image->p_addr;
549         u32 byte_cnt = image->len;
550
551         iwl_write_direct32(priv,
552                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
553                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
554
555         iwl_write_direct32(priv,
556                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
557
558         iwl_write_direct32(priv,
559                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
560                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
561
562         iwl_write_direct32(priv,
563                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
564                 (iwl_get_dma_hi_addr(phy_addr)
565                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
566
567         iwl_write_direct32(priv,
568                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
569                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
570                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
571                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
572
573         iwl_write_direct32(priv,
574                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
575                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
576                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
577                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
578
579         return 0;
580 }
581
582 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
583                 struct fw_desc *inst_image,
584                 struct fw_desc *data_image)
585 {
586         int ret = 0;
587
588         ret = iwl5000_load_section(priv, inst_image,
589                                    IWL50_RTC_INST_LOWER_BOUND);
590         if (ret)
591                 return ret;
592
593         IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
594         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
595                                         priv->ucode_write_complete, 5 * HZ);
596         if (ret == -ERESTARTSYS) {
597                 IWL_ERR(priv, "Could not load the INST uCode section due "
598                         "to interrupt\n");
599                 return ret;
600         }
601         if (!ret) {
602                 IWL_ERR(priv, "Could not load the INST uCode section\n");
603                 return -ETIMEDOUT;
604         }
605
606         priv->ucode_write_complete = 0;
607
608         ret = iwl5000_load_section(
609                 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
610         if (ret)
611                 return ret;
612
613         IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
614
615         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
616                                 priv->ucode_write_complete, 5 * HZ);
617         if (ret == -ERESTARTSYS) {
618                 IWL_ERR(priv, "Could not load the INST uCode section due "
619                         "to interrupt\n");
620                 return ret;
621         } else if (!ret) {
622                 IWL_ERR(priv, "Could not load the DATA uCode section\n");
623                 return -ETIMEDOUT;
624         } else
625                 ret = 0;
626
627         priv->ucode_write_complete = 0;
628
629         return ret;
630 }
631
632 int iwl5000_load_ucode(struct iwl_priv *priv)
633 {
634         int ret = 0;
635
636         /* check whether init ucode should be loaded, or rather runtime ucode */
637         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
638                 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
639                 ret = iwl5000_load_given_ucode(priv,
640                         &priv->ucode_init, &priv->ucode_init_data);
641                 if (!ret) {
642                         IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
643                         priv->ucode_type = UCODE_INIT;
644                 }
645         } else {
646                 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
647                         "Loading runtime ucode...\n");
648                 ret = iwl5000_load_given_ucode(priv,
649                         &priv->ucode_code, &priv->ucode_data);
650                 if (!ret) {
651                         IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
652                         priv->ucode_type = UCODE_RT;
653                 }
654         }
655
656         return ret;
657 }
658
659 void iwl5000_init_alive_start(struct iwl_priv *priv)
660 {
661         int ret = 0;
662
663         /* Check alive response for "valid" sign from uCode */
664         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
665                 /* We had an error bringing up the hardware, so take it
666                  * all the way back down so we can try again */
667                 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
668                 goto restart;
669         }
670
671         /* initialize uCode was loaded... verify inst image.
672          * This is a paranoid check, because we would not have gotten the
673          * "initialize" alive if code weren't properly loaded.  */
674         if (iwl_verify_ucode(priv)) {
675                 /* Runtime instruction load was bad;
676                  * take it all the way back down so we can try again */
677                 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
678                 goto restart;
679         }
680
681         iwl_clear_stations_table(priv);
682         ret = priv->cfg->ops->lib->alive_notify(priv);
683         if (ret) {
684                 IWL_WARN(priv,
685                         "Could not complete ALIVE transition: %d\n", ret);
686                 goto restart;
687         }
688
689         iwl5000_send_calib_cfg(priv);
690         return;
691
692 restart:
693         /* real restart (first load init_ucode) */
694         queue_work(priv->workqueue, &priv->restart);
695 }
696
697 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
698                                 int txq_id, u32 index)
699 {
700         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
701                         (index & 0xff) | (txq_id << 8));
702         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
703 }
704
705 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
706                                         struct iwl_tx_queue *txq,
707                                         int tx_fifo_id, int scd_retry)
708 {
709         int txq_id = txq->q.id;
710         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
711
712         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
713                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
714                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
715                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
716                         IWL50_SCD_QUEUE_STTS_REG_MSK);
717
718         txq->sched_retry = scd_retry;
719
720         IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
721                        active ? "Activate" : "Deactivate",
722                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
723 }
724
725 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
726 {
727         struct iwl_wimax_coex_cmd coex_cmd;
728
729         memset(&coex_cmd, 0, sizeof(coex_cmd));
730
731         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
732                                 sizeof(coex_cmd), &coex_cmd);
733 }
734
735 int iwl5000_alive_notify(struct iwl_priv *priv)
736 {
737         u32 a;
738         unsigned long flags;
739         int i, chan;
740         u32 reg_val;
741
742         spin_lock_irqsave(&priv->lock, flags);
743
744         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
745         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
746         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
747                 a += 4)
748                 iwl_write_targ_mem(priv, a, 0);
749         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
750                 a += 4)
751                 iwl_write_targ_mem(priv, a, 0);
752         for (; a < priv->scd_base_addr +
753                IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
754                 iwl_write_targ_mem(priv, a, 0);
755
756         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
757                        priv->scd_bc_tbls.dma >> 10);
758
759         /* Enable DMA channel */
760         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
761                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
762                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
763                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
764
765         /* Update FH chicken bits */
766         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
767         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
768                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
769
770         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
771                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
772         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
773
774         /* initiate the queues */
775         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
776                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
777                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
778                 iwl_write_targ_mem(priv, priv->scd_base_addr +
779                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
780                 iwl_write_targ_mem(priv, priv->scd_base_addr +
781                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
782                                 sizeof(u32),
783                                 ((SCD_WIN_SIZE <<
784                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
785                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
786                                 ((SCD_FRAME_LIMIT <<
787                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
788                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
789         }
790
791         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
792                         IWL_MASK(0, priv->hw_params.max_txq_num));
793
794         /* Activate all Tx DMA/FIFO channels */
795         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
796
797         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
798
799         /* map qos queues to fifos one-to-one */
800         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
801                 int ac = iwl5000_default_queue_to_tx_fifo[i];
802                 iwl_txq_ctx_activate(priv, i);
803                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
804         }
805         /* TODO - need to initialize those FIFOs inside the loop above,
806          * not only mark them as active */
807         iwl_txq_ctx_activate(priv, 4);
808         iwl_txq_ctx_activate(priv, 7);
809         iwl_txq_ctx_activate(priv, 8);
810         iwl_txq_ctx_activate(priv, 9);
811
812         spin_unlock_irqrestore(&priv->lock, flags);
813
814
815         iwl5000_send_wimax_coex(priv);
816
817         iwl5000_set_Xtal_calib(priv);
818         iwl_send_calib_results(priv);
819
820         return 0;
821 }
822
823 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
824 {
825         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
826             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
827                 IWL_ERR(priv,
828                         "invalid queues_num, should be between %d and %d\n",
829                         IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
830                 return -EINVAL;
831         }
832
833         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
834         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
835         priv->hw_params.scd_bc_tbls_size =
836                         IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
837         priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
838         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
839         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
840
841         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
842         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
843
844         priv->hw_params.max_bsm_size = 0;
845         priv->hw_params.ht40_channel =  BIT(IEEE80211_BAND_2GHZ) |
846                                         BIT(IEEE80211_BAND_5GHZ);
847         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
848
849         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
850         priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
851         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
852         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
853
854         if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
855                 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
856
857         /* Set initial sensitivity parameters */
858         /* Set initial calibration set */
859         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
860         case CSR_HW_REV_TYPE_5150:
861                 priv->hw_params.sens = &iwl5150_sensitivity;
862                 priv->hw_params.calib_init_cfg =
863                         BIT(IWL_CALIB_DC)               |
864                         BIT(IWL_CALIB_LO)               |
865                         BIT(IWL_CALIB_TX_IQ)            |
866                         BIT(IWL_CALIB_BASE_BAND);
867
868                 break;
869         default:
870                 priv->hw_params.sens = &iwl5000_sensitivity;
871                 priv->hw_params.calib_init_cfg =
872                         BIT(IWL_CALIB_XTAL)             |
873                         BIT(IWL_CALIB_LO)               |
874                         BIT(IWL_CALIB_TX_IQ)            |
875                         BIT(IWL_CALIB_TX_IQ_PERD)       |
876                         BIT(IWL_CALIB_BASE_BAND);
877                 break;
878         }
879
880         return 0;
881 }
882
883 /**
884  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
885  */
886 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
887                                             struct iwl_tx_queue *txq,
888                                             u16 byte_cnt)
889 {
890         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
891         int write_ptr = txq->q.write_ptr;
892         int txq_id = txq->q.id;
893         u8 sec_ctl = 0;
894         u8 sta_id = 0;
895         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
896         __le16 bc_ent;
897
898         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
899
900         if (txq_id != IWL_CMD_QUEUE_NUM) {
901                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
902                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
903
904                 switch (sec_ctl & TX_CMD_SEC_MSK) {
905                 case TX_CMD_SEC_CCM:
906                         len += CCMP_MIC_LEN;
907                         break;
908                 case TX_CMD_SEC_TKIP:
909                         len += TKIP_ICV_LEN;
910                         break;
911                 case TX_CMD_SEC_WEP:
912                         len += WEP_IV_LEN + WEP_ICV_LEN;
913                         break;
914                 }
915         }
916
917         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
918
919         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
920
921         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
922                 scd_bc_tbl[txq_id].
923                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
924 }
925
926 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
927                                            struct iwl_tx_queue *txq)
928 {
929         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
930         int txq_id = txq->q.id;
931         int read_ptr = txq->q.read_ptr;
932         u8 sta_id = 0;
933         __le16 bc_ent;
934
935         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
936
937         if (txq_id != IWL_CMD_QUEUE_NUM)
938                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
939
940         bc_ent =  cpu_to_le16(1 | (sta_id << 12));
941         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
942
943         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
944                 scd_bc_tbl[txq_id].
945                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =  bc_ent;
946 }
947
948 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
949                                         u16 txq_id)
950 {
951         u32 tbl_dw_addr;
952         u32 tbl_dw;
953         u16 scd_q2ratid;
954
955         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
956
957         tbl_dw_addr = priv->scd_base_addr +
958                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
959
960         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
961
962         if (txq_id & 0x1)
963                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
964         else
965                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
966
967         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
968
969         return 0;
970 }
971 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
972 {
973         /* Simply stop the queue, but don't change any configuration;
974          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
975         iwl_write_prph(priv,
976                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
977                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
978                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
979 }
980
981 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
982                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
983 {
984         unsigned long flags;
985         u16 ra_tid;
986
987         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
988             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
989                 IWL_WARN(priv,
990                         "queue number out of range: %d, must be %d to %d\n",
991                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
992                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
993                 return -EINVAL;
994         }
995
996         ra_tid = BUILD_RAxTID(sta_id, tid);
997
998         /* Modify device's station table to Tx this TID */
999         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1000
1001         spin_lock_irqsave(&priv->lock, flags);
1002
1003         /* Stop this Tx queue before configuring it */
1004         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1005
1006         /* Map receiver-address / traffic-ID to this queue */
1007         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1008
1009         /* Set this queue as a chain-building queue */
1010         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1011
1012         /* enable aggregations for the queue */
1013         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1014
1015         /* Place first TFD at index corresponding to start sequence number.
1016          * Assumes that ssn_idx is valid (!= 0xFFF) */
1017         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1018         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1019         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1020
1021         /* Set up Tx window size and frame limit for this queue */
1022         iwl_write_targ_mem(priv, priv->scd_base_addr +
1023                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1024                         sizeof(u32),
1025                         ((SCD_WIN_SIZE <<
1026                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1027                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1028                         ((SCD_FRAME_LIMIT <<
1029                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1030                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1031
1032         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1033
1034         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1035         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1036
1037         spin_unlock_irqrestore(&priv->lock, flags);
1038
1039         return 0;
1040 }
1041
1042 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1043                                    u16 ssn_idx, u8 tx_fifo)
1044 {
1045         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1046             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1047                 IWL_ERR(priv,
1048                         "queue number out of range: %d, must be %d to %d\n",
1049                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1050                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1051                 return -EINVAL;
1052         }
1053
1054         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1055
1056         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1057
1058         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1059         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1060         /* supposes that ssn_idx is valid (!= 0xFFF) */
1061         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1062
1063         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1064         iwl_txq_ctx_deactivate(priv, txq_id);
1065         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1066
1067         return 0;
1068 }
1069
1070 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1071 {
1072         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1073         struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1074         memcpy(addsta, cmd, size);
1075         /* resrved in 5000 */
1076         addsta->rate_n_flags = cpu_to_le16(0);
1077         return size;
1078 }
1079
1080
1081 /*
1082  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1083  * must be called under priv->lock and mac access
1084  */
1085 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1086 {
1087         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1088 }
1089
1090
1091 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1092 {
1093         return le32_to_cpup((__le32 *)&tx_resp->status +
1094                             tx_resp->frame_count) & MAX_SN;
1095 }
1096
1097 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1098                                       struct iwl_ht_agg *agg,
1099                                       struct iwl5000_tx_resp *tx_resp,
1100                                       int txq_id, u16 start_idx)
1101 {
1102         u16 status;
1103         struct agg_tx_status *frame_status = &tx_resp->status;
1104         struct ieee80211_tx_info *info = NULL;
1105         struct ieee80211_hdr *hdr = NULL;
1106         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1107         int i, sh, idx;
1108         u16 seq;
1109
1110         if (agg->wait_for_ba)
1111                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1112
1113         agg->frame_count = tx_resp->frame_count;
1114         agg->start_idx = start_idx;
1115         agg->rate_n_flags = rate_n_flags;
1116         agg->bitmap = 0;
1117
1118         /* # frames attempted by Tx command */
1119         if (agg->frame_count == 1) {
1120                 /* Only one frame was attempted; no block-ack will arrive */
1121                 status = le16_to_cpu(frame_status[0].status);
1122                 idx = start_idx;
1123
1124                 /* FIXME: code repetition */
1125                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1126                                    agg->frame_count, agg->start_idx, idx);
1127
1128                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1129                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1130                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1131                 info->flags |= iwl_is_tx_success(status) ?
1132                                         IEEE80211_TX_STAT_ACK : 0;
1133                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1134
1135                 /* FIXME: code repetition end */
1136
1137                 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1138                                     status & 0xff, tx_resp->failure_frame);
1139                 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1140
1141                 agg->wait_for_ba = 0;
1142         } else {
1143                 /* Two or more frames were attempted; expect block-ack */
1144                 u64 bitmap = 0;
1145                 int start = agg->start_idx;
1146
1147                 /* Construct bit-map of pending frames within Tx window */
1148                 for (i = 0; i < agg->frame_count; i++) {
1149                         u16 sc;
1150                         status = le16_to_cpu(frame_status[i].status);
1151                         seq  = le16_to_cpu(frame_status[i].sequence);
1152                         idx = SEQ_TO_INDEX(seq);
1153                         txq_id = SEQ_TO_QUEUE(seq);
1154
1155                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1156                                       AGG_TX_STATE_ABORT_MSK))
1157                                 continue;
1158
1159                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1160                                            agg->frame_count, txq_id, idx);
1161
1162                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1163                         if (!hdr) {
1164                                 IWL_ERR(priv,
1165                                         "BUG_ON idx doesn't point to valid skb"
1166                                         " idx=%d, txq_id=%d\n", idx, txq_id);
1167                                 return -1;
1168                         }
1169
1170                         sc = le16_to_cpu(hdr->seq_ctrl);
1171                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1172                                 IWL_ERR(priv,
1173                                         "BUG_ON idx doesn't match seq control"
1174                                         " idx=%d, seq_idx=%d, seq=%d\n",
1175                                           idx, SEQ_TO_SN(sc),
1176                                           hdr->seq_ctrl);
1177                                 return -1;
1178                         }
1179
1180                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1181                                            i, idx, SEQ_TO_SN(sc));
1182
1183                         sh = idx - start;
1184                         if (sh > 64) {
1185                                 sh = (start - idx) + 0xff;
1186                                 bitmap = bitmap << sh;
1187                                 sh = 0;
1188                                 start = idx;
1189                         } else if (sh < -64)
1190                                 sh  = 0xff - (start - idx);
1191                         else if (sh < 0) {
1192                                 sh = start - idx;
1193                                 start = idx;
1194                                 bitmap = bitmap << sh;
1195                                 sh = 0;
1196                         }
1197                         bitmap |= 1ULL << sh;
1198                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1199                                            start, (unsigned long long)bitmap);
1200                 }
1201
1202                 agg->bitmap = bitmap;
1203                 agg->start_idx = start;
1204                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1205                                    agg->frame_count, agg->start_idx,
1206                                    (unsigned long long)agg->bitmap);
1207
1208                 if (bitmap)
1209                         agg->wait_for_ba = 1;
1210         }
1211         return 0;
1212 }
1213
1214 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1215                                 struct iwl_rx_mem_buffer *rxb)
1216 {
1217         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1218         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1219         int txq_id = SEQ_TO_QUEUE(sequence);
1220         int index = SEQ_TO_INDEX(sequence);
1221         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1222         struct ieee80211_tx_info *info;
1223         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1224         u32  status = le16_to_cpu(tx_resp->status.status);
1225         int tid;
1226         int sta_id;
1227         int freed;
1228
1229         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1230                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1231                           "is out of range [0-%d] %d %d\n", txq_id,
1232                           index, txq->q.n_bd, txq->q.write_ptr,
1233                           txq->q.read_ptr);
1234                 return;
1235         }
1236
1237         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1238         memset(&info->status, 0, sizeof(info->status));
1239
1240         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1241         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1242
1243         if (txq->sched_retry) {
1244                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1245                 struct iwl_ht_agg *agg = NULL;
1246
1247                 agg = &priv->stations[sta_id].tid[tid].agg;
1248
1249                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1250
1251                 /* check if BAR is needed */
1252                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1253                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1254
1255                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1256                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1257                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1258                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1259                                         scd_ssn , index, txq_id, txq->swq_id);
1260
1261                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1262                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1263
1264                         if (priv->mac80211_registered &&
1265                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1266                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1267                                 if (agg->state == IWL_AGG_OFF)
1268                                         iwl_wake_queue(priv, txq_id);
1269                                 else
1270                                         iwl_wake_queue(priv, txq->swq_id);
1271                         }
1272                 }
1273         } else {
1274                 BUG_ON(txq_id != txq->swq_id);
1275
1276                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1277                 info->flags |= iwl_is_tx_success(status) ?
1278                                         IEEE80211_TX_STAT_ACK : 0;
1279                 iwl_hwrate_to_tx_control(priv,
1280                                         le32_to_cpu(tx_resp->rate_n_flags),
1281                                         info);
1282
1283                 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1284                                    "0x%x retries %d\n",
1285                                    txq_id,
1286                                    iwl_get_tx_fail_reason(status), status,
1287                                    le32_to_cpu(tx_resp->rate_n_flags),
1288                                    tx_resp->failure_frame);
1289
1290                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1291                 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1292                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1293
1294                 if (priv->mac80211_registered &&
1295                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1296                         iwl_wake_queue(priv, txq_id);
1297         }
1298
1299         if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1300                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1301
1302         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1303                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
1304 }
1305
1306 /* Currently 5000 is the superset of everything */
1307 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1308 {
1309         return len;
1310 }
1311
1312 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1313 {
1314         /* in 5000 the tx power calibration is done in uCode */
1315         priv->disable_tx_power_cal = 1;
1316 }
1317
1318 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1319 {
1320         /* init calibration handlers */
1321         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1322                                         iwl5000_rx_calib_result;
1323         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1324                                         iwl5000_rx_calib_complete;
1325         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1326 }
1327
1328
1329 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1330 {
1331         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1332                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1333 }
1334
1335 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1336 {
1337         int ret = 0;
1338         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1339         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1340         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1341
1342         if ((rxon1->flags == rxon2->flags) &&
1343             (rxon1->filter_flags == rxon2->filter_flags) &&
1344             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1345             (rxon1->ofdm_ht_single_stream_basic_rates ==
1346              rxon2->ofdm_ht_single_stream_basic_rates) &&
1347             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1348              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1349             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1350              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1351             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1352             (rxon1->rx_chain == rxon2->rx_chain) &&
1353             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1354                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1355                 return 0;
1356         }
1357
1358         rxon_assoc.flags = priv->staging_rxon.flags;
1359         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1360         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1361         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1362         rxon_assoc.reserved1 = 0;
1363         rxon_assoc.reserved2 = 0;
1364         rxon_assoc.reserved3 = 0;
1365         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1366             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1367         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1368             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1369         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1370         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1371                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1372         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1373
1374         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1375                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1376         if (ret)
1377                 return ret;
1378
1379         return ret;
1380 }
1381 int  iwl5000_send_tx_power(struct iwl_priv *priv)
1382 {
1383         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1384         u8 tx_ant_cfg_cmd;
1385
1386         /* half dBm need to multiply */
1387         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1388         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1389         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1390
1391         if (IWL_UCODE_API(priv->ucode_ver) == 1)
1392                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1393         else
1394                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1395
1396         return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1397                                        sizeof(tx_power_cmd), &tx_power_cmd,
1398                                        NULL);
1399 }
1400
1401 void iwl5000_temperature(struct iwl_priv *priv)
1402 {
1403         /* store temperature from statistics (in Celsius) */
1404         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1405         iwl_tt_handler(priv);
1406 }
1407
1408 static void iwl5150_temperature(struct iwl_priv *priv)
1409 {
1410         u32 vt = 0;
1411         s32 offset =  iwl_temp_calib_to_offset(priv);
1412
1413         vt = le32_to_cpu(priv->statistics.general.temperature);
1414         vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1415         /* now vt hold the temperature in Kelvin */
1416         priv->temperature = KELVIN_TO_CELSIUS(vt);
1417         iwl_tt_handler(priv);
1418 }
1419
1420 /* Calc max signal level (dBm) among 3 possible receivers */
1421 int iwl5000_calc_rssi(struct iwl_priv *priv,
1422                              struct iwl_rx_phy_res *rx_resp)
1423 {
1424         /* data from PHY/DSP regarding signal strength, etc.,
1425          *   contents are always there, not configurable by host
1426          */
1427         struct iwl5000_non_cfg_phy *ncphy =
1428                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1429         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1430         u8 agc;
1431
1432         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1433         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1434
1435         /* Find max rssi among 3 possible receivers.
1436          * These values are measured by the digital signal processor (DSP).
1437          * They should stay fairly constant even as the signal strength varies,
1438          *   if the radio's automatic gain control (AGC) is working right.
1439          * AGC value (see below) will provide the "interesting" info.
1440          */
1441         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1442         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1443         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1444         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1445         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1446
1447         max_rssi = max_t(u32, rssi_a, rssi_b);
1448         max_rssi = max_t(u32, max_rssi, rssi_c);
1449
1450         IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1451                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1452
1453         /* dBm = max_rssi dB - agc dB - constant.
1454          * Higher AGC (higher radio gain) means lower signal. */
1455         return max_rssi - agc - IWL49_RSSI_OFFSET;
1456 }
1457
1458 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1459 {
1460         struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1461           .valid = cpu_to_le32(valid_tx_ant),
1462         };
1463
1464         if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1465                 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1466                 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1467                                         sizeof(struct iwl_tx_ant_config_cmd),
1468                                         &tx_ant_cmd);
1469         } else {
1470                 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1471                 return -EOPNOTSUPP;
1472         }
1473 }
1474
1475
1476 #define IWL5000_UCODE_GET(item)                                         \
1477 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1478                                     u32 api_ver)                        \
1479 {                                                                       \
1480         if (api_ver <= 2)                                               \
1481                 return le32_to_cpu(ucode->u.v1.item);                   \
1482         return le32_to_cpu(ucode->u.v2.item);                           \
1483 }
1484
1485 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1486 {
1487         if (api_ver <= 2)
1488                 return UCODE_HEADER_SIZE(1);
1489         return UCODE_HEADER_SIZE(2);
1490 }
1491
1492 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1493                                    u32 api_ver)
1494 {
1495         if (api_ver <= 2)
1496                 return 0;
1497         return le32_to_cpu(ucode->u.v2.build);
1498 }
1499
1500 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1501                                   u32 api_ver)
1502 {
1503         if (api_ver <= 2)
1504                 return (u8 *) ucode->u.v1.data;
1505         return (u8 *) ucode->u.v2.data;
1506 }
1507
1508 IWL5000_UCODE_GET(inst_size);
1509 IWL5000_UCODE_GET(data_size);
1510 IWL5000_UCODE_GET(init_size);
1511 IWL5000_UCODE_GET(init_data_size);
1512 IWL5000_UCODE_GET(boot_size);
1513
1514 struct iwl_hcmd_ops iwl5000_hcmd = {
1515         .rxon_assoc = iwl5000_send_rxon_assoc,
1516         .commit_rxon = iwl_commit_rxon,
1517         .set_rxon_chain = iwl_set_rxon_chain,
1518         .set_tx_ant = iwl5000_send_tx_ant_config,
1519 };
1520
1521 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1522         .get_hcmd_size = iwl5000_get_hcmd_size,
1523         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1524         .gain_computation = iwl5000_gain_computation,
1525         .chain_noise_reset = iwl5000_chain_noise_reset,
1526         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1527         .calc_rssi = iwl5000_calc_rssi,
1528 };
1529
1530 struct iwl_ucode_ops iwl5000_ucode = {
1531         .get_header_size = iwl5000_ucode_get_header_size,
1532         .get_build = iwl5000_ucode_get_build,
1533         .get_inst_size = iwl5000_ucode_get_inst_size,
1534         .get_data_size = iwl5000_ucode_get_data_size,
1535         .get_init_size = iwl5000_ucode_get_init_size,
1536         .get_init_data_size = iwl5000_ucode_get_init_data_size,
1537         .get_boot_size = iwl5000_ucode_get_boot_size,
1538         .get_data = iwl5000_ucode_get_data,
1539 };
1540
1541 struct iwl_lib_ops iwl5000_lib = {
1542         .set_hw_params = iwl5000_hw_set_hw_params,
1543         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1544         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1545         .txq_set_sched = iwl5000_txq_set_sched,
1546         .txq_agg_enable = iwl5000_txq_agg_enable,
1547         .txq_agg_disable = iwl5000_txq_agg_disable,
1548         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1549         .txq_free_tfd = iwl_hw_txq_free_tfd,
1550         .txq_init = iwl_hw_tx_queue_init,
1551         .rx_handler_setup = iwl5000_rx_handler_setup,
1552         .setup_deferred_work = iwl5000_setup_deferred_work,
1553         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1554         .dump_nic_event_log = iwl_dump_nic_event_log,
1555         .dump_nic_error_log = iwl_dump_nic_error_log,
1556         .load_ucode = iwl5000_load_ucode,
1557         .init_alive_start = iwl5000_init_alive_start,
1558         .alive_notify = iwl5000_alive_notify,
1559         .send_tx_power = iwl5000_send_tx_power,
1560         .update_chain_flags = iwl_update_chain_flags,
1561         .apm_ops = {
1562                 .init = iwl5000_apm_init,
1563                 .reset = iwl5000_apm_reset,
1564                 .stop = iwl5000_apm_stop,
1565                 .config = iwl5000_nic_config,
1566                 .set_pwr_src = iwl_set_pwr_src,
1567         },
1568         .eeprom_ops = {
1569                 .regulatory_bands = {
1570                         EEPROM_5000_REG_BAND_1_CHANNELS,
1571                         EEPROM_5000_REG_BAND_2_CHANNELS,
1572                         EEPROM_5000_REG_BAND_3_CHANNELS,
1573                         EEPROM_5000_REG_BAND_4_CHANNELS,
1574                         EEPROM_5000_REG_BAND_5_CHANNELS,
1575                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1576                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1577                 },
1578                 .verify_signature  = iwlcore_eeprom_verify_signature,
1579                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1580                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1581                 .calib_version  = iwl5000_eeprom_calib_version,
1582                 .query_addr = iwl5000_eeprom_query_addr,
1583         },
1584         .post_associate = iwl_post_associate,
1585         .isr = iwl_isr_ict,
1586         .config_ap = iwl_config_ap,
1587         .temp_ops = {
1588                 .temperature = iwl5000_temperature,
1589                 .set_ct_kill = iwl5000_set_ct_threshold,
1590          },
1591 };
1592
1593 static struct iwl_lib_ops iwl5150_lib = {
1594         .set_hw_params = iwl5000_hw_set_hw_params,
1595         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1596         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1597         .txq_set_sched = iwl5000_txq_set_sched,
1598         .txq_agg_enable = iwl5000_txq_agg_enable,
1599         .txq_agg_disable = iwl5000_txq_agg_disable,
1600         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1601         .txq_free_tfd = iwl_hw_txq_free_tfd,
1602         .txq_init = iwl_hw_tx_queue_init,
1603         .rx_handler_setup = iwl5000_rx_handler_setup,
1604         .setup_deferred_work = iwl5000_setup_deferred_work,
1605         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1606         .dump_nic_event_log = iwl_dump_nic_event_log,
1607         .dump_nic_error_log = iwl_dump_nic_error_log,
1608         .load_ucode = iwl5000_load_ucode,
1609         .init_alive_start = iwl5000_init_alive_start,
1610         .alive_notify = iwl5000_alive_notify,
1611         .send_tx_power = iwl5000_send_tx_power,
1612         .update_chain_flags = iwl_update_chain_flags,
1613         .apm_ops = {
1614                 .init = iwl5000_apm_init,
1615                 .reset = iwl5000_apm_reset,
1616                 .stop = iwl5000_apm_stop,
1617                 .config = iwl5000_nic_config,
1618                 .set_pwr_src = iwl_set_pwr_src,
1619         },
1620         .eeprom_ops = {
1621                 .regulatory_bands = {
1622                         EEPROM_5000_REG_BAND_1_CHANNELS,
1623                         EEPROM_5000_REG_BAND_2_CHANNELS,
1624                         EEPROM_5000_REG_BAND_3_CHANNELS,
1625                         EEPROM_5000_REG_BAND_4_CHANNELS,
1626                         EEPROM_5000_REG_BAND_5_CHANNELS,
1627                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1628                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1629                 },
1630                 .verify_signature  = iwlcore_eeprom_verify_signature,
1631                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1632                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1633                 .calib_version  = iwl5000_eeprom_calib_version,
1634                 .query_addr = iwl5000_eeprom_query_addr,
1635         },
1636         .post_associate = iwl_post_associate,
1637         .isr = iwl_isr_ict,
1638         .config_ap = iwl_config_ap,
1639         .temp_ops = {
1640                 .temperature = iwl5150_temperature,
1641                 .set_ct_kill = iwl5150_set_ct_threshold,
1642          },
1643 };
1644
1645 static struct iwl_ops iwl5000_ops = {
1646         .ucode = &iwl5000_ucode,
1647         .lib = &iwl5000_lib,
1648         .hcmd = &iwl5000_hcmd,
1649         .utils = &iwl5000_hcmd_utils,
1650         .led = &iwlagn_led_ops,
1651 };
1652
1653 static struct iwl_ops iwl5150_ops = {
1654         .ucode = &iwl5000_ucode,
1655         .lib = &iwl5150_lib,
1656         .hcmd = &iwl5000_hcmd,
1657         .utils = &iwl5000_hcmd_utils,
1658         .led = &iwlagn_led_ops,
1659 };
1660
1661 struct iwl_mod_params iwl50_mod_params = {
1662         .num_of_queues = IWL50_NUM_QUEUES,
1663         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1664         .amsdu_size_8K = 1,
1665         .restart_fw = 1,
1666         /* the rest are 0 by default */
1667 };
1668
1669
1670 struct iwl_cfg iwl5300_agn_cfg = {
1671         .name = "5300AGN",
1672         .fw_name_pre = IWL5000_FW_PRE,
1673         .ucode_api_max = IWL5000_UCODE_API_MAX,
1674         .ucode_api_min = IWL5000_UCODE_API_MIN,
1675         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1676         .ops = &iwl5000_ops,
1677         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1678         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1679         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1680         .mod_params = &iwl50_mod_params,
1681         .valid_tx_ant = ANT_ABC,
1682         .valid_rx_ant = ANT_ABC,
1683         .need_pll_cfg = true,
1684         .ht_greenfield_support = true,
1685         .led_compensation = 51,
1686         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1687 };
1688
1689 struct iwl_cfg iwl5100_bg_cfg = {
1690         .name = "5100BG",
1691         .fw_name_pre = IWL5000_FW_PRE,
1692         .ucode_api_max = IWL5000_UCODE_API_MAX,
1693         .ucode_api_min = IWL5000_UCODE_API_MIN,
1694         .sku = IWL_SKU_G,
1695         .ops = &iwl5000_ops,
1696         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1697         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1698         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1699         .mod_params = &iwl50_mod_params,
1700         .valid_tx_ant = ANT_B,
1701         .valid_rx_ant = ANT_AB,
1702         .need_pll_cfg = true,
1703         .ht_greenfield_support = true,
1704         .led_compensation = 51,
1705         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1706 };
1707
1708 struct iwl_cfg iwl5100_abg_cfg = {
1709         .name = "5100ABG",
1710         .fw_name_pre = IWL5000_FW_PRE,
1711         .ucode_api_max = IWL5000_UCODE_API_MAX,
1712         .ucode_api_min = IWL5000_UCODE_API_MIN,
1713         .sku = IWL_SKU_A|IWL_SKU_G,
1714         .ops = &iwl5000_ops,
1715         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1716         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1717         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1718         .mod_params = &iwl50_mod_params,
1719         .valid_tx_ant = ANT_B,
1720         .valid_rx_ant = ANT_AB,
1721         .need_pll_cfg = true,
1722         .ht_greenfield_support = true,
1723         .led_compensation = 51,
1724         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1725 };
1726
1727 struct iwl_cfg iwl5100_agn_cfg = {
1728         .name = "5100AGN",
1729         .fw_name_pre = IWL5000_FW_PRE,
1730         .ucode_api_max = IWL5000_UCODE_API_MAX,
1731         .ucode_api_min = IWL5000_UCODE_API_MIN,
1732         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1733         .ops = &iwl5000_ops,
1734         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1735         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1736         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1737         .mod_params = &iwl50_mod_params,
1738         .valid_tx_ant = ANT_B,
1739         .valid_rx_ant = ANT_AB,
1740         .need_pll_cfg = true,
1741         .ht_greenfield_support = true,
1742         .led_compensation = 51,
1743         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1744 };
1745
1746 struct iwl_cfg iwl5350_agn_cfg = {
1747         .name = "5350AGN",
1748         .fw_name_pre = IWL5000_FW_PRE,
1749         .ucode_api_max = IWL5000_UCODE_API_MAX,
1750         .ucode_api_min = IWL5000_UCODE_API_MIN,
1751         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1752         .ops = &iwl5000_ops,
1753         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1754         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1755         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1756         .mod_params = &iwl50_mod_params,
1757         .valid_tx_ant = ANT_ABC,
1758         .valid_rx_ant = ANT_ABC,
1759         .need_pll_cfg = true,
1760         .ht_greenfield_support = true,
1761         .led_compensation = 51,
1762         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1763 };
1764
1765 struct iwl_cfg iwl5150_agn_cfg = {
1766         .name = "5150AGN",
1767         .fw_name_pre = IWL5150_FW_PRE,
1768         .ucode_api_max = IWL5150_UCODE_API_MAX,
1769         .ucode_api_min = IWL5150_UCODE_API_MIN,
1770         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1771         .ops = &iwl5150_ops,
1772         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1773         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1774         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1775         .mod_params = &iwl50_mod_params,
1776         .valid_tx_ant = ANT_A,
1777         .valid_rx_ant = ANT_AB,
1778         .need_pll_cfg = true,
1779         .ht_greenfield_support = true,
1780         .led_compensation = 51,
1781         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1782 };
1783
1784 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1785 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1786
1787 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1788 MODULE_PARM_DESC(swcrypto50,
1789                   "using software crypto engine (default 0 [hardware])\n");
1790 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1791 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1792 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1793 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1794 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1795                    int, S_IRUGO);
1796 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1797 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1798 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");