276f314688f72c9eaa8f87004c486fe0e815819d
[linux-2.6.git] / drivers / net / wireless / b43legacy / main.c
1 /*
2  *
3  *  Broadcom B43legacy wireless driver
4  *
5  *  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6  *  Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
7  *  Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8  *  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9  *  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10  *  Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11  *
12  *  Some parts of the code in this file are derived from the ipw2200
13  *  driver  Copyright(c) 2003 - 2004 Intel Corporation.
14
15  *  This program is free software; you can redistribute it and/or modify
16  *  it under the terms of the GNU General Public License as published by
17  *  the Free Software Foundation; either version 2 of the License, or
18  *  (at your option) any later version.
19  *
20  *  This program is distributed in the hope that it will be useful,
21  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
22  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  *  GNU General Public License for more details.
24  *
25  *  You should have received a copy of the GNU General Public License
26  *  along with this program; see the file COPYING.  If not, write to
27  *  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28  *  Boston, MA 02110-1301, USA.
29  *
30  */
31
32 #include <linux/delay.h>
33 #include <linux/init.h>
34 #include <linux/moduleparam.h>
35 #include <linux/if_arp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <net/dst.h>
43 #include <asm/unaligned.h>
44
45 #include "b43legacy.h"
46 #include "main.h"
47 #include "debugfs.h"
48 #include "phy.h"
49 #include "dma.h"
50 #include "pio.h"
51 #include "sysfs.h"
52 #include "xmit.h"
53 #include "radio.h"
54
55
56 MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
57 MODULE_AUTHOR("Martin Langer");
58 MODULE_AUTHOR("Stefano Brivio");
59 MODULE_AUTHOR("Michael Buesch");
60 MODULE_LICENSE("GPL");
61
62 MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
63
64 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
65 static int modparam_pio;
66 module_param_named(pio, modparam_pio, int, 0444);
67 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
68 #elif defined(CONFIG_B43LEGACY_DMA)
69 # define modparam_pio   0
70 #elif defined(CONFIG_B43LEGACY_PIO)
71 # define modparam_pio   1
72 #endif
73
74 static int modparam_bad_frames_preempt;
75 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
76 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
77                  " Preemption");
78
79 static char modparam_fwpostfix[16];
80 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
81 MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
82
83 /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
84 static const struct ssb_device_id b43legacy_ssb_tbl[] = {
85         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
86         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
87         SSB_DEVTABLE_END
88 };
89 MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
90
91
92 /* Channel and ratetables are shared for all devices.
93  * They can't be const, because ieee80211 puts some precalculated
94  * data in there. This data is the same for all devices, so we don't
95  * get concurrency issues */
96 #define RATETAB_ENT(_rateid, _flags) \
97         {                                                               \
98                 .bitrate        = B43legacy_RATE_TO_100KBPS(_rateid),   \
99                 .hw_value       = (_rateid),                            \
100                 .flags          = (_flags),                             \
101         }
102 /*
103  * NOTE: When changing this, sync with xmit.c's
104  *       b43legacy_plcp_get_bitrate_idx_* functions!
105  */
106 static struct ieee80211_rate __b43legacy_ratetable[] = {
107         RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
108         RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
109         RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
110         RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
111         RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
112         RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
113         RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
114         RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
115         RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
116         RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
117         RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
118         RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
119 };
120 #define b43legacy_b_ratetable           (__b43legacy_ratetable + 0)
121 #define b43legacy_b_ratetable_size      4
122 #define b43legacy_g_ratetable           (__b43legacy_ratetable + 0)
123 #define b43legacy_g_ratetable_size      12
124
125 #define CHANTAB_ENT(_chanid, _freq) \
126         {                                                       \
127                 .center_freq    = (_freq),                      \
128                 .hw_value       = (_chanid),                    \
129         }
130 static struct ieee80211_channel b43legacy_bg_chantable[] = {
131         CHANTAB_ENT(1, 2412),
132         CHANTAB_ENT(2, 2417),
133         CHANTAB_ENT(3, 2422),
134         CHANTAB_ENT(4, 2427),
135         CHANTAB_ENT(5, 2432),
136         CHANTAB_ENT(6, 2437),
137         CHANTAB_ENT(7, 2442),
138         CHANTAB_ENT(8, 2447),
139         CHANTAB_ENT(9, 2452),
140         CHANTAB_ENT(10, 2457),
141         CHANTAB_ENT(11, 2462),
142         CHANTAB_ENT(12, 2467),
143         CHANTAB_ENT(13, 2472),
144         CHANTAB_ENT(14, 2484),
145 };
146
147 static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
148         .channels = b43legacy_bg_chantable,
149         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
150         .bitrates = b43legacy_b_ratetable,
151         .n_bitrates = b43legacy_b_ratetable_size,
152 };
153
154 static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
155         .channels = b43legacy_bg_chantable,
156         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
157         .bitrates = b43legacy_g_ratetable,
158         .n_bitrates = b43legacy_g_ratetable_size,
159 };
160
161 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
162 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
163 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
164 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
165
166
167 static int b43legacy_ratelimit(struct b43legacy_wl *wl)
168 {
169         if (!wl || !wl->current_dev)
170                 return 1;
171         if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
172                 return 1;
173         /* We are up and running.
174          * Ratelimit the messages to avoid DoS over the net. */
175         return net_ratelimit();
176 }
177
178 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
179 {
180         va_list args;
181
182         if (!b43legacy_ratelimit(wl))
183                 return;
184         va_start(args, fmt);
185         printk(KERN_INFO "b43legacy-%s: ",
186                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
187         vprintk(fmt, args);
188         va_end(args);
189 }
190
191 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
192 {
193         va_list args;
194
195         if (!b43legacy_ratelimit(wl))
196                 return;
197         va_start(args, fmt);
198         printk(KERN_ERR "b43legacy-%s ERROR: ",
199                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
200         vprintk(fmt, args);
201         va_end(args);
202 }
203
204 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
205 {
206         va_list args;
207
208         if (!b43legacy_ratelimit(wl))
209                 return;
210         va_start(args, fmt);
211         printk(KERN_WARNING "b43legacy-%s warning: ",
212                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
213         vprintk(fmt, args);
214         va_end(args);
215 }
216
217 #if B43legacy_DEBUG
218 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
219 {
220         va_list args;
221
222         va_start(args, fmt);
223         printk(KERN_DEBUG "b43legacy-%s debug: ",
224                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
225         vprintk(fmt, args);
226         va_end(args);
227 }
228 #endif /* DEBUG */
229
230 static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
231                                 u32 val)
232 {
233         u32 status;
234
235         B43legacy_WARN_ON(offset % 4 != 0);
236
237         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
238         if (status & B43legacy_MACCTL_BE)
239                 val = swab32(val);
240
241         b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
242         mmiowb();
243         b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
244 }
245
246 static inline
247 void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
248                                 u16 routing, u16 offset)
249 {
250         u32 control;
251
252         /* "offset" is the WORD offset. */
253
254         control = routing;
255         control <<= 16;
256         control |= offset;
257         b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
258 }
259
260 u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
261                        u16 routing, u16 offset)
262 {
263         u32 ret;
264
265         if (routing == B43legacy_SHM_SHARED) {
266                 B43legacy_WARN_ON((offset & 0x0001) != 0);
267                 if (offset & 0x0003) {
268                         /* Unaligned access */
269                         b43legacy_shm_control_word(dev, routing, offset >> 2);
270                         ret = b43legacy_read16(dev,
271                                 B43legacy_MMIO_SHM_DATA_UNALIGNED);
272                         ret <<= 16;
273                         b43legacy_shm_control_word(dev, routing,
274                                                      (offset >> 2) + 1);
275                         ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
276
277                         return ret;
278                 }
279                 offset >>= 2;
280         }
281         b43legacy_shm_control_word(dev, routing, offset);
282         ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
283
284         return ret;
285 }
286
287 u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
288                            u16 routing, u16 offset)
289 {
290         u16 ret;
291
292         if (routing == B43legacy_SHM_SHARED) {
293                 B43legacy_WARN_ON((offset & 0x0001) != 0);
294                 if (offset & 0x0003) {
295                         /* Unaligned access */
296                         b43legacy_shm_control_word(dev, routing, offset >> 2);
297                         ret = b43legacy_read16(dev,
298                                              B43legacy_MMIO_SHM_DATA_UNALIGNED);
299
300                         return ret;
301                 }
302                 offset >>= 2;
303         }
304         b43legacy_shm_control_word(dev, routing, offset);
305         ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
306
307         return ret;
308 }
309
310 void b43legacy_shm_write32(struct b43legacy_wldev *dev,
311                            u16 routing, u16 offset,
312                            u32 value)
313 {
314         if (routing == B43legacy_SHM_SHARED) {
315                 B43legacy_WARN_ON((offset & 0x0001) != 0);
316                 if (offset & 0x0003) {
317                         /* Unaligned access */
318                         b43legacy_shm_control_word(dev, routing, offset >> 2);
319                         mmiowb();
320                         b43legacy_write16(dev,
321                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
322                                           (value >> 16) & 0xffff);
323                         mmiowb();
324                         b43legacy_shm_control_word(dev, routing,
325                                                    (offset >> 2) + 1);
326                         mmiowb();
327                         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
328                                           value & 0xffff);
329                         return;
330                 }
331                 offset >>= 2;
332         }
333         b43legacy_shm_control_word(dev, routing, offset);
334         mmiowb();
335         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
336 }
337
338 void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
339                            u16 value)
340 {
341         if (routing == B43legacy_SHM_SHARED) {
342                 B43legacy_WARN_ON((offset & 0x0001) != 0);
343                 if (offset & 0x0003) {
344                         /* Unaligned access */
345                         b43legacy_shm_control_word(dev, routing, offset >> 2);
346                         mmiowb();
347                         b43legacy_write16(dev,
348                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
349                                           value);
350                         return;
351                 }
352                 offset >>= 2;
353         }
354         b43legacy_shm_control_word(dev, routing, offset);
355         mmiowb();
356         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
357 }
358
359 /* Read HostFlags */
360 u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
361 {
362         u32 ret;
363
364         ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
365                                    B43legacy_SHM_SH_HOSTFHI);
366         ret <<= 16;
367         ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
368                                     B43legacy_SHM_SH_HOSTFLO);
369
370         return ret;
371 }
372
373 /* Write HostFlags */
374 void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
375 {
376         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
377                               B43legacy_SHM_SH_HOSTFLO,
378                               (value & 0x0000FFFF));
379         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
380                               B43legacy_SHM_SH_HOSTFHI,
381                               ((value & 0xFFFF0000) >> 16));
382 }
383
384 void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
385 {
386         /* We need to be careful. As we read the TSF from multiple
387          * registers, we should take care of register overflows.
388          * In theory, the whole tsf read process should be atomic.
389          * We try to be atomic here, by restaring the read process,
390          * if any of the high registers changed (overflew).
391          */
392         if (dev->dev->id.revision >= 3) {
393                 u32 low;
394                 u32 high;
395                 u32 high2;
396
397                 do {
398                         high = b43legacy_read32(dev,
399                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
400                         low = b43legacy_read32(dev,
401                                         B43legacy_MMIO_REV3PLUS_TSF_LOW);
402                         high2 = b43legacy_read32(dev,
403                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
404                 } while (unlikely(high != high2));
405
406                 *tsf = high;
407                 *tsf <<= 32;
408                 *tsf |= low;
409         } else {
410                 u64 tmp;
411                 u16 v0;
412                 u16 v1;
413                 u16 v2;
414                 u16 v3;
415                 u16 test1;
416                 u16 test2;
417                 u16 test3;
418
419                 do {
420                         v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
421                         v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
422                         v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
423                         v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
424
425                         test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
426                         test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
427                         test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
428                 } while (v3 != test3 || v2 != test2 || v1 != test1);
429
430                 *tsf = v3;
431                 *tsf <<= 48;
432                 tmp = v2;
433                 tmp <<= 32;
434                 *tsf |= tmp;
435                 tmp = v1;
436                 tmp <<= 16;
437                 *tsf |= tmp;
438                 *tsf |= v0;
439         }
440 }
441
442 static void b43legacy_time_lock(struct b43legacy_wldev *dev)
443 {
444         u32 status;
445
446         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
447         status |= B43legacy_MACCTL_TBTTHOLD;
448         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
449         mmiowb();
450 }
451
452 static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
453 {
454         u32 status;
455
456         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
457         status &= ~B43legacy_MACCTL_TBTTHOLD;
458         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
459 }
460
461 static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
462 {
463         /* Be careful with the in-progress timer.
464          * First zero out the low register, so we have a full
465          * register-overflow duration to complete the operation.
466          */
467         if (dev->dev->id.revision >= 3) {
468                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
469                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
470
471                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
472                 mmiowb();
473                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
474                                     hi);
475                 mmiowb();
476                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
477                                     lo);
478         } else {
479                 u16 v0 = (tsf & 0x000000000000FFFFULL);
480                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
481                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
482                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
483
484                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
485                 mmiowb();
486                 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
487                 mmiowb();
488                 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
489                 mmiowb();
490                 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
491                 mmiowb();
492                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
493         }
494 }
495
496 void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
497 {
498         b43legacy_time_lock(dev);
499         b43legacy_tsf_write_locked(dev, tsf);
500         b43legacy_time_unlock(dev);
501 }
502
503 static
504 void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
505                              u16 offset, const u8 *mac)
506 {
507         static const u8 zero_addr[ETH_ALEN] = { 0 };
508         u16 data;
509
510         if (!mac)
511                 mac = zero_addr;
512
513         offset |= 0x0020;
514         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
515
516         data = mac[0];
517         data |= mac[1] << 8;
518         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
519         data = mac[2];
520         data |= mac[3] << 8;
521         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
522         data = mac[4];
523         data |= mac[5] << 8;
524         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
525 }
526
527 static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
528 {
529         static const u8 zero_addr[ETH_ALEN] = { 0 };
530         const u8 *mac = dev->wl->mac_addr;
531         const u8 *bssid = dev->wl->bssid;
532         u8 mac_bssid[ETH_ALEN * 2];
533         int i;
534         u32 tmp;
535
536         if (!bssid)
537                 bssid = zero_addr;
538         if (!mac)
539                 mac = zero_addr;
540
541         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
542
543         memcpy(mac_bssid, mac, ETH_ALEN);
544         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
545
546         /* Write our MAC address and BSSID to template ram */
547         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
548                 tmp =  (u32)(mac_bssid[i + 0]);
549                 tmp |= (u32)(mac_bssid[i + 1]) << 8;
550                 tmp |= (u32)(mac_bssid[i + 2]) << 16;
551                 tmp |= (u32)(mac_bssid[i + 3]) << 24;
552                 b43legacy_ram_write(dev, 0x20 + i, tmp);
553                 b43legacy_ram_write(dev, 0x78 + i, tmp);
554                 b43legacy_ram_write(dev, 0x478 + i, tmp);
555         }
556 }
557
558 static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
559 {
560         b43legacy_write_mac_bssid_templates(dev);
561         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
562                                 dev->wl->mac_addr);
563 }
564
565 static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
566                                     u16 slot_time)
567 {
568         /* slot_time is in usec. */
569         if (dev->phy.type != B43legacy_PHYTYPE_G)
570                 return;
571         b43legacy_write16(dev, 0x684, 510 + slot_time);
572         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
573                               slot_time);
574 }
575
576 static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
577 {
578         b43legacy_set_slot_time(dev, 9);
579 }
580
581 static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
582 {
583         b43legacy_set_slot_time(dev, 20);
584 }
585
586 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
587  * Returns the _previously_ enabled IRQ mask.
588  */
589 static inline u32 b43legacy_interrupt_enable(struct b43legacy_wldev *dev,
590                                              u32 mask)
591 {
592         u32 old_mask;
593
594         old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
595         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask |
596                           mask);
597
598         return old_mask;
599 }
600
601 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
602  * Returns the _previously_ enabled IRQ mask.
603  */
604 static inline u32 b43legacy_interrupt_disable(struct b43legacy_wldev *dev,
605                                               u32 mask)
606 {
607         u32 old_mask;
608
609         old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
610         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
611
612         return old_mask;
613 }
614
615 /* Synchronize IRQ top- and bottom-half.
616  * IRQs must be masked before calling this.
617  * This must not be called with the irq_lock held.
618  */
619 static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
620 {
621         synchronize_irq(dev->dev->irq);
622         tasklet_kill(&dev->isr_tasklet);
623 }
624
625 /* DummyTransmission function, as documented on
626  * http://bcm-specs.sipsolutions.net/DummyTransmission
627  */
628 void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
629 {
630         struct b43legacy_phy *phy = &dev->phy;
631         unsigned int i;
632         unsigned int max_loop;
633         u16 value;
634         u32 buffer[5] = {
635                 0x00000000,
636                 0x00D40000,
637                 0x00000000,
638                 0x01000000,
639                 0x00000000,
640         };
641
642         switch (phy->type) {
643         case B43legacy_PHYTYPE_B:
644         case B43legacy_PHYTYPE_G:
645                 max_loop = 0xFA;
646                 buffer[0] = 0x000B846E;
647                 break;
648         default:
649                 B43legacy_BUG_ON(1);
650                 return;
651         }
652
653         for (i = 0; i < 5; i++)
654                 b43legacy_ram_write(dev, i * 4, buffer[i]);
655
656         /* dummy read follows */
657         b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
658
659         b43legacy_write16(dev, 0x0568, 0x0000);
660         b43legacy_write16(dev, 0x07C0, 0x0000);
661         b43legacy_write16(dev, 0x050C, 0x0000);
662         b43legacy_write16(dev, 0x0508, 0x0000);
663         b43legacy_write16(dev, 0x050A, 0x0000);
664         b43legacy_write16(dev, 0x054C, 0x0000);
665         b43legacy_write16(dev, 0x056A, 0x0014);
666         b43legacy_write16(dev, 0x0568, 0x0826);
667         b43legacy_write16(dev, 0x0500, 0x0000);
668         b43legacy_write16(dev, 0x0502, 0x0030);
669
670         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
671                 b43legacy_radio_write16(dev, 0x0051, 0x0017);
672         for (i = 0x00; i < max_loop; i++) {
673                 value = b43legacy_read16(dev, 0x050E);
674                 if (value & 0x0080)
675                         break;
676                 udelay(10);
677         }
678         for (i = 0x00; i < 0x0A; i++) {
679                 value = b43legacy_read16(dev, 0x050E);
680                 if (value & 0x0400)
681                         break;
682                 udelay(10);
683         }
684         for (i = 0x00; i < 0x0A; i++) {
685                 value = b43legacy_read16(dev, 0x0690);
686                 if (!(value & 0x0100))
687                         break;
688                 udelay(10);
689         }
690         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
691                 b43legacy_radio_write16(dev, 0x0051, 0x0037);
692 }
693
694 /* Turn the Analog ON/OFF */
695 static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
696 {
697         b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
698 }
699
700 void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
701 {
702         u32 tmslow;
703         u32 macctl;
704
705         flags |= B43legacy_TMSLOW_PHYCLKEN;
706         flags |= B43legacy_TMSLOW_PHYRESET;
707         ssb_device_enable(dev->dev, flags);
708         msleep(2); /* Wait for the PLL to turn on. */
709
710         /* Now take the PHY out of Reset again */
711         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
712         tmslow |= SSB_TMSLOW_FGC;
713         tmslow &= ~B43legacy_TMSLOW_PHYRESET;
714         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
715         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
716         msleep(1);
717         tmslow &= ~SSB_TMSLOW_FGC;
718         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
719         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
720         msleep(1);
721
722         /* Turn Analog ON */
723         b43legacy_switch_analog(dev, 1);
724
725         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
726         macctl &= ~B43legacy_MACCTL_GMODE;
727         if (flags & B43legacy_TMSLOW_GMODE) {
728                 macctl |= B43legacy_MACCTL_GMODE;
729                 dev->phy.gmode = 1;
730         } else
731                 dev->phy.gmode = 0;
732         macctl |= B43legacy_MACCTL_IHR_ENABLED;
733         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
734 }
735
736 static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
737 {
738         u32 v0;
739         u32 v1;
740         u16 tmp;
741         struct b43legacy_txstatus stat;
742
743         while (1) {
744                 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
745                 if (!(v0 & 0x00000001))
746                         break;
747                 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
748
749                 stat.cookie = (v0 >> 16);
750                 stat.seq = (v1 & 0x0000FFFF);
751                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
752                 tmp = (v0 & 0x0000FFFF);
753                 stat.frame_count = ((tmp & 0xF000) >> 12);
754                 stat.rts_count = ((tmp & 0x0F00) >> 8);
755                 stat.supp_reason = ((tmp & 0x001C) >> 2);
756                 stat.pm_indicated = !!(tmp & 0x0080);
757                 stat.intermediate = !!(tmp & 0x0040);
758                 stat.for_ampdu = !!(tmp & 0x0020);
759                 stat.acked = !!(tmp & 0x0002);
760
761                 b43legacy_handle_txstatus(dev, &stat);
762         }
763 }
764
765 static void drain_txstatus_queue(struct b43legacy_wldev *dev)
766 {
767         u32 dummy;
768
769         if (dev->dev->id.revision < 5)
770                 return;
771         /* Read all entries from the microcode TXstatus FIFO
772          * and throw them away.
773          */
774         while (1) {
775                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
776                 if (!(dummy & 0x00000001))
777                         break;
778                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
779         }
780 }
781
782 static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
783 {
784         u32 val = 0;
785
786         val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
787         val <<= 16;
788         val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
789
790         return val;
791 }
792
793 static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
794 {
795         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
796                               (jssi & 0x0000FFFF));
797         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
798                               (jssi & 0xFFFF0000) >> 16);
799 }
800
801 static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
802 {
803         b43legacy_jssi_write(dev, 0x7F7F7F7F);
804         b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
805                           b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
806                           | B43legacy_MACCMD_BGNOISE);
807         B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
808                             dev->phy.channel);
809 }
810
811 static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
812 {
813         /* Top half of Link Quality calculation. */
814
815         if (dev->noisecalc.calculation_running)
816                 return;
817         dev->noisecalc.channel_at_start = dev->phy.channel;
818         dev->noisecalc.calculation_running = 1;
819         dev->noisecalc.nr_samples = 0;
820
821         b43legacy_generate_noise_sample(dev);
822 }
823
824 static void handle_irq_noise(struct b43legacy_wldev *dev)
825 {
826         struct b43legacy_phy *phy = &dev->phy;
827         u16 tmp;
828         u8 noise[4];
829         u8 i;
830         u8 j;
831         s32 average;
832
833         /* Bottom half of Link Quality calculation. */
834
835         B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
836         if (dev->noisecalc.channel_at_start != phy->channel)
837                 goto drop_calculation;
838         *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
839         if (noise[0] == 0x7F || noise[1] == 0x7F ||
840             noise[2] == 0x7F || noise[3] == 0x7F)
841                 goto generate_new;
842
843         /* Get the noise samples. */
844         B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
845         i = dev->noisecalc.nr_samples;
846         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
847         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
848         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
849         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
850         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
851         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
852         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
853         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
854         dev->noisecalc.nr_samples++;
855         if (dev->noisecalc.nr_samples == 8) {
856                 /* Calculate the Link Quality by the noise samples. */
857                 average = 0;
858                 for (i = 0; i < 8; i++) {
859                         for (j = 0; j < 4; j++)
860                                 average += dev->noisecalc.samples[i][j];
861                 }
862                 average /= (8 * 4);
863                 average *= 125;
864                 average += 64;
865                 average /= 128;
866                 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
867                                              0x40C);
868                 tmp = (tmp / 128) & 0x1F;
869                 if (tmp >= 8)
870                         average += 2;
871                 else
872                         average -= 25;
873                 if (tmp == 8)
874                         average -= 72;
875                 else
876                         average -= 48;
877
878                 dev->stats.link_noise = average;
879 drop_calculation:
880                 dev->noisecalc.calculation_running = 0;
881                 return;
882         }
883 generate_new:
884         b43legacy_generate_noise_sample(dev);
885 }
886
887 static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
888 {
889         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
890                 /* TODO: PS TBTT */
891         } else {
892                 if (1/*FIXME: the last PSpoll frame was sent successfully */)
893                         b43legacy_power_saving_ctl_bits(dev, -1, -1);
894         }
895         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
896                 dev->dfq_valid = 1;
897 }
898
899 static void handle_irq_atim_end(struct b43legacy_wldev *dev)
900 {
901         if (dev->dfq_valid) {
902                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
903                                   b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
904                                   | B43legacy_MACCMD_DFQ_VALID);
905                 dev->dfq_valid = 0;
906         }
907 }
908
909 static void handle_irq_pmq(struct b43legacy_wldev *dev)
910 {
911         u32 tmp;
912
913         /* TODO: AP mode. */
914
915         while (1) {
916                 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
917                 if (!(tmp & 0x00000008))
918                         break;
919         }
920         /* 16bit write is odd, but correct. */
921         b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
922 }
923
924 static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
925                                             const u8 *data, u16 size,
926                                             u16 ram_offset,
927                                             u16 shm_size_offset, u8 rate)
928 {
929         u32 i;
930         u32 tmp;
931         struct b43legacy_plcp_hdr4 plcp;
932
933         plcp.data = 0;
934         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
935         b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
936         ram_offset += sizeof(u32);
937         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
938          * So leave the first two bytes of the next write blank.
939          */
940         tmp = (u32)(data[0]) << 16;
941         tmp |= (u32)(data[1]) << 24;
942         b43legacy_ram_write(dev, ram_offset, tmp);
943         ram_offset += sizeof(u32);
944         for (i = 2; i < size; i += sizeof(u32)) {
945                 tmp = (u32)(data[i + 0]);
946                 if (i + 1 < size)
947                         tmp |= (u32)(data[i + 1]) << 8;
948                 if (i + 2 < size)
949                         tmp |= (u32)(data[i + 2]) << 16;
950                 if (i + 3 < size)
951                         tmp |= (u32)(data[i + 3]) << 24;
952                 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
953         }
954         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
955                               size + sizeof(struct b43legacy_plcp_hdr6));
956 }
957
958 /* Convert a b43legacy antenna number value to the PHY TX control value. */
959 static u16 b43legacy_antenna_to_phyctl(int antenna)
960 {
961         switch (antenna) {
962         case B43legacy_ANTENNA0:
963                 return B43legacy_TX4_PHY_ANT0;
964         case B43legacy_ANTENNA1:
965                 return B43legacy_TX4_PHY_ANT1;
966         }
967         return B43legacy_TX4_PHY_ANTLAST;
968 }
969
970 static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
971                                             u16 ram_offset,
972                                             u16 shm_size_offset)
973 {
974
975         unsigned int i, len, variable_len;
976         const struct ieee80211_mgmt *bcn;
977         const u8 *ie;
978         bool tim_found = 0;
979         unsigned int rate;
980         u16 ctl;
981         int antenna;
982         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
983
984         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
985         len = min((size_t)dev->wl->current_beacon->len,
986                   0x200 - sizeof(struct b43legacy_plcp_hdr6));
987         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
988
989         b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
990                                         shm_size_offset, rate);
991
992         /* Write the PHY TX control parameters. */
993         antenna = B43legacy_ANTENNA_DEFAULT;
994         antenna = b43legacy_antenna_to_phyctl(antenna);
995         ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
996                                    B43legacy_SHM_SH_BEACPHYCTL);
997         /* We can't send beacons with short preamble. Would get PHY errors. */
998         ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
999         ctl &= ~B43legacy_TX4_PHY_ANT;
1000         ctl &= ~B43legacy_TX4_PHY_ENC;
1001         ctl |= antenna;
1002         ctl |= B43legacy_TX4_PHY_ENC_CCK;
1003         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1004                               B43legacy_SHM_SH_BEACPHYCTL, ctl);
1005
1006         /* Find the position of the TIM and the DTIM_period value
1007          * and write them to SHM. */
1008         ie = bcn->u.beacon.variable;
1009         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1010         for (i = 0; i < variable_len - 2; ) {
1011                 uint8_t ie_id, ie_len;
1012
1013                 ie_id = ie[i];
1014                 ie_len = ie[i + 1];
1015                 if (ie_id == 5) {
1016                         u16 tim_position;
1017                         u16 dtim_period;
1018                         /* This is the TIM Information Element */
1019
1020                         /* Check whether the ie_len is in the beacon data range. */
1021                         if (variable_len < ie_len + 2 + i)
1022                                 break;
1023                         /* A valid TIM is at least 4 bytes long. */
1024                         if (ie_len < 4)
1025                                 break;
1026                         tim_found = 1;
1027
1028                         tim_position = sizeof(struct b43legacy_plcp_hdr6);
1029                         tim_position += offsetof(struct ieee80211_mgmt,
1030                                                  u.beacon.variable);
1031                         tim_position += i;
1032
1033                         dtim_period = ie[i + 3];
1034
1035                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1036                                         B43legacy_SHM_SH_TIMPOS, tim_position);
1037                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1038                                         B43legacy_SHM_SH_DTIMP, dtim_period);
1039                         break;
1040                 }
1041                 i += ie_len + 2;
1042         }
1043         if (!tim_found) {
1044                 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1045                               "beacon template packet. AP or IBSS operation "
1046                               "may be broken.\n");
1047         } else
1048                 b43legacydbg(dev->wl, "Updated beacon template\n");
1049 }
1050
1051 static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1052                                             u16 shm_offset, u16 size,
1053                                             struct ieee80211_rate *rate)
1054 {
1055         struct b43legacy_plcp_hdr4 plcp;
1056         u32 tmp;
1057         __le16 dur;
1058
1059         plcp.data = 0;
1060         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1061         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1062                                                dev->wl->vif,
1063                                                size,
1064                                                rate);
1065         /* Write PLCP in two parts and timing for packet transfer */
1066         tmp = le32_to_cpu(plcp.data);
1067         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1068                               tmp & 0xFFFF);
1069         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1070                               tmp >> 16);
1071         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1072                               le16_to_cpu(dur));
1073 }
1074
1075 /* Instead of using custom probe response template, this function
1076  * just patches custom beacon template by:
1077  * 1) Changing packet type
1078  * 2) Patching duration field
1079  * 3) Stripping TIM
1080  */
1081 static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1082                                                u16 *dest_size,
1083                                                struct ieee80211_rate *rate)
1084 {
1085         const u8 *src_data;
1086         u8 *dest_data;
1087         u16 src_size, elem_size, src_pos, dest_pos;
1088         __le16 dur;
1089         struct ieee80211_hdr *hdr;
1090         size_t ie_start;
1091
1092         src_size = dev->wl->current_beacon->len;
1093         src_data = (const u8 *)dev->wl->current_beacon->data;
1094
1095         /* Get the start offset of the variable IEs in the packet. */
1096         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1097         B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1098                                                u.beacon.variable));
1099
1100         if (B43legacy_WARN_ON(src_size < ie_start))
1101                 return NULL;
1102
1103         dest_data = kmalloc(src_size, GFP_ATOMIC);
1104         if (unlikely(!dest_data))
1105                 return NULL;
1106
1107         /* Copy the static data and all Information Elements, except the TIM. */
1108         memcpy(dest_data, src_data, ie_start);
1109         src_pos = ie_start;
1110         dest_pos = ie_start;
1111         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1112                 elem_size = src_data[src_pos + 1] + 2;
1113                 if (src_data[src_pos] == 5) {
1114                         /* This is the TIM. */
1115                         continue;
1116                 }
1117                 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1118                 dest_pos += elem_size;
1119         }
1120         *dest_size = dest_pos;
1121         hdr = (struct ieee80211_hdr *)dest_data;
1122
1123         /* Set the frame control. */
1124         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1125                                          IEEE80211_STYPE_PROBE_RESP);
1126         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1127                                                dev->wl->vif,
1128                                                *dest_size,
1129                                                rate);
1130         hdr->duration_id = dur;
1131
1132         return dest_data;
1133 }
1134
1135 static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1136                                                 u16 ram_offset,
1137                                                 u16 shm_size_offset,
1138                                                 struct ieee80211_rate *rate)
1139 {
1140         const u8 *probe_resp_data;
1141         u16 size;
1142
1143         size = dev->wl->current_beacon->len;
1144         probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1145         if (unlikely(!probe_resp_data))
1146                 return;
1147
1148         /* Looks like PLCP headers plus packet timings are stored for
1149          * all possible basic rates
1150          */
1151         b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
1152                                         &b43legacy_b_ratetable[0]);
1153         b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
1154                                         &b43legacy_b_ratetable[1]);
1155         b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
1156                                         &b43legacy_b_ratetable[2]);
1157         b43legacy_write_probe_resp_plcp(dev, 0x350, size,
1158                                         &b43legacy_b_ratetable[3]);
1159
1160         size = min((size_t)size,
1161                    0x200 - sizeof(struct b43legacy_plcp_hdr6));
1162         b43legacy_write_template_common(dev, probe_resp_data,
1163                                         size, ram_offset,
1164                                         shm_size_offset, rate->hw_value);
1165         kfree(probe_resp_data);
1166 }
1167
1168 static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1169 {
1170         struct b43legacy_wl *wl = dev->wl;
1171
1172         if (wl->beacon0_uploaded)
1173                 return;
1174         b43legacy_write_beacon_template(dev, 0x68, 0x18);
1175         /* FIXME: Probe resp upload doesn't really belong here,
1176          *        but we don't use that feature anyway. */
1177         b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1178                                       &__b43legacy_ratetable[3]);
1179         wl->beacon0_uploaded = 1;
1180 }
1181
1182 static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1183 {
1184         struct b43legacy_wl *wl = dev->wl;
1185
1186         if (wl->beacon1_uploaded)
1187                 return;
1188         b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1189         wl->beacon1_uploaded = 1;
1190 }
1191
1192 static void handle_irq_beacon(struct b43legacy_wldev *dev)
1193 {
1194         struct b43legacy_wl *wl = dev->wl;
1195         u32 cmd, beacon0_valid, beacon1_valid;
1196
1197         if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1198                 return;
1199
1200         /* This is the bottom half of the asynchronous beacon update. */
1201
1202         /* Ignore interrupt in the future. */
1203         dev->irq_savedstate &= ~B43legacy_IRQ_BEACON;
1204
1205         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1206         beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1207         beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1208
1209         /* Schedule interrupt manually, if busy. */
1210         if (beacon0_valid && beacon1_valid) {
1211                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
1212                 dev->irq_savedstate |= B43legacy_IRQ_BEACON;
1213                 return;
1214         }
1215
1216         if (unlikely(wl->beacon_templates_virgin)) {
1217                 /* We never uploaded a beacon before.
1218                  * Upload both templates now, but only mark one valid. */
1219                 wl->beacon_templates_virgin = 0;
1220                 b43legacy_upload_beacon0(dev);
1221                 b43legacy_upload_beacon1(dev);
1222                 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1223                 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1224                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1225         } else {
1226                 if (!beacon0_valid) {
1227                         b43legacy_upload_beacon0(dev);
1228                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1229                         cmd |= B43legacy_MACCMD_BEACON0_VALID;
1230                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1231                 } else if (!beacon1_valid) {
1232                         b43legacy_upload_beacon1(dev);
1233                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1234                         cmd |= B43legacy_MACCMD_BEACON1_VALID;
1235                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1236                 }
1237         }
1238 }
1239
1240 static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1241 {
1242         struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1243                                          beacon_update_trigger);
1244         struct b43legacy_wldev *dev;
1245
1246         mutex_lock(&wl->mutex);
1247         dev = wl->current_dev;
1248         if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
1249                 spin_lock_irq(&wl->irq_lock);
1250                 /* update beacon right away or defer to irq */
1251                 dev->irq_savedstate = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
1252                 handle_irq_beacon(dev);
1253                 /* The handler might have updated the IRQ mask. */
1254                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1255                             dev->irq_savedstate);
1256                 mmiowb();
1257                 spin_unlock_irq(&wl->irq_lock);
1258         }
1259         mutex_unlock(&wl->mutex);
1260 }
1261
1262 /* Asynchronously update the packet templates in template RAM.
1263  * Locking: Requires wl->irq_lock to be locked. */
1264 static void b43legacy_update_templates(struct b43legacy_wl *wl)
1265 {
1266         struct sk_buff *beacon;
1267         /* This is the top half of the ansynchronous beacon update. The bottom
1268          * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1269          * sending an invalid beacon. This can happen for example, if the
1270          * firmware transmits a beacon while we are updating it. */
1271
1272         /* We could modify the existing beacon and set the aid bit in the TIM
1273          * field, but that would probably require resizing and moving of data
1274          * within the beacon template. Simply request a new beacon and let
1275          * mac80211 do the hard work. */
1276         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1277         if (unlikely(!beacon))
1278                 return;
1279
1280         if (wl->current_beacon)
1281                 dev_kfree_skb_any(wl->current_beacon);
1282         wl->current_beacon = beacon;
1283         wl->beacon0_uploaded = 0;
1284         wl->beacon1_uploaded = 0;
1285         queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1286 }
1287
1288 static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1289                                      u16 beacon_int)
1290 {
1291         b43legacy_time_lock(dev);
1292         if (dev->dev->id.revision >= 3) {
1293                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1294                                  (beacon_int << 16));
1295                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1296                                  (beacon_int << 10));
1297         } else {
1298                 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1299                 b43legacy_write16(dev, 0x610, beacon_int);
1300         }
1301         b43legacy_time_unlock(dev);
1302         b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1303 }
1304
1305 static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1306 {
1307 }
1308
1309 /* Interrupt handler bottom-half */
1310 static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1311 {
1312         u32 reason;
1313         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1314         u32 merged_dma_reason = 0;
1315         int i;
1316         unsigned long flags;
1317
1318         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1319
1320         B43legacy_WARN_ON(b43legacy_status(dev) <
1321                           B43legacy_STAT_INITIALIZED);
1322
1323         reason = dev->irq_reason;
1324         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1325                 dma_reason[i] = dev->dma_reason[i];
1326                 merged_dma_reason |= dma_reason[i];
1327         }
1328
1329         if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1330                 b43legacyerr(dev->wl, "MAC transmission error\n");
1331
1332         if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
1333                 b43legacyerr(dev->wl, "PHY transmission error\n");
1334                 rmb();
1335                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1336                         b43legacyerr(dev->wl, "Too many PHY TX errors, "
1337                                               "restarting the controller\n");
1338                         b43legacy_controller_restart(dev, "PHY TX errors");
1339                 }
1340         }
1341
1342         if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1343                                           B43legacy_DMAIRQ_NONFATALMASK))) {
1344                 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1345                         b43legacyerr(dev->wl, "Fatal DMA error: "
1346                                "0x%08X, 0x%08X, 0x%08X, "
1347                                "0x%08X, 0x%08X, 0x%08X\n",
1348                                dma_reason[0], dma_reason[1],
1349                                dma_reason[2], dma_reason[3],
1350                                dma_reason[4], dma_reason[5]);
1351                         b43legacy_controller_restart(dev, "DMA error");
1352                         mmiowb();
1353                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1354                         return;
1355                 }
1356                 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1357                         b43legacyerr(dev->wl, "DMA error: "
1358                                "0x%08X, 0x%08X, 0x%08X, "
1359                                "0x%08X, 0x%08X, 0x%08X\n",
1360                                dma_reason[0], dma_reason[1],
1361                                dma_reason[2], dma_reason[3],
1362                                dma_reason[4], dma_reason[5]);
1363         }
1364
1365         if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1366                 handle_irq_ucode_debug(dev);
1367         if (reason & B43legacy_IRQ_TBTT_INDI)
1368                 handle_irq_tbtt_indication(dev);
1369         if (reason & B43legacy_IRQ_ATIM_END)
1370                 handle_irq_atim_end(dev);
1371         if (reason & B43legacy_IRQ_BEACON)
1372                 handle_irq_beacon(dev);
1373         if (reason & B43legacy_IRQ_PMQ)
1374                 handle_irq_pmq(dev);
1375         if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1376                 ;/*TODO*/
1377         if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1378                 handle_irq_noise(dev);
1379
1380         /* Check the DMA reason registers for received data. */
1381         if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1382                 if (b43legacy_using_pio(dev))
1383                         b43legacy_pio_rx(dev->pio.queue0);
1384                 else
1385                         b43legacy_dma_rx(dev->dma.rx_ring0);
1386         }
1387         B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1388         B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1389         if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1390                 if (b43legacy_using_pio(dev))
1391                         b43legacy_pio_rx(dev->pio.queue3);
1392                 else
1393                         b43legacy_dma_rx(dev->dma.rx_ring3);
1394         }
1395         B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1396         B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1397
1398         if (reason & B43legacy_IRQ_TX_OK)
1399                 handle_irq_transmit_status(dev);
1400
1401         b43legacy_interrupt_enable(dev, dev->irq_savedstate);
1402         mmiowb();
1403         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1404 }
1405
1406 static void pio_irq_workaround(struct b43legacy_wldev *dev,
1407                                u16 base, int queueidx)
1408 {
1409         u16 rxctl;
1410
1411         rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1412         if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1413                 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1414         else
1415                 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1416 }
1417
1418 static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1419 {
1420         if (b43legacy_using_pio(dev) &&
1421             (dev->dev->id.revision < 3) &&
1422             (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1423                 /* Apply a PIO specific workaround to the dma_reasons */
1424                 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1425                 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1426                 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1427                 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1428         }
1429
1430         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1431
1432         b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1433                           dev->dma_reason[0]);
1434         b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1435                           dev->dma_reason[1]);
1436         b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1437                           dev->dma_reason[2]);
1438         b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1439                           dev->dma_reason[3]);
1440         b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1441                           dev->dma_reason[4]);
1442         b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1443                           dev->dma_reason[5]);
1444 }
1445
1446 /* Interrupt handler top-half */
1447 static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1448 {
1449         irqreturn_t ret = IRQ_NONE;
1450         struct b43legacy_wldev *dev = dev_id;
1451         u32 reason;
1452
1453         if (!dev)
1454                 return IRQ_NONE;
1455
1456         spin_lock(&dev->wl->irq_lock);
1457
1458         if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
1459                 goto out;
1460         reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1461         if (reason == 0xffffffff) /* shared IRQ */
1462                 goto out;
1463         ret = IRQ_HANDLED;
1464         reason &= b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
1465         if (!reason)
1466                 goto out;
1467
1468         dev->dma_reason[0] = b43legacy_read32(dev,
1469                                               B43legacy_MMIO_DMA0_REASON)
1470                                               & 0x0001DC00;
1471         dev->dma_reason[1] = b43legacy_read32(dev,
1472                                               B43legacy_MMIO_DMA1_REASON)
1473                                               & 0x0000DC00;
1474         dev->dma_reason[2] = b43legacy_read32(dev,
1475                                               B43legacy_MMIO_DMA2_REASON)
1476                                               & 0x0000DC00;
1477         dev->dma_reason[3] = b43legacy_read32(dev,
1478                                               B43legacy_MMIO_DMA3_REASON)
1479                                               & 0x0001DC00;
1480         dev->dma_reason[4] = b43legacy_read32(dev,
1481                                               B43legacy_MMIO_DMA4_REASON)
1482                                               & 0x0000DC00;
1483         dev->dma_reason[5] = b43legacy_read32(dev,
1484                                               B43legacy_MMIO_DMA5_REASON)
1485                                               & 0x0000DC00;
1486
1487         b43legacy_interrupt_ack(dev, reason);
1488         /* disable all IRQs. They are enabled again in the bottom half. */
1489         dev->irq_savedstate = b43legacy_interrupt_disable(dev,
1490                                                           B43legacy_IRQ_ALL);
1491         /* save the reason code and call our bottom half. */
1492         dev->irq_reason = reason;
1493         tasklet_schedule(&dev->isr_tasklet);
1494 out:
1495         mmiowb();
1496         spin_unlock(&dev->wl->irq_lock);
1497
1498         return ret;
1499 }
1500
1501 static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1502 {
1503         release_firmware(dev->fw.ucode);
1504         dev->fw.ucode = NULL;
1505         release_firmware(dev->fw.pcm);
1506         dev->fw.pcm = NULL;
1507         release_firmware(dev->fw.initvals);
1508         dev->fw.initvals = NULL;
1509         release_firmware(dev->fw.initvals_band);
1510         dev->fw.initvals_band = NULL;
1511 }
1512
1513 static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1514 {
1515         b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
1516                      "Drivers/b43#devicefirmware "
1517                      "and download the correct firmware (version 3).\n");
1518 }
1519
1520 static int do_request_fw(struct b43legacy_wldev *dev,
1521                          const char *name,
1522                          const struct firmware **fw)
1523 {
1524         char path[sizeof(modparam_fwpostfix) + 32];
1525         struct b43legacy_fw_header *hdr;
1526         u32 size;
1527         int err;
1528
1529         if (!name)
1530                 return 0;
1531
1532         snprintf(path, ARRAY_SIZE(path),
1533                  "b43legacy%s/%s.fw",
1534                  modparam_fwpostfix, name);
1535         err = request_firmware(fw, path, dev->dev->dev);
1536         if (err) {
1537                 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1538                        "or load failed.\n", path);
1539                 return err;
1540         }
1541         if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1542                 goto err_format;
1543         hdr = (struct b43legacy_fw_header *)((*fw)->data);
1544         switch (hdr->type) {
1545         case B43legacy_FW_TYPE_UCODE:
1546         case B43legacy_FW_TYPE_PCM:
1547                 size = be32_to_cpu(hdr->size);
1548                 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1549                         goto err_format;
1550                 /* fallthrough */
1551         case B43legacy_FW_TYPE_IV:
1552                 if (hdr->ver != 1)
1553                         goto err_format;
1554                 break;
1555         default:
1556                 goto err_format;
1557         }
1558
1559         return err;
1560
1561 err_format:
1562         b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1563         return -EPROTO;
1564 }
1565
1566 static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1567 {
1568         struct b43legacy_firmware *fw = &dev->fw;
1569         const u8 rev = dev->dev->id.revision;
1570         const char *filename;
1571         u32 tmshigh;
1572         int err;
1573
1574         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1575         if (!fw->ucode) {
1576                 if (rev == 2)
1577                         filename = "ucode2";
1578                 else if (rev == 4)
1579                         filename = "ucode4";
1580                 else
1581                         filename = "ucode5";
1582                 err = do_request_fw(dev, filename, &fw->ucode);
1583                 if (err)
1584                         goto err_load;
1585         }
1586         if (!fw->pcm) {
1587                 if (rev < 5)
1588                         filename = "pcm4";
1589                 else
1590                         filename = "pcm5";
1591                 err = do_request_fw(dev, filename, &fw->pcm);
1592                 if (err)
1593                         goto err_load;
1594         }
1595         if (!fw->initvals) {
1596                 switch (dev->phy.type) {
1597                 case B43legacy_PHYTYPE_B:
1598                 case B43legacy_PHYTYPE_G:
1599                         if ((rev >= 5) && (rev <= 10))
1600                                 filename = "b0g0initvals5";
1601                         else if (rev == 2 || rev == 4)
1602                                 filename = "b0g0initvals2";
1603                         else
1604                                 goto err_no_initvals;
1605                         break;
1606                 default:
1607                         goto err_no_initvals;
1608                 }
1609                 err = do_request_fw(dev, filename, &fw->initvals);
1610                 if (err)
1611                         goto err_load;
1612         }
1613         if (!fw->initvals_band) {
1614                 switch (dev->phy.type) {
1615                 case B43legacy_PHYTYPE_B:
1616                 case B43legacy_PHYTYPE_G:
1617                         if ((rev >= 5) && (rev <= 10))
1618                                 filename = "b0g0bsinitvals5";
1619                         else if (rev >= 11)
1620                                 filename = NULL;
1621                         else if (rev == 2 || rev == 4)
1622                                 filename = NULL;
1623                         else
1624                                 goto err_no_initvals;
1625                         break;
1626                 default:
1627                         goto err_no_initvals;
1628                 }
1629                 err = do_request_fw(dev, filename, &fw->initvals_band);
1630                 if (err)
1631                         goto err_load;
1632         }
1633
1634         return 0;
1635
1636 err_load:
1637         b43legacy_print_fw_helptext(dev->wl);
1638         goto error;
1639
1640 err_no_initvals:
1641         err = -ENODEV;
1642         b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1643                "core rev %u\n", dev->phy.type, rev);
1644         goto error;
1645
1646 error:
1647         b43legacy_release_firmware(dev);
1648         return err;
1649 }
1650
1651 static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1652 {
1653         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1654         const __be32 *data;
1655         unsigned int i;
1656         unsigned int len;
1657         u16 fwrev;
1658         u16 fwpatch;
1659         u16 fwdate;
1660         u16 fwtime;
1661         u32 tmp, macctl;
1662         int err = 0;
1663
1664         /* Jump the microcode PSM to offset 0 */
1665         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1666         B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1667         macctl |= B43legacy_MACCTL_PSM_JMP0;
1668         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1669         /* Zero out all microcode PSM registers and shared memory. */
1670         for (i = 0; i < 64; i++)
1671                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1672         for (i = 0; i < 4096; i += 2)
1673                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1674
1675         /* Upload Microcode. */
1676         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1677         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1678         b43legacy_shm_control_word(dev,
1679                                    B43legacy_SHM_UCODE |
1680                                    B43legacy_SHM_AUTOINC_W,
1681                                    0x0000);
1682         for (i = 0; i < len; i++) {
1683                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1684                                     be32_to_cpu(data[i]));
1685                 udelay(10);
1686         }
1687
1688         if (dev->fw.pcm) {
1689                 /* Upload PCM data. */
1690                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1691                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1692                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1693                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1694                 /* No need for autoinc bit in SHM_HW */
1695                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1696                 for (i = 0; i < len; i++) {
1697                         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1698                                           be32_to_cpu(data[i]));
1699                         udelay(10);
1700                 }
1701         }
1702
1703         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1704                           B43legacy_IRQ_ALL);
1705
1706         /* Start the microcode PSM */
1707         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1708         macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1709         macctl |= B43legacy_MACCTL_PSM_RUN;
1710         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1711
1712         /* Wait for the microcode to load and respond */
1713         i = 0;
1714         while (1) {
1715                 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1716                 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1717                         break;
1718                 i++;
1719                 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1720                         b43legacyerr(dev->wl, "Microcode not responding\n");
1721                         b43legacy_print_fw_helptext(dev->wl);
1722                         err = -ENODEV;
1723                         goto error;
1724                 }
1725                 msleep_interruptible(50);
1726                 if (signal_pending(current)) {
1727                         err = -EINTR;
1728                         goto error;
1729                 }
1730         }
1731         /* dummy read follows */
1732         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1733
1734         /* Get and check the revisions. */
1735         fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1736                                      B43legacy_SHM_SH_UCODEREV);
1737         fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1738                                        B43legacy_SHM_SH_UCODEPATCH);
1739         fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1740                                       B43legacy_SHM_SH_UCODEDATE);
1741         fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1742                                       B43legacy_SHM_SH_UCODETIME);
1743
1744         if (fwrev > 0x128) {
1745                 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1746                              " Only firmware from binary drivers version 3.x"
1747                              " is supported. You must change your firmware"
1748                              " files.\n");
1749                 b43legacy_print_fw_helptext(dev->wl);
1750                 err = -EOPNOTSUPP;
1751                 goto error;
1752         }
1753         b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1754                       "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1755                       (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1756                       (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1757                       fwtime & 0x1F);
1758
1759         dev->fw.rev = fwrev;
1760         dev->fw.patch = fwpatch;
1761
1762         return 0;
1763
1764 error:
1765         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1766         macctl &= ~B43legacy_MACCTL_PSM_RUN;
1767         macctl |= B43legacy_MACCTL_PSM_JMP0;
1768         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1769
1770         return err;
1771 }
1772
1773 static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1774                                     const struct b43legacy_iv *ivals,
1775                                     size_t count,
1776                                     size_t array_size)
1777 {
1778         const struct b43legacy_iv *iv;
1779         u16 offset;
1780         size_t i;
1781         bool bit32;
1782
1783         BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1784         iv = ivals;
1785         for (i = 0; i < count; i++) {
1786                 if (array_size < sizeof(iv->offset_size))
1787                         goto err_format;
1788                 array_size -= sizeof(iv->offset_size);
1789                 offset = be16_to_cpu(iv->offset_size);
1790                 bit32 = !!(offset & B43legacy_IV_32BIT);
1791                 offset &= B43legacy_IV_OFFSET_MASK;
1792                 if (offset >= 0x1000)
1793                         goto err_format;
1794                 if (bit32) {
1795                         u32 value;
1796
1797                         if (array_size < sizeof(iv->data.d32))
1798                                 goto err_format;
1799                         array_size -= sizeof(iv->data.d32);
1800
1801                         value = get_unaligned_be32(&iv->data.d32);
1802                         b43legacy_write32(dev, offset, value);
1803
1804                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1805                                                         sizeof(__be16) +
1806                                                         sizeof(__be32));
1807                 } else {
1808                         u16 value;
1809
1810                         if (array_size < sizeof(iv->data.d16))
1811                                 goto err_format;
1812                         array_size -= sizeof(iv->data.d16);
1813
1814                         value = be16_to_cpu(iv->data.d16);
1815                         b43legacy_write16(dev, offset, value);
1816
1817                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1818                                                         sizeof(__be16) +
1819                                                         sizeof(__be16));
1820                 }
1821         }
1822         if (array_size)
1823                 goto err_format;
1824
1825         return 0;
1826
1827 err_format:
1828         b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1829         b43legacy_print_fw_helptext(dev->wl);
1830
1831         return -EPROTO;
1832 }
1833
1834 static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1835 {
1836         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1837         const struct b43legacy_fw_header *hdr;
1838         struct b43legacy_firmware *fw = &dev->fw;
1839         const struct b43legacy_iv *ivals;
1840         size_t count;
1841         int err;
1842
1843         hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1844         ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1845         count = be32_to_cpu(hdr->size);
1846         err = b43legacy_write_initvals(dev, ivals, count,
1847                                  fw->initvals->size - hdr_len);
1848         if (err)
1849                 goto out;
1850         if (fw->initvals_band) {
1851                 hdr = (const struct b43legacy_fw_header *)
1852                       (fw->initvals_band->data);
1853                 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1854                         + hdr_len);
1855                 count = be32_to_cpu(hdr->size);
1856                 err = b43legacy_write_initvals(dev, ivals, count,
1857                                          fw->initvals_band->size - hdr_len);
1858                 if (err)
1859                         goto out;
1860         }
1861 out:
1862
1863         return err;
1864 }
1865
1866 /* Initialize the GPIOs
1867  * http://bcm-specs.sipsolutions.net/GPIO
1868  */
1869 static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1870 {
1871         struct ssb_bus *bus = dev->dev->bus;
1872         struct ssb_device *gpiodev, *pcidev = NULL;
1873         u32 mask;
1874         u32 set;
1875
1876         b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1877                           b43legacy_read32(dev,
1878                           B43legacy_MMIO_MACCTL)
1879                           & 0xFFFF3FFF);
1880
1881         b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1882                           b43legacy_read16(dev,
1883                           B43legacy_MMIO_GPIO_MASK)
1884                           | 0x000F);
1885
1886         mask = 0x0000001F;
1887         set = 0x0000000F;
1888         if (dev->dev->bus->chip_id == 0x4301) {
1889                 mask |= 0x0060;
1890                 set |= 0x0060;
1891         }
1892         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
1893                 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1894                                   b43legacy_read16(dev,
1895                                   B43legacy_MMIO_GPIO_MASK)
1896                                   | 0x0200);
1897                 mask |= 0x0200;
1898                 set |= 0x0200;
1899         }
1900         if (dev->dev->id.revision >= 2)
1901                 mask  |= 0x0010; /* FIXME: This is redundant. */
1902
1903 #ifdef CONFIG_SSB_DRIVER_PCICORE
1904         pcidev = bus->pcicore.dev;
1905 #endif
1906         gpiodev = bus->chipco.dev ? : pcidev;
1907         if (!gpiodev)
1908                 return 0;
1909         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1910                     (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1911                      & mask) | set);
1912
1913         return 0;
1914 }
1915
1916 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1917 static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1918 {
1919         struct ssb_bus *bus = dev->dev->bus;
1920         struct ssb_device *gpiodev, *pcidev = NULL;
1921
1922 #ifdef CONFIG_SSB_DRIVER_PCICORE
1923         pcidev = bus->pcicore.dev;
1924 #endif
1925         gpiodev = bus->chipco.dev ? : pcidev;
1926         if (!gpiodev)
1927                 return;
1928         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1929 }
1930
1931 /* http://bcm-specs.sipsolutions.net/EnableMac */
1932 void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1933 {
1934         dev->mac_suspended--;
1935         B43legacy_WARN_ON(dev->mac_suspended < 0);
1936         B43legacy_WARN_ON(irqs_disabled());
1937         if (dev->mac_suspended == 0) {
1938                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1939                                   b43legacy_read32(dev,
1940                                   B43legacy_MMIO_MACCTL)
1941                                   | B43legacy_MACCTL_ENABLED);
1942                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1943                                   B43legacy_IRQ_MAC_SUSPENDED);
1944                 /* the next two are dummy reads */
1945                 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1946                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1947                 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1948
1949                 /* Re-enable IRQs. */
1950                 spin_lock_irq(&dev->wl->irq_lock);
1951                 b43legacy_interrupt_enable(dev, dev->irq_savedstate);
1952                 spin_unlock_irq(&dev->wl->irq_lock);
1953         }
1954 }
1955
1956 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1957 void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1958 {
1959         int i;
1960         u32 tmp;
1961
1962         might_sleep();
1963         B43legacy_WARN_ON(irqs_disabled());
1964         B43legacy_WARN_ON(dev->mac_suspended < 0);
1965
1966         if (dev->mac_suspended == 0) {
1967                 /* Mask IRQs before suspending MAC. Otherwise
1968                  * the MAC stays busy and won't suspend. */
1969                 spin_lock_irq(&dev->wl->irq_lock);
1970                 tmp = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
1971                 spin_unlock_irq(&dev->wl->irq_lock);
1972                 b43legacy_synchronize_irq(dev);
1973                 dev->irq_savedstate = tmp;
1974
1975                 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1976                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1977                                   b43legacy_read32(dev,
1978                                   B43legacy_MMIO_MACCTL)
1979                                   & ~B43legacy_MACCTL_ENABLED);
1980                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1981                 for (i = 40; i; i--) {
1982                         tmp = b43legacy_read32(dev,
1983                                                B43legacy_MMIO_GEN_IRQ_REASON);
1984                         if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1985                                 goto out;
1986                         msleep(1);
1987                 }
1988                 b43legacyerr(dev->wl, "MAC suspend failed\n");
1989         }
1990 out:
1991         dev->mac_suspended++;
1992 }
1993
1994 static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1995 {
1996         struct b43legacy_wl *wl = dev->wl;
1997         u32 ctl;
1998         u16 cfp_pretbtt;
1999
2000         ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2001         /* Reset status to STA infrastructure mode. */
2002         ctl &= ~B43legacy_MACCTL_AP;
2003         ctl &= ~B43legacy_MACCTL_KEEP_CTL;
2004         ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
2005         ctl &= ~B43legacy_MACCTL_KEEP_BAD;
2006         ctl &= ~B43legacy_MACCTL_PROMISC;
2007         ctl &= ~B43legacy_MACCTL_BEACPROMISC;
2008         ctl |= B43legacy_MACCTL_INFRA;
2009
2010         if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
2011                 ctl |= B43legacy_MACCTL_AP;
2012         else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
2013                 ctl &= ~B43legacy_MACCTL_INFRA;
2014
2015         if (wl->filter_flags & FIF_CONTROL)
2016                 ctl |= B43legacy_MACCTL_KEEP_CTL;
2017         if (wl->filter_flags & FIF_FCSFAIL)
2018                 ctl |= B43legacy_MACCTL_KEEP_BAD;
2019         if (wl->filter_flags & FIF_PLCPFAIL)
2020                 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
2021         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2022                 ctl |= B43legacy_MACCTL_PROMISC;
2023         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2024                 ctl |= B43legacy_MACCTL_BEACPROMISC;
2025
2026         /* Workaround: On old hardware the HW-MAC-address-filter
2027          * doesn't work properly, so always run promisc in filter
2028          * it in software. */
2029         if (dev->dev->id.revision <= 4)
2030                 ctl |= B43legacy_MACCTL_PROMISC;
2031
2032         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2033
2034         cfp_pretbtt = 2;
2035         if ((ctl & B43legacy_MACCTL_INFRA) &&
2036             !(ctl & B43legacy_MACCTL_AP)) {
2037                 if (dev->dev->bus->chip_id == 0x4306 &&
2038                     dev->dev->bus->chip_rev == 3)
2039                         cfp_pretbtt = 100;
2040                 else
2041                         cfp_pretbtt = 50;
2042         }
2043         b43legacy_write16(dev, 0x612, cfp_pretbtt);
2044 }
2045
2046 static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2047                                         u16 rate,
2048                                         int is_ofdm)
2049 {
2050         u16 offset;
2051
2052         if (is_ofdm) {
2053                 offset = 0x480;
2054                 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2055         } else {
2056                 offset = 0x4C0;
2057                 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2058         }
2059         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2060                               b43legacy_shm_read16(dev,
2061                               B43legacy_SHM_SHARED, offset));
2062 }
2063
2064 static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2065 {
2066         switch (dev->phy.type) {
2067         case B43legacy_PHYTYPE_G:
2068                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2069                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2070                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2071                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2072                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2073                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2074                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2075                 /* fallthrough */
2076         case B43legacy_PHYTYPE_B:
2077                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2078                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2079                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2080                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2081                 break;
2082         default:
2083                 B43legacy_BUG_ON(1);
2084         }
2085 }
2086
2087 /* Set the TX-Antenna for management frames sent by firmware. */
2088 static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2089                                           int antenna)
2090 {
2091         u16 ant = 0;
2092         u16 tmp;
2093
2094         switch (antenna) {
2095         case B43legacy_ANTENNA0:
2096                 ant |= B43legacy_TX4_PHY_ANT0;
2097                 break;
2098         case B43legacy_ANTENNA1:
2099                 ant |= B43legacy_TX4_PHY_ANT1;
2100                 break;
2101         case B43legacy_ANTENNA_AUTO:
2102                 ant |= B43legacy_TX4_PHY_ANTLAST;
2103                 break;
2104         default:
2105                 B43legacy_BUG_ON(1);
2106         }
2107
2108         /* FIXME We also need to set the other flags of the PHY control
2109          * field somewhere. */
2110
2111         /* For Beacons */
2112         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2113                                    B43legacy_SHM_SH_BEACPHYCTL);
2114         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2115         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2116                               B43legacy_SHM_SH_BEACPHYCTL, tmp);
2117         /* For ACK/CTS */
2118         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2119                                    B43legacy_SHM_SH_ACKCTSPHYCTL);
2120         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2121         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2122                               B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2123         /* For Probe Resposes */
2124         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2125                                    B43legacy_SHM_SH_PRPHYCTL);
2126         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2127         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2128                               B43legacy_SHM_SH_PRPHYCTL, tmp);
2129 }
2130
2131 /* This is the opposite of b43legacy_chip_init() */
2132 static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2133 {
2134         b43legacy_radio_turn_off(dev, 1);
2135         b43legacy_gpio_cleanup(dev);
2136         /* firmware is released later */
2137 }
2138
2139 /* Initialize the chip
2140  * http://bcm-specs.sipsolutions.net/ChipInit
2141  */
2142 static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2143 {
2144         struct b43legacy_phy *phy = &dev->phy;
2145         int err;
2146         int tmp;
2147         u32 value32, macctl;
2148         u16 value16;
2149
2150         /* Initialize the MAC control */
2151         macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2152         if (dev->phy.gmode)
2153                 macctl |= B43legacy_MACCTL_GMODE;
2154         macctl |= B43legacy_MACCTL_INFRA;
2155         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
2156
2157         err = b43legacy_request_firmware(dev);
2158         if (err)
2159                 goto out;
2160         err = b43legacy_upload_microcode(dev);
2161         if (err)
2162                 goto out; /* firmware is released later */
2163
2164         err = b43legacy_gpio_init(dev);
2165         if (err)
2166                 goto out; /* firmware is released later */
2167
2168         err = b43legacy_upload_initvals(dev);
2169         if (err)
2170                 goto err_gpio_clean;
2171         b43legacy_radio_turn_on(dev);
2172
2173         b43legacy_write16(dev, 0x03E6, 0x0000);
2174         err = b43legacy_phy_init(dev);
2175         if (err)
2176                 goto err_radio_off;
2177
2178         /* Select initial Interference Mitigation. */
2179         tmp = phy->interfmode;
2180         phy->interfmode = B43legacy_INTERFMODE_NONE;
2181         b43legacy_radio_set_interference_mitigation(dev, tmp);
2182
2183         b43legacy_phy_set_antenna_diversity(dev);
2184         b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2185
2186         if (phy->type == B43legacy_PHYTYPE_B) {
2187                 value16 = b43legacy_read16(dev, 0x005E);
2188                 value16 |= 0x0004;
2189                 b43legacy_write16(dev, 0x005E, value16);
2190         }
2191         b43legacy_write32(dev, 0x0100, 0x01000000);
2192         if (dev->dev->id.revision < 5)
2193                 b43legacy_write32(dev, 0x010C, 0x01000000);
2194
2195         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2196         value32 &= ~B43legacy_MACCTL_INFRA;
2197         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2198         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2199         value32 |= B43legacy_MACCTL_INFRA;
2200         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2201
2202         if (b43legacy_using_pio(dev)) {
2203                 b43legacy_write32(dev, 0x0210, 0x00000100);
2204                 b43legacy_write32(dev, 0x0230, 0x00000100);
2205                 b43legacy_write32(dev, 0x0250, 0x00000100);
2206                 b43legacy_write32(dev, 0x0270, 0x00000100);
2207                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2208                                       0x0000);
2209         }
2210
2211         /* Probe Response Timeout value */
2212         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2213         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2214
2215         /* Initially set the wireless operation mode. */
2216         b43legacy_adjust_opmode(dev);
2217
2218         if (dev->dev->id.revision < 3) {
2219                 b43legacy_write16(dev, 0x060E, 0x0000);
2220                 b43legacy_write16(dev, 0x0610, 0x8000);
2221                 b43legacy_write16(dev, 0x0604, 0x0000);
2222                 b43legacy_write16(dev, 0x0606, 0x0200);
2223         } else {
2224                 b43legacy_write32(dev, 0x0188, 0x80000000);
2225                 b43legacy_write32(dev, 0x018C, 0x02000000);
2226         }
2227         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2228         b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2229         b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2230         b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2231         b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2232         b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2233         b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2234
2235         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2236         value32 |= 0x00100000;
2237         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2238
2239         b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2240                           dev->dev->bus->chipco.fast_pwrup_delay);
2241
2242         /* PHY TX errors counter. */
2243         atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2244
2245         B43legacy_WARN_ON(err != 0);
2246         b43legacydbg(dev->wl, "Chip initialized\n");
2247 out:
2248         return err;
2249
2250 err_radio_off:
2251         b43legacy_radio_turn_off(dev, 1);
2252 err_gpio_clean:
2253         b43legacy_gpio_cleanup(dev);
2254         goto out;
2255 }
2256
2257 static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2258 {
2259         struct b43legacy_phy *phy = &dev->phy;
2260
2261         if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2262                 return;
2263
2264         b43legacy_mac_suspend(dev);
2265         b43legacy_phy_lo_g_measure(dev);
2266         b43legacy_mac_enable(dev);
2267 }
2268
2269 static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2270 {
2271         b43legacy_phy_lo_mark_all_unused(dev);
2272         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
2273                 b43legacy_mac_suspend(dev);
2274                 b43legacy_calc_nrssi_slope(dev);
2275                 b43legacy_mac_enable(dev);
2276         }
2277 }
2278
2279 static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2280 {
2281         /* Update device statistics. */
2282         b43legacy_calculate_link_quality(dev);
2283 }
2284
2285 static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2286 {
2287         b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
2288
2289         atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2290         wmb();
2291 }
2292
2293 static void do_periodic_work(struct b43legacy_wldev *dev)
2294 {
2295         unsigned int state;
2296
2297         state = dev->periodic_state;
2298         if (state % 8 == 0)
2299                 b43legacy_periodic_every120sec(dev);
2300         if (state % 4 == 0)
2301                 b43legacy_periodic_every60sec(dev);
2302         if (state % 2 == 0)
2303                 b43legacy_periodic_every30sec(dev);
2304         b43legacy_periodic_every15sec(dev);
2305 }
2306
2307 /* Periodic work locking policy:
2308  *      The whole periodic work handler is protected by
2309  *      wl->mutex. If another lock is needed somewhere in the
2310  *      pwork callchain, it's aquired in-place, where it's needed.
2311  */
2312 static void b43legacy_periodic_work_handler(struct work_struct *work)
2313 {
2314         struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2315                                              periodic_work.work);
2316         struct b43legacy_wl *wl = dev->wl;
2317         unsigned long delay;
2318
2319         mutex_lock(&wl->mutex);
2320
2321         if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2322                 goto out;
2323         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2324                 goto out_requeue;
2325
2326         do_periodic_work(dev);
2327
2328         dev->periodic_state++;
2329 out_requeue:
2330         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2331                 delay = msecs_to_jiffies(50);
2332         else
2333                 delay = round_jiffies_relative(HZ * 15);
2334         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2335 out:
2336         mutex_unlock(&wl->mutex);
2337 }
2338
2339 static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2340 {
2341         struct delayed_work *work = &dev->periodic_work;
2342
2343         dev->periodic_state = 0;
2344         INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2345         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2346 }
2347
2348 /* Validate access to the chip (SHM) */
2349 static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2350 {
2351         u32 value;
2352         u32 shm_backup;
2353
2354         shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2355         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2356         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2357                                  0xAA5555AA)
2358                 goto error;
2359         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2360         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2361                                  0x55AAAA55)
2362                 goto error;
2363         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2364
2365         value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2366         if ((value | B43legacy_MACCTL_GMODE) !=
2367             (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2368                 goto error;
2369
2370         value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2371         if (value)
2372                 goto error;
2373
2374         return 0;
2375 error:
2376         b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2377         return -ENODEV;
2378 }
2379
2380 static void b43legacy_security_init(struct b43legacy_wldev *dev)
2381 {
2382         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2383         B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2384         dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2385                                         0x0056);
2386         /* KTP is a word address, but we address SHM bytewise.
2387          * So multiply by two.
2388          */
2389         dev->ktp *= 2;
2390         if (dev->dev->id.revision >= 5)
2391                 /* Number of RCMTA address slots */
2392                 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2393                                   dev->max_nr_keys - 8);
2394 }
2395
2396 #ifdef CONFIG_B43LEGACY_HWRNG
2397 static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2398 {
2399         struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2400         unsigned long flags;
2401
2402         /* Don't take wl->mutex here, as it could deadlock with
2403          * hwrng internal locking. It's not needed to take
2404          * wl->mutex here, anyway. */
2405
2406         spin_lock_irqsave(&wl->irq_lock, flags);
2407         *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2408         spin_unlock_irqrestore(&wl->irq_lock, flags);
2409
2410         return (sizeof(u16));
2411 }
2412 #endif
2413
2414 static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2415 {
2416 #ifdef CONFIG_B43LEGACY_HWRNG
2417         if (wl->rng_initialized)
2418                 hwrng_unregister(&wl->rng);
2419 #endif
2420 }
2421
2422 static int b43legacy_rng_init(struct b43legacy_wl *wl)
2423 {
2424         int err = 0;
2425
2426 #ifdef CONFIG_B43LEGACY_HWRNG
2427         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2428                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2429         wl->rng.name = wl->rng_name;
2430         wl->rng.data_read = b43legacy_rng_read;
2431         wl->rng.priv = (unsigned long)wl;
2432         wl->rng_initialized = 1;
2433         err = hwrng_register(&wl->rng);
2434         if (err) {
2435                 wl->rng_initialized = 0;
2436                 b43legacyerr(wl, "Failed to register the random "
2437                        "number generator (%d)\n", err);
2438         }
2439
2440 #endif
2441         return err;
2442 }
2443
2444 static int b43legacy_op_tx(struct ieee80211_hw *hw,
2445                            struct sk_buff *skb)
2446 {
2447         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2448         struct b43legacy_wldev *dev = wl->current_dev;
2449         int err = -ENODEV;
2450         unsigned long flags;
2451
2452         if (unlikely(!dev))
2453                 goto out;
2454         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2455                 goto out;
2456         /* DMA-TX is done without a global lock. */
2457         if (b43legacy_using_pio(dev)) {
2458                 spin_lock_irqsave(&wl->irq_lock, flags);
2459                 err = b43legacy_pio_tx(dev, skb);
2460                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2461         } else
2462                 err = b43legacy_dma_tx(dev, skb);
2463 out:
2464         if (unlikely(err)) {
2465                 /* Drop the packet. */
2466                 dev_kfree_skb_any(skb);
2467         }
2468         return NETDEV_TX_OK;
2469 }
2470
2471 static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
2472                                 const struct ieee80211_tx_queue_params *params)
2473 {
2474         return 0;
2475 }
2476
2477 static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
2478                                      struct ieee80211_tx_queue_stats *stats)
2479 {
2480         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2481         struct b43legacy_wldev *dev = wl->current_dev;
2482         unsigned long flags;
2483         int err = -ENODEV;
2484
2485         if (!dev)
2486                 goto out;
2487         spin_lock_irqsave(&wl->irq_lock, flags);
2488         if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
2489                 if (b43legacy_using_pio(dev))
2490                         b43legacy_pio_get_tx_stats(dev, stats);
2491                 else
2492                         b43legacy_dma_get_tx_stats(dev, stats);
2493                 err = 0;
2494         }
2495         spin_unlock_irqrestore(&wl->irq_lock, flags);
2496 out:
2497         return err;
2498 }
2499
2500 static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2501                                   struct ieee80211_low_level_stats *stats)
2502 {
2503         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2504         unsigned long flags;
2505
2506         spin_lock_irqsave(&wl->irq_lock, flags);
2507         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2508         spin_unlock_irqrestore(&wl->irq_lock, flags);
2509
2510         return 0;
2511 }
2512
2513 static const char *phymode_to_string(unsigned int phymode)
2514 {
2515         switch (phymode) {
2516         case B43legacy_PHYMODE_B:
2517                 return "B";
2518         case B43legacy_PHYMODE_G:
2519                 return "G";
2520         default:
2521                 B43legacy_BUG_ON(1);
2522         }
2523         return "";
2524 }
2525
2526 static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2527                                   unsigned int phymode,
2528                                   struct b43legacy_wldev **dev,
2529                                   bool *gmode)
2530 {
2531         struct b43legacy_wldev *d;
2532
2533         list_for_each_entry(d, &wl->devlist, list) {
2534                 if (d->phy.possible_phymodes & phymode) {
2535                         /* Ok, this device supports the PHY-mode.
2536                          * Set the gmode bit. */
2537                         *gmode = 1;
2538                         *dev = d;
2539
2540                         return 0;
2541                 }
2542         }
2543
2544         return -ESRCH;
2545 }
2546
2547 static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2548 {
2549         struct ssb_device *sdev = dev->dev;
2550         u32 tmslow;
2551
2552         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2553         tmslow &= ~B43legacy_TMSLOW_GMODE;
2554         tmslow |= B43legacy_TMSLOW_PHYRESET;
2555         tmslow |= SSB_TMSLOW_FGC;
2556         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2557         msleep(1);
2558
2559         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2560         tmslow &= ~SSB_TMSLOW_FGC;
2561         tmslow |= B43legacy_TMSLOW_PHYRESET;
2562         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2563         msleep(1);
2564 }
2565
2566 /* Expects wl->mutex locked */
2567 static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2568                                       unsigned int new_mode)
2569 {
2570         struct b43legacy_wldev *uninitialized_var(up_dev);
2571         struct b43legacy_wldev *down_dev;
2572         int err;
2573         bool gmode = 0;
2574         int prev_status;
2575
2576         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2577         if (err) {
2578                 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2579                        phymode_to_string(new_mode));
2580                 return err;
2581         }
2582         if ((up_dev == wl->current_dev) &&
2583             (!!wl->current_dev->phy.gmode == !!gmode))
2584                 /* This device is already running. */
2585                 return 0;
2586         b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2587                phymode_to_string(new_mode));
2588         down_dev = wl->current_dev;
2589
2590         prev_status = b43legacy_status(down_dev);
2591         /* Shutdown the currently running core. */
2592         if (prev_status >= B43legacy_STAT_STARTED)
2593                 b43legacy_wireless_core_stop(down_dev);
2594         if (prev_status >= B43legacy_STAT_INITIALIZED)
2595                 b43legacy_wireless_core_exit(down_dev);
2596
2597         if (down_dev != up_dev)
2598                 /* We switch to a different core, so we put PHY into
2599                  * RESET on the old core. */
2600                 b43legacy_put_phy_into_reset(down_dev);
2601
2602         /* Now start the new core. */
2603         up_dev->phy.gmode = gmode;
2604         if (prev_status >= B43legacy_STAT_INITIALIZED) {
2605                 err = b43legacy_wireless_core_init(up_dev);
2606                 if (err) {
2607                         b43legacyerr(wl, "Fatal: Could not initialize device"
2608                                      " for newly selected %s-PHY mode\n",
2609                                      phymode_to_string(new_mode));
2610                         goto init_failure;
2611                 }
2612         }
2613         if (prev_status >= B43legacy_STAT_STARTED) {
2614                 err = b43legacy_wireless_core_start(up_dev);
2615                 if (err) {
2616                         b43legacyerr(wl, "Fatal: Coult not start device for "
2617                                "newly selected %s-PHY mode\n",
2618                                phymode_to_string(new_mode));
2619                         b43legacy_wireless_core_exit(up_dev);
2620                         goto init_failure;
2621                 }
2622         }
2623         B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2624
2625         b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2626
2627         wl->current_dev = up_dev;
2628
2629         return 0;
2630 init_failure:
2631         /* Whoops, failed to init the new core. No core is operating now. */
2632         wl->current_dev = NULL;
2633         return err;
2634 }
2635
2636 /* Write the short and long frame retry limit values. */
2637 static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2638                                        unsigned int short_retry,
2639                                        unsigned int long_retry)
2640 {
2641         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2642          * the chip-internal counter. */
2643         short_retry = min(short_retry, (unsigned int)0xF);
2644         long_retry = min(long_retry, (unsigned int)0xF);
2645
2646         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2647         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2648 }
2649
2650 static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2651                                    u32 changed)
2652 {
2653         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2654         struct b43legacy_wldev *dev;
2655         struct b43legacy_phy *phy;
2656         struct ieee80211_conf *conf = &hw->conf;
2657         unsigned long flags;
2658         unsigned int new_phymode = 0xFFFF;
2659         int antenna_tx;
2660         int antenna_rx;
2661         int err = 0;
2662         u32 savedirqs;
2663
2664         antenna_tx = B43legacy_ANTENNA_DEFAULT;
2665         antenna_rx = B43legacy_ANTENNA_DEFAULT;
2666
2667         mutex_lock(&wl->mutex);
2668         dev = wl->current_dev;
2669         phy = &dev->phy;
2670
2671         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2672                 b43legacy_set_retry_limits(dev,
2673                                            conf->short_frame_max_tx_count,
2674                                            conf->long_frame_max_tx_count);
2675         changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2676         if (!changed)
2677                 goto out_unlock_mutex;
2678
2679         /* Switch the PHY mode (if necessary). */
2680         switch (conf->channel->band) {
2681         case IEEE80211_BAND_2GHZ:
2682                 if (phy->type == B43legacy_PHYTYPE_B)
2683                         new_phymode = B43legacy_PHYMODE_B;
2684                 else
2685                         new_phymode = B43legacy_PHYMODE_G;
2686                 break;
2687         default:
2688                 B43legacy_WARN_ON(1);
2689         }
2690         err = b43legacy_switch_phymode(wl, new_phymode);
2691         if (err)
2692                 goto out_unlock_mutex;
2693
2694         /* Disable IRQs while reconfiguring the device.
2695          * This makes it possible to drop the spinlock throughout
2696          * the reconfiguration process. */
2697         spin_lock_irqsave(&wl->irq_lock, flags);
2698         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2699                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2700                 goto out_unlock_mutex;
2701         }
2702         savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
2703         spin_unlock_irqrestore(&wl->irq_lock, flags);
2704         b43legacy_synchronize_irq(dev);
2705
2706         /* Switch to the requested channel.
2707          * The firmware takes care of races with the TX handler. */
2708         if (conf->channel->hw_value != phy->channel)
2709                 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
2710
2711         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2712
2713         /* Adjust the desired TX power level. */
2714         if (conf->power_level != 0) {
2715                 if (conf->power_level != phy->power_level) {
2716                         phy->power_level = conf->power_level;
2717                         b43legacy_phy_xmitpower(dev);
2718                 }
2719         }
2720
2721         /* Antennas for RX and management frame TX. */
2722         b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2723
2724         if (!!conf->radio_enabled != phy->radio_on) {
2725                 if (conf->radio_enabled) {
2726                         b43legacy_radio_turn_on(dev);
2727                         b43legacyinfo(dev->wl, "Radio turned on by software\n");
2728                         if (!dev->radio_hw_enable)
2729                                 b43legacyinfo(dev->wl, "The hardware RF-kill"
2730                                               " button still turns the radio"
2731                                               " physically off. Press the"
2732                                               " button to turn it on.\n");
2733                 } else {
2734                         b43legacy_radio_turn_off(dev, 0);
2735                         b43legacyinfo(dev->wl, "Radio turned off by"
2736                                       " software\n");
2737                 }
2738         }
2739
2740         spin_lock_irqsave(&wl->irq_lock, flags);
2741         b43legacy_interrupt_enable(dev, savedirqs);
2742         mmiowb();
2743         spin_unlock_irqrestore(&wl->irq_lock, flags);
2744 out_unlock_mutex:
2745         mutex_unlock(&wl->mutex);
2746
2747         return err;
2748 }
2749
2750 static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
2751 {
2752         struct ieee80211_supported_band *sband =
2753                 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2754         struct ieee80211_rate *rate;
2755         int i;
2756         u16 basic, direct, offset, basic_offset, rateptr;
2757
2758         for (i = 0; i < sband->n_bitrates; i++) {
2759                 rate = &sband->bitrates[i];
2760
2761                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2762                         direct = B43legacy_SHM_SH_CCKDIRECT;
2763                         basic = B43legacy_SHM_SH_CCKBASIC;
2764                         offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2765                         offset &= 0xF;
2766                 } else {
2767                         direct = B43legacy_SHM_SH_OFDMDIRECT;
2768                         basic = B43legacy_SHM_SH_OFDMBASIC;
2769                         offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2770                         offset &= 0xF;
2771                 }
2772
2773                 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2774
2775                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2776                         basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2777                         basic_offset &= 0xF;
2778                 } else {
2779                         basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2780                         basic_offset &= 0xF;
2781                 }
2782
2783                 /*
2784                  * Get the pointer that we need to point to
2785                  * from the direct map
2786                  */
2787                 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2788                                                direct + 2 * basic_offset);
2789                 /* and write it to the basic map */
2790                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2791                                       basic + 2 * offset, rateptr);
2792         }
2793 }
2794
2795 static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2796                                     struct ieee80211_vif *vif,
2797                                     struct ieee80211_bss_conf *conf,
2798                                     u32 changed)
2799 {
2800         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2801         struct b43legacy_wldev *dev;
2802         struct b43legacy_phy *phy;
2803         unsigned long flags;
2804         u32 savedirqs;
2805
2806         mutex_lock(&wl->mutex);
2807
2808         dev = wl->current_dev;
2809         phy = &dev->phy;
2810
2811         /* Disable IRQs while reconfiguring the device.
2812          * This makes it possible to drop the spinlock throughout
2813          * the reconfiguration process. */
2814         spin_lock_irqsave(&wl->irq_lock, flags);
2815         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2816                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2817                 goto out_unlock_mutex;
2818         }
2819         savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
2820         spin_unlock_irqrestore(&wl->irq_lock, flags);
2821         b43legacy_synchronize_irq(dev);
2822
2823         b43legacy_mac_suspend(dev);
2824
2825         if (changed & BSS_CHANGED_BEACON_INT &&
2826             (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2827              b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2828                 b43legacy_set_beacon_int(dev, conf->beacon_int);
2829
2830         if (changed & BSS_CHANGED_BASIC_RATES)
2831                 b43legacy_update_basic_rates(dev, conf->basic_rates);
2832
2833         if (changed & BSS_CHANGED_ERP_SLOT) {
2834                 if (conf->use_short_slot)
2835                         b43legacy_short_slot_timing_enable(dev);
2836                 else
2837                         b43legacy_short_slot_timing_disable(dev);
2838         }
2839
2840         b43legacy_mac_enable(dev);
2841
2842         spin_lock_irqsave(&wl->irq_lock, flags);
2843         b43legacy_interrupt_enable(dev, savedirqs);
2844         /* XXX: why? */
2845         mmiowb();
2846         spin_unlock_irqrestore(&wl->irq_lock, flags);
2847  out_unlock_mutex:
2848         mutex_unlock(&wl->mutex);
2849
2850         return;
2851 }
2852
2853 static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2854                                           unsigned int changed,
2855                                           unsigned int *fflags,
2856                                           int mc_count,
2857                                           struct dev_addr_list *mc_list)
2858 {
2859         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2860         struct b43legacy_wldev *dev = wl->current_dev;
2861         unsigned long flags;
2862
2863         if (!dev) {
2864                 *fflags = 0;
2865                 return;
2866         }
2867
2868         spin_lock_irqsave(&wl->irq_lock, flags);
2869         *fflags &= FIF_PROMISC_IN_BSS |
2870                   FIF_ALLMULTI |
2871                   FIF_FCSFAIL |
2872                   FIF_PLCPFAIL |
2873                   FIF_CONTROL |
2874                   FIF_OTHER_BSS |
2875                   FIF_BCN_PRBRESP_PROMISC;
2876
2877         changed &= FIF_PROMISC_IN_BSS |
2878                    FIF_ALLMULTI |
2879                    FIF_FCSFAIL |
2880                    FIF_PLCPFAIL |
2881                    FIF_CONTROL |
2882                    FIF_OTHER_BSS |
2883                    FIF_BCN_PRBRESP_PROMISC;
2884
2885         wl->filter_flags = *fflags;
2886
2887         if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2888                 b43legacy_adjust_opmode(dev);
2889         spin_unlock_irqrestore(&wl->irq_lock, flags);
2890 }
2891
2892 static int b43legacy_op_config_interface(struct ieee80211_hw *hw,
2893                                          struct ieee80211_vif *vif,
2894                                          struct ieee80211_if_conf *conf)
2895 {
2896         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2897         struct b43legacy_wldev *dev = wl->current_dev;
2898         unsigned long flags;
2899
2900         if (!dev)
2901                 return -ENODEV;
2902         mutex_lock(&wl->mutex);
2903         spin_lock_irqsave(&wl->irq_lock, flags);
2904         B43legacy_WARN_ON(wl->vif != vif);
2905         if (conf->bssid)
2906                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2907         else
2908                 memset(wl->bssid, 0, ETH_ALEN);
2909         if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2910                 if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP)) {
2911                         B43legacy_WARN_ON(vif->type != NL80211_IFTYPE_AP);
2912                         if (conf->changed & IEEE80211_IFCC_BEACON)
2913                                 b43legacy_update_templates(wl);
2914                 } else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)) {
2915                         if (conf->changed & IEEE80211_IFCC_BEACON)
2916                                 b43legacy_update_templates(wl);
2917                 }
2918                 b43legacy_write_mac_bssid_templates(dev);
2919         }
2920         spin_unlock_irqrestore(&wl->irq_lock, flags);
2921         mutex_unlock(&wl->mutex);
2922
2923         return 0;
2924 }
2925
2926 /* Locking: wl->mutex */
2927 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2928 {
2929         struct b43legacy_wl *wl = dev->wl;
2930         unsigned long flags;
2931
2932         if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2933                 return;
2934
2935         /* Disable and sync interrupts. We must do this before than
2936          * setting the status to INITIALIZED, as the interrupt handler
2937          * won't care about IRQs then. */
2938         spin_lock_irqsave(&wl->irq_lock, flags);
2939         dev->irq_savedstate = b43legacy_interrupt_disable(dev,
2940                                                           B43legacy_IRQ_ALL);
2941         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2942         spin_unlock_irqrestore(&wl->irq_lock, flags);
2943         b43legacy_synchronize_irq(dev);
2944
2945         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2946
2947         mutex_unlock(&wl->mutex);
2948         /* Must unlock as it would otherwise deadlock. No races here.
2949          * Cancel the possibly running self-rearming periodic work. */
2950         cancel_delayed_work_sync(&dev->periodic_work);
2951         mutex_lock(&wl->mutex);
2952
2953         ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2954
2955         b43legacy_mac_suspend(dev);
2956         free_irq(dev->dev->irq, dev);
2957         b43legacydbg(wl, "Wireless interface stopped\n");
2958 }
2959
2960 /* Locking: wl->mutex */
2961 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2962 {
2963         int err;
2964
2965         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2966
2967         drain_txstatus_queue(dev);
2968         err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2969                           IRQF_SHARED, KBUILD_MODNAME, dev);
2970         if (err) {
2971                 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2972                        dev->dev->irq);
2973                 goto out;
2974         }
2975         /* We are ready to run. */
2976         b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2977
2978         /* Start data flow (TX/RX) */
2979         b43legacy_mac_enable(dev);
2980         b43legacy_interrupt_enable(dev, dev->irq_savedstate);
2981
2982         /* Start maintenance work */
2983         b43legacy_periodic_tasks_setup(dev);
2984
2985         b43legacydbg(dev->wl, "Wireless interface started\n");
2986 out:
2987         return err;
2988 }
2989
2990 /* Get PHY and RADIO versioning numbers */
2991 static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2992 {
2993         struct b43legacy_phy *phy = &dev->phy;
2994         u32 tmp;
2995         u8 analog_type;
2996         u8 phy_type;
2997         u8 phy_rev;
2998         u16 radio_manuf;
2999         u16 radio_ver;
3000         u16 radio_rev;
3001         int unsupported = 0;
3002
3003         /* Get PHY versioning */
3004         tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
3005         analog_type = (tmp & B43legacy_PHYVER_ANALOG)
3006                       >> B43legacy_PHYVER_ANALOG_SHIFT;
3007         phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
3008         phy_rev = (tmp & B43legacy_PHYVER_VERSION);
3009         switch (phy_type) {
3010         case B43legacy_PHYTYPE_B:
3011                 if (phy_rev != 2 && phy_rev != 4
3012                     && phy_rev != 6 && phy_rev != 7)
3013                         unsupported = 1;
3014                 break;
3015         case B43legacy_PHYTYPE_G:
3016                 if (phy_rev > 8)
3017                         unsupported = 1;
3018                 break;
3019         default:
3020                 unsupported = 1;
3021         };
3022         if (unsupported) {
3023                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
3024                        "(Analog %u, Type %u, Revision %u)\n",
3025                        analog_type, phy_type, phy_rev);
3026                 return -EOPNOTSUPP;
3027         }
3028         b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3029                analog_type, phy_type, phy_rev);
3030
3031
3032         /* Get RADIO versioning */
3033         if (dev->dev->bus->chip_id == 0x4317) {
3034                 if (dev->dev->bus->chip_rev == 0)
3035                         tmp = 0x3205017F;
3036                 else if (dev->dev->bus->chip_rev == 1)
3037                         tmp = 0x4205017F;
3038                 else
3039                         tmp = 0x5205017F;
3040         } else {
3041                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
3042                                   B43legacy_RADIOCTL_ID);
3043                 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
3044                 tmp <<= 16;
3045                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
3046                                   B43legacy_RADIOCTL_ID);
3047                 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
3048         }
3049         radio_manuf = (tmp & 0x00000FFF);
3050         radio_ver = (tmp & 0x0FFFF000) >> 12;
3051         radio_rev = (tmp & 0xF0000000) >> 28;
3052         switch (phy_type) {
3053         case B43legacy_PHYTYPE_B:
3054                 if ((radio_ver & 0xFFF0) != 0x2050)
3055                         unsupported = 1;
3056                 break;
3057         case B43legacy_PHYTYPE_G:
3058                 if (radio_ver != 0x2050)
3059                         unsupported = 1;
3060                 break;
3061         default:
3062                 B43legacy_BUG_ON(1);
3063         }
3064         if (unsupported) {
3065                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
3066                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3067                        radio_manuf, radio_ver, radio_rev);
3068                 return -EOPNOTSUPP;
3069         }
3070         b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
3071                      " Revision %u\n", radio_manuf, radio_ver, radio_rev);
3072
3073
3074         phy->radio_manuf = radio_manuf;
3075         phy->radio_ver = radio_ver;
3076         phy->radio_rev = radio_rev;
3077
3078         phy->analog = analog_type;
3079         phy->type = phy_type;
3080         phy->rev = phy_rev;
3081
3082         return 0;
3083 }
3084
3085 static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
3086                                       struct b43legacy_phy *phy)
3087 {
3088         struct b43legacy_lopair *lo;
3089         int i;
3090
3091         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3092         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3093
3094         /* Assume the radio is enabled. If it's not enabled, the state will
3095          * immediately get fixed on the first periodic work run. */
3096         dev->radio_hw_enable = 1;
3097
3098         phy->savedpctlreg = 0xFFFF;
3099         phy->aci_enable = 0;
3100         phy->aci_wlan_automatic = 0;
3101         phy->aci_hw_rssi = 0;
3102
3103         lo = phy->_lo_pairs;
3104         if (lo)
3105                 memset(lo, 0, sizeof(struct b43legacy_lopair) *
3106                                      B43legacy_LO_COUNT);
3107         phy->max_lb_gain = 0;
3108         phy->trsw_rx_gain = 0;
3109
3110         /* Set default attenuation values. */
3111         phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3112         phy->rfatt = b43legacy_default_radio_attenuation(dev);
3113         phy->txctl1 = b43legacy_default_txctl1(dev);
3114         phy->txpwr_offset = 0;
3115
3116         /* NRSSI */
3117         phy->nrssislope = 0;
3118         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3119                 phy->nrssi[i] = -1000;
3120         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3121                 phy->nrssi_lt[i] = i;
3122
3123         phy->lofcal = 0xFFFF;
3124         phy->initval = 0xFFFF;
3125
3126         phy->interfmode = B43legacy_INTERFMODE_NONE;
3127         phy->channel = 0xFF;
3128 }
3129
3130 static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
3131 {
3132         /* Flags */
3133         dev->dfq_valid = 0;
3134
3135         /* Stats */
3136         memset(&dev->stats, 0, sizeof(dev->stats));
3137
3138         setup_struct_phy_for_init(dev, &dev->phy);
3139
3140         /* IRQ related flags */
3141         dev->irq_reason = 0;
3142         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3143         dev->irq_savedstate = B43legacy_IRQ_MASKTEMPLATE;
3144
3145         dev->mac_suspended = 1;
3146
3147         /* Noise calculation context */
3148         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3149 }
3150
3151 static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
3152 {
3153 #ifdef CONFIG_SSB_DRIVER_PCICORE
3154         struct ssb_bus *bus = dev->dev->bus;
3155         u32 tmp;
3156
3157         if (bus->pcicore.dev &&
3158             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3159             bus->pcicore.dev->id.revision <= 5) {
3160                 /* IMCFGLO timeouts workaround. */
3161                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3162                 tmp &= ~SSB_IMCFGLO_REQTO;
3163                 tmp &= ~SSB_IMCFGLO_SERTO;
3164                 switch (bus->bustype) {
3165                 case SSB_BUSTYPE_PCI:
3166                 case SSB_BUSTYPE_PCMCIA:
3167                         tmp |= 0x32;
3168                         break;
3169                 case SSB_BUSTYPE_SSB:
3170                         tmp |= 0x53;
3171                         break;
3172                 }
3173                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3174         }
3175 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3176 }
3177
3178 static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,
3179                                           bool idle) {
3180         u16 pu_delay = 1050;
3181
3182         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3183                 pu_delay = 500;
3184         if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3185                 pu_delay = max(pu_delay, (u16)2400);
3186
3187         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3188                               B43legacy_SHM_SH_SPUWKUP, pu_delay);
3189 }
3190
3191 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3192 static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev)
3193 {
3194         u16 pretbtt;
3195
3196         /* The time value is in microseconds. */
3197         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3198                 pretbtt = 2;
3199         else
3200                 pretbtt = 250;
3201         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3202                               B43legacy_SHM_SH_PRETBTT, pretbtt);
3203         b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt);
3204 }
3205
3206 /* Shutdown a wireless core */
3207 /* Locking: wl->mutex */
3208 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
3209 {
3210         struct b43legacy_phy *phy = &dev->phy;
3211         u32 macctl;
3212
3213         B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
3214         if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
3215                 return;
3216         b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3217
3218         /* Stop the microcode PSM. */
3219         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3220         macctl &= ~B43legacy_MACCTL_PSM_RUN;
3221         macctl |= B43legacy_MACCTL_PSM_JMP0;
3222         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3223
3224         b43legacy_leds_exit(dev);
3225         b43legacy_rng_exit(dev->wl);
3226         b43legacy_pio_free(dev);
3227         b43legacy_dma_free(dev);
3228         b43legacy_chip_exit(dev);
3229         b43legacy_radio_turn_off(dev, 1);
3230         b43legacy_switch_analog(dev, 0);
3231         if (phy->dyn_tssi_tbl)
3232                 kfree(phy->tssi2dbm);
3233         kfree(phy->lo_control);
3234         phy->lo_control = NULL;
3235         if (dev->wl->current_beacon) {
3236                 dev_kfree_skb_any(dev->wl->current_beacon);
3237                 dev->wl->current_beacon = NULL;
3238         }
3239
3240         ssb_device_disable(dev->dev, 0);
3241         ssb_bus_may_powerdown(dev->dev->bus);
3242 }
3243
3244 static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3245 {
3246         struct b43legacy_phy *phy = &dev->phy;
3247         int i;
3248
3249         /* Set default attenuation values. */
3250         phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3251         phy->rfatt = b43legacy_default_radio_attenuation(dev);
3252         phy->txctl1 = b43legacy_default_txctl1(dev);
3253         phy->txctl2 = 0xFFFF;
3254         phy->txpwr_offset = 0;
3255
3256         /* NRSSI */
3257         phy->nrssislope = 0;
3258         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3259                 phy->nrssi[i] = -1000;
3260         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3261                 phy->nrssi_lt[i] = i;
3262
3263         phy->lofcal = 0xFFFF;
3264         phy->initval = 0xFFFF;
3265
3266         phy->aci_enable = 0;
3267         phy->aci_wlan_automatic = 0;
3268         phy->aci_hw_rssi = 0;
3269
3270         phy->antenna_diversity = 0xFFFF;
3271         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3272         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3273
3274         /* Flags */
3275         phy->calibrated = 0;
3276
3277         if (phy->_lo_pairs)
3278                 memset(phy->_lo_pairs, 0,
3279                        sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3280         memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3281 }
3282
3283 /* Initialize a wireless core */
3284 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3285 {
3286         struct b43legacy_wl *wl = dev->wl;
3287         struct ssb_bus *bus = dev->dev->bus;
3288         struct b43legacy_phy *phy = &dev->phy;
3289         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3290         int err;
3291         u32 hf;
3292         u32 tmp;
3293
3294         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3295
3296         err = ssb_bus_powerup(bus, 0);
3297         if (err)
3298                 goto out;
3299         if (!ssb_device_is_enabled(dev->dev)) {
3300                 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3301                 b43legacy_wireless_core_reset(dev, tmp);
3302         }
3303
3304         if ((phy->type == B43legacy_PHYTYPE_B) ||
3305             (phy->type == B43legacy_PHYTYPE_G)) {
3306                 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3307                                          * B43legacy_LO_COUNT,
3308                                          GFP_KERNEL);
3309                 if (!phy->_lo_pairs)
3310                         return -ENOMEM;
3311         }
3312         setup_struct_wldev_for_init(dev);
3313
3314         err = b43legacy_phy_init_tssi2dbm_table(dev);
3315         if (err)
3316                 goto err_kfree_lo_control;
3317
3318         /* Enable IRQ routing to this device. */
3319         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3320
3321         b43legacy_imcfglo_timeouts_workaround(dev);
3322         prepare_phy_data_for_init(dev);
3323         b43legacy_phy_calibrate(dev);
3324         err = b43legacy_chip_init(dev);
3325         if (err)
3326                 goto err_kfree_tssitbl;
3327         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3328                               B43legacy_SHM_SH_WLCOREREV,
3329                               dev->dev->id.revision);
3330         hf = b43legacy_hf_read(dev);
3331         if (phy->type == B43legacy_PHYTYPE_G) {
3332                 hf |= B43legacy_HF_SYMW;
3333                 if (phy->rev == 1)
3334                         hf |= B43legacy_HF_GDCW;
3335                 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
3336                         hf |= B43legacy_HF_OFDMPABOOST;
3337         } else if (phy->type == B43legacy_PHYTYPE_B) {
3338                 hf |= B43legacy_HF_SYMW;
3339                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3340                         hf &= ~B43legacy_HF_GDCW;
3341         }
3342         b43legacy_hf_write(dev, hf);
3343
3344         b43legacy_set_retry_limits(dev,
3345                                    B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3346                                    B43legacy_DEFAULT_LONG_RETRY_LIMIT);
3347
3348         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3349                               0x0044, 3);
3350         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3351                               0x0046, 2);
3352
3353         /* Disable sending probe responses from firmware.
3354          * Setting the MaxTime to one usec will always trigger
3355          * a timeout, so we never send any probe resp.
3356          * A timeout of zero is infinite. */
3357         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3358                               B43legacy_SHM_SH_PRMAXTIME, 1);
3359
3360         b43legacy_rate_memory_init(dev);
3361
3362         /* Minimum Contention Window */
3363         if (phy->type == B43legacy_PHYTYPE_B)
3364                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3365                                       0x0003, 31);
3366         else
3367                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3368                                       0x0003, 15);
3369         /* Maximum Contention Window */
3370         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3371                               0x0004, 1023);
3372
3373         do {
3374                 if (b43legacy_using_pio(dev))
3375                         err = b43legacy_pio_init(dev);
3376                 else {
3377                         err = b43legacy_dma_init(dev);
3378                         if (!err)
3379                                 b43legacy_qos_init(dev);
3380                 }
3381         } while (err == -EAGAIN);
3382         if (err)
3383                 goto err_chip_exit;
3384
3385         b43legacy_set_synth_pu_delay(dev, 1);
3386
3387         ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3388         b43legacy_upload_card_macaddress(dev);
3389         b43legacy_security_init(dev);
3390         b43legacy_rng_init(wl);
3391
3392         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3393
3394         b43legacy_leds_init(dev);
3395 out:
3396         return err;
3397
3398 err_chip_exit:
3399         b43legacy_chip_exit(dev);
3400 err_kfree_tssitbl:
3401         if (phy->dyn_tssi_tbl)
3402                 kfree(phy->tssi2dbm);
3403 err_kfree_lo_control:
3404         kfree(phy->lo_control);
3405         phy->lo_control = NULL;
3406         ssb_bus_may_powerdown(bus);
3407         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3408         return err;
3409 }
3410
3411 static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
3412                                       struct ieee80211_if_init_conf *conf)
3413 {
3414         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3415         struct b43legacy_wldev *dev;
3416         unsigned long flags;
3417         int err = -EOPNOTSUPP;
3418
3419         /* TODO: allow WDS/AP devices to coexist */
3420
3421         if (conf->type != NL80211_IFTYPE_AP &&
3422             conf->type != NL80211_IFTYPE_STATION &&
3423             conf->type != NL80211_IFTYPE_WDS &&
3424             conf->type != NL80211_IFTYPE_ADHOC)
3425                 return -EOPNOTSUPP;
3426
3427         mutex_lock(&wl->mutex);
3428         if (wl->operating)
3429                 goto out_mutex_unlock;
3430
3431         b43legacydbg(wl, "Adding Interface type %d\n", conf->type);
3432
3433         dev = wl->current_dev;
3434         wl->operating = 1;
3435         wl->vif = conf->vif;
3436         wl->if_type = conf->type;
3437         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3438
3439         spin_lock_irqsave(&wl->irq_lock, flags);
3440         b43legacy_adjust_opmode(dev);
3441         b43legacy_set_pretbtt(dev);
3442         b43legacy_set_synth_pu_delay(dev, 0);
3443         b43legacy_upload_card_macaddress(dev);
3444         spin_unlock_irqrestore(&wl->irq_lock, flags);
3445
3446         err = 0;
3447  out_mutex_unlock:
3448         mutex_unlock(&wl->mutex);
3449
3450         return err;
3451 }
3452
3453 static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
3454                                           struct ieee80211_if_init_conf *conf)
3455 {
3456         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3457         struct b43legacy_wldev *dev = wl->current_dev;
3458         unsigned long flags;
3459
3460         b43legacydbg(wl, "Removing Interface type %d\n", conf->type);
3461
3462         mutex_lock(&wl->mutex);
3463
3464         B43legacy_WARN_ON(!wl->operating);
3465         B43legacy_WARN_ON(wl->vif != conf->vif);
3466         wl->vif = NULL;
3467
3468         wl->operating = 0;
3469
3470         spin_lock_irqsave(&wl->irq_lock, flags);
3471         b43legacy_adjust_opmode(dev);
3472         memset(wl->mac_addr, 0, ETH_ALEN);
3473         b43legacy_upload_card_macaddress(dev);
3474         spin_unlock_irqrestore(&wl->irq_lock, flags);
3475
3476         mutex_unlock(&wl->mutex);
3477 }
3478
3479 static int b43legacy_op_start(struct ieee80211_hw *hw)
3480 {
3481         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3482         struct b43legacy_wldev *dev = wl->current_dev;
3483         int did_init = 0;
3484         int err = 0;
3485         bool do_rfkill_exit = 0;
3486
3487         /* First register RFkill.
3488          * LEDs that are registered later depend on it. */
3489         b43legacy_rfkill_init(dev);
3490
3491         /* Kill all old instance specific information to make sure
3492          * the card won't use it in the short timeframe between start
3493          * and mac80211 reconfiguring it. */
3494         memset(wl->bssid, 0, ETH_ALEN);
3495         memset(wl->mac_addr, 0, ETH_ALEN);
3496         wl->filter_flags = 0;
3497         wl->beacon0_uploaded = 0;
3498         wl->beacon1_uploaded = 0;
3499         wl->beacon_templates_virgin = 1;
3500
3501         mutex_lock(&wl->mutex);
3502
3503         if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
3504                 err = b43legacy_wireless_core_init(dev);
3505                 if (err) {
3506                         do_rfkill_exit = 1;
3507                         goto out_mutex_unlock;
3508                 }
3509                 did_init = 1;
3510         }
3511
3512         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
3513                 err = b43legacy_wireless_core_start(dev);
3514                 if (err) {
3515                         if (did_init)
3516                                 b43legacy_wireless_core_exit(dev);
3517                         do_rfkill_exit = 1;
3518                         goto out_mutex_unlock;
3519                 }
3520         }
3521
3522 out_mutex_unlock:
3523         mutex_unlock(&wl->mutex);
3524
3525         if (do_rfkill_exit)
3526                 b43legacy_rfkill_exit(dev);
3527
3528         return err;
3529 }
3530
3531 static void b43legacy_op_stop(struct ieee80211_hw *hw)
3532 {
3533         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3534         struct b43legacy_wldev *dev = wl->current_dev;
3535
3536         b43legacy_rfkill_exit(dev);
3537         cancel_work_sync(&(wl->beacon_update_trigger));
3538
3539         mutex_lock(&wl->mutex);
3540         if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
3541                 b43legacy_wireless_core_stop(dev);
3542         b43legacy_wireless_core_exit(dev);
3543         mutex_unlock(&wl->mutex);
3544 }
3545
3546 static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw,
3547                                        struct ieee80211_sta *sta, bool set)
3548 {
3549         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3550         unsigned long flags;
3551
3552         spin_lock_irqsave(&wl->irq_lock, flags);
3553         b43legacy_update_templates(wl);
3554         spin_unlock_irqrestore(&wl->irq_lock, flags);
3555
3556         return 0;
3557 }
3558
3559 static const struct ieee80211_ops b43legacy_hw_ops = {
3560         .tx                     = b43legacy_op_tx,
3561         .conf_tx                = b43legacy_op_conf_tx,
3562         .add_interface          = b43legacy_op_add_interface,
3563         .remove_interface       = b43legacy_op_remove_interface,
3564         .config                 = b43legacy_op_dev_config,
3565         .bss_info_changed       = b43legacy_op_bss_info_changed,
3566         .config_interface       = b43legacy_op_config_interface,
3567         .configure_filter       = b43legacy_op_configure_filter,
3568         .get_stats              = b43legacy_op_get_stats,
3569         .get_tx_stats           = b43legacy_op_get_tx_stats,
3570         .start                  = b43legacy_op_start,
3571         .stop                   = b43legacy_op_stop,
3572         .set_tim                = b43legacy_op_beacon_set_tim,
3573 };
3574
3575 /* Hard-reset the chip. Do not call this directly.
3576  * Use b43legacy_controller_restart()
3577  */
3578 static void b43legacy_chip_reset(struct work_struct *work)
3579 {
3580         struct b43legacy_wldev *dev =
3581                 container_of(work, struct b43legacy_wldev, restart_work);
3582         struct b43legacy_wl *wl = dev->wl;
3583         int err = 0;
3584         int prev_status;
3585
3586         mutex_lock(&wl->mutex);
3587
3588         prev_status = b43legacy_status(dev);
3589         /* Bring the device down... */
3590         if (prev_status >= B43legacy_STAT_STARTED)
3591                 b43legacy_wireless_core_stop(dev);
3592         if (prev_status >= B43legacy_STAT_INITIALIZED)
3593                 b43legacy_wireless_core_exit(dev);
3594
3595         /* ...and up again. */
3596         if (prev_status >= B43legacy_STAT_INITIALIZED) {
3597                 err = b43legacy_wireless_core_init(dev);
3598                 if (err)
3599                         goto out;
3600         }
3601         if (prev_status >= B43legacy_STAT_STARTED) {
3602                 err = b43legacy_wireless_core_start(dev);
3603                 if (err) {
3604                         b43legacy_wireless_core_exit(dev);
3605                         goto out;
3606                 }
3607         }
3608 out:
3609         if (err)
3610                 wl->current_dev = NULL; /* Failed to init the dev. */
3611         mutex_unlock(&wl->mutex);
3612         if (err)
3613                 b43legacyerr(wl, "Controller restart FAILED\n");
3614         else
3615                 b43legacyinfo(wl, "Controller restarted\n");
3616 }
3617
3618 static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
3619                                  int have_bphy,
3620                                  int have_gphy)
3621 {
3622         struct ieee80211_hw *hw = dev->wl->hw;
3623         struct b43legacy_phy *phy = &dev->phy;
3624
3625         phy->possible_phymodes = 0;
3626         if (have_bphy) {
3627                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3628                         &b43legacy_band_2GHz_BPHY;
3629                 phy->possible_phymodes |= B43legacy_PHYMODE_B;
3630         }
3631
3632         if (have_gphy) {
3633                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3634                         &b43legacy_band_2GHz_GPHY;
3635                 phy->possible_phymodes |= B43legacy_PHYMODE_G;
3636         }
3637
3638         return 0;
3639 }
3640
3641 static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
3642 {
3643         /* We release firmware that late to not be required to re-request
3644          * is all the time when we reinit the core. */
3645         b43legacy_release_firmware(dev);
3646 }
3647
3648 static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
3649 {
3650         struct b43legacy_wl *wl = dev->wl;
3651         struct ssb_bus *bus = dev->dev->bus;
3652         struct pci_dev *pdev = bus->host_pci;
3653         int err;
3654         int have_bphy = 0;
3655         int have_gphy = 0;
3656         u32 tmp;
3657
3658         /* Do NOT do any device initialization here.
3659          * Do it in wireless_core_init() instead.
3660          * This function is for gathering basic information about the HW, only.
3661          * Also some structs may be set up here. But most likely you want to
3662          * have that in core_init(), too.
3663          */
3664
3665         err = ssb_bus_powerup(bus, 0);
3666         if (err) {
3667                 b43legacyerr(wl, "Bus powerup failed\n");
3668                 goto out;
3669         }
3670         /* Get the PHY type. */
3671         if (dev->dev->id.revision >= 5) {
3672                 u32 tmshigh;
3673
3674                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3675                 have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
3676                 if (!have_gphy)
3677                         have_bphy = 1;
3678         } else if (dev->dev->id.revision == 4)
3679                 have_gphy = 1;
3680         else
3681                 have_bphy = 1;
3682
3683         dev->phy.gmode = (have_gphy || have_bphy);
3684         tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3685         b43legacy_wireless_core_reset(dev, tmp);
3686
3687         err = b43legacy_phy_versioning(dev);
3688         if (err)
3689                 goto err_powerdown;
3690         /* Check if this device supports multiband. */
3691         if (!pdev ||
3692             (pdev->device != 0x4312 &&
3693              pdev->device != 0x4319 &&
3694              pdev->device != 0x4324)) {
3695                 /* No multiband support. */
3696                 have_bphy = 0;
3697                 have_gphy = 0;
3698                 switch (dev->phy.type) {
3699                 case B43legacy_PHYTYPE_B:
3700                         have_bphy = 1;
3701                         break;
3702                 case B43legacy_PHYTYPE_G:
3703                         have_gphy = 1;
3704                         break;
3705                 default:
3706                         B43legacy_BUG_ON(1);
3707                 }
3708         }
3709         dev->phy.gmode = (have_gphy || have_bphy);
3710         tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3711         b43legacy_wireless_core_reset(dev, tmp);
3712
3713         err = b43legacy_validate_chipaccess(dev);
3714         if (err)
3715                 goto err_powerdown;
3716         err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
3717         if (err)
3718                 goto err_powerdown;
3719
3720         /* Now set some default "current_dev" */
3721         if (!wl->current_dev)
3722                 wl->current_dev = dev;
3723         INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
3724
3725         b43legacy_radio_turn_off(dev, 1);
3726         b43legacy_switch_analog(dev, 0);
3727         ssb_device_disable(dev->dev, 0);
3728         ssb_bus_may_powerdown(bus);
3729
3730 out:
3731         return err;
3732
3733 err_powerdown:
3734         ssb_bus_may_powerdown(bus);
3735         return err;
3736 }
3737
3738 static void b43legacy_one_core_detach(struct ssb_device *dev)
3739 {
3740         struct b43legacy_wldev *wldev;
3741         struct b43legacy_wl *wl;
3742
3743         /* Do not cancel ieee80211-workqueue based work here.
3744          * See comment in b43legacy_remove(). */
3745
3746         wldev = ssb_get_drvdata(dev);
3747         wl = wldev->wl;
3748         b43legacy_debugfs_remove_device(wldev);
3749         b43legacy_wireless_core_detach(wldev);
3750         list_del(&wldev->list);
3751         wl->nr_devs--;
3752         ssb_set_drvdata(dev, NULL);
3753         kfree(wldev);
3754 }
3755
3756 static int b43legacy_one_core_attach(struct ssb_device *dev,
3757                                      struct b43legacy_wl *wl)
3758 {
3759         struct b43legacy_wldev *wldev;
3760         struct pci_dev *pdev;
3761         int err = -ENOMEM;
3762
3763         if (!list_empty(&wl->devlist)) {
3764                 /* We are not the first core on this chip. */
3765                 pdev = dev->bus->host_pci;
3766                 /* Only special chips support more than one wireless
3767                  * core, although some of the other chips have more than
3768                  * one wireless core as well. Check for this and
3769                  * bail out early.
3770                  */
3771                 if (!pdev ||
3772                     ((pdev->device != 0x4321) &&
3773                      (pdev->device != 0x4313) &&
3774                      (pdev->device != 0x431A))) {
3775                         b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
3776                         return -ENODEV;
3777                 }
3778         }
3779
3780         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3781         if (!wldev)
3782                 goto out;
3783
3784         wldev->dev = dev;
3785         wldev->wl = wl;
3786         b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
3787         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3788         tasklet_init(&wldev->isr_tasklet,
3789                      (void (*)(unsigned long))b43legacy_interrupt_tasklet,
3790                      (unsigned long)wldev);
3791         if (modparam_pio)
3792                 wldev->__using_pio = 1;
3793         INIT_LIST_HEAD(&wldev->list);
3794
3795         err = b43legacy_wireless_core_attach(wldev);
3796         if (err)
3797                 goto err_kfree_wldev;
3798
3799         list_add(&wldev->list, &wl->devlist);
3800         wl->nr_devs++;
3801         ssb_set_drvdata(dev, wldev);
3802         b43legacy_debugfs_add_device(wldev);
3803 out:
3804         return err;
3805
3806 err_kfree_wldev:
3807         kfree(wldev);
3808         return err;
3809 }
3810
3811 static void b43legacy_sprom_fixup(struct ssb_bus *bus)
3812 {
3813         /* boardflags workarounds */
3814         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3815             bus->boardinfo.type == 0x4E &&
3816             bus->boardinfo.rev > 0x40)
3817                 bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
3818 }
3819
3820 static void b43legacy_wireless_exit(struct ssb_device *dev,
3821                                   struct b43legacy_wl *wl)
3822 {
3823         struct ieee80211_hw *hw = wl->hw;
3824
3825         ssb_set_devtypedata(dev, NULL);
3826         ieee80211_free_hw(hw);
3827 }
3828
3829 static int b43legacy_wireless_init(struct ssb_device *dev)
3830 {
3831         struct ssb_sprom *sprom = &dev->bus->sprom;
3832         struct ieee80211_hw *hw;
3833         struct b43legacy_wl *wl;
3834         int err = -ENOMEM;
3835
3836         b43legacy_sprom_fixup(dev->bus);
3837
3838         hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
3839         if (!hw) {
3840                 b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
3841                 goto out;
3842         }
3843
3844         /* fill hw info */
3845         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3846                     IEEE80211_HW_SIGNAL_DBM |
3847                     IEEE80211_HW_NOISE_DBM;
3848         hw->wiphy->interface_modes =
3849                 BIT(NL80211_IFTYPE_AP) |
3850                 BIT(NL80211_IFTYPE_STATION) |
3851                 BIT(NL80211_IFTYPE_WDS) |
3852                 BIT(NL80211_IFTYPE_ADHOC);
3853         hw->queues = 1; /* FIXME: hardware has more queues */
3854         hw->max_rates = 2;
3855         SET_IEEE80211_DEV(hw, dev->dev);
3856         if (is_valid_ether_addr(sprom->et1mac))
3857                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3858         else
3859                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3860
3861         /* Get and initialize struct b43legacy_wl */
3862         wl = hw_to_b43legacy_wl(hw);
3863         memset(wl, 0, sizeof(*wl));
3864         wl->hw = hw;
3865         spin_lock_init(&wl->irq_lock);
3866         spin_lock_init(&wl->leds_lock);
3867         mutex_init(&wl->mutex);
3868         INIT_LIST_HEAD(&wl->devlist);
3869         INIT_WORK(&wl->beacon_update_trigger, b43legacy_beacon_update_trigger_work);
3870
3871         ssb_set_devtypedata(dev, wl);
3872         b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3873         err = 0;
3874 out:
3875         return err;
3876 }
3877
3878 static int b43legacy_probe(struct ssb_device *dev,
3879                          const struct ssb_device_id *id)
3880 {
3881         struct b43legacy_wl *wl;
3882         int err;
3883         int first = 0;
3884
3885         wl = ssb_get_devtypedata(dev);
3886         if (!wl) {
3887                 /* Probing the first core - setup common struct b43legacy_wl */
3888                 first = 1;
3889                 err = b43legacy_wireless_init(dev);
3890                 if (err)
3891                         goto out;
3892                 wl = ssb_get_devtypedata(dev);
3893                 B43legacy_WARN_ON(!wl);
3894         }
3895         err = b43legacy_one_core_attach(dev, wl);
3896         if (err)
3897                 goto err_wireless_exit;
3898
3899         if (first) {
3900                 err = ieee80211_register_hw(wl->hw);
3901                 if (err)
3902                         goto err_one_core_detach;
3903         }
3904
3905 out:
3906         return err;
3907
3908 err_one_core_detach:
3909         b43legacy_one_core_detach(dev);
3910 err_wireless_exit:
3911         if (first)
3912                 b43legacy_wireless_exit(dev, wl);
3913         return err;
3914 }
3915
3916 static void b43legacy_remove(struct ssb_device *dev)
3917 {
3918         struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
3919         struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3920
3921         /* We must cancel any work here before unregistering from ieee80211,
3922          * as the ieee80211 unreg will destroy the workqueue. */
3923         cancel_work_sync(&wldev->restart_work);
3924
3925         B43legacy_WARN_ON(!wl);
3926         if (wl->current_dev == wldev)
3927                 ieee80211_unregister_hw(wl->hw);
3928
3929         b43legacy_one_core_detach(dev);
3930
3931         if (list_empty(&wl->devlist))
3932                 /* Last core on the chip unregistered.
3933                  * We can destroy common struct b43legacy_wl.
3934                  */
3935                 b43legacy_wireless_exit(dev, wl);
3936 }
3937
3938 /* Perform a hardware reset. This can be called from any context. */
3939 void b43legacy_controller_restart(struct b43legacy_wldev *dev,
3940                                   const char *reason)
3941 {
3942         /* Must avoid requeueing, if we are in shutdown. */
3943         if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
3944                 return;
3945         b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
3946         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3947 }
3948
3949 #ifdef CONFIG_PM
3950
3951 static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
3952 {
3953         struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3954         struct b43legacy_wl *wl = wldev->wl;
3955
3956         b43legacydbg(wl, "Suspending...\n");
3957
3958         mutex_lock(&wl->mutex);
3959         wldev->suspend_init_status = b43legacy_status(wldev);
3960         if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
3961                 b43legacy_wireless_core_stop(wldev);
3962         if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
3963                 b43legacy_wireless_core_exit(wldev);
3964         mutex_unlock(&wl->mutex);
3965
3966         b43legacydbg(wl, "Device suspended.\n");
3967
3968         return 0;
3969 }
3970
3971 static int b43legacy_resume(struct ssb_device *dev)
3972 {
3973         struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3974         struct b43legacy_wl *wl = wldev->wl;
3975         int err = 0;
3976
3977         b43legacydbg(wl, "Resuming...\n");
3978
3979         mutex_lock(&wl->mutex);
3980         if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
3981                 err = b43legacy_wireless_core_init(wldev);
3982                 if (err) {
3983                         b43legacyerr(wl, "Resume failed at core init\n");
3984                         goto out;
3985                 }
3986         }
3987         if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
3988                 err = b43legacy_wireless_core_start(wldev);
3989                 if (err) {
3990                         b43legacy_wireless_core_exit(wldev);
3991                         b43legacyerr(wl, "Resume failed at core start\n");
3992                         goto out;
3993                 }
3994         }
3995
3996         b43legacydbg(wl, "Device resumed.\n");
3997 out:
3998         mutex_unlock(&wl->mutex);
3999         return err;
4000 }
4001
4002 #else   /* CONFIG_PM */
4003 # define b43legacy_suspend      NULL
4004 # define b43legacy_resume               NULL
4005 #endif  /* CONFIG_PM */
4006
4007 static struct ssb_driver b43legacy_ssb_driver = {
4008         .name           = KBUILD_MODNAME,
4009         .id_table       = b43legacy_ssb_tbl,
4010         .probe          = b43legacy_probe,
4011         .remove         = b43legacy_remove,
4012         .suspend        = b43legacy_suspend,
4013         .resume         = b43legacy_resume,
4014 };
4015
4016 static void b43legacy_print_driverinfo(void)
4017 {
4018         const char *feat_pci = "", *feat_leds = "", *feat_rfkill = "",
4019                    *feat_pio = "", *feat_dma = "";
4020
4021 #ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
4022         feat_pci = "P";
4023 #endif
4024 #ifdef CONFIG_B43LEGACY_LEDS
4025         feat_leds = "L";
4026 #endif
4027 #ifdef CONFIG_B43LEGACY_RFKILL
4028         feat_rfkill = "R";
4029 #endif
4030 #ifdef CONFIG_B43LEGACY_PIO
4031         feat_pio = "I";
4032 #endif
4033 #ifdef CONFIG_B43LEGACY_DMA
4034         feat_dma = "D";
4035 #endif
4036         printk(KERN_INFO "Broadcom 43xx-legacy driver loaded "
4037                "[ Features: %s%s%s%s%s, Firmware-ID: "
4038                B43legacy_SUPPORTED_FIRMWARE_ID " ]\n",
4039                feat_pci, feat_leds, feat_rfkill, feat_pio, feat_dma);
4040 }
4041
4042 static int __init b43legacy_init(void)
4043 {
4044         int err;
4045
4046         b43legacy_debugfs_init();
4047
4048         err = ssb_driver_register(&b43legacy_ssb_driver);
4049         if (err)
4050                 goto err_dfs_exit;
4051
4052         b43legacy_print_driverinfo();
4053
4054         return err;
4055
4056 err_dfs_exit:
4057         b43legacy_debugfs_exit();
4058         return err;
4059 }
4060
4061 static void __exit b43legacy_exit(void)
4062 {
4063         ssb_driver_unregister(&b43legacy_ssb_driver);
4064         b43legacy_debugfs_exit();
4065 }
4066
4067 module_init(b43legacy_init)
4068 module_exit(b43legacy_exit)