mac80211: move TX info into skb->cb
[linux-2.6.git] / drivers / net / wireless / b43legacy / dma.c
1 /*
2
3   Broadcom B43legacy wireless driver
4
5   DMA ringbuffer and descriptor allocation/management
6
7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8
9   Some code in this file is derived from the b44.c driver
10   Copyright (C) 2002 David S. Miller
11   Copyright (C) Pekka Pietikainen
12
13   This program is free software; you can redistribute it and/or modify
14   it under the terms of the GNU General Public License as published by
15   the Free Software Foundation; either version 2 of the License, or
16   (at your option) any later version.
17
18   This program is distributed in the hope that it will be useful,
19   but WITHOUT ANY WARRANTY; without even the implied warranty of
20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21   GNU General Public License for more details.
22
23   You should have received a copy of the GNU General Public License
24   along with this program; see the file COPYING.  If not, write to
25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26   Boston, MA 02110-1301, USA.
27
28 */
29
30 #include "b43legacy.h"
31 #include "dma.h"
32 #include "main.h"
33 #include "debugfs.h"
34 #include "xmit.h"
35
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <net/dst.h>
41
42 /* 32bit DMA ops. */
43 static
44 struct b43legacy_dmadesc_generic *op32_idx2desc(
45                                         struct b43legacy_dmaring *ring,
46                                         int slot,
47                                         struct b43legacy_dmadesc_meta **meta)
48 {
49         struct b43legacy_dmadesc32 *desc;
50
51         *meta = &(ring->meta[slot]);
52         desc = ring->descbase;
53         desc = &(desc[slot]);
54
55         return (struct b43legacy_dmadesc_generic *)desc;
56 }
57
58 static void op32_fill_descriptor(struct b43legacy_dmaring *ring,
59                                  struct b43legacy_dmadesc_generic *desc,
60                                  dma_addr_t dmaaddr, u16 bufsize,
61                                  int start, int end, int irq)
62 {
63         struct b43legacy_dmadesc32 *descbase = ring->descbase;
64         int slot;
65         u32 ctl;
66         u32 addr;
67         u32 addrext;
68
69         slot = (int)(&(desc->dma32) - descbase);
70         B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
71
72         addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
73         addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
74                    >> SSB_DMA_TRANSLATION_SHIFT;
75         addr |= ssb_dma_translation(ring->dev->dev);
76         ctl = (bufsize - ring->frameoffset)
77               & B43legacy_DMA32_DCTL_BYTECNT;
78         if (slot == ring->nr_slots - 1)
79                 ctl |= B43legacy_DMA32_DCTL_DTABLEEND;
80         if (start)
81                 ctl |= B43legacy_DMA32_DCTL_FRAMESTART;
82         if (end)
83                 ctl |= B43legacy_DMA32_DCTL_FRAMEEND;
84         if (irq)
85                 ctl |= B43legacy_DMA32_DCTL_IRQ;
86         ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT)
87                & B43legacy_DMA32_DCTL_ADDREXT_MASK;
88
89         desc->dma32.control = cpu_to_le32(ctl);
90         desc->dma32.address = cpu_to_le32(addr);
91 }
92
93 static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot)
94 {
95         b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX,
96                             (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
97 }
98
99 static void op32_tx_suspend(struct b43legacy_dmaring *ring)
100 {
101         b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
102                             b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
103                             | B43legacy_DMA32_TXSUSPEND);
104 }
105
106 static void op32_tx_resume(struct b43legacy_dmaring *ring)
107 {
108         b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
109                             b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
110                             & ~B43legacy_DMA32_TXSUSPEND);
111 }
112
113 static int op32_get_current_rxslot(struct b43legacy_dmaring *ring)
114 {
115         u32 val;
116
117         val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS);
118         val &= B43legacy_DMA32_RXDPTR;
119
120         return (val / sizeof(struct b43legacy_dmadesc32));
121 }
122
123 static void op32_set_current_rxslot(struct b43legacy_dmaring *ring,
124                                     int slot)
125 {
126         b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
127                             (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
128 }
129
130 static const struct b43legacy_dma_ops dma32_ops = {
131         .idx2desc               = op32_idx2desc,
132         .fill_descriptor        = op32_fill_descriptor,
133         .poke_tx                = op32_poke_tx,
134         .tx_suspend             = op32_tx_suspend,
135         .tx_resume              = op32_tx_resume,
136         .get_current_rxslot     = op32_get_current_rxslot,
137         .set_current_rxslot     = op32_set_current_rxslot,
138 };
139
140 /* 64bit DMA ops. */
141 static
142 struct b43legacy_dmadesc_generic *op64_idx2desc(
143                                         struct b43legacy_dmaring *ring,
144                                         int slot,
145                                         struct b43legacy_dmadesc_meta
146                                         **meta)
147 {
148         struct b43legacy_dmadesc64 *desc;
149
150         *meta = &(ring->meta[slot]);
151         desc = ring->descbase;
152         desc = &(desc[slot]);
153
154         return (struct b43legacy_dmadesc_generic *)desc;
155 }
156
157 static void op64_fill_descriptor(struct b43legacy_dmaring *ring,
158                                  struct b43legacy_dmadesc_generic *desc,
159                                  dma_addr_t dmaaddr, u16 bufsize,
160                                  int start, int end, int irq)
161 {
162         struct b43legacy_dmadesc64 *descbase = ring->descbase;
163         int slot;
164         u32 ctl0 = 0;
165         u32 ctl1 = 0;
166         u32 addrlo;
167         u32 addrhi;
168         u32 addrext;
169
170         slot = (int)(&(desc->dma64) - descbase);
171         B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
172
173         addrlo = (u32)(dmaaddr & 0xFFFFFFFF);
174         addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
175         addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
176                   >> SSB_DMA_TRANSLATION_SHIFT;
177         addrhi |= ssb_dma_translation(ring->dev->dev);
178         if (slot == ring->nr_slots - 1)
179                 ctl0 |= B43legacy_DMA64_DCTL0_DTABLEEND;
180         if (start)
181                 ctl0 |= B43legacy_DMA64_DCTL0_FRAMESTART;
182         if (end)
183                 ctl0 |= B43legacy_DMA64_DCTL0_FRAMEEND;
184         if (irq)
185                 ctl0 |= B43legacy_DMA64_DCTL0_IRQ;
186         ctl1 |= (bufsize - ring->frameoffset)
187                 & B43legacy_DMA64_DCTL1_BYTECNT;
188         ctl1 |= (addrext << B43legacy_DMA64_DCTL1_ADDREXT_SHIFT)
189                 & B43legacy_DMA64_DCTL1_ADDREXT_MASK;
190
191         desc->dma64.control0 = cpu_to_le32(ctl0);
192         desc->dma64.control1 = cpu_to_le32(ctl1);
193         desc->dma64.address_low = cpu_to_le32(addrlo);
194         desc->dma64.address_high = cpu_to_le32(addrhi);
195 }
196
197 static void op64_poke_tx(struct b43legacy_dmaring *ring, int slot)
198 {
199         b43legacy_dma_write(ring, B43legacy_DMA64_TXINDEX,
200                             (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
201 }
202
203 static void op64_tx_suspend(struct b43legacy_dmaring *ring)
204 {
205         b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
206                             b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
207                             | B43legacy_DMA64_TXSUSPEND);
208 }
209
210 static void op64_tx_resume(struct b43legacy_dmaring *ring)
211 {
212         b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
213                             b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
214                             & ~B43legacy_DMA64_TXSUSPEND);
215 }
216
217 static int op64_get_current_rxslot(struct b43legacy_dmaring *ring)
218 {
219         u32 val;
220
221         val = b43legacy_dma_read(ring, B43legacy_DMA64_RXSTATUS);
222         val &= B43legacy_DMA64_RXSTATDPTR;
223
224         return (val / sizeof(struct b43legacy_dmadesc64));
225 }
226
227 static void op64_set_current_rxslot(struct b43legacy_dmaring *ring,
228                                     int slot)
229 {
230         b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
231                             (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
232 }
233
234 static const struct b43legacy_dma_ops dma64_ops = {
235         .idx2desc               = op64_idx2desc,
236         .fill_descriptor        = op64_fill_descriptor,
237         .poke_tx                = op64_poke_tx,
238         .tx_suspend             = op64_tx_suspend,
239         .tx_resume              = op64_tx_resume,
240         .get_current_rxslot     = op64_get_current_rxslot,
241         .set_current_rxslot     = op64_set_current_rxslot,
242 };
243
244
245 static inline int free_slots(struct b43legacy_dmaring *ring)
246 {
247         return (ring->nr_slots - ring->used_slots);
248 }
249
250 static inline int next_slot(struct b43legacy_dmaring *ring, int slot)
251 {
252         B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
253         if (slot == ring->nr_slots - 1)
254                 return 0;
255         return slot + 1;
256 }
257
258 static inline int prev_slot(struct b43legacy_dmaring *ring, int slot)
259 {
260         B43legacy_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
261         if (slot == 0)
262                 return ring->nr_slots - 1;
263         return slot - 1;
264 }
265
266 #ifdef CONFIG_B43LEGACY_DEBUG
267 static void update_max_used_slots(struct b43legacy_dmaring *ring,
268                                   int current_used_slots)
269 {
270         if (current_used_slots <= ring->max_used_slots)
271                 return;
272         ring->max_used_slots = current_used_slots;
273         if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE))
274                 b43legacydbg(ring->dev->wl,
275                        "max_used_slots increased to %d on %s ring %d\n",
276                        ring->max_used_slots,
277                        ring->tx ? "TX" : "RX",
278                        ring->index);
279 }
280 #else
281 static inline
282 void update_max_used_slots(struct b43legacy_dmaring *ring,
283                            int current_used_slots)
284 { }
285 #endif /* DEBUG */
286
287 /* Request a slot for usage. */
288 static inline
289 int request_slot(struct b43legacy_dmaring *ring)
290 {
291         int slot;
292
293         B43legacy_WARN_ON(!ring->tx);
294         B43legacy_WARN_ON(ring->stopped);
295         B43legacy_WARN_ON(free_slots(ring) == 0);
296
297         slot = next_slot(ring, ring->current_slot);
298         ring->current_slot = slot;
299         ring->used_slots++;
300
301         update_max_used_slots(ring, ring->used_slots);
302
303         return slot;
304 }
305
306 /* Mac80211-queue to b43legacy-ring mapping */
307 static struct b43legacy_dmaring *priority_to_txring(
308                                                 struct b43legacy_wldev *dev,
309                                                 int queue_priority)
310 {
311         struct b43legacy_dmaring *ring;
312
313 /*FIXME: For now we always run on TX-ring-1 */
314 return dev->dma.tx_ring1;
315
316         /* 0 = highest priority */
317         switch (queue_priority) {
318         default:
319                 B43legacy_WARN_ON(1);
320                 /* fallthrough */
321         case 0:
322                 ring = dev->dma.tx_ring3;
323                 break;
324         case 1:
325                 ring = dev->dma.tx_ring2;
326                 break;
327         case 2:
328                 ring = dev->dma.tx_ring1;
329                 break;
330         case 3:
331                 ring = dev->dma.tx_ring0;
332                 break;
333         case 4:
334                 ring = dev->dma.tx_ring4;
335                 break;
336         case 5:
337                 ring = dev->dma.tx_ring5;
338                 break;
339         }
340
341         return ring;
342 }
343
344 /* Bcm4301-ring to mac80211-queue mapping */
345 static inline int txring_to_priority(struct b43legacy_dmaring *ring)
346 {
347         static const u8 idx_to_prio[] =
348                 { 3, 2, 1, 0, 4, 5, };
349
350 /*FIXME: have only one queue, for now */
351 return 0;
352
353         return idx_to_prio[ring->index];
354 }
355
356
357 static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type,
358                                         int controller_idx)
359 {
360         static const u16 map64[] = {
361                 B43legacy_MMIO_DMA64_BASE0,
362                 B43legacy_MMIO_DMA64_BASE1,
363                 B43legacy_MMIO_DMA64_BASE2,
364                 B43legacy_MMIO_DMA64_BASE3,
365                 B43legacy_MMIO_DMA64_BASE4,
366                 B43legacy_MMIO_DMA64_BASE5,
367         };
368         static const u16 map32[] = {
369                 B43legacy_MMIO_DMA32_BASE0,
370                 B43legacy_MMIO_DMA32_BASE1,
371                 B43legacy_MMIO_DMA32_BASE2,
372                 B43legacy_MMIO_DMA32_BASE3,
373                 B43legacy_MMIO_DMA32_BASE4,
374                 B43legacy_MMIO_DMA32_BASE5,
375         };
376
377         if (type == B43legacy_DMA_64BIT) {
378                 B43legacy_WARN_ON(!(controller_idx >= 0 &&
379                                   controller_idx < ARRAY_SIZE(map64)));
380                 return map64[controller_idx];
381         }
382         B43legacy_WARN_ON(!(controller_idx >= 0 &&
383                           controller_idx < ARRAY_SIZE(map32)));
384         return map32[controller_idx];
385 }
386
387 static inline
388 dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring,
389                           unsigned char *buf,
390                           size_t len,
391                           int tx)
392 {
393         dma_addr_t dmaaddr;
394
395         if (tx)
396                 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
397                                          buf, len,
398                                          DMA_TO_DEVICE);
399         else
400                 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
401                                          buf, len,
402                                          DMA_FROM_DEVICE);
403
404         return dmaaddr;
405 }
406
407 static inline
408 void unmap_descbuffer(struct b43legacy_dmaring *ring,
409                       dma_addr_t addr,
410                       size_t len,
411                       int tx)
412 {
413         if (tx)
414                 dma_unmap_single(ring->dev->dev->dma_dev,
415                                  addr, len,
416                                  DMA_TO_DEVICE);
417         else
418                 dma_unmap_single(ring->dev->dev->dma_dev,
419                                  addr, len,
420                                  DMA_FROM_DEVICE);
421 }
422
423 static inline
424 void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring,
425                              dma_addr_t addr,
426                              size_t len)
427 {
428         B43legacy_WARN_ON(ring->tx);
429
430         dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
431                                 addr, len, DMA_FROM_DEVICE);
432 }
433
434 static inline
435 void sync_descbuffer_for_device(struct b43legacy_dmaring *ring,
436                                 dma_addr_t addr,
437                                 size_t len)
438 {
439         B43legacy_WARN_ON(ring->tx);
440
441         dma_sync_single_for_device(ring->dev->dev->dma_dev,
442                                    addr, len, DMA_FROM_DEVICE);
443 }
444
445 static inline
446 void free_descriptor_buffer(struct b43legacy_dmaring *ring,
447                             struct b43legacy_dmadesc_meta *meta,
448                             int irq_context)
449 {
450         if (meta->skb) {
451                 if (irq_context)
452                         dev_kfree_skb_irq(meta->skb);
453                 else
454                         dev_kfree_skb(meta->skb);
455                 meta->skb = NULL;
456         }
457 }
458
459 static int alloc_ringmemory(struct b43legacy_dmaring *ring)
460 {
461         struct device *dma_dev = ring->dev->dev->dma_dev;
462
463         ring->descbase = dma_alloc_coherent(dma_dev, B43legacy_DMA_RINGMEMSIZE,
464                                             &(ring->dmabase), GFP_KERNEL);
465         if (!ring->descbase) {
466                 b43legacyerr(ring->dev->wl, "DMA ringmemory allocation"
467                              " failed\n");
468                 return -ENOMEM;
469         }
470         memset(ring->descbase, 0, B43legacy_DMA_RINGMEMSIZE);
471
472         return 0;
473 }
474
475 static void free_ringmemory(struct b43legacy_dmaring *ring)
476 {
477         struct device *dma_dev = ring->dev->dev->dma_dev;
478
479         dma_free_coherent(dma_dev, B43legacy_DMA_RINGMEMSIZE,
480                           ring->descbase, ring->dmabase);
481 }
482
483 /* Reset the RX DMA channel */
484 static int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev,
485                                             u16 mmio_base,
486                                             enum b43legacy_dmatype type)
487 {
488         int i;
489         u32 value;
490         u16 offset;
491
492         might_sleep();
493
494         offset = (type == B43legacy_DMA_64BIT) ?
495                  B43legacy_DMA64_RXCTL : B43legacy_DMA32_RXCTL;
496         b43legacy_write32(dev, mmio_base + offset, 0);
497         for (i = 0; i < 10; i++) {
498                 offset = (type == B43legacy_DMA_64BIT) ?
499                          B43legacy_DMA64_RXSTATUS : B43legacy_DMA32_RXSTATUS;
500                 value = b43legacy_read32(dev, mmio_base + offset);
501                 if (type == B43legacy_DMA_64BIT) {
502                         value &= B43legacy_DMA64_RXSTAT;
503                         if (value == B43legacy_DMA64_RXSTAT_DISABLED) {
504                                 i = -1;
505                                 break;
506                         }
507                 } else {
508                         value &= B43legacy_DMA32_RXSTATE;
509                         if (value == B43legacy_DMA32_RXSTAT_DISABLED) {
510                                 i = -1;
511                                 break;
512                         }
513                 }
514                 msleep(1);
515         }
516         if (i != -1) {
517                 b43legacyerr(dev->wl, "DMA RX reset timed out\n");
518                 return -ENODEV;
519         }
520
521         return 0;
522 }
523
524 /* Reset the RX DMA channel */
525 static int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev,
526                                             u16 mmio_base,
527                                             enum b43legacy_dmatype type)
528 {
529         int i;
530         u32 value;
531         u16 offset;
532
533         might_sleep();
534
535         for (i = 0; i < 10; i++) {
536                 offset = (type == B43legacy_DMA_64BIT) ?
537                          B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
538                 value = b43legacy_read32(dev, mmio_base + offset);
539                 if (type == B43legacy_DMA_64BIT) {
540                         value &= B43legacy_DMA64_TXSTAT;
541                         if (value == B43legacy_DMA64_TXSTAT_DISABLED ||
542                             value == B43legacy_DMA64_TXSTAT_IDLEWAIT ||
543                             value == B43legacy_DMA64_TXSTAT_STOPPED)
544                                 break;
545                 } else {
546                         value &= B43legacy_DMA32_TXSTATE;
547                         if (value == B43legacy_DMA32_TXSTAT_DISABLED ||
548                             value == B43legacy_DMA32_TXSTAT_IDLEWAIT ||
549                             value == B43legacy_DMA32_TXSTAT_STOPPED)
550                                 break;
551                 }
552                 msleep(1);
553         }
554         offset = (type == B43legacy_DMA_64BIT) ? B43legacy_DMA64_TXCTL :
555                                                  B43legacy_DMA32_TXCTL;
556         b43legacy_write32(dev, mmio_base + offset, 0);
557         for (i = 0; i < 10; i++) {
558                 offset = (type == B43legacy_DMA_64BIT) ?
559                          B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
560                 value = b43legacy_read32(dev, mmio_base + offset);
561                 if (type == B43legacy_DMA_64BIT) {
562                         value &= B43legacy_DMA64_TXSTAT;
563                         if (value == B43legacy_DMA64_TXSTAT_DISABLED) {
564                                 i = -1;
565                                 break;
566                         }
567                 } else {
568                         value &= B43legacy_DMA32_TXSTATE;
569                         if (value == B43legacy_DMA32_TXSTAT_DISABLED) {
570                                 i = -1;
571                                 break;
572                         }
573                 }
574                 msleep(1);
575         }
576         if (i != -1) {
577                 b43legacyerr(dev->wl, "DMA TX reset timed out\n");
578                 return -ENODEV;
579         }
580         /* ensure the reset is completed. */
581         msleep(1);
582
583         return 0;
584 }
585
586 /* Check if a DMA mapping address is invalid. */
587 static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring,
588                                          dma_addr_t addr,
589                                          size_t buffersize,
590                                          bool dma_to_device)
591 {
592         if (unlikely(dma_mapping_error(addr)))
593                 return 1;
594
595         switch (ring->type) {
596         case B43legacy_DMA_30BIT:
597                 if ((u64)addr + buffersize > (1ULL << 30))
598                         goto address_error;
599                 break;
600         case B43legacy_DMA_32BIT:
601                 if ((u64)addr + buffersize > (1ULL << 32))
602                         goto address_error;
603                 break;
604         case B43legacy_DMA_64BIT:
605                 /* Currently we can't have addresses beyond 64 bits in the kernel. */
606                 break;
607         }
608
609         /* The address is OK. */
610         return 0;
611
612 address_error:
613         /* We can't support this address. Unmap it again. */
614         unmap_descbuffer(ring, addr, buffersize, dma_to_device);
615
616         return 1;
617 }
618
619 static int setup_rx_descbuffer(struct b43legacy_dmaring *ring,
620                                struct b43legacy_dmadesc_generic *desc,
621                                struct b43legacy_dmadesc_meta *meta,
622                                gfp_t gfp_flags)
623 {
624         struct b43legacy_rxhdr_fw3 *rxhdr;
625         struct b43legacy_hwtxstatus *txstat;
626         dma_addr_t dmaaddr;
627         struct sk_buff *skb;
628
629         B43legacy_WARN_ON(ring->tx);
630
631         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
632         if (unlikely(!skb))
633                 return -ENOMEM;
634         dmaaddr = map_descbuffer(ring, skb->data,
635                                  ring->rx_buffersize, 0);
636         if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
637                 /* ugh. try to realloc in zone_dma */
638                 gfp_flags |= GFP_DMA;
639
640                 dev_kfree_skb_any(skb);
641
642                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
643                 if (unlikely(!skb))
644                         return -ENOMEM;
645                 dmaaddr = map_descbuffer(ring, skb->data,
646                                          ring->rx_buffersize, 0);
647         }
648
649         if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
650                 dev_kfree_skb_any(skb);
651                 return -EIO;
652         }
653
654         meta->skb = skb;
655         meta->dmaaddr = dmaaddr;
656         ring->ops->fill_descriptor(ring, desc, dmaaddr,
657                                    ring->rx_buffersize, 0, 0, 0);
658
659         rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data);
660         rxhdr->frame_len = 0;
661         txstat = (struct b43legacy_hwtxstatus *)(skb->data);
662         txstat->cookie = 0;
663
664         return 0;
665 }
666
667 /* Allocate the initial descbuffers.
668  * This is used for an RX ring only.
669  */
670 static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring)
671 {
672         int i;
673         int err = -ENOMEM;
674         struct b43legacy_dmadesc_generic *desc;
675         struct b43legacy_dmadesc_meta *meta;
676
677         for (i = 0; i < ring->nr_slots; i++) {
678                 desc = ring->ops->idx2desc(ring, i, &meta);
679
680                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
681                 if (err) {
682                         b43legacyerr(ring->dev->wl,
683                                "Failed to allocate initial descbuffers\n");
684                         goto err_unwind;
685                 }
686         }
687         mb(); /* all descbuffer setup before next line */
688         ring->used_slots = ring->nr_slots;
689         err = 0;
690 out:
691         return err;
692
693 err_unwind:
694         for (i--; i >= 0; i--) {
695                 desc = ring->ops->idx2desc(ring, i, &meta);
696
697                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
698                 dev_kfree_skb(meta->skb);
699         }
700         goto out;
701 }
702
703 /* Do initial setup of the DMA controller.
704  * Reset the controller, write the ring busaddress
705  * and switch the "enable" bit on.
706  */
707 static int dmacontroller_setup(struct b43legacy_dmaring *ring)
708 {
709         int err = 0;
710         u32 value;
711         u32 addrext;
712         u32 trans = ssb_dma_translation(ring->dev->dev);
713
714         if (ring->tx) {
715                 if (ring->type == B43legacy_DMA_64BIT) {
716                         u64 ringbase = (u64)(ring->dmabase);
717
718                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
719                                   >> SSB_DMA_TRANSLATION_SHIFT;
720                         value = B43legacy_DMA64_TXENABLE;
721                         value |= (addrext << B43legacy_DMA64_TXADDREXT_SHIFT)
722                                 & B43legacy_DMA64_TXADDREXT_MASK;
723                         b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
724                                             value);
725                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO,
726                                             (ringbase & 0xFFFFFFFF));
727                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI,
728                                             ((ringbase >> 32)
729                                             & ~SSB_DMA_TRANSLATION_MASK)
730                                             | trans);
731                 } else {
732                         u32 ringbase = (u32)(ring->dmabase);
733
734                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
735                                   >> SSB_DMA_TRANSLATION_SHIFT;
736                         value = B43legacy_DMA32_TXENABLE;
737                         value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT)
738                                 & B43legacy_DMA32_TXADDREXT_MASK;
739                         b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
740                                             value);
741                         b43legacy_dma_write(ring, B43legacy_DMA32_TXRING,
742                                             (ringbase &
743                                             ~SSB_DMA_TRANSLATION_MASK)
744                                             | trans);
745                 }
746         } else {
747                 err = alloc_initial_descbuffers(ring);
748                 if (err)
749                         goto out;
750                 if (ring->type == B43legacy_DMA_64BIT) {
751                         u64 ringbase = (u64)(ring->dmabase);
752
753                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
754                                   >> SSB_DMA_TRANSLATION_SHIFT;
755                         value = (ring->frameoffset <<
756                                  B43legacy_DMA64_RXFROFF_SHIFT);
757                         value |= B43legacy_DMA64_RXENABLE;
758                         value |= (addrext << B43legacy_DMA64_RXADDREXT_SHIFT)
759                                 & B43legacy_DMA64_RXADDREXT_MASK;
760                         b43legacy_dma_write(ring, B43legacy_DMA64_RXCTL,
761                                             value);
762                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO,
763                                             (ringbase & 0xFFFFFFFF));
764                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI,
765                                             ((ringbase >> 32) &
766                                             ~SSB_DMA_TRANSLATION_MASK) |
767                                             trans);
768                         b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
769                                             200);
770                 } else {
771                         u32 ringbase = (u32)(ring->dmabase);
772
773                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
774                                   >> SSB_DMA_TRANSLATION_SHIFT;
775                         value = (ring->frameoffset <<
776                                  B43legacy_DMA32_RXFROFF_SHIFT);
777                         value |= B43legacy_DMA32_RXENABLE;
778                         value |= (addrext <<
779                                  B43legacy_DMA32_RXADDREXT_SHIFT)
780                                  & B43legacy_DMA32_RXADDREXT_MASK;
781                         b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL,
782                                             value);
783                         b43legacy_dma_write(ring, B43legacy_DMA32_RXRING,
784                                             (ringbase &
785                                             ~SSB_DMA_TRANSLATION_MASK)
786                                             | trans);
787                         b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
788                                             200);
789                 }
790         }
791
792 out:
793         return err;
794 }
795
796 /* Shutdown the DMA controller. */
797 static void dmacontroller_cleanup(struct b43legacy_dmaring *ring)
798 {
799         if (ring->tx) {
800                 b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
801                                                  ring->type);
802                 if (ring->type == B43legacy_DMA_64BIT) {
803                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO, 0);
804                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI, 0);
805                 } else
806                         b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0);
807         } else {
808                 b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
809                                                  ring->type);
810                 if (ring->type == B43legacy_DMA_64BIT) {
811                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO, 0);
812                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI, 0);
813                 } else
814                         b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0);
815         }
816 }
817
818 static void free_all_descbuffers(struct b43legacy_dmaring *ring)
819 {
820         struct b43legacy_dmadesc_generic *desc;
821         struct b43legacy_dmadesc_meta *meta;
822         int i;
823
824         if (!ring->used_slots)
825                 return;
826         for (i = 0; i < ring->nr_slots; i++) {
827                 desc = ring->ops->idx2desc(ring, i, &meta);
828
829                 if (!meta->skb) {
830                         B43legacy_WARN_ON(!ring->tx);
831                         continue;
832                 }
833                 if (ring->tx)
834                         unmap_descbuffer(ring, meta->dmaaddr,
835                                          meta->skb->len, 1);
836                 else
837                         unmap_descbuffer(ring, meta->dmaaddr,
838                                          ring->rx_buffersize, 0);
839                 free_descriptor_buffer(ring, meta, 0);
840         }
841 }
842
843 static u64 supported_dma_mask(struct b43legacy_wldev *dev)
844 {
845         u32 tmp;
846         u16 mmio_base;
847
848         tmp = b43legacy_read32(dev, SSB_TMSHIGH);
849         if (tmp & SSB_TMSHIGH_DMA64)
850                 return DMA_64BIT_MASK;
851         mmio_base = b43legacy_dmacontroller_base(0, 0);
852         b43legacy_write32(dev,
853                         mmio_base + B43legacy_DMA32_TXCTL,
854                         B43legacy_DMA32_TXADDREXT_MASK);
855         tmp = b43legacy_read32(dev, mmio_base +
856                                B43legacy_DMA32_TXCTL);
857         if (tmp & B43legacy_DMA32_TXADDREXT_MASK)
858                 return DMA_32BIT_MASK;
859
860         return DMA_30BIT_MASK;
861 }
862
863 /* Main initialization function. */
864 static
865 struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
866                                                   int controller_index,
867                                                   int for_tx,
868                                                   enum b43legacy_dmatype type)
869 {
870         struct b43legacy_dmaring *ring;
871         int err;
872         int nr_slots;
873         dma_addr_t dma_test;
874
875         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
876         if (!ring)
877                 goto out;
878         ring->type = type;
879
880         nr_slots = B43legacy_RXRING_SLOTS;
881         if (for_tx)
882                 nr_slots = B43legacy_TXRING_SLOTS;
883
884         ring->meta = kcalloc(nr_slots, sizeof(struct b43legacy_dmadesc_meta),
885                              GFP_KERNEL);
886         if (!ring->meta)
887                 goto err_kfree_ring;
888         if (for_tx) {
889                 ring->txhdr_cache = kcalloc(nr_slots,
890                                         sizeof(struct b43legacy_txhdr_fw3),
891                                         GFP_KERNEL);
892                 if (!ring->txhdr_cache)
893                         goto err_kfree_meta;
894
895                 /* test for ability to dma to txhdr_cache */
896                 dma_test = dma_map_single(dev->dev->dma_dev, ring->txhdr_cache,
897                                           sizeof(struct b43legacy_txhdr_fw3),
898                                           DMA_TO_DEVICE);
899
900                 if (b43legacy_dma_mapping_error(ring, dma_test,
901                                         sizeof(struct b43legacy_txhdr_fw3), 1)) {
902                         /* ugh realloc */
903                         kfree(ring->txhdr_cache);
904                         ring->txhdr_cache = kcalloc(nr_slots,
905                                         sizeof(struct b43legacy_txhdr_fw3),
906                                         GFP_KERNEL | GFP_DMA);
907                         if (!ring->txhdr_cache)
908                                 goto err_kfree_meta;
909
910                         dma_test = dma_map_single(dev->dev->dma_dev,
911                                         ring->txhdr_cache,
912                                         sizeof(struct b43legacy_txhdr_fw3),
913                                         DMA_TO_DEVICE);
914
915                         if (b43legacy_dma_mapping_error(ring, dma_test,
916                                         sizeof(struct b43legacy_txhdr_fw3), 1))
917                                 goto err_kfree_txhdr_cache;
918                 }
919
920                 dma_unmap_single(dev->dev->dma_dev,
921                                  dma_test, sizeof(struct b43legacy_txhdr_fw3),
922                                  DMA_TO_DEVICE);
923         }
924
925         ring->dev = dev;
926         ring->nr_slots = nr_slots;
927         ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index);
928         ring->index = controller_index;
929         if (type == B43legacy_DMA_64BIT)
930                 ring->ops = &dma64_ops;
931         else
932                 ring->ops = &dma32_ops;
933         if (for_tx) {
934                 ring->tx = 1;
935                 ring->current_slot = -1;
936         } else {
937                 if (ring->index == 0) {
938                         ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE;
939                         ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET;
940                 } else if (ring->index == 3) {
941                         ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE;
942                         ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET;
943                 } else
944                         B43legacy_WARN_ON(1);
945         }
946         spin_lock_init(&ring->lock);
947 #ifdef CONFIG_B43LEGACY_DEBUG
948         ring->last_injected_overflow = jiffies;
949 #endif
950
951         err = alloc_ringmemory(ring);
952         if (err)
953                 goto err_kfree_txhdr_cache;
954         err = dmacontroller_setup(ring);
955         if (err)
956                 goto err_free_ringmemory;
957
958 out:
959         return ring;
960
961 err_free_ringmemory:
962         free_ringmemory(ring);
963 err_kfree_txhdr_cache:
964         kfree(ring->txhdr_cache);
965 err_kfree_meta:
966         kfree(ring->meta);
967 err_kfree_ring:
968         kfree(ring);
969         ring = NULL;
970         goto out;
971 }
972
973 /* Main cleanup function. */
974 static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring)
975 {
976         if (!ring)
977                 return;
978
979         b43legacydbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots:"
980                      " %d/%d\n", (unsigned int)(ring->type), ring->mmio_base,
981                      (ring->tx) ? "TX" : "RX", ring->max_used_slots,
982                      ring->nr_slots);
983         /* Device IRQs are disabled prior entering this function,
984          * so no need to take care of concurrency with rx handler stuff.
985          */
986         dmacontroller_cleanup(ring);
987         free_all_descbuffers(ring);
988         free_ringmemory(ring);
989
990         kfree(ring->txhdr_cache);
991         kfree(ring->meta);
992         kfree(ring);
993 }
994
995 void b43legacy_dma_free(struct b43legacy_wldev *dev)
996 {
997         struct b43legacy_dma *dma;
998
999         if (b43legacy_using_pio(dev))
1000                 return;
1001         dma = &dev->dma;
1002
1003         b43legacy_destroy_dmaring(dma->rx_ring3);
1004         dma->rx_ring3 = NULL;
1005         b43legacy_destroy_dmaring(dma->rx_ring0);
1006         dma->rx_ring0 = NULL;
1007
1008         b43legacy_destroy_dmaring(dma->tx_ring5);
1009         dma->tx_ring5 = NULL;
1010         b43legacy_destroy_dmaring(dma->tx_ring4);
1011         dma->tx_ring4 = NULL;
1012         b43legacy_destroy_dmaring(dma->tx_ring3);
1013         dma->tx_ring3 = NULL;
1014         b43legacy_destroy_dmaring(dma->tx_ring2);
1015         dma->tx_ring2 = NULL;
1016         b43legacy_destroy_dmaring(dma->tx_ring1);
1017         dma->tx_ring1 = NULL;
1018         b43legacy_destroy_dmaring(dma->tx_ring0);
1019         dma->tx_ring0 = NULL;
1020 }
1021
1022 int b43legacy_dma_init(struct b43legacy_wldev *dev)
1023 {
1024         struct b43legacy_dma *dma = &dev->dma;
1025         struct b43legacy_dmaring *ring;
1026         int err;
1027         u64 dmamask;
1028         enum b43legacy_dmatype type;
1029
1030         dmamask = supported_dma_mask(dev);
1031         switch (dmamask) {
1032         default:
1033                 B43legacy_WARN_ON(1);
1034         case DMA_30BIT_MASK:
1035                 type = B43legacy_DMA_30BIT;
1036                 break;
1037         case DMA_32BIT_MASK:
1038                 type = B43legacy_DMA_32BIT;
1039                 break;
1040         case DMA_64BIT_MASK:
1041                 type = B43legacy_DMA_64BIT;
1042                 break;
1043         }
1044
1045         err = ssb_dma_set_mask(dev->dev, dmamask);
1046         if (err) {
1047 #ifdef CONFIG_B43LEGACY_PIO
1048                 b43legacywarn(dev->wl, "DMA for this device not supported. "
1049                         "Falling back to PIO\n");
1050                 dev->__using_pio = 1;
1051                 return -EAGAIN;
1052 #else
1053                 b43legacyerr(dev->wl, "DMA for this device not supported and "
1054                        "no PIO support compiled in\n");
1055                 return -EOPNOTSUPP;
1056 #endif
1057         }
1058
1059         err = -ENOMEM;
1060         /* setup TX DMA channels. */
1061         ring = b43legacy_setup_dmaring(dev, 0, 1, type);
1062         if (!ring)
1063                 goto out;
1064         dma->tx_ring0 = ring;
1065
1066         ring = b43legacy_setup_dmaring(dev, 1, 1, type);
1067         if (!ring)
1068                 goto err_destroy_tx0;
1069         dma->tx_ring1 = ring;
1070
1071         ring = b43legacy_setup_dmaring(dev, 2, 1, type);
1072         if (!ring)
1073                 goto err_destroy_tx1;
1074         dma->tx_ring2 = ring;
1075
1076         ring = b43legacy_setup_dmaring(dev, 3, 1, type);
1077         if (!ring)
1078                 goto err_destroy_tx2;
1079         dma->tx_ring3 = ring;
1080
1081         ring = b43legacy_setup_dmaring(dev, 4, 1, type);
1082         if (!ring)
1083                 goto err_destroy_tx3;
1084         dma->tx_ring4 = ring;
1085
1086         ring = b43legacy_setup_dmaring(dev, 5, 1, type);
1087         if (!ring)
1088                 goto err_destroy_tx4;
1089         dma->tx_ring5 = ring;
1090
1091         /* setup RX DMA channels. */
1092         ring = b43legacy_setup_dmaring(dev, 0, 0, type);
1093         if (!ring)
1094                 goto err_destroy_tx5;
1095         dma->rx_ring0 = ring;
1096
1097         if (dev->dev->id.revision < 5) {
1098                 ring = b43legacy_setup_dmaring(dev, 3, 0, type);
1099                 if (!ring)
1100                         goto err_destroy_rx0;
1101                 dma->rx_ring3 = ring;
1102         }
1103
1104         b43legacydbg(dev->wl, "%u-bit DMA initialized\n", (unsigned int)type);
1105         err = 0;
1106 out:
1107         return err;
1108
1109 err_destroy_rx0:
1110         b43legacy_destroy_dmaring(dma->rx_ring0);
1111         dma->rx_ring0 = NULL;
1112 err_destroy_tx5:
1113         b43legacy_destroy_dmaring(dma->tx_ring5);
1114         dma->tx_ring5 = NULL;
1115 err_destroy_tx4:
1116         b43legacy_destroy_dmaring(dma->tx_ring4);
1117         dma->tx_ring4 = NULL;
1118 err_destroy_tx3:
1119         b43legacy_destroy_dmaring(dma->tx_ring3);
1120         dma->tx_ring3 = NULL;
1121 err_destroy_tx2:
1122         b43legacy_destroy_dmaring(dma->tx_ring2);
1123         dma->tx_ring2 = NULL;
1124 err_destroy_tx1:
1125         b43legacy_destroy_dmaring(dma->tx_ring1);
1126         dma->tx_ring1 = NULL;
1127 err_destroy_tx0:
1128         b43legacy_destroy_dmaring(dma->tx_ring0);
1129         dma->tx_ring0 = NULL;
1130         goto out;
1131 }
1132
1133 /* Generate a cookie for the TX header. */
1134 static u16 generate_cookie(struct b43legacy_dmaring *ring,
1135                            int slot)
1136 {
1137         u16 cookie = 0x1000;
1138
1139         /* Use the upper 4 bits of the cookie as
1140          * DMA controller ID and store the slot number
1141          * in the lower 12 bits.
1142          * Note that the cookie must never be 0, as this
1143          * is a special value used in RX path.
1144          */
1145         switch (ring->index) {
1146         case 0:
1147                 cookie = 0xA000;
1148                 break;
1149         case 1:
1150                 cookie = 0xB000;
1151                 break;
1152         case 2:
1153                 cookie = 0xC000;
1154                 break;
1155         case 3:
1156                 cookie = 0xD000;
1157                 break;
1158         case 4:
1159                 cookie = 0xE000;
1160                 break;
1161         case 5:
1162                 cookie = 0xF000;
1163                 break;
1164         }
1165         B43legacy_WARN_ON(!(((u16)slot & 0xF000) == 0x0000));
1166         cookie |= (u16)slot;
1167
1168         return cookie;
1169 }
1170
1171 /* Inspect a cookie and find out to which controller/slot it belongs. */
1172 static
1173 struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev,
1174                                       u16 cookie, int *slot)
1175 {
1176         struct b43legacy_dma *dma = &dev->dma;
1177         struct b43legacy_dmaring *ring = NULL;
1178
1179         switch (cookie & 0xF000) {
1180         case 0xA000:
1181                 ring = dma->tx_ring0;
1182                 break;
1183         case 0xB000:
1184                 ring = dma->tx_ring1;
1185                 break;
1186         case 0xC000:
1187                 ring = dma->tx_ring2;
1188                 break;
1189         case 0xD000:
1190                 ring = dma->tx_ring3;
1191                 break;
1192         case 0xE000:
1193                 ring = dma->tx_ring4;
1194                 break;
1195         case 0xF000:
1196                 ring = dma->tx_ring5;
1197                 break;
1198         default:
1199                 B43legacy_WARN_ON(1);
1200         }
1201         *slot = (cookie & 0x0FFF);
1202         B43legacy_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1203
1204         return ring;
1205 }
1206
1207 static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1208                             struct sk_buff *skb)
1209 {
1210         const struct b43legacy_dma_ops *ops = ring->ops;
1211         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1212         u8 *header;
1213         int slot, old_top_slot, old_used_slots;
1214         int err;
1215         struct b43legacy_dmadesc_generic *desc;
1216         struct b43legacy_dmadesc_meta *meta;
1217         struct b43legacy_dmadesc_meta *meta_hdr;
1218         struct sk_buff *bounce_skb;
1219
1220 #define SLOTS_PER_PACKET  2
1221         B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0);
1222
1223         old_top_slot = ring->current_slot;
1224         old_used_slots = ring->used_slots;
1225
1226         /* Get a slot for the header. */
1227         slot = request_slot(ring);
1228         desc = ops->idx2desc(ring, slot, &meta_hdr);
1229         memset(meta_hdr, 0, sizeof(*meta_hdr));
1230
1231         header = &(ring->txhdr_cache[slot * sizeof(
1232                                struct b43legacy_txhdr_fw3)]);
1233         err = b43legacy_generate_txhdr(ring->dev, header,
1234                                  skb->data, skb->len, info,
1235                                  generate_cookie(ring, slot));
1236         if (unlikely(err)) {
1237                 ring->current_slot = old_top_slot;
1238                 ring->used_slots = old_used_slots;
1239                 return err;
1240         }
1241
1242         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1243                                            sizeof(struct b43legacy_txhdr_fw3), 1);
1244         if (b43legacy_dma_mapping_error(ring, meta_hdr->dmaaddr,
1245                                         sizeof(struct b43legacy_txhdr_fw3), 1)) {
1246                 ring->current_slot = old_top_slot;
1247                 ring->used_slots = old_used_slots;
1248                 return -EIO;
1249         }
1250         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1251                              sizeof(struct b43legacy_txhdr_fw3), 1, 0, 0);
1252
1253         /* Get a slot for the payload. */
1254         slot = request_slot(ring);
1255         desc = ops->idx2desc(ring, slot, &meta);
1256         memset(meta, 0, sizeof(*meta));
1257
1258         meta->skb = skb;
1259         meta->is_last_fragment = 1;
1260
1261         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1262         /* create a bounce buffer in zone_dma on mapping failure. */
1263         if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1264                 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1265                 if (!bounce_skb) {
1266                         ring->current_slot = old_top_slot;
1267                         ring->used_slots = old_used_slots;
1268                         err = -ENOMEM;
1269                         goto out_unmap_hdr;
1270                 }
1271
1272                 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1273                 dev_kfree_skb_any(skb);
1274                 skb = bounce_skb;
1275                 meta->skb = skb;
1276                 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1277                 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1278                         ring->current_slot = old_top_slot;
1279                         ring->used_slots = old_used_slots;
1280                         err = -EIO;
1281                         goto out_free_bounce;
1282                 }
1283         }
1284
1285         ops->fill_descriptor(ring, desc, meta->dmaaddr,
1286                              skb->len, 0, 1, 1);
1287
1288         wmb();  /* previous stuff MUST be done */
1289         /* Now transfer the whole frame. */
1290         ops->poke_tx(ring, next_slot(ring, slot));
1291         return 0;
1292
1293 out_free_bounce:
1294         dev_kfree_skb_any(skb);
1295 out_unmap_hdr:
1296         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1297                          sizeof(struct b43legacy_txhdr_fw3), 1);
1298         return err;
1299 }
1300
1301 static inline
1302 int should_inject_overflow(struct b43legacy_dmaring *ring)
1303 {
1304 #ifdef CONFIG_B43LEGACY_DEBUG
1305         if (unlikely(b43legacy_debug(ring->dev,
1306                                      B43legacy_DBG_DMAOVERFLOW))) {
1307                 /* Check if we should inject another ringbuffer overflow
1308                  * to test handling of this situation in the stack. */
1309                 unsigned long next_overflow;
1310
1311                 next_overflow = ring->last_injected_overflow + HZ;
1312                 if (time_after(jiffies, next_overflow)) {
1313                         ring->last_injected_overflow = jiffies;
1314                         b43legacydbg(ring->dev->wl,
1315                                "Injecting TX ring overflow on "
1316                                "DMA controller %d\n", ring->index);
1317                         return 1;
1318                 }
1319         }
1320 #endif /* CONFIG_B43LEGACY_DEBUG */
1321         return 0;
1322 }
1323
1324 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1325                      struct sk_buff *skb)
1326 {
1327         struct b43legacy_dmaring *ring;
1328         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1329         int err = 0;
1330         unsigned long flags;
1331
1332         ring = priority_to_txring(dev, info->queue);
1333         spin_lock_irqsave(&ring->lock, flags);
1334         B43legacy_WARN_ON(!ring->tx);
1335         if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1336                 b43legacywarn(dev->wl, "DMA queue overflow\n");
1337                 err = -ENOSPC;
1338                 goto out_unlock;
1339         }
1340         /* Check if the queue was stopped in mac80211,
1341          * but we got called nevertheless.
1342          * That would be a mac80211 bug. */
1343         B43legacy_BUG_ON(ring->stopped);
1344
1345         err = dma_tx_fragment(ring, skb);
1346         if (unlikely(err == -ENOKEY)) {
1347                 /* Drop this packet, as we don't have the encryption key
1348                  * anymore and must not transmit it unencrypted. */
1349                 dev_kfree_skb_any(skb);
1350                 err = 0;
1351                 goto out_unlock;
1352         }
1353         if (unlikely(err)) {
1354                 b43legacyerr(dev->wl, "DMA tx mapping failure\n");
1355                 goto out_unlock;
1356         }
1357         ring->nr_tx_packets++;
1358         if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1359             should_inject_overflow(ring)) {
1360                 /* This TX ring is full. */
1361                 ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
1362                 ring->stopped = 1;
1363                 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1364                         b43legacydbg(dev->wl, "Stopped TX ring %d\n",
1365                                ring->index);
1366         }
1367 out_unlock:
1368         spin_unlock_irqrestore(&ring->lock, flags);
1369
1370         return err;
1371 }
1372
1373 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1374                                  const struct b43legacy_txstatus *status)
1375 {
1376         const struct b43legacy_dma_ops *ops;
1377         struct b43legacy_dmaring *ring;
1378         struct b43legacy_dmadesc_generic *desc;
1379         struct b43legacy_dmadesc_meta *meta;
1380         int slot;
1381
1382         ring = parse_cookie(dev, status->cookie, &slot);
1383         if (unlikely(!ring))
1384                 return;
1385         B43legacy_WARN_ON(!irqs_disabled());
1386         spin_lock(&ring->lock);
1387
1388         B43legacy_WARN_ON(!ring->tx);
1389         ops = ring->ops;
1390         while (1) {
1391                 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1392                 desc = ops->idx2desc(ring, slot, &meta);
1393
1394                 if (meta->skb)
1395                         unmap_descbuffer(ring, meta->dmaaddr,
1396                                          meta->skb->len, 1);
1397                 else
1398                         unmap_descbuffer(ring, meta->dmaaddr,
1399                                          sizeof(struct b43legacy_txhdr_fw3),
1400                                          1);
1401
1402                 if (meta->is_last_fragment) {
1403                         struct ieee80211_tx_info *info;
1404                         BUG_ON(!meta->skb);
1405                         info = IEEE80211_SKB_CB(meta->skb);
1406                         /* Call back to inform the ieee80211 subsystem about the
1407                          * status of the transmission.
1408                          * Some fields of txstat are already filled in dma_tx().
1409                          */
1410
1411                         memset(&info->status, 0, sizeof(info->status));
1412
1413                         if (status->acked) {
1414                                 info->flags |= IEEE80211_TX_STAT_ACK;
1415                         } else {
1416                                 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
1417                                          info->status.excessive_retries = 1;
1418                         }
1419                         if (status->frame_count == 0) {
1420                                 /* The frame was not transmitted at all. */
1421                                 info->status.retry_count = 0;
1422                         } else
1423                                 info->status.retry_count = status->frame_count
1424                                                            - 1;
1425                         ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
1426                         /* skb is freed by ieee80211_tx_status_irqsafe() */
1427                         meta->skb = NULL;
1428                 } else {
1429                         /* No need to call free_descriptor_buffer here, as
1430                          * this is only the txhdr, which is not allocated.
1431                          */
1432                         B43legacy_WARN_ON(meta->skb != NULL);
1433                 }
1434
1435                 /* Everything unmapped and free'd. So it's not used anymore. */
1436                 ring->used_slots--;
1437
1438                 if (meta->is_last_fragment)
1439                         break;
1440                 slot = next_slot(ring, slot);
1441         }
1442         dev->stats.last_tx = jiffies;
1443         if (ring->stopped) {
1444                 B43legacy_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1445                 ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
1446                 ring->stopped = 0;
1447                 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1448                         b43legacydbg(dev->wl, "Woke up TX ring %d\n",
1449                                ring->index);
1450         }
1451
1452         spin_unlock(&ring->lock);
1453 }
1454
1455 void b43legacy_dma_get_tx_stats(struct b43legacy_wldev *dev,
1456                               struct ieee80211_tx_queue_stats *stats)
1457 {
1458         const int nr_queues = dev->wl->hw->queues;
1459         struct b43legacy_dmaring *ring;
1460         unsigned long flags;
1461         int i;
1462
1463         for (i = 0; i < nr_queues; i++) {
1464                 ring = priority_to_txring(dev, i);
1465
1466                 spin_lock_irqsave(&ring->lock, flags);
1467                 stats[i].len = ring->used_slots / SLOTS_PER_PACKET;
1468                 stats[i].limit = ring->nr_slots / SLOTS_PER_PACKET;
1469                 stats[i].count = ring->nr_tx_packets;
1470                 spin_unlock_irqrestore(&ring->lock, flags);
1471         }
1472 }
1473
1474 static void dma_rx(struct b43legacy_dmaring *ring,
1475                    int *slot)
1476 {
1477         const struct b43legacy_dma_ops *ops = ring->ops;
1478         struct b43legacy_dmadesc_generic *desc;
1479         struct b43legacy_dmadesc_meta *meta;
1480         struct b43legacy_rxhdr_fw3 *rxhdr;
1481         struct sk_buff *skb;
1482         u16 len;
1483         int err;
1484         dma_addr_t dmaaddr;
1485
1486         desc = ops->idx2desc(ring, *slot, &meta);
1487
1488         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1489         skb = meta->skb;
1490
1491         if (ring->index == 3) {
1492                 /* We received an xmit status. */
1493                 struct b43legacy_hwtxstatus *hw =
1494                                 (struct b43legacy_hwtxstatus *)skb->data;
1495                 int i = 0;
1496
1497                 while (hw->cookie == 0) {
1498                         if (i > 100)
1499                                 break;
1500                         i++;
1501                         udelay(2);
1502                         barrier();
1503                 }
1504                 b43legacy_handle_hwtxstatus(ring->dev, hw);
1505                 /* recycle the descriptor buffer. */
1506                 sync_descbuffer_for_device(ring, meta->dmaaddr,
1507                                            ring->rx_buffersize);
1508
1509                 return;
1510         }
1511         rxhdr = (struct b43legacy_rxhdr_fw3 *)skb->data;
1512         len = le16_to_cpu(rxhdr->frame_len);
1513         if (len == 0) {
1514                 int i = 0;
1515
1516                 do {
1517                         udelay(2);
1518                         barrier();
1519                         len = le16_to_cpu(rxhdr->frame_len);
1520                 } while (len == 0 && i++ < 5);
1521                 if (unlikely(len == 0)) {
1522                         /* recycle the descriptor buffer. */
1523                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1524                                                    ring->rx_buffersize);
1525                         goto drop;
1526                 }
1527         }
1528         if (unlikely(len > ring->rx_buffersize)) {
1529                 /* The data did not fit into one descriptor buffer
1530                  * and is split over multiple buffers.
1531                  * This should never happen, as we try to allocate buffers
1532                  * big enough. So simply ignore this packet.
1533                  */
1534                 int cnt = 0;
1535                 s32 tmp = len;
1536
1537                 while (1) {
1538                         desc = ops->idx2desc(ring, *slot, &meta);
1539                         /* recycle the descriptor buffer. */
1540                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1541                                                    ring->rx_buffersize);
1542                         *slot = next_slot(ring, *slot);
1543                         cnt++;
1544                         tmp -= ring->rx_buffersize;
1545                         if (tmp <= 0)
1546                                 break;
1547                 }
1548                 b43legacyerr(ring->dev->wl, "DMA RX buffer too small "
1549                        "(len: %u, buffer: %u, nr-dropped: %d)\n",
1550                        len, ring->rx_buffersize, cnt);
1551                 goto drop;
1552         }
1553
1554         dmaaddr = meta->dmaaddr;
1555         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1556         if (unlikely(err)) {
1557                 b43legacydbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer()"
1558                              " failed\n");
1559                 sync_descbuffer_for_device(ring, dmaaddr,
1560                                            ring->rx_buffersize);
1561                 goto drop;
1562         }
1563
1564         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1565         skb_put(skb, len + ring->frameoffset);
1566         skb_pull(skb, ring->frameoffset);
1567
1568         b43legacy_rx(ring->dev, skb, rxhdr);
1569 drop:
1570         return;
1571 }
1572
1573 void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
1574 {
1575         const struct b43legacy_dma_ops *ops = ring->ops;
1576         int slot;
1577         int current_slot;
1578         int used_slots = 0;
1579
1580         B43legacy_WARN_ON(ring->tx);
1581         current_slot = ops->get_current_rxslot(ring);
1582         B43legacy_WARN_ON(!(current_slot >= 0 && current_slot <
1583                            ring->nr_slots));
1584
1585         slot = ring->current_slot;
1586         for (; slot != current_slot; slot = next_slot(ring, slot)) {
1587                 dma_rx(ring, &slot);
1588                 update_max_used_slots(ring, ++used_slots);
1589         }
1590         ops->set_current_rxslot(ring, slot);
1591         ring->current_slot = slot;
1592 }
1593
1594 static void b43legacy_dma_tx_suspend_ring(struct b43legacy_dmaring *ring)
1595 {
1596         unsigned long flags;
1597
1598         spin_lock_irqsave(&ring->lock, flags);
1599         B43legacy_WARN_ON(!ring->tx);
1600         ring->ops->tx_suspend(ring);
1601         spin_unlock_irqrestore(&ring->lock, flags);
1602 }
1603
1604 static void b43legacy_dma_tx_resume_ring(struct b43legacy_dmaring *ring)
1605 {
1606         unsigned long flags;
1607
1608         spin_lock_irqsave(&ring->lock, flags);
1609         B43legacy_WARN_ON(!ring->tx);
1610         ring->ops->tx_resume(ring);
1611         spin_unlock_irqrestore(&ring->lock, flags);
1612 }
1613
1614 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
1615 {
1616         b43legacy_power_saving_ctl_bits(dev, -1, 1);
1617         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring0);
1618         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring1);
1619         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring2);
1620         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring3);
1621         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring4);
1622         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring5);
1623 }
1624
1625 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
1626 {
1627         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring5);
1628         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring4);
1629         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring3);
1630         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring2);
1631         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring1);
1632         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring0);
1633         b43legacy_power_saving_ctl_bits(dev, -1, -1);
1634 }