dma-mapping: replace all DMA_64BIT_MASK macro with DMA_BIT_MASK(64)
[linux-2.6.git] / drivers / net / wireless / b43legacy / dma.c
1 /*
2
3   Broadcom B43legacy wireless driver
4
5   DMA ringbuffer and descriptor allocation/management
6
7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8
9   Some code in this file is derived from the b44.c driver
10   Copyright (C) 2002 David S. Miller
11   Copyright (C) Pekka Pietikainen
12
13   This program is free software; you can redistribute it and/or modify
14   it under the terms of the GNU General Public License as published by
15   the Free Software Foundation; either version 2 of the License, or
16   (at your option) any later version.
17
18   This program is distributed in the hope that it will be useful,
19   but WITHOUT ANY WARRANTY; without even the implied warranty of
20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21   GNU General Public License for more details.
22
23   You should have received a copy of the GNU General Public License
24   along with this program; see the file COPYING.  If not, write to
25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26   Boston, MA 02110-1301, USA.
27
28 */
29
30 #include "b43legacy.h"
31 #include "dma.h"
32 #include "main.h"
33 #include "debugfs.h"
34 #include "xmit.h"
35
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <net/dst.h>
41
42 /* 32bit DMA ops. */
43 static
44 struct b43legacy_dmadesc_generic *op32_idx2desc(
45                                         struct b43legacy_dmaring *ring,
46                                         int slot,
47                                         struct b43legacy_dmadesc_meta **meta)
48 {
49         struct b43legacy_dmadesc32 *desc;
50
51         *meta = &(ring->meta[slot]);
52         desc = ring->descbase;
53         desc = &(desc[slot]);
54
55         return (struct b43legacy_dmadesc_generic *)desc;
56 }
57
58 static void op32_fill_descriptor(struct b43legacy_dmaring *ring,
59                                  struct b43legacy_dmadesc_generic *desc,
60                                  dma_addr_t dmaaddr, u16 bufsize,
61                                  int start, int end, int irq)
62 {
63         struct b43legacy_dmadesc32 *descbase = ring->descbase;
64         int slot;
65         u32 ctl;
66         u32 addr;
67         u32 addrext;
68
69         slot = (int)(&(desc->dma32) - descbase);
70         B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
71
72         addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
73         addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
74                    >> SSB_DMA_TRANSLATION_SHIFT;
75         addr |= ssb_dma_translation(ring->dev->dev);
76         ctl = (bufsize - ring->frameoffset)
77               & B43legacy_DMA32_DCTL_BYTECNT;
78         if (slot == ring->nr_slots - 1)
79                 ctl |= B43legacy_DMA32_DCTL_DTABLEEND;
80         if (start)
81                 ctl |= B43legacy_DMA32_DCTL_FRAMESTART;
82         if (end)
83                 ctl |= B43legacy_DMA32_DCTL_FRAMEEND;
84         if (irq)
85                 ctl |= B43legacy_DMA32_DCTL_IRQ;
86         ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT)
87                & B43legacy_DMA32_DCTL_ADDREXT_MASK;
88
89         desc->dma32.control = cpu_to_le32(ctl);
90         desc->dma32.address = cpu_to_le32(addr);
91 }
92
93 static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot)
94 {
95         b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX,
96                             (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
97 }
98
99 static void op32_tx_suspend(struct b43legacy_dmaring *ring)
100 {
101         b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
102                             b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
103                             | B43legacy_DMA32_TXSUSPEND);
104 }
105
106 static void op32_tx_resume(struct b43legacy_dmaring *ring)
107 {
108         b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
109                             b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
110                             & ~B43legacy_DMA32_TXSUSPEND);
111 }
112
113 static int op32_get_current_rxslot(struct b43legacy_dmaring *ring)
114 {
115         u32 val;
116
117         val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS);
118         val &= B43legacy_DMA32_RXDPTR;
119
120         return (val / sizeof(struct b43legacy_dmadesc32));
121 }
122
123 static void op32_set_current_rxslot(struct b43legacy_dmaring *ring,
124                                     int slot)
125 {
126         b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
127                             (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
128 }
129
130 static const struct b43legacy_dma_ops dma32_ops = {
131         .idx2desc               = op32_idx2desc,
132         .fill_descriptor        = op32_fill_descriptor,
133         .poke_tx                = op32_poke_tx,
134         .tx_suspend             = op32_tx_suspend,
135         .tx_resume              = op32_tx_resume,
136         .get_current_rxslot     = op32_get_current_rxslot,
137         .set_current_rxslot     = op32_set_current_rxslot,
138 };
139
140 /* 64bit DMA ops. */
141 static
142 struct b43legacy_dmadesc_generic *op64_idx2desc(
143                                         struct b43legacy_dmaring *ring,
144                                         int slot,
145                                         struct b43legacy_dmadesc_meta
146                                         **meta)
147 {
148         struct b43legacy_dmadesc64 *desc;
149
150         *meta = &(ring->meta[slot]);
151         desc = ring->descbase;
152         desc = &(desc[slot]);
153
154         return (struct b43legacy_dmadesc_generic *)desc;
155 }
156
157 static void op64_fill_descriptor(struct b43legacy_dmaring *ring,
158                                  struct b43legacy_dmadesc_generic *desc,
159                                  dma_addr_t dmaaddr, u16 bufsize,
160                                  int start, int end, int irq)
161 {
162         struct b43legacy_dmadesc64 *descbase = ring->descbase;
163         int slot;
164         u32 ctl0 = 0;
165         u32 ctl1 = 0;
166         u32 addrlo;
167         u32 addrhi;
168         u32 addrext;
169
170         slot = (int)(&(desc->dma64) - descbase);
171         B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
172
173         addrlo = (u32)(dmaaddr & 0xFFFFFFFF);
174         addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
175         addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
176                   >> SSB_DMA_TRANSLATION_SHIFT;
177         addrhi |= ssb_dma_translation(ring->dev->dev);
178         if (slot == ring->nr_slots - 1)
179                 ctl0 |= B43legacy_DMA64_DCTL0_DTABLEEND;
180         if (start)
181                 ctl0 |= B43legacy_DMA64_DCTL0_FRAMESTART;
182         if (end)
183                 ctl0 |= B43legacy_DMA64_DCTL0_FRAMEEND;
184         if (irq)
185                 ctl0 |= B43legacy_DMA64_DCTL0_IRQ;
186         ctl1 |= (bufsize - ring->frameoffset)
187                 & B43legacy_DMA64_DCTL1_BYTECNT;
188         ctl1 |= (addrext << B43legacy_DMA64_DCTL1_ADDREXT_SHIFT)
189                 & B43legacy_DMA64_DCTL1_ADDREXT_MASK;
190
191         desc->dma64.control0 = cpu_to_le32(ctl0);
192         desc->dma64.control1 = cpu_to_le32(ctl1);
193         desc->dma64.address_low = cpu_to_le32(addrlo);
194         desc->dma64.address_high = cpu_to_le32(addrhi);
195 }
196
197 static void op64_poke_tx(struct b43legacy_dmaring *ring, int slot)
198 {
199         b43legacy_dma_write(ring, B43legacy_DMA64_TXINDEX,
200                             (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
201 }
202
203 static void op64_tx_suspend(struct b43legacy_dmaring *ring)
204 {
205         b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
206                             b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
207                             | B43legacy_DMA64_TXSUSPEND);
208 }
209
210 static void op64_tx_resume(struct b43legacy_dmaring *ring)
211 {
212         b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
213                             b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
214                             & ~B43legacy_DMA64_TXSUSPEND);
215 }
216
217 static int op64_get_current_rxslot(struct b43legacy_dmaring *ring)
218 {
219         u32 val;
220
221         val = b43legacy_dma_read(ring, B43legacy_DMA64_RXSTATUS);
222         val &= B43legacy_DMA64_RXSTATDPTR;
223
224         return (val / sizeof(struct b43legacy_dmadesc64));
225 }
226
227 static void op64_set_current_rxslot(struct b43legacy_dmaring *ring,
228                                     int slot)
229 {
230         b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
231                             (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
232 }
233
234 static const struct b43legacy_dma_ops dma64_ops = {
235         .idx2desc               = op64_idx2desc,
236         .fill_descriptor        = op64_fill_descriptor,
237         .poke_tx                = op64_poke_tx,
238         .tx_suspend             = op64_tx_suspend,
239         .tx_resume              = op64_tx_resume,
240         .get_current_rxslot     = op64_get_current_rxslot,
241         .set_current_rxslot     = op64_set_current_rxslot,
242 };
243
244
245 static inline int free_slots(struct b43legacy_dmaring *ring)
246 {
247         return (ring->nr_slots - ring->used_slots);
248 }
249
250 static inline int next_slot(struct b43legacy_dmaring *ring, int slot)
251 {
252         B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
253         if (slot == ring->nr_slots - 1)
254                 return 0;
255         return slot + 1;
256 }
257
258 static inline int prev_slot(struct b43legacy_dmaring *ring, int slot)
259 {
260         B43legacy_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
261         if (slot == 0)
262                 return ring->nr_slots - 1;
263         return slot - 1;
264 }
265
266 #ifdef CONFIG_B43LEGACY_DEBUG
267 static void update_max_used_slots(struct b43legacy_dmaring *ring,
268                                   int current_used_slots)
269 {
270         if (current_used_slots <= ring->max_used_slots)
271                 return;
272         ring->max_used_slots = current_used_slots;
273         if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE))
274                 b43legacydbg(ring->dev->wl,
275                        "max_used_slots increased to %d on %s ring %d\n",
276                        ring->max_used_slots,
277                        ring->tx ? "TX" : "RX",
278                        ring->index);
279 }
280 #else
281 static inline
282 void update_max_used_slots(struct b43legacy_dmaring *ring,
283                            int current_used_slots)
284 { }
285 #endif /* DEBUG */
286
287 /* Request a slot for usage. */
288 static inline
289 int request_slot(struct b43legacy_dmaring *ring)
290 {
291         int slot;
292
293         B43legacy_WARN_ON(!ring->tx);
294         B43legacy_WARN_ON(ring->stopped);
295         B43legacy_WARN_ON(free_slots(ring) == 0);
296
297         slot = next_slot(ring, ring->current_slot);
298         ring->current_slot = slot;
299         ring->used_slots++;
300
301         update_max_used_slots(ring, ring->used_slots);
302
303         return slot;
304 }
305
306 /* Mac80211-queue to b43legacy-ring mapping */
307 static struct b43legacy_dmaring *priority_to_txring(
308                                                 struct b43legacy_wldev *dev,
309                                                 int queue_priority)
310 {
311         struct b43legacy_dmaring *ring;
312
313 /*FIXME: For now we always run on TX-ring-1 */
314 return dev->dma.tx_ring1;
315
316         /* 0 = highest priority */
317         switch (queue_priority) {
318         default:
319                 B43legacy_WARN_ON(1);
320                 /* fallthrough */
321         case 0:
322                 ring = dev->dma.tx_ring3;
323                 break;
324         case 1:
325                 ring = dev->dma.tx_ring2;
326                 break;
327         case 2:
328                 ring = dev->dma.tx_ring1;
329                 break;
330         case 3:
331                 ring = dev->dma.tx_ring0;
332                 break;
333         case 4:
334                 ring = dev->dma.tx_ring4;
335                 break;
336         case 5:
337                 ring = dev->dma.tx_ring5;
338                 break;
339         }
340
341         return ring;
342 }
343
344 /* Bcm4301-ring to mac80211-queue mapping */
345 static inline int txring_to_priority(struct b43legacy_dmaring *ring)
346 {
347         static const u8 idx_to_prio[] =
348                 { 3, 2, 1, 0, 4, 5, };
349
350 /*FIXME: have only one queue, for now */
351 return 0;
352
353         return idx_to_prio[ring->index];
354 }
355
356
357 static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type,
358                                         int controller_idx)
359 {
360         static const u16 map64[] = {
361                 B43legacy_MMIO_DMA64_BASE0,
362                 B43legacy_MMIO_DMA64_BASE1,
363                 B43legacy_MMIO_DMA64_BASE2,
364                 B43legacy_MMIO_DMA64_BASE3,
365                 B43legacy_MMIO_DMA64_BASE4,
366                 B43legacy_MMIO_DMA64_BASE5,
367         };
368         static const u16 map32[] = {
369                 B43legacy_MMIO_DMA32_BASE0,
370                 B43legacy_MMIO_DMA32_BASE1,
371                 B43legacy_MMIO_DMA32_BASE2,
372                 B43legacy_MMIO_DMA32_BASE3,
373                 B43legacy_MMIO_DMA32_BASE4,
374                 B43legacy_MMIO_DMA32_BASE5,
375         };
376
377         if (type == B43legacy_DMA_64BIT) {
378                 B43legacy_WARN_ON(!(controller_idx >= 0 &&
379                                   controller_idx < ARRAY_SIZE(map64)));
380                 return map64[controller_idx];
381         }
382         B43legacy_WARN_ON(!(controller_idx >= 0 &&
383                           controller_idx < ARRAY_SIZE(map32)));
384         return map32[controller_idx];
385 }
386
387 static inline
388 dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring,
389                           unsigned char *buf,
390                           size_t len,
391                           int tx)
392 {
393         dma_addr_t dmaaddr;
394
395         if (tx)
396                 dmaaddr = ssb_dma_map_single(ring->dev->dev,
397                                              buf, len,
398                                              DMA_TO_DEVICE);
399         else
400                 dmaaddr = ssb_dma_map_single(ring->dev->dev,
401                                              buf, len,
402                                              DMA_FROM_DEVICE);
403
404         return dmaaddr;
405 }
406
407 static inline
408 void unmap_descbuffer(struct b43legacy_dmaring *ring,
409                       dma_addr_t addr,
410                       size_t len,
411                       int tx)
412 {
413         if (tx)
414                 ssb_dma_unmap_single(ring->dev->dev,
415                                      addr, len,
416                                      DMA_TO_DEVICE);
417         else
418                 ssb_dma_unmap_single(ring->dev->dev,
419                                      addr, len,
420                                      DMA_FROM_DEVICE);
421 }
422
423 static inline
424 void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring,
425                              dma_addr_t addr,
426                              size_t len)
427 {
428         B43legacy_WARN_ON(ring->tx);
429
430         ssb_dma_sync_single_for_cpu(ring->dev->dev,
431                                     addr, len, DMA_FROM_DEVICE);
432 }
433
434 static inline
435 void sync_descbuffer_for_device(struct b43legacy_dmaring *ring,
436                                 dma_addr_t addr,
437                                 size_t len)
438 {
439         B43legacy_WARN_ON(ring->tx);
440
441         ssb_dma_sync_single_for_device(ring->dev->dev,
442                                        addr, len, DMA_FROM_DEVICE);
443 }
444
445 static inline
446 void free_descriptor_buffer(struct b43legacy_dmaring *ring,
447                             struct b43legacy_dmadesc_meta *meta,
448                             int irq_context)
449 {
450         if (meta->skb) {
451                 if (irq_context)
452                         dev_kfree_skb_irq(meta->skb);
453                 else
454                         dev_kfree_skb(meta->skb);
455                 meta->skb = NULL;
456         }
457 }
458
459 static int alloc_ringmemory(struct b43legacy_dmaring *ring)
460 {
461         /* GFP flags must match the flags in free_ringmemory()! */
462         ring->descbase = ssb_dma_alloc_consistent(ring->dev->dev,
463                                                   B43legacy_DMA_RINGMEMSIZE,
464                                                   &(ring->dmabase),
465                                                   GFP_KERNEL);
466         if (!ring->descbase) {
467                 b43legacyerr(ring->dev->wl, "DMA ringmemory allocation"
468                              " failed\n");
469                 return -ENOMEM;
470         }
471         memset(ring->descbase, 0, B43legacy_DMA_RINGMEMSIZE);
472
473         return 0;
474 }
475
476 static void free_ringmemory(struct b43legacy_dmaring *ring)
477 {
478         ssb_dma_free_consistent(ring->dev->dev, B43legacy_DMA_RINGMEMSIZE,
479                                 ring->descbase, ring->dmabase, GFP_KERNEL);
480 }
481
482 /* Reset the RX DMA channel */
483 static int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev,
484                                             u16 mmio_base,
485                                             enum b43legacy_dmatype type)
486 {
487         int i;
488         u32 value;
489         u16 offset;
490
491         might_sleep();
492
493         offset = (type == B43legacy_DMA_64BIT) ?
494                  B43legacy_DMA64_RXCTL : B43legacy_DMA32_RXCTL;
495         b43legacy_write32(dev, mmio_base + offset, 0);
496         for (i = 0; i < 10; i++) {
497                 offset = (type == B43legacy_DMA_64BIT) ?
498                          B43legacy_DMA64_RXSTATUS : B43legacy_DMA32_RXSTATUS;
499                 value = b43legacy_read32(dev, mmio_base + offset);
500                 if (type == B43legacy_DMA_64BIT) {
501                         value &= B43legacy_DMA64_RXSTAT;
502                         if (value == B43legacy_DMA64_RXSTAT_DISABLED) {
503                                 i = -1;
504                                 break;
505                         }
506                 } else {
507                         value &= B43legacy_DMA32_RXSTATE;
508                         if (value == B43legacy_DMA32_RXSTAT_DISABLED) {
509                                 i = -1;
510                                 break;
511                         }
512                 }
513                 msleep(1);
514         }
515         if (i != -1) {
516                 b43legacyerr(dev->wl, "DMA RX reset timed out\n");
517                 return -ENODEV;
518         }
519
520         return 0;
521 }
522
523 /* Reset the RX DMA channel */
524 static int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev,
525                                             u16 mmio_base,
526                                             enum b43legacy_dmatype type)
527 {
528         int i;
529         u32 value;
530         u16 offset;
531
532         might_sleep();
533
534         for (i = 0; i < 10; i++) {
535                 offset = (type == B43legacy_DMA_64BIT) ?
536                          B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
537                 value = b43legacy_read32(dev, mmio_base + offset);
538                 if (type == B43legacy_DMA_64BIT) {
539                         value &= B43legacy_DMA64_TXSTAT;
540                         if (value == B43legacy_DMA64_TXSTAT_DISABLED ||
541                             value == B43legacy_DMA64_TXSTAT_IDLEWAIT ||
542                             value == B43legacy_DMA64_TXSTAT_STOPPED)
543                                 break;
544                 } else {
545                         value &= B43legacy_DMA32_TXSTATE;
546                         if (value == B43legacy_DMA32_TXSTAT_DISABLED ||
547                             value == B43legacy_DMA32_TXSTAT_IDLEWAIT ||
548                             value == B43legacy_DMA32_TXSTAT_STOPPED)
549                                 break;
550                 }
551                 msleep(1);
552         }
553         offset = (type == B43legacy_DMA_64BIT) ? B43legacy_DMA64_TXCTL :
554                                                  B43legacy_DMA32_TXCTL;
555         b43legacy_write32(dev, mmio_base + offset, 0);
556         for (i = 0; i < 10; i++) {
557                 offset = (type == B43legacy_DMA_64BIT) ?
558                          B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
559                 value = b43legacy_read32(dev, mmio_base + offset);
560                 if (type == B43legacy_DMA_64BIT) {
561                         value &= B43legacy_DMA64_TXSTAT;
562                         if (value == B43legacy_DMA64_TXSTAT_DISABLED) {
563                                 i = -1;
564                                 break;
565                         }
566                 } else {
567                         value &= B43legacy_DMA32_TXSTATE;
568                         if (value == B43legacy_DMA32_TXSTAT_DISABLED) {
569                                 i = -1;
570                                 break;
571                         }
572                 }
573                 msleep(1);
574         }
575         if (i != -1) {
576                 b43legacyerr(dev->wl, "DMA TX reset timed out\n");
577                 return -ENODEV;
578         }
579         /* ensure the reset is completed. */
580         msleep(1);
581
582         return 0;
583 }
584
585 /* Check if a DMA mapping address is invalid. */
586 static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring,
587                                          dma_addr_t addr,
588                                          size_t buffersize,
589                                          bool dma_to_device)
590 {
591         if (unlikely(ssb_dma_mapping_error(ring->dev->dev, addr)))
592                 return 1;
593
594         switch (ring->type) {
595         case B43legacy_DMA_30BIT:
596                 if ((u64)addr + buffersize > (1ULL << 30))
597                         goto address_error;
598                 break;
599         case B43legacy_DMA_32BIT:
600                 if ((u64)addr + buffersize > (1ULL << 32))
601                         goto address_error;
602                 break;
603         case B43legacy_DMA_64BIT:
604                 /* Currently we can't have addresses beyond 64 bits in the kernel. */
605                 break;
606         }
607
608         /* The address is OK. */
609         return 0;
610
611 address_error:
612         /* We can't support this address. Unmap it again. */
613         unmap_descbuffer(ring, addr, buffersize, dma_to_device);
614
615         return 1;
616 }
617
618 static int setup_rx_descbuffer(struct b43legacy_dmaring *ring,
619                                struct b43legacy_dmadesc_generic *desc,
620                                struct b43legacy_dmadesc_meta *meta,
621                                gfp_t gfp_flags)
622 {
623         struct b43legacy_rxhdr_fw3 *rxhdr;
624         struct b43legacy_hwtxstatus *txstat;
625         dma_addr_t dmaaddr;
626         struct sk_buff *skb;
627
628         B43legacy_WARN_ON(ring->tx);
629
630         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
631         if (unlikely(!skb))
632                 return -ENOMEM;
633         dmaaddr = map_descbuffer(ring, skb->data,
634                                  ring->rx_buffersize, 0);
635         if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
636                 /* ugh. try to realloc in zone_dma */
637                 gfp_flags |= GFP_DMA;
638
639                 dev_kfree_skb_any(skb);
640
641                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
642                 if (unlikely(!skb))
643                         return -ENOMEM;
644                 dmaaddr = map_descbuffer(ring, skb->data,
645                                          ring->rx_buffersize, 0);
646         }
647
648         if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
649                 dev_kfree_skb_any(skb);
650                 return -EIO;
651         }
652
653         meta->skb = skb;
654         meta->dmaaddr = dmaaddr;
655         ring->ops->fill_descriptor(ring, desc, dmaaddr,
656                                    ring->rx_buffersize, 0, 0, 0);
657
658         rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data);
659         rxhdr->frame_len = 0;
660         txstat = (struct b43legacy_hwtxstatus *)(skb->data);
661         txstat->cookie = 0;
662
663         return 0;
664 }
665
666 /* Allocate the initial descbuffers.
667  * This is used for an RX ring only.
668  */
669 static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring)
670 {
671         int i;
672         int err = -ENOMEM;
673         struct b43legacy_dmadesc_generic *desc;
674         struct b43legacy_dmadesc_meta *meta;
675
676         for (i = 0; i < ring->nr_slots; i++) {
677                 desc = ring->ops->idx2desc(ring, i, &meta);
678
679                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
680                 if (err) {
681                         b43legacyerr(ring->dev->wl,
682                                "Failed to allocate initial descbuffers\n");
683                         goto err_unwind;
684                 }
685         }
686         mb(); /* all descbuffer setup before next line */
687         ring->used_slots = ring->nr_slots;
688         err = 0;
689 out:
690         return err;
691
692 err_unwind:
693         for (i--; i >= 0; i--) {
694                 desc = ring->ops->idx2desc(ring, i, &meta);
695
696                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
697                 dev_kfree_skb(meta->skb);
698         }
699         goto out;
700 }
701
702 /* Do initial setup of the DMA controller.
703  * Reset the controller, write the ring busaddress
704  * and switch the "enable" bit on.
705  */
706 static int dmacontroller_setup(struct b43legacy_dmaring *ring)
707 {
708         int err = 0;
709         u32 value;
710         u32 addrext;
711         u32 trans = ssb_dma_translation(ring->dev->dev);
712
713         if (ring->tx) {
714                 if (ring->type == B43legacy_DMA_64BIT) {
715                         u64 ringbase = (u64)(ring->dmabase);
716
717                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
718                                   >> SSB_DMA_TRANSLATION_SHIFT;
719                         value = B43legacy_DMA64_TXENABLE;
720                         value |= (addrext << B43legacy_DMA64_TXADDREXT_SHIFT)
721                                 & B43legacy_DMA64_TXADDREXT_MASK;
722                         b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
723                                             value);
724                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO,
725                                             (ringbase & 0xFFFFFFFF));
726                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI,
727                                             ((ringbase >> 32)
728                                             & ~SSB_DMA_TRANSLATION_MASK)
729                                             | trans);
730                 } else {
731                         u32 ringbase = (u32)(ring->dmabase);
732
733                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
734                                   >> SSB_DMA_TRANSLATION_SHIFT;
735                         value = B43legacy_DMA32_TXENABLE;
736                         value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT)
737                                 & B43legacy_DMA32_TXADDREXT_MASK;
738                         b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
739                                             value);
740                         b43legacy_dma_write(ring, B43legacy_DMA32_TXRING,
741                                             (ringbase &
742                                             ~SSB_DMA_TRANSLATION_MASK)
743                                             | trans);
744                 }
745         } else {
746                 err = alloc_initial_descbuffers(ring);
747                 if (err)
748                         goto out;
749                 if (ring->type == B43legacy_DMA_64BIT) {
750                         u64 ringbase = (u64)(ring->dmabase);
751
752                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
753                                   >> SSB_DMA_TRANSLATION_SHIFT;
754                         value = (ring->frameoffset <<
755                                  B43legacy_DMA64_RXFROFF_SHIFT);
756                         value |= B43legacy_DMA64_RXENABLE;
757                         value |= (addrext << B43legacy_DMA64_RXADDREXT_SHIFT)
758                                 & B43legacy_DMA64_RXADDREXT_MASK;
759                         b43legacy_dma_write(ring, B43legacy_DMA64_RXCTL,
760                                             value);
761                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO,
762                                             (ringbase & 0xFFFFFFFF));
763                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI,
764                                             ((ringbase >> 32) &
765                                             ~SSB_DMA_TRANSLATION_MASK) |
766                                             trans);
767                         b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
768                                             200);
769                 } else {
770                         u32 ringbase = (u32)(ring->dmabase);
771
772                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
773                                   >> SSB_DMA_TRANSLATION_SHIFT;
774                         value = (ring->frameoffset <<
775                                  B43legacy_DMA32_RXFROFF_SHIFT);
776                         value |= B43legacy_DMA32_RXENABLE;
777                         value |= (addrext <<
778                                  B43legacy_DMA32_RXADDREXT_SHIFT)
779                                  & B43legacy_DMA32_RXADDREXT_MASK;
780                         b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL,
781                                             value);
782                         b43legacy_dma_write(ring, B43legacy_DMA32_RXRING,
783                                             (ringbase &
784                                             ~SSB_DMA_TRANSLATION_MASK)
785                                             | trans);
786                         b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
787                                             200);
788                 }
789         }
790
791 out:
792         return err;
793 }
794
795 /* Shutdown the DMA controller. */
796 static void dmacontroller_cleanup(struct b43legacy_dmaring *ring)
797 {
798         if (ring->tx) {
799                 b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
800                                                  ring->type);
801                 if (ring->type == B43legacy_DMA_64BIT) {
802                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO, 0);
803                         b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI, 0);
804                 } else
805                         b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0);
806         } else {
807                 b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
808                                                  ring->type);
809                 if (ring->type == B43legacy_DMA_64BIT) {
810                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO, 0);
811                         b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI, 0);
812                 } else
813                         b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0);
814         }
815 }
816
817 static void free_all_descbuffers(struct b43legacy_dmaring *ring)
818 {
819         struct b43legacy_dmadesc_generic *desc;
820         struct b43legacy_dmadesc_meta *meta;
821         int i;
822
823         if (!ring->used_slots)
824                 return;
825         for (i = 0; i < ring->nr_slots; i++) {
826                 desc = ring->ops->idx2desc(ring, i, &meta);
827
828                 if (!meta->skb) {
829                         B43legacy_WARN_ON(!ring->tx);
830                         continue;
831                 }
832                 if (ring->tx)
833                         unmap_descbuffer(ring, meta->dmaaddr,
834                                          meta->skb->len, 1);
835                 else
836                         unmap_descbuffer(ring, meta->dmaaddr,
837                                          ring->rx_buffersize, 0);
838                 free_descriptor_buffer(ring, meta, 0);
839         }
840 }
841
842 static u64 supported_dma_mask(struct b43legacy_wldev *dev)
843 {
844         u32 tmp;
845         u16 mmio_base;
846
847         tmp = b43legacy_read32(dev, SSB_TMSHIGH);
848         if (tmp & SSB_TMSHIGH_DMA64)
849                 return DMA_BIT_MASK(64);
850         mmio_base = b43legacy_dmacontroller_base(0, 0);
851         b43legacy_write32(dev,
852                         mmio_base + B43legacy_DMA32_TXCTL,
853                         B43legacy_DMA32_TXADDREXT_MASK);
854         tmp = b43legacy_read32(dev, mmio_base +
855                                B43legacy_DMA32_TXCTL);
856         if (tmp & B43legacy_DMA32_TXADDREXT_MASK)
857                 return DMA_32BIT_MASK;
858
859         return DMA_30BIT_MASK;
860 }
861
862 static enum b43legacy_dmatype dma_mask_to_engine_type(u64 dmamask)
863 {
864         if (dmamask == DMA_30BIT_MASK)
865                 return B43legacy_DMA_30BIT;
866         if (dmamask == DMA_32BIT_MASK)
867                 return B43legacy_DMA_32BIT;
868         if (dmamask == DMA_BIT_MASK(64))
869                 return B43legacy_DMA_64BIT;
870         B43legacy_WARN_ON(1);
871         return B43legacy_DMA_30BIT;
872 }
873
874 /* Main initialization function. */
875 static
876 struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
877                                                   int controller_index,
878                                                   int for_tx,
879                                                   enum b43legacy_dmatype type)
880 {
881         struct b43legacy_dmaring *ring;
882         int err;
883         int nr_slots;
884         dma_addr_t dma_test;
885
886         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
887         if (!ring)
888                 goto out;
889         ring->type = type;
890         ring->dev = dev;
891
892         nr_slots = B43legacy_RXRING_SLOTS;
893         if (for_tx)
894                 nr_slots = B43legacy_TXRING_SLOTS;
895
896         ring->meta = kcalloc(nr_slots, sizeof(struct b43legacy_dmadesc_meta),
897                              GFP_KERNEL);
898         if (!ring->meta)
899                 goto err_kfree_ring;
900         if (for_tx) {
901                 ring->txhdr_cache = kcalloc(nr_slots,
902                                         sizeof(struct b43legacy_txhdr_fw3),
903                                         GFP_KERNEL);
904                 if (!ring->txhdr_cache)
905                         goto err_kfree_meta;
906
907                 /* test for ability to dma to txhdr_cache */
908                 dma_test = ssb_dma_map_single(dev->dev, ring->txhdr_cache,
909                                               sizeof(struct b43legacy_txhdr_fw3),
910                                               DMA_TO_DEVICE);
911
912                 if (b43legacy_dma_mapping_error(ring, dma_test,
913                                         sizeof(struct b43legacy_txhdr_fw3), 1)) {
914                         /* ugh realloc */
915                         kfree(ring->txhdr_cache);
916                         ring->txhdr_cache = kcalloc(nr_slots,
917                                         sizeof(struct b43legacy_txhdr_fw3),
918                                         GFP_KERNEL | GFP_DMA);
919                         if (!ring->txhdr_cache)
920                                 goto err_kfree_meta;
921
922                         dma_test = ssb_dma_map_single(dev->dev,
923                                         ring->txhdr_cache,
924                                         sizeof(struct b43legacy_txhdr_fw3),
925                                         DMA_TO_DEVICE);
926
927                         if (b43legacy_dma_mapping_error(ring, dma_test,
928                                         sizeof(struct b43legacy_txhdr_fw3), 1))
929                                 goto err_kfree_txhdr_cache;
930                 }
931
932                 ssb_dma_unmap_single(dev->dev, dma_test,
933                                      sizeof(struct b43legacy_txhdr_fw3),
934                                      DMA_TO_DEVICE);
935         }
936
937         ring->nr_slots = nr_slots;
938         ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index);
939         ring->index = controller_index;
940         if (type == B43legacy_DMA_64BIT)
941                 ring->ops = &dma64_ops;
942         else
943                 ring->ops = &dma32_ops;
944         if (for_tx) {
945                 ring->tx = 1;
946                 ring->current_slot = -1;
947         } else {
948                 if (ring->index == 0) {
949                         ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE;
950                         ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET;
951                 } else if (ring->index == 3) {
952                         ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE;
953                         ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET;
954                 } else
955                         B43legacy_WARN_ON(1);
956         }
957         spin_lock_init(&ring->lock);
958 #ifdef CONFIG_B43LEGACY_DEBUG
959         ring->last_injected_overflow = jiffies;
960 #endif
961
962         err = alloc_ringmemory(ring);
963         if (err)
964                 goto err_kfree_txhdr_cache;
965         err = dmacontroller_setup(ring);
966         if (err)
967                 goto err_free_ringmemory;
968
969 out:
970         return ring;
971
972 err_free_ringmemory:
973         free_ringmemory(ring);
974 err_kfree_txhdr_cache:
975         kfree(ring->txhdr_cache);
976 err_kfree_meta:
977         kfree(ring->meta);
978 err_kfree_ring:
979         kfree(ring);
980         ring = NULL;
981         goto out;
982 }
983
984 /* Main cleanup function. */
985 static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring)
986 {
987         if (!ring)
988                 return;
989
990         b43legacydbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots:"
991                      " %d/%d\n", (unsigned int)(ring->type), ring->mmio_base,
992                      (ring->tx) ? "TX" : "RX", ring->max_used_slots,
993                      ring->nr_slots);
994         /* Device IRQs are disabled prior entering this function,
995          * so no need to take care of concurrency with rx handler stuff.
996          */
997         dmacontroller_cleanup(ring);
998         free_all_descbuffers(ring);
999         free_ringmemory(ring);
1000
1001         kfree(ring->txhdr_cache);
1002         kfree(ring->meta);
1003         kfree(ring);
1004 }
1005
1006 void b43legacy_dma_free(struct b43legacy_wldev *dev)
1007 {
1008         struct b43legacy_dma *dma;
1009
1010         if (b43legacy_using_pio(dev))
1011                 return;
1012         dma = &dev->dma;
1013
1014         b43legacy_destroy_dmaring(dma->rx_ring3);
1015         dma->rx_ring3 = NULL;
1016         b43legacy_destroy_dmaring(dma->rx_ring0);
1017         dma->rx_ring0 = NULL;
1018
1019         b43legacy_destroy_dmaring(dma->tx_ring5);
1020         dma->tx_ring5 = NULL;
1021         b43legacy_destroy_dmaring(dma->tx_ring4);
1022         dma->tx_ring4 = NULL;
1023         b43legacy_destroy_dmaring(dma->tx_ring3);
1024         dma->tx_ring3 = NULL;
1025         b43legacy_destroy_dmaring(dma->tx_ring2);
1026         dma->tx_ring2 = NULL;
1027         b43legacy_destroy_dmaring(dma->tx_ring1);
1028         dma->tx_ring1 = NULL;
1029         b43legacy_destroy_dmaring(dma->tx_ring0);
1030         dma->tx_ring0 = NULL;
1031 }
1032
1033 static int b43legacy_dma_set_mask(struct b43legacy_wldev *dev, u64 mask)
1034 {
1035         u64 orig_mask = mask;
1036         bool fallback = 0;
1037         int err;
1038
1039         /* Try to set the DMA mask. If it fails, try falling back to a
1040          * lower mask, as we can always also support a lower one. */
1041         while (1) {
1042                 err = ssb_dma_set_mask(dev->dev, mask);
1043                 if (!err)
1044                         break;
1045                 if (mask == DMA_BIT_MASK(64)) {
1046                         mask = DMA_32BIT_MASK;
1047                         fallback = 1;
1048                         continue;
1049                 }
1050                 if (mask == DMA_32BIT_MASK) {
1051                         mask = DMA_30BIT_MASK;
1052                         fallback = 1;
1053                         continue;
1054                 }
1055                 b43legacyerr(dev->wl, "The machine/kernel does not support "
1056                        "the required %u-bit DMA mask\n",
1057                        (unsigned int)dma_mask_to_engine_type(orig_mask));
1058                 return -EOPNOTSUPP;
1059         }
1060         if (fallback) {
1061                 b43legacyinfo(dev->wl, "DMA mask fallback from %u-bit to %u-"
1062                         "bit\n",
1063                         (unsigned int)dma_mask_to_engine_type(orig_mask),
1064                         (unsigned int)dma_mask_to_engine_type(mask));
1065         }
1066
1067         return 0;
1068 }
1069
1070 int b43legacy_dma_init(struct b43legacy_wldev *dev)
1071 {
1072         struct b43legacy_dma *dma = &dev->dma;
1073         struct b43legacy_dmaring *ring;
1074         int err;
1075         u64 dmamask;
1076         enum b43legacy_dmatype type;
1077
1078         dmamask = supported_dma_mask(dev);
1079         type = dma_mask_to_engine_type(dmamask);
1080         err = b43legacy_dma_set_mask(dev, dmamask);
1081         if (err) {
1082 #ifdef CONFIG_B43LEGACY_PIO
1083                 b43legacywarn(dev->wl, "DMA for this device not supported. "
1084                         "Falling back to PIO\n");
1085                 dev->__using_pio = 1;
1086                 return -EAGAIN;
1087 #else
1088                 b43legacyerr(dev->wl, "DMA for this device not supported and "
1089                        "no PIO support compiled in\n");
1090                 return -EOPNOTSUPP;
1091 #endif
1092         }
1093
1094         err = -ENOMEM;
1095         /* setup TX DMA channels. */
1096         ring = b43legacy_setup_dmaring(dev, 0, 1, type);
1097         if (!ring)
1098                 goto out;
1099         dma->tx_ring0 = ring;
1100
1101         ring = b43legacy_setup_dmaring(dev, 1, 1, type);
1102         if (!ring)
1103                 goto err_destroy_tx0;
1104         dma->tx_ring1 = ring;
1105
1106         ring = b43legacy_setup_dmaring(dev, 2, 1, type);
1107         if (!ring)
1108                 goto err_destroy_tx1;
1109         dma->tx_ring2 = ring;
1110
1111         ring = b43legacy_setup_dmaring(dev, 3, 1, type);
1112         if (!ring)
1113                 goto err_destroy_tx2;
1114         dma->tx_ring3 = ring;
1115
1116         ring = b43legacy_setup_dmaring(dev, 4, 1, type);
1117         if (!ring)
1118                 goto err_destroy_tx3;
1119         dma->tx_ring4 = ring;
1120
1121         ring = b43legacy_setup_dmaring(dev, 5, 1, type);
1122         if (!ring)
1123                 goto err_destroy_tx4;
1124         dma->tx_ring5 = ring;
1125
1126         /* setup RX DMA channels. */
1127         ring = b43legacy_setup_dmaring(dev, 0, 0, type);
1128         if (!ring)
1129                 goto err_destroy_tx5;
1130         dma->rx_ring0 = ring;
1131
1132         if (dev->dev->id.revision < 5) {
1133                 ring = b43legacy_setup_dmaring(dev, 3, 0, type);
1134                 if (!ring)
1135                         goto err_destroy_rx0;
1136                 dma->rx_ring3 = ring;
1137         }
1138
1139         b43legacydbg(dev->wl, "%u-bit DMA initialized\n", (unsigned int)type);
1140         err = 0;
1141 out:
1142         return err;
1143
1144 err_destroy_rx0:
1145         b43legacy_destroy_dmaring(dma->rx_ring0);
1146         dma->rx_ring0 = NULL;
1147 err_destroy_tx5:
1148         b43legacy_destroy_dmaring(dma->tx_ring5);
1149         dma->tx_ring5 = NULL;
1150 err_destroy_tx4:
1151         b43legacy_destroy_dmaring(dma->tx_ring4);
1152         dma->tx_ring4 = NULL;
1153 err_destroy_tx3:
1154         b43legacy_destroy_dmaring(dma->tx_ring3);
1155         dma->tx_ring3 = NULL;
1156 err_destroy_tx2:
1157         b43legacy_destroy_dmaring(dma->tx_ring2);
1158         dma->tx_ring2 = NULL;
1159 err_destroy_tx1:
1160         b43legacy_destroy_dmaring(dma->tx_ring1);
1161         dma->tx_ring1 = NULL;
1162 err_destroy_tx0:
1163         b43legacy_destroy_dmaring(dma->tx_ring0);
1164         dma->tx_ring0 = NULL;
1165         goto out;
1166 }
1167
1168 /* Generate a cookie for the TX header. */
1169 static u16 generate_cookie(struct b43legacy_dmaring *ring,
1170                            int slot)
1171 {
1172         u16 cookie = 0x1000;
1173
1174         /* Use the upper 4 bits of the cookie as
1175          * DMA controller ID and store the slot number
1176          * in the lower 12 bits.
1177          * Note that the cookie must never be 0, as this
1178          * is a special value used in RX path.
1179          */
1180         switch (ring->index) {
1181         case 0:
1182                 cookie = 0xA000;
1183                 break;
1184         case 1:
1185                 cookie = 0xB000;
1186                 break;
1187         case 2:
1188                 cookie = 0xC000;
1189                 break;
1190         case 3:
1191                 cookie = 0xD000;
1192                 break;
1193         case 4:
1194                 cookie = 0xE000;
1195                 break;
1196         case 5:
1197                 cookie = 0xF000;
1198                 break;
1199         }
1200         B43legacy_WARN_ON(!(((u16)slot & 0xF000) == 0x0000));
1201         cookie |= (u16)slot;
1202
1203         return cookie;
1204 }
1205
1206 /* Inspect a cookie and find out to which controller/slot it belongs. */
1207 static
1208 struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev,
1209                                       u16 cookie, int *slot)
1210 {
1211         struct b43legacy_dma *dma = &dev->dma;
1212         struct b43legacy_dmaring *ring = NULL;
1213
1214         switch (cookie & 0xF000) {
1215         case 0xA000:
1216                 ring = dma->tx_ring0;
1217                 break;
1218         case 0xB000:
1219                 ring = dma->tx_ring1;
1220                 break;
1221         case 0xC000:
1222                 ring = dma->tx_ring2;
1223                 break;
1224         case 0xD000:
1225                 ring = dma->tx_ring3;
1226                 break;
1227         case 0xE000:
1228                 ring = dma->tx_ring4;
1229                 break;
1230         case 0xF000:
1231                 ring = dma->tx_ring5;
1232                 break;
1233         default:
1234                 B43legacy_WARN_ON(1);
1235         }
1236         *slot = (cookie & 0x0FFF);
1237         B43legacy_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1238
1239         return ring;
1240 }
1241
1242 static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1243                             struct sk_buff *skb)
1244 {
1245         const struct b43legacy_dma_ops *ops = ring->ops;
1246         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1247         u8 *header;
1248         int slot, old_top_slot, old_used_slots;
1249         int err;
1250         struct b43legacy_dmadesc_generic *desc;
1251         struct b43legacy_dmadesc_meta *meta;
1252         struct b43legacy_dmadesc_meta *meta_hdr;
1253         struct sk_buff *bounce_skb;
1254
1255 #define SLOTS_PER_PACKET  2
1256         B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0);
1257
1258         old_top_slot = ring->current_slot;
1259         old_used_slots = ring->used_slots;
1260
1261         /* Get a slot for the header. */
1262         slot = request_slot(ring);
1263         desc = ops->idx2desc(ring, slot, &meta_hdr);
1264         memset(meta_hdr, 0, sizeof(*meta_hdr));
1265
1266         header = &(ring->txhdr_cache[slot * sizeof(
1267                                struct b43legacy_txhdr_fw3)]);
1268         err = b43legacy_generate_txhdr(ring->dev, header,
1269                                  skb->data, skb->len, info,
1270                                  generate_cookie(ring, slot));
1271         if (unlikely(err)) {
1272                 ring->current_slot = old_top_slot;
1273                 ring->used_slots = old_used_slots;
1274                 return err;
1275         }
1276
1277         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1278                                            sizeof(struct b43legacy_txhdr_fw3), 1);
1279         if (b43legacy_dma_mapping_error(ring, meta_hdr->dmaaddr,
1280                                         sizeof(struct b43legacy_txhdr_fw3), 1)) {
1281                 ring->current_slot = old_top_slot;
1282                 ring->used_slots = old_used_slots;
1283                 return -EIO;
1284         }
1285         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1286                              sizeof(struct b43legacy_txhdr_fw3), 1, 0, 0);
1287
1288         /* Get a slot for the payload. */
1289         slot = request_slot(ring);
1290         desc = ops->idx2desc(ring, slot, &meta);
1291         memset(meta, 0, sizeof(*meta));
1292
1293         meta->skb = skb;
1294         meta->is_last_fragment = 1;
1295
1296         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1297         /* create a bounce buffer in zone_dma on mapping failure. */
1298         if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1299                 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1300                 if (!bounce_skb) {
1301                         ring->current_slot = old_top_slot;
1302                         ring->used_slots = old_used_slots;
1303                         err = -ENOMEM;
1304                         goto out_unmap_hdr;
1305                 }
1306
1307                 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1308                 dev_kfree_skb_any(skb);
1309                 skb = bounce_skb;
1310                 meta->skb = skb;
1311                 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1312                 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1313                         ring->current_slot = old_top_slot;
1314                         ring->used_slots = old_used_slots;
1315                         err = -EIO;
1316                         goto out_free_bounce;
1317                 }
1318         }
1319
1320         ops->fill_descriptor(ring, desc, meta->dmaaddr,
1321                              skb->len, 0, 1, 1);
1322
1323         wmb();  /* previous stuff MUST be done */
1324         /* Now transfer the whole frame. */
1325         ops->poke_tx(ring, next_slot(ring, slot));
1326         return 0;
1327
1328 out_free_bounce:
1329         dev_kfree_skb_any(skb);
1330 out_unmap_hdr:
1331         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1332                          sizeof(struct b43legacy_txhdr_fw3), 1);
1333         return err;
1334 }
1335
1336 static inline
1337 int should_inject_overflow(struct b43legacy_dmaring *ring)
1338 {
1339 #ifdef CONFIG_B43LEGACY_DEBUG
1340         if (unlikely(b43legacy_debug(ring->dev,
1341                                      B43legacy_DBG_DMAOVERFLOW))) {
1342                 /* Check if we should inject another ringbuffer overflow
1343                  * to test handling of this situation in the stack. */
1344                 unsigned long next_overflow;
1345
1346                 next_overflow = ring->last_injected_overflow + HZ;
1347                 if (time_after(jiffies, next_overflow)) {
1348                         ring->last_injected_overflow = jiffies;
1349                         b43legacydbg(ring->dev->wl,
1350                                "Injecting TX ring overflow on "
1351                                "DMA controller %d\n", ring->index);
1352                         return 1;
1353                 }
1354         }
1355 #endif /* CONFIG_B43LEGACY_DEBUG */
1356         return 0;
1357 }
1358
1359 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1360                      struct sk_buff *skb)
1361 {
1362         struct b43legacy_dmaring *ring;
1363         int err = 0;
1364         unsigned long flags;
1365
1366         ring = priority_to_txring(dev, skb_get_queue_mapping(skb));
1367         spin_lock_irqsave(&ring->lock, flags);
1368         B43legacy_WARN_ON(!ring->tx);
1369         if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1370                 b43legacywarn(dev->wl, "DMA queue overflow\n");
1371                 err = -ENOSPC;
1372                 goto out_unlock;
1373         }
1374         /* Check if the queue was stopped in mac80211,
1375          * but we got called nevertheless.
1376          * That would be a mac80211 bug. */
1377         B43legacy_BUG_ON(ring->stopped);
1378
1379         err = dma_tx_fragment(ring, skb);
1380         if (unlikely(err == -ENOKEY)) {
1381                 /* Drop this packet, as we don't have the encryption key
1382                  * anymore and must not transmit it unencrypted. */
1383                 dev_kfree_skb_any(skb);
1384                 err = 0;
1385                 goto out_unlock;
1386         }
1387         if (unlikely(err)) {
1388                 b43legacyerr(dev->wl, "DMA tx mapping failure\n");
1389                 goto out_unlock;
1390         }
1391         ring->nr_tx_packets++;
1392         if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1393             should_inject_overflow(ring)) {
1394                 /* This TX ring is full. */
1395                 ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
1396                 ring->stopped = 1;
1397                 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1398                         b43legacydbg(dev->wl, "Stopped TX ring %d\n",
1399                                ring->index);
1400         }
1401 out_unlock:
1402         spin_unlock_irqrestore(&ring->lock, flags);
1403
1404         return err;
1405 }
1406
1407 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1408                                  const struct b43legacy_txstatus *status)
1409 {
1410         const struct b43legacy_dma_ops *ops;
1411         struct b43legacy_dmaring *ring;
1412         struct b43legacy_dmadesc_generic *desc;
1413         struct b43legacy_dmadesc_meta *meta;
1414         int retry_limit;
1415         int slot;
1416
1417         ring = parse_cookie(dev, status->cookie, &slot);
1418         if (unlikely(!ring))
1419                 return;
1420         B43legacy_WARN_ON(!irqs_disabled());
1421         spin_lock(&ring->lock);
1422
1423         B43legacy_WARN_ON(!ring->tx);
1424         ops = ring->ops;
1425         while (1) {
1426                 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1427                 desc = ops->idx2desc(ring, slot, &meta);
1428
1429                 if (meta->skb)
1430                         unmap_descbuffer(ring, meta->dmaaddr,
1431                                          meta->skb->len, 1);
1432                 else
1433                         unmap_descbuffer(ring, meta->dmaaddr,
1434                                          sizeof(struct b43legacy_txhdr_fw3),
1435                                          1);
1436
1437                 if (meta->is_last_fragment) {
1438                         struct ieee80211_tx_info *info;
1439                         BUG_ON(!meta->skb);
1440                         info = IEEE80211_SKB_CB(meta->skb);
1441
1442                         /* preserve the confiured retry limit before clearing the status
1443                          * The xmit function has overwritten the rc's value with the actual
1444                          * retry limit done by the hardware */
1445                         retry_limit = info->status.rates[0].count;
1446                         ieee80211_tx_info_clear_status(info);
1447
1448                         if (status->acked)
1449                                 info->flags |= IEEE80211_TX_STAT_ACK;
1450
1451                         if (status->rts_count > dev->wl->hw->conf.short_frame_max_tx_count) {
1452                                 /*
1453                                  * If the short retries (RTS, not data frame) have exceeded
1454                                  * the limit, the hw will not have tried the selected rate,
1455                                  * but will have used the fallback rate instead.
1456                                  * Don't let the rate control count attempts for the selected
1457                                  * rate in this case, otherwise the statistics will be off.
1458                                  */
1459                                 info->status.rates[0].count = 0;
1460                                 info->status.rates[1].count = status->frame_count;
1461                         } else {
1462                                 if (status->frame_count > retry_limit) {
1463                                         info->status.rates[0].count = retry_limit;
1464                                         info->status.rates[1].count = status->frame_count -
1465                                                         retry_limit;
1466
1467                                 } else {
1468                                         info->status.rates[0].count = status->frame_count;
1469                                         info->status.rates[1].idx = -1;
1470                                 }
1471                         }
1472
1473                         /* Call back to inform the ieee80211 subsystem about the
1474                          * status of the transmission.
1475                          * Some fields of txstat are already filled in dma_tx().
1476                          */
1477                         ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
1478                         /* skb is freed by ieee80211_tx_status_irqsafe() */
1479                         meta->skb = NULL;
1480                 } else {
1481                         /* No need to call free_descriptor_buffer here, as
1482                          * this is only the txhdr, which is not allocated.
1483                          */
1484                         B43legacy_WARN_ON(meta->skb != NULL);
1485                 }
1486
1487                 /* Everything unmapped and free'd. So it's not used anymore. */
1488                 ring->used_slots--;
1489
1490                 if (meta->is_last_fragment)
1491                         break;
1492                 slot = next_slot(ring, slot);
1493         }
1494         dev->stats.last_tx = jiffies;
1495         if (ring->stopped) {
1496                 B43legacy_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1497                 ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
1498                 ring->stopped = 0;
1499                 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1500                         b43legacydbg(dev->wl, "Woke up TX ring %d\n",
1501                                ring->index);
1502         }
1503
1504         spin_unlock(&ring->lock);
1505 }
1506
1507 void b43legacy_dma_get_tx_stats(struct b43legacy_wldev *dev,
1508                               struct ieee80211_tx_queue_stats *stats)
1509 {
1510         const int nr_queues = dev->wl->hw->queues;
1511         struct b43legacy_dmaring *ring;
1512         unsigned long flags;
1513         int i;
1514
1515         for (i = 0; i < nr_queues; i++) {
1516                 ring = priority_to_txring(dev, i);
1517
1518                 spin_lock_irqsave(&ring->lock, flags);
1519                 stats[i].len = ring->used_slots / SLOTS_PER_PACKET;
1520                 stats[i].limit = ring->nr_slots / SLOTS_PER_PACKET;
1521                 stats[i].count = ring->nr_tx_packets;
1522                 spin_unlock_irqrestore(&ring->lock, flags);
1523         }
1524 }
1525
1526 static void dma_rx(struct b43legacy_dmaring *ring,
1527                    int *slot)
1528 {
1529         const struct b43legacy_dma_ops *ops = ring->ops;
1530         struct b43legacy_dmadesc_generic *desc;
1531         struct b43legacy_dmadesc_meta *meta;
1532         struct b43legacy_rxhdr_fw3 *rxhdr;
1533         struct sk_buff *skb;
1534         u16 len;
1535         int err;
1536         dma_addr_t dmaaddr;
1537
1538         desc = ops->idx2desc(ring, *slot, &meta);
1539
1540         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1541         skb = meta->skb;
1542
1543         if (ring->index == 3) {
1544                 /* We received an xmit status. */
1545                 struct b43legacy_hwtxstatus *hw =
1546                                 (struct b43legacy_hwtxstatus *)skb->data;
1547                 int i = 0;
1548
1549                 while (hw->cookie == 0) {
1550                         if (i > 100)
1551                                 break;
1552                         i++;
1553                         udelay(2);
1554                         barrier();
1555                 }
1556                 b43legacy_handle_hwtxstatus(ring->dev, hw);
1557                 /* recycle the descriptor buffer. */
1558                 sync_descbuffer_for_device(ring, meta->dmaaddr,
1559                                            ring->rx_buffersize);
1560
1561                 return;
1562         }
1563         rxhdr = (struct b43legacy_rxhdr_fw3 *)skb->data;
1564         len = le16_to_cpu(rxhdr->frame_len);
1565         if (len == 0) {
1566                 int i = 0;
1567
1568                 do {
1569                         udelay(2);
1570                         barrier();
1571                         len = le16_to_cpu(rxhdr->frame_len);
1572                 } while (len == 0 && i++ < 5);
1573                 if (unlikely(len == 0)) {
1574                         /* recycle the descriptor buffer. */
1575                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1576                                                    ring->rx_buffersize);
1577                         goto drop;
1578                 }
1579         }
1580         if (unlikely(len > ring->rx_buffersize)) {
1581                 /* The data did not fit into one descriptor buffer
1582                  * and is split over multiple buffers.
1583                  * This should never happen, as we try to allocate buffers
1584                  * big enough. So simply ignore this packet.
1585                  */
1586                 int cnt = 0;
1587                 s32 tmp = len;
1588
1589                 while (1) {
1590                         desc = ops->idx2desc(ring, *slot, &meta);
1591                         /* recycle the descriptor buffer. */
1592                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1593                                                    ring->rx_buffersize);
1594                         *slot = next_slot(ring, *slot);
1595                         cnt++;
1596                         tmp -= ring->rx_buffersize;
1597                         if (tmp <= 0)
1598                                 break;
1599                 }
1600                 b43legacyerr(ring->dev->wl, "DMA RX buffer too small "
1601                        "(len: %u, buffer: %u, nr-dropped: %d)\n",
1602                        len, ring->rx_buffersize, cnt);
1603                 goto drop;
1604         }
1605
1606         dmaaddr = meta->dmaaddr;
1607         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1608         if (unlikely(err)) {
1609                 b43legacydbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer()"
1610                              " failed\n");
1611                 sync_descbuffer_for_device(ring, dmaaddr,
1612                                            ring->rx_buffersize);
1613                 goto drop;
1614         }
1615
1616         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1617         skb_put(skb, len + ring->frameoffset);
1618         skb_pull(skb, ring->frameoffset);
1619
1620         b43legacy_rx(ring->dev, skb, rxhdr);
1621 drop:
1622         return;
1623 }
1624
1625 void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
1626 {
1627         const struct b43legacy_dma_ops *ops = ring->ops;
1628         int slot;
1629         int current_slot;
1630         int used_slots = 0;
1631
1632         B43legacy_WARN_ON(ring->tx);
1633         current_slot = ops->get_current_rxslot(ring);
1634         B43legacy_WARN_ON(!(current_slot >= 0 && current_slot <
1635                            ring->nr_slots));
1636
1637         slot = ring->current_slot;
1638         for (; slot != current_slot; slot = next_slot(ring, slot)) {
1639                 dma_rx(ring, &slot);
1640                 update_max_used_slots(ring, ++used_slots);
1641         }
1642         ops->set_current_rxslot(ring, slot);
1643         ring->current_slot = slot;
1644 }
1645
1646 static void b43legacy_dma_tx_suspend_ring(struct b43legacy_dmaring *ring)
1647 {
1648         unsigned long flags;
1649
1650         spin_lock_irqsave(&ring->lock, flags);
1651         B43legacy_WARN_ON(!ring->tx);
1652         ring->ops->tx_suspend(ring);
1653         spin_unlock_irqrestore(&ring->lock, flags);
1654 }
1655
1656 static void b43legacy_dma_tx_resume_ring(struct b43legacy_dmaring *ring)
1657 {
1658         unsigned long flags;
1659
1660         spin_lock_irqsave(&ring->lock, flags);
1661         B43legacy_WARN_ON(!ring->tx);
1662         ring->ops->tx_resume(ring);
1663         spin_unlock_irqrestore(&ring->lock, flags);
1664 }
1665
1666 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
1667 {
1668         b43legacy_power_saving_ctl_bits(dev, -1, 1);
1669         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring0);
1670         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring1);
1671         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring2);
1672         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring3);
1673         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring4);
1674         b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring5);
1675 }
1676
1677 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
1678 {
1679         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring5);
1680         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring4);
1681         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring3);
1682         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring2);
1683         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring1);
1684         b43legacy_dma_tx_resume_ring(dev->dma.tx_ring0);
1685         b43legacy_power_saving_ctl_bits(dev, -1, -1);
1686 }