46428ad5ab8428cc0fa4f857676ff505bbd1ed13
[linux-2.6.git] / drivers / net / wireless / b43 / phy_n.c
1 /*
2
3   Broadcom B43 wireless driver
4   IEEE 802.11n PHY support
5
6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8   This program is free software; you can redistribute it and/or modify
9   it under the terms of the GNU General Public License as published by
10   the Free Software Foundation; either version 2 of the License, or
11   (at your option) any later version.
12
13   This program is distributed in the hope that it will be useful,
14   but WITHOUT ANY WARRANTY; without even the implied warranty of
15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16   GNU General Public License for more details.
17
18   You should have received a copy of the GNU General Public License
19   along with this program; see the file COPYING.  If not, write to
20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21   Boston, MA 02110-1301, USA.
22
23 */
24
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/types.h>
28
29 #include "b43.h"
30 #include "phy_n.h"
31 #include "tables_nphy.h"
32 #include "radio_2055.h"
33 #include "radio_2056.h"
34 #include "main.h"
35
36 struct nphy_txgains {
37         u16 txgm[2];
38         u16 pga[2];
39         u16 pad[2];
40         u16 ipa[2];
41 };
42
43 struct nphy_iqcal_params {
44         u16 txgm;
45         u16 pga;
46         u16 pad;
47         u16 ipa;
48         u16 cal_gain;
49         u16 ncorr[5];
50 };
51
52 struct nphy_iq_est {
53         s32 iq0_prod;
54         u32 i0_pwr;
55         u32 q0_pwr;
56         s32 iq1_prod;
57         u32 i1_pwr;
58         u32 q1_pwr;
59 };
60
61 enum b43_nphy_rf_sequence {
62         B43_RFSEQ_RX2TX,
63         B43_RFSEQ_TX2RX,
64         B43_RFSEQ_RESET2RX,
65         B43_RFSEQ_UPDATE_GAINH,
66         B43_RFSEQ_UPDATE_GAINL,
67         B43_RFSEQ_UPDATE_GAINU,
68 };
69
70 enum b43_nphy_rssi_type {
71         B43_NPHY_RSSI_X = 0,
72         B43_NPHY_RSSI_Y,
73         B43_NPHY_RSSI_Z,
74         B43_NPHY_RSSI_PWRDET,
75         B43_NPHY_RSSI_TSSI_I,
76         B43_NPHY_RSSI_TSSI_Q,
77         B43_NPHY_RSSI_TBD,
78 };
79
80 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
81                                                 bool enable);
82 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
83                                         u8 *events, u8 *delays, u8 length);
84 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
85                                        enum b43_nphy_rf_sequence seq);
86 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
87                                                 u16 value, u8 core, bool off);
88 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
89                                                 u16 value, u8 core);
90
91 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
92 {//TODO
93 }
94
95 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
96 {//TODO
97 }
98
99 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
100                                                         bool ignore_tssi)
101 {//TODO
102         return B43_TXPWR_RES_DONE;
103 }
104
105 static void b43_chantab_radio_upload(struct b43_wldev *dev,
106                                 const struct b43_nphy_channeltab_entry_rev2 *e)
107 {
108         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
109         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
110         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
111         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
112         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
113
114         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
115         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
116         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
117         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
118         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
119
120         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
121         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
122         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
123         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
124         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
125
126         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
127         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
128         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
129         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
130         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
131
132         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
133         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
134         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
135         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
136         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
137
138         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
139         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
140 }
141
142 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
143                                 const struct b43_nphy_channeltab_entry_rev3 *e)
144 {
145         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
146         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
147         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
148         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
149         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
150         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
151                                         e->radio_syn_pll_loopfilter1);
152         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
153                                         e->radio_syn_pll_loopfilter2);
154         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
155                                         e->radio_syn_pll_loopfilter3);
156         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
157                                         e->radio_syn_pll_loopfilter4);
158         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
159                                         e->radio_syn_pll_loopfilter5);
160         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
161                                         e->radio_syn_reserved_addr27);
162         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
163                                         e->radio_syn_reserved_addr28);
164         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
165                                         e->radio_syn_reserved_addr29);
166         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
167                                         e->radio_syn_logen_vcobuf1);
168         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
169         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
170         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
171
172         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
173                                         e->radio_rx0_lnaa_tune);
174         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
175                                         e->radio_rx0_lnag_tune);
176
177         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
178                                         e->radio_tx0_intpaa_boost_tune);
179         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
180                                         e->radio_tx0_intpag_boost_tune);
181         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
182                                         e->radio_tx0_pada_boost_tune);
183         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
184                                         e->radio_tx0_padg_boost_tune);
185         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
186                                         e->radio_tx0_pgaa_boost_tune);
187         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
188                                         e->radio_tx0_pgag_boost_tune);
189         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
190                                         e->radio_tx0_mixa_boost_tune);
191         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
192                                         e->radio_tx0_mixg_boost_tune);
193
194         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
195                                         e->radio_rx1_lnaa_tune);
196         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
197                                         e->radio_rx1_lnag_tune);
198
199         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
200                                         e->radio_tx1_intpaa_boost_tune);
201         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
202                                         e->radio_tx1_intpag_boost_tune);
203         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
204                                         e->radio_tx1_pada_boost_tune);
205         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
206                                         e->radio_tx1_padg_boost_tune);
207         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
208                                         e->radio_tx1_pgaa_boost_tune);
209         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
210                                         e->radio_tx1_pgag_boost_tune);
211         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
212                                         e->radio_tx1_mixa_boost_tune);
213         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
214                                         e->radio_tx1_mixg_boost_tune);
215 }
216
217 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
218 static void b43_radio_2056_setup(struct b43_wldev *dev,
219                                 const struct b43_nphy_channeltab_entry_rev3 *e)
220 {
221         B43_WARN_ON(dev->phy.rev < 3);
222
223         b43_chantab_radio_2056_upload(dev, e);
224         /* TODO */
225         udelay(50);
226         /* VCO calibration */
227         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
228         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
229         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
230         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
231         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
232         udelay(300);
233 }
234
235 static void b43_chantab_phy_upload(struct b43_wldev *dev,
236                                    const struct b43_phy_n_sfo_cfg *e)
237 {
238         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
239         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
240         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
241         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
242         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
243         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
244 }
245
246 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
247 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
248 {
249         struct b43_phy_n *nphy = dev->phy.n;
250         u8 i;
251         u16 tmp;
252
253         if (nphy->hang_avoid)
254                 b43_nphy_stay_in_carrier_search(dev, 1);
255
256         nphy->txpwrctrl = enable;
257         if (!enable) {
258                 if (dev->phy.rev >= 3)
259                         ; /* TODO */
260
261                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
262                 for (i = 0; i < 84; i++)
263                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
264
265                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
266                 for (i = 0; i < 84; i++)
267                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
268
269                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
270                 if (dev->phy.rev >= 3)
271                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
272                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
273
274                 if (dev->phy.rev >= 3) {
275                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
276                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
277                 } else {
278                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
279                 }
280
281                 if (dev->phy.rev == 2)
282                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
283                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
284                 else if (dev->phy.rev < 2)
285                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
286                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
287
288                 if (dev->phy.rev < 2 && 0)
289                         ; /* TODO */
290         } else {
291                 b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
292         }
293
294         if (nphy->hang_avoid)
295                 b43_nphy_stay_in_carrier_search(dev, 0);
296 }
297
298 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
299 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
300 {
301         struct b43_phy_n *nphy = dev->phy.n;
302         struct ssb_sprom *sprom = dev->dev->bus_sprom;
303
304         u8 txpi[2], bbmult, i;
305         u16 tmp, radio_gain, dac_gain;
306         u16 freq = dev->phy.channel_freq;
307         u32 txgain;
308         /* u32 gaintbl; rev3+ */
309
310         if (nphy->hang_avoid)
311                 b43_nphy_stay_in_carrier_search(dev, 1);
312
313         if (dev->phy.rev >= 3) {
314                 txpi[0] = 40;
315                 txpi[1] = 40;
316         } else if (sprom->revision < 4) {
317                 txpi[0] = 72;
318                 txpi[1] = 72;
319         } else {
320                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
321                         txpi[0] = sprom->txpid2g[0];
322                         txpi[1] = sprom->txpid2g[1];
323                 } else if (freq >= 4900 && freq < 5100) {
324                         txpi[0] = sprom->txpid5gl[0];
325                         txpi[1] = sprom->txpid5gl[1];
326                 } else if (freq >= 5100 && freq < 5500) {
327                         txpi[0] = sprom->txpid5g[0];
328                         txpi[1] = sprom->txpid5g[1];
329                 } else if (freq >= 5500) {
330                         txpi[0] = sprom->txpid5gh[0];
331                         txpi[1] = sprom->txpid5gh[1];
332                 } else {
333                         txpi[0] = 91;
334                         txpi[1] = 91;
335                 }
336         }
337
338         /*
339         for (i = 0; i < 2; i++) {
340                 nphy->txpwrindex[i].index_internal = txpi[i];
341                 nphy->txpwrindex[i].index_internal_save = txpi[i];
342         }
343         */
344
345         for (i = 0; i < 2; i++) {
346                 if (dev->phy.rev >= 3) {
347                         /* FIXME: support 5GHz */
348                         txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
349                         radio_gain = (txgain >> 16) & 0x1FFFF;
350                 } else {
351                         txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
352                         radio_gain = (txgain >> 16) & 0x1FFF;
353                 }
354
355                 dac_gain = (txgain >> 8) & 0x3F;
356                 bbmult = txgain & 0xFF;
357
358                 if (dev->phy.rev >= 3) {
359                         if (i == 0)
360                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
361                         else
362                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
363                 } else {
364                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
365                 }
366
367                 if (i == 0)
368                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
369                 else
370                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
371
372                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
373                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
374
375                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
376                 tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
377
378                 if (i == 0)
379                         tmp = (tmp & 0x00FF) | (bbmult << 8);
380                 else
381                         tmp = (tmp & 0xFF00) | bbmult;
382
383                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
384                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
385
386                 if (0)
387                         ; /* TODO */
388         }
389
390         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
391
392         if (nphy->hang_avoid)
393                 b43_nphy_stay_in_carrier_search(dev, 0);
394 }
395
396
397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
398 static void b43_radio_2055_setup(struct b43_wldev *dev,
399                                 const struct b43_nphy_channeltab_entry_rev2 *e)
400 {
401         B43_WARN_ON(dev->phy.rev >= 3);
402
403         b43_chantab_radio_upload(dev, e);
404         udelay(50);
405         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
406         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
407         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
408         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
409         udelay(300);
410 }
411
412 static void b43_radio_init2055_pre(struct b43_wldev *dev)
413 {
414         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
415                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
416         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
417                     B43_NPHY_RFCTL_CMD_CHIP0PU |
418                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
419         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
420                     B43_NPHY_RFCTL_CMD_PORFORCE);
421 }
422
423 static void b43_radio_init2055_post(struct b43_wldev *dev)
424 {
425         struct b43_phy_n *nphy = dev->phy.n;
426         struct ssb_sprom *sprom = dev->dev->bus_sprom;
427         struct ssb_boardinfo *binfo = &(dev->sdev->bus->boardinfo);
428         int i;
429         u16 val;
430         bool workaround = false;
431
432         if (sprom->revision < 4)
433                 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM &&
434                                 binfo->type == 0x46D &&
435                                 binfo->rev >= 0x41);
436         else
437                 workaround =
438                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
439
440         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
441         if (workaround) {
442                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
443                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
444         }
445         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
446         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
447         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
448         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
449         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
450         msleep(1);
451         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
452         for (i = 0; i < 200; i++) {
453                 val = b43_radio_read(dev, B2055_CAL_COUT2);
454                 if (val & 0x80) {
455                         i = 0;
456                         break;
457                 }
458                 udelay(10);
459         }
460         if (i)
461                 b43err(dev->wl, "radio post init timeout\n");
462         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
463         b43_switch_channel(dev, dev->phy.channel);
464         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
465         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
466         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
467         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
468         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
469         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
470         if (!nphy->gain_boost) {
471                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
472                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
473         } else {
474                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
475                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
476         }
477         udelay(2);
478 }
479
480 /*
481  * Initialize a Broadcom 2055 N-radio
482  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
483  */
484 static void b43_radio_init2055(struct b43_wldev *dev)
485 {
486         b43_radio_init2055_pre(dev);
487         if (b43_status(dev) < B43_STAT_INITIALIZED) {
488                 /* Follow wl, not specs. Do not force uploading all regs */
489                 b2055_upload_inittab(dev, 0, 0);
490         } else {
491                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
492                 b2055_upload_inittab(dev, ghz5, 0);
493         }
494         b43_radio_init2055_post(dev);
495 }
496
497 static void b43_radio_init2056_pre(struct b43_wldev *dev)
498 {
499         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
500                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
501         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
502         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
503                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
504         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
505                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
506         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
507                     B43_NPHY_RFCTL_CMD_CHIP0PU);
508 }
509
510 static void b43_radio_init2056_post(struct b43_wldev *dev)
511 {
512         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
513         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
514         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
515         msleep(1);
516         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
517         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
518         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
519         /*
520         if (nphy->init_por)
521                 Call Radio 2056 Recalibrate
522         */
523 }
524
525 /*
526  * Initialize a Broadcom 2056 N-radio
527  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
528  */
529 static void b43_radio_init2056(struct b43_wldev *dev)
530 {
531         b43_radio_init2056_pre(dev);
532         b2056_upload_inittabs(dev, 0, 0);
533         b43_radio_init2056_post(dev);
534 }
535
536 /*
537  * Upload the N-PHY tables.
538  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
539  */
540 static void b43_nphy_tables_init(struct b43_wldev *dev)
541 {
542         if (dev->phy.rev < 3)
543                 b43_nphy_rev0_1_2_tables_init(dev);
544         else
545                 b43_nphy_rev3plus_tables_init(dev);
546 }
547
548 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
549 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
550 {
551         struct b43_phy_n *nphy = dev->phy.n;
552         enum ieee80211_band band;
553         u16 tmp;
554
555         if (!enable) {
556                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
557                                                        B43_NPHY_RFCTL_INTC1);
558                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
559                                                        B43_NPHY_RFCTL_INTC2);
560                 band = b43_current_band(dev->wl);
561                 if (dev->phy.rev >= 3) {
562                         if (band == IEEE80211_BAND_5GHZ)
563                                 tmp = 0x600;
564                         else
565                                 tmp = 0x480;
566                 } else {
567                         if (band == IEEE80211_BAND_5GHZ)
568                                 tmp = 0x180;
569                         else
570                                 tmp = 0x120;
571                 }
572                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
573                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
574         } else {
575                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
576                                 nphy->rfctrl_intc1_save);
577                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
578                                 nphy->rfctrl_intc2_save);
579         }
580 }
581
582 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
583 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
584 {
585         struct b43_phy_n *nphy = dev->phy.n;
586         u16 tmp;
587         enum ieee80211_band band = b43_current_band(dev->wl);
588         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
589                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
590
591         if (dev->phy.rev >= 3) {
592                 if (ipa) {
593                         tmp = 4;
594                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
595                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
596                 }
597
598                 tmp = 1;
599                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
600                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
601         }
602 }
603
604 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
605 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
606 {
607         u32 tmslow;
608
609         if (dev->phy.type != B43_PHYTYPE_N)
610                 return;
611
612         tmslow = ssb_read32(dev->sdev, SSB_TMSLOW);
613         if (force)
614                 tmslow |= SSB_TMSLOW_FGC;
615         else
616                 tmslow &= ~SSB_TMSLOW_FGC;
617         ssb_write32(dev->sdev, SSB_TMSLOW, tmslow);
618 }
619
620 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
621 static void b43_nphy_reset_cca(struct b43_wldev *dev)
622 {
623         u16 bbcfg;
624
625         b43_nphy_bmac_clock_fgc(dev, 1);
626         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
627         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
628         udelay(1);
629         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
630         b43_nphy_bmac_clock_fgc(dev, 0);
631         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
632 }
633
634 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
635 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
636 {
637         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
638
639         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
640         if (preamble == 1)
641                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
642         else
643                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
644
645         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
646 }
647
648 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
649 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
650 {
651         struct b43_phy_n *nphy = dev->phy.n;
652
653         bool override = false;
654         u16 chain = 0x33;
655
656         if (nphy->txrx_chain == 0) {
657                 chain = 0x11;
658                 override = true;
659         } else if (nphy->txrx_chain == 1) {
660                 chain = 0x22;
661                 override = true;
662         }
663
664         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
665                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
666                         chain);
667
668         if (override)
669                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
670                                 B43_NPHY_RFSEQMODE_CAOVER);
671         else
672                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
673                                 ~B43_NPHY_RFSEQMODE_CAOVER);
674 }
675
676 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
677 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
678                                 u16 samps, u8 time, bool wait)
679 {
680         int i;
681         u16 tmp;
682
683         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
684         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
685         if (wait)
686                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
687         else
688                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
689
690         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
691
692         for (i = 1000; i; i--) {
693                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
694                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
695                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
696                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
697                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
698                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
699                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
700                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
701
702                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
703                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
704                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
705                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
706                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
707                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
708                         return;
709                 }
710                 udelay(10);
711         }
712         memset(est, 0, sizeof(*est));
713 }
714
715 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
716 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
717                                         struct b43_phy_n_iq_comp *pcomp)
718 {
719         if (write) {
720                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
721                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
722                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
723                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
724         } else {
725                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
726                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
727                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
728                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
729         }
730 }
731
732 #if 0
733 /* Ready but not used anywhere */
734 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
735 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
736 {
737         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
738
739         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
740         if (core == 0) {
741                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
742                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
743         } else {
744                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
745                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
746         }
747         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
748         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
749         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
750         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
751         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
752         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
753         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
754         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
755 }
756
757 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
758 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
759 {
760         u8 rxval, txval;
761         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
762
763         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
764         if (core == 0) {
765                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
766                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
767         } else {
768                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
769                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
770         }
771         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
772         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
773         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
774         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
775         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
776         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
777         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
778         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
779
780         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
781         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
782
783         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
784                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
785                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
786         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
787                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
788         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
789                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
790         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
791                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
792
793         if (core == 0) {
794                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
795                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
796         } else {
797                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
798                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
799         }
800
801         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
802         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
803         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
804
805         if (core == 0) {
806                 rxval = 1;
807                 txval = 8;
808         } else {
809                 rxval = 4;
810                 txval = 2;
811         }
812         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
813         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
814 }
815 #endif
816
817 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
818 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
819 {
820         int i;
821         s32 iq;
822         u32 ii;
823         u32 qq;
824         int iq_nbits, qq_nbits;
825         int arsh, brsh;
826         u16 tmp, a, b;
827
828         struct nphy_iq_est est;
829         struct b43_phy_n_iq_comp old;
830         struct b43_phy_n_iq_comp new = { };
831         bool error = false;
832
833         if (mask == 0)
834                 return;
835
836         b43_nphy_rx_iq_coeffs(dev, false, &old);
837         b43_nphy_rx_iq_coeffs(dev, true, &new);
838         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
839         new = old;
840
841         for (i = 0; i < 2; i++) {
842                 if (i == 0 && (mask & 1)) {
843                         iq = est.iq0_prod;
844                         ii = est.i0_pwr;
845                         qq = est.q0_pwr;
846                 } else if (i == 1 && (mask & 2)) {
847                         iq = est.iq1_prod;
848                         ii = est.i1_pwr;
849                         qq = est.q1_pwr;
850                 } else {
851                         continue;
852                 }
853
854                 if (ii + qq < 2) {
855                         error = true;
856                         break;
857                 }
858
859                 iq_nbits = fls(abs(iq));
860                 qq_nbits = fls(qq);
861
862                 arsh = iq_nbits - 20;
863                 if (arsh >= 0) {
864                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
865                         tmp = ii >> arsh;
866                 } else {
867                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
868                         tmp = ii << -arsh;
869                 }
870                 if (tmp == 0) {
871                         error = true;
872                         break;
873                 }
874                 a /= tmp;
875
876                 brsh = qq_nbits - 11;
877                 if (brsh >= 0) {
878                         b = (qq << (31 - qq_nbits));
879                         tmp = ii >> brsh;
880                 } else {
881                         b = (qq << (31 - qq_nbits));
882                         tmp = ii << -brsh;
883                 }
884                 if (tmp == 0) {
885                         error = true;
886                         break;
887                 }
888                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
889
890                 if (i == 0 && (mask & 0x1)) {
891                         if (dev->phy.rev >= 3) {
892                                 new.a0 = a & 0x3FF;
893                                 new.b0 = b & 0x3FF;
894                         } else {
895                                 new.a0 = b & 0x3FF;
896                                 new.b0 = a & 0x3FF;
897                         }
898                 } else if (i == 1 && (mask & 0x2)) {
899                         if (dev->phy.rev >= 3) {
900                                 new.a1 = a & 0x3FF;
901                                 new.b1 = b & 0x3FF;
902                         } else {
903                                 new.a1 = b & 0x3FF;
904                                 new.b1 = a & 0x3FF;
905                         }
906                 }
907         }
908
909         if (error)
910                 new = old;
911
912         b43_nphy_rx_iq_coeffs(dev, true, &new);
913 }
914
915 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
916 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
917 {
918         u16 array[4];
919         int i;
920
921         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
922         for (i = 0; i < 4; i++)
923                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
924
925         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
926         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
927         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
928         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
929 }
930
931 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
932 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
933                                           const u16 *clip_st)
934 {
935         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
936         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
937 }
938
939 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
940 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
941 {
942         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
943         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
944 }
945
946 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
947 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
948 {
949         if (dev->phy.rev >= 3) {
950                 if (!init)
951                         return;
952                 if (0 /* FIXME */) {
953                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
954                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
955                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
956                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
957                 }
958         } else {
959                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
960                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
961
962                 ssb_chipco_gpio_control(&dev->sdev->bus->chipco, 0xFC00,
963                                         0xFC00);
964                 b43_write32(dev, B43_MMIO_MACCTL,
965                         b43_read32(dev, B43_MMIO_MACCTL) &
966                         ~B43_MACCTL_GPOUTSMSK);
967                 b43_write16(dev, B43_MMIO_GPIO_MASK,
968                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
969                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
970                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
971
972                 if (init) {
973                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
974                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
975                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
976                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
977                 }
978         }
979 }
980
981 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
982 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
983 {
984         u16 tmp;
985
986         if (dev->dev->core_rev == 16)
987                 b43_mac_suspend(dev);
988
989         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
990         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
991                 B43_NPHY_CLASSCTL_WAITEDEN);
992         tmp &= ~mask;
993         tmp |= (val & mask);
994         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
995
996         if (dev->dev->core_rev == 16)
997                 b43_mac_enable(dev);
998
999         return tmp;
1000 }
1001
1002 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
1003 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
1004 {
1005         struct b43_phy *phy = &dev->phy;
1006         struct b43_phy_n *nphy = phy->n;
1007
1008         if (enable) {
1009                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
1010                 if (nphy->deaf_count++ == 0) {
1011                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
1012                         b43_nphy_classifier(dev, 0x7, 0);
1013                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
1014                         b43_nphy_write_clip_detection(dev, clip);
1015                 }
1016                 b43_nphy_reset_cca(dev);
1017         } else {
1018                 if (--nphy->deaf_count == 0) {
1019                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
1020                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
1021                 }
1022         }
1023 }
1024
1025 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
1026 static void b43_nphy_stop_playback(struct b43_wldev *dev)
1027 {
1028         struct b43_phy_n *nphy = dev->phy.n;
1029         u16 tmp;
1030
1031         if (nphy->hang_avoid)
1032                 b43_nphy_stay_in_carrier_search(dev, 1);
1033
1034         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
1035         if (tmp & 0x1)
1036                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
1037         else if (tmp & 0x2)
1038                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1039
1040         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
1041
1042         if (nphy->bb_mult_save & 0x80000000) {
1043                 tmp = nphy->bb_mult_save & 0xFFFF;
1044                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1045                 nphy->bb_mult_save = 0;
1046         }
1047
1048         if (nphy->hang_avoid)
1049                 b43_nphy_stay_in_carrier_search(dev, 0);
1050 }
1051
1052 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
1053 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
1054 {
1055         struct b43_phy_n *nphy = dev->phy.n;
1056
1057         u8 channel = dev->phy.channel;
1058         int tone[2] = { 57, 58 };
1059         u32 noise[2] = { 0x3FF, 0x3FF };
1060
1061         B43_WARN_ON(dev->phy.rev < 3);
1062
1063         if (nphy->hang_avoid)
1064                 b43_nphy_stay_in_carrier_search(dev, 1);
1065
1066         if (nphy->gband_spurwar_en) {
1067                 /* TODO: N PHY Adjust Analog Pfbw (7) */
1068                 if (channel == 11 && dev->phy.is_40mhz)
1069                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
1070                 else
1071                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1072                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
1073         }
1074
1075         if (nphy->aband_spurwar_en) {
1076                 if (channel == 54) {
1077                         tone[0] = 0x20;
1078                         noise[0] = 0x25F;
1079                 } else if (channel == 38 || channel == 102 || channel == 118) {
1080                         if (0 /* FIXME */) {
1081                                 tone[0] = 0x20;
1082                                 noise[0] = 0x21F;
1083                         } else {
1084                                 tone[0] = 0;
1085                                 noise[0] = 0;
1086                         }
1087                 } else if (channel == 134) {
1088                         tone[0] = 0x20;
1089                         noise[0] = 0x21F;
1090                 } else if (channel == 151) {
1091                         tone[0] = 0x10;
1092                         noise[0] = 0x23F;
1093                 } else if (channel == 153 || channel == 161) {
1094                         tone[0] = 0x30;
1095                         noise[0] = 0x23F;
1096                 } else {
1097                         tone[0] = 0;
1098                         noise[0] = 0;
1099                 }
1100
1101                 if (!tone[0] && !noise[0])
1102                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
1103                 else
1104                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
1105         }
1106
1107         if (nphy->hang_avoid)
1108                 b43_nphy_stay_in_carrier_search(dev, 0);
1109 }
1110
1111 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
1112 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1113 {
1114         struct b43_phy_n *nphy = dev->phy.n;
1115
1116         u8 i;
1117         s16 tmp;
1118         u16 data[4];
1119         s16 gain[2];
1120         u16 minmax[2];
1121         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
1122
1123         if (nphy->hang_avoid)
1124                 b43_nphy_stay_in_carrier_search(dev, 1);
1125
1126         if (nphy->gain_boost) {
1127                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1128                         gain[0] = 6;
1129                         gain[1] = 6;
1130                 } else {
1131                         tmp = 40370 - 315 * dev->phy.channel;
1132                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
1133                         tmp = 23242 - 224 * dev->phy.channel;
1134                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
1135                 }
1136         } else {
1137                 gain[0] = 0;
1138                 gain[1] = 0;
1139         }
1140
1141         for (i = 0; i < 2; i++) {
1142                 if (nphy->elna_gain_config) {
1143                         data[0] = 19 + gain[i];
1144                         data[1] = 25 + gain[i];
1145                         data[2] = 25 + gain[i];
1146                         data[3] = 25 + gain[i];
1147                 } else {
1148                         data[0] = lna_gain[0] + gain[i];
1149                         data[1] = lna_gain[1] + gain[i];
1150                         data[2] = lna_gain[2] + gain[i];
1151                         data[3] = lna_gain[3] + gain[i];
1152                 }
1153                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
1154
1155                 minmax[i] = 23 + gain[i];
1156         }
1157
1158         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
1159                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
1160         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
1161                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
1162
1163         if (nphy->hang_avoid)
1164                 b43_nphy_stay_in_carrier_search(dev, 0);
1165 }
1166
1167 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1168 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1169 {
1170         struct b43_phy_n *nphy = dev->phy.n;
1171         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1172
1173         /* PHY rev 0, 1, 2 */
1174         u8 i, j;
1175         u8 code;
1176         u16 tmp;
1177         u8 rfseq_events[3] = { 6, 8, 7 };
1178         u8 rfseq_delays[3] = { 10, 30, 1 };
1179
1180         /* PHY rev >= 3 */
1181         bool ghz5;
1182         bool ext_lna;
1183         u16 rssi_gain;
1184         struct nphy_gain_ctl_workaround_entry *e;
1185         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1186         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1187
1188         if (dev->phy.rev >= 3) {
1189                 /* Prepare values */
1190                 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1191                         & B43_NPHY_BANDCTL_5GHZ;
1192                 ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1193                 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1194                 if (ghz5 && dev->phy.rev >= 5)
1195                         rssi_gain = 0x90;
1196                 else
1197                         rssi_gain = 0x50;
1198
1199                 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1200
1201                 /* Set Clip 2 detect */
1202                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1203                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1204                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1205                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1206
1207                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1208                                 0x17);
1209                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1210                                 0x17);
1211                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1212                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1213                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1214                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1215                 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1216                                 rssi_gain);
1217                 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1218                                 rssi_gain);
1219                 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1220                                 0x17);
1221                 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1222                                 0x17);
1223                 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1224                 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1225
1226                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1227                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1228                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1229                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1230                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1231                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1232                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1233                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1234                 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1235                 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1236                 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1237                 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1238
1239                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1240                 b43_phy_write(dev, 0x2A7, e->init_gain);
1241                 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1242                                         e->rfseq_init);
1243                 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1244
1245                 /* TODO: check defines. Do not match variables names */
1246                 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1247                 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1248                 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1249                 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1250                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1251                 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1252
1253                 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1254                 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1255                 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1256                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1257                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1258                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1259                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1260                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1261                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1262                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1263         } else {
1264                 /* Set Clip 2 detect */
1265                 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1266                                 B43_NPHY_C1_CGAINI_CL2DETECT);
1267                 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1268                                 B43_NPHY_C2_CGAINI_CL2DETECT);
1269
1270                 /* Set narrowband clip threshold */
1271                 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1272                 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1273
1274                 if (!dev->phy.is_40mhz) {
1275                         /* Set dwell lengths */
1276                         b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1277                         b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1278                         b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1279                         b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1280                 }
1281
1282                 /* Set wideband clip 2 threshold */
1283                 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1284                                 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
1285                                 21);
1286                 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1287                                 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
1288                                 21);
1289
1290                 if (!dev->phy.is_40mhz) {
1291                         b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1292                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1293                         b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1294                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1295                         b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1296                                 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1297                         b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1298                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1299                 }
1300
1301                 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1302
1303                 if (nphy->gain_boost) {
1304                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1305                             dev->phy.is_40mhz)
1306                                 code = 4;
1307                         else
1308                                 code = 5;
1309                 } else {
1310                         code = dev->phy.is_40mhz ? 6 : 7;
1311                 }
1312
1313                 /* Set HPVGA2 index */
1314                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
1315                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
1316                                 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1317                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
1318                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
1319                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1320
1321                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1322                 /* specs say about 2 loops, but wl does 4 */
1323                 for (i = 0; i < 4; i++)
1324                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1325                                                         (code << 8 | 0x7C));
1326
1327                 b43_nphy_adjust_lna_gain_table(dev);
1328
1329                 if (nphy->elna_gain_config) {
1330                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1331                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1332                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1333                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1334                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1335
1336                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1337                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1338                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1339                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1340                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1341
1342                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1343                         /* specs say about 2 loops, but wl does 4 */
1344                         for (i = 0; i < 4; i++)
1345                                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1346                                                         (code << 8 | 0x74));
1347                 }
1348
1349                 if (dev->phy.rev == 2) {
1350                         for (i = 0; i < 4; i++) {
1351                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1352                                                 (0x0400 * i) + 0x0020);
1353                                 for (j = 0; j < 21; j++) {
1354                                         tmp = j * (i < 2 ? 3 : 1);
1355                                         b43_phy_write(dev,
1356                                                 B43_NPHY_TABLE_DATALO, tmp);
1357                                 }
1358                         }
1359                 }
1360
1361                 b43_nphy_set_rf_sequence(dev, 5,
1362                                 rfseq_events, rfseq_delays, 3);
1363                 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1364                         ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1365                         0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1366
1367                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1368                         b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1369                                         0xFF80, 4);
1370         }
1371 }
1372
1373 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1374 static void b43_nphy_workarounds(struct b43_wldev *dev)
1375 {
1376         struct ssb_bus *bus = dev->sdev->bus;
1377         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1378         struct b43_phy *phy = &dev->phy;
1379         struct b43_phy_n *nphy = phy->n;
1380
1381         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1382         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1383
1384         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1385         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1386
1387         u16 tmp16;
1388         u32 tmp32;
1389
1390         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1391                 b43_nphy_classifier(dev, 1, 0);
1392         else
1393                 b43_nphy_classifier(dev, 1, 1);
1394
1395         if (nphy->hang_avoid)
1396                 b43_nphy_stay_in_carrier_search(dev, 1);
1397
1398         b43_phy_set(dev, B43_NPHY_IQFLIP,
1399                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1400
1401         if (dev->phy.rev >= 3) {
1402                 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1403                 tmp32 &= 0xffffff;
1404                 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1405
1406                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1407                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1408                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1409                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1410                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1411                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1412
1413                 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1414                 b43_phy_write(dev, 0x2AE, 0x000C);
1415
1416                 /* TODO */
1417
1418                 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1419                         0x2 : 0x9C40;
1420                 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1421
1422                 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1423
1424                 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1425                 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1426
1427                 b43_nphy_gain_ctrl_workarounds(dev);
1428
1429                 b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
1430                 b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
1431
1432                 /* TODO */
1433
1434                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1435                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1436                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1437                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1438                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1439                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1440                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1441                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1442                 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1443                 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1444
1445                 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1446
1447                 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1448                     b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1449                     (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1450                     b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1451                         tmp32 = 0x00088888;
1452                 else
1453                         tmp32 = 0x88888888;
1454                 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1455                 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1456                 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1457
1458                 if (dev->phy.rev == 4 &&
1459                     b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1460                         b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1461                                         0x70);
1462                         b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1463                                         0x70);
1464                 }
1465
1466                 b43_phy_write(dev, 0x224, 0x039C);
1467                 b43_phy_write(dev, 0x225, 0x0357);
1468                 b43_phy_write(dev, 0x226, 0x0317);
1469                 b43_phy_write(dev, 0x227, 0x02D7);
1470                 b43_phy_write(dev, 0x228, 0x039C);
1471                 b43_phy_write(dev, 0x229, 0x0357);
1472                 b43_phy_write(dev, 0x22A, 0x0317);
1473                 b43_phy_write(dev, 0x22B, 0x02D7);
1474                 b43_phy_write(dev, 0x22C, 0x039C);
1475                 b43_phy_write(dev, 0x22D, 0x0357);
1476                 b43_phy_write(dev, 0x22E, 0x0317);
1477                 b43_phy_write(dev, 0x22F, 0x02D7);
1478         } else {
1479                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1480                     nphy->band5g_pwrgain) {
1481                         b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1482                         b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1483                 } else {
1484                         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1485                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1486                 }
1487
1488                 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1489                 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1490                 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1491                 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1492
1493                 if (dev->phy.rev < 2) {
1494                         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1495                         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1496                         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1497                         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1498                         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1499                         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1500                 }
1501
1502                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1503                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1504                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1505                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1506
1507                 if (sprom->boardflags2_lo & 0x100 &&
1508                     bus->boardinfo.type == 0x8B) {
1509                         delays1[0] = 0x1;
1510                         delays1[5] = 0x14;
1511                 }
1512                 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1513                 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1514
1515                 b43_nphy_gain_ctrl_workarounds(dev);
1516
1517                 if (dev->phy.rev < 2) {
1518                         if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1519                                 b43_hf_write(dev, b43_hf_read(dev) |
1520                                                 B43_HF_MLADVW);
1521                 } else if (dev->phy.rev == 2) {
1522                         b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1523                         b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1524                 }
1525
1526                 if (dev->phy.rev < 2)
1527                         b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1528                                         ~B43_NPHY_SCRAM_SIGCTL_SCM);
1529
1530                 /* Set phase track alpha and beta */
1531                 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1532                 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1533                 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1534                 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1535                 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1536                 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1537
1538                 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1539                                 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1540                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1541                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1542                 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1543
1544                 if (dev->phy.rev == 2)
1545                         b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1546                                         B43_NPHY_FINERX2_CGC_DECGC);
1547         }
1548
1549         if (nphy->hang_avoid)
1550                 b43_nphy_stay_in_carrier_search(dev, 0);
1551 }
1552
1553 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1554 static int b43_nphy_load_samples(struct b43_wldev *dev,
1555                                         struct b43_c32 *samples, u16 len) {
1556         struct b43_phy_n *nphy = dev->phy.n;
1557         u16 i;
1558         u32 *data;
1559
1560         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1561         if (!data) {
1562                 b43err(dev->wl, "allocation for samples loading failed\n");
1563                 return -ENOMEM;
1564         }
1565         if (nphy->hang_avoid)
1566                 b43_nphy_stay_in_carrier_search(dev, 1);
1567
1568         for (i = 0; i < len; i++) {
1569                 data[i] = (samples[i].i & 0x3FF << 10);
1570                 data[i] |= samples[i].q & 0x3FF;
1571         }
1572         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1573
1574         kfree(data);
1575         if (nphy->hang_avoid)
1576                 b43_nphy_stay_in_carrier_search(dev, 0);
1577         return 0;
1578 }
1579
1580 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1581 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1582                                         bool test)
1583 {
1584         int i;
1585         u16 bw, len, rot, angle;
1586         struct b43_c32 *samples;
1587
1588
1589         bw = (dev->phy.is_40mhz) ? 40 : 20;
1590         len = bw << 3;
1591
1592         if (test) {
1593                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1594                         bw = 82;
1595                 else
1596                         bw = 80;
1597
1598                 if (dev->phy.is_40mhz)
1599                         bw <<= 1;
1600
1601                 len = bw << 1;
1602         }
1603
1604         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1605         if (!samples) {
1606                 b43err(dev->wl, "allocation for samples generation failed\n");
1607                 return 0;
1608         }
1609         rot = (((freq * 36) / bw) << 16) / 100;
1610         angle = 0;
1611
1612         for (i = 0; i < len; i++) {
1613                 samples[i] = b43_cordic(angle);
1614                 angle += rot;
1615                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1616                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1617         }
1618
1619         i = b43_nphy_load_samples(dev, samples, len);
1620         kfree(samples);
1621         return (i < 0) ? 0 : len;
1622 }
1623
1624 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1625 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1626                                         u16 wait, bool iqmode, bool dac_test)
1627 {
1628         struct b43_phy_n *nphy = dev->phy.n;
1629         int i;
1630         u16 seq_mode;
1631         u32 tmp;
1632
1633         if (nphy->hang_avoid)
1634                 b43_nphy_stay_in_carrier_search(dev, true);
1635
1636         if ((nphy->bb_mult_save & 0x80000000) == 0) {
1637                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1638                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1639         }
1640
1641         if (!dev->phy.is_40mhz)
1642                 tmp = 0x6464;
1643         else
1644                 tmp = 0x4747;
1645         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1646
1647         if (nphy->hang_avoid)
1648                 b43_nphy_stay_in_carrier_search(dev, false);
1649
1650         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1651
1652         if (loops != 0xFFFF)
1653                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1654         else
1655                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1656
1657         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1658
1659         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1660
1661         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1662         if (iqmode) {
1663                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1664                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1665         } else {
1666                 if (dac_test)
1667                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1668                 else
1669                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1670         }
1671         for (i = 0; i < 100; i++) {
1672                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1673                         i = 0;
1674                         break;
1675                 }
1676                 udelay(10);
1677         }
1678         if (i)
1679                 b43err(dev->wl, "run samples timeout\n");
1680
1681         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1682 }
1683
1684 /*
1685  * Transmits a known value for LO calibration
1686  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1687  */
1688 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1689                                 bool iqmode, bool dac_test)
1690 {
1691         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1692         if (samp == 0)
1693                 return -1;
1694         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1695         return 0;
1696 }
1697
1698 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1699 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1700 {
1701         struct b43_phy_n *nphy = dev->phy.n;
1702         int i, j;
1703         u32 tmp;
1704         u32 cur_real, cur_imag, real_part, imag_part;
1705
1706         u16 buffer[7];
1707
1708         if (nphy->hang_avoid)
1709                 b43_nphy_stay_in_carrier_search(dev, true);
1710
1711         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1712
1713         for (i = 0; i < 2; i++) {
1714                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1715                         (buffer[i * 2 + 1] & 0x3FF);
1716                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1717                                 (((i + 26) << 10) | 320));
1718                 for (j = 0; j < 128; j++) {
1719                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1720                                         ((tmp >> 16) & 0xFFFF));
1721                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1722                                         (tmp & 0xFFFF));
1723                 }
1724         }
1725
1726         for (i = 0; i < 2; i++) {
1727                 tmp = buffer[5 + i];
1728                 real_part = (tmp >> 8) & 0xFF;
1729                 imag_part = (tmp & 0xFF);
1730                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1731                                 (((i + 26) << 10) | 448));
1732
1733                 if (dev->phy.rev >= 3) {
1734                         cur_real = real_part;
1735                         cur_imag = imag_part;
1736                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1737                 }
1738
1739                 for (j = 0; j < 128; j++) {
1740                         if (dev->phy.rev < 3) {
1741                                 cur_real = (real_part * loscale[j] + 128) >> 8;
1742                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1743                                 tmp = ((cur_real & 0xFF) << 8) |
1744                                         (cur_imag & 0xFF);
1745                         }
1746                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1747                                         ((tmp >> 16) & 0xFFFF));
1748                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1749                                         (tmp & 0xFFFF));
1750                 }
1751         }
1752
1753         if (dev->phy.rev >= 3) {
1754                 b43_shm_write16(dev, B43_SHM_SHARED,
1755                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1756                 b43_shm_write16(dev, B43_SHM_SHARED,
1757                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1758         }
1759
1760         if (nphy->hang_avoid)
1761                 b43_nphy_stay_in_carrier_search(dev, false);
1762 }
1763
1764 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1765 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1766                                         u8 *events, u8 *delays, u8 length)
1767 {
1768         struct b43_phy_n *nphy = dev->phy.n;
1769         u8 i;
1770         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1771         u16 offset1 = cmd << 4;
1772         u16 offset2 = offset1 + 0x80;
1773
1774         if (nphy->hang_avoid)
1775                 b43_nphy_stay_in_carrier_search(dev, true);
1776
1777         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1778         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1779
1780         for (i = length; i < 16; i++) {
1781                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1782                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1783         }
1784
1785         if (nphy->hang_avoid)
1786                 b43_nphy_stay_in_carrier_search(dev, false);
1787 }
1788
1789 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1790 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1791                                        enum b43_nphy_rf_sequence seq)
1792 {
1793         static const u16 trigger[] = {
1794                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
1795                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
1796                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
1797                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
1798                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
1799                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
1800         };
1801         int i;
1802         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1803
1804         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1805
1806         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1807                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1808         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1809         for (i = 0; i < 200; i++) {
1810                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1811                         goto ok;
1812                 msleep(1);
1813         }
1814         b43err(dev->wl, "RF sequence status timeout\n");
1815 ok:
1816         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1817 }
1818
1819 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1820 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1821                                                 u16 value, u8 core, bool off)
1822 {
1823         int i;
1824         u8 index = fls(field);
1825         u8 addr, en_addr, val_addr;
1826         /* we expect only one bit set */
1827         B43_WARN_ON(field & (~(1 << (index - 1))));
1828
1829         if (dev->phy.rev >= 3) {
1830                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1831                 for (i = 0; i < 2; i++) {
1832                         if (index == 0 || index == 16) {
1833                                 b43err(dev->wl,
1834                                         "Unsupported RF Ctrl Override call\n");
1835                                 return;
1836                         }
1837
1838                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1839                         en_addr = B43_PHY_N((i == 0) ?
1840                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1841                         val_addr = B43_PHY_N((i == 0) ?
1842                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1843
1844                         if (off) {
1845                                 b43_phy_mask(dev, en_addr, ~(field));
1846                                 b43_phy_mask(dev, val_addr,
1847                                                 ~(rf_ctrl->val_mask));
1848                         } else {
1849                                 if (core == 0 || ((1 << core) & i) != 0) {
1850                                         b43_phy_set(dev, en_addr, field);
1851                                         b43_phy_maskset(dev, val_addr,
1852                                                 ~(rf_ctrl->val_mask),
1853                                                 (value << rf_ctrl->val_shift));
1854                                 }
1855                         }
1856                 }
1857         } else {
1858                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1859                 if (off) {
1860                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1861                         value = 0;
1862                 } else {
1863                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1864                 }
1865
1866                 for (i = 0; i < 2; i++) {
1867                         if (index <= 1 || index == 16) {
1868                                 b43err(dev->wl,
1869                                         "Unsupported RF Ctrl Override call\n");
1870                                 return;
1871                         }
1872
1873                         if (index == 2 || index == 10 ||
1874                             (index >= 13 && index <= 15)) {
1875                                 core = 1;
1876                         }
1877
1878                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1879                         addr = B43_PHY_N((i == 0) ?
1880                                 rf_ctrl->addr0 : rf_ctrl->addr1);
1881
1882                         if ((core & (1 << i)) != 0)
1883                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1884                                                 (value << rf_ctrl->shift));
1885
1886                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1887                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1888                                         B43_NPHY_RFCTL_CMD_START);
1889                         udelay(1);
1890                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1891                 }
1892         }
1893 }
1894
1895 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1896 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1897                                                 u16 value, u8 core)
1898 {
1899         u8 i, j;
1900         u16 reg, tmp, val;
1901
1902         B43_WARN_ON(dev->phy.rev < 3);
1903         B43_WARN_ON(field > 4);
1904
1905         for (i = 0; i < 2; i++) {
1906                 if ((core == 1 && i == 1) || (core == 2 && !i))
1907                         continue;
1908
1909                 reg = (i == 0) ?
1910                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1911                 b43_phy_mask(dev, reg, 0xFBFF);
1912
1913                 switch (field) {
1914                 case 0:
1915                         b43_phy_write(dev, reg, 0);
1916                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1917                         break;
1918                 case 1:
1919                         if (!i) {
1920                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1921                                                 0xFC3F, (value << 6));
1922                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1923                                                 0xFFFE, 1);
1924                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1925                                                 B43_NPHY_RFCTL_CMD_START);
1926                                 for (j = 0; j < 100; j++) {
1927                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1928                                                 j = 0;
1929                                                 break;
1930                                         }
1931                                         udelay(10);
1932                                 }
1933                                 if (j)
1934                                         b43err(dev->wl,
1935                                                 "intc override timeout\n");
1936                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1937                                                 0xFFFE);
1938                         } else {
1939                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1940                                                 0xFC3F, (value << 6));
1941                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1942                                                 0xFFFE, 1);
1943                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1944                                                 B43_NPHY_RFCTL_CMD_RXTX);
1945                                 for (j = 0; j < 100; j++) {
1946                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1947                                                 j = 0;
1948                                                 break;
1949                                         }
1950                                         udelay(10);
1951                                 }
1952                                 if (j)
1953                                         b43err(dev->wl,
1954                                                 "intc override timeout\n");
1955                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1956                                                 0xFFFE);
1957                         }
1958                         break;
1959                 case 2:
1960                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1961                                 tmp = 0x0020;
1962                                 val = value << 5;
1963                         } else {
1964                                 tmp = 0x0010;
1965                                 val = value << 4;
1966                         }
1967                         b43_phy_maskset(dev, reg, ~tmp, val);
1968                         break;
1969                 case 3:
1970                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1971                                 tmp = 0x0001;
1972                                 val = value;
1973                         } else {
1974                                 tmp = 0x0004;
1975                                 val = value << 2;
1976                         }
1977                         b43_phy_maskset(dev, reg, ~tmp, val);
1978                         break;
1979                 case 4:
1980                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1981                                 tmp = 0x0002;
1982                                 val = value << 1;
1983                         } else {
1984                                 tmp = 0x0008;
1985                                 val = value << 3;
1986                         }
1987                         b43_phy_maskset(dev, reg, ~tmp, val);
1988                         break;
1989                 }
1990         }
1991 }
1992
1993 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
1994 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1995 {
1996         unsigned int i;
1997         u16 val;
1998
1999         val = 0x1E1F;
2000         for (i = 0; i < 16; i++) {
2001                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
2002                 val -= 0x202;
2003         }
2004         val = 0x3E3F;
2005         for (i = 0; i < 16; i++) {
2006                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
2007                 val -= 0x202;
2008         }
2009         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
2010 }
2011
2012 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
2013 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
2014                                         s8 offset, u8 core, u8 rail,
2015                                         enum b43_nphy_rssi_type type)
2016 {
2017         u16 tmp;
2018         bool core1or5 = (core == 1) || (core == 5);
2019         bool core2or5 = (core == 2) || (core == 5);
2020
2021         offset = clamp_val(offset, -32, 31);
2022         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
2023
2024         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2025                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
2026         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2027                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
2028         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
2029                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
2030         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
2031                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
2032
2033         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2034                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
2035         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2036                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
2037         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
2038                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
2039         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
2040                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
2041
2042         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2043                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
2044         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2045                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
2046         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
2047                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
2048         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
2049                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
2050
2051         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2052                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
2053         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2054                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
2055         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
2056                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
2057         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
2058                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
2059
2060         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2061                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
2062         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2063                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
2064         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
2065                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
2066         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
2067                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
2068
2069         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
2070                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
2071         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
2072                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
2073
2074         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2075                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
2076         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
2077                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
2078 }
2079
2080 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2081 {
2082         u16 val;
2083
2084         if (type < 3)
2085                 val = 0;
2086         else if (type == 6)
2087                 val = 1;
2088         else if (type == 3)
2089                 val = 2;
2090         else
2091                 val = 3;
2092
2093         val = (val << 12) | (val << 14);
2094         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
2095         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
2096
2097         if (type < 3) {
2098                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
2099                                 (type + 1) << 4);
2100                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
2101                                 (type + 1) << 4);
2102         }
2103
2104         if (code == 0) {
2105                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
2106                 if (type < 3) {
2107                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2108                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2109                                   B43_NPHY_RFCTL_CMD_CORESEL));
2110                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
2111                                 ~(0x1 << 12 |
2112                                   0x1 << 5 |
2113                                   0x1 << 1 |
2114                                   0x1));
2115                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
2116                                 ~B43_NPHY_RFCTL_CMD_START);
2117                         udelay(20);
2118                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2119                 }
2120         } else {
2121                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
2122                 if (type < 3) {
2123                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
2124                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
2125                                   B43_NPHY_RFCTL_CMD_CORESEL),
2126                                 (B43_NPHY_RFCTL_CMD_RXEN |
2127                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
2128                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
2129                                 (0x1 << 12 |
2130                                   0x1 << 5 |
2131                                   0x1 << 1 |
2132                                   0x1));
2133                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
2134                                 B43_NPHY_RFCTL_CMD_START);
2135                         udelay(20);
2136                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
2137                 }
2138         }
2139 }
2140
2141 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2142 {
2143         struct b43_phy_n *nphy = dev->phy.n;
2144         u8 i;
2145         u16 reg, val;
2146
2147         if (code == 0) {
2148                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
2149                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
2150                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
2151                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
2152                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
2153                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
2154                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
2155                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
2156         } else {
2157                 for (i = 0; i < 2; i++) {
2158                         if ((code == 1 && i == 1) || (code == 2 && !i))
2159                                 continue;
2160
2161                         reg = (i == 0) ?
2162                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
2163                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
2164
2165                         if (type < 3) {
2166                                 reg = (i == 0) ?
2167                                         B43_NPHY_AFECTL_C1 :
2168                                         B43_NPHY_AFECTL_C2;
2169                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
2170
2171                                 reg = (i == 0) ?
2172                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
2173                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
2174                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
2175
2176                                 if (type == 0)
2177                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
2178                                 else if (type == 1)
2179                                         val = 16;
2180                                 else
2181                                         val = 32;
2182                                 b43_phy_set(dev, reg, val);
2183
2184                                 reg = (i == 0) ?
2185                                         B43_NPHY_TXF_40CO_B1S0 :
2186                                         B43_NPHY_TXF_40CO_B32S1;
2187                                 b43_phy_set(dev, reg, 0x0020);
2188                         } else {
2189                                 if (type == 6)
2190                                         val = 0x0100;
2191                                 else if (type == 3)
2192                                         val = 0x0200;
2193                                 else
2194                                         val = 0x0300;
2195
2196                                 reg = (i == 0) ?
2197                                         B43_NPHY_AFECTL_C1 :
2198                                         B43_NPHY_AFECTL_C2;
2199
2200                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
2201                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
2202
2203                                 if (type != 3 && type != 6) {
2204                                         enum ieee80211_band band =
2205                                                 b43_current_band(dev->wl);
2206
2207                                         if ((nphy->ipa2g_on &&
2208                                                 band == IEEE80211_BAND_2GHZ) ||
2209                                                 (nphy->ipa5g_on &&
2210                                                 band == IEEE80211_BAND_5GHZ))
2211                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2212                                         else
2213                                                 val = 0x11;
2214                                         reg = (i == 0) ? 0x2000 : 0x3000;
2215                                         reg |= B2055_PADDRV;
2216                                         b43_radio_write16(dev, reg, val);
2217
2218                                         reg = (i == 0) ?
2219                                                 B43_NPHY_AFECTL_OVER1 :
2220                                                 B43_NPHY_AFECTL_OVER;
2221                                         b43_phy_set(dev, reg, 0x0200);
2222                                 }
2223                         }
2224                 }
2225         }
2226 }
2227
2228 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
2229 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
2230 {
2231         if (dev->phy.rev >= 3)
2232                 b43_nphy_rev3_rssi_select(dev, code, type);
2233         else
2234                 b43_nphy_rev2_rssi_select(dev, code, type);
2235 }
2236
2237 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
2238 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
2239 {
2240         int i;
2241         for (i = 0; i < 2; i++) {
2242                 if (type == 2) {
2243                         if (i == 0) {
2244                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
2245                                                   0xFC, buf[0]);
2246                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2247                                                   0xFC, buf[1]);
2248                         } else {
2249                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
2250                                                   0xFC, buf[2 * i]);
2251                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2252                                                   0xFC, buf[2 * i + 1]);
2253                         }
2254                 } else {
2255                         if (i == 0)
2256                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
2257                                                   0xF3, buf[0] << 2);
2258                         else
2259                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
2260                                                   0xF3, buf[2 * i + 1] << 2);
2261                 }
2262         }
2263 }
2264
2265 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
2266 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
2267                                 u8 nsamp)
2268 {
2269         int i;
2270         int out;
2271         u16 save_regs_phy[9];
2272         u16 s[2];
2273
2274         if (dev->phy.rev >= 3) {
2275                 save_regs_phy[0] = b43_phy_read(dev,
2276                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
2277                 save_regs_phy[1] = b43_phy_read(dev,
2278                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
2279                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2280                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2281                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2282                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2283                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
2284                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
2285                 save_regs_phy[8] = 0;
2286         } else {
2287                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2288                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2289                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2290                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
2291                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2292                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2293                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2294                 save_regs_phy[7] = 0;
2295                 save_regs_phy[8] = 0;
2296         }
2297
2298         b43_nphy_rssi_select(dev, 5, type);
2299
2300         if (dev->phy.rev < 2) {
2301                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
2302                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
2303         }
2304
2305         for (i = 0; i < 4; i++)
2306                 buf[i] = 0;
2307
2308         for (i = 0; i < nsamp; i++) {
2309                 if (dev->phy.rev < 2) {
2310                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
2311                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
2312                 } else {
2313                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
2314                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
2315                 }
2316
2317                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
2318                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
2319                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
2320                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
2321         }
2322         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
2323                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
2324
2325         if (dev->phy.rev < 2)
2326                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
2327
2328         if (dev->phy.rev >= 3) {
2329                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
2330                                 save_regs_phy[0]);
2331                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
2332                                 save_regs_phy[1]);
2333                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
2334                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
2335                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
2336                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
2337                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
2338                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
2339         } else {
2340                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
2341                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
2342                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
2343                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
2344                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
2345                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
2346                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
2347         }
2348
2349         return out;
2350 }
2351
2352 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
2353 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
2354 {
2355         int i, j;
2356         u8 state[4];
2357         u8 code, val;
2358         u16 class, override;
2359         u8 regs_save_radio[2];
2360         u16 regs_save_phy[2];
2361
2362         s8 offset[4];
2363         u8 core;
2364         u8 rail;
2365
2366         u16 clip_state[2];
2367         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
2368         s32 results_min[4] = { };
2369         u8 vcm_final[4] = { };
2370         s32 results[4][4] = { };
2371         s32 miniq[4][2] = { };
2372
2373         if (type == 2) {
2374                 code = 0;
2375                 val = 6;
2376         } else if (type < 2) {
2377                 code = 25;
2378                 val = 4;
2379         } else {
2380                 B43_WARN_ON(1);
2381                 return;
2382         }
2383
2384         class = b43_nphy_classifier(dev, 0, 0);
2385         b43_nphy_classifier(dev, 7, 4);
2386         b43_nphy_read_clip_detection(dev, clip_state);
2387         b43_nphy_write_clip_detection(dev, clip_off);
2388
2389         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2390                 override = 0x140;
2391         else
2392                 override = 0x110;
2393
2394         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2395         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
2396         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
2397         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
2398
2399         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2400         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
2401         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
2402         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
2403
2404         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
2405         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
2406         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
2407         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
2408         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
2409         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
2410
2411         b43_nphy_rssi_select(dev, 5, type);
2412         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
2413         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
2414
2415         for (i = 0; i < 4; i++) {
2416                 u8 tmp[4];
2417                 for (j = 0; j < 4; j++)
2418                         tmp[j] = i;
2419                 if (type != 1)
2420                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
2421                 b43_nphy_poll_rssi(dev, type, results[i], 8);
2422                 if (type < 2)
2423                         for (j = 0; j < 2; j++)
2424                                 miniq[i][j] = min(results[i][2 * j],
2425                                                 results[i][2 * j + 1]);
2426         }
2427
2428         for (i = 0; i < 4; i++) {
2429                 s32 mind = 40;
2430                 u8 minvcm = 0;
2431                 s32 minpoll = 249;
2432                 s32 curr;
2433                 for (j = 0; j < 4; j++) {
2434                         if (type == 2)
2435                                 curr = abs(results[j][i]);
2436                         else
2437                                 curr = abs(miniq[j][i / 2] - code * 8);
2438
2439                         if (curr < mind) {
2440                                 mind = curr;
2441                                 minvcm = j;
2442                         }
2443
2444                         if (results[j][i] < minpoll)
2445                                 minpoll = results[j][i];
2446                 }
2447                 results_min[i] = minpoll;
2448                 vcm_final[i] = minvcm;
2449         }
2450
2451         if (type != 1)
2452                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2453
2454         for (i = 0; i < 4; i++) {
2455                 offset[i] = (code * 8) - results[vcm_final[i]][i];
2456
2457                 if (offset[i] < 0)
2458                         offset[i] = -((abs(offset[i]) + 4) / 8);
2459                 else
2460                         offset[i] = (offset[i] + 4) / 8;
2461
2462                 if (results_min[i] == 248)
2463                         offset[i] = code - 32;
2464
2465                 core = (i / 2) ? 2 : 1;
2466                 rail = (i % 2) ? 1 : 0;
2467
2468                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2469                                                 type);
2470         }
2471
2472         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2473         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2474
2475         switch (state[2]) {
2476         case 1:
2477                 b43_nphy_rssi_select(dev, 1, 2);
2478                 break;
2479         case 4:
2480                 b43_nphy_rssi_select(dev, 1, 0);
2481                 break;
2482         case 2:
2483                 b43_nphy_rssi_select(dev, 1, 1);
2484                 break;
2485         default:
2486                 b43_nphy_rssi_select(dev, 1, 1);
2487                 break;
2488         }
2489
2490         switch (state[3]) {
2491         case 1:
2492                 b43_nphy_rssi_select(dev, 2, 2);
2493                 break;
2494         case 4:
2495                 b43_nphy_rssi_select(dev, 2, 0);
2496                 break;
2497         default:
2498                 b43_nphy_rssi_select(dev, 2, 1);
2499                 break;
2500         }
2501
2502         b43_nphy_rssi_select(dev, 0, type);
2503
2504         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2505         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2506         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2507         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2508
2509         b43_nphy_classifier(dev, 7, class);
2510         b43_nphy_write_clip_detection(dev, clip_state);
2511         /* Specs don't say about reset here, but it makes wl and b43 dumps
2512            identical, it really seems wl performs this */
2513         b43_nphy_reset_cca(dev);
2514 }
2515
2516 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2517 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2518 {
2519         /* TODO */
2520 }
2521
2522 /*
2523  * RSSI Calibration
2524  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2525  */
2526 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2527 {
2528         if (dev->phy.rev >= 3) {
2529                 b43_nphy_rev3_rssi_cal(dev);
2530         } else {
2531                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
2532                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
2533                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
2534         }
2535 }
2536
2537 /*
2538  * Restore RSSI Calibration
2539  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2540  */
2541 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2542 {
2543         struct b43_phy_n *nphy = dev->phy.n;
2544
2545         u16 *rssical_radio_regs = NULL;
2546         u16 *rssical_phy_regs = NULL;
2547
2548         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2549                 if (!nphy->rssical_chanspec_2G.center_freq)
2550                         return;
2551                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2552                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2553         } else {
2554                 if (!nphy->rssical_chanspec_5G.center_freq)
2555                         return;
2556                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2557                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2558         }
2559
2560         /* TODO use some definitions */
2561         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2562         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2563
2564         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2565         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2566         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2567         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2568
2569         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2570         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2571         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2572         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2573
2574         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2575         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2576         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2577         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2578 }
2579
2580 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2581 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2582 {
2583         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2584                 if (dev->phy.rev >= 6) {
2585                         /* TODO If the chip is 47162
2586                                 return txpwrctrl_tx_gain_ipa_rev5 */
2587                         return txpwrctrl_tx_gain_ipa_rev6;
2588                 } else if (dev->phy.rev >= 5) {
2589                         return txpwrctrl_tx_gain_ipa_rev5;
2590                 } else {
2591                         return txpwrctrl_tx_gain_ipa;
2592                 }
2593         } else {
2594                 return txpwrctrl_tx_gain_ipa_5g;
2595         }
2596 }
2597
2598 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2599 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2600 {
2601         struct b43_phy_n *nphy = dev->phy.n;
2602         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2603         u16 tmp;
2604         u8 offset, i;
2605
2606         if (dev->phy.rev >= 3) {
2607             for (i = 0; i < 2; i++) {
2608                 tmp = (i == 0) ? 0x2000 : 0x3000;
2609                 offset = i * 11;
2610
2611                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2612                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2613                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2614                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2615                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2616                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2617                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2618                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2619                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2620                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2621                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2622
2623                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2624                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2625                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2626                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2627                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2628                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2629                         if (nphy->ipa5g_on) {
2630                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2631                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2632                         } else {
2633                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2634                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2635                         }
2636                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2637                 } else {
2638                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2639                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2640                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2641                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2642                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2643                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2644                         if (nphy->ipa2g_on) {
2645                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2646                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2647                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2648                         } else {
2649                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2650                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2651                         }
2652                 }
2653                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2654                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2655                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2656             }
2657         } else {
2658                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2659                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2660
2661                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2662                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2663
2664                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2665                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2666
2667                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2668                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2669
2670                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2671                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2672
2673                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2674                     B43_NPHY_BANDCTL_5GHZ)) {
2675                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2676                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2677                 } else {
2678                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2679                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2680                 }
2681
2682                 if (dev->phy.rev < 2) {
2683                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2684                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2685                 } else {
2686                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2687                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2688                 }
2689         }
2690 }
2691
2692 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2693 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2694                                         struct nphy_txgains target,
2695                                         struct nphy_iqcal_params *params)
2696 {
2697         int i, j, indx;
2698         u16 gain;
2699
2700         if (dev->phy.rev >= 3) {
2701                 params->txgm = target.txgm[core];
2702                 params->pga = target.pga[core];
2703                 params->pad = target.pad[core];
2704                 params->ipa = target.ipa[core];
2705                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2706                                         (params->pad << 4) | (params->ipa);
2707                 for (j = 0; j < 5; j++)
2708                         params->ncorr[j] = 0x79;
2709         } else {
2710                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2711                         (target.txgm[core] << 8);
2712
2713                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2714                         1 : 0;
2715                 for (i = 0; i < 9; i++)
2716                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2717                                 break;
2718                 i = min(i, 8);
2719
2720                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2721                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2722                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2723                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2724                                         (params->pad << 2);
2725                 for (j = 0; j < 4; j++)
2726                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2727         }
2728 }
2729
2730 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2731 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2732 {
2733         struct b43_phy_n *nphy = dev->phy.n;
2734         int i;
2735         u16 scale, entry;
2736
2737         u16 tmp = nphy->txcal_bbmult;
2738         if (core == 0)
2739                 tmp >>= 8;
2740         tmp &= 0xff;
2741
2742         for (i = 0; i < 18; i++) {
2743                 scale = (ladder_lo[i].percent * tmp) / 100;
2744                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2745                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2746
2747                 scale = (ladder_iq[i].percent * tmp) / 100;
2748                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2749                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2750         }
2751 }
2752
2753 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2754 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2755 {
2756         int i;
2757         for (i = 0; i < 15; i++)
2758                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2759                                 tbl_tx_filter_coef_rev4[2][i]);
2760 }
2761
2762 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2763 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2764 {
2765         int i, j;
2766         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2767         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2768
2769         for (i = 0; i < 3; i++)
2770                 for (j = 0; j < 15; j++)
2771                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2772                                         tbl_tx_filter_coef_rev4[i][j]);
2773
2774         if (dev->phy.is_40mhz) {
2775                 for (j = 0; j < 15; j++)
2776                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2777                                         tbl_tx_filter_coef_rev4[3][j]);
2778         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2779                 for (j = 0; j < 15; j++)
2780                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2781                                         tbl_tx_filter_coef_rev4[5][j]);
2782         }
2783
2784         if (dev->phy.channel == 14)
2785                 for (j = 0; j < 15; j++)
2786                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2787                                         tbl_tx_filter_coef_rev4[6][j]);
2788 }
2789
2790 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2791 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2792 {
2793         struct b43_phy_n *nphy = dev->phy.n;
2794
2795         u16 curr_gain[2];
2796         struct nphy_txgains target;
2797         const u32 *table = NULL;
2798
2799         if (!nphy->txpwrctrl) {
2800                 int i;
2801
2802                 if (nphy->hang_avoid)
2803                         b43_nphy_stay_in_carrier_search(dev, true);
2804                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2805                 if (nphy->hang_avoid)
2806                         b43_nphy_stay_in_carrier_search(dev, false);
2807
2808                 for (i = 0; i < 2; ++i) {
2809                         if (dev->phy.rev >= 3) {
2810                                 target.ipa[i] = curr_gain[i] & 0x000F;
2811                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2812                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2813                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2814                         } else {
2815                                 target.ipa[i] = curr_gain[i] & 0x0003;
2816                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2817                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2818                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2819                         }
2820                 }
2821         } else {
2822                 int i;
2823                 u16 index[2];
2824                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2825                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2826                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2827                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2828                         B43_NPHY_TXPCTL_STAT_BIDX) >>
2829                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2830
2831                 for (i = 0; i < 2; ++i) {
2832                         if (dev->phy.rev >= 3) {
2833                                 enum ieee80211_band band =
2834                                         b43_current_band(dev->wl);
2835
2836                                 if ((nphy->ipa2g_on &&
2837                                      band == IEEE80211_BAND_2GHZ) ||
2838                                     (nphy->ipa5g_on &&
2839                                      band == IEEE80211_BAND_5GHZ)) {
2840                                         table = b43_nphy_get_ipa_gain_table(dev);
2841                                 } else {
2842                                         if (band == IEEE80211_BAND_5GHZ) {
2843                                                 if (dev->phy.rev == 3)
2844                                                         table = b43_ntab_tx_gain_rev3_5ghz;
2845                                                 else if (dev->phy.rev == 4)
2846                                                         table = b43_ntab_tx_gain_rev4_5ghz;
2847                                                 else
2848                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2849                                         } else {
2850                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2851                                         }
2852                                 }
2853
2854                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2855                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2856                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2857                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2858                         } else {
2859                                 table = b43_ntab_tx_gain_rev0_1_2;
2860
2861                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2862                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2863                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2864                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2865                         }
2866                 }
2867         }
2868
2869         return target;
2870 }
2871
2872 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2873 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2874 {
2875         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2876
2877         if (dev->phy.rev >= 3) {
2878                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2879                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2880                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2881                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2882                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2883                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2884                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2885                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2886                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2887                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2888                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2889                 b43_nphy_reset_cca(dev);
2890         } else {
2891                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2892                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2893                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2894                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2895                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2896                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2897                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2898         }
2899 }
2900
2901 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2902 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2903 {
2904         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2905         u16 tmp;
2906
2907         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2908         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2909         if (dev->phy.rev >= 3) {
2910                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2911                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2912
2913                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2914                 regs[2] = tmp;
2915                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2916
2917                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2918                 regs[3] = tmp;
2919                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2920
2921                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2922                 b43_phy_mask(dev, B43_NPHY_BBCFG,
2923                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2924
2925                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2926                 regs[5] = tmp;
2927                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2928
2929                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2930                 regs[6] = tmp;
2931                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2932                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2933                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2934
2935                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2936                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2937                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2938
2939                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2940                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2941                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2942                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2943         } else {
2944                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2945                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2946                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2947                 regs[2] = tmp;
2948                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2949                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2950                 regs[3] = tmp;
2951                 tmp |= 0x2000;
2952                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2953                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2954                 regs[4] = tmp;
2955                 tmp |= 0x2000;
2956                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2957                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2958                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2959                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2960                         tmp = 0x0180;
2961                 else
2962                         tmp = 0x0120;
2963                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2964                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2965         }
2966 }
2967
2968 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2969 static void b43_nphy_save_cal(struct b43_wldev *dev)
2970 {
2971         struct b43_phy_n *nphy = dev->phy.n;
2972
2973         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2974         u16 *txcal_radio_regs = NULL;
2975         struct b43_chanspec *iqcal_chanspec;
2976         u16 *table = NULL;
2977
2978         if (nphy->hang_avoid)
2979                 b43_nphy_stay_in_carrier_search(dev, 1);
2980
2981         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2982                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2983                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2984                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2985                 table = nphy->cal_cache.txcal_coeffs_2G;
2986         } else {
2987                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2988                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2989                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2990                 table = nphy->cal_cache.txcal_coeffs_5G;
2991         }
2992
2993         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2994         /* TODO use some definitions */
2995         if (dev->phy.rev >= 3) {
2996                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2997                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2998                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2999                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3000                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3001                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3002                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3003                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3004         } else {
3005                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3006                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3007                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3008                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3009         }
3010         iqcal_chanspec->center_freq = dev->phy.channel_freq;
3011         iqcal_chanspec->channel_type = dev->phy.channel_type;
3012         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3013
3014         if (nphy->hang_avoid)
3015                 b43_nphy_stay_in_carrier_search(dev, 0);
3016 }
3017
3018 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3019 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3020 {
3021         struct b43_phy_n *nphy = dev->phy.n;
3022
3023         u16 coef[4];
3024         u16 *loft = NULL;
3025         u16 *table = NULL;
3026
3027         int i;
3028         u16 *txcal_radio_regs = NULL;
3029         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3030
3031         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3032                 if (!nphy->iqcal_chanspec_2G.center_freq)
3033                         return;
3034                 table = nphy->cal_cache.txcal_coeffs_2G;
3035                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3036         } else {
3037                 if (!nphy->iqcal_chanspec_5G.center_freq)
3038                         return;
3039                 table = nphy->cal_cache.txcal_coeffs_5G;
3040                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3041         }
3042
3043         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3044
3045         for (i = 0; i < 4; i++) {
3046                 if (dev->phy.rev >= 3)
3047                         table[i] = coef[i];
3048                 else
3049                         coef[i] = 0;
3050         }
3051
3052         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3053         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3054         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3055
3056         if (dev->phy.rev < 2)
3057                 b43_nphy_tx_iq_workaround(dev);
3058
3059         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3060                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3061                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3062         } else {
3063                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3064                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3065         }
3066
3067         /* TODO use some definitions */
3068         if (dev->phy.rev >= 3) {
3069                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3070                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3071                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3072                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3073                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3074                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3075                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3076                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3077         } else {
3078                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3079                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3080                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3081                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3082         }
3083         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3084 }
3085
3086 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3087 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3088                                 struct nphy_txgains target,
3089                                 bool full, bool mphase)
3090 {
3091         struct b43_phy_n *nphy = dev->phy.n;
3092         int i;
3093         int error = 0;
3094         int freq;
3095         bool avoid = false;
3096         u8 length;
3097         u16 tmp, core, type, count, max, numb, last = 0, cmd;
3098         const u16 *table;
3099         bool phy6or5x;
3100
3101         u16 buffer[11];
3102         u16 diq_start = 0;
3103         u16 save[2];
3104         u16 gain[2];
3105         struct nphy_iqcal_params params[2];
3106         bool updated[2] = { };
3107
3108         b43_nphy_stay_in_carrier_search(dev, true);
3109
3110         if (dev->phy.rev >= 4) {
3111                 avoid = nphy->hang_avoid;
3112                 nphy->hang_avoid = 0;
3113         }
3114
3115         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3116
3117         for (i = 0; i < 2; i++) {
3118                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3119                 gain[i] = params[i].cal_gain;
3120         }
3121
3122         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3123
3124         b43_nphy_tx_cal_radio_setup(dev);
3125         b43_nphy_tx_cal_phy_setup(dev);
3126
3127         phy6or5x = dev->phy.rev >= 6 ||
3128                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3129                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3130         if (phy6or5x) {
3131                 if (dev->phy.is_40mhz) {
3132                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3133                                         tbl_tx_iqlo_cal_loft_ladder_40);
3134                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3135                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
3136                 } else {
3137                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3138                                         tbl_tx_iqlo_cal_loft_ladder_20);
3139                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3140                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
3141                 }
3142         }
3143
3144         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3145
3146         if (!dev->phy.is_40mhz)
3147                 freq = 2500;
3148         else
3149                 freq = 5000;
3150
3151         if (nphy->mphase_cal_phase_id > 2)
3152                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3153                                         0xFFFF, 0, true, false);
3154         else
3155                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3156
3157         if (error == 0) {
3158                 if (nphy->mphase_cal_phase_id > 2) {
3159                         table = nphy->mphase_txcal_bestcoeffs;
3160                         length = 11;
3161                         if (dev->phy.rev < 3)
3162                                 length -= 2;
3163                 } else {
3164                         if (!full && nphy->txiqlocal_coeffsvalid) {
3165                                 table = nphy->txiqlocal_bestc;
3166                                 length = 11;
3167                                 if (dev->phy.rev < 3)
3168                                         length -= 2;
3169                         } else {
3170                                 full = true;
3171                                 if (dev->phy.rev >= 3) {
3172                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3173                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3174                                 } else {
3175                                         table = tbl_tx_iqlo_cal_startcoefs;
3176                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3177                                 }
3178                         }
3179                 }
3180
3181                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3182
3183                 if (full) {
3184                         if (dev->phy.rev >= 3)
3185                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3186                         else
3187                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3188                 } else {
3189                         if (dev->phy.rev >= 3)
3190                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3191                         else
3192                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3193                 }
3194
3195                 if (mphase) {
3196                         count = nphy->mphase_txcal_cmdidx;
3197                         numb = min(max,
3198                                 (u16)(count + nphy->mphase_txcal_numcmds));
3199                 } else {
3200                         count = 0;
3201                         numb = max;
3202                 }
3203
3204                 for (; count < numb; count++) {
3205                         if (full) {
3206                                 if (dev->phy.rev >= 3)
3207                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3208                                 else
3209                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3210                         } else {
3211                                 if (dev->phy.rev >= 3)
3212                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3213                                 else
3214                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3215                         }
3216
3217                         core = (cmd & 0x3000) >> 12;
3218                         type = (cmd & 0x0F00) >> 8;
3219
3220                         if (phy6or5x && updated[core] == 0) {
3221                                 b43_nphy_update_tx_cal_ladder(dev, core);
3222                                 updated[core] = 1;
3223                         }
3224
3225                         tmp = (params[core].ncorr[type] << 8) | 0x66;
3226                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3227
3228                         if (type == 1 || type == 3 || type == 4) {
3229                                 buffer[0] = b43_ntab_read(dev,
3230                                                 B43_NTAB16(15, 69 + core));
3231                                 diq_start = buffer[0];
3232                                 buffer[0] = 0;
3233                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3234                                                 0);
3235                         }
3236
3237                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3238                         for (i = 0; i < 2000; i++) {
3239                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3240                                 if (tmp & 0xC000)
3241                                         break;
3242                                 udelay(10);
3243                         }
3244
3245                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3246                                                 buffer);
3247                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3248                                                 buffer);
3249
3250                         if (type == 1 || type == 3 || type == 4)
3251                                 buffer[0] = diq_start;
3252                 }
3253
3254                 if (mphase)
3255                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3256
3257                 last = (dev->phy.rev < 3) ? 6 : 7;
3258
3259                 if (!mphase || nphy->mphase_cal_phase_id == last) {
3260                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3261                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3262                         if (dev->phy.rev < 3) {
3263                                 buffer[0] = 0;
3264                                 buffer[1] = 0;
3265                                 buffer[2] = 0;
3266                                 buffer[3] = 0;
3267                         }
3268                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3269                                                 buffer);
3270                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3271                                                 buffer);
3272                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3273                                                 buffer);
3274                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3275                                                 buffer);
3276                         length = 11;
3277                         if (dev->phy.rev < 3)
3278                                 length -= 2;
3279                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3280                                                 nphy->txiqlocal_bestc);
3281                         nphy->txiqlocal_coeffsvalid = true;
3282                         nphy->txiqlocal_chanspec.center_freq =
3283                                                         dev->phy.channel_freq;
3284                         nphy->txiqlocal_chanspec.channel_type =
3285                                                         dev->phy.channel_type;
3286                 } else {
3287                         length = 11;
3288                         if (dev->phy.rev < 3)
3289                                 length -= 2;
3290                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3291                                                 nphy->mphase_txcal_bestcoeffs);
3292                 }
3293
3294                 b43_nphy_stop_playback(dev);
3295                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3296         }
3297
3298         b43_nphy_tx_cal_phy_cleanup(dev);
3299         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3300
3301         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3302                 b43_nphy_tx_iq_workaround(dev);
3303
3304         if (dev->phy.rev >= 4)
3305                 nphy->hang_avoid = avoid;
3306
3307         b43_nphy_stay_in_carrier_search(dev, false);
3308
3309         return error;
3310 }
3311
3312 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3313 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3314 {
3315         struct b43_phy_n *nphy = dev->phy.n;
3316         u8 i;
3317         u16 buffer[7];
3318         bool equal = true;
3319
3320         if (!nphy->txiqlocal_coeffsvalid ||
3321             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3322             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3323                 return;
3324
3325         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3326         for (i = 0; i < 4; i++) {
3327                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3328                         equal = false;
3329                         break;
3330                 }
3331         }
3332
3333         if (!equal) {
3334                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3335                                         nphy->txiqlocal_bestc);
3336                 for (i = 0; i < 4; i++)
3337                         buffer[i] = 0;
3338                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3339                                         buffer);
3340                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3341                                         &nphy->txiqlocal_bestc[5]);
3342                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3343                                         &nphy->txiqlocal_bestc[5]);
3344         }
3345 }
3346
3347 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3348 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3349                         struct nphy_txgains target, u8 type, bool debug)
3350 {
3351         struct b43_phy_n *nphy = dev->phy.n;
3352         int i, j, index;
3353         u8 rfctl[2];
3354         u8 afectl_core;
3355         u16 tmp[6];
3356         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3357         u32 real, imag;
3358         enum ieee80211_band band;
3359
3360         u8 use;
3361         u16 cur_hpf;
3362         u16 lna[3] = { 3, 3, 1 };
3363         u16 hpf1[3] = { 7, 2, 0 };
3364         u16 hpf2[3] = { 2, 0, 0 };
3365         u32 power[3] = { };
3366         u16 gain_save[2];
3367         u16 cal_gain[2];
3368         struct nphy_iqcal_params cal_params[2];
3369         struct nphy_iq_est est;
3370         int ret = 0;
3371         bool playtone = true;
3372         int desired = 13;
3373
3374         b43_nphy_stay_in_carrier_search(dev, 1);
3375
3376         if (dev->phy.rev < 2)
3377                 b43_nphy_reapply_tx_cal_coeffs(dev);
3378         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3379         for (i = 0; i < 2; i++) {
3380                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3381                 cal_gain[i] = cal_params[i].cal_gain;
3382         }
3383         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3384
3385         for (i = 0; i < 2; i++) {
3386                 if (i == 0) {
3387                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
3388                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
3389                         afectl_core = B43_NPHY_AFECTL_C1;
3390                 } else {
3391                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
3392                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
3393                         afectl_core = B43_NPHY_AFECTL_C2;
3394                 }
3395
3396                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3397                 tmp[2] = b43_phy_read(dev, afectl_core);
3398                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3399                 tmp[4] = b43_phy_read(dev, rfctl[0]);
3400                 tmp[5] = b43_phy_read(dev, rfctl[1]);
3401
3402                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3403                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3404                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3405                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3406                                 (1 - i));
3407                 b43_phy_set(dev, afectl_core, 0x0006);
3408                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3409
3410                 band = b43_current_band(dev->wl);
3411
3412                 if (nphy->rxcalparams & 0xFF000000) {
3413                         if (band == IEEE80211_BAND_5GHZ)
3414                                 b43_phy_write(dev, rfctl[0], 0x140);
3415                         else
3416                                 b43_phy_write(dev, rfctl[0], 0x110);
3417                 } else {
3418                         if (band == IEEE80211_BAND_5GHZ)
3419                                 b43_phy_write(dev, rfctl[0], 0x180);
3420                         else
3421                                 b43_phy_write(dev, rfctl[0], 0x120);
3422                 }
3423
3424                 if (band == IEEE80211_BAND_5GHZ)
3425                         b43_phy_write(dev, rfctl[1], 0x148);
3426                 else
3427                         b43_phy_write(dev, rfctl[1], 0x114);
3428
3429                 if (nphy->rxcalparams & 0x10000) {
3430                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3431                                         (i + 1));
3432                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3433                                         (2 - i));
3434                 }
3435
3436                 for (j = 0; j < 4; j++) {
3437                         if (j < 3) {
3438                                 cur_lna = lna[j];
3439                                 cur_hpf1 = hpf1[j];
3440                                 cur_hpf2 = hpf2[j];
3441                         } else {
3442                                 if (power[1] > 10000) {
3443                                         use = 1;
3444                                         cur_hpf = cur_hpf1;
3445                                         index = 2;
3446                                 } else {
3447                                         if (power[0] > 10000) {
3448                                                 use = 1;
3449                                                 cur_hpf = cur_hpf1;
3450                                                 index = 1;
3451                                         } else {
3452                                                 index = 0;
3453                                                 use = 2;
3454                                                 cur_hpf = cur_hpf2;
3455                                         }
3456                                 }
3457                                 cur_lna = lna[index];
3458                                 cur_hpf1 = hpf1[index];
3459                                 cur_hpf2 = hpf2[index];
3460                                 cur_hpf += desired - hweight32(power[index]);
3461                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
3462                                 if (use == 1)
3463                                         cur_hpf1 = cur_hpf;
3464                                 else
3465                                         cur_hpf2 = cur_hpf;
3466                         }
3467
3468                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3469                                         (cur_lna << 2));
3470                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3471                                                                         false);
3472                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3473                         b43_nphy_stop_playback(dev);
3474
3475                         if (playtone) {
3476                                 ret = b43_nphy_tx_tone(dev, 4000,
3477                                                 (nphy->rxcalparams & 0xFFFF),
3478                                                 false, false);
3479                                 playtone = false;
3480                         } else {
3481                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3482                                                         false, false);
3483                         }
3484
3485                         if (ret == 0) {
3486                                 if (j < 3) {
3487                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3488                                                                         false);
3489                                         if (i == 0) {
3490                                                 real = est.i0_pwr;
3491                                                 imag = est.q0_pwr;
3492                                         } else {
3493                                                 real = est.i1_pwr;
3494                                                 imag = est.q1_pwr;
3495                                         }
3496                                         power[i] = ((real + imag) / 1024) + 1;
3497                                 } else {
3498                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3499                                 }
3500                                 b43_nphy_stop_playback(dev);
3501                         }
3502
3503                         if (ret != 0)
3504                                 break;
3505                 }
3506
3507                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3508                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3509                 b43_phy_write(dev, rfctl[1], tmp[5]);
3510                 b43_phy_write(dev, rfctl[0], tmp[4]);
3511                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3512                 b43_phy_write(dev, afectl_core, tmp[2]);
3513                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3514
3515                 if (ret != 0)
3516                         break;
3517         }
3518
3519         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3520         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3521         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3522
3523         b43_nphy_stay_in_carrier_search(dev, 0);
3524
3525         return ret;
3526 }
3527
3528 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3529                         struct nphy_txgains target, u8 type, bool debug)
3530 {
3531         return -1;
3532 }
3533
3534 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3535 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3536                         struct nphy_txgains target, u8 type, bool debug)
3537 {
3538         if (dev->phy.rev >= 3)
3539                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3540         else
3541                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3542 }
3543
3544 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3545 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3546 {
3547         struct b43_phy *phy = &dev->phy;
3548         struct b43_phy_n *nphy = phy->n;
3549         /* u16 buf[16]; it's rev3+ */
3550
3551         nphy->phyrxchain = mask;
3552
3553         if (0 /* FIXME clk */)
3554                 return;
3555
3556         b43_mac_suspend(dev);
3557
3558         if (nphy->hang_avoid)
3559                 b43_nphy_stay_in_carrier_search(dev, true);
3560
3561         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3562                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3563
3564         if ((mask & 0x3) != 0x3) {
3565                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3566                 if (dev->phy.rev >= 3) {
3567                         /* TODO */
3568                 }
3569         } else {
3570                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3571                 if (dev->phy.rev >= 3) {
3572                         /* TODO */
3573                 }
3574         }
3575
3576         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3577
3578         if (nphy->hang_avoid)
3579                 b43_nphy_stay_in_carrier_search(dev, false);
3580
3581         b43_mac_enable(dev);
3582 }
3583
3584 /*
3585  * Init N-PHY
3586  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3587  */
3588 int b43_phy_initn(struct b43_wldev *dev)
3589 {
3590         struct ssb_bus *bus = dev->sdev->bus;
3591         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3592         struct b43_phy *phy = &dev->phy;
3593         struct b43_phy_n *nphy = phy->n;
3594         u8 tx_pwr_state;
3595         struct nphy_txgains target;
3596         u16 tmp;
3597         enum ieee80211_band tmp2;
3598         bool do_rssi_cal;
3599
3600         u16 clip[2];
3601         bool do_cal = false;
3602
3603         if ((dev->phy.rev >= 3) &&
3604            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3605            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3606                 chipco_set32(&dev->sdev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3607         }
3608         nphy->deaf_count = 0;
3609         b43_nphy_tables_init(dev);
3610         nphy->crsminpwr_adjusted = false;
3611         nphy->noisevars_adjusted = false;
3612
3613         /* Clear all overrides */
3614         if (dev->phy.rev >= 3) {
3615                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3616                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3617                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3618                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3619         } else {
3620                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3621         }
3622         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3623         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3624         if (dev->phy.rev < 6) {
3625                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3626                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3627         }
3628         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3629                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3630                        B43_NPHY_RFSEQMODE_TROVER));
3631         if (dev->phy.rev >= 3)
3632                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3633         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3634
3635         if (dev->phy.rev <= 2) {
3636                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3637                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3638                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3639                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3640         }
3641         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3642         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3643
3644         if (sprom->boardflags2_lo & 0x100 ||
3645             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3646              bus->boardinfo.type == 0x8B))
3647                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3648         else
3649                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3650         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3651         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3652         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3653
3654         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3655         b43_nphy_update_txrx_chain(dev);
3656
3657         if (phy->rev < 2) {
3658                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3659                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3660         }
3661
3662         tmp2 = b43_current_band(dev->wl);
3663         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3664             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3665                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3666                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3667                                 nphy->papd_epsilon_offset[0] << 7);
3668                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3669                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3670                                 nphy->papd_epsilon_offset[1] << 7);
3671                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3672         } else if (phy->rev >= 5) {
3673                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3674         }
3675
3676         b43_nphy_workarounds(dev);
3677
3678         /* Reset CCA, in init code it differs a little from standard way */
3679         b43_nphy_bmac_clock_fgc(dev, 1);
3680         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3681         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3682         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3683         b43_nphy_bmac_clock_fgc(dev, 0);
3684
3685         b43_mac_phy_clock_set(dev, true);
3686
3687         b43_nphy_pa_override(dev, false);
3688         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3689         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3690         b43_nphy_pa_override(dev, true);
3691
3692         b43_nphy_classifier(dev, 0, 0);
3693         b43_nphy_read_clip_detection(dev, clip);
3694         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3695                 b43_nphy_bphy_init(dev);
3696
3697         tx_pwr_state = nphy->txpwrctrl;
3698         b43_nphy_tx_power_ctrl(dev, false);
3699         b43_nphy_tx_power_fix(dev);
3700         /* TODO N PHY TX Power Control Idle TSSI */
3701         /* TODO N PHY TX Power Control Setup */
3702
3703         if (phy->rev >= 3) {
3704                 /* TODO */
3705         } else {
3706                 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3707                                         b43_ntab_tx_gain_rev0_1_2);
3708                 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3709                                         b43_ntab_tx_gain_rev0_1_2);
3710         }
3711
3712         if (nphy->phyrxchain != 3)
3713                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3714         if (nphy->mphase_cal_phase_id > 0)
3715                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3716
3717         do_rssi_cal = false;
3718         if (phy->rev >= 3) {
3719                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3720                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3721                 else
3722                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3723
3724                 if (do_rssi_cal)
3725                         b43_nphy_rssi_cal(dev);
3726                 else
3727                         b43_nphy_restore_rssi_cal(dev);
3728         } else {
3729                 b43_nphy_rssi_cal(dev);
3730         }
3731
3732         if (!((nphy->measure_hold & 0x6) != 0)) {
3733                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3734                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3735                 else
3736                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3737
3738                 if (nphy->mute)
3739                         do_cal = false;
3740
3741                 if (do_cal) {
3742                         target = b43_nphy_get_tx_gains(dev);
3743
3744                         if (nphy->antsel_type == 2)
3745                                 b43_nphy_superswitch_init(dev, true);
3746                         if (nphy->perical != 2) {
3747                                 b43_nphy_rssi_cal(dev);
3748                                 if (phy->rev >= 3) {
3749                                         nphy->cal_orig_pwr_idx[0] =
3750                                             nphy->txpwrindex[0].index_internal;
3751                                         nphy->cal_orig_pwr_idx[1] =
3752                                             nphy->txpwrindex[1].index_internal;
3753                                         /* TODO N PHY Pre Calibrate TX Gain */
3754                                         target = b43_nphy_get_tx_gains(dev);
3755                                 }
3756                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
3757                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3758                                                 b43_nphy_save_cal(dev);
3759                         } else if (nphy->mphase_cal_phase_id == 0)
3760                                 ;/* N PHY Periodic Calibration with arg 3 */
3761                 } else {
3762                         b43_nphy_restore_cal(dev);
3763                 }
3764         }
3765
3766         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3767         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
3768         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3769         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3770         if (phy->rev >= 3 && phy->rev <= 6)
3771                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3772         b43_nphy_tx_lp_fbw(dev);
3773         if (phy->rev >= 3)
3774                 b43_nphy_spur_workaround(dev);
3775
3776         return 0;
3777 }
3778
3779 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3780 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3781                                 const struct b43_phy_n_sfo_cfg *e,
3782                                 struct ieee80211_channel *new_channel)
3783 {
3784         struct b43_phy *phy = &dev->phy;
3785         struct b43_phy_n *nphy = dev->phy.n;
3786
3787         u16 old_band_5ghz;
3788         u32 tmp32;
3789
3790         old_band_5ghz =
3791                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3792         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3793                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3794                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3795                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3796                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3797                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3798         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3799                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3800                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3801                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3802                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3803                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3804         }
3805
3806         b43_chantab_phy_upload(dev, e);
3807
3808         if (new_channel->hw_value == 14) {
3809                 b43_nphy_classifier(dev, 2, 0);
3810                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3811         } else {
3812                 b43_nphy_classifier(dev, 2, 2);
3813                 if (new_channel->band == IEEE80211_BAND_2GHZ)
3814                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3815         }
3816
3817         if (!nphy->txpwrctrl)
3818                 b43_nphy_tx_power_fix(dev);
3819
3820         if (dev->phy.rev < 3)
3821                 b43_nphy_adjust_lna_gain_table(dev);
3822
3823         b43_nphy_tx_lp_fbw(dev);
3824
3825         if (dev->phy.rev >= 3 && 0) {
3826                 /* TODO */
3827         }
3828
3829         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3830
3831         if (phy->rev >= 3)
3832                 b43_nphy_spur_workaround(dev);
3833 }
3834
3835 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3836 static int b43_nphy_set_channel(struct b43_wldev *dev,
3837                                 struct ieee80211_channel *channel,
3838                                 enum nl80211_channel_type channel_type)
3839 {
3840         struct b43_phy *phy = &dev->phy;
3841
3842         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
3843         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
3844
3845         u8 tmp;
3846
3847         if (dev->phy.rev >= 3) {
3848                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3849                                                         channel->center_freq);
3850                 if (!tabent_r3)
3851                         return -ESRCH;
3852         } else {
3853                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3854                                                         channel->hw_value);
3855                 if (!tabent_r2)
3856                         return -ESRCH;
3857         }
3858
3859         /* Channel is set later in common code, but we need to set it on our
3860            own to let this function's subcalls work properly. */
3861         phy->channel = channel->hw_value;
3862         phy->channel_freq = channel->center_freq;
3863
3864         if (b43_channel_type_is_40mhz(phy->channel_type) !=
3865                 b43_channel_type_is_40mhz(channel_type))
3866                 ; /* TODO: BMAC BW Set (channel_type) */
3867
3868         if (channel_type == NL80211_CHAN_HT40PLUS)
3869                 b43_phy_set(dev, B43_NPHY_RXCTL,
3870                                 B43_NPHY_RXCTL_BSELU20);
3871         else if (channel_type == NL80211_CHAN_HT40MINUS)
3872                 b43_phy_mask(dev, B43_NPHY_RXCTL,
3873                                 ~B43_NPHY_RXCTL_BSELU20);
3874
3875         if (dev->phy.rev >= 3) {
3876                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3877                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3878                 b43_radio_2056_setup(dev, tabent_r3);
3879                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3880         } else {
3881                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3882                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3883                 b43_radio_2055_setup(dev, tabent_r2);
3884                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3885         }
3886
3887         return 0;
3888 }
3889
3890 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3891 {
3892         struct b43_phy_n *nphy;
3893
3894         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3895         if (!nphy)
3896                 return -ENOMEM;
3897         dev->phy.n = nphy;
3898
3899         return 0;
3900 }
3901
3902 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3903 {
3904         struct b43_phy *phy = &dev->phy;
3905         struct b43_phy_n *nphy = phy->n;
3906
3907         memset(nphy, 0, sizeof(*nphy));
3908
3909         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
3910         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3911         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3912         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
3913         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
3914 }
3915
3916 static void b43_nphy_op_free(struct b43_wldev *dev)
3917 {
3918         struct b43_phy *phy = &dev->phy;
3919         struct b43_phy_n *nphy = phy->n;
3920
3921         kfree(nphy);
3922         phy->n = NULL;
3923 }
3924
3925 static int b43_nphy_op_init(struct b43_wldev *dev)
3926 {
3927         return b43_phy_initn(dev);
3928 }
3929
3930 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3931 {
3932 #if B43_DEBUG
3933         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3934                 /* OFDM registers are onnly available on A/G-PHYs */
3935                 b43err(dev->wl, "Invalid OFDM PHY access at "
3936                        "0x%04X on N-PHY\n", offset);
3937                 dump_stack();
3938         }
3939         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3940                 /* Ext-G registers are only available on G-PHYs */
3941                 b43err(dev->wl, "Invalid EXT-G PHY access at "
3942                        "0x%04X on N-PHY\n", offset);
3943                 dump_stack();
3944         }
3945 #endif /* B43_DEBUG */
3946 }
3947
3948 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3949 {
3950         check_phyreg(dev, reg);
3951         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3952         return b43_read16(dev, B43_MMIO_PHY_DATA);
3953 }
3954
3955 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3956 {
3957         check_phyreg(dev, reg);
3958         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3959         b43_write16(dev, B43_MMIO_PHY_DATA, value);
3960 }
3961
3962 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
3963                                  u16 set)
3964 {
3965         check_phyreg(dev, reg);
3966         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3967         b43_write16(dev, B43_MMIO_PHY_DATA,
3968                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
3969 }
3970
3971 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3972 {
3973         /* Register 1 is a 32-bit register. */
3974         B43_WARN_ON(reg == 1);
3975         /* N-PHY needs 0x100 for read access */
3976         reg |= 0x100;
3977
3978         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3979         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3980 }
3981
3982 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3983 {
3984         /* Register 1 is a 32-bit register. */
3985         B43_WARN_ON(reg == 1);
3986
3987         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3988         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3989 }
3990
3991 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3992 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3993                                         bool blocked)
3994 {
3995         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3996                 b43err(dev->wl, "MAC not suspended\n");
3997
3998         if (blocked) {
3999                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4000                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4001                 if (dev->phy.rev >= 3) {
4002                         b43_radio_mask(dev, 0x09, ~0x2);
4003
4004                         b43_radio_write(dev, 0x204D, 0);
4005                         b43_radio_write(dev, 0x2053, 0);
4006                         b43_radio_write(dev, 0x2058, 0);
4007                         b43_radio_write(dev, 0x205E, 0);
4008                         b43_radio_mask(dev, 0x2062, ~0xF0);
4009                         b43_radio_write(dev, 0x2064, 0);
4010
4011                         b43_radio_write(dev, 0x304D, 0);
4012                         b43_radio_write(dev, 0x3053, 0);
4013                         b43_radio_write(dev, 0x3058, 0);
4014                         b43_radio_write(dev, 0x305E, 0);
4015                         b43_radio_mask(dev, 0x3062, ~0xF0);
4016                         b43_radio_write(dev, 0x3064, 0);
4017                 }
4018         } else {
4019                 if (dev->phy.rev >= 3) {
4020                         b43_radio_init2056(dev);
4021                         b43_switch_channel(dev, dev->phy.channel);
4022                 } else {
4023                         b43_radio_init2055(dev);
4024                 }
4025         }
4026 }
4027
4028 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4029 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4030 {
4031         u16 val = on ? 0 : 0x7FFF;
4032
4033         if (dev->phy.rev >= 3)
4034                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, val);
4035         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, val);
4036 }
4037
4038 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4039                                       unsigned int new_channel)
4040 {
4041         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4042         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4043
4044         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4045                 if ((new_channel < 1) || (new_channel > 14))
4046                         return -EINVAL;
4047         } else {
4048                 if (new_channel > 200)
4049                         return -EINVAL;
4050         }
4051
4052         return b43_nphy_set_channel(dev, channel, channel_type);
4053 }
4054
4055 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4056 {
4057         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4058                 return 1;
4059         return 36;
4060 }
4061
4062 const struct b43_phy_operations b43_phyops_n = {
4063         .allocate               = b43_nphy_op_allocate,
4064         .free                   = b43_nphy_op_free,
4065         .prepare_structs        = b43_nphy_op_prepare_structs,
4066         .init                   = b43_nphy_op_init,
4067         .phy_read               = b43_nphy_op_read,
4068         .phy_write              = b43_nphy_op_write,
4069         .phy_maskset            = b43_nphy_op_maskset,
4070         .radio_read             = b43_nphy_op_radio_read,
4071         .radio_write            = b43_nphy_op_radio_write,
4072         .software_rfkill        = b43_nphy_op_software_rfkill,
4073         .switch_analog          = b43_nphy_op_switch_analog,
4074         .switch_channel         = b43_nphy_op_switch_channel,
4075         .get_default_chan       = b43_nphy_op_get_default_chan,
4076         .recalc_txpower         = b43_nphy_op_recalc_txpower,
4077         .adjust_txpower         = b43_nphy_op_adjust_txpower,
4078 };