Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6.git] / drivers / net / wireless / b43 / phy_n.c
1 /*
2
3   Broadcom B43 wireless driver
4   IEEE 802.11n PHY support
5
6   Copyright (c) 2008 Michael Buesch <m@bues.ch>
7   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
8
9   This program is free software; you can redistribute it and/or modify
10   it under the terms of the GNU General Public License as published by
11   the Free Software Foundation; either version 2 of the License, or
12   (at your option) any later version.
13
14   This program is distributed in the hope that it will be useful,
15   but WITHOUT ANY WARRANTY; without even the implied warranty of
16   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17   GNU General Public License for more details.
18
19   You should have received a copy of the GNU General Public License
20   along with this program; see the file COPYING.  If not, write to
21   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22   Boston, MA 02110-1301, USA.
23
24 */
25
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
29
30 #include "b43.h"
31 #include "phy_n.h"
32 #include "tables_nphy.h"
33 #include "radio_2055.h"
34 #include "radio_2056.h"
35 #include "main.h"
36
37 struct nphy_txgains {
38         u16 txgm[2];
39         u16 pga[2];
40         u16 pad[2];
41         u16 ipa[2];
42 };
43
44 struct nphy_iqcal_params {
45         u16 txgm;
46         u16 pga;
47         u16 pad;
48         u16 ipa;
49         u16 cal_gain;
50         u16 ncorr[5];
51 };
52
53 struct nphy_iq_est {
54         s32 iq0_prod;
55         u32 i0_pwr;
56         u32 q0_pwr;
57         s32 iq1_prod;
58         u32 i1_pwr;
59         u32 q1_pwr;
60 };
61
62 enum b43_nphy_rf_sequence {
63         B43_RFSEQ_RX2TX,
64         B43_RFSEQ_TX2RX,
65         B43_RFSEQ_RESET2RX,
66         B43_RFSEQ_UPDATE_GAINH,
67         B43_RFSEQ_UPDATE_GAINL,
68         B43_RFSEQ_UPDATE_GAINU,
69 };
70
71 enum b43_nphy_rssi_type {
72         B43_NPHY_RSSI_X = 0,
73         B43_NPHY_RSSI_Y,
74         B43_NPHY_RSSI_Z,
75         B43_NPHY_RSSI_PWRDET,
76         B43_NPHY_RSSI_TSSI_I,
77         B43_NPHY_RSSI_TSSI_Q,
78         B43_NPHY_RSSI_TBD,
79 };
80
81 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
82 {
83         enum ieee80211_band band = b43_current_band(dev->wl);
84         return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
85                 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
86 }
87
88 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
89 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
90 {
91         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
92                 if (dev->phy.rev >= 6) {
93                         if (dev->dev->chip_id == 47162)
94                                 return txpwrctrl_tx_gain_ipa_rev5;
95                         return txpwrctrl_tx_gain_ipa_rev6;
96                 } else if (dev->phy.rev >= 5) {
97                         return txpwrctrl_tx_gain_ipa_rev5;
98                 } else {
99                         return txpwrctrl_tx_gain_ipa;
100                 }
101         } else {
102                 return txpwrctrl_tx_gain_ipa_5g;
103         }
104 }
105
106 /**************************************************
107  * RF (just without b43_nphy_rf_control_intc_override)
108  **************************************************/
109
110 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
111 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
112                                        enum b43_nphy_rf_sequence seq)
113 {
114         static const u16 trigger[] = {
115                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
116                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
117                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
118                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
119                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
120                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
121         };
122         int i;
123         u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
124
125         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
126
127         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
128                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
129         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
130         for (i = 0; i < 200; i++) {
131                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
132                         goto ok;
133                 msleep(1);
134         }
135         b43err(dev->wl, "RF sequence status timeout\n");
136 ok:
137         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
138 }
139
140 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
141 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
142                                                 u16 value, u8 core, bool off)
143 {
144         int i;
145         u8 index = fls(field);
146         u8 addr, en_addr, val_addr;
147         /* we expect only one bit set */
148         B43_WARN_ON(field & (~(1 << (index - 1))));
149
150         if (dev->phy.rev >= 3) {
151                 const struct nphy_rf_control_override_rev3 *rf_ctrl;
152                 for (i = 0; i < 2; i++) {
153                         if (index == 0 || index == 16) {
154                                 b43err(dev->wl,
155                                         "Unsupported RF Ctrl Override call\n");
156                                 return;
157                         }
158
159                         rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
160                         en_addr = B43_PHY_N((i == 0) ?
161                                 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
162                         val_addr = B43_PHY_N((i == 0) ?
163                                 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
164
165                         if (off) {
166                                 b43_phy_mask(dev, en_addr, ~(field));
167                                 b43_phy_mask(dev, val_addr,
168                                                 ~(rf_ctrl->val_mask));
169                         } else {
170                                 if (core == 0 || ((1 << core) & i) != 0) {
171                                         b43_phy_set(dev, en_addr, field);
172                                         b43_phy_maskset(dev, val_addr,
173                                                 ~(rf_ctrl->val_mask),
174                                                 (value << rf_ctrl->val_shift));
175                                 }
176                         }
177                 }
178         } else {
179                 const struct nphy_rf_control_override_rev2 *rf_ctrl;
180                 if (off) {
181                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
182                         value = 0;
183                 } else {
184                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
185                 }
186
187                 for (i = 0; i < 2; i++) {
188                         if (index <= 1 || index == 16) {
189                                 b43err(dev->wl,
190                                         "Unsupported RF Ctrl Override call\n");
191                                 return;
192                         }
193
194                         if (index == 2 || index == 10 ||
195                             (index >= 13 && index <= 15)) {
196                                 core = 1;
197                         }
198
199                         rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
200                         addr = B43_PHY_N((i == 0) ?
201                                 rf_ctrl->addr0 : rf_ctrl->addr1);
202
203                         if ((core & (1 << i)) != 0)
204                                 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
205                                                 (value << rf_ctrl->shift));
206
207                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
208                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
209                                         B43_NPHY_RFCTL_CMD_START);
210                         udelay(1);
211                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
212                 }
213         }
214 }
215
216 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
217 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
218                                                 u16 value, u8 core)
219 {
220         u8 i, j;
221         u16 reg, tmp, val;
222
223         B43_WARN_ON(dev->phy.rev < 3);
224         B43_WARN_ON(field > 4);
225
226         for (i = 0; i < 2; i++) {
227                 if ((core == 1 && i == 1) || (core == 2 && !i))
228                         continue;
229
230                 reg = (i == 0) ?
231                         B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
232                 b43_phy_mask(dev, reg, 0xFBFF);
233
234                 switch (field) {
235                 case 0:
236                         b43_phy_write(dev, reg, 0);
237                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
238                         break;
239                 case 1:
240                         if (!i) {
241                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
242                                                 0xFC3F, (value << 6));
243                                 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
244                                                 0xFFFE, 1);
245                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
246                                                 B43_NPHY_RFCTL_CMD_START);
247                                 for (j = 0; j < 100; j++) {
248                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
249                                                 j = 0;
250                                                 break;
251                                         }
252                                         udelay(10);
253                                 }
254                                 if (j)
255                                         b43err(dev->wl,
256                                                 "intc override timeout\n");
257                                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
258                                                 0xFFFE);
259                         } else {
260                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
261                                                 0xFC3F, (value << 6));
262                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
263                                                 0xFFFE, 1);
264                                 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
265                                                 B43_NPHY_RFCTL_CMD_RXTX);
266                                 for (j = 0; j < 100; j++) {
267                                         if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
268                                                 j = 0;
269                                                 break;
270                                         }
271                                         udelay(10);
272                                 }
273                                 if (j)
274                                         b43err(dev->wl,
275                                                 "intc override timeout\n");
276                                 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
277                                                 0xFFFE);
278                         }
279                         break;
280                 case 2:
281                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
282                                 tmp = 0x0020;
283                                 val = value << 5;
284                         } else {
285                                 tmp = 0x0010;
286                                 val = value << 4;
287                         }
288                         b43_phy_maskset(dev, reg, ~tmp, val);
289                         break;
290                 case 3:
291                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
292                                 tmp = 0x0001;
293                                 val = value;
294                         } else {
295                                 tmp = 0x0004;
296                                 val = value << 2;
297                         }
298                         b43_phy_maskset(dev, reg, ~tmp, val);
299                         break;
300                 case 4:
301                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
302                                 tmp = 0x0002;
303                                 val = value << 1;
304                         } else {
305                                 tmp = 0x0008;
306                                 val = value << 3;
307                         }
308                         b43_phy_maskset(dev, reg, ~tmp, val);
309                         break;
310                 }
311         }
312 }
313
314 /**************************************************
315  * Various PHY ops
316  **************************************************/
317
318 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
319 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
320                                           const u16 *clip_st)
321 {
322         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
323         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
324 }
325
326 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
327 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
328 {
329         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
330         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
331 }
332
333 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
334 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
335 {
336         u16 tmp;
337
338         if (dev->dev->core_rev == 16)
339                 b43_mac_suspend(dev);
340
341         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
342         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
343                 B43_NPHY_CLASSCTL_WAITEDEN);
344         tmp &= ~mask;
345         tmp |= (val & mask);
346         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
347
348         if (dev->dev->core_rev == 16)
349                 b43_mac_enable(dev);
350
351         return tmp;
352 }
353
354 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
355 static void b43_nphy_reset_cca(struct b43_wldev *dev)
356 {
357         u16 bbcfg;
358
359         b43_phy_force_clock(dev, 1);
360         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
361         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
362         udelay(1);
363         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
364         b43_phy_force_clock(dev, 0);
365         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
366 }
367
368 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
369 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
370 {
371         struct b43_phy *phy = &dev->phy;
372         struct b43_phy_n *nphy = phy->n;
373
374         if (enable) {
375                 static const u16 clip[] = { 0xFFFF, 0xFFFF };
376                 if (nphy->deaf_count++ == 0) {
377                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
378                         b43_nphy_classifier(dev, 0x7, 0);
379                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
380                         b43_nphy_write_clip_detection(dev, clip);
381                 }
382                 b43_nphy_reset_cca(dev);
383         } else {
384                 if (--nphy->deaf_count == 0) {
385                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
386                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
387                 }
388         }
389 }
390
391 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
392 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
393 {
394         struct b43_phy_n *nphy = dev->phy.n;
395
396         u8 i;
397         s16 tmp;
398         u16 data[4];
399         s16 gain[2];
400         u16 minmax[2];
401         static const u16 lna_gain[4] = { -2, 10, 19, 25 };
402
403         if (nphy->hang_avoid)
404                 b43_nphy_stay_in_carrier_search(dev, 1);
405
406         if (nphy->gain_boost) {
407                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
408                         gain[0] = 6;
409                         gain[1] = 6;
410                 } else {
411                         tmp = 40370 - 315 * dev->phy.channel;
412                         gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
413                         tmp = 23242 - 224 * dev->phy.channel;
414                         gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
415                 }
416         } else {
417                 gain[0] = 0;
418                 gain[1] = 0;
419         }
420
421         for (i = 0; i < 2; i++) {
422                 if (nphy->elna_gain_config) {
423                         data[0] = 19 + gain[i];
424                         data[1] = 25 + gain[i];
425                         data[2] = 25 + gain[i];
426                         data[3] = 25 + gain[i];
427                 } else {
428                         data[0] = lna_gain[0] + gain[i];
429                         data[1] = lna_gain[1] + gain[i];
430                         data[2] = lna_gain[2] + gain[i];
431                         data[3] = lna_gain[3] + gain[i];
432                 }
433                 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
434
435                 minmax[i] = 23 + gain[i];
436         }
437
438         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
439                                 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
440         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
441                                 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
442
443         if (nphy->hang_avoid)
444                 b43_nphy_stay_in_carrier_search(dev, 0);
445 }
446
447 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
448 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
449                                         u8 *events, u8 *delays, u8 length)
450 {
451         struct b43_phy_n *nphy = dev->phy.n;
452         u8 i;
453         u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
454         u16 offset1 = cmd << 4;
455         u16 offset2 = offset1 + 0x80;
456
457         if (nphy->hang_avoid)
458                 b43_nphy_stay_in_carrier_search(dev, true);
459
460         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
461         b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
462
463         for (i = length; i < 16; i++) {
464                 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
465                 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
466         }
467
468         if (nphy->hang_avoid)
469                 b43_nphy_stay_in_carrier_search(dev, false);
470 }
471
472 /**************************************************
473  * Radio 0x2056
474  **************************************************/
475
476 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
477                                 const struct b43_nphy_channeltab_entry_rev3 *e)
478 {
479         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
480         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
481         b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
482         b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
483         b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
484         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
485                                         e->radio_syn_pll_loopfilter1);
486         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
487                                         e->radio_syn_pll_loopfilter2);
488         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
489                                         e->radio_syn_pll_loopfilter3);
490         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
491                                         e->radio_syn_pll_loopfilter4);
492         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
493                                         e->radio_syn_pll_loopfilter5);
494         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
495                                         e->radio_syn_reserved_addr27);
496         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
497                                         e->radio_syn_reserved_addr28);
498         b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
499                                         e->radio_syn_reserved_addr29);
500         b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
501                                         e->radio_syn_logen_vcobuf1);
502         b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
503         b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
504         b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
505
506         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
507                                         e->radio_rx0_lnaa_tune);
508         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
509                                         e->radio_rx0_lnag_tune);
510
511         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
512                                         e->radio_tx0_intpaa_boost_tune);
513         b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
514                                         e->radio_tx0_intpag_boost_tune);
515         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
516                                         e->radio_tx0_pada_boost_tune);
517         b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
518                                         e->radio_tx0_padg_boost_tune);
519         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
520                                         e->radio_tx0_pgaa_boost_tune);
521         b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
522                                         e->radio_tx0_pgag_boost_tune);
523         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
524                                         e->radio_tx0_mixa_boost_tune);
525         b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
526                                         e->radio_tx0_mixg_boost_tune);
527
528         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
529                                         e->radio_rx1_lnaa_tune);
530         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
531                                         e->radio_rx1_lnag_tune);
532
533         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
534                                         e->radio_tx1_intpaa_boost_tune);
535         b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
536                                         e->radio_tx1_intpag_boost_tune);
537         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
538                                         e->radio_tx1_pada_boost_tune);
539         b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
540                                         e->radio_tx1_padg_boost_tune);
541         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
542                                         e->radio_tx1_pgaa_boost_tune);
543         b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
544                                         e->radio_tx1_pgag_boost_tune);
545         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
546                                         e->radio_tx1_mixa_boost_tune);
547         b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
548                                         e->radio_tx1_mixg_boost_tune);
549 }
550
551 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
552 static void b43_radio_2056_setup(struct b43_wldev *dev,
553                                 const struct b43_nphy_channeltab_entry_rev3 *e)
554 {
555         struct ssb_sprom *sprom = dev->dev->bus_sprom;
556         enum ieee80211_band band = b43_current_band(dev->wl);
557         u16 offset;
558         u8 i;
559         u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost;
560
561         B43_WARN_ON(dev->phy.rev < 3);
562
563         b43_chantab_radio_2056_upload(dev, e);
564         b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
565
566         if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
567             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
568                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
569                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
570                 if (dev->dev->chip_id == 0x4716) {
571                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
572                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
573                 } else {
574                         b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
575                         b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
576                 }
577         }
578         if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
579             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
580                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
581                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
582                 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
583                 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
584         }
585
586         if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
587                 for (i = 0; i < 2; i++) {
588                         offset = i ? B2056_TX1 : B2056_TX0;
589                         if (dev->phy.rev >= 5) {
590                                 b43_radio_write(dev,
591                                         offset | B2056_TX_PADG_IDAC, 0xcc);
592
593                                 if (dev->dev->chip_id == 0x4716) {
594                                         bias = 0x40;
595                                         cbias = 0x45;
596                                         pag_boost = 0x5;
597                                         pgag_boost = 0x33;
598                                         mixg_boost = 0x55;
599                                 } else {
600                                         bias = 0x25;
601                                         cbias = 0x20;
602                                         pag_boost = 0x4;
603                                         pgag_boost = 0x03;
604                                         mixg_boost = 0x65;
605                                 }
606                                 padg_boost = 0x77;
607
608                                 b43_radio_write(dev,
609                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
610                                         bias);
611                                 b43_radio_write(dev,
612                                         offset | B2056_TX_INTPAG_IAUX_STAT,
613                                         bias);
614                                 b43_radio_write(dev,
615                                         offset | B2056_TX_INTPAG_CASCBIAS,
616                                         cbias);
617                                 b43_radio_write(dev,
618                                         offset | B2056_TX_INTPAG_BOOST_TUNE,
619                                         pag_boost);
620                                 b43_radio_write(dev,
621                                         offset | B2056_TX_PGAG_BOOST_TUNE,
622                                         pgag_boost);
623                                 b43_radio_write(dev,
624                                         offset | B2056_TX_PADG_BOOST_TUNE,
625                                         padg_boost);
626                                 b43_radio_write(dev,
627                                         offset | B2056_TX_MIXG_BOOST_TUNE,
628                                         mixg_boost);
629                         } else {
630                                 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
631                                 b43_radio_write(dev,
632                                         offset | B2056_TX_INTPAG_IMAIN_STAT,
633                                         bias);
634                                 b43_radio_write(dev,
635                                         offset | B2056_TX_INTPAG_IAUX_STAT,
636                                         bias);
637                                 b43_radio_write(dev,
638                                         offset | B2056_TX_INTPAG_CASCBIAS,
639                                         0x30);
640                         }
641                         b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
642                 }
643         } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
644                 /* TODO */
645         }
646
647         udelay(50);
648         /* VCO calibration */
649         b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
650         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
651         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
652         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
653         b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
654         udelay(300);
655 }
656
657 static void b43_radio_init2056_pre(struct b43_wldev *dev)
658 {
659         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
660                      ~B43_NPHY_RFCTL_CMD_CHIP0PU);
661         /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
662         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
663                      B43_NPHY_RFCTL_CMD_OEPORFORCE);
664         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
665                     ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
666         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
667                     B43_NPHY_RFCTL_CMD_CHIP0PU);
668 }
669
670 static void b43_radio_init2056_post(struct b43_wldev *dev)
671 {
672         b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
673         b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
674         b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
675         msleep(1);
676         b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
677         b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
678         b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
679         /*
680         if (nphy->init_por)
681                 Call Radio 2056 Recalibrate
682         */
683 }
684
685 /*
686  * Initialize a Broadcom 2056 N-radio
687  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
688  */
689 static void b43_radio_init2056(struct b43_wldev *dev)
690 {
691         b43_radio_init2056_pre(dev);
692         b2056_upload_inittabs(dev, 0, 0);
693         b43_radio_init2056_post(dev);
694 }
695
696 /**************************************************
697  * Radio 0x2055
698  **************************************************/
699
700 static void b43_chantab_radio_upload(struct b43_wldev *dev,
701                                 const struct b43_nphy_channeltab_entry_rev2 *e)
702 {
703         b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
704         b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
705         b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
706         b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
707         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
708
709         b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
710         b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
711         b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
712         b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
713         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
714
715         b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
716         b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
717         b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
718         b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
719         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
720
721         b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
722         b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
723         b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
724         b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
725         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
726
727         b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
728         b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
729         b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
730         b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
731         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
732
733         b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
734         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
735 }
736
737 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
738 static void b43_radio_2055_setup(struct b43_wldev *dev,
739                                 const struct b43_nphy_channeltab_entry_rev2 *e)
740 {
741         B43_WARN_ON(dev->phy.rev >= 3);
742
743         b43_chantab_radio_upload(dev, e);
744         udelay(50);
745         b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
746         b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
747         b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
748         b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
749         udelay(300);
750 }
751
752 static void b43_radio_init2055_pre(struct b43_wldev *dev)
753 {
754         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
755                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
756         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
757                     B43_NPHY_RFCTL_CMD_CHIP0PU |
758                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
759         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
760                     B43_NPHY_RFCTL_CMD_PORFORCE);
761 }
762
763 static void b43_radio_init2055_post(struct b43_wldev *dev)
764 {
765         struct b43_phy_n *nphy = dev->phy.n;
766         struct ssb_sprom *sprom = dev->dev->bus_sprom;
767         int i;
768         u16 val;
769         bool workaround = false;
770
771         if (sprom->revision < 4)
772                 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
773                               && dev->dev->board_type == 0x46D
774                               && dev->dev->board_rev >= 0x41);
775         else
776                 workaround =
777                         !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
778
779         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
780         if (workaround) {
781                 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
782                 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
783         }
784         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
785         b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
786         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
787         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
788         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
789         msleep(1);
790         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
791         for (i = 0; i < 200; i++) {
792                 val = b43_radio_read(dev, B2055_CAL_COUT2);
793                 if (val & 0x80) {
794                         i = 0;
795                         break;
796                 }
797                 udelay(10);
798         }
799         if (i)
800                 b43err(dev->wl, "radio post init timeout\n");
801         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
802         b43_switch_channel(dev, dev->phy.channel);
803         b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
804         b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
805         b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
806         b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
807         b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
808         b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
809         if (!nphy->gain_boost) {
810                 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
811                 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
812         } else {
813                 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
814                 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
815         }
816         udelay(2);
817 }
818
819 /*
820  * Initialize a Broadcom 2055 N-radio
821  * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
822  */
823 static void b43_radio_init2055(struct b43_wldev *dev)
824 {
825         b43_radio_init2055_pre(dev);
826         if (b43_status(dev) < B43_STAT_INITIALIZED) {
827                 /* Follow wl, not specs. Do not force uploading all regs */
828                 b2055_upload_inittab(dev, 0, 0);
829         } else {
830                 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
831                 b2055_upload_inittab(dev, ghz5, 0);
832         }
833         b43_radio_init2055_post(dev);
834 }
835
836 /**************************************************
837  * Samples
838  **************************************************/
839
840 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
841 static int b43_nphy_load_samples(struct b43_wldev *dev,
842                                         struct b43_c32 *samples, u16 len) {
843         struct b43_phy_n *nphy = dev->phy.n;
844         u16 i;
845         u32 *data;
846
847         data = kzalloc(len * sizeof(u32), GFP_KERNEL);
848         if (!data) {
849                 b43err(dev->wl, "allocation for samples loading failed\n");
850                 return -ENOMEM;
851         }
852         if (nphy->hang_avoid)
853                 b43_nphy_stay_in_carrier_search(dev, 1);
854
855         for (i = 0; i < len; i++) {
856                 data[i] = (samples[i].i & 0x3FF << 10);
857                 data[i] |= samples[i].q & 0x3FF;
858         }
859         b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
860
861         kfree(data);
862         if (nphy->hang_avoid)
863                 b43_nphy_stay_in_carrier_search(dev, 0);
864         return 0;
865 }
866
867 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
868 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
869                                         bool test)
870 {
871         int i;
872         u16 bw, len, rot, angle;
873         struct b43_c32 *samples;
874
875
876         bw = (dev->phy.is_40mhz) ? 40 : 20;
877         len = bw << 3;
878
879         if (test) {
880                 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
881                         bw = 82;
882                 else
883                         bw = 80;
884
885                 if (dev->phy.is_40mhz)
886                         bw <<= 1;
887
888                 len = bw << 1;
889         }
890
891         samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
892         if (!samples) {
893                 b43err(dev->wl, "allocation for samples generation failed\n");
894                 return 0;
895         }
896         rot = (((freq * 36) / bw) << 16) / 100;
897         angle = 0;
898
899         for (i = 0; i < len; i++) {
900                 samples[i] = b43_cordic(angle);
901                 angle += rot;
902                 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
903                 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
904         }
905
906         i = b43_nphy_load_samples(dev, samples, len);
907         kfree(samples);
908         return (i < 0) ? 0 : len;
909 }
910
911 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
912 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
913                                         u16 wait, bool iqmode, bool dac_test)
914 {
915         struct b43_phy_n *nphy = dev->phy.n;
916         int i;
917         u16 seq_mode;
918         u32 tmp;
919
920         if (nphy->hang_avoid)
921                 b43_nphy_stay_in_carrier_search(dev, true);
922
923         if ((nphy->bb_mult_save & 0x80000000) == 0) {
924                 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
925                 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
926         }
927
928         if (!dev->phy.is_40mhz)
929                 tmp = 0x6464;
930         else
931                 tmp = 0x4747;
932         b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
933
934         if (nphy->hang_avoid)
935                 b43_nphy_stay_in_carrier_search(dev, false);
936
937         b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
938
939         if (loops != 0xFFFF)
940                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
941         else
942                 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
943
944         b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
945
946         seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
947
948         b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
949         if (iqmode) {
950                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
951                 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
952         } else {
953                 if (dac_test)
954                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
955                 else
956                         b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
957         }
958         for (i = 0; i < 100; i++) {
959                 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
960                         i = 0;
961                         break;
962                 }
963                 udelay(10);
964         }
965         if (i)
966                 b43err(dev->wl, "run samples timeout\n");
967
968         b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
969 }
970
971 /**************************************************
972  * RSSI
973  **************************************************/
974
975 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
976 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
977                                         s8 offset, u8 core, u8 rail,
978                                         enum b43_nphy_rssi_type type)
979 {
980         u16 tmp;
981         bool core1or5 = (core == 1) || (core == 5);
982         bool core2or5 = (core == 2) || (core == 5);
983
984         offset = clamp_val(offset, -32, 31);
985         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
986
987         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
988                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
989         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
990                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
991         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
992                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
993         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
994                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
995
996         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
997                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
998         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
999                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1000         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
1001                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1002         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
1003                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1004
1005         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1006                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1007         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1008                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1009         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
1010                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1011         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1012                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1013
1014         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1015                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1016         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1017                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1018         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1019                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1020         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1021                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1022
1023         if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1024                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1025         if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1026                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1027         if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1028                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1029         if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1030                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1031
1032         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
1033                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1034         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
1035                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1036
1037         if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1038                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1039         if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1040                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1041 }
1042
1043 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1044 {
1045         u8 i;
1046         u16 reg, val;
1047
1048         if (code == 0) {
1049                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1050                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1051                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1052                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1053                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1054                 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1055                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1056                 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1057         } else {
1058                 for (i = 0; i < 2; i++) {
1059                         if ((code == 1 && i == 1) || (code == 2 && !i))
1060                                 continue;
1061
1062                         reg = (i == 0) ?
1063                                 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1064                         b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1065
1066                         if (type < 3) {
1067                                 reg = (i == 0) ?
1068                                         B43_NPHY_AFECTL_C1 :
1069                                         B43_NPHY_AFECTL_C2;
1070                                 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1071
1072                                 reg = (i == 0) ?
1073                                         B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1074                                         B43_NPHY_RFCTL_LUT_TRSW_UP2;
1075                                 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1076
1077                                 if (type == 0)
1078                                         val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1079                                 else if (type == 1)
1080                                         val = 16;
1081                                 else
1082                                         val = 32;
1083                                 b43_phy_set(dev, reg, val);
1084
1085                                 reg = (i == 0) ?
1086                                         B43_NPHY_TXF_40CO_B1S0 :
1087                                         B43_NPHY_TXF_40CO_B32S1;
1088                                 b43_phy_set(dev, reg, 0x0020);
1089                         } else {
1090                                 if (type == 6)
1091                                         val = 0x0100;
1092                                 else if (type == 3)
1093                                         val = 0x0200;
1094                                 else
1095                                         val = 0x0300;
1096
1097                                 reg = (i == 0) ?
1098                                         B43_NPHY_AFECTL_C1 :
1099                                         B43_NPHY_AFECTL_C2;
1100
1101                                 b43_phy_maskset(dev, reg, 0xFCFF, val);
1102                                 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1103
1104                                 if (type != 3 && type != 6) {
1105                                         enum ieee80211_band band =
1106                                                 b43_current_band(dev->wl);
1107
1108                                         if (b43_nphy_ipa(dev))
1109                                                 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1110                                         else
1111                                                 val = 0x11;
1112                                         reg = (i == 0) ? 0x2000 : 0x3000;
1113                                         reg |= B2055_PADDRV;
1114                                         b43_radio_write16(dev, reg, val);
1115
1116                                         reg = (i == 0) ?
1117                                                 B43_NPHY_AFECTL_OVER1 :
1118                                                 B43_NPHY_AFECTL_OVER;
1119                                         b43_phy_set(dev, reg, 0x0200);
1120                                 }
1121                         }
1122                 }
1123         }
1124 }
1125
1126 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1127 {
1128         u16 val;
1129
1130         if (type < 3)
1131                 val = 0;
1132         else if (type == 6)
1133                 val = 1;
1134         else if (type == 3)
1135                 val = 2;
1136         else
1137                 val = 3;
1138
1139         val = (val << 12) | (val << 14);
1140         b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1141         b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1142
1143         if (type < 3) {
1144                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1145                                 (type + 1) << 4);
1146                 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1147                                 (type + 1) << 4);
1148         }
1149
1150         if (code == 0) {
1151                 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1152                 if (type < 3) {
1153                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1154                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1155                                   B43_NPHY_RFCTL_CMD_CORESEL));
1156                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1157                                 ~(0x1 << 12 |
1158                                   0x1 << 5 |
1159                                   0x1 << 1 |
1160                                   0x1));
1161                         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1162                                 ~B43_NPHY_RFCTL_CMD_START);
1163                         udelay(20);
1164                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1165                 }
1166         } else {
1167                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1168                 if (type < 3) {
1169                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1170                                 ~(B43_NPHY_RFCTL_CMD_RXEN |
1171                                   B43_NPHY_RFCTL_CMD_CORESEL),
1172                                 (B43_NPHY_RFCTL_CMD_RXEN |
1173                                  code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1174                         b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1175                                 (0x1 << 12 |
1176                                   0x1 << 5 |
1177                                   0x1 << 1 |
1178                                   0x1));
1179                         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1180                                 B43_NPHY_RFCTL_CMD_START);
1181                         udelay(20);
1182                         b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1183                 }
1184         }
1185 }
1186
1187 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1188 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1189 {
1190         if (dev->phy.rev >= 3)
1191                 b43_nphy_rev3_rssi_select(dev, code, type);
1192         else
1193                 b43_nphy_rev2_rssi_select(dev, code, type);
1194 }
1195
1196 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1197 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1198 {
1199         int i;
1200         for (i = 0; i < 2; i++) {
1201                 if (type == 2) {
1202                         if (i == 0) {
1203                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1204                                                   0xFC, buf[0]);
1205                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1206                                                   0xFC, buf[1]);
1207                         } else {
1208                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1209                                                   0xFC, buf[2 * i]);
1210                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1211                                                   0xFC, buf[2 * i + 1]);
1212                         }
1213                 } else {
1214                         if (i == 0)
1215                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1216                                                   0xF3, buf[0] << 2);
1217                         else
1218                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1219                                                   0xF3, buf[2 * i + 1] << 2);
1220                 }
1221         }
1222 }
1223
1224 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1225 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1226                                 u8 nsamp)
1227 {
1228         int i;
1229         int out;
1230         u16 save_regs_phy[9];
1231         u16 s[2];
1232
1233         if (dev->phy.rev >= 3) {
1234                 save_regs_phy[0] = b43_phy_read(dev,
1235                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1236                 save_regs_phy[1] = b43_phy_read(dev,
1237                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1238                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1239                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1240                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1241                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1242                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1243                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1244                 save_regs_phy[8] = 0;
1245         } else {
1246                 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1247                 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1248                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1249                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1250                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1251                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1252                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1253                 save_regs_phy[7] = 0;
1254                 save_regs_phy[8] = 0;
1255         }
1256
1257         b43_nphy_rssi_select(dev, 5, type);
1258
1259         if (dev->phy.rev < 2) {
1260                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1261                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1262         }
1263
1264         for (i = 0; i < 4; i++)
1265                 buf[i] = 0;
1266
1267         for (i = 0; i < nsamp; i++) {
1268                 if (dev->phy.rev < 2) {
1269                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1270                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1271                 } else {
1272                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1273                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1274                 }
1275
1276                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1277                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1278                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1279                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1280         }
1281         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1282                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1283
1284         if (dev->phy.rev < 2)
1285                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1286
1287         if (dev->phy.rev >= 3) {
1288                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1289                                 save_regs_phy[0]);
1290                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1291                                 save_regs_phy[1]);
1292                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1293                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1294                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1295                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1296                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1297                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1298         } else {
1299                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1300                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1301                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1302                 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1303                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1304                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1305                 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1306         }
1307
1308         return out;
1309 }
1310
1311 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1312 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1313 {
1314         int i, j;
1315         u8 state[4];
1316         u8 code, val;
1317         u16 class, override;
1318         u8 regs_save_radio[2];
1319         u16 regs_save_phy[2];
1320
1321         s8 offset[4];
1322         u8 core;
1323         u8 rail;
1324
1325         u16 clip_state[2];
1326         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1327         s32 results_min[4] = { };
1328         u8 vcm_final[4] = { };
1329         s32 results[4][4] = { };
1330         s32 miniq[4][2] = { };
1331
1332         if (type == 2) {
1333                 code = 0;
1334                 val = 6;
1335         } else if (type < 2) {
1336                 code = 25;
1337                 val = 4;
1338         } else {
1339                 B43_WARN_ON(1);
1340                 return;
1341         }
1342
1343         class = b43_nphy_classifier(dev, 0, 0);
1344         b43_nphy_classifier(dev, 7, 4);
1345         b43_nphy_read_clip_detection(dev, clip_state);
1346         b43_nphy_write_clip_detection(dev, clip_off);
1347
1348         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1349                 override = 0x140;
1350         else
1351                 override = 0x110;
1352
1353         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1354         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1355         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1356         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1357
1358         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1359         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1360         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1361         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1362
1363         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1364         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1365         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1366         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1367         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1368         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1369
1370         b43_nphy_rssi_select(dev, 5, type);
1371         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1372         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1373
1374         for (i = 0; i < 4; i++) {
1375                 u8 tmp[4];
1376                 for (j = 0; j < 4; j++)
1377                         tmp[j] = i;
1378                 if (type != 1)
1379                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1380                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1381                 if (type < 2)
1382                         for (j = 0; j < 2; j++)
1383                                 miniq[i][j] = min(results[i][2 * j],
1384                                                 results[i][2 * j + 1]);
1385         }
1386
1387         for (i = 0; i < 4; i++) {
1388                 s32 mind = 40;
1389                 u8 minvcm = 0;
1390                 s32 minpoll = 249;
1391                 s32 curr;
1392                 for (j = 0; j < 4; j++) {
1393                         if (type == 2)
1394                                 curr = abs(results[j][i]);
1395                         else
1396                                 curr = abs(miniq[j][i / 2] - code * 8);
1397
1398                         if (curr < mind) {
1399                                 mind = curr;
1400                                 minvcm = j;
1401                         }
1402
1403                         if (results[j][i] < minpoll)
1404                                 minpoll = results[j][i];
1405                 }
1406                 results_min[i] = minpoll;
1407                 vcm_final[i] = minvcm;
1408         }
1409
1410         if (type != 1)
1411                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1412
1413         for (i = 0; i < 4; i++) {
1414                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1415
1416                 if (offset[i] < 0)
1417                         offset[i] = -((abs(offset[i]) + 4) / 8);
1418                 else
1419                         offset[i] = (offset[i] + 4) / 8;
1420
1421                 if (results_min[i] == 248)
1422                         offset[i] = code - 32;
1423
1424                 core = (i / 2) ? 2 : 1;
1425                 rail = (i % 2) ? 1 : 0;
1426
1427                 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1428                                                 type);
1429         }
1430
1431         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1432         b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1433
1434         switch (state[2]) {
1435         case 1:
1436                 b43_nphy_rssi_select(dev, 1, 2);
1437                 break;
1438         case 4:
1439                 b43_nphy_rssi_select(dev, 1, 0);
1440                 break;
1441         case 2:
1442                 b43_nphy_rssi_select(dev, 1, 1);
1443                 break;
1444         default:
1445                 b43_nphy_rssi_select(dev, 1, 1);
1446                 break;
1447         }
1448
1449         switch (state[3]) {
1450         case 1:
1451                 b43_nphy_rssi_select(dev, 2, 2);
1452                 break;
1453         case 4:
1454                 b43_nphy_rssi_select(dev, 2, 0);
1455                 break;
1456         default:
1457                 b43_nphy_rssi_select(dev, 2, 1);
1458                 break;
1459         }
1460
1461         b43_nphy_rssi_select(dev, 0, type);
1462
1463         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1464         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1465         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1466         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1467
1468         b43_nphy_classifier(dev, 7, class);
1469         b43_nphy_write_clip_detection(dev, clip_state);
1470         /* Specs don't say about reset here, but it makes wl and b43 dumps
1471            identical, it really seems wl performs this */
1472         b43_nphy_reset_cca(dev);
1473 }
1474
1475 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1476 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1477 {
1478         /* TODO */
1479 }
1480
1481 /*
1482  * RSSI Calibration
1483  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1484  */
1485 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1486 {
1487         if (dev->phy.rev >= 3) {
1488                 b43_nphy_rev3_rssi_cal(dev);
1489         } else {
1490                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
1491                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
1492                 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
1493         }
1494 }
1495
1496 /**************************************************
1497  * Workarounds
1498  **************************************************/
1499
1500 static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1501 {
1502         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1503
1504         bool ghz5;
1505         bool ext_lna;
1506         u16 rssi_gain;
1507         struct nphy_gain_ctl_workaround_entry *e;
1508         u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1509         u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1510
1511         /* Prepare values */
1512         ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1513                 & B43_NPHY_BANDCTL_5GHZ;
1514         ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
1515         e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1516         if (ghz5 && dev->phy.rev >= 5)
1517                 rssi_gain = 0x90;
1518         else
1519                 rssi_gain = 0x50;
1520
1521         b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1522
1523         /* Set Clip 2 detect */
1524         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1525                         B43_NPHY_C1_CGAINI_CL2DETECT);
1526         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1527                         B43_NPHY_C2_CGAINI_CL2DETECT);
1528
1529         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1530                         0x17);
1531         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1532                         0x17);
1533         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1534         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1535         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1536         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1537         b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1538                         rssi_gain);
1539         b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1540                         rssi_gain);
1541         b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1542                         0x17);
1543         b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1544                         0x17);
1545         b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1546         b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1547
1548         b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1549         b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1550         b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1551         b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1552         b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1553         b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1554         b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1555         b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1556         b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1557         b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1558         b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1559         b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1560
1561         b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1562         b43_phy_write(dev, 0x2A7, e->init_gain);
1563         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1564                                 e->rfseq_init);
1565         b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1566
1567         /* TODO: check defines. Do not match variables names */
1568         b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1569         b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1570         b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1571         b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1572         b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1573         b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1574
1575         b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1576         b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1577         b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1578         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1579         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1580         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1581                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1582         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1583                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1584         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1585 }
1586
1587 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
1588 {
1589         struct b43_phy_n *nphy = dev->phy.n;
1590
1591         u8 i, j;
1592         u8 code;
1593         u16 tmp;
1594         u8 rfseq_events[3] = { 6, 8, 7 };
1595         u8 rfseq_delays[3] = { 10, 30, 1 };
1596
1597         /* Set Clip 2 detect */
1598         b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
1599         b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
1600
1601         /* Set narrowband clip threshold */
1602         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1603         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1604
1605         if (!dev->phy.is_40mhz) {
1606                 /* Set dwell lengths */
1607                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1608                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1609                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1610                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1611         }
1612
1613         /* Set wideband clip 2 threshold */
1614         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1615                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
1616         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1617                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
1618
1619         if (!dev->phy.is_40mhz) {
1620                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1621                         ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1622                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1623                         ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1624                 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1625                         ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1626                 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1627                         ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1628         }
1629
1630         b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1631
1632         if (nphy->gain_boost) {
1633                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1634                         dev->phy.is_40mhz)
1635                         code = 4;
1636                 else
1637                         code = 5;
1638         } else {
1639                 code = dev->phy.is_40mhz ? 6 : 7;
1640         }
1641
1642         /* Set HPVGA2 index */
1643         b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
1644                         code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1645         b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
1646                         code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1647
1648         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1649         /* specs say about 2 loops, but wl does 4 */
1650         for (i = 0; i < 4; i++)
1651                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
1652
1653         b43_nphy_adjust_lna_gain_table(dev);
1654
1655         if (nphy->elna_gain_config) {
1656                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1657                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1658                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1659                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1660                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1661
1662                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1663                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1664                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1665                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1666                 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1667
1668                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1669                 /* specs say about 2 loops, but wl does 4 */
1670                 for (i = 0; i < 4; i++)
1671                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1672                                                 (code << 8 | 0x74));
1673         }
1674
1675         if (dev->phy.rev == 2) {
1676                 for (i = 0; i < 4; i++) {
1677                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1678                                         (0x0400 * i) + 0x0020);
1679                         for (j = 0; j < 21; j++) {
1680                                 tmp = j * (i < 2 ? 3 : 1);
1681                                 b43_phy_write(dev,
1682                                         B43_NPHY_TABLE_DATALO, tmp);
1683                         }
1684                 }
1685         }
1686
1687         b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
1688         b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1689                 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1690                 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1691
1692         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1693                 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
1694 }
1695
1696 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1697 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
1698 {
1699         if (dev->phy.rev >= 3)
1700                 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
1701         else
1702                 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
1703 }
1704
1705 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1706 {
1707         struct b43_phy_n *nphy = dev->phy.n;
1708         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1709
1710         /* TX to RX */
1711         u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
1712         u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
1713         /* RX to TX */
1714         u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
1715                                         0x1F };
1716         u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
1717         u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
1718         u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
1719
1720         u16 tmp16;
1721         u32 tmp32;
1722
1723         b43_phy_write(dev, 0x23f, 0x1f8);
1724         b43_phy_write(dev, 0x240, 0x1f8);
1725
1726         tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1727         tmp32 &= 0xffffff;
1728         b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1729
1730         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1731         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1732         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1733         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1734         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1735         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1736
1737         b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1738         b43_phy_write(dev, 0x2AE, 0x000C);
1739
1740         /* TX to RX */
1741         b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
1742                                  ARRAY_SIZE(tx2rx_events));
1743
1744         /* RX to TX */
1745         if (b43_nphy_ipa(dev))
1746                 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
1747                                 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
1748         if (nphy->hw_phyrxchain != 3 &&
1749             nphy->hw_phyrxchain != nphy->hw_phytxchain) {
1750                 if (b43_nphy_ipa(dev)) {
1751                         rx2tx_delays[5] = 59;
1752                         rx2tx_delays[6] = 1;
1753                         rx2tx_events[7] = 0x1F;
1754                 }
1755                 b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays,
1756                                          ARRAY_SIZE(rx2tx_events));
1757         }
1758
1759         tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1760                 0x2 : 0x9C40;
1761         b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1762
1763         b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1764
1765         b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1766         b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1767
1768         b43_nphy_gain_ctl_workarounds(dev);
1769
1770         b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
1771         b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
1772
1773         /* TODO */
1774
1775         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1776         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1777         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1778         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1779         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1780         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1781         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1782         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1783         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1784         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1785         b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1786         b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1787
1788         /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1789
1790         if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1791              b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1792             (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1793              b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1794                 tmp32 = 0x00088888;
1795         else
1796                 tmp32 = 0x88888888;
1797         b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1798         b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1799         b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1800
1801         if (dev->phy.rev == 4 &&
1802                 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1803                 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1804                                 0x70);
1805                 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1806                                 0x70);
1807         }
1808
1809         b43_phy_write(dev, 0x224, 0x03eb);
1810         b43_phy_write(dev, 0x225, 0x03eb);
1811         b43_phy_write(dev, 0x226, 0x0341);
1812         b43_phy_write(dev, 0x227, 0x0341);
1813         b43_phy_write(dev, 0x228, 0x042b);
1814         b43_phy_write(dev, 0x229, 0x042b);
1815         b43_phy_write(dev, 0x22a, 0x0381);
1816         b43_phy_write(dev, 0x22b, 0x0381);
1817         b43_phy_write(dev, 0x22c, 0x042b);
1818         b43_phy_write(dev, 0x22d, 0x042b);
1819         b43_phy_write(dev, 0x22e, 0x0381);
1820         b43_phy_write(dev, 0x22f, 0x0381);
1821 }
1822
1823 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
1824 {
1825         struct ssb_sprom *sprom = dev->dev->bus_sprom;
1826         struct b43_phy *phy = &dev->phy;
1827         struct b43_phy_n *nphy = phy->n;
1828
1829         u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1830         u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1831
1832         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1833         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1834
1835         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1836             nphy->band5g_pwrgain) {
1837                 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1838                 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1839         } else {
1840                 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1841                 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1842         }
1843
1844         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1845         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1846         b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1847         b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1848
1849         if (dev->phy.rev < 2) {
1850                 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1851                 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1852                 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1853                 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1854                 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1855                 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1856         }
1857
1858         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1859         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1860         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1861         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1862
1863         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
1864             dev->dev->board_type == 0x8B) {
1865                 delays1[0] = 0x1;
1866                 delays1[5] = 0x14;
1867         }
1868         b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1869         b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1870
1871         b43_nphy_gain_ctl_workarounds(dev);
1872
1873         if (dev->phy.rev < 2) {
1874                 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1875                         b43_hf_write(dev, b43_hf_read(dev) |
1876                                         B43_HF_MLADVW);
1877         } else if (dev->phy.rev == 2) {
1878                 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1879                 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1880         }
1881
1882         if (dev->phy.rev < 2)
1883                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1884                                 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1885
1886         /* Set phase track alpha and beta */
1887         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1888         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1889         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1890         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1891         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1892         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1893
1894         b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1895                         ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1896         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1897         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1898         b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1899
1900         if (dev->phy.rev == 2)
1901                 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1902                                 B43_NPHY_FINERX2_CGC_DECGC);
1903 }
1904
1905 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1906 static void b43_nphy_workarounds(struct b43_wldev *dev)
1907 {
1908         struct b43_phy *phy = &dev->phy;
1909         struct b43_phy_n *nphy = phy->n;
1910
1911         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1912                 b43_nphy_classifier(dev, 1, 0);
1913         else
1914                 b43_nphy_classifier(dev, 1, 1);
1915
1916         if (nphy->hang_avoid)
1917                 b43_nphy_stay_in_carrier_search(dev, 1);
1918
1919         b43_phy_set(dev, B43_NPHY_IQFLIP,
1920                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1921
1922         if (dev->phy.rev >= 3)
1923                 b43_nphy_workarounds_rev3plus(dev);
1924         else
1925                 b43_nphy_workarounds_rev1_2(dev);
1926
1927         if (nphy->hang_avoid)
1928                 b43_nphy_stay_in_carrier_search(dev, 0);
1929 }
1930
1931 /**************************************************
1932  * Tx and Rx
1933  **************************************************/
1934
1935 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
1936 {//TODO
1937 }
1938
1939 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
1940 {//TODO
1941 }
1942
1943 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
1944                                                         bool ignore_tssi)
1945 {//TODO
1946         return B43_TXPWR_RES_DONE;
1947 }
1948
1949 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
1950 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
1951 {
1952         struct b43_phy_n *nphy = dev->phy.n;
1953         u8 i;
1954         u16 bmask, val, tmp;
1955         enum ieee80211_band band = b43_current_band(dev->wl);
1956
1957         if (nphy->hang_avoid)
1958                 b43_nphy_stay_in_carrier_search(dev, 1);
1959
1960         nphy->txpwrctrl = enable;
1961         if (!enable) {
1962                 if (dev->phy.rev >= 3 &&
1963                     (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
1964                      (B43_NPHY_TXPCTL_CMD_COEFF |
1965                       B43_NPHY_TXPCTL_CMD_HWPCTLEN |
1966                       B43_NPHY_TXPCTL_CMD_PCTLEN))) {
1967                         /* We disable enabled TX pwr ctl, save it's state */
1968                         nphy->tx_pwr_idx[0] = b43_phy_read(dev,
1969                                                 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
1970                         nphy->tx_pwr_idx[1] = b43_phy_read(dev,
1971                                                 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
1972                 }
1973
1974                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
1975                 for (i = 0; i < 84; i++)
1976                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
1977
1978                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
1979                 for (i = 0; i < 84; i++)
1980                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
1981
1982                 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
1983                 if (dev->phy.rev >= 3)
1984                         tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
1985                 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
1986
1987                 if (dev->phy.rev >= 3) {
1988                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
1989                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
1990                 } else {
1991                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
1992                 }
1993
1994                 if (dev->phy.rev == 2)
1995                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
1996                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
1997                 else if (dev->phy.rev < 2)
1998                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
1999                                 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
2000
2001                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2002                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
2003         } else {
2004                 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2005                                     nphy->adj_pwr_tbl);
2006                 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2007                                     nphy->adj_pwr_tbl);
2008
2009                 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2010                         B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2011                 /* wl does useless check for "enable" param here */
2012                 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2013                 if (dev->phy.rev >= 3) {
2014                         bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2015                         if (val)
2016                                 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2017                 }
2018                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
2019
2020                 if (band == IEEE80211_BAND_5GHZ) {
2021                         b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2022                                         ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2023                         if (dev->phy.rev > 1)
2024                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2025                                                 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2026                                                 0x64);
2027                 }
2028
2029                 if (dev->phy.rev >= 3) {
2030                         if (nphy->tx_pwr_idx[0] != 128 &&
2031                             nphy->tx_pwr_idx[1] != 128) {
2032                                 /* Recover TX pwr ctl state */
2033                                 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2034                                                 ~B43_NPHY_TXPCTL_CMD_INIT,
2035                                                 nphy->tx_pwr_idx[0]);
2036                                 if (dev->phy.rev > 1)
2037                                         b43_phy_maskset(dev,
2038                                                 B43_NPHY_TXPCTL_INIT,
2039                                                 ~0xff, nphy->tx_pwr_idx[1]);
2040                         }
2041                 }
2042
2043                 if (dev->phy.rev >= 3) {
2044                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2045                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2046                 } else {
2047                         b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2048                 }
2049
2050                 if (dev->phy.rev == 2)
2051                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2052                 else if (dev->phy.rev < 2)
2053                         b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
2054
2055                 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2056                         b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
2057
2058                 if (b43_nphy_ipa(dev)) {
2059                         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2060                         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
2061                 }
2062         }
2063
2064         if (nphy->hang_avoid)
2065                 b43_nphy_stay_in_carrier_search(dev, 0);
2066 }
2067
2068 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
2069 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
2070 {
2071         struct b43_phy_n *nphy = dev->phy.n;
2072         struct ssb_sprom *sprom = dev->dev->bus_sprom;
2073
2074         u8 txpi[2], bbmult, i;
2075         u16 tmp, radio_gain, dac_gain;
2076         u16 freq = dev->phy.channel_freq;
2077         u32 txgain;
2078         /* u32 gaintbl; rev3+ */
2079
2080         if (nphy->hang_avoid)
2081                 b43_nphy_stay_in_carrier_search(dev, 1);
2082
2083         if (dev->phy.rev >= 7) {
2084                 txpi[0] = txpi[1] = 30;
2085         } else if (dev->phy.rev >= 3) {
2086                 txpi[0] = 40;
2087                 txpi[1] = 40;
2088         } else if (sprom->revision < 4) {
2089                 txpi[0] = 72;
2090                 txpi[1] = 72;
2091         } else {
2092                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2093                         txpi[0] = sprom->txpid2g[0];
2094                         txpi[1] = sprom->txpid2g[1];
2095                 } else if (freq >= 4900 && freq < 5100) {
2096                         txpi[0] = sprom->txpid5gl[0];
2097                         txpi[1] = sprom->txpid5gl[1];
2098                 } else if (freq >= 5100 && freq < 5500) {
2099                         txpi[0] = sprom->txpid5g[0];
2100                         txpi[1] = sprom->txpid5g[1];
2101                 } else if (freq >= 5500) {
2102                         txpi[0] = sprom->txpid5gh[0];
2103                         txpi[1] = sprom->txpid5gh[1];
2104                 } else {
2105                         txpi[0] = 91;
2106                         txpi[1] = 91;
2107                 }
2108         }
2109         if (dev->phy.rev < 7 &&
2110             (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 10))
2111                 txpi[0] = txpi[1] = 91;
2112
2113         /*
2114         for (i = 0; i < 2; i++) {
2115                 nphy->txpwrindex[i].index_internal = txpi[i];
2116                 nphy->txpwrindex[i].index_internal_save = txpi[i];
2117         }
2118         */
2119
2120         for (i = 0; i < 2; i++) {
2121                 if (dev->phy.rev >= 3) {
2122                         if (b43_nphy_ipa(dev)) {
2123                                 txgain = *(b43_nphy_get_ipa_gain_table(dev) +
2124                                                 txpi[i]);
2125                         } else if (b43_current_band(dev->wl) ==
2126                                    IEEE80211_BAND_5GHZ) {
2127                                 /* FIXME: use 5GHz tables */
2128                                 txgain =
2129                                         b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
2130                         } else {
2131                                 if (dev->phy.rev >= 5 &&
2132                                     sprom->fem.ghz5.extpa_gain == 3)
2133                                         ; /* FIXME: 5GHz_txgain_HiPwrEPA */
2134                                 txgain =
2135                                         b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
2136                         }
2137                         radio_gain = (txgain >> 16) & 0x1FFFF;
2138                 } else {
2139                         txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
2140                         radio_gain = (txgain >> 16) & 0x1FFF;
2141                 }
2142
2143                 if (dev->phy.rev >= 7)
2144                         dac_gain = (txgain >> 8) & 0x7;
2145                 else
2146                         dac_gain = (txgain >> 8) & 0x3F;
2147                 bbmult = txgain & 0xFF;
2148
2149                 if (dev->phy.rev >= 3) {
2150                         if (i == 0)
2151                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2152                         else
2153                                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2154                 } else {
2155                         b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2156                 }
2157
2158                 if (i == 0)
2159                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
2160                 else
2161                         b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
2162
2163                 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
2164
2165                 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
2166                 if (i == 0)
2167                         tmp = (tmp & 0x00FF) | (bbmult << 8);
2168                 else
2169                         tmp = (tmp & 0xFF00) | bbmult;
2170                 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
2171
2172                 if (b43_nphy_ipa(dev)) {
2173                         u32 tmp32;
2174                         u16 reg = (i == 0) ?
2175                                 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
2176                         tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
2177                                                               576 + txpi[i]));
2178                         b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
2179                         b43_phy_set(dev, reg, 0x4);
2180                 }
2181         }
2182
2183         b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
2184
2185         if (nphy->hang_avoid)
2186                 b43_nphy_stay_in_carrier_search(dev, 0);
2187 }
2188
2189 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
2190 {
2191         struct b43_phy *phy = &dev->phy;
2192
2193         const u32 *table = NULL;
2194 #if 0
2195         TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
2196         u32 rfpwr_offset;
2197         u8 pga_gain;
2198         int i;
2199 #endif
2200
2201         if (phy->rev >= 3) {
2202                 if (b43_nphy_ipa(dev)) {
2203                         table = b43_nphy_get_ipa_gain_table(dev);
2204                 } else {
2205                         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2206                                 if (phy->rev == 3)
2207                                         table = b43_ntab_tx_gain_rev3_5ghz;
2208                                 if (phy->rev == 4)
2209                                         table = b43_ntab_tx_gain_rev4_5ghz;
2210                                 else
2211                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
2212                         } else {
2213                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
2214                         }
2215                 }
2216         } else {
2217                 table = b43_ntab_tx_gain_rev0_1_2;
2218         }
2219         b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
2220         b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
2221
2222         if (phy->rev >= 3) {
2223 #if 0
2224                 nphy->gmval = (table[0] >> 16) & 0x7000;
2225
2226                 for (i = 0; i < 128; i++) {
2227                         pga_gain = (table[i] >> 24) & 0xF;
2228                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2229                                 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
2230                         else
2231                                 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
2232                         b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
2233                                        rfpwr_offset);
2234                         b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
2235                                        rfpwr_offset);
2236                 }
2237 #endif
2238         }
2239 }
2240
2241 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
2242 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
2243 {
2244         struct b43_phy_n *nphy = dev->phy.n;
2245         enum ieee80211_band band;
2246         u16 tmp;
2247
2248         if (!enable) {
2249                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
2250                                                        B43_NPHY_RFCTL_INTC1);
2251                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
2252                                                        B43_NPHY_RFCTL_INTC2);
2253                 band = b43_current_band(dev->wl);
2254                 if (dev->phy.rev >= 3) {
2255                         if (band == IEEE80211_BAND_5GHZ)
2256                                 tmp = 0x600;
2257                         else
2258                                 tmp = 0x480;
2259                 } else {
2260                         if (band == IEEE80211_BAND_5GHZ)
2261                                 tmp = 0x180;
2262                         else
2263                                 tmp = 0x120;
2264                 }
2265                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2266                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2267         } else {
2268                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
2269                                 nphy->rfctrl_intc1_save);
2270                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
2271                                 nphy->rfctrl_intc2_save);
2272         }
2273 }
2274
2275 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
2276 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
2277 {
2278         u16 tmp;
2279
2280         if (dev->phy.rev >= 3) {
2281                 if (b43_nphy_ipa(dev)) {
2282                         tmp = 4;
2283                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
2284                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
2285                 }
2286
2287                 tmp = 1;
2288                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
2289                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
2290         }
2291 }
2292
2293 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2294 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2295 {
2296         struct b43_phy_n *nphy = dev->phy.n;
2297
2298         bool override = false;
2299         u16 chain = 0x33;
2300
2301         if (nphy->txrx_chain == 0) {
2302                 chain = 0x11;
2303                 override = true;
2304         } else if (nphy->txrx_chain == 1) {
2305                 chain = 0x22;
2306                 override = true;
2307         }
2308
2309         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2310                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2311                         chain);
2312
2313         if (override)
2314                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2315                                 B43_NPHY_RFSEQMODE_CAOVER);
2316         else
2317                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2318                                 ~B43_NPHY_RFSEQMODE_CAOVER);
2319 }
2320
2321 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
2322 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
2323                                 u16 samps, u8 time, bool wait)
2324 {
2325         int i;
2326         u16 tmp;
2327
2328         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
2329         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
2330         if (wait)
2331                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
2332         else
2333                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
2334
2335         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
2336
2337         for (i = 1000; i; i--) {
2338                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
2339                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
2340                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
2341                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
2342                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
2343                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
2344                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
2345                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
2346
2347                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
2348                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
2349                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
2350                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
2351                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
2352                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
2353                         return;
2354                 }
2355                 udelay(10);
2356         }
2357         memset(est, 0, sizeof(*est));
2358 }
2359
2360 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
2361 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
2362                                         struct b43_phy_n_iq_comp *pcomp)
2363 {
2364         if (write) {
2365                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
2366                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
2367                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
2368                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
2369         } else {
2370                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
2371                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
2372                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
2373                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
2374         }
2375 }
2376
2377 #if 0
2378 /* Ready but not used anywhere */
2379 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
2380 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
2381 {
2382         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2383
2384         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
2385         if (core == 0) {
2386                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
2387                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2388         } else {
2389                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2390                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2391         }
2392         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
2393         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
2394         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
2395         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
2396         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
2397         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
2398         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2399         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2400 }
2401
2402 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
2403 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
2404 {
2405         u8 rxval, txval;
2406         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2407
2408         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2409         if (core == 0) {
2410                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2411                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2412         } else {
2413                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2414                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2415         }
2416         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2417         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2418         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2419         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2420         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
2421         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2422         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2423         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2424
2425         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2426         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2427
2428         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2429                         ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
2430                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2431         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2432                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
2433         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
2434                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
2435         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
2436                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
2437
2438         if (core == 0) {
2439                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
2440                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
2441         } else {
2442                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
2443                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
2444         }
2445
2446         b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
2447         b43_nphy_rf_control_override(dev, 8, 0, 3, false);
2448         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
2449
2450         if (core == 0) {
2451                 rxval = 1;
2452                 txval = 8;
2453         } else {
2454                 rxval = 4;
2455                 txval = 2;
2456         }
2457         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
2458         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
2459 }
2460 #endif
2461
2462 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
2463 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
2464 {
2465         int i;
2466         s32 iq;
2467         u32 ii;
2468         u32 qq;
2469         int iq_nbits, qq_nbits;
2470         int arsh, brsh;
2471         u16 tmp, a, b;
2472
2473         struct nphy_iq_est est;
2474         struct b43_phy_n_iq_comp old;
2475         struct b43_phy_n_iq_comp new = { };
2476         bool error = false;
2477
2478         if (mask == 0)
2479                 return;
2480
2481         b43_nphy_rx_iq_coeffs(dev, false, &old);
2482         b43_nphy_rx_iq_coeffs(dev, true, &new);
2483         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
2484         new = old;
2485
2486         for (i = 0; i < 2; i++) {
2487                 if (i == 0 && (mask & 1)) {
2488                         iq = est.iq0_prod;
2489                         ii = est.i0_pwr;
2490                         qq = est.q0_pwr;
2491                 } else if (i == 1 && (mask & 2)) {
2492                         iq = est.iq1_prod;
2493                         ii = est.i1_pwr;
2494                         qq = est.q1_pwr;
2495                 } else {
2496                         continue;
2497                 }
2498
2499                 if (ii + qq < 2) {
2500                         error = true;
2501                         break;
2502                 }
2503
2504                 iq_nbits = fls(abs(iq));
2505                 qq_nbits = fls(qq);
2506
2507                 arsh = iq_nbits - 20;
2508                 if (arsh >= 0) {
2509                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
2510                         tmp = ii >> arsh;
2511                 } else {
2512                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
2513                         tmp = ii << -arsh;
2514                 }
2515                 if (tmp == 0) {
2516                         error = true;
2517                         break;
2518                 }
2519                 a /= tmp;
2520
2521                 brsh = qq_nbits - 11;
2522                 if (brsh >= 0) {
2523                         b = (qq << (31 - qq_nbits));
2524                         tmp = ii >> brsh;
2525                 } else {
2526                         b = (qq << (31 - qq_nbits));
2527                         tmp = ii << -brsh;
2528                 }
2529                 if (tmp == 0) {
2530                         error = true;
2531                         break;
2532                 }
2533                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
2534
2535                 if (i == 0 && (mask & 0x1)) {
2536                         if (dev->phy.rev >= 3) {
2537                                 new.a0 = a & 0x3FF;
2538                                 new.b0 = b & 0x3FF;
2539                         } else {
2540                                 new.a0 = b & 0x3FF;
2541                                 new.b0 = a & 0x3FF;
2542                         }
2543                 } else if (i == 1 && (mask & 0x2)) {
2544                         if (dev->phy.rev >= 3) {
2545                                 new.a1 = a & 0x3FF;
2546                                 new.b1 = b & 0x3FF;
2547                         } else {
2548                                 new.a1 = b & 0x3FF;
2549                                 new.b1 = a & 0x3FF;
2550                         }
2551                 }
2552         }
2553
2554         if (error)
2555                 new = old;
2556
2557         b43_nphy_rx_iq_coeffs(dev, true, &new);
2558 }
2559
2560 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
2561 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
2562 {
2563         u16 array[4];
2564         b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
2565
2566         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
2567         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
2568         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
2569         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
2570 }
2571
2572 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2573 static void b43_nphy_stop_playback(struct b43_wldev *dev)
2574 {
2575         struct b43_phy_n *nphy = dev->phy.n;
2576         u16 tmp;
2577
2578         if (nphy->hang_avoid)
2579                 b43_nphy_stay_in_carrier_search(dev, 1);
2580
2581         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2582         if (tmp & 0x1)
2583                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2584         else if (tmp & 0x2)
2585                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2586
2587         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2588
2589         if (nphy->bb_mult_save & 0x80000000) {
2590                 tmp = nphy->bb_mult_save & 0xFFFF;
2591                 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2592                 nphy->bb_mult_save = 0;
2593         }
2594
2595         if (nphy->hang_avoid)
2596                 b43_nphy_stay_in_carrier_search(dev, 0);
2597 }
2598
2599 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
2600 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
2601 {
2602         struct b43_phy_n *nphy = dev->phy.n;
2603
2604         u8 channel = dev->phy.channel;
2605         int tone[2] = { 57, 58 };
2606         u32 noise[2] = { 0x3FF, 0x3FF };
2607
2608         B43_WARN_ON(dev->phy.rev < 3);
2609
2610         if (nphy->hang_avoid)
2611                 b43_nphy_stay_in_carrier_search(dev, 1);
2612
2613         if (nphy->gband_spurwar_en) {
2614                 /* TODO: N PHY Adjust Analog Pfbw (7) */
2615                 if (channel == 11 && dev->phy.is_40mhz)
2616                         ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
2617                 else
2618                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
2619                 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
2620         }
2621
2622         if (nphy->aband_spurwar_en) {
2623                 if (channel == 54) {
2624                         tone[0] = 0x20;
2625                         noise[0] = 0x25F;
2626                 } else if (channel == 38 || channel == 102 || channel == 118) {
2627                         if (0 /* FIXME */) {
2628                                 tone[0] = 0x20;
2629                                 noise[0] = 0x21F;
2630                         } else {
2631                                 tone[0] = 0;
2632                                 noise[0] = 0;
2633                         }
2634                 } else if (channel == 134) {
2635                         tone[0] = 0x20;
2636                         noise[0] = 0x21F;
2637                 } else if (channel == 151) {
2638                         tone[0] = 0x10;
2639                         noise[0] = 0x23F;
2640                 } else if (channel == 153 || channel == 161) {
2641                         tone[0] = 0x30;
2642                         noise[0] = 0x23F;
2643                 } else {
2644                         tone[0] = 0;
2645                         noise[0] = 0;
2646                 }
2647
2648                 if (!tone[0] && !noise[0])
2649                         ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
2650                 else
2651                         ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
2652         }
2653
2654         if (nphy->hang_avoid)
2655                 b43_nphy_stay_in_carrier_search(dev, 0);
2656 }
2657
2658 /*
2659  * Transmits a known value for LO calibration
2660  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2661  */
2662 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2663                                 bool iqmode, bool dac_test)
2664 {
2665         u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2666         if (samp == 0)
2667                 return -1;
2668         b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2669         return 0;
2670 }
2671
2672 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
2673 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
2674 {
2675         struct b43_phy_n *nphy = dev->phy.n;
2676         int i, j;
2677         u32 tmp;
2678         u32 cur_real, cur_imag, real_part, imag_part;
2679
2680         u16 buffer[7];
2681
2682         if (nphy->hang_avoid)
2683                 b43_nphy_stay_in_carrier_search(dev, true);
2684
2685         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2686
2687         for (i = 0; i < 2; i++) {
2688                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
2689                         (buffer[i * 2 + 1] & 0x3FF);
2690                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2691                                 (((i + 26) << 10) | 320));
2692                 for (j = 0; j < 128; j++) {
2693                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
2694                                         ((tmp >> 16) & 0xFFFF));
2695                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2696                                         (tmp & 0xFFFF));
2697                 }
2698         }
2699
2700         for (i = 0; i < 2; i++) {
2701                 tmp = buffer[5 + i];
2702                 real_part = (tmp >> 8) & 0xFF;
2703                 imag_part = (tmp & 0xFF);
2704                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2705                                 (((i + 26) << 10) | 448));
2706
2707                 if (dev->phy.rev >= 3) {
2708                         cur_real = real_part;
2709                         cur_imag = imag_part;
2710                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
2711                 }
2712
2713                 for (j = 0; j < 128; j++) {
2714                         if (dev->phy.rev < 3) {
2715                                 cur_real = (real_part * loscale[j] + 128) >> 8;
2716                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
2717                                 tmp = ((cur_real & 0xFF) << 8) |
2718                                         (cur_imag & 0xFF);
2719                         }
2720                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
2721                                         ((tmp >> 16) & 0xFFFF));
2722                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2723                                         (tmp & 0xFFFF));
2724                 }
2725         }
2726
2727         if (dev->phy.rev >= 3) {
2728                 b43_shm_write16(dev, B43_SHM_SHARED,
2729                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
2730                 b43_shm_write16(dev, B43_SHM_SHARED,
2731                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
2732         }
2733
2734         if (nphy->hang_avoid)
2735                 b43_nphy_stay_in_carrier_search(dev, false);
2736 }
2737
2738 /*
2739  * Restore RSSI Calibration
2740  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2741  */
2742 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2743 {
2744         struct b43_phy_n *nphy = dev->phy.n;
2745
2746         u16 *rssical_radio_regs = NULL;
2747         u16 *rssical_phy_regs = NULL;
2748
2749         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2750                 if (!nphy->rssical_chanspec_2G.center_freq)
2751                         return;
2752                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2753                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2754         } else {
2755                 if (!nphy->rssical_chanspec_5G.center_freq)
2756                         return;
2757                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2758                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2759         }
2760
2761         /* TODO use some definitions */
2762         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2763         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2764
2765         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2766         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2767         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2768         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2769
2770         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2771         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2772         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2773         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2774
2775         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2776         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2777         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2778         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2779 }
2780
2781 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2782 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2783 {
2784         struct b43_phy_n *nphy = dev->phy.n;
2785         u16 *save = nphy->tx_rx_cal_radio_saveregs;
2786         u16 tmp;
2787         u8 offset, i;
2788
2789         if (dev->phy.rev >= 3) {
2790             for (i = 0; i < 2; i++) {
2791                 tmp = (i == 0) ? 0x2000 : 0x3000;
2792                 offset = i * 11;
2793
2794                 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2795                 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2796                 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2797                 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2798                 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2799                 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2800                 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2801                 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2802                 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2803                 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2804                 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2805
2806                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2807                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2808                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2809                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2810                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2811                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2812                         if (nphy->ipa5g_on) {
2813                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2814                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2815                         } else {
2816                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2817                                 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2818                         }
2819                         b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2820                 } else {
2821                         b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2822                         b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2823                         b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2824                         b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2825                         b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2826                         b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2827                         if (nphy->ipa2g_on) {
2828                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2829                                 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2830                                         (dev->phy.rev < 5) ? 0x11 : 0x01);
2831                         } else {
2832                                 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2833                                 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2834                         }
2835                 }
2836                 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2837                 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2838                 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2839             }
2840         } else {
2841                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2842                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2843
2844                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2845                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2846
2847                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2848                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2849
2850                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2851                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2852
2853                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2854                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2855
2856                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2857                     B43_NPHY_BANDCTL_5GHZ)) {
2858                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2859                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2860                 } else {
2861                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2862                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2863                 }
2864
2865                 if (dev->phy.rev < 2) {
2866                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2867                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2868                 } else {
2869                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2870                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2871                 }
2872         }
2873 }
2874
2875 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2876 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2877                                         struct nphy_txgains target,
2878                                         struct nphy_iqcal_params *params)
2879 {
2880         int i, j, indx;
2881         u16 gain;
2882
2883         if (dev->phy.rev >= 3) {
2884                 params->txgm = target.txgm[core];
2885                 params->pga = target.pga[core];
2886                 params->pad = target.pad[core];
2887                 params->ipa = target.ipa[core];
2888                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2889                                         (params->pad << 4) | (params->ipa);
2890                 for (j = 0; j < 5; j++)
2891                         params->ncorr[j] = 0x79;
2892         } else {
2893                 gain = (target.pad[core]) | (target.pga[core] << 4) |
2894                         (target.txgm[core] << 8);
2895
2896                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2897                         1 : 0;
2898                 for (i = 0; i < 9; i++)
2899                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
2900                                 break;
2901                 i = min(i, 8);
2902
2903                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2904                 params->pga = tbl_iqcal_gainparams[indx][i][2];
2905                 params->pad = tbl_iqcal_gainparams[indx][i][3];
2906                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2907                                         (params->pad << 2);
2908                 for (j = 0; j < 4; j++)
2909                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2910         }
2911 }
2912
2913 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2914 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2915 {
2916         struct b43_phy_n *nphy = dev->phy.n;
2917         int i;
2918         u16 scale, entry;
2919
2920         u16 tmp = nphy->txcal_bbmult;
2921         if (core == 0)
2922                 tmp >>= 8;
2923         tmp &= 0xff;
2924
2925         for (i = 0; i < 18; i++) {
2926                 scale = (ladder_lo[i].percent * tmp) / 100;
2927                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2928                 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2929
2930                 scale = (ladder_iq[i].percent * tmp) / 100;
2931                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2932                 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2933         }
2934 }
2935
2936 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2937 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2938 {
2939         int i;
2940         for (i = 0; i < 15; i++)
2941                 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2942                                 tbl_tx_filter_coef_rev4[2][i]);
2943 }
2944
2945 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2946 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2947 {
2948         int i, j;
2949         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2950         static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
2951
2952         for (i = 0; i < 3; i++)
2953                 for (j = 0; j < 15; j++)
2954                         b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2955                                         tbl_tx_filter_coef_rev4[i][j]);
2956
2957         if (dev->phy.is_40mhz) {
2958                 for (j = 0; j < 15; j++)
2959                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2960                                         tbl_tx_filter_coef_rev4[3][j]);
2961         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2962                 for (j = 0; j < 15; j++)
2963                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2964                                         tbl_tx_filter_coef_rev4[5][j]);
2965         }
2966
2967         if (dev->phy.channel == 14)
2968                 for (j = 0; j < 15; j++)
2969                         b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2970                                         tbl_tx_filter_coef_rev4[6][j]);
2971 }
2972
2973 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2974 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2975 {
2976         struct b43_phy_n *nphy = dev->phy.n;
2977
2978         u16 curr_gain[2];
2979         struct nphy_txgains target;
2980         const u32 *table = NULL;
2981
2982         if (!nphy->txpwrctrl) {
2983                 int i;
2984
2985                 if (nphy->hang_avoid)
2986                         b43_nphy_stay_in_carrier_search(dev, true);
2987                 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2988                 if (nphy->hang_avoid)
2989                         b43_nphy_stay_in_carrier_search(dev, false);
2990
2991                 for (i = 0; i < 2; ++i) {
2992                         if (dev->phy.rev >= 3) {
2993                                 target.ipa[i] = curr_gain[i] & 0x000F;
2994                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2995                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2996                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2997                         } else {
2998                                 target.ipa[i] = curr_gain[i] & 0x0003;
2999                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
3000                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
3001                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
3002                         }
3003                 }
3004         } else {
3005                 int i;
3006                 u16 index[2];
3007                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
3008                         B43_NPHY_TXPCTL_STAT_BIDX) >>
3009                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3010                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
3011                         B43_NPHY_TXPCTL_STAT_BIDX) >>
3012                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3013
3014                 for (i = 0; i < 2; ++i) {
3015                         if (dev->phy.rev >= 3) {
3016                                 enum ieee80211_band band =
3017                                         b43_current_band(dev->wl);
3018
3019                                 if (b43_nphy_ipa(dev)) {
3020                                         table = b43_nphy_get_ipa_gain_table(dev);
3021                                 } else {
3022                                         if (band == IEEE80211_BAND_5GHZ) {
3023                                                 if (dev->phy.rev == 3)
3024                                                         table = b43_ntab_tx_gain_rev3_5ghz;
3025                                                 else if (dev->phy.rev == 4)
3026                                                         table = b43_ntab_tx_gain_rev4_5ghz;
3027                                                 else
3028                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
3029                                         } else {
3030                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
3031                                         }
3032                                 }
3033
3034                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
3035                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
3036                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
3037                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
3038                         } else {
3039                                 table = b43_ntab_tx_gain_rev0_1_2;
3040
3041                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
3042                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
3043                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
3044                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
3045                         }
3046                 }
3047         }
3048
3049         return target;
3050 }
3051
3052 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
3053 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
3054 {
3055         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3056
3057         if (dev->phy.rev >= 3) {
3058                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
3059                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3060                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3061                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
3062                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
3063                 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
3064                 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
3065                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
3066                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
3067                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3068                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3069                 b43_nphy_reset_cca(dev);
3070         } else {
3071                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
3072                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
3073                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3074                 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
3075                 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
3076                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
3077                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
3078         }
3079 }
3080
3081 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
3082 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
3083 {
3084         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3085         u16 tmp;
3086
3087         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3088         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3089         if (dev->phy.rev >= 3) {
3090                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
3091                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
3092
3093                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3094                 regs[2] = tmp;
3095                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
3096
3097                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3098                 regs[3] = tmp;
3099                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
3100
3101                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
3102                 b43_phy_mask(dev, B43_NPHY_BBCFG,
3103                              ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
3104
3105                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
3106                 regs[5] = tmp;
3107                 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
3108
3109                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
3110                 regs[6] = tmp;
3111                 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
3112                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3113                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3114
3115                 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
3116                 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3117                 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
3118
3119                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3120                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3121                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3122                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3123         } else {
3124                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3125                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3126                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3127                 regs[2] = tmp;
3128                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
3129                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
3130                 regs[3] = tmp;
3131                 tmp |= 0x2000;
3132                 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
3133                 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
3134                 regs[4] = tmp;
3135                 tmp |= 0x2000;
3136                 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
3137                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3138                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3139                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3140                         tmp = 0x0180;
3141                 else
3142                         tmp = 0x0120;
3143                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3144                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3145         }
3146 }
3147
3148 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3149 static void b43_nphy_save_cal(struct b43_wldev *dev)
3150 {
3151         struct b43_phy_n *nphy = dev->phy.n;
3152
3153         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3154         u16 *txcal_radio_regs = NULL;
3155         struct b43_chanspec *iqcal_chanspec;
3156         u16 *table = NULL;
3157
3158         if (nphy->hang_avoid)
3159                 b43_nphy_stay_in_carrier_search(dev, 1);
3160
3161         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3162                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3163                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3164                 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3165                 table = nphy->cal_cache.txcal_coeffs_2G;
3166         } else {
3167                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3168                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3169                 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3170                 table = nphy->cal_cache.txcal_coeffs_5G;
3171         }
3172
3173         b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3174         /* TODO use some definitions */
3175         if (dev->phy.rev >= 3) {
3176                 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3177                 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3178                 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3179                 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3180                 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3181                 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3182                 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3183                 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3184         } else {
3185                 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3186                 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3187                 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3188                 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3189         }
3190         iqcal_chanspec->center_freq = dev->phy.channel_freq;
3191         iqcal_chanspec->channel_type = dev->phy.channel_type;
3192         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3193
3194         if (nphy->hang_avoid)
3195                 b43_nphy_stay_in_carrier_search(dev, 0);
3196 }
3197
3198 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3199 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3200 {
3201         struct b43_phy_n *nphy = dev->phy.n;
3202
3203         u16 coef[4];
3204         u16 *loft = NULL;
3205         u16 *table = NULL;
3206
3207         int i;
3208         u16 *txcal_radio_regs = NULL;
3209         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3210
3211         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3212                 if (!nphy->iqcal_chanspec_2G.center_freq)
3213                         return;
3214                 table = nphy->cal_cache.txcal_coeffs_2G;
3215                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3216         } else {
3217                 if (!nphy->iqcal_chanspec_5G.center_freq)
3218                         return;
3219                 table = nphy->cal_cache.txcal_coeffs_5G;
3220                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3221         }
3222
3223         b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3224
3225         for (i = 0; i < 4; i++) {
3226                 if (dev->phy.rev >= 3)
3227                         table[i] = coef[i];
3228                 else
3229                         coef[i] = 0;
3230         }
3231
3232         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3233         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3234         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3235
3236         if (dev->phy.rev < 2)
3237                 b43_nphy_tx_iq_workaround(dev);
3238
3239         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3240                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3241                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3242         } else {
3243                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3244                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3245         }
3246
3247         /* TODO use some definitions */
3248         if (dev->phy.rev >= 3) {
3249                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3250                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3251                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3252                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3253                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3254                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3255                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3256                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3257         } else {
3258                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3259                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3260                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3261                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3262         }
3263         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3264 }
3265
3266 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3267 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3268                                 struct nphy_txgains target,
3269                                 bool full, bool mphase)
3270 {
3271         struct b43_phy_n *nphy = dev->phy.n;
3272         int i;
3273         int error = 0;
3274         int freq;
3275         bool avoid = false;
3276         u8 length;
3277         u16 tmp, core, type, count, max, numb, last = 0, cmd;
3278         const u16 *table;
3279         bool phy6or5x;
3280
3281         u16 buffer[11];
3282         u16 diq_start = 0;
3283         u16 save[2];
3284         u16 gain[2];
3285         struct nphy_iqcal_params params[2];
3286         bool updated[2] = { };
3287
3288         b43_nphy_stay_in_carrier_search(dev, true);
3289
3290         if (dev->phy.rev >= 4) {
3291                 avoid = nphy->hang_avoid;
3292                 nphy->hang_avoid = false;
3293         }
3294
3295         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3296
3297         for (i = 0; i < 2; i++) {
3298                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3299                 gain[i] = params[i].cal_gain;
3300         }
3301
3302         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3303
3304         b43_nphy_tx_cal_radio_setup(dev);
3305         b43_nphy_tx_cal_phy_setup(dev);
3306
3307         phy6or5x = dev->phy.rev >= 6 ||
3308                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3309                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3310         if (phy6or5x) {
3311                 if (dev->phy.is_40mhz) {
3312                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3313                                         tbl_tx_iqlo_cal_loft_ladder_40);
3314                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3315                                         tbl_tx_iqlo_cal_iqimb_ladder_40);
3316                 } else {
3317                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3318                                         tbl_tx_iqlo_cal_loft_ladder_20);
3319                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3320                                         tbl_tx_iqlo_cal_iqimb_ladder_20);
3321                 }
3322         }
3323
3324         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3325
3326         if (!dev->phy.is_40mhz)
3327                 freq = 2500;
3328         else
3329                 freq = 5000;
3330
3331         if (nphy->mphase_cal_phase_id > 2)
3332                 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3333                                         0xFFFF, 0, true, false);
3334         else
3335                 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3336
3337         if (error == 0) {
3338                 if (nphy->mphase_cal_phase_id > 2) {
3339                         table = nphy->mphase_txcal_bestcoeffs;
3340                         length = 11;
3341                         if (dev->phy.rev < 3)
3342                                 length -= 2;
3343                 } else {
3344                         if (!full && nphy->txiqlocal_coeffsvalid) {
3345                                 table = nphy->txiqlocal_bestc;
3346                                 length = 11;
3347                                 if (dev->phy.rev < 3)
3348                                         length -= 2;
3349                         } else {
3350                                 full = true;
3351                                 if (dev->phy.rev >= 3) {
3352                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3353                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3354                                 } else {
3355                                         table = tbl_tx_iqlo_cal_startcoefs;
3356                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3357                                 }
3358                         }
3359                 }
3360
3361                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3362
3363                 if (full) {
3364                         if (dev->phy.rev >= 3)
3365                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3366                         else
3367                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3368                 } else {
3369                         if (dev->phy.rev >= 3)
3370                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3371                         else
3372                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3373                 }
3374
3375                 if (mphase) {
3376                         count = nphy->mphase_txcal_cmdidx;
3377                         numb = min(max,
3378                                 (u16)(count + nphy->mphase_txcal_numcmds));
3379                 } else {
3380                         count = 0;
3381                         numb = max;
3382                 }
3383
3384                 for (; count < numb; count++) {
3385                         if (full) {
3386                                 if (dev->phy.rev >= 3)
3387                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3388                                 else
3389                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3390                         } else {
3391                                 if (dev->phy.rev >= 3)
3392                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3393                                 else
3394                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3395                         }
3396
3397                         core = (cmd & 0x3000) >> 12;
3398                         type = (cmd & 0x0F00) >> 8;
3399
3400                         if (phy6or5x && updated[core] == 0) {
3401                                 b43_nphy_update_tx_cal_ladder(dev, core);
3402                                 updated[core] = true;
3403                         }
3404
3405                         tmp = (params[core].ncorr[type] << 8) | 0x66;
3406                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3407
3408                         if (type == 1 || type == 3 || type == 4) {
3409                                 buffer[0] = b43_ntab_read(dev,
3410                                                 B43_NTAB16(15, 69 + core));
3411                                 diq_start = buffer[0];
3412                                 buffer[0] = 0;
3413                                 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3414                                                 0);
3415                         }
3416
3417                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3418                         for (i = 0; i < 2000; i++) {
3419                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3420                                 if (tmp & 0xC000)
3421                                         break;
3422                                 udelay(10);
3423                         }
3424
3425                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3426                                                 buffer);
3427                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3428                                                 buffer);
3429
3430                         if (type == 1 || type == 3 || type == 4)
3431                                 buffer[0] = diq_start;
3432                 }
3433
3434                 if (mphase)
3435                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3436
3437                 last = (dev->phy.rev < 3) ? 6 : 7;
3438
3439                 if (!mphase || nphy->mphase_cal_phase_id == last) {
3440                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3441                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3442                         if (dev->phy.rev < 3) {
3443                                 buffer[0] = 0;
3444                                 buffer[1] = 0;
3445                                 buffer[2] = 0;
3446                                 buffer[3] = 0;
3447                         }
3448                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3449                                                 buffer);
3450                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3451                                                 buffer);
3452                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3453                                                 buffer);
3454                         b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3455                                                 buffer);
3456                         length = 11;
3457                         if (dev->phy.rev < 3)
3458                                 length -= 2;
3459                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3460                                                 nphy->txiqlocal_bestc);
3461                         nphy->txiqlocal_coeffsvalid = true;
3462                         nphy->txiqlocal_chanspec.center_freq =
3463                                                         dev->phy.channel_freq;
3464                         nphy->txiqlocal_chanspec.channel_type =
3465                                                         dev->phy.channel_type;
3466                 } else {
3467                         length = 11;
3468                         if (dev->phy.rev < 3)
3469                                 length -= 2;
3470                         b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3471                                                 nphy->mphase_txcal_bestcoeffs);
3472                 }
3473
3474                 b43_nphy_stop_playback(dev);
3475                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3476         }
3477
3478         b43_nphy_tx_cal_phy_cleanup(dev);
3479         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3480
3481         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3482                 b43_nphy_tx_iq_workaround(dev);
3483
3484         if (dev->phy.rev >= 4)
3485                 nphy->hang_avoid = avoid;
3486
3487         b43_nphy_stay_in_carrier_search(dev, false);
3488
3489         return error;
3490 }
3491
3492 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3493 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3494 {
3495         struct b43_phy_n *nphy = dev->phy.n;
3496         u8 i;
3497         u16 buffer[7];
3498         bool equal = true;
3499
3500         if (!nphy->txiqlocal_coeffsvalid ||
3501             nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3502             nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3503                 return;
3504
3505         b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3506         for (i = 0; i < 4; i++) {
3507                 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3508                         equal = false;
3509                         break;
3510                 }
3511         }
3512
3513         if (!equal) {
3514                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3515                                         nphy->txiqlocal_bestc);
3516                 for (i = 0; i < 4; i++)
3517                         buffer[i] = 0;
3518                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3519                                         buffer);
3520                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3521                                         &nphy->txiqlocal_bestc[5]);
3522                 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3523                                         &nphy->txiqlocal_bestc[5]);
3524         }
3525 }
3526
3527 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3528 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3529                         struct nphy_txgains target, u8 type, bool debug)
3530 {
3531         struct b43_phy_n *nphy = dev->phy.n;
3532         int i, j, index;
3533         u8 rfctl[2];
3534         u8 afectl_core;
3535         u16 tmp[6];
3536         u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3537         u32 real, imag;
3538         enum ieee80211_band band;
3539
3540         u8 use;
3541         u16 cur_hpf;
3542         u16 lna[3] = { 3, 3, 1 };
3543         u16 hpf1[3] = { 7, 2, 0 };
3544         u16 hpf2[3] = { 2, 0, 0 };
3545         u32 power[3] = { };
3546         u16 gain_save[2];
3547         u16 cal_gain[2];
3548         struct nphy_iqcal_params cal_params[2];
3549         struct nphy_iq_est est;
3550         int ret = 0;
3551         bool playtone = true;
3552         int desired = 13;
3553
3554         b43_nphy_stay_in_carrier_search(dev, 1);
3555
3556         if (dev->phy.rev < 2)
3557                 b43_nphy_reapply_tx_cal_coeffs(dev);
3558         b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3559         for (i = 0; i < 2; i++) {
3560                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
3561                 cal_gain[i] = cal_params[i].cal_gain;
3562         }
3563         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
3564
3565         for (i = 0; i < 2; i++) {
3566                 if (i == 0) {
3567                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
3568                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
3569                         afectl_core = B43_NPHY_AFECTL_C1;
3570                 } else {
3571                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
3572                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
3573                         afectl_core = B43_NPHY_AFECTL_C2;
3574                 }
3575
3576                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3577                 tmp[2] = b43_phy_read(dev, afectl_core);
3578                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3579                 tmp[4] = b43_phy_read(dev, rfctl[0]);
3580                 tmp[5] = b43_phy_read(dev, rfctl[1]);
3581
3582                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3583                                 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
3584                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3585                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3586                                 (1 - i));
3587                 b43_phy_set(dev, afectl_core, 0x0006);
3588                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
3589
3590                 band = b43_current_band(dev->wl);
3591
3592                 if (nphy->rxcalparams & 0xFF000000) {
3593                         if (band == IEEE80211_BAND_5GHZ)
3594                                 b43_phy_write(dev, rfctl[0], 0x140);
3595                         else
3596                                 b43_phy_write(dev, rfctl[0], 0x110);
3597                 } else {
3598                         if (band == IEEE80211_BAND_5GHZ)
3599                                 b43_phy_write(dev, rfctl[0], 0x180);
3600                         else
3601                                 b43_phy_write(dev, rfctl[0], 0x120);
3602                 }
3603
3604                 if (band == IEEE80211_BAND_5GHZ)
3605                         b43_phy_write(dev, rfctl[1], 0x148);
3606                 else
3607                         b43_phy_write(dev, rfctl[1], 0x114);
3608
3609                 if (nphy->rxcalparams & 0x10000) {
3610                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
3611                                         (i + 1));
3612                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
3613                                         (2 - i));
3614                 }
3615
3616                 for (j = 0; j < 4; j++) {
3617                         if (j < 3) {
3618                                 cur_lna = lna[j];
3619                                 cur_hpf1 = hpf1[j];
3620                                 cur_hpf2 = hpf2[j];
3621                         } else {
3622                                 if (power[1] > 10000) {
3623                                         use = 1;
3624                                         cur_hpf = cur_hpf1;
3625                                         index = 2;
3626                                 } else {
3627                                         if (power[0] > 10000) {
3628                                                 use = 1;
3629                                                 cur_hpf = cur_hpf1;
3630                                                 index = 1;
3631                                         } else {
3632                                                 index = 0;
3633                                                 use = 2;
3634                                                 cur_hpf = cur_hpf2;
3635                                         }
3636                                 }
3637                                 cur_lna = lna[index];
3638                                 cur_hpf1 = hpf1[index];
3639                                 cur_hpf2 = hpf2[index];
3640                                 cur_hpf += desired - hweight32(power[index]);
3641                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
3642                                 if (use == 1)
3643                                         cur_hpf1 = cur_hpf;
3644                                 else
3645                                         cur_hpf2 = cur_hpf;
3646                         }
3647
3648                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3649                                         (cur_lna << 2));
3650                         b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3651                                                                         false);
3652                         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3653                         b43_nphy_stop_playback(dev);
3654
3655                         if (playtone) {
3656                                 ret = b43_nphy_tx_tone(dev, 4000,
3657                                                 (nphy->rxcalparams & 0xFFFF),
3658                                                 false, false);
3659                                 playtone = false;
3660                         } else {
3661                                 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3662                                                         false, false);
3663                         }
3664
3665                         if (ret == 0) {
3666                                 if (j < 3) {
3667                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3668                                                                         false);
3669                                         if (i == 0) {
3670                                                 real = est.i0_pwr;
3671                                                 imag = est.q0_pwr;
3672                                         } else {
3673                                                 real = est.i1_pwr;
3674                                                 imag = est.q1_pwr;
3675                                         }
3676                                         power[i] = ((real + imag) / 1024) + 1;
3677                                 } else {
3678                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3679                                 }
3680                                 b43_nphy_stop_playback(dev);
3681                         }
3682
3683                         if (ret != 0)
3684                                 break;
3685                 }
3686
3687                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3688                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3689                 b43_phy_write(dev, rfctl[1], tmp[5]);
3690                 b43_phy_write(dev, rfctl[0], tmp[4]);
3691                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3692                 b43_phy_write(dev, afectl_core, tmp[2]);
3693                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3694
3695                 if (ret != 0)
3696                         break;
3697         }
3698
3699         b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3700         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3701         b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3702
3703         b43_nphy_stay_in_carrier_search(dev, 0);
3704
3705         return ret;
3706 }
3707
3708 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3709                         struct nphy_txgains target, u8 type, bool debug)
3710 {
3711         return -1;
3712 }
3713
3714 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3715 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3716                         struct nphy_txgains target, u8 type, bool debug)
3717 {
3718         if (dev->phy.rev >= 3)
3719                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3720         else
3721                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3722 }
3723
3724 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3725 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3726 {
3727         struct b43_phy *phy = &dev->phy;
3728         struct b43_phy_n *nphy = phy->n;
3729         /* u16 buf[16]; it's rev3+ */
3730
3731         nphy->phyrxchain = mask;
3732
3733         if (0 /* FIXME clk */)
3734                 return;
3735
3736         b43_mac_suspend(dev);
3737
3738         if (nphy->hang_avoid)
3739                 b43_nphy_stay_in_carrier_search(dev, true);
3740
3741         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3742                         (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3743
3744         if ((mask & 0x3) != 0x3) {
3745                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3746                 if (dev->phy.rev >= 3) {
3747                         /* TODO */
3748                 }
3749         } else {
3750                 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3751                 if (dev->phy.rev >= 3) {
3752                         /* TODO */
3753                 }
3754         }
3755
3756         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3757
3758         if (nphy->hang_avoid)
3759                 b43_nphy_stay_in_carrier_search(dev, false);
3760
3761         b43_mac_enable(dev);
3762 }
3763
3764 /**************************************************
3765  * N-PHY init
3766  **************************************************/
3767
3768 /*
3769  * Upload the N-PHY tables.
3770  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
3771  */
3772 static void b43_nphy_tables_init(struct b43_wldev *dev)
3773 {
3774         if (dev->phy.rev < 3)
3775                 b43_nphy_rev0_1_2_tables_init(dev);
3776         else
3777                 b43_nphy_rev3plus_tables_init(dev);
3778 }
3779
3780 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
3781 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
3782 {
3783         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
3784
3785         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
3786         if (preamble == 1)
3787                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
3788         else
3789                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
3790
3791         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
3792 }
3793
3794 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
3795 static void b43_nphy_bphy_init(struct b43_wldev *dev)
3796 {
3797         unsigned int i;
3798         u16 val;
3799
3800         val = 0x1E1F;
3801         for (i = 0; i < 16; i++) {
3802                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
3803                 val -= 0x202;
3804         }
3805         val = 0x3E3F;
3806         for (i = 0; i < 16; i++) {
3807                 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
3808                 val -= 0x202;
3809         }
3810         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
3811 }
3812
3813 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
3814 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
3815 {
3816         if (dev->phy.rev >= 3) {
3817                 if (!init)
3818                         return;
3819                 if (0 /* FIXME */) {
3820                         b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
3821                         b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
3822                         b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
3823                         b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
3824                 }
3825         } else {
3826                 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
3827                 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
3828
3829                 switch (dev->dev->bus_type) {
3830 #ifdef CONFIG_B43_BCMA
3831                 case B43_BUS_BCMA:
3832                         bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
3833                                                  0xFC00, 0xFC00);
3834                         break;
3835 #endif
3836 #ifdef CONFIG_B43_SSB
3837                 case B43_BUS_SSB:
3838                         ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
3839                                                 0xFC00, 0xFC00);
3840                         break;
3841 #endif
3842                 }
3843
3844                 b43_write32(dev, B43_MMIO_MACCTL,
3845                         b43_read32(dev, B43_MMIO_MACCTL) &
3846                         ~B43_MACCTL_GPOUTSMSK);
3847                 b43_write16(dev, B43_MMIO_GPIO_MASK,
3848                         b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
3849                 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
3850                         b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
3851
3852                 if (init) {
3853                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
3854                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
3855                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
3856                         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
3857                 }
3858         }
3859 }
3860
3861 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
3862 int b43_phy_initn(struct b43_wldev *dev)
3863 {
3864         struct ssb_sprom *sprom = dev->dev->bus_sprom;
3865         struct b43_phy *phy = &dev->phy;
3866         struct b43_phy_n *nphy = phy->n;
3867         u8 tx_pwr_state;
3868         struct nphy_txgains target;
3869         u16 tmp;
3870         enum ieee80211_band tmp2;
3871         bool do_rssi_cal;
3872
3873         u16 clip[2];
3874         bool do_cal = false;
3875
3876         if ((dev->phy.rev >= 3) &&
3877            (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3878            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3879                 switch (dev->dev->bus_type) {
3880 #ifdef CONFIG_B43_BCMA
3881                 case B43_BUS_BCMA:
3882                         bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3883                                       BCMA_CC_CHIPCTL, 0x40);
3884                         break;
3885 #endif
3886 #ifdef CONFIG_B43_SSB
3887                 case B43_BUS_SSB:
3888                         chipco_set32(&dev->dev->sdev->bus->chipco,
3889                                      SSB_CHIPCO_CHIPCTL, 0x40);
3890                         break;
3891 #endif
3892                 }
3893         }
3894         nphy->deaf_count = 0;
3895         b43_nphy_tables_init(dev);
3896         nphy->crsminpwr_adjusted = false;
3897         nphy->noisevars_adjusted = false;
3898
3899         /* Clear all overrides */
3900         if (dev->phy.rev >= 3) {
3901                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3902                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3903                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3904                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3905         } else {
3906                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3907         }
3908         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3909         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3910         if (dev->phy.rev < 6) {
3911                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3912                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3913         }
3914         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3915                      ~(B43_NPHY_RFSEQMODE_CAOVER |
3916                        B43_NPHY_RFSEQMODE_TROVER));
3917         if (dev->phy.rev >= 3)
3918                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3919         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3920
3921         if (dev->phy.rev <= 2) {
3922                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3923                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3924                                 ~B43_NPHY_BPHY_CTL3_SCALE,
3925                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3926         }
3927         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3928         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3929
3930         if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
3931             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3932              dev->dev->board_type == 0x8B))
3933                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3934         else
3935                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3936         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3937         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3938         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3939
3940         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3941         b43_nphy_update_txrx_chain(dev);
3942
3943         if (phy->rev < 2) {
3944                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3945                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3946         }
3947
3948         tmp2 = b43_current_band(dev->wl);
3949         if (b43_nphy_ipa(dev)) {
3950                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3951                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3952                                 nphy->papd_epsilon_offset[0] << 7);
3953                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3954                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3955                                 nphy->papd_epsilon_offset[1] << 7);
3956                 b43_nphy_int_pa_set_tx_dig_filters(dev);
3957         } else if (phy->rev >= 5) {
3958                 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3959         }
3960
3961         b43_nphy_workarounds(dev);
3962
3963         /* Reset CCA, in init code it differs a little from standard way */
3964         b43_phy_force_clock(dev, 1);
3965         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3966         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3967         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3968         b43_phy_force_clock(dev, 0);
3969
3970         b43_mac_phy_clock_set(dev, true);
3971
3972         b43_nphy_pa_override(dev, false);
3973         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3974         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3975         b43_nphy_pa_override(dev, true);
3976
3977         b43_nphy_classifier(dev, 0, 0);
3978         b43_nphy_read_clip_detection(dev, clip);
3979         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3980                 b43_nphy_bphy_init(dev);
3981
3982         tx_pwr_state = nphy->txpwrctrl;
3983         b43_nphy_tx_power_ctrl(dev, false);
3984         b43_nphy_tx_power_fix(dev);
3985         /* TODO N PHY TX Power Control Idle TSSI */
3986         /* TODO N PHY TX Power Control Setup */
3987         b43_nphy_tx_gain_table_upload(dev);
3988
3989         if (nphy->phyrxchain != 3)
3990                 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3991         if (nphy->mphase_cal_phase_id > 0)
3992                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3993
3994         do_rssi_cal = false;
3995         if (phy->rev >= 3) {
3996                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3997                         do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3998                 else
3999                         do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
4000
4001                 if (do_rssi_cal)
4002                         b43_nphy_rssi_cal(dev);
4003                 else
4004                         b43_nphy_restore_rssi_cal(dev);
4005         } else {
4006                 b43_nphy_rssi_cal(dev);
4007         }
4008
4009         if (!((nphy->measure_hold & 0x6) != 0)) {
4010                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4011                         do_cal = !nphy->iqcal_chanspec_2G.center_freq;
4012                 else
4013                         do_cal = !nphy->iqcal_chanspec_5G.center_freq;
4014
4015                 if (nphy->mute)
4016                         do_cal = false;
4017
4018                 if (do_cal) {
4019                         target = b43_nphy_get_tx_gains(dev);
4020
4021                         if (nphy->antsel_type == 2)
4022                                 b43_nphy_superswitch_init(dev, true);
4023                         if (nphy->perical != 2) {
4024                                 b43_nphy_rssi_cal(dev);
4025                                 if (phy->rev >= 3) {
4026                                         nphy->cal_orig_pwr_idx[0] =
4027                                             nphy->txpwrindex[0].index_internal;
4028                                         nphy->cal_orig_pwr_idx[1] =
4029                                             nphy->txpwrindex[1].index_internal;
4030                                         /* TODO N PHY Pre Calibrate TX Gain */
4031                                         target = b43_nphy_get_tx_gains(dev);
4032                                 }
4033                                 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
4034                                         if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
4035                                                 b43_nphy_save_cal(dev);
4036                         } else if (nphy->mphase_cal_phase_id == 0)
4037                                 ;/* N PHY Periodic Calibration with arg 3 */
4038                 } else {
4039                         b43_nphy_restore_cal(dev);
4040                 }
4041         }
4042
4043         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
4044         b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
4045         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
4046         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
4047         if (phy->rev >= 3 && phy->rev <= 6)
4048                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
4049         b43_nphy_tx_lp_fbw(dev);
4050         if (phy->rev >= 3)
4051                 b43_nphy_spur_workaround(dev);
4052
4053         return 0;
4054 }
4055
4056 /**************************************************
4057  * Channel switching ops.
4058  **************************************************/
4059
4060 static void b43_chantab_phy_upload(struct b43_wldev *dev,
4061                                    const struct b43_phy_n_sfo_cfg *e)
4062 {
4063         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
4064         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
4065         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
4066         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
4067         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
4068         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
4069 }
4070
4071 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
4072 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
4073 {
4074         struct bcma_drv_cc __maybe_unused *cc;
4075         u32 __maybe_unused pmu_ctl;
4076
4077         switch (dev->dev->bus_type) {
4078 #ifdef CONFIG_B43_BCMA
4079         case B43_BUS_BCMA:
4080                 cc = &dev->dev->bdev->bus->drv_cc;
4081                 if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
4082                         if (avoid) {
4083                                 bcma_chipco_pll_write(cc, 0x0, 0x11500010);
4084                                 bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
4085                                 bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
4086                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4087                                 bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
4088                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4089                         } else {
4090                                 bcma_chipco_pll_write(cc, 0x0, 0x11100010);
4091                                 bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
4092                                 bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
4093                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4094                                 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4095                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4096                         }
4097                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4098                 } else if (dev->dev->chip_id == 0x4716) {
4099                         if (avoid) {
4100                                 bcma_chipco_pll_write(cc, 0x0, 0x11500060);
4101                                 bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
4102                                 bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
4103                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4104                                 bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
4105                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4106                         } else {
4107                                 bcma_chipco_pll_write(cc, 0x0, 0x11100060);
4108                                 bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
4109                                 bcma_chipco_pll_write(cc, 0x2, 0x03000000);
4110                                 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4111                                 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4112                                 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4113                         }
4114                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD |
4115                                   BCMA_CC_PMU_CTL_NOILPONW;
4116                 } else if (dev->dev->chip_id == 0x4322 ||
4117                            dev->dev->chip_id == 0x4340 ||
4118                            dev->dev->chip_id == 0x4341) {
4119                         bcma_chipco_pll_write(cc, 0x0, 0x11100070);
4120                         bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
4121                         bcma_chipco_pll_write(cc, 0x5, 0x88888854);
4122                         if (avoid)
4123                                 bcma_chipco_pll_write(cc, 0x2, 0x05201828);
4124                         else
4125                                 bcma_chipco_pll_write(cc, 0x2, 0x05001828);
4126                         pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4127                 } else {
4128                         return;
4129                 }
4130                 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
4131                 break;
4132 #endif
4133 #ifdef CONFIG_B43_SSB
4134         case B43_BUS_SSB:
4135                 /* FIXME */
4136                 break;
4137 #endif
4138         }
4139 }
4140
4141 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
4142 static void b43_nphy_channel_setup(struct b43_wldev *dev,
4143                                 const struct b43_phy_n_sfo_cfg *e,
4144                                 struct ieee80211_channel *new_channel)
4145 {
4146         struct b43_phy *phy = &dev->phy;
4147         struct b43_phy_n *nphy = dev->phy.n;
4148         int ch = new_channel->hw_value;
4149
4150         u16 old_band_5ghz;
4151         u32 tmp32;
4152
4153         old_band_5ghz =
4154                 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
4155         if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
4156                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4157                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4158                 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
4159                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4160                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
4161         } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
4162                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
4163                 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4164                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4165                 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
4166                 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4167         }
4168
4169         b43_chantab_phy_upload(dev, e);
4170
4171         if (new_channel->hw_value == 14) {
4172                 b43_nphy_classifier(dev, 2, 0);
4173                 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
4174         } else {
4175                 b43_nphy_classifier(dev, 2, 2);
4176                 if (new_channel->band == IEEE80211_BAND_2GHZ)
4177                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
4178         }
4179
4180         if (!nphy->txpwrctrl)
4181                 b43_nphy_tx_power_fix(dev);
4182
4183         if (dev->phy.rev < 3)
4184                 b43_nphy_adjust_lna_gain_table(dev);
4185
4186         b43_nphy_tx_lp_fbw(dev);
4187
4188         if (dev->phy.rev >= 3 &&
4189             dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
4190                 bool avoid = false;
4191                 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
4192                         avoid = true;
4193                 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
4194                         if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
4195                                 avoid = true;
4196                 } else { /* 40MHz */
4197                         if (nphy->aband_spurwar_en &&
4198                             (ch == 38 || ch == 102 || ch == 118))
4199                                 avoid = dev->dev->chip_id == 0x4716;
4200                 }
4201
4202                 b43_nphy_pmu_spur_avoid(dev, avoid);
4203
4204                 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
4205                     dev->dev->chip_id == 43225) {
4206                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
4207                                     avoid ? 0x5341 : 0x8889);
4208                         b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
4209                 }
4210
4211                 if (dev->phy.rev == 3 || dev->phy.rev == 4)
4212                         ; /* TODO: reset PLL */
4213
4214                 if (avoid)
4215                         b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
4216                 else
4217                         b43_phy_mask(dev, B43_NPHY_BBCFG,
4218                                      ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4219
4220                 b43_nphy_reset_cca(dev);
4221
4222                 /* wl sets useless phy_isspuravoid here */
4223         }
4224
4225         b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
4226
4227         if (phy->rev >= 3)
4228                 b43_nphy_spur_workaround(dev);
4229 }
4230
4231 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
4232 static int b43_nphy_set_channel(struct b43_wldev *dev,
4233                                 struct ieee80211_channel *channel,
4234                                 enum nl80211_channel_type channel_type)
4235 {
4236         struct b43_phy *phy = &dev->phy;
4237
4238         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
4239         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
4240
4241         u8 tmp;
4242
4243         if (dev->phy.rev >= 3) {
4244                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
4245                                                         channel->center_freq);
4246                 if (!tabent_r3)
4247                         return -ESRCH;
4248         } else {
4249                 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
4250                                                         channel->hw_value);
4251                 if (!tabent_r2)
4252                         return -ESRCH;
4253         }
4254
4255         /* Channel is set later in common code, but we need to set it on our
4256            own to let this function's subcalls work properly. */
4257         phy->channel = channel->hw_value;
4258         phy->channel_freq = channel->center_freq;
4259
4260         if (b43_channel_type_is_40mhz(phy->channel_type) !=
4261                 b43_channel_type_is_40mhz(channel_type))
4262                 ; /* TODO: BMAC BW Set (channel_type) */
4263
4264         if (channel_type == NL80211_CHAN_HT40PLUS)
4265                 b43_phy_set(dev, B43_NPHY_RXCTL,
4266                                 B43_NPHY_RXCTL_BSELU20);
4267         else if (channel_type == NL80211_CHAN_HT40MINUS)
4268                 b43_phy_mask(dev, B43_NPHY_RXCTL,
4269                                 ~B43_NPHY_RXCTL_BSELU20);
4270
4271         if (dev->phy.rev >= 3) {
4272                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
4273                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
4274                 b43_radio_2056_setup(dev, tabent_r3);
4275                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
4276         } else {
4277                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
4278                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
4279                 b43_radio_2055_setup(dev, tabent_r2);
4280                 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
4281         }
4282
4283         return 0;
4284 }
4285
4286 /**************************************************
4287  * Basic PHY ops.
4288  **************************************************/
4289
4290 static int b43_nphy_op_allocate(struct b43_wldev *dev)
4291 {
4292         struct b43_phy_n *nphy;
4293
4294         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
4295         if (!nphy)
4296                 return -ENOMEM;
4297         dev->phy.n = nphy;
4298
4299         return 0;
4300 }
4301
4302 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
4303 {
4304         struct b43_phy *phy = &dev->phy;
4305         struct b43_phy_n *nphy = phy->n;
4306         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4307
4308         memset(nphy, 0, sizeof(*nphy));
4309
4310         nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
4311         nphy->spur_avoid = (phy->rev >= 3) ?
4312                                 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
4313         nphy->gain_boost = true; /* this way we follow wl, assume it is true */
4314         nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
4315         nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
4316         nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
4317         /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
4318          * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
4319         nphy->tx_pwr_idx[0] = 128;
4320         nphy->tx_pwr_idx[1] = 128;
4321
4322         /* Hardware TX power control and 5GHz power gain */
4323         nphy->txpwrctrl = false;
4324         nphy->pwg_gain_5ghz = false;
4325         if (dev->phy.rev >= 3 ||
4326             (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4327              (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
4328                 nphy->txpwrctrl = true;
4329                 nphy->pwg_gain_5ghz = true;
4330         } else if (sprom->revision >= 4) {
4331                 if (dev->phy.rev >= 2 &&
4332                     (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
4333                         nphy->txpwrctrl = true;
4334 #ifdef CONFIG_B43_SSB
4335                         if (dev->dev->bus_type == B43_BUS_SSB &&
4336                             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
4337                                 struct pci_dev *pdev =
4338                                         dev->dev->sdev->bus->host_pci;
4339                                 if (pdev->device == 0x4328 ||
4340                                     pdev->device == 0x432a)
4341                                         nphy->pwg_gain_5ghz = true;
4342                         }
4343 #endif
4344                 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
4345                         nphy->pwg_gain_5ghz = true;
4346                 }
4347         }
4348
4349         if (dev->phy.rev >= 3) {
4350                 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
4351                 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
4352         }
4353 }
4354
4355 static void b43_nphy_op_free(struct b43_wldev *dev)
4356 {
4357         struct b43_phy *phy = &dev->phy;
4358         struct b43_phy_n *nphy = phy->n;
4359
4360         kfree(nphy);
4361         phy->n = NULL;
4362 }
4363
4364 static int b43_nphy_op_init(struct b43_wldev *dev)
4365 {
4366         return b43_phy_initn(dev);
4367 }
4368
4369 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4370 {
4371 #if B43_DEBUG
4372         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4373                 /* OFDM registers are onnly available on A/G-PHYs */
4374                 b43err(dev->wl, "Invalid OFDM PHY access at "
4375                        "0x%04X on N-PHY\n", offset);
4376                 dump_stack();
4377         }
4378         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4379                 /* Ext-G registers are only available on G-PHYs */
4380                 b43err(dev->wl, "Invalid EXT-G PHY access at "
4381                        "0x%04X on N-PHY\n", offset);
4382                 dump_stack();
4383         }
4384 #endif /* B43_DEBUG */
4385 }
4386
4387 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4388 {
4389         check_phyreg(dev, reg);
4390         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4391         return b43_read16(dev, B43_MMIO_PHY_DATA);
4392 }
4393
4394 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4395 {
4396         check_phyreg(dev, reg);
4397         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4398         b43_write16(dev, B43_MMIO_PHY_DATA, value);
4399 }
4400
4401 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4402                                  u16 set)
4403 {
4404         check_phyreg(dev, reg);
4405         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4406         b43_write16(dev, B43_MMIO_PHY_DATA,
4407                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
4408 }
4409
4410 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4411 {
4412         /* Register 1 is a 32-bit register. */
4413         B43_WARN_ON(reg == 1);
4414         /* N-PHY needs 0x100 for read access */
4415         reg |= 0x100;
4416
4417         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4418         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4419 }
4420
4421 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4422 {
4423         /* Register 1 is a 32-bit register. */
4424         B43_WARN_ON(reg == 1);
4425
4426         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4427         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4428 }
4429
4430 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
4431 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4432                                         bool blocked)
4433 {
4434         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4435                 b43err(dev->wl, "MAC not suspended\n");
4436
4437         if (blocked) {
4438                 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4439                                 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4440                 if (dev->phy.rev >= 3) {
4441                         b43_radio_mask(dev, 0x09, ~0x2);
4442
4443                         b43_radio_write(dev, 0x204D, 0);
4444                         b43_radio_write(dev, 0x2053, 0);
4445                         b43_radio_write(dev, 0x2058, 0);
4446                         b43_radio_write(dev, 0x205E, 0);
4447                         b43_radio_mask(dev, 0x2062, ~0xF0);
4448                         b43_radio_write(dev, 0x2064, 0);
4449
4450                         b43_radio_write(dev, 0x304D, 0);
4451                         b43_radio_write(dev, 0x3053, 0);
4452                         b43_radio_write(dev, 0x3058, 0);
4453                         b43_radio_write(dev, 0x305E, 0);
4454                         b43_radio_mask(dev, 0x3062, ~0xF0);
4455                         b43_radio_write(dev, 0x3064, 0);
4456                 }
4457         } else {
4458                 if (dev->phy.rev >= 3) {
4459                         b43_radio_init2056(dev);
4460                         b43_switch_channel(dev, dev->phy.channel);
4461                 } else {
4462                         b43_radio_init2055(dev);
4463                 }
4464         }
4465 }
4466
4467 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4468 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4469 {
4470         u16 override = on ? 0x0 : 0x7FFF;
4471         u16 core = on ? 0xD : 0x00FD;
4472
4473         if (dev->phy.rev >= 3) {
4474                 if (on) {
4475                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4476                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4477                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4478                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4479                 } else {
4480                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4481                         b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4482                         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4483                         b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4484                 }
4485         } else {
4486                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4487         }
4488 }
4489
4490 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4491                                       unsigned int new_channel)
4492 {
4493         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4494         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4495
4496         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4497                 if ((new_channel < 1) || (new_channel > 14))
4498                         return -EINVAL;
4499         } else {
4500                 if (new_channel > 200)
4501                         return -EINVAL;
4502         }
4503
4504         return b43_nphy_set_channel(dev, channel, channel_type);
4505 }
4506
4507 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4508 {
4509         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4510                 return 1;
4511         return 36;
4512 }
4513
4514 const struct b43_phy_operations b43_phyops_n = {
4515         .allocate               = b43_nphy_op_allocate,
4516         .free                   = b43_nphy_op_free,
4517         .prepare_structs        = b43_nphy_op_prepare_structs,
4518         .init                   = b43_nphy_op_init,
4519         .phy_read               = b43_nphy_op_read,
4520         .phy_write              = b43_nphy_op_write,
4521         .phy_maskset            = b43_nphy_op_maskset,
4522         .radio_read             = b43_nphy_op_radio_read,
4523         .radio_write            = b43_nphy_op_radio_write,
4524         .software_rfkill        = b43_nphy_op_software_rfkill,
4525         .switch_analog          = b43_nphy_op_switch_analog,
4526         .switch_channel         = b43_nphy_op_switch_channel,
4527         .get_default_chan       = b43_nphy_op_get_default_chan,
4528         .recalc_txpower         = b43_nphy_op_recalc_txpower,
4529         .adjust_txpower         = b43_nphy_op_adjust_txpower,
4530 };