b43: LP-PHY: Implement reading band SPROM
[linux-2.6.git] / drivers / net / wireless / b43 / phy_lp.c
1 /*
2
3   Broadcom B43 wireless driver
4   IEEE 802.11g LP-PHY driver
5
6   Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
7
8   This program is free software; you can redistribute it and/or modify
9   it under the terms of the GNU General Public License as published by
10   the Free Software Foundation; either version 2 of the License, or
11   (at your option) any later version.
12
13   This program is distributed in the hope that it will be useful,
14   but WITHOUT ANY WARRANTY; without even the implied warranty of
15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16   GNU General Public License for more details.
17
18   You should have received a copy of the GNU General Public License
19   along with this program; see the file COPYING.  If not, write to
20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21   Boston, MA 02110-1301, USA.
22
23 */
24
25 #include "b43.h"
26 #include "main.h"
27 #include "phy_lp.h"
28 #include "phy_common.h"
29 #include "tables_lpphy.h"
30
31
32 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
33 {
34         struct b43_phy_lp *lpphy;
35
36         lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
37         if (!lpphy)
38                 return -ENOMEM;
39         dev->phy.lp = lpphy;
40
41         return 0;
42 }
43
44 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
45 {
46         struct b43_phy *phy = &dev->phy;
47         struct b43_phy_lp *lpphy = phy->lp;
48
49         memset(lpphy, 0, sizeof(*lpphy));
50
51         //TODO
52 }
53
54 static void b43_lpphy_op_free(struct b43_wldev *dev)
55 {
56         struct b43_phy_lp *lpphy = dev->phy.lp;
57
58         kfree(lpphy);
59         dev->phy.lp = NULL;
60 }
61
62 static void lpphy_read_band_sprom(struct b43_wldev *dev)
63 {
64         struct b43_phy_lp *lpphy = dev->phy.lp;
65         struct ssb_bus *bus = dev->dev->bus;
66         u16 cckpo, maxpwr;
67         u32 ofdmpo;
68         int i;
69
70         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
71                 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
72                 lpphy->bx_arch = bus->sprom.bxa2g;
73                 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
74                 lpphy->rssi_vf = bus->sprom.rssismf2g;
75                 lpphy->rssi_vc = bus->sprom.rssismc2g;
76                 lpphy->rssi_gs = bus->sprom.rssisav2g;
77                 lpphy->txpa[0] = bus->sprom.pa0b0;
78                 lpphy->txpa[1] = bus->sprom.pa0b1;
79                 lpphy->txpa[2] = bus->sprom.pa0b2;
80                 maxpwr = bus->sprom.maxpwr_bg;
81                 lpphy->max_tx_pwr_med_band = maxpwr;
82                 cckpo = bus->sprom.cck2gpo;
83                 ofdmpo = bus->sprom.ofdm2gpo;
84                 if (cckpo) {
85                         for (i = 0; i < 4; i++) {
86                                 lpphy->tx_max_rate[i] =
87                                         maxpwr - (ofdmpo & 0xF) * 2;
88                                 ofdmpo >>= 4;
89                         }
90                         ofdmpo = bus->sprom.ofdm2gpo;
91                         for (i = 4; i < 15; i++) {
92                                 lpphy->tx_max_rate[i] =
93                                         maxpwr - (ofdmpo & 0xF) * 2;
94                                 ofdmpo >>= 4;
95                         }
96                 } else {
97                         ofdmpo &= 0xFF;
98                         for (i = 0; i < 4; i++)
99                                 lpphy->tx_max_rate[i] = maxpwr;
100                         for (i = 4; i < 15; i++)
101                                 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
102                 }
103         } else { /* 5GHz */
104                 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
105                 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
106                 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
107                 lpphy->bx_arch = bus->sprom.bxa5g;
108                 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
109                 lpphy->rssi_vf = bus->sprom.rssismf5g;
110                 lpphy->rssi_vc = bus->sprom.rssismc5g;
111                 lpphy->rssi_gs = bus->sprom.rssisav5g;
112                 lpphy->txpa[0] = bus->sprom.pa1b0;
113                 lpphy->txpa[1] = bus->sprom.pa1b1;
114                 lpphy->txpa[2] = bus->sprom.pa1b2;
115                 lpphy->txpal[0] = bus->sprom.pa1lob0;
116                 lpphy->txpal[1] = bus->sprom.pa1lob1;
117                 lpphy->txpal[2] = bus->sprom.pa1lob2;
118                 lpphy->txpah[0] = bus->sprom.pa1hib0;
119                 lpphy->txpah[1] = bus->sprom.pa1hib1;
120                 lpphy->txpah[2] = bus->sprom.pa1hib2;
121                 maxpwr = bus->sprom.maxpwr_al;
122                 ofdmpo = bus->sprom.ofdm5glpo;
123                 lpphy->max_tx_pwr_low_band = maxpwr;
124                 for (i = 4; i < 12; i++) {
125                         lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
126                         ofdmpo >>= 4;
127                 }
128                 maxpwr = bus->sprom.maxpwr_a;
129                 ofdmpo = bus->sprom.ofdm5gpo;
130                 lpphy->max_tx_pwr_med_band = maxpwr;
131                 for (i = 4; i < 12; i++) {
132                         lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
133                         ofdmpo >>= 4;
134                 }
135                 maxpwr = bus->sprom.maxpwr_ah;
136                 ofdmpo = bus->sprom.ofdm5ghpo;
137                 lpphy->max_tx_pwr_hi_band = maxpwr;
138                 for (i = 4; i < 12; i++) {
139                         lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
140                         ofdmpo >>= 4;
141                 }
142         }
143 }
144
145 static void lpphy_adjust_gain_table(struct b43_wldev *dev)
146 {
147         struct b43_phy_lp *lpphy = dev->phy.lp;
148         u32 freq = dev->wl->hw->conf.channel->center_freq;
149         u16 temp[3];
150         u16 isolation;
151
152         B43_WARN_ON(dev->phy.rev >= 2);
153
154         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
155                 isolation = lpphy->tx_isolation_med_band;
156         else if (freq <= 5320)
157                 isolation = lpphy->tx_isolation_low_band;
158         else if (freq <= 5700)
159                 isolation = lpphy->tx_isolation_med_band;
160         else
161                 isolation = lpphy->tx_isolation_hi_band;
162
163         temp[0] = ((isolation - 26) / 12) << 12;
164         temp[1] = temp[0] + 0x1000;
165         temp[2] = temp[0] + 0x2000;
166
167         b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
168         b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
169 }
170
171 static void lpphy_table_init(struct b43_wldev *dev)
172 {
173         if (dev->phy.rev < 2)
174                 lpphy_rev0_1_table_init(dev);
175         else
176                 lpphy_rev2plus_table_init(dev);
177
178         lpphy_init_tx_gain_table(dev);
179
180         if (dev->phy.rev < 2)
181                 lpphy_adjust_gain_table(dev);
182 }
183
184 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
185 {
186         struct ssb_bus *bus = dev->dev->bus;
187         u16 tmp, tmp2;
188
189         if (dev->phy.rev == 1 &&
190            (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
191                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
192                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
193                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
194                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
195                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
196                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
197                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
198                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
199                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
200                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
201                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
202                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
203                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
204                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
205                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
206                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
207         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
208                   (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
209                   (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
210                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
211                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
212                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
213                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
214                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
215                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
216                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
217                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
218         } else if (dev->phy.rev == 1 ||
219                   (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
220                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
221                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
222                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
223                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
224                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
225                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
226                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
227                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
228         } else {
229                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
230                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
231                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
232                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
233                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
234                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
235                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
236                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
237         }
238         if (dev->phy.rev == 1) {
239                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
240                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
241                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
242                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
243         }
244         if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
245             (bus->chip_id == 0x5354) &&
246             (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
247                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
248                 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
249                 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
250                 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
251         }
252         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
253                 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
254                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
255                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
256                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
257                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
258                 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
259                 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
260                 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
261         } else { /* 5GHz */
262                 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
263                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
264         }
265         if (dev->phy.rev == 1) {
266                 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
267                 tmp2 = (tmp & 0x03E0) >> 5;
268                 tmp2 |= tmp << 5;
269                 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
270                 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
271                 tmp2 = (tmp & 0x1F00) >> 8;
272                 tmp2 |= tmp << 5;
273                 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
274                 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
275                 tmp2 = tmp & 0x00FF;
276                 tmp2 |= tmp << 8;
277                 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
278         }
279 }
280
281 static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
282 {
283         static const u16 addr[] = {
284                 B43_PHY_OFDM(0xC1),
285                 B43_PHY_OFDM(0xC2),
286                 B43_PHY_OFDM(0xC3),
287                 B43_PHY_OFDM(0xC4),
288                 B43_PHY_OFDM(0xC5),
289                 B43_PHY_OFDM(0xC6),
290                 B43_PHY_OFDM(0xC7),
291                 B43_PHY_OFDM(0xC8),
292                 B43_PHY_OFDM(0xCF),
293         };
294
295         static const u16 coefs[] = {
296                 0xDE5E, 0xE832, 0xE331, 0x4D26,
297                 0x0026, 0x1420, 0x0020, 0xFE08,
298                 0x0008,
299         };
300
301         struct b43_phy_lp *lpphy = dev->phy.lp;
302         int i;
303
304         for (i = 0; i < ARRAY_SIZE(addr); i++) {
305                 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
306                 b43_phy_write(dev, addr[i], coefs[i]);
307         }
308 }
309
310 static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
311 {
312         static const u16 addr[] = {
313                 B43_PHY_OFDM(0xC1),
314                 B43_PHY_OFDM(0xC2),
315                 B43_PHY_OFDM(0xC3),
316                 B43_PHY_OFDM(0xC4),
317                 B43_PHY_OFDM(0xC5),
318                 B43_PHY_OFDM(0xC6),
319                 B43_PHY_OFDM(0xC7),
320                 B43_PHY_OFDM(0xC8),
321                 B43_PHY_OFDM(0xCF),
322         };
323
324         struct b43_phy_lp *lpphy = dev->phy.lp;
325         int i;
326
327         for (i = 0; i < ARRAY_SIZE(addr); i++)
328                 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
329 }
330
331 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
332 {
333         struct ssb_bus *bus = dev->dev->bus;
334         struct b43_phy_lp *lpphy = dev->phy.lp;
335
336         b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
337         b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
338         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
339         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
340         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
341         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
342         b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
343         b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
344         b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
345         b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
346         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
347         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
348         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
349         b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
350         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
351         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
352         b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
353         if (bus->boardinfo.rev >= 0x18) {
354                 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
355                 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
356         } else {
357                 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
358         }
359         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
360         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
361         b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
362         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
363         b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
364         b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
365         b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
366         b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
367         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xF81F, 0xA0);
368         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
369         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
370         if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
371                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
372                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
373         } else {
374                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
375                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
376         }
377         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
378         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
379         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
380         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
381         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
382         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
383         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
384         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
385         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
386         b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
387
388         if ((bus->chip_id == 0x4325) && (bus->chip_rev == 1)) {
389                 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
390                 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
391         }
392
393         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
394                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
395                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
396                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
397                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
398                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
399         } else /* 5GHz */
400                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
401
402         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
403         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
404         b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
405         b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
406         b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
407         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
408         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
409                       0x2000 | ((u16)lpphy->rssi_gs << 10) |
410                       ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
411
412         if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
413                 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
414                 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
415                 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
416         }
417
418         lpphy_save_dig_flt_state(dev);
419 }
420
421 static void lpphy_baseband_init(struct b43_wldev *dev)
422 {
423         lpphy_table_init(dev);
424         if (dev->phy.rev >= 2)
425                 lpphy_baseband_rev2plus_init(dev);
426         else
427                 lpphy_baseband_rev0_1_init(dev);
428 }
429
430 struct b2062_freqdata {
431         u16 freq;
432         u8 data[6];
433 };
434
435 /* Initialize the 2062 radio. */
436 static void lpphy_2062_init(struct b43_wldev *dev)
437 {
438         struct ssb_bus *bus = dev->dev->bus;
439         u32 crystalfreq, pdiv, tmp, ref;
440         unsigned int i;
441         const struct b2062_freqdata *fd = NULL;
442
443         static const struct b2062_freqdata freqdata_tab[] = {
444                 { .freq = 12000, .data[0] =  6, .data[1] =  6, .data[2] =  6,
445                                  .data[3] =  6, .data[4] = 10, .data[5] =  6, },
446                 { .freq = 13000, .data[0] =  4, .data[1] =  4, .data[2] =  4,
447                                  .data[3] =  4, .data[4] = 11, .data[5] =  7, },
448                 { .freq = 14400, .data[0] =  3, .data[1] =  3, .data[2] =  3,
449                                  .data[3] =  3, .data[4] = 12, .data[5] =  7, },
450                 { .freq = 16200, .data[0] =  3, .data[1] =  3, .data[2] =  3,
451                                  .data[3] =  3, .data[4] = 13, .data[5] =  8, },
452                 { .freq = 18000, .data[0] =  2, .data[1] =  2, .data[2] =  2,
453                                  .data[3] =  2, .data[4] = 14, .data[5] =  8, },
454                 { .freq = 19200, .data[0] =  1, .data[1] =  1, .data[2] =  1,
455                                  .data[3] =  1, .data[4] = 14, .data[5] =  9, },
456         };
457
458         b2062_upload_init_table(dev);
459
460         b43_radio_write(dev, B2062_N_TX_CTL3, 0);
461         b43_radio_write(dev, B2062_N_TX_CTL4, 0);
462         b43_radio_write(dev, B2062_N_TX_CTL5, 0);
463         b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
464         b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
465         b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
466         b43_radio_write(dev, B2062_N_CALIB_TS, 0);
467         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
468                 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
469         else
470                 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
471
472         /* Get the crystal freq, in Hz. */
473         crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
474
475         B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
476         B43_WARN_ON(crystalfreq == 0);
477
478         if (crystalfreq >= 30000000) {
479                 pdiv = 1;
480                 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
481         } else {
482                 pdiv = 2;
483                 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
484         }
485
486         tmp = (800000000 * pdiv + crystalfreq) / (32000000 * pdiv);
487         tmp = (tmp - 1) & 0xFF;
488         b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
489
490         tmp = (2 * crystalfreq + 1000000 * pdiv) / (2000000 * pdiv);
491         tmp = ((tmp & 0xFF) - 1) & 0xFFFF;
492         b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
493
494         ref = (1000 * pdiv + 2 * crystalfreq) / (2000 * pdiv);
495         ref &= 0xFFFF;
496         for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
497                 if (ref < freqdata_tab[i].freq) {
498                         fd = &freqdata_tab[i];
499                         break;
500                 }
501         }
502         if (!fd)
503                 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
504         b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
505                fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
506
507         b43_radio_write(dev, B2062_S_RFPLL_CTL8,
508                         ((u16)(fd->data[1]) << 4) | fd->data[0]);
509         b43_radio_write(dev, B2062_S_RFPLL_CTL9,
510                         ((u16)(fd->data[3]) << 4) | fd->data[2]);
511         b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
512         b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
513 }
514
515 /* Initialize the 2063 radio. */
516 static void lpphy_2063_init(struct b43_wldev *dev)
517 {
518         b2063_upload_init_table(dev);
519         b43_radio_write(dev, B2063_LOGEN_SP5, 0);
520         b43_radio_set(dev, B2063_COMM8, 0x38);
521         b43_radio_write(dev, B2063_REG_SP1, 0x56);
522         b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
523         b43_radio_write(dev, B2063_PA_SP7, 0);
524         b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
525         b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
526         b43_radio_write(dev, B2063_PA_SP3, 0xa0);
527         b43_radio_write(dev, B2063_PA_SP4, 0xa0);
528         b43_radio_write(dev, B2063_PA_SP2, 0x18);
529 }
530
531 struct lpphy_stx_table_entry {
532         u16 phy_offset;
533         u16 phy_shift;
534         u16 rf_addr;
535         u16 rf_shift;
536         u16 mask;
537 };
538
539 static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
540         { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
541         { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
542         { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
543         { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
544         { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
545         { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
546         { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
547         { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
548         { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
549         { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
550         { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
551         { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
552         { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
553         { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
554         { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
555         { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
556         { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
557         { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
558         { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
559         { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
560         { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
561         { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
562         { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
563         { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
564         { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
565         { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
566         { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
567         { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
568         { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
569 };
570
571 static void lpphy_sync_stx(struct b43_wldev *dev)
572 {
573         const struct lpphy_stx_table_entry *e;
574         unsigned int i;
575         u16 tmp;
576
577         for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
578                 e = &lpphy_stx_table[i];
579                 tmp = b43_radio_read(dev, e->rf_addr);
580                 tmp >>= e->rf_shift;
581                 tmp <<= e->phy_shift;
582                 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
583                                 ~(e->mask << e->phy_shift), tmp);
584         }
585 }
586
587 static void lpphy_radio_init(struct b43_wldev *dev)
588 {
589         /* The radio is attached through the 4wire bus. */
590         b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
591         udelay(1);
592         b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
593         udelay(1);
594
595         if (dev->phy.rev < 2) {
596                 lpphy_2062_init(dev);
597         } else {
598                 lpphy_2063_init(dev);
599                 lpphy_sync_stx(dev);
600                 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
601                 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
602                 if (dev->dev->bus->chip_id == 0x4325) {
603                         // TODO SSB PMU recalibration
604                 }
605         }
606 }
607
608 /* Read the TX power control mode from hardware. */
609 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
610 {
611         struct b43_phy_lp *lpphy = dev->phy.lp;
612         u16 ctl;
613
614         ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
615         switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
616         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
617                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
618                 break;
619         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
620                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
621                 break;
622         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
623                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
624                 break;
625         default:
626                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
627                 B43_WARN_ON(1);
628                 break;
629         }
630 }
631
632 /* Set the TX power control mode in hardware. */
633 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
634 {
635         struct b43_phy_lp *lpphy = dev->phy.lp;
636         u16 ctl;
637
638         switch (lpphy->txpctl_mode) {
639         case B43_LPPHY_TXPCTL_OFF:
640                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
641                 break;
642         case B43_LPPHY_TXPCTL_HW:
643                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
644                 break;
645         case B43_LPPHY_TXPCTL_SW:
646                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
647                 break;
648         default:
649                 ctl = 0;
650                 B43_WARN_ON(1);
651         }
652         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
653                         (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
654 }
655
656 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
657                                        enum b43_lpphy_txpctl_mode mode)
658 {
659         struct b43_phy_lp *lpphy = dev->phy.lp;
660         enum b43_lpphy_txpctl_mode oldmode;
661
662         oldmode = lpphy->txpctl_mode;
663         lpphy_read_tx_pctl_mode_from_hardware(dev);
664         if (lpphy->txpctl_mode == mode)
665                 return;
666         lpphy->txpctl_mode = mode;
667
668         if (oldmode == B43_LPPHY_TXPCTL_HW) {
669                 //TODO Update TX Power NPT
670                 //TODO Clear all TX Power offsets
671         } else {
672                 if (mode == B43_LPPHY_TXPCTL_HW) {
673                         //TODO Recalculate target TX power
674                         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
675                                         0xFF80, lpphy->tssi_idx);
676                         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
677                                         0x8FFF, ((u16)lpphy->tssi_npt << 16));
678                         //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
679                         //TODO Disable TX gain override
680                         lpphy->tx_pwr_idx_over = -1;
681                 }
682         }
683         if (dev->phy.rev >= 2) {
684                 if (mode == B43_LPPHY_TXPCTL_HW)
685                         b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
686                 else
687                         b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
688         }
689         lpphy_write_tx_pctl_mode_to_hardware(dev);
690 }
691
692 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
693 {
694         struct b43_phy_lp *lpphy = dev->phy.lp;
695
696         lpphy->tx_pwr_idx_over = index;
697         if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
698                 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
699
700         //TODO
701 }
702
703 static void lpphy_btcoex_override(struct b43_wldev *dev)
704 {
705         b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
706         b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
707 }
708
709 static void lpphy_pr41573_workaround(struct b43_wldev *dev)
710 {
711         struct b43_phy_lp *lpphy = dev->phy.lp;
712         u32 *saved_tab;
713         const unsigned int saved_tab_size = 256;
714         enum b43_lpphy_txpctl_mode txpctl_mode;
715         s8 tx_pwr_idx_over;
716         u16 tssi_npt, tssi_idx;
717
718         saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
719         if (!saved_tab) {
720                 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
721                 return;
722         }
723
724         lpphy_read_tx_pctl_mode_from_hardware(dev);
725         txpctl_mode = lpphy->txpctl_mode;
726         tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
727         tssi_npt = lpphy->tssi_npt;
728         tssi_idx = lpphy->tssi_idx;
729
730         if (dev->phy.rev < 2) {
731                 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
732                                     saved_tab_size, saved_tab);
733         } else {
734                 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
735                                     saved_tab_size, saved_tab);
736         }
737         //TODO
738
739         kfree(saved_tab);
740 }
741
742 static void lpphy_calibration(struct b43_wldev *dev)
743 {
744         struct b43_phy_lp *lpphy = dev->phy.lp;
745         enum b43_lpphy_txpctl_mode saved_pctl_mode;
746
747         b43_mac_suspend(dev);
748
749         lpphy_btcoex_override(dev);
750         lpphy_read_tx_pctl_mode_from_hardware(dev);
751         saved_pctl_mode = lpphy->txpctl_mode;
752         lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
753         //TODO Perform transmit power table I/Q LO calibration
754         if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
755                 lpphy_pr41573_workaround(dev);
756         //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
757         lpphy_set_tx_power_control(dev, saved_pctl_mode);
758         //TODO Perform I/Q calibration with a single control value set
759
760         b43_mac_enable(dev);
761 }
762
763 /* Initialize TX power control */
764 static void lpphy_tx_pctl_init(struct b43_wldev *dev)
765 {
766         if (0/*FIXME HWPCTL capable */) {
767                 //TODO
768         } else { /* This device is only software TX power control capable. */
769                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
770                         //TODO
771                 } else {
772                         //TODO
773                 }
774                 //TODO set BB multiplier to 0x0096
775         }
776 }
777
778 static int b43_lpphy_op_init(struct b43_wldev *dev)
779 {
780         lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
781         lpphy_baseband_init(dev);
782         lpphy_radio_init(dev);
783         //TODO calibrate RC
784         //TODO set channel
785         lpphy_tx_pctl_init(dev);
786         lpphy_calibration(dev);
787         //TODO ACI init
788
789         return 0;
790 }
791
792 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
793 {
794         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
795         return b43_read16(dev, B43_MMIO_PHY_DATA);
796 }
797
798 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
799 {
800         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
801         b43_write16(dev, B43_MMIO_PHY_DATA, value);
802 }
803
804 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
805 {
806         /* Register 1 is a 32-bit register. */
807         B43_WARN_ON(reg == 1);
808         /* LP-PHY needs a special bit set for read access */
809         if (dev->phy.rev < 2) {
810                 if (reg != 0x4001)
811                         reg |= 0x100;
812         } else
813                 reg |= 0x200;
814
815         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
816         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
817 }
818
819 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
820 {
821         /* Register 1 is a 32-bit register. */
822         B43_WARN_ON(reg == 1);
823
824         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
825         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
826 }
827
828 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
829                                          bool blocked)
830 {
831         //TODO
832 }
833
834 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
835                                        unsigned int new_channel)
836 {
837         //TODO
838         return 0;
839 }
840
841 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
842 {
843         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
844                 return 1;
845         return 36;
846 }
847
848 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
849 {
850         //TODO
851 }
852
853 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
854 {
855         //TODO
856 }
857
858 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
859                                                          bool ignore_tssi)
860 {
861         //TODO
862         return B43_TXPWR_RES_DONE;
863 }
864
865 const struct b43_phy_operations b43_phyops_lp = {
866         .allocate               = b43_lpphy_op_allocate,
867         .free                   = b43_lpphy_op_free,
868         .prepare_structs        = b43_lpphy_op_prepare_structs,
869         .init                   = b43_lpphy_op_init,
870         .phy_read               = b43_lpphy_op_read,
871         .phy_write              = b43_lpphy_op_write,
872         .radio_read             = b43_lpphy_op_radio_read,
873         .radio_write            = b43_lpphy_op_radio_write,
874         .software_rfkill        = b43_lpphy_op_software_rfkill,
875         .switch_analog          = b43_phyop_switch_analog_generic,
876         .switch_channel         = b43_lpphy_op_switch_channel,
877         .get_default_chan       = b43_lpphy_op_get_default_chan,
878         .set_rx_antenna         = b43_lpphy_op_set_rx_antenna,
879         .recalc_txpower         = b43_lpphy_op_recalc_txpower,
880         .adjust_txpower         = b43_lpphy_op_adjust_txpower,
881 };