b43: implement baseband init for LP-PHY <= rev1
[linux-2.6.git] / drivers / net / wireless / b43 / phy_lp.c
1 /*
2
3   Broadcom B43 wireless driver
4   IEEE 802.11g LP-PHY driver
5
6   Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
7
8   This program is free software; you can redistribute it and/or modify
9   it under the terms of the GNU General Public License as published by
10   the Free Software Foundation; either version 2 of the License, or
11   (at your option) any later version.
12
13   This program is distributed in the hope that it will be useful,
14   but WITHOUT ANY WARRANTY; without even the implied warranty of
15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16   GNU General Public License for more details.
17
18   You should have received a copy of the GNU General Public License
19   along with this program; see the file COPYING.  If not, write to
20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21   Boston, MA 02110-1301, USA.
22
23 */
24
25 #include "b43.h"
26 #include "main.h"
27 #include "phy_lp.h"
28 #include "phy_common.h"
29 #include "tables_lpphy.h"
30
31
32 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
33 {
34         struct b43_phy_lp *lpphy;
35
36         lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
37         if (!lpphy)
38                 return -ENOMEM;
39         dev->phy.lp = lpphy;
40
41         return 0;
42 }
43
44 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
45 {
46         struct b43_phy *phy = &dev->phy;
47         struct b43_phy_lp *lpphy = phy->lp;
48
49         memset(lpphy, 0, sizeof(*lpphy));
50
51         //TODO
52 }
53
54 static void b43_lpphy_op_free(struct b43_wldev *dev)
55 {
56         struct b43_phy_lp *lpphy = dev->phy.lp;
57
58         kfree(lpphy);
59         dev->phy.lp = NULL;
60 }
61
62 static void lpphy_table_init(struct b43_wldev *dev)
63 {
64         //TODO
65 }
66
67 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
68 {
69         struct ssb_bus *bus = dev->dev->bus;
70         u16 tmp, tmp2;
71
72         if (dev->phy.rev == 1 &&
73            (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
74                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
75                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
76                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
77                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
78                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
79                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
80                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
81                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
82                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
83                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
84                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
85                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
86                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
87                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
88                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
89                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
90         } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
91                   (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
92                   (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
93                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
94                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
95                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
96                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
97                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
98                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
99                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
100                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
101         } else if (dev->phy.rev == 1 ||
102                   (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
103                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
104                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
105                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
106                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
107                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
108                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
109                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
110                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
111         } else {
112                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
113                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
114                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
115                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
116                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
117                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
118                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
119                 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
120         }
121         if (dev->phy.rev == 1) {
122                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
123                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
124                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
125                 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
126         }
127         if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
128             (bus->chip_id == 0x5354) &&
129             (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
130                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
131                 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
132                 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
133                 b43_hf_write(dev, b43_hf_read(dev) | 0x0800ULL << 32);
134         }
135         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
136                 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
137                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
138                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
139                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
140                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
141                 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
142                 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
143                 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
144         } else { /* 5GHz */
145                 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
146                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
147         }
148         if (dev->phy.rev == 1) {
149                 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
150                 tmp2 = (tmp & 0x03E0) >> 5;
151                 tmp2 |= tmp << 5;
152                 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
153                 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
154                 tmp2 = (tmp & 0x1F00) >> 8;
155                 tmp2 |= tmp << 5;
156                 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
157                 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
158                 tmp2 = tmp & 0x00FF;
159                 tmp2 |= tmp << 8;
160                 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
161         }
162 }
163
164 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
165 {
166         struct ssb_bus *bus = dev->dev->bus;
167         struct b43_phy_lp *lpphy = dev->phy.lp;
168
169         b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
170         b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
171         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
172         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
173         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
174         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
175         b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
176         b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
177         b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
178         b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x78);
179         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
180         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
181         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
182         b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
183         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
184         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
185         b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
186         b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
187         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
188         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
189         b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
190         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
191         b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
192         b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
193         b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
194         b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
195         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xF81F, 0xA0);
196         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
197         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
198         if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
199                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
200                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
201         } else {
202                 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
203                 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
204         }
205         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
206         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
207         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
208         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
209         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
210         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
211         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
212         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
213         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
214         b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
215
216         b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
217         b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
218
219         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
220                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
221                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
222                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
223                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
224                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
225         } else /* 5GHz */
226                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
227
228         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
229         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
230         b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
231         b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
232         b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
233         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
234         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
235                       0x2000 | ((u16)lpphy->rssi_gs << 10) |
236                       ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
237 }
238
239 static void lpphy_baseband_init(struct b43_wldev *dev)
240 {
241         lpphy_table_init(dev);
242         if (dev->phy.rev >= 2)
243                 lpphy_baseband_rev2plus_init(dev);
244         else
245                 lpphy_baseband_rev0_1_init(dev);
246 }
247
248 struct b2062_freqdata {
249         u16 freq;
250         u8 data[6];
251 };
252
253 /* Initialize the 2062 radio. */
254 static void lpphy_2062_init(struct b43_wldev *dev)
255 {
256         struct ssb_bus *bus = dev->dev->bus;
257         u32 crystalfreq, pdiv, tmp, ref;
258         unsigned int i;
259         const struct b2062_freqdata *fd = NULL;
260
261         static const struct b2062_freqdata freqdata_tab[] = {
262                 { .freq = 12000, .data[0] =  6, .data[1] =  6, .data[2] =  6,
263                                  .data[3] =  6, .data[4] = 10, .data[5] =  6, },
264                 { .freq = 13000, .data[0] =  4, .data[1] =  4, .data[2] =  4,
265                                  .data[3] =  4, .data[4] = 11, .data[5] =  7, },
266                 { .freq = 14400, .data[0] =  3, .data[1] =  3, .data[2] =  3,
267                                  .data[3] =  3, .data[4] = 12, .data[5] =  7, },
268                 { .freq = 16200, .data[0] =  3, .data[1] =  3, .data[2] =  3,
269                                  .data[3] =  3, .data[4] = 13, .data[5] =  8, },
270                 { .freq = 18000, .data[0] =  2, .data[1] =  2, .data[2] =  2,
271                                  .data[3] =  2, .data[4] = 14, .data[5] =  8, },
272                 { .freq = 19200, .data[0] =  1, .data[1] =  1, .data[2] =  1,
273                                  .data[3] =  1, .data[4] = 14, .data[5] =  9, },
274         };
275
276         b2062_upload_init_table(dev);
277
278         b43_radio_write(dev, B2062_N_TX_CTL3, 0);
279         b43_radio_write(dev, B2062_N_TX_CTL4, 0);
280         b43_radio_write(dev, B2062_N_TX_CTL5, 0);
281         b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
282         b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
283         b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
284         b43_radio_write(dev, B2062_N_CALIB_TS, 0);
285         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
286                 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
287         else
288                 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
289
290         /* Get the crystal freq, in Hz. */
291         crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
292
293         B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
294         B43_WARN_ON(crystalfreq == 0);
295
296         if (crystalfreq >= 30000000) {
297                 pdiv = 1;
298                 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
299         } else {
300                 pdiv = 2;
301                 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
302         }
303
304         tmp = (800000000 * pdiv + crystalfreq) / (32000000 * pdiv);
305         tmp = (tmp - 1) & 0xFF;
306         b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
307
308         tmp = (2 * crystalfreq + 1000000 * pdiv) / (2000000 * pdiv);
309         tmp = ((tmp & 0xFF) - 1) & 0xFFFF;
310         b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
311
312         ref = (1000 * pdiv + 2 * crystalfreq) / (2000 * pdiv);
313         ref &= 0xFFFF;
314         for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
315                 if (ref < freqdata_tab[i].freq) {
316                         fd = &freqdata_tab[i];
317                         break;
318                 }
319         }
320         if (!fd)
321                 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
322         b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
323                fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
324
325         b43_radio_write(dev, B2062_S_RFPLL_CTL8,
326                         ((u16)(fd->data[1]) << 4) | fd->data[0]);
327         b43_radio_write(dev, B2062_S_RFPLL_CTL9,
328                         ((u16)(fd->data[3]) << 4) | fd->data[2]);
329         b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
330         b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
331 }
332
333 /* Initialize the 2063 radio. */
334 static void lpphy_2063_init(struct b43_wldev *dev)
335 {
336         //TODO
337 }
338
339 static void lpphy_sync_stx(struct b43_wldev *dev)
340 {
341         //TODO
342 }
343
344 static void lpphy_radio_init(struct b43_wldev *dev)
345 {
346         /* The radio is attached through the 4wire bus. */
347         b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
348         udelay(1);
349         b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
350         udelay(1);
351
352         if (dev->phy.rev < 2) {
353                 lpphy_2062_init(dev);
354         } else {
355                 lpphy_2063_init(dev);
356                 lpphy_sync_stx(dev);
357                 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
358                 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
359                 //TODO Do something on the backplane
360         }
361 }
362
363 /* Read the TX power control mode from hardware. */
364 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
365 {
366         struct b43_phy_lp *lpphy = dev->phy.lp;
367         u16 ctl;
368
369         ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
370         switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
371         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
372                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
373                 break;
374         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
375                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
376                 break;
377         case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
378                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
379                 break;
380         default:
381                 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
382                 B43_WARN_ON(1);
383                 break;
384         }
385 }
386
387 /* Set the TX power control mode in hardware. */
388 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
389 {
390         struct b43_phy_lp *lpphy = dev->phy.lp;
391         u16 ctl;
392
393         switch (lpphy->txpctl_mode) {
394         case B43_LPPHY_TXPCTL_OFF:
395                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
396                 break;
397         case B43_LPPHY_TXPCTL_HW:
398                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
399                 break;
400         case B43_LPPHY_TXPCTL_SW:
401                 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
402                 break;
403         default:
404                 ctl = 0;
405                 B43_WARN_ON(1);
406         }
407         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
408                         (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
409 }
410
411 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
412                                        enum b43_lpphy_txpctl_mode mode)
413 {
414         struct b43_phy_lp *lpphy = dev->phy.lp;
415         enum b43_lpphy_txpctl_mode oldmode;
416
417         oldmode = lpphy->txpctl_mode;
418         lpphy_read_tx_pctl_mode_from_hardware(dev);
419         if (lpphy->txpctl_mode == mode)
420                 return;
421         lpphy->txpctl_mode = mode;
422
423         if (oldmode == B43_LPPHY_TXPCTL_HW) {
424                 //TODO Update TX Power NPT
425                 //TODO Clear all TX Power offsets
426         } else {
427                 if (mode == B43_LPPHY_TXPCTL_HW) {
428                         //TODO Recalculate target TX power
429                         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
430                                         0xFF80, lpphy->tssi_idx);
431                         b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
432                                         0x8FFF, ((u16)lpphy->tssi_npt << 16));
433                         //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
434                         //TODO Disable TX gain override
435                         lpphy->tx_pwr_idx_over = -1;
436                 }
437         }
438         if (dev->phy.rev >= 2) {
439                 if (mode == B43_LPPHY_TXPCTL_HW)
440                         b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0x2);
441                 else
442                         b43_phy_maskset(dev, B43_PHY_OFDM(0xD0), 0xFD, 0);
443         }
444         lpphy_write_tx_pctl_mode_to_hardware(dev);
445 }
446
447 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
448 {
449         struct b43_phy_lp *lpphy = dev->phy.lp;
450
451         lpphy->tx_pwr_idx_over = index;
452         if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
453                 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
454
455         //TODO
456 }
457
458 static void lpphy_btcoex_override(struct b43_wldev *dev)
459 {
460         b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
461         b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
462 }
463
464 static void lpphy_pr41573_workaround(struct b43_wldev *dev)
465 {
466         struct b43_phy_lp *lpphy = dev->phy.lp;
467         u32 *saved_tab;
468         const unsigned int saved_tab_size = 256;
469         enum b43_lpphy_txpctl_mode txpctl_mode;
470         s8 tx_pwr_idx_over;
471         u16 tssi_npt, tssi_idx;
472
473         saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
474         if (!saved_tab) {
475                 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
476                 return;
477         }
478
479         lpphy_read_tx_pctl_mode_from_hardware(dev);
480         txpctl_mode = lpphy->txpctl_mode;
481         tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
482         tssi_npt = lpphy->tssi_npt;
483         tssi_idx = lpphy->tssi_idx;
484
485         if (dev->phy.rev < 2) {
486                 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
487                                     saved_tab_size, saved_tab);
488         } else {
489                 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
490                                     saved_tab_size, saved_tab);
491         }
492         //TODO
493
494         kfree(saved_tab);
495 }
496
497 static void lpphy_calibration(struct b43_wldev *dev)
498 {
499         struct b43_phy_lp *lpphy = dev->phy.lp;
500         enum b43_lpphy_txpctl_mode saved_pctl_mode;
501
502         b43_mac_suspend(dev);
503
504         lpphy_btcoex_override(dev);
505         lpphy_read_tx_pctl_mode_from_hardware(dev);
506         saved_pctl_mode = lpphy->txpctl_mode;
507         lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
508         //TODO Perform transmit power table I/Q LO calibration
509         if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
510                 lpphy_pr41573_workaround(dev);
511         //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
512         lpphy_set_tx_power_control(dev, saved_pctl_mode);
513         //TODO Perform I/Q calibration with a single control value set
514
515         b43_mac_enable(dev);
516 }
517
518 /* Initialize TX power control */
519 static void lpphy_tx_pctl_init(struct b43_wldev *dev)
520 {
521         if (0/*FIXME HWPCTL capable */) {
522                 //TODO
523         } else { /* This device is only software TX power control capable. */
524                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
525                         //TODO
526                 } else {
527                         //TODO
528                 }
529                 //TODO set BB multiplier to 0x0096
530         }
531 }
532
533 static int b43_lpphy_op_init(struct b43_wldev *dev)
534 {
535         /* TODO: band SPROM */
536         lpphy_baseband_init(dev);
537         lpphy_radio_init(dev);
538         //TODO calibrate RC
539         //TODO set channel
540         lpphy_tx_pctl_init(dev);
541         //TODO full calib
542
543         return 0;
544 }
545
546 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
547 {
548         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
549         return b43_read16(dev, B43_MMIO_PHY_DATA);
550 }
551
552 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
553 {
554         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
555         b43_write16(dev, B43_MMIO_PHY_DATA, value);
556 }
557
558 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
559 {
560         /* Register 1 is a 32-bit register. */
561         B43_WARN_ON(reg == 1);
562         /* LP-PHY needs a special bit set for read access */
563         if (dev->phy.rev < 2) {
564                 if (reg != 0x4001)
565                         reg |= 0x100;
566         } else
567                 reg |= 0x200;
568
569         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
570         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
571 }
572
573 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
574 {
575         /* Register 1 is a 32-bit register. */
576         B43_WARN_ON(reg == 1);
577
578         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
579         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
580 }
581
582 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
583                                          bool blocked)
584 {
585         //TODO
586 }
587
588 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
589                                        unsigned int new_channel)
590 {
591         //TODO
592         return 0;
593 }
594
595 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
596 {
597         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
598                 return 1;
599         return 36;
600 }
601
602 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
603 {
604         //TODO
605 }
606
607 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
608 {
609         //TODO
610 }
611
612 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
613                                                          bool ignore_tssi)
614 {
615         //TODO
616         return B43_TXPWR_RES_DONE;
617 }
618
619
620 const struct b43_phy_operations b43_phyops_lp = {
621         .allocate               = b43_lpphy_op_allocate,
622         .free                   = b43_lpphy_op_free,
623         .prepare_structs        = b43_lpphy_op_prepare_structs,
624         .init                   = b43_lpphy_op_init,
625         .phy_read               = b43_lpphy_op_read,
626         .phy_write              = b43_lpphy_op_write,
627         .radio_read             = b43_lpphy_op_radio_read,
628         .radio_write            = b43_lpphy_op_radio_write,
629         .software_rfkill        = b43_lpphy_op_software_rfkill,
630         .switch_analog          = b43_phyop_switch_analog_generic,
631         .switch_channel         = b43_lpphy_op_switch_channel,
632         .get_default_chan       = b43_lpphy_op_get_default_chan,
633         .set_rx_antenna         = b43_lpphy_op_set_rx_antenna,
634         .recalc_txpower         = b43_lpphy_op_recalc_txpower,
635         .adjust_txpower         = b43_lpphy_op_adjust_txpower,
636 };