b43: Add LP-PHY baseband init for >=rev2
[linux-2.6.git] / drivers / net / wireless / b43 / phy_lp.c
1 /*
2
3   Broadcom B43 wireless driver
4   IEEE 802.11g LP-PHY driver
5
6   Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
7
8   This program is free software; you can redistribute it and/or modify
9   it under the terms of the GNU General Public License as published by
10   the Free Software Foundation; either version 2 of the License, or
11   (at your option) any later version.
12
13   This program is distributed in the hope that it will be useful,
14   but WITHOUT ANY WARRANTY; without even the implied warranty of
15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16   GNU General Public License for more details.
17
18   You should have received a copy of the GNU General Public License
19   along with this program; see the file COPYING.  If not, write to
20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21   Boston, MA 02110-1301, USA.
22
23 */
24
25 #include "b43.h"
26 #include "phy_lp.h"
27 #include "phy_common.h"
28 #include "tables_lpphy.h"
29
30
31 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
32 {
33         struct b43_phy_lp *lpphy;
34
35         lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
36         if (!lpphy)
37                 return -ENOMEM;
38         dev->phy.lp = lpphy;
39
40         return 0;
41 }
42
43 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
44 {
45         struct b43_phy *phy = &dev->phy;
46         struct b43_phy_lp *lpphy = phy->lp;
47
48         memset(lpphy, 0, sizeof(*lpphy));
49
50         //TODO
51 }
52
53 static void b43_lpphy_op_free(struct b43_wldev *dev)
54 {
55         struct b43_phy_lp *lpphy = dev->phy.lp;
56
57         kfree(lpphy);
58         dev->phy.lp = NULL;
59 }
60
61 static void lpphy_table_init(struct b43_wldev *dev)
62 {
63         //TODO
64 }
65
66 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
67 {
68         B43_WARN_ON(1);//TODO rev < 2 not supported, yet.
69 }
70
71 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
72 {
73         struct b43_phy_lp *lpphy = dev->phy.lp;
74
75         b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
76         b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
77         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
78         b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
79         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
80         b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
81         b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
82         b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
83         b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
84         b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x78);
85         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
86         b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
87         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
88         b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
89         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
90         b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
91         b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
92         b43_phy_maskset(dev, B43_LPPHY_CCKLMSSTEPSIZE, 0xFF01, 0x10);
93         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
94         b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);//FIXME specs are different
95         b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
96         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
97         b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
98         b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
99         b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
100         b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
101         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xF81F, 0xA0);
102         b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
103         b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
104         b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
105         b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
106         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
107         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
108         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
109         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
110         b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
111         b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
112         b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
113         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
114         b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
115         b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
116
117         if (dev->phy.rev < 2) {
118                 //FIXME this will never execute.
119
120                 //FIXME 32bit?
121                 b43_lptab_write(dev, B43_LPTAB32(0x11, 0x14), 0);
122                 b43_lptab_write(dev, B43_LPTAB32(0x08, 0x12), 0x40);
123         } else {
124                 //FIXME 32bit?
125                 b43_lptab_write(dev, B43_LPTAB32(0x08, 0x14), 0);
126                 b43_lptab_write(dev, B43_LPTAB32(0x08, 0x12), 0x40);
127         }
128
129         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
130                 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
131                 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
132                 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
133                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
134                 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
135         } else /* 5GHz */
136                 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
137
138         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
139         b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
140         b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
141         b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
142         b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
143         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
144         b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
145                       0x2000 | ((u16)lpphy->rssi_gs << 10) |
146                       ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
147 }
148
149 static void lpphy_baseband_init(struct b43_wldev *dev)
150 {
151         lpphy_table_init(dev);
152         if (dev->phy.rev >= 2)
153                 lpphy_baseband_rev2plus_init(dev);
154         else
155                 lpphy_baseband_rev0_1_init(dev);
156 }
157
158 static void lpphy_radio_init(struct b43_wldev *dev)
159 {
160         //TODO
161 }
162
163 static int b43_lpphy_op_init(struct b43_wldev *dev)
164 {
165         /* TODO: band SPROM */
166         lpphy_baseband_init(dev);
167         lpphy_radio_init(dev);
168
169         //TODO
170
171         return 0;
172 }
173
174 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
175 {
176         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
177         return b43_read16(dev, B43_MMIO_PHY_DATA);
178 }
179
180 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
181 {
182         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
183         b43_write16(dev, B43_MMIO_PHY_DATA, value);
184 }
185
186 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
187 {
188         /* Register 1 is a 32-bit register. */
189         B43_WARN_ON(reg == 1);
190         /* LP-PHY needs a special bit set for read access */
191         if (dev->phy.rev < 2) {
192                 if (reg != 0x4001)
193                         reg |= 0x100;
194         } else
195                 reg |= 0x200;
196
197         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
198         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
199 }
200
201 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
202 {
203         /* Register 1 is a 32-bit register. */
204         B43_WARN_ON(reg == 1);
205
206         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
207         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
208 }
209
210 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
211                                          enum rfkill_state state)
212 {
213         //TODO
214 }
215
216 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
217                                        unsigned int new_channel)
218 {
219         //TODO
220         return 0;
221 }
222
223 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
224 {
225         return 1; /* Default to channel 1 */
226 }
227
228 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
229 {
230         //TODO
231 }
232
233 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
234 {
235         //TODO
236 }
237
238 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
239                                                          bool ignore_tssi)
240 {
241         //TODO
242         return B43_TXPWR_RES_DONE;
243 }
244
245
246 const struct b43_phy_operations b43_phyops_lp = {
247         .allocate               = b43_lpphy_op_allocate,
248         .free                   = b43_lpphy_op_free,
249         .prepare_structs        = b43_lpphy_op_prepare_structs,
250         .init                   = b43_lpphy_op_init,
251         .phy_read               = b43_lpphy_op_read,
252         .phy_write              = b43_lpphy_op_write,
253         .radio_read             = b43_lpphy_op_radio_read,
254         .radio_write            = b43_lpphy_op_radio_write,
255         .software_rfkill        = b43_lpphy_op_software_rfkill,
256         .switch_analog          = b43_phyop_switch_analog_generic,
257         .switch_channel         = b43_lpphy_op_switch_channel,
258         .get_default_chan       = b43_lpphy_op_get_default_chan,
259         .set_rx_antenna         = b43_lpphy_op_set_rx_antenna,
260         .recalc_txpower         = b43_lpphy_op_recalc_txpower,
261         .adjust_txpower         = b43_lpphy_op_adjust_txpower,
262 };