b43: Fix firmware loading when driver is built into the kernel
[linux-2.6.git] / drivers / net / wireless / b43 / main.c
1 /*
2
3   Broadcom B43 wireless driver
4
5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7   Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10   Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
11
12   SDIO support
13   Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14
15   Some parts of the code in this file are derived from the ipw2200
16   driver  Copyright(c) 2003 - 2004 Intel Corporation.
17
18   This program is free software; you can redistribute it and/or modify
19   it under the terms of the GNU General Public License as published by
20   the Free Software Foundation; either version 2 of the License, or
21   (at your option) any later version.
22
23   This program is distributed in the hope that it will be useful,
24   but WITHOUT ANY WARRANTY; without even the implied warranty of
25   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26   GNU General Public License for more details.
27
28   You should have received a copy of the GNU General Public License
29   along with this program; see the file COPYING.  If not, write to
30   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
31   Boston, MA 02110-1301, USA.
32
33 */
34
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/module.h>
38 #include <linux/if_arp.h>
39 #include <linux/etherdevice.h>
40 #include <linux/firmware.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
43 #include <linux/io.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/slab.h>
46 #include <asm/unaligned.h>
47
48 #include "b43.h"
49 #include "main.h"
50 #include "debugfs.h"
51 #include "phy_common.h"
52 #include "phy_g.h"
53 #include "phy_n.h"
54 #include "dma.h"
55 #include "pio.h"
56 #include "sysfs.h"
57 #include "xmit.h"
58 #include "lo.h"
59 #include "pcmcia.h"
60 #include "sdio.h"
61 #include <linux/mmc/sdio_func.h>
62
63 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
64 MODULE_AUTHOR("Martin Langer");
65 MODULE_AUTHOR("Stefano Brivio");
66 MODULE_AUTHOR("Michael Buesch");
67 MODULE_AUTHOR("Gábor Stefanik");
68 MODULE_AUTHOR("Rafał Miłecki");
69 MODULE_LICENSE("GPL");
70
71 MODULE_FIRMWARE("b43/ucode11.fw");
72 MODULE_FIRMWARE("b43/ucode13.fw");
73 MODULE_FIRMWARE("b43/ucode14.fw");
74 MODULE_FIRMWARE("b43/ucode15.fw");
75 MODULE_FIRMWARE("b43/ucode16_mimo.fw");
76 MODULE_FIRMWARE("b43/ucode5.fw");
77 MODULE_FIRMWARE("b43/ucode9.fw");
78
79 static int modparam_bad_frames_preempt;
80 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
81 MODULE_PARM_DESC(bad_frames_preempt,
82                  "enable(1) / disable(0) Bad Frames Preemption");
83
84 static char modparam_fwpostfix[16];
85 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
86 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
87
88 static int modparam_hwpctl;
89 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
90 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
91
92 static int modparam_nohwcrypt;
93 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
94 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
95
96 static int modparam_hwtkip;
97 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
98 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
99
100 static int modparam_qos = 1;
101 module_param_named(qos, modparam_qos, int, 0444);
102 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
103
104 static int modparam_btcoex = 1;
105 module_param_named(btcoex, modparam_btcoex, int, 0444);
106 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
107
108 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
109 module_param_named(verbose, b43_modparam_verbose, int, 0644);
110 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
111
112 static int b43_modparam_pio = 0;
113 module_param_named(pio, b43_modparam_pio, int, 0644);
114 MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
115
116 #ifdef CONFIG_B43_BCMA
117 static const struct bcma_device_id b43_bcma_tbl[] = {
118         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
119 #ifdef CONFIG_B43_BCMA_EXTRA
120         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
121         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
122 #endif
123         BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
124         BCMA_CORETABLE_END
125 };
126 MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
127 #endif
128
129 #ifdef CONFIG_B43_SSB
130 static const struct ssb_device_id b43_ssb_tbl[] = {
131         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
132         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
133         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
134         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
135         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
136         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
137         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
138         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
139         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
140         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
141         SSB_DEVTABLE_END
142 };
143 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
144 #endif
145
146 /* Channel and ratetables are shared for all devices.
147  * They can't be const, because ieee80211 puts some precalculated
148  * data in there. This data is the same for all devices, so we don't
149  * get concurrency issues */
150 #define RATETAB_ENT(_rateid, _flags) \
151         {                                                               \
152                 .bitrate        = B43_RATE_TO_BASE100KBPS(_rateid),     \
153                 .hw_value       = (_rateid),                            \
154                 .flags          = (_flags),                             \
155         }
156
157 /*
158  * NOTE: When changing this, sync with xmit.c's
159  *       b43_plcp_get_bitrate_idx_* functions!
160  */
161 static struct ieee80211_rate __b43_ratetable[] = {
162         RATETAB_ENT(B43_CCK_RATE_1MB, 0),
163         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
164         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
165         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
166         RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
167         RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
168         RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
169         RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
170         RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
171         RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
172         RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
173         RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
174 };
175
176 #define b43_a_ratetable         (__b43_ratetable + 4)
177 #define b43_a_ratetable_size    8
178 #define b43_b_ratetable         (__b43_ratetable + 0)
179 #define b43_b_ratetable_size    4
180 #define b43_g_ratetable         (__b43_ratetable + 0)
181 #define b43_g_ratetable_size    12
182
183 #define CHAN4G(_channel, _freq, _flags) {                       \
184         .band                   = IEEE80211_BAND_2GHZ,          \
185         .center_freq            = (_freq),                      \
186         .hw_value               = (_channel),                   \
187         .flags                  = (_flags),                     \
188         .max_antenna_gain       = 0,                            \
189         .max_power              = 30,                           \
190 }
191 static struct ieee80211_channel b43_2ghz_chantable[] = {
192         CHAN4G(1, 2412, 0),
193         CHAN4G(2, 2417, 0),
194         CHAN4G(3, 2422, 0),
195         CHAN4G(4, 2427, 0),
196         CHAN4G(5, 2432, 0),
197         CHAN4G(6, 2437, 0),
198         CHAN4G(7, 2442, 0),
199         CHAN4G(8, 2447, 0),
200         CHAN4G(9, 2452, 0),
201         CHAN4G(10, 2457, 0),
202         CHAN4G(11, 2462, 0),
203         CHAN4G(12, 2467, 0),
204         CHAN4G(13, 2472, 0),
205         CHAN4G(14, 2484, 0),
206 };
207 #undef CHAN4G
208
209 #define CHAN5G(_channel, _flags) {                              \
210         .band                   = IEEE80211_BAND_5GHZ,          \
211         .center_freq            = 5000 + (5 * (_channel)),      \
212         .hw_value               = (_channel),                   \
213         .flags                  = (_flags),                     \
214         .max_antenna_gain       = 0,                            \
215         .max_power              = 30,                           \
216 }
217 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
218         CHAN5G(32, 0),          CHAN5G(34, 0),
219         CHAN5G(36, 0),          CHAN5G(38, 0),
220         CHAN5G(40, 0),          CHAN5G(42, 0),
221         CHAN5G(44, 0),          CHAN5G(46, 0),
222         CHAN5G(48, 0),          CHAN5G(50, 0),
223         CHAN5G(52, 0),          CHAN5G(54, 0),
224         CHAN5G(56, 0),          CHAN5G(58, 0),
225         CHAN5G(60, 0),          CHAN5G(62, 0),
226         CHAN5G(64, 0),          CHAN5G(66, 0),
227         CHAN5G(68, 0),          CHAN5G(70, 0),
228         CHAN5G(72, 0),          CHAN5G(74, 0),
229         CHAN5G(76, 0),          CHAN5G(78, 0),
230         CHAN5G(80, 0),          CHAN5G(82, 0),
231         CHAN5G(84, 0),          CHAN5G(86, 0),
232         CHAN5G(88, 0),          CHAN5G(90, 0),
233         CHAN5G(92, 0),          CHAN5G(94, 0),
234         CHAN5G(96, 0),          CHAN5G(98, 0),
235         CHAN5G(100, 0),         CHAN5G(102, 0),
236         CHAN5G(104, 0),         CHAN5G(106, 0),
237         CHAN5G(108, 0),         CHAN5G(110, 0),
238         CHAN5G(112, 0),         CHAN5G(114, 0),
239         CHAN5G(116, 0),         CHAN5G(118, 0),
240         CHAN5G(120, 0),         CHAN5G(122, 0),
241         CHAN5G(124, 0),         CHAN5G(126, 0),
242         CHAN5G(128, 0),         CHAN5G(130, 0),
243         CHAN5G(132, 0),         CHAN5G(134, 0),
244         CHAN5G(136, 0),         CHAN5G(138, 0),
245         CHAN5G(140, 0),         CHAN5G(142, 0),
246         CHAN5G(144, 0),         CHAN5G(145, 0),
247         CHAN5G(146, 0),         CHAN5G(147, 0),
248         CHAN5G(148, 0),         CHAN5G(149, 0),
249         CHAN5G(150, 0),         CHAN5G(151, 0),
250         CHAN5G(152, 0),         CHAN5G(153, 0),
251         CHAN5G(154, 0),         CHAN5G(155, 0),
252         CHAN5G(156, 0),         CHAN5G(157, 0),
253         CHAN5G(158, 0),         CHAN5G(159, 0),
254         CHAN5G(160, 0),         CHAN5G(161, 0),
255         CHAN5G(162, 0),         CHAN5G(163, 0),
256         CHAN5G(164, 0),         CHAN5G(165, 0),
257         CHAN5G(166, 0),         CHAN5G(168, 0),
258         CHAN5G(170, 0),         CHAN5G(172, 0),
259         CHAN5G(174, 0),         CHAN5G(176, 0),
260         CHAN5G(178, 0),         CHAN5G(180, 0),
261         CHAN5G(182, 0),         CHAN5G(184, 0),
262         CHAN5G(186, 0),         CHAN5G(188, 0),
263         CHAN5G(190, 0),         CHAN5G(192, 0),
264         CHAN5G(194, 0),         CHAN5G(196, 0),
265         CHAN5G(198, 0),         CHAN5G(200, 0),
266         CHAN5G(202, 0),         CHAN5G(204, 0),
267         CHAN5G(206, 0),         CHAN5G(208, 0),
268         CHAN5G(210, 0),         CHAN5G(212, 0),
269         CHAN5G(214, 0),         CHAN5G(216, 0),
270         CHAN5G(218, 0),         CHAN5G(220, 0),
271         CHAN5G(222, 0),         CHAN5G(224, 0),
272         CHAN5G(226, 0),         CHAN5G(228, 0),
273 };
274
275 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
276         CHAN5G(34, 0),          CHAN5G(36, 0),
277         CHAN5G(38, 0),          CHAN5G(40, 0),
278         CHAN5G(42, 0),          CHAN5G(44, 0),
279         CHAN5G(46, 0),          CHAN5G(48, 0),
280         CHAN5G(52, 0),          CHAN5G(56, 0),
281         CHAN5G(60, 0),          CHAN5G(64, 0),
282         CHAN5G(100, 0),         CHAN5G(104, 0),
283         CHAN5G(108, 0),         CHAN5G(112, 0),
284         CHAN5G(116, 0),         CHAN5G(120, 0),
285         CHAN5G(124, 0),         CHAN5G(128, 0),
286         CHAN5G(132, 0),         CHAN5G(136, 0),
287         CHAN5G(140, 0),         CHAN5G(149, 0),
288         CHAN5G(153, 0),         CHAN5G(157, 0),
289         CHAN5G(161, 0),         CHAN5G(165, 0),
290         CHAN5G(184, 0),         CHAN5G(188, 0),
291         CHAN5G(192, 0),         CHAN5G(196, 0),
292         CHAN5G(200, 0),         CHAN5G(204, 0),
293         CHAN5G(208, 0),         CHAN5G(212, 0),
294         CHAN5G(216, 0),
295 };
296 #undef CHAN5G
297
298 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
299         .band           = IEEE80211_BAND_5GHZ,
300         .channels       = b43_5ghz_nphy_chantable,
301         .n_channels     = ARRAY_SIZE(b43_5ghz_nphy_chantable),
302         .bitrates       = b43_a_ratetable,
303         .n_bitrates     = b43_a_ratetable_size,
304 };
305
306 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
307         .band           = IEEE80211_BAND_5GHZ,
308         .channels       = b43_5ghz_aphy_chantable,
309         .n_channels     = ARRAY_SIZE(b43_5ghz_aphy_chantable),
310         .bitrates       = b43_a_ratetable,
311         .n_bitrates     = b43_a_ratetable_size,
312 };
313
314 static struct ieee80211_supported_band b43_band_2GHz = {
315         .band           = IEEE80211_BAND_2GHZ,
316         .channels       = b43_2ghz_chantable,
317         .n_channels     = ARRAY_SIZE(b43_2ghz_chantable),
318         .bitrates       = b43_g_ratetable,
319         .n_bitrates     = b43_g_ratetable_size,
320 };
321
322 static void b43_wireless_core_exit(struct b43_wldev *dev);
323 static int b43_wireless_core_init(struct b43_wldev *dev);
324 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
325 static int b43_wireless_core_start(struct b43_wldev *dev);
326 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
327                                     struct ieee80211_vif *vif,
328                                     struct ieee80211_bss_conf *conf,
329                                     u32 changed);
330
331 static int b43_ratelimit(struct b43_wl *wl)
332 {
333         if (!wl || !wl->current_dev)
334                 return 1;
335         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
336                 return 1;
337         /* We are up and running.
338          * Ratelimit the messages to avoid DoS over the net. */
339         return net_ratelimit();
340 }
341
342 void b43info(struct b43_wl *wl, const char *fmt, ...)
343 {
344         struct va_format vaf;
345         va_list args;
346
347         if (b43_modparam_verbose < B43_VERBOSITY_INFO)
348                 return;
349         if (!b43_ratelimit(wl))
350                 return;
351
352         va_start(args, fmt);
353
354         vaf.fmt = fmt;
355         vaf.va = &args;
356
357         printk(KERN_INFO "b43-%s: %pV",
358                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
359
360         va_end(args);
361 }
362
363 void b43err(struct b43_wl *wl, const char *fmt, ...)
364 {
365         struct va_format vaf;
366         va_list args;
367
368         if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
369                 return;
370         if (!b43_ratelimit(wl))
371                 return;
372
373         va_start(args, fmt);
374
375         vaf.fmt = fmt;
376         vaf.va = &args;
377
378         printk(KERN_ERR "b43-%s ERROR: %pV",
379                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
380
381         va_end(args);
382 }
383
384 void b43warn(struct b43_wl *wl, const char *fmt, ...)
385 {
386         struct va_format vaf;
387         va_list args;
388
389         if (b43_modparam_verbose < B43_VERBOSITY_WARN)
390                 return;
391         if (!b43_ratelimit(wl))
392                 return;
393
394         va_start(args, fmt);
395
396         vaf.fmt = fmt;
397         vaf.va = &args;
398
399         printk(KERN_WARNING "b43-%s warning: %pV",
400                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
401
402         va_end(args);
403 }
404
405 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
406 {
407         struct va_format vaf;
408         va_list args;
409
410         if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
411                 return;
412
413         va_start(args, fmt);
414
415         vaf.fmt = fmt;
416         vaf.va = &args;
417
418         printk(KERN_DEBUG "b43-%s debug: %pV",
419                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
420
421         va_end(args);
422 }
423
424 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
425 {
426         u32 macctl;
427
428         B43_WARN_ON(offset % 4 != 0);
429
430         macctl = b43_read32(dev, B43_MMIO_MACCTL);
431         if (macctl & B43_MACCTL_BE)
432                 val = swab32(val);
433
434         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
435         mmiowb();
436         b43_write32(dev, B43_MMIO_RAM_DATA, val);
437 }
438
439 static inline void b43_shm_control_word(struct b43_wldev *dev,
440                                         u16 routing, u16 offset)
441 {
442         u32 control;
443
444         /* "offset" is the WORD offset. */
445         control = routing;
446         control <<= 16;
447         control |= offset;
448         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
449 }
450
451 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
452 {
453         u32 ret;
454
455         if (routing == B43_SHM_SHARED) {
456                 B43_WARN_ON(offset & 0x0001);
457                 if (offset & 0x0003) {
458                         /* Unaligned access */
459                         b43_shm_control_word(dev, routing, offset >> 2);
460                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
461                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
462                         ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
463
464                         goto out;
465                 }
466                 offset >>= 2;
467         }
468         b43_shm_control_word(dev, routing, offset);
469         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
470 out:
471         return ret;
472 }
473
474 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
475 {
476         u16 ret;
477
478         if (routing == B43_SHM_SHARED) {
479                 B43_WARN_ON(offset & 0x0001);
480                 if (offset & 0x0003) {
481                         /* Unaligned access */
482                         b43_shm_control_word(dev, routing, offset >> 2);
483                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
484
485                         goto out;
486                 }
487                 offset >>= 2;
488         }
489         b43_shm_control_word(dev, routing, offset);
490         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
491 out:
492         return ret;
493 }
494
495 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
496 {
497         if (routing == B43_SHM_SHARED) {
498                 B43_WARN_ON(offset & 0x0001);
499                 if (offset & 0x0003) {
500                         /* Unaligned access */
501                         b43_shm_control_word(dev, routing, offset >> 2);
502                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
503                                     value & 0xFFFF);
504                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
505                         b43_write16(dev, B43_MMIO_SHM_DATA,
506                                     (value >> 16) & 0xFFFF);
507                         return;
508                 }
509                 offset >>= 2;
510         }
511         b43_shm_control_word(dev, routing, offset);
512         b43_write32(dev, B43_MMIO_SHM_DATA, value);
513 }
514
515 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
516 {
517         if (routing == B43_SHM_SHARED) {
518                 B43_WARN_ON(offset & 0x0001);
519                 if (offset & 0x0003) {
520                         /* Unaligned access */
521                         b43_shm_control_word(dev, routing, offset >> 2);
522                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
523                         return;
524                 }
525                 offset >>= 2;
526         }
527         b43_shm_control_word(dev, routing, offset);
528         b43_write16(dev, B43_MMIO_SHM_DATA, value);
529 }
530
531 /* Read HostFlags */
532 u64 b43_hf_read(struct b43_wldev *dev)
533 {
534         u64 ret;
535
536         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
537         ret <<= 16;
538         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
539         ret <<= 16;
540         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
541
542         return ret;
543 }
544
545 /* Write HostFlags */
546 void b43_hf_write(struct b43_wldev *dev, u64 value)
547 {
548         u16 lo, mi, hi;
549
550         lo = (value & 0x00000000FFFFULL);
551         mi = (value & 0x0000FFFF0000ULL) >> 16;
552         hi = (value & 0xFFFF00000000ULL) >> 32;
553         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
554         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
555         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
556 }
557
558 /* Read the firmware capabilities bitmask (Opensource firmware only) */
559 static u16 b43_fwcapa_read(struct b43_wldev *dev)
560 {
561         B43_WARN_ON(!dev->fw.opensource);
562         return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
563 }
564
565 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
566 {
567         u32 low, high;
568
569         B43_WARN_ON(dev->dev->core_rev < 3);
570
571         /* The hardware guarantees us an atomic read, if we
572          * read the low register first. */
573         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
574         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
575
576         *tsf = high;
577         *tsf <<= 32;
578         *tsf |= low;
579 }
580
581 static void b43_time_lock(struct b43_wldev *dev)
582 {
583         b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
584         /* Commit the write */
585         b43_read32(dev, B43_MMIO_MACCTL);
586 }
587
588 static void b43_time_unlock(struct b43_wldev *dev)
589 {
590         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
591         /* Commit the write */
592         b43_read32(dev, B43_MMIO_MACCTL);
593 }
594
595 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
596 {
597         u32 low, high;
598
599         B43_WARN_ON(dev->dev->core_rev < 3);
600
601         low = tsf;
602         high = (tsf >> 32);
603         /* The hardware guarantees us an atomic write, if we
604          * write the low register first. */
605         b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
606         mmiowb();
607         b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
608         mmiowb();
609 }
610
611 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
612 {
613         b43_time_lock(dev);
614         b43_tsf_write_locked(dev, tsf);
615         b43_time_unlock(dev);
616 }
617
618 static
619 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
620 {
621         static const u8 zero_addr[ETH_ALEN] = { 0 };
622         u16 data;
623
624         if (!mac)
625                 mac = zero_addr;
626
627         offset |= 0x0020;
628         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
629
630         data = mac[0];
631         data |= mac[1] << 8;
632         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
633         data = mac[2];
634         data |= mac[3] << 8;
635         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
636         data = mac[4];
637         data |= mac[5] << 8;
638         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
639 }
640
641 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
642 {
643         const u8 *mac;
644         const u8 *bssid;
645         u8 mac_bssid[ETH_ALEN * 2];
646         int i;
647         u32 tmp;
648
649         bssid = dev->wl->bssid;
650         mac = dev->wl->mac_addr;
651
652         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
653
654         memcpy(mac_bssid, mac, ETH_ALEN);
655         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
656
657         /* Write our MAC address and BSSID to template ram */
658         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
659                 tmp = (u32) (mac_bssid[i + 0]);
660                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
661                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
662                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
663                 b43_ram_write(dev, 0x20 + i, tmp);
664         }
665 }
666
667 static void b43_upload_card_macaddress(struct b43_wldev *dev)
668 {
669         b43_write_mac_bssid_templates(dev);
670         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
671 }
672
673 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
674 {
675         /* slot_time is in usec. */
676         /* This test used to exit for all but a G PHY. */
677         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
678                 return;
679         b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
680         /* Shared memory location 0x0010 is the slot time and should be
681          * set to slot_time; however, this register is initially 0 and changing
682          * the value adversely affects the transmit rate for BCM4311
683          * devices. Until this behavior is unterstood, delete this step
684          *
685          * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
686          */
687 }
688
689 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
690 {
691         b43_set_slot_time(dev, 9);
692 }
693
694 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
695 {
696         b43_set_slot_time(dev, 20);
697 }
698
699 /* DummyTransmission function, as documented on
700  * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
701  */
702 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
703 {
704         struct b43_phy *phy = &dev->phy;
705         unsigned int i, max_loop;
706         u16 value;
707         u32 buffer[5] = {
708                 0x00000000,
709                 0x00D40000,
710                 0x00000000,
711                 0x01000000,
712                 0x00000000,
713         };
714
715         if (ofdm) {
716                 max_loop = 0x1E;
717                 buffer[0] = 0x000201CC;
718         } else {
719                 max_loop = 0xFA;
720                 buffer[0] = 0x000B846E;
721         }
722
723         for (i = 0; i < 5; i++)
724                 b43_ram_write(dev, i * 4, buffer[i]);
725
726         b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
727
728         if (dev->dev->core_rev < 11)
729                 b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
730         else
731                 b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
732
733         value = (ofdm ? 0x41 : 0x40);
734         b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
735         if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
736             phy->type == B43_PHYTYPE_LCN)
737                 b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
738
739         b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
740         b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
741
742         b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
743         b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
744         b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
745         b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
746
747         if (!pa_on && phy->type == B43_PHYTYPE_N)
748                 ; /*b43_nphy_pa_override(dev, false) */
749
750         switch (phy->type) {
751         case B43_PHYTYPE_N:
752         case B43_PHYTYPE_LCN:
753                 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
754                 break;
755         case B43_PHYTYPE_LP:
756                 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
757                 break;
758         default:
759                 b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
760         }
761         b43_read16(dev, B43_MMIO_TXE0_AUX);
762
763         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
764                 b43_radio_write16(dev, 0x0051, 0x0017);
765         for (i = 0x00; i < max_loop; i++) {
766                 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
767                 if (value & 0x0080)
768                         break;
769                 udelay(10);
770         }
771         for (i = 0x00; i < 0x0A; i++) {
772                 value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
773                 if (value & 0x0400)
774                         break;
775                 udelay(10);
776         }
777         for (i = 0x00; i < 0x19; i++) {
778                 value = b43_read16(dev, B43_MMIO_IFSSTAT);
779                 if (!(value & 0x0100))
780                         break;
781                 udelay(10);
782         }
783         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
784                 b43_radio_write16(dev, 0x0051, 0x0037);
785 }
786
787 static void key_write(struct b43_wldev *dev,
788                       u8 index, u8 algorithm, const u8 *key)
789 {
790         unsigned int i;
791         u32 offset;
792         u16 value;
793         u16 kidx;
794
795         /* Key index/algo block */
796         kidx = b43_kidx_to_fw(dev, index);
797         value = ((kidx << 4) | algorithm);
798         b43_shm_write16(dev, B43_SHM_SHARED,
799                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
800
801         /* Write the key to the Key Table Pointer offset */
802         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
803         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
804                 value = key[i];
805                 value |= (u16) (key[i + 1]) << 8;
806                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
807         }
808 }
809
810 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
811 {
812         u32 addrtmp[2] = { 0, 0, };
813         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
814
815         if (b43_new_kidx_api(dev))
816                 pairwise_keys_start = B43_NR_GROUP_KEYS;
817
818         B43_WARN_ON(index < pairwise_keys_start);
819         /* We have four default TX keys and possibly four default RX keys.
820          * Physical mac 0 is mapped to physical key 4 or 8, depending
821          * on the firmware version.
822          * So we must adjust the index here.
823          */
824         index -= pairwise_keys_start;
825         B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
826
827         if (addr) {
828                 addrtmp[0] = addr[0];
829                 addrtmp[0] |= ((u32) (addr[1]) << 8);
830                 addrtmp[0] |= ((u32) (addr[2]) << 16);
831                 addrtmp[0] |= ((u32) (addr[3]) << 24);
832                 addrtmp[1] = addr[4];
833                 addrtmp[1] |= ((u32) (addr[5]) << 8);
834         }
835
836         /* Receive match transmitter address (RCMTA) mechanism */
837         b43_shm_write32(dev, B43_SHM_RCMTA,
838                         (index * 2) + 0, addrtmp[0]);
839         b43_shm_write16(dev, B43_SHM_RCMTA,
840                         (index * 2) + 1, addrtmp[1]);
841 }
842
843 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
844  * When a packet is received, the iv32 is checked.
845  * - if it doesn't the packet is returned without modification (and software
846  *   decryption can be done). That's what happen when iv16 wrap.
847  * - if it does, the rc4 key is computed, and decryption is tried.
848  *   Either it will success and B43_RX_MAC_DEC is returned,
849  *   either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
850  *   and the packet is not usable (it got modified by the ucode).
851  * So in order to never have B43_RX_MAC_DECERR, we should provide
852  * a iv32 and phase1key that match. Because we drop packets in case of
853  * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
854  * packets will be lost without higher layer knowing (ie no resync possible
855  * until next wrap).
856  *
857  * NOTE : this should support 50 key like RCMTA because
858  * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
859  */
860 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
861                 u16 *phase1key)
862 {
863         unsigned int i;
864         u32 offset;
865         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
866
867         if (!modparam_hwtkip)
868                 return;
869
870         if (b43_new_kidx_api(dev))
871                 pairwise_keys_start = B43_NR_GROUP_KEYS;
872
873         B43_WARN_ON(index < pairwise_keys_start);
874         /* We have four default TX keys and possibly four default RX keys.
875          * Physical mac 0 is mapped to physical key 4 or 8, depending
876          * on the firmware version.
877          * So we must adjust the index here.
878          */
879         index -= pairwise_keys_start;
880         B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
881
882         if (b43_debug(dev, B43_DBG_KEYS)) {
883                 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
884                                 index, iv32);
885         }
886         /* Write the key to the  RX tkip shared mem */
887         offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
888         for (i = 0; i < 10; i += 2) {
889                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
890                                 phase1key ? phase1key[i / 2] : 0);
891         }
892         b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
893         b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
894 }
895
896 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
897                                    struct ieee80211_vif *vif,
898                                    struct ieee80211_key_conf *keyconf,
899                                    struct ieee80211_sta *sta,
900                                    u32 iv32, u16 *phase1key)
901 {
902         struct b43_wl *wl = hw_to_b43_wl(hw);
903         struct b43_wldev *dev;
904         int index = keyconf->hw_key_idx;
905
906         if (B43_WARN_ON(!modparam_hwtkip))
907                 return;
908
909         /* This is only called from the RX path through mac80211, where
910          * our mutex is already locked. */
911         B43_WARN_ON(!mutex_is_locked(&wl->mutex));
912         dev = wl->current_dev;
913         B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
914
915         keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
916
917         rx_tkip_phase1_write(dev, index, iv32, phase1key);
918         /* only pairwise TKIP keys are supported right now */
919         if (WARN_ON(!sta))
920                 return;
921         keymac_write(dev, index, sta->addr);
922 }
923
924 static void do_key_write(struct b43_wldev *dev,
925                          u8 index, u8 algorithm,
926                          const u8 *key, size_t key_len, const u8 *mac_addr)
927 {
928         u8 buf[B43_SEC_KEYSIZE] = { 0, };
929         u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
930
931         if (b43_new_kidx_api(dev))
932                 pairwise_keys_start = B43_NR_GROUP_KEYS;
933
934         B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
935         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
936
937         if (index >= pairwise_keys_start)
938                 keymac_write(dev, index, NULL); /* First zero out mac. */
939         if (algorithm == B43_SEC_ALGO_TKIP) {
940                 /*
941                  * We should provide an initial iv32, phase1key pair.
942                  * We could start with iv32=0 and compute the corresponding
943                  * phase1key, but this means calling ieee80211_get_tkip_key
944                  * with a fake skb (or export other tkip function).
945                  * Because we are lazy we hope iv32 won't start with
946                  * 0xffffffff and let's b43_op_update_tkip_key provide a
947                  * correct pair.
948                  */
949                 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
950         } else if (index >= pairwise_keys_start) /* clear it */
951                 rx_tkip_phase1_write(dev, index, 0, NULL);
952         if (key)
953                 memcpy(buf, key, key_len);
954         key_write(dev, index, algorithm, buf);
955         if (index >= pairwise_keys_start)
956                 keymac_write(dev, index, mac_addr);
957
958         dev->key[index].algorithm = algorithm;
959 }
960
961 static int b43_key_write(struct b43_wldev *dev,
962                          int index, u8 algorithm,
963                          const u8 *key, size_t key_len,
964                          const u8 *mac_addr,
965                          struct ieee80211_key_conf *keyconf)
966 {
967         int i;
968         int pairwise_keys_start;
969
970         /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
971          *      - Temporal Encryption Key (128 bits)
972          *      - Temporal Authenticator Tx MIC Key (64 bits)
973          *      - Temporal Authenticator Rx MIC Key (64 bits)
974          *
975          *      Hardware only store TEK
976          */
977         if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
978                 key_len = 16;
979         if (key_len > B43_SEC_KEYSIZE)
980                 return -EINVAL;
981         for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
982                 /* Check that we don't already have this key. */
983                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
984         }
985         if (index < 0) {
986                 /* Pairwise key. Get an empty slot for the key. */
987                 if (b43_new_kidx_api(dev))
988                         pairwise_keys_start = B43_NR_GROUP_KEYS;
989                 else
990                         pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
991                 for (i = pairwise_keys_start;
992                      i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
993                      i++) {
994                         B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
995                         if (!dev->key[i].keyconf) {
996                                 /* found empty */
997                                 index = i;
998                                 break;
999                         }
1000                 }
1001                 if (index < 0) {
1002                         b43warn(dev->wl, "Out of hardware key memory\n");
1003                         return -ENOSPC;
1004                 }
1005         } else
1006                 B43_WARN_ON(index > 3);
1007
1008         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
1009         if ((index <= 3) && !b43_new_kidx_api(dev)) {
1010                 /* Default RX key */
1011                 B43_WARN_ON(mac_addr);
1012                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
1013         }
1014         keyconf->hw_key_idx = index;
1015         dev->key[index].keyconf = keyconf;
1016
1017         return 0;
1018 }
1019
1020 static int b43_key_clear(struct b43_wldev *dev, int index)
1021 {
1022         if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1023                 return -EINVAL;
1024         do_key_write(dev, index, B43_SEC_ALGO_NONE,
1025                      NULL, B43_SEC_KEYSIZE, NULL);
1026         if ((index <= 3) && !b43_new_kidx_api(dev)) {
1027                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1028                              NULL, B43_SEC_KEYSIZE, NULL);
1029         }
1030         dev->key[index].keyconf = NULL;
1031
1032         return 0;
1033 }
1034
1035 static void b43_clear_keys(struct b43_wldev *dev)
1036 {
1037         int i, count;
1038
1039         if (b43_new_kidx_api(dev))
1040                 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1041         else
1042                 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1043         for (i = 0; i < count; i++)
1044                 b43_key_clear(dev, i);
1045 }
1046
1047 static void b43_dump_keymemory(struct b43_wldev *dev)
1048 {
1049         unsigned int i, index, count, offset, pairwise_keys_start;
1050         u8 mac[ETH_ALEN];
1051         u16 algo;
1052         u32 rcmta0;
1053         u16 rcmta1;
1054         u64 hf;
1055         struct b43_key *key;
1056
1057         if (!b43_debug(dev, B43_DBG_KEYS))
1058                 return;
1059
1060         hf = b43_hf_read(dev);
1061         b43dbg(dev->wl, "Hardware key memory dump:  USEDEFKEYS=%u\n",
1062                !!(hf & B43_HF_USEDEFKEYS));
1063         if (b43_new_kidx_api(dev)) {
1064                 pairwise_keys_start = B43_NR_GROUP_KEYS;
1065                 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1066         } else {
1067                 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1068                 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1069         }
1070         for (index = 0; index < count; index++) {
1071                 key = &(dev->key[index]);
1072                 printk(KERN_DEBUG "Key slot %02u: %s",
1073                        index, (key->keyconf == NULL) ? " " : "*");
1074                 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1075                 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1076                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1077                         printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1078                 }
1079
1080                 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1081                                       B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1082                 printk("   Algo: %04X/%02X", algo, key->algorithm);
1083
1084                 if (index >= pairwise_keys_start) {
1085                         if (key->algorithm == B43_SEC_ALGO_TKIP) {
1086                                 printk("   TKIP: ");
1087                                 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1088                                 for (i = 0; i < 14; i += 2) {
1089                                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1090                                         printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1091                                 }
1092                         }
1093                         rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1094                                                 ((index - pairwise_keys_start) * 2) + 0);
1095                         rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1096                                                 ((index - pairwise_keys_start) * 2) + 1);
1097                         *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1098                         *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1099                         printk("   MAC: %pM", mac);
1100                 } else
1101                         printk("   DEFAULT KEY");
1102                 printk("\n");
1103         }
1104 }
1105
1106 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1107 {
1108         u32 macctl;
1109         u16 ucstat;
1110         bool hwps;
1111         bool awake;
1112         int i;
1113
1114         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1115                     (ps_flags & B43_PS_DISABLED));
1116         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1117
1118         if (ps_flags & B43_PS_ENABLED) {
1119                 hwps = true;
1120         } else if (ps_flags & B43_PS_DISABLED) {
1121                 hwps = false;
1122         } else {
1123                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1124                 //      and thus is not an AP and we are associated, set bit 25
1125         }
1126         if (ps_flags & B43_PS_AWAKE) {
1127                 awake = true;
1128         } else if (ps_flags & B43_PS_ASLEEP) {
1129                 awake = false;
1130         } else {
1131                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1132                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
1133                 //      successful, set bit26
1134         }
1135
1136 /* FIXME: For now we force awake-on and hwps-off */
1137         hwps = false;
1138         awake = true;
1139
1140         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1141         if (hwps)
1142                 macctl |= B43_MACCTL_HWPS;
1143         else
1144                 macctl &= ~B43_MACCTL_HWPS;
1145         if (awake)
1146                 macctl |= B43_MACCTL_AWAKE;
1147         else
1148                 macctl &= ~B43_MACCTL_AWAKE;
1149         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1150         /* Commit write */
1151         b43_read32(dev, B43_MMIO_MACCTL);
1152         if (awake && dev->dev->core_rev >= 5) {
1153                 /* Wait for the microcode to wake up. */
1154                 for (i = 0; i < 100; i++) {
1155                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1156                                                 B43_SHM_SH_UCODESTAT);
1157                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1158                                 break;
1159                         udelay(10);
1160                 }
1161         }
1162 }
1163
1164 #ifdef CONFIG_B43_BCMA
1165 static void b43_bcma_phy_reset(struct b43_wldev *dev)
1166 {
1167         u32 flags;
1168
1169         /* Put PHY into reset */
1170         flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1171         flags |= B43_BCMA_IOCTL_PHY_RESET;
1172         flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1173         bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1174         udelay(2);
1175
1176         /* Take PHY out of reset */
1177         flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1178         flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1179         flags |= BCMA_IOCTL_FGC;
1180         bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1181         udelay(1);
1182
1183         /* Do not force clock anymore */
1184         flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1185         flags &= ~BCMA_IOCTL_FGC;
1186         bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1187         udelay(1);
1188 }
1189
1190 static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1191 {
1192         b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1193         bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1194         b43_bcma_phy_reset(dev);
1195         bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
1196 }
1197 #endif
1198
1199 static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1200 {
1201         struct ssb_device *sdev = dev->dev->sdev;
1202         u32 tmslow;
1203         u32 flags = 0;
1204
1205         if (gmode)
1206                 flags |= B43_TMSLOW_GMODE;
1207         flags |= B43_TMSLOW_PHYCLKEN;
1208         flags |= B43_TMSLOW_PHYRESET;
1209         if (dev->phy.type == B43_PHYTYPE_N)
1210                 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1211         b43_device_enable(dev, flags);
1212         msleep(2);              /* Wait for the PLL to turn on. */
1213
1214         /* Now take the PHY out of Reset again */
1215         tmslow = ssb_read32(sdev, SSB_TMSLOW);
1216         tmslow |= SSB_TMSLOW_FGC;
1217         tmslow &= ~B43_TMSLOW_PHYRESET;
1218         ssb_write32(sdev, SSB_TMSLOW, tmslow);
1219         ssb_read32(sdev, SSB_TMSLOW);   /* flush */
1220         msleep(1);
1221         tmslow &= ~SSB_TMSLOW_FGC;
1222         ssb_write32(sdev, SSB_TMSLOW, tmslow);
1223         ssb_read32(sdev, SSB_TMSLOW);   /* flush */
1224         msleep(1);
1225 }
1226
1227 void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1228 {
1229         u32 macctl;
1230
1231         switch (dev->dev->bus_type) {
1232 #ifdef CONFIG_B43_BCMA
1233         case B43_BUS_BCMA:
1234                 b43_bcma_wireless_core_reset(dev, gmode);
1235                 break;
1236 #endif
1237 #ifdef CONFIG_B43_SSB
1238         case B43_BUS_SSB:
1239                 b43_ssb_wireless_core_reset(dev, gmode);
1240                 break;
1241 #endif
1242         }
1243
1244         /* Turn Analog ON, but only if we already know the PHY-type.
1245          * This protects against very early setup where we don't know the
1246          * PHY-type, yet. wireless_core_reset will be called once again later,
1247          * when we know the PHY-type. */
1248         if (dev->phy.ops)
1249                 dev->phy.ops->switch_analog(dev, 1);
1250
1251         macctl = b43_read32(dev, B43_MMIO_MACCTL);
1252         macctl &= ~B43_MACCTL_GMODE;
1253         if (gmode)
1254                 macctl |= B43_MACCTL_GMODE;
1255         macctl |= B43_MACCTL_IHR_ENABLED;
1256         b43_write32(dev, B43_MMIO_MACCTL, macctl);
1257 }
1258
1259 static void handle_irq_transmit_status(struct b43_wldev *dev)
1260 {
1261         u32 v0, v1;
1262         u16 tmp;
1263         struct b43_txstatus stat;
1264
1265         while (1) {
1266                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1267                 if (!(v0 & 0x00000001))
1268                         break;
1269                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1270
1271                 stat.cookie = (v0 >> 16);
1272                 stat.seq = (v1 & 0x0000FFFF);
1273                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1274                 tmp = (v0 & 0x0000FFFF);
1275                 stat.frame_count = ((tmp & 0xF000) >> 12);
1276                 stat.rts_count = ((tmp & 0x0F00) >> 8);
1277                 stat.supp_reason = ((tmp & 0x001C) >> 2);
1278                 stat.pm_indicated = !!(tmp & 0x0080);
1279                 stat.intermediate = !!(tmp & 0x0040);
1280                 stat.for_ampdu = !!(tmp & 0x0020);
1281                 stat.acked = !!(tmp & 0x0002);
1282
1283                 b43_handle_txstatus(dev, &stat);
1284         }
1285 }
1286
1287 static void drain_txstatus_queue(struct b43_wldev *dev)
1288 {
1289         u32 dummy;
1290
1291         if (dev->dev->core_rev < 5)
1292                 return;
1293         /* Read all entries from the microcode TXstatus FIFO
1294          * and throw them away.
1295          */
1296         while (1) {
1297                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1298                 if (!(dummy & 0x00000001))
1299                         break;
1300                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1301         }
1302 }
1303
1304 static u32 b43_jssi_read(struct b43_wldev *dev)
1305 {
1306         u32 val = 0;
1307
1308         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1309         val <<= 16;
1310         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1311
1312         return val;
1313 }
1314
1315 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1316 {
1317         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1318         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1319 }
1320
1321 static void b43_generate_noise_sample(struct b43_wldev *dev)
1322 {
1323         b43_jssi_write(dev, 0x7F7F7F7F);
1324         b43_write32(dev, B43_MMIO_MACCMD,
1325                     b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1326 }
1327
1328 static void b43_calculate_link_quality(struct b43_wldev *dev)
1329 {
1330         /* Top half of Link Quality calculation. */
1331
1332         if (dev->phy.type != B43_PHYTYPE_G)
1333                 return;
1334         if (dev->noisecalc.calculation_running)
1335                 return;
1336         dev->noisecalc.calculation_running = true;
1337         dev->noisecalc.nr_samples = 0;
1338
1339         b43_generate_noise_sample(dev);
1340 }
1341
1342 static void handle_irq_noise(struct b43_wldev *dev)
1343 {
1344         struct b43_phy_g *phy = dev->phy.g;
1345         u16 tmp;
1346         u8 noise[4];
1347         u8 i, j;
1348         s32 average;
1349
1350         /* Bottom half of Link Quality calculation. */
1351
1352         if (dev->phy.type != B43_PHYTYPE_G)
1353                 return;
1354
1355         /* Possible race condition: It might be possible that the user
1356          * changed to a different channel in the meantime since we
1357          * started the calculation. We ignore that fact, since it's
1358          * not really that much of a problem. The background noise is
1359          * an estimation only anyway. Slightly wrong results will get damped
1360          * by the averaging of the 8 sample rounds. Additionally the
1361          * value is shortlived. So it will be replaced by the next noise
1362          * calculation round soon. */
1363
1364         B43_WARN_ON(!dev->noisecalc.calculation_running);
1365         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1366         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1367             noise[2] == 0x7F || noise[3] == 0x7F)
1368                 goto generate_new;
1369
1370         /* Get the noise samples. */
1371         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1372         i = dev->noisecalc.nr_samples;
1373         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1374         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1375         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1376         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1377         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1378         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1379         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1380         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1381         dev->noisecalc.nr_samples++;
1382         if (dev->noisecalc.nr_samples == 8) {
1383                 /* Calculate the Link Quality by the noise samples. */
1384                 average = 0;
1385                 for (i = 0; i < 8; i++) {
1386                         for (j = 0; j < 4; j++)
1387                                 average += dev->noisecalc.samples[i][j];
1388                 }
1389                 average /= (8 * 4);
1390                 average *= 125;
1391                 average += 64;
1392                 average /= 128;
1393                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1394                 tmp = (tmp / 128) & 0x1F;
1395                 if (tmp >= 8)
1396                         average += 2;
1397                 else
1398                         average -= 25;
1399                 if (tmp == 8)
1400                         average -= 72;
1401                 else
1402                         average -= 48;
1403
1404                 dev->stats.link_noise = average;
1405                 dev->noisecalc.calculation_running = false;
1406                 return;
1407         }
1408 generate_new:
1409         b43_generate_noise_sample(dev);
1410 }
1411
1412 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1413 {
1414         if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1415                 ///TODO: PS TBTT
1416         } else {
1417                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1418                         b43_power_saving_ctl_bits(dev, 0);
1419         }
1420         if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1421                 dev->dfq_valid = true;
1422 }
1423
1424 static void handle_irq_atim_end(struct b43_wldev *dev)
1425 {
1426         if (dev->dfq_valid) {
1427                 b43_write32(dev, B43_MMIO_MACCMD,
1428                             b43_read32(dev, B43_MMIO_MACCMD)
1429                             | B43_MACCMD_DFQ_VALID);
1430                 dev->dfq_valid = false;
1431         }
1432 }
1433
1434 static void handle_irq_pmq(struct b43_wldev *dev)
1435 {
1436         u32 tmp;
1437
1438         //TODO: AP mode.
1439
1440         while (1) {
1441                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1442                 if (!(tmp & 0x00000008))
1443                         break;
1444         }
1445         /* 16bit write is odd, but correct. */
1446         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1447 }
1448
1449 static void b43_write_template_common(struct b43_wldev *dev,
1450                                       const u8 *data, u16 size,
1451                                       u16 ram_offset,
1452                                       u16 shm_size_offset, u8 rate)
1453 {
1454         u32 i, tmp;
1455         struct b43_plcp_hdr4 plcp;
1456
1457         plcp.data = 0;
1458         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1459         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1460         ram_offset += sizeof(u32);
1461         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1462          * So leave the first two bytes of the next write blank.
1463          */
1464         tmp = (u32) (data[0]) << 16;
1465         tmp |= (u32) (data[1]) << 24;
1466         b43_ram_write(dev, ram_offset, tmp);
1467         ram_offset += sizeof(u32);
1468         for (i = 2; i < size; i += sizeof(u32)) {
1469                 tmp = (u32) (data[i + 0]);
1470                 if (i + 1 < size)
1471                         tmp |= (u32) (data[i + 1]) << 8;
1472                 if (i + 2 < size)
1473                         tmp |= (u32) (data[i + 2]) << 16;
1474                 if (i + 3 < size)
1475                         tmp |= (u32) (data[i + 3]) << 24;
1476                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1477         }
1478         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1479                         size + sizeof(struct b43_plcp_hdr6));
1480 }
1481
1482 /* Check if the use of the antenna that ieee80211 told us to
1483  * use is possible. This will fall back to DEFAULT.
1484  * "antenna_nr" is the antenna identifier we got from ieee80211. */
1485 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1486                                   u8 antenna_nr)
1487 {
1488         u8 antenna_mask;
1489
1490         if (antenna_nr == 0) {
1491                 /* Zero means "use default antenna". That's always OK. */
1492                 return 0;
1493         }
1494
1495         /* Get the mask of available antennas. */
1496         if (dev->phy.gmode)
1497                 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1498         else
1499                 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1500
1501         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1502                 /* This antenna is not available. Fall back to default. */
1503                 return 0;
1504         }
1505
1506         return antenna_nr;
1507 }
1508
1509 /* Convert a b43 antenna number value to the PHY TX control value. */
1510 static u16 b43_antenna_to_phyctl(int antenna)
1511 {
1512         switch (antenna) {
1513         case B43_ANTENNA0:
1514                 return B43_TXH_PHY_ANT0;
1515         case B43_ANTENNA1:
1516                 return B43_TXH_PHY_ANT1;
1517         case B43_ANTENNA2:
1518                 return B43_TXH_PHY_ANT2;
1519         case B43_ANTENNA3:
1520                 return B43_TXH_PHY_ANT3;
1521         case B43_ANTENNA_AUTO0:
1522         case B43_ANTENNA_AUTO1:
1523                 return B43_TXH_PHY_ANT01AUTO;
1524         }
1525         B43_WARN_ON(1);
1526         return 0;
1527 }
1528
1529 static void b43_write_beacon_template(struct b43_wldev *dev,
1530                                       u16 ram_offset,
1531                                       u16 shm_size_offset)
1532 {
1533         unsigned int i, len, variable_len;
1534         const struct ieee80211_mgmt *bcn;
1535         const u8 *ie;
1536         bool tim_found = false;
1537         unsigned int rate;
1538         u16 ctl;
1539         int antenna;
1540         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1541
1542         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1543         len = min((size_t) dev->wl->current_beacon->len,
1544                   0x200 - sizeof(struct b43_plcp_hdr6));
1545         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1546
1547         b43_write_template_common(dev, (const u8 *)bcn,
1548                                   len, ram_offset, shm_size_offset, rate);
1549
1550         /* Write the PHY TX control parameters. */
1551         antenna = B43_ANTENNA_DEFAULT;
1552         antenna = b43_antenna_to_phyctl(antenna);
1553         ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1554         /* We can't send beacons with short preamble. Would get PHY errors. */
1555         ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1556         ctl &= ~B43_TXH_PHY_ANT;
1557         ctl &= ~B43_TXH_PHY_ENC;
1558         ctl |= antenna;
1559         if (b43_is_cck_rate(rate))
1560                 ctl |= B43_TXH_PHY_ENC_CCK;
1561         else
1562                 ctl |= B43_TXH_PHY_ENC_OFDM;
1563         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1564
1565         /* Find the position of the TIM and the DTIM_period value
1566          * and write them to SHM. */
1567         ie = bcn->u.beacon.variable;
1568         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1569         for (i = 0; i < variable_len - 2; ) {
1570                 uint8_t ie_id, ie_len;
1571
1572                 ie_id = ie[i];
1573                 ie_len = ie[i + 1];
1574                 if (ie_id == 5) {
1575                         u16 tim_position;
1576                         u16 dtim_period;
1577                         /* This is the TIM Information Element */
1578
1579                         /* Check whether the ie_len is in the beacon data range. */
1580                         if (variable_len < ie_len + 2 + i)
1581                                 break;
1582                         /* A valid TIM is at least 4 bytes long. */
1583                         if (ie_len < 4)
1584                                 break;
1585                         tim_found = true;
1586
1587                         tim_position = sizeof(struct b43_plcp_hdr6);
1588                         tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1589                         tim_position += i;
1590
1591                         dtim_period = ie[i + 3];
1592
1593                         b43_shm_write16(dev, B43_SHM_SHARED,
1594                                         B43_SHM_SH_TIMBPOS, tim_position);
1595                         b43_shm_write16(dev, B43_SHM_SHARED,
1596                                         B43_SHM_SH_DTIMPER, dtim_period);
1597                         break;
1598                 }
1599                 i += ie_len + 2;
1600         }
1601         if (!tim_found) {
1602                 /*
1603                  * If ucode wants to modify TIM do it behind the beacon, this
1604                  * will happen, for example, when doing mesh networking.
1605                  */
1606                 b43_shm_write16(dev, B43_SHM_SHARED,
1607                                 B43_SHM_SH_TIMBPOS,
1608                                 len + sizeof(struct b43_plcp_hdr6));
1609                 b43_shm_write16(dev, B43_SHM_SHARED,
1610                                 B43_SHM_SH_DTIMPER, 0);
1611         }
1612         b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1613 }
1614
1615 static void b43_upload_beacon0(struct b43_wldev *dev)
1616 {
1617         struct b43_wl *wl = dev->wl;
1618
1619         if (wl->beacon0_uploaded)
1620                 return;
1621         b43_write_beacon_template(dev, 0x68, 0x18);
1622         wl->beacon0_uploaded = true;
1623 }
1624
1625 static void b43_upload_beacon1(struct b43_wldev *dev)
1626 {
1627         struct b43_wl *wl = dev->wl;
1628
1629         if (wl->beacon1_uploaded)
1630                 return;
1631         b43_write_beacon_template(dev, 0x468, 0x1A);
1632         wl->beacon1_uploaded = true;
1633 }
1634
1635 static void handle_irq_beacon(struct b43_wldev *dev)
1636 {
1637         struct b43_wl *wl = dev->wl;
1638         u32 cmd, beacon0_valid, beacon1_valid;
1639
1640         if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1641             !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
1642             !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
1643                 return;
1644
1645         /* This is the bottom half of the asynchronous beacon update. */
1646
1647         /* Ignore interrupt in the future. */
1648         dev->irq_mask &= ~B43_IRQ_BEACON;
1649
1650         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1651         beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1652         beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1653
1654         /* Schedule interrupt manually, if busy. */
1655         if (beacon0_valid && beacon1_valid) {
1656                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1657                 dev->irq_mask |= B43_IRQ_BEACON;
1658                 return;
1659         }
1660
1661         if (unlikely(wl->beacon_templates_virgin)) {
1662                 /* We never uploaded a beacon before.
1663                  * Upload both templates now, but only mark one valid. */
1664                 wl->beacon_templates_virgin = false;
1665                 b43_upload_beacon0(dev);
1666                 b43_upload_beacon1(dev);
1667                 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1668                 cmd |= B43_MACCMD_BEACON0_VALID;
1669                 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1670         } else {
1671                 if (!beacon0_valid) {
1672                         b43_upload_beacon0(dev);
1673                         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1674                         cmd |= B43_MACCMD_BEACON0_VALID;
1675                         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1676                 } else if (!beacon1_valid) {
1677                         b43_upload_beacon1(dev);
1678                         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1679                         cmd |= B43_MACCMD_BEACON1_VALID;
1680                         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1681                 }
1682         }
1683 }
1684
1685 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1686 {
1687         u32 old_irq_mask = dev->irq_mask;
1688
1689         /* update beacon right away or defer to irq */
1690         handle_irq_beacon(dev);
1691         if (old_irq_mask != dev->irq_mask) {
1692                 /* The handler updated the IRQ mask. */
1693                 B43_WARN_ON(!dev->irq_mask);
1694                 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1695                         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1696                 } else {
1697                         /* Device interrupts are currently disabled. That means
1698                          * we just ran the hardirq handler and scheduled the
1699                          * IRQ thread. The thread will write the IRQ mask when
1700                          * it finished, so there's nothing to do here. Writing
1701                          * the mask _here_ would incorrectly re-enable IRQs. */
1702                 }
1703         }
1704 }
1705
1706 static void b43_beacon_update_trigger_work(struct work_struct *work)
1707 {
1708         struct b43_wl *wl = container_of(work, struct b43_wl,
1709                                          beacon_update_trigger);
1710         struct b43_wldev *dev;
1711
1712         mutex_lock(&wl->mutex);
1713         dev = wl->current_dev;
1714         if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1715                 if (b43_bus_host_is_sdio(dev->dev)) {
1716                         /* wl->mutex is enough. */
1717                         b43_do_beacon_update_trigger_work(dev);
1718                         mmiowb();
1719                 } else {
1720                         spin_lock_irq(&wl->hardirq_lock);
1721                         b43_do_beacon_update_trigger_work(dev);
1722                         mmiowb();
1723                         spin_unlock_irq(&wl->hardirq_lock);
1724                 }
1725         }
1726         mutex_unlock(&wl->mutex);
1727 }
1728
1729 /* Asynchronously update the packet templates in template RAM.
1730  * Locking: Requires wl->mutex to be locked. */
1731 static void b43_update_templates(struct b43_wl *wl)
1732 {
1733         struct sk_buff *beacon;
1734
1735         /* This is the top half of the ansynchronous beacon update.
1736          * The bottom half is the beacon IRQ.
1737          * Beacon update must be asynchronous to avoid sending an
1738          * invalid beacon. This can happen for example, if the firmware
1739          * transmits a beacon while we are updating it. */
1740
1741         /* We could modify the existing beacon and set the aid bit in
1742          * the TIM field, but that would probably require resizing and
1743          * moving of data within the beacon template.
1744          * Simply request a new beacon and let mac80211 do the hard work. */
1745         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1746         if (unlikely(!beacon))
1747                 return;
1748
1749         if (wl->current_beacon)
1750                 dev_kfree_skb_any(wl->current_beacon);
1751         wl->current_beacon = beacon;
1752         wl->beacon0_uploaded = false;
1753         wl->beacon1_uploaded = false;
1754         ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1755 }
1756
1757 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1758 {
1759         b43_time_lock(dev);
1760         if (dev->dev->core_rev >= 3) {
1761                 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1762                 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1763         } else {
1764                 b43_write16(dev, 0x606, (beacon_int >> 6));
1765                 b43_write16(dev, 0x610, beacon_int);
1766         }
1767         b43_time_unlock(dev);
1768         b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1769 }
1770
1771 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1772 {
1773         u16 reason;
1774
1775         /* Read the register that contains the reason code for the panic. */
1776         reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1777         b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1778
1779         switch (reason) {
1780         default:
1781                 b43dbg(dev->wl, "The panic reason is unknown.\n");
1782                 /* fallthrough */
1783         case B43_FWPANIC_DIE:
1784                 /* Do not restart the controller or firmware.
1785                  * The device is nonfunctional from now on.
1786                  * Restarting would result in this panic to trigger again,
1787                  * so we avoid that recursion. */
1788                 break;
1789         case B43_FWPANIC_RESTART:
1790                 b43_controller_restart(dev, "Microcode panic");
1791                 break;
1792         }
1793 }
1794
1795 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1796 {
1797         unsigned int i, cnt;
1798         u16 reason, marker_id, marker_line;
1799         __le16 *buf;
1800
1801         /* The proprietary firmware doesn't have this IRQ. */
1802         if (!dev->fw.opensource)
1803                 return;
1804
1805         /* Read the register that contains the reason code for this IRQ. */
1806         reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1807
1808         switch (reason) {
1809         case B43_DEBUGIRQ_PANIC:
1810                 b43_handle_firmware_panic(dev);
1811                 break;
1812         case B43_DEBUGIRQ_DUMP_SHM:
1813                 if (!B43_DEBUG)
1814                         break; /* Only with driver debugging enabled. */
1815                 buf = kmalloc(4096, GFP_ATOMIC);
1816                 if (!buf) {
1817                         b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1818                         goto out;
1819                 }
1820                 for (i = 0; i < 4096; i += 2) {
1821                         u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1822                         buf[i / 2] = cpu_to_le16(tmp);
1823                 }
1824                 b43info(dev->wl, "Shared memory dump:\n");
1825                 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1826                                16, 2, buf, 4096, 1);
1827                 kfree(buf);
1828                 break;
1829         case B43_DEBUGIRQ_DUMP_REGS:
1830                 if (!B43_DEBUG)
1831                         break; /* Only with driver debugging enabled. */
1832                 b43info(dev->wl, "Microcode register dump:\n");
1833                 for (i = 0, cnt = 0; i < 64; i++) {
1834                         u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1835                         if (cnt == 0)
1836                                 printk(KERN_INFO);
1837                         printk("r%02u: 0x%04X  ", i, tmp);
1838                         cnt++;
1839                         if (cnt == 6) {
1840                                 printk("\n");
1841                                 cnt = 0;
1842                         }
1843                 }
1844                 printk("\n");
1845                 break;
1846         case B43_DEBUGIRQ_MARKER:
1847                 if (!B43_DEBUG)
1848                         break; /* Only with driver debugging enabled. */
1849                 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1850                                            B43_MARKER_ID_REG);
1851                 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1852                                              B43_MARKER_LINE_REG);
1853                 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1854                         "at line number %u\n",
1855                         marker_id, marker_line);
1856                 break;
1857         default:
1858                 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1859                        reason);
1860         }
1861 out:
1862         /* Acknowledge the debug-IRQ, so the firmware can continue. */
1863         b43_shm_write16(dev, B43_SHM_SCRATCH,
1864                         B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1865 }
1866
1867 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1868 {
1869         u32 reason;
1870         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1871         u32 merged_dma_reason = 0;
1872         int i;
1873
1874         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1875                 return;
1876
1877         reason = dev->irq_reason;
1878         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1879                 dma_reason[i] = dev->dma_reason[i];
1880                 merged_dma_reason |= dma_reason[i];
1881         }
1882
1883         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1884                 b43err(dev->wl, "MAC transmission error\n");
1885
1886         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1887                 b43err(dev->wl, "PHY transmission error\n");
1888                 rmb();
1889                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1890                         atomic_set(&dev->phy.txerr_cnt,
1891                                    B43_PHY_TX_BADNESS_LIMIT);
1892                         b43err(dev->wl, "Too many PHY TX errors, "
1893                                         "restarting the controller\n");
1894                         b43_controller_restart(dev, "PHY TX errors");
1895                 }
1896         }
1897
1898         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1899                                           B43_DMAIRQ_NONFATALMASK))) {
1900                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1901                         b43err(dev->wl, "Fatal DMA error: "
1902                                "0x%08X, 0x%08X, 0x%08X, "
1903                                "0x%08X, 0x%08X, 0x%08X\n",
1904                                dma_reason[0], dma_reason[1],
1905                                dma_reason[2], dma_reason[3],
1906                                dma_reason[4], dma_reason[5]);
1907                         b43err(dev->wl, "This device does not support DMA "
1908                                "on your system. It will now be switched to PIO.\n");
1909                         /* Fall back to PIO transfers if we get fatal DMA errors! */
1910                         dev->use_pio = true;
1911                         b43_controller_restart(dev, "DMA error");
1912                         return;
1913                 }
1914                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1915                         b43err(dev->wl, "DMA error: "
1916                                "0x%08X, 0x%08X, 0x%08X, "
1917                                "0x%08X, 0x%08X, 0x%08X\n",
1918                                dma_reason[0], dma_reason[1],
1919                                dma_reason[2], dma_reason[3],
1920                                dma_reason[4], dma_reason[5]);
1921                 }
1922         }
1923
1924         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1925                 handle_irq_ucode_debug(dev);
1926         if (reason & B43_IRQ_TBTT_INDI)
1927                 handle_irq_tbtt_indication(dev);
1928         if (reason & B43_IRQ_ATIM_END)
1929                 handle_irq_atim_end(dev);
1930         if (reason & B43_IRQ_BEACON)
1931                 handle_irq_beacon(dev);
1932         if (reason & B43_IRQ_PMQ)
1933                 handle_irq_pmq(dev);
1934         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1935                 ;/* TODO */
1936         if (reason & B43_IRQ_NOISESAMPLE_OK)
1937                 handle_irq_noise(dev);
1938
1939         /* Check the DMA reason registers for received data. */
1940         if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1941                 if (b43_using_pio_transfers(dev))
1942                         b43_pio_rx(dev->pio.rx_queue);
1943                 else
1944                         b43_dma_rx(dev->dma.rx_ring);
1945         }
1946         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1947         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1948         B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1949         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1950         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1951
1952         if (reason & B43_IRQ_TX_OK)
1953                 handle_irq_transmit_status(dev);
1954
1955         /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1956         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1957
1958 #if B43_DEBUG
1959         if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1960                 dev->irq_count++;
1961                 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1962                         if (reason & (1 << i))
1963                                 dev->irq_bit_count[i]++;
1964                 }
1965         }
1966 #endif
1967 }
1968
1969 /* Interrupt thread handler. Handles device interrupts in thread context. */
1970 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1971 {
1972         struct b43_wldev *dev = dev_id;
1973
1974         mutex_lock(&dev->wl->mutex);
1975         b43_do_interrupt_thread(dev);
1976         mmiowb();
1977         mutex_unlock(&dev->wl->mutex);
1978
1979         return IRQ_HANDLED;
1980 }
1981
1982 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1983 {
1984         u32 reason;
1985
1986         /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1987          * On SDIO, this runs under wl->mutex. */
1988
1989         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1990         if (reason == 0xffffffff)       /* shared IRQ */
1991                 return IRQ_NONE;
1992         reason &= dev->irq_mask;
1993         if (!reason)
1994                 return IRQ_NONE;
1995
1996         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1997             & 0x0001DC00;
1998         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1999             & 0x0000DC00;
2000         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
2001             & 0x0000DC00;
2002         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
2003             & 0x0001DC00;
2004         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
2005             & 0x0000DC00;
2006 /* Unused ring
2007         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
2008             & 0x0000DC00;
2009 */
2010
2011         /* ACK the interrupt. */
2012         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
2013         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
2014         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
2015         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
2016         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
2017         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
2018 /* Unused ring
2019         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
2020 */
2021
2022         /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
2023         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
2024         /* Save the reason bitmasks for the IRQ thread handler. */
2025         dev->irq_reason = reason;
2026
2027         return IRQ_WAKE_THREAD;
2028 }
2029
2030 /* Interrupt handler top-half. This runs with interrupts disabled. */
2031 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
2032 {
2033         struct b43_wldev *dev = dev_id;
2034         irqreturn_t ret;
2035
2036         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2037                 return IRQ_NONE;
2038
2039         spin_lock(&dev->wl->hardirq_lock);
2040         ret = b43_do_interrupt(dev);
2041         mmiowb();
2042         spin_unlock(&dev->wl->hardirq_lock);
2043
2044         return ret;
2045 }
2046
2047 /* SDIO interrupt handler. This runs in process context. */
2048 static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
2049 {
2050         struct b43_wl *wl = dev->wl;
2051         irqreturn_t ret;
2052
2053         mutex_lock(&wl->mutex);
2054
2055         ret = b43_do_interrupt(dev);
2056         if (ret == IRQ_WAKE_THREAD)
2057                 b43_do_interrupt_thread(dev);
2058
2059         mutex_unlock(&wl->mutex);
2060 }
2061
2062 void b43_do_release_fw(struct b43_firmware_file *fw)
2063 {
2064         release_firmware(fw->data);
2065         fw->data = NULL;
2066         fw->filename = NULL;
2067 }
2068
2069 static void b43_release_firmware(struct b43_wldev *dev)
2070 {
2071         b43_do_release_fw(&dev->fw.ucode);
2072         b43_do_release_fw(&dev->fw.pcm);
2073         b43_do_release_fw(&dev->fw.initvals);
2074         b43_do_release_fw(&dev->fw.initvals_band);
2075 }
2076
2077 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
2078 {
2079         const char text[] =
2080                 "You must go to " \
2081                 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
2082                 "and download the correct firmware for this driver version. " \
2083                 "Please carefully read all instructions on this website.\n";
2084
2085         if (error)
2086                 b43err(wl, text);
2087         else
2088                 b43warn(wl, text);
2089 }
2090
2091 static void b43_fw_cb(const struct firmware *firmware, void *context)
2092 {
2093         struct b43_request_fw_context *ctx = context;
2094
2095         ctx->blob = firmware;
2096         complete(&ctx->fw_load_complete);
2097 }
2098
2099 int b43_do_request_fw(struct b43_request_fw_context *ctx,
2100                       const char *name,
2101                       struct b43_firmware_file *fw, bool async)
2102 {
2103         struct b43_fw_header *hdr;
2104         u32 size;
2105         int err;
2106
2107         if (!name) {
2108                 /* Don't fetch anything. Free possibly cached firmware. */
2109                 /* FIXME: We should probably keep it anyway, to save some headache
2110                  * on suspend/resume with multiband devices. */
2111                 b43_do_release_fw(fw);
2112                 return 0;
2113         }
2114         if (fw->filename) {
2115                 if ((fw->type == ctx->req_type) &&
2116                     (strcmp(fw->filename, name) == 0))
2117                         return 0; /* Already have this fw. */
2118                 /* Free the cached firmware first. */
2119                 /* FIXME: We should probably do this later after we successfully
2120                  * got the new fw. This could reduce headache with multiband devices.
2121                  * We could also redesign this to cache the firmware for all possible
2122                  * bands all the time. */
2123                 b43_do_release_fw(fw);
2124         }
2125
2126         switch (ctx->req_type) {
2127         case B43_FWTYPE_PROPRIETARY:
2128                 snprintf(ctx->fwname, sizeof(ctx->fwname),
2129                          "b43%s/%s.fw",
2130                          modparam_fwpostfix, name);
2131                 break;
2132         case B43_FWTYPE_OPENSOURCE:
2133                 snprintf(ctx->fwname, sizeof(ctx->fwname),
2134                          "b43-open%s/%s.fw",
2135                          modparam_fwpostfix, name);
2136                 break;
2137         default:
2138                 B43_WARN_ON(1);
2139                 return -ENOSYS;
2140         }
2141         if (async) {
2142                 /* do this part asynchronously */
2143                 init_completion(&ctx->fw_load_complete);
2144                 err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
2145                                               ctx->dev->dev->dev, GFP_KERNEL,
2146                                               ctx, b43_fw_cb);
2147                 if (err < 0) {
2148                         pr_err("Unable to load firmware\n");
2149                         return err;
2150                 }
2151                 /* stall here until fw ready */
2152                 wait_for_completion(&ctx->fw_load_complete);
2153                 if (ctx->blob)
2154                         goto fw_ready;
2155         /* On some ARM systems, the async request will fail, but the next sync
2156          * request works. For this reason, we dall through here
2157          */
2158         }
2159         err = request_firmware(&ctx->blob, ctx->fwname,
2160                                ctx->dev->dev->dev);
2161         if (err == -ENOENT) {
2162                 snprintf(ctx->errors[ctx->req_type],
2163                          sizeof(ctx->errors[ctx->req_type]),
2164                          "Firmware file \"%s\" not found\n",
2165                          ctx->fwname);
2166                 return err;
2167         } else if (err) {
2168                 snprintf(ctx->errors[ctx->req_type],
2169                          sizeof(ctx->errors[ctx->req_type]),
2170                          "Firmware file \"%s\" request failed (err=%d)\n",
2171                          ctx->fwname, err);
2172                 return err;
2173         }
2174 fw_ready:
2175         if (ctx->blob->size < sizeof(struct b43_fw_header))
2176                 goto err_format;
2177         hdr = (struct b43_fw_header *)(ctx->blob->data);
2178         switch (hdr->type) {
2179         case B43_FW_TYPE_UCODE:
2180         case B43_FW_TYPE_PCM:
2181                 size = be32_to_cpu(hdr->size);
2182                 if (size != ctx->blob->size - sizeof(struct b43_fw_header))
2183                         goto err_format;
2184                 /* fallthrough */
2185         case B43_FW_TYPE_IV:
2186                 if (hdr->ver != 1)
2187                         goto err_format;
2188                 break;
2189         default:
2190                 goto err_format;
2191         }
2192
2193         fw->data = ctx->blob;
2194         fw->filename = name;
2195         fw->type = ctx->req_type;
2196
2197         return 0;
2198
2199 err_format:
2200         snprintf(ctx->errors[ctx->req_type],
2201                  sizeof(ctx->errors[ctx->req_type]),
2202                  "Firmware file \"%s\" format error.\n", ctx->fwname);
2203         release_firmware(ctx->blob);
2204
2205         return -EPROTO;
2206 }
2207
2208 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2209 {
2210         struct b43_wldev *dev = ctx->dev;
2211         struct b43_firmware *fw = &ctx->dev->fw;
2212         const u8 rev = ctx->dev->dev->core_rev;
2213         const char *filename;
2214         u32 tmshigh;
2215         int err;
2216
2217         /* Files for HT and LCN were found by trying one by one */
2218
2219         /* Get microcode */
2220         if ((rev >= 5) && (rev <= 10)) {
2221                 filename = "ucode5";
2222         } else if ((rev >= 11) && (rev <= 12)) {
2223                 filename = "ucode11";
2224         } else if (rev == 13) {
2225                 filename = "ucode13";
2226         } else if (rev == 14) {
2227                 filename = "ucode14";
2228         } else if (rev == 15) {
2229                 filename = "ucode15";
2230         } else {
2231                 switch (dev->phy.type) {
2232                 case B43_PHYTYPE_N:
2233                         if (rev >= 16)
2234                                 filename = "ucode16_mimo";
2235                         else
2236                                 goto err_no_ucode;
2237                         break;
2238                 case B43_PHYTYPE_HT:
2239                         if (rev == 29)
2240                                 filename = "ucode29_mimo";
2241                         else
2242                                 goto err_no_ucode;
2243                         break;
2244                 case B43_PHYTYPE_LCN:
2245                         if (rev == 24)
2246                                 filename = "ucode24_mimo";
2247                         else
2248                                 goto err_no_ucode;
2249                         break;
2250                 default:
2251                         goto err_no_ucode;
2252                 }
2253         }
2254         err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
2255         if (err)
2256                 goto err_load;
2257
2258         /* Get PCM code */
2259         if ((rev >= 5) && (rev <= 10))
2260                 filename = "pcm5";
2261         else if (rev >= 11)
2262                 filename = NULL;
2263         else
2264                 goto err_no_pcm;
2265         fw->pcm_request_failed = false;
2266         err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
2267         if (err == -ENOENT) {
2268                 /* We did not find a PCM file? Not fatal, but
2269                  * core rev <= 10 must do without hwcrypto then. */
2270                 fw->pcm_request_failed = true;
2271         } else if (err)
2272                 goto err_load;
2273
2274         /* Get initvals */
2275         switch (dev->phy.type) {
2276         case B43_PHYTYPE_A:
2277                 if ((rev >= 5) && (rev <= 10)) {
2278                         tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2279                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2280                                 filename = "a0g1initvals5";
2281                         else
2282                                 filename = "a0g0initvals5";
2283                 } else
2284                         goto err_no_initvals;
2285                 break;
2286         case B43_PHYTYPE_G:
2287                 if ((rev >= 5) && (rev <= 10))
2288                         filename = "b0g0initvals5";
2289                 else if (rev >= 13)
2290                         filename = "b0g0initvals13";
2291                 else
2292                         goto err_no_initvals;
2293                 break;
2294         case B43_PHYTYPE_N:
2295                 if (rev >= 16)
2296                         filename = "n0initvals16";
2297                 else if ((rev >= 11) && (rev <= 12))
2298                         filename = "n0initvals11";
2299                 else
2300                         goto err_no_initvals;
2301                 break;
2302         case B43_PHYTYPE_LP:
2303                 if (rev == 13)
2304                         filename = "lp0initvals13";
2305                 else if (rev == 14)
2306                         filename = "lp0initvals14";
2307                 else if (rev >= 15)
2308                         filename = "lp0initvals15";
2309                 else
2310                         goto err_no_initvals;
2311                 break;
2312         case B43_PHYTYPE_HT:
2313                 if (rev == 29)
2314                         filename = "ht0initvals29";
2315                 else
2316                         goto err_no_initvals;
2317                 break;
2318         case B43_PHYTYPE_LCN:
2319                 if (rev == 24)
2320                         filename = "lcn0initvals24";
2321                 else
2322                         goto err_no_initvals;
2323                 break;
2324         default:
2325                 goto err_no_initvals;
2326         }
2327         err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
2328         if (err)
2329                 goto err_load;
2330
2331         /* Get bandswitch initvals */
2332         switch (dev->phy.type) {
2333         case B43_PHYTYPE_A:
2334                 if ((rev >= 5) && (rev <= 10)) {
2335                         tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2336                         if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2337                                 filename = "a0g1bsinitvals5";
2338                         else
2339                                 filename = "a0g0bsinitvals5";
2340                 } else if (rev >= 11)
2341                         filename = NULL;
2342                 else
2343                         goto err_no_initvals;
2344                 break;
2345         case B43_PHYTYPE_G:
2346                 if ((rev >= 5) && (rev <= 10))
2347                         filename = "b0g0bsinitvals5";
2348                 else if (rev >= 11)
2349                         filename = NULL;
2350                 else
2351                         goto err_no_initvals;
2352                 break;
2353         case B43_PHYTYPE_N:
2354                 if (rev >= 16)
2355                         filename = "n0bsinitvals16";
2356                 else if ((rev >= 11) && (rev <= 12))
2357                         filename = "n0bsinitvals11";
2358                 else
2359                         goto err_no_initvals;
2360                 break;
2361         case B43_PHYTYPE_LP:
2362                 if (rev == 13)
2363                         filename = "lp0bsinitvals13";
2364                 else if (rev == 14)
2365                         filename = "lp0bsinitvals14";
2366                 else if (rev >= 15)
2367                         filename = "lp0bsinitvals15";
2368                 else
2369                         goto err_no_initvals;
2370                 break;
2371         case B43_PHYTYPE_HT:
2372                 if (rev == 29)
2373                         filename = "ht0bsinitvals29";
2374                 else
2375                         goto err_no_initvals;
2376                 break;
2377         case B43_PHYTYPE_LCN:
2378                 if (rev == 24)
2379                         filename = "lcn0bsinitvals24";
2380                 else
2381                         goto err_no_initvals;
2382                 break;
2383         default:
2384                 goto err_no_initvals;
2385         }
2386         err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
2387         if (err)
2388                 goto err_load;
2389
2390         return 0;
2391
2392 err_no_ucode:
2393         err = ctx->fatal_failure = -EOPNOTSUPP;
2394         b43err(dev->wl, "The driver does not know which firmware (ucode) "
2395                "is required for your device (wl-core rev %u)\n", rev);
2396         goto error;
2397
2398 err_no_pcm:
2399         err = ctx->fatal_failure = -EOPNOTSUPP;
2400         b43err(dev->wl, "The driver does not know which firmware (PCM) "
2401                "is required for your device (wl-core rev %u)\n", rev);
2402         goto error;
2403
2404 err_no_initvals:
2405         err = ctx->fatal_failure = -EOPNOTSUPP;
2406         b43err(dev->wl, "The driver does not know which firmware (initvals) "
2407                "is required for your device (wl-core rev %u)\n", rev);
2408         goto error;
2409
2410 err_load:
2411         /* We failed to load this firmware image. The error message
2412          * already is in ctx->errors. Return and let our caller decide
2413          * what to do. */
2414         goto error;
2415
2416 error:
2417         b43_release_firmware(dev);
2418         return err;
2419 }
2420
2421 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
2422 static void b43_one_core_detach(struct b43_bus_dev *dev);
2423
2424 static void b43_request_firmware(struct work_struct *work)
2425 {
2426         struct b43_wl *wl = container_of(work,
2427                             struct b43_wl, firmware_load);
2428         struct b43_wldev *dev = wl->current_dev;
2429         struct b43_request_fw_context *ctx;
2430         unsigned int i;
2431         int err;
2432         const char *errmsg;
2433
2434         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2435         if (!ctx)
2436                 return;
2437         ctx->dev = dev;
2438
2439         ctx->req_type = B43_FWTYPE_PROPRIETARY;
2440         err = b43_try_request_fw(ctx);
2441         if (!err)
2442                 goto start_ieee80211; /* Successfully loaded it. */
2443         /* Was fw version known? */
2444         if (ctx->fatal_failure)
2445                 goto out;
2446
2447         /* proprietary fw not found, try open source */
2448         ctx->req_type = B43_FWTYPE_OPENSOURCE;
2449         err = b43_try_request_fw(ctx);
2450         if (!err)
2451                 goto start_ieee80211; /* Successfully loaded it. */
2452         if(ctx->fatal_failure)
2453                 goto out;
2454
2455         /* Could not find a usable firmware. Print the errors. */
2456         for (i = 0; i < B43_NR_FWTYPES; i++) {
2457                 errmsg = ctx->errors[i];
2458                 if (strlen(errmsg))
2459                         b43err(dev->wl, errmsg);
2460         }
2461         b43_print_fw_helptext(dev->wl, 1);
2462         goto out;
2463
2464 start_ieee80211:
2465         err = ieee80211_register_hw(wl->hw);
2466         if (err)
2467                 goto err_one_core_detach;
2468         b43_leds_register(wl->current_dev);
2469         goto out;
2470
2471 err_one_core_detach:
2472         b43_one_core_detach(dev->dev);
2473
2474 out:
2475         kfree(ctx);
2476 }
2477
2478 static int b43_upload_microcode(struct b43_wldev *dev)
2479 {
2480         struct wiphy *wiphy = dev->wl->hw->wiphy;
2481         const size_t hdr_len = sizeof(struct b43_fw_header);
2482         const __be32 *data;
2483         unsigned int i, len;
2484         u16 fwrev, fwpatch, fwdate, fwtime;
2485         u32 tmp, macctl;
2486         int err = 0;
2487
2488         /* Jump the microcode PSM to offset 0 */
2489         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2490         B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2491         macctl |= B43_MACCTL_PSM_JMP0;
2492         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2493         /* Zero out all microcode PSM registers and shared memory. */
2494         for (i = 0; i < 64; i++)
2495                 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2496         for (i = 0; i < 4096; i += 2)
2497                 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2498
2499         /* Upload Microcode. */
2500         data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2501         len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2502         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2503         for (i = 0; i < len; i++) {
2504                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2505                 udelay(10);
2506         }
2507
2508         if (dev->fw.pcm.data) {
2509                 /* Upload PCM data. */
2510                 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2511                 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2512                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2513                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2514                 /* No need for autoinc bit in SHM_HW */
2515                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2516                 for (i = 0; i < len; i++) {
2517                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2518                         udelay(10);
2519                 }
2520         }
2521
2522         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2523
2524         /* Start the microcode PSM */
2525         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
2526                       B43_MACCTL_PSM_RUN);
2527
2528         /* Wait for the microcode to load and respond */
2529         i = 0;
2530         while (1) {
2531                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2532                 if (tmp == B43_IRQ_MAC_SUSPENDED)
2533                         break;
2534                 i++;
2535                 if (i >= 20) {
2536                         b43err(dev->wl, "Microcode not responding\n");
2537                         b43_print_fw_helptext(dev->wl, 1);
2538                         err = -ENODEV;
2539                         goto error;
2540                 }
2541                 msleep(50);
2542         }
2543         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
2544
2545         /* Get and check the revisions. */
2546         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2547         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2548         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2549         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2550
2551         if (fwrev <= 0x128) {
2552                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2553                        "binary drivers older than version 4.x is unsupported. "
2554                        "You must upgrade your firmware files.\n");
2555                 b43_print_fw_helptext(dev->wl, 1);
2556                 err = -EOPNOTSUPP;
2557                 goto error;
2558         }
2559         dev->fw.rev = fwrev;
2560         dev->fw.patch = fwpatch;
2561         if (dev->fw.rev >= 598)
2562                 dev->fw.hdr_format = B43_FW_HDR_598;
2563         else if (dev->fw.rev >= 410)
2564                 dev->fw.hdr_format = B43_FW_HDR_410;
2565         else
2566                 dev->fw.hdr_format = B43_FW_HDR_351;
2567         dev->fw.opensource = (fwdate == 0xFFFF);
2568
2569         /* Default to use-all-queues. */
2570         dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2571         dev->qos_enabled = !!modparam_qos;
2572         /* Default to firmware/hardware crypto acceleration. */
2573         dev->hwcrypto_enabled = true;
2574
2575         if (dev->fw.opensource) {
2576                 u16 fwcapa;
2577
2578                 /* Patchlevel info is encoded in the "time" field. */
2579                 dev->fw.patch = fwtime;
2580                 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2581                         dev->fw.rev, dev->fw.patch);
2582
2583                 fwcapa = b43_fwcapa_read(dev);
2584                 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2585                         b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2586                         /* Disable hardware crypto and fall back to software crypto. */
2587                         dev->hwcrypto_enabled = false;
2588                 }
2589                 if (!(fwcapa & B43_FWCAPA_QOS)) {
2590                         b43info(dev->wl, "QoS not supported by firmware\n");
2591                         /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2592                          * ieee80211_unregister to make sure the networking core can
2593                          * properly free possible resources. */
2594                         dev->wl->hw->queues = 1;
2595                         dev->qos_enabled = false;
2596                 }
2597         } else {
2598                 b43info(dev->wl, "Loading firmware version %u.%u "
2599                         "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2600                         fwrev, fwpatch,
2601                         (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2602                         (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2603                 if (dev->fw.pcm_request_failed) {
2604                         b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2605                                 "Hardware accelerated cryptography is disabled.\n");
2606                         b43_print_fw_helptext(dev->wl, 0);
2607                 }
2608         }
2609
2610         snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2611                         dev->fw.rev, dev->fw.patch);
2612         wiphy->hw_version = dev->dev->core_id;
2613
2614         if (dev->fw.hdr_format == B43_FW_HDR_351) {
2615                 /* We're over the deadline, but we keep support for old fw
2616                  * until it turns out to be in major conflict with something new. */
2617                 b43warn(dev->wl, "You are using an old firmware image. "
2618                         "Support for old firmware will be removed soon "
2619                         "(official deadline was July 2008).\n");
2620                 b43_print_fw_helptext(dev->wl, 0);
2621         }
2622
2623         return 0;
2624
2625 error:
2626         /* Stop the microcode PSM. */
2627         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
2628                       B43_MACCTL_PSM_JMP0);
2629
2630         return err;
2631 }
2632
2633 static int b43_write_initvals(struct b43_wldev *dev,
2634                               const struct b43_iv *ivals,
2635                               size_t count,
2636                               size_t array_size)
2637 {
2638         const struct b43_iv *iv;
2639         u16 offset;
2640         size_t i;
2641         bool bit32;
2642
2643         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2644         iv = ivals;
2645         for (i = 0; i < count; i++) {
2646                 if (array_size < sizeof(iv->offset_size))
2647                         goto err_format;
2648                 array_size -= sizeof(iv->offset_size);
2649                 offset = be16_to_cpu(iv->offset_size);
2650                 bit32 = !!(offset & B43_IV_32BIT);
2651                 offset &= B43_IV_OFFSET_MASK;
2652                 if (offset >= 0x1000)
2653                         goto err_format;
2654                 if (bit32) {
2655                         u32 value;
2656
2657                         if (array_size < sizeof(iv->data.d32))
2658                                 goto err_format;
2659                         array_size -= sizeof(iv->data.d32);
2660
2661                         value = get_unaligned_be32(&iv->data.d32);
2662                         b43_write32(dev, offset, value);
2663
2664                         iv = (const struct b43_iv *)((const uint8_t *)iv +
2665                                                         sizeof(__be16) +
2666                                                         sizeof(__be32));
2667                 } else {
2668                         u16 value;
2669
2670                         if (array_size < sizeof(iv->data.d16))
2671                                 goto err_format;
2672                         array_size -= sizeof(iv->data.d16);
2673
2674                         value = be16_to_cpu(iv->data.d16);
2675                         b43_write16(dev, offset, value);
2676
2677                         iv = (const struct b43_iv *)((const uint8_t *)iv +
2678                                                         sizeof(__be16) +
2679                                                         sizeof(__be16));
2680                 }
2681         }
2682         if (array_size)
2683                 goto err_format;
2684
2685         return 0;
2686
2687 err_format:
2688         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2689         b43_print_fw_helptext(dev->wl, 1);
2690
2691         return -EPROTO;
2692 }
2693
2694 static int b43_upload_initvals(struct b43_wldev *dev)
2695 {
2696         const size_t hdr_len = sizeof(struct b43_fw_header);
2697         const struct b43_fw_header *hdr;
2698         struct b43_firmware *fw = &dev->fw;
2699         const struct b43_iv *ivals;
2700         size_t count;
2701         int err;
2702
2703         hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2704         ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2705         count = be32_to_cpu(hdr->size);
2706         err = b43_write_initvals(dev, ivals, count,
2707                                  fw->initvals.data->size - hdr_len);
2708         if (err)
2709                 goto out;
2710         if (fw->initvals_band.data) {
2711                 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2712                 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2713                 count = be32_to_cpu(hdr->size);
2714                 err = b43_write_initvals(dev, ivals, count,
2715                                          fw->initvals_band.data->size - hdr_len);
2716                 if (err)
2717                         goto out;
2718         }
2719 out:
2720
2721         return err;
2722 }
2723
2724 /* Initialize the GPIOs
2725  * http://bcm-specs.sipsolutions.net/GPIO
2726  */
2727 static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2728 {
2729         struct ssb_bus *bus = dev->dev->sdev->bus;
2730
2731 #ifdef CONFIG_SSB_DRIVER_PCICORE
2732         return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
2733 #else
2734         return bus->chipco.dev;
2735 #endif
2736 }
2737
2738 static int b43_gpio_init(struct b43_wldev *dev)
2739 {
2740         struct ssb_device *gpiodev;
2741         u32 mask, set;
2742
2743         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
2744         b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
2745
2746         mask = 0x0000001F;
2747         set = 0x0000000F;
2748         if (dev->dev->chip_id == 0x4301) {
2749                 mask |= 0x0060;
2750                 set |= 0x0060;
2751         }
2752         if (dev->dev->chip_id == 0x5354)
2753                 set &= 0xff02;
2754         if (0 /* FIXME: conditional unknown */ ) {
2755                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2756                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2757                             | 0x0100);
2758                 mask |= 0x0180;
2759                 set |= 0x0180;
2760         }
2761         if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2762                 b43_write16(dev, B43_MMIO_GPIO_MASK,
2763                             b43_read16(dev, B43_MMIO_GPIO_MASK)
2764                             | 0x0200);
2765                 mask |= 0x0200;
2766                 set |= 0x0200;
2767         }
2768         if (dev->dev->core_rev >= 2)
2769                 mask |= 0x0010; /* FIXME: This is redundant. */
2770
2771         switch (dev->dev->bus_type) {
2772 #ifdef CONFIG_B43_BCMA
2773         case B43_BUS_BCMA:
2774                 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2775                                 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2776                                         BCMA_CC_GPIOCTL) & mask) | set);
2777                 break;
2778 #endif
2779 #ifdef CONFIG_B43_SSB
2780         case B43_BUS_SSB:
2781                 gpiodev = b43_ssb_gpio_dev(dev);
2782                 if (gpiodev)
2783                         ssb_write32(gpiodev, B43_GPIO_CONTROL,
2784                                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2785                                     & mask) | set);
2786                 break;
2787 #endif
2788         }
2789
2790         return 0;
2791 }
2792
2793 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2794 static void b43_gpio_cleanup(struct b43_wldev *dev)
2795 {
2796         struct ssb_device *gpiodev;
2797
2798         switch (dev->dev->bus_type) {
2799 #ifdef CONFIG_B43_BCMA
2800         case B43_BUS_BCMA:
2801                 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2802                                 0);
2803                 break;
2804 #endif
2805 #ifdef CONFIG_B43_SSB
2806         case B43_BUS_SSB:
2807                 gpiodev = b43_ssb_gpio_dev(dev);
2808                 if (gpiodev)
2809                         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2810                 break;
2811 #endif
2812         }
2813 }
2814
2815 /* http://bcm-specs.sipsolutions.net/EnableMac */
2816 void b43_mac_enable(struct b43_wldev *dev)
2817 {
2818         if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2819                 u16 fwstate;
2820
2821                 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2822                                          B43_SHM_SH_UCODESTAT);
2823                 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2824                     (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2825                         b43err(dev->wl, "b43_mac_enable(): The firmware "
2826                                "should be suspended, but current state is %u\n",
2827                                fwstate);
2828                 }
2829         }
2830
2831         dev->mac_suspended--;
2832         B43_WARN_ON(dev->mac_suspended < 0);
2833         if (dev->mac_suspended == 0) {
2834                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
2835                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2836                             B43_IRQ_MAC_SUSPENDED);
2837                 /* Commit writes */
2838                 b43_read32(dev, B43_MMIO_MACCTL);
2839                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2840                 b43_power_saving_ctl_bits(dev, 0);
2841         }
2842 }
2843
2844 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2845 void b43_mac_suspend(struct b43_wldev *dev)
2846 {
2847         int i;
2848         u32 tmp;
2849
2850         might_sleep();
2851         B43_WARN_ON(dev->mac_suspended < 0);
2852
2853         if (dev->mac_suspended == 0) {
2854                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2855                 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
2856                 /* force pci to flush the write */
2857                 b43_read32(dev, B43_MMIO_MACCTL);
2858                 for (i = 35; i; i--) {
2859                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2860                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2861                                 goto out;
2862                         udelay(10);
2863                 }
2864                 /* Hm, it seems this will take some time. Use msleep(). */
2865                 for (i = 40; i; i--) {
2866                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2867                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2868                                 goto out;
2869                         msleep(1);
2870                 }
2871                 b43err(dev->wl, "MAC suspend failed\n");
2872         }
2873 out:
2874         dev->mac_suspended++;
2875 }
2876
2877 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2878 void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2879 {
2880         u32 tmp;
2881
2882         switch (dev->dev->bus_type) {
2883 #ifdef CONFIG_B43_BCMA
2884         case B43_BUS_BCMA:
2885                 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2886                 if (on)
2887                         tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2888                 else
2889                         tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2890                 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
2891                 break;
2892 #endif
2893 #ifdef CONFIG_B43_SSB
2894         case B43_BUS_SSB:
2895                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2896                 if (on)
2897                         tmp |= B43_TMSLOW_MACPHYCLKEN;
2898                 else
2899                         tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2900                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2901                 break;
2902 #endif
2903         }
2904 }
2905
2906 static void b43_adjust_opmode(struct b43_wldev *dev)
2907 {
2908         struct b43_wl *wl = dev->wl;
2909         u32 ctl;
2910         u16 cfp_pretbtt;
2911
2912         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2913         /* Reset status to STA infrastructure mode. */
2914         ctl &= ~B43_MACCTL_AP;
2915         ctl &= ~B43_MACCTL_KEEP_CTL;
2916         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2917         ctl &= ~B43_MACCTL_KEEP_BAD;
2918         ctl &= ~B43_MACCTL_PROMISC;
2919         ctl &= ~B43_MACCTL_BEACPROMISC;
2920         ctl |= B43_MACCTL_INFRA;
2921
2922         if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2923             b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2924                 ctl |= B43_MACCTL_AP;
2925         else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2926                 ctl &= ~B43_MACCTL_INFRA;
2927
2928         if (wl->filter_flags & FIF_CONTROL)
2929                 ctl |= B43_MACCTL_KEEP_CTL;
2930         if (wl->filter_flags & FIF_FCSFAIL)
2931                 ctl |= B43_MACCTL_KEEP_BAD;
2932         if (wl->filter_flags & FIF_PLCPFAIL)
2933                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2934         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2935                 ctl |= B43_MACCTL_PROMISC;
2936         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2937                 ctl |= B43_MACCTL_BEACPROMISC;
2938
2939         /* Workaround: On old hardware the HW-MAC-address-filter
2940          * doesn't work properly, so always run promisc in filter
2941          * it in software. */
2942         if (dev->dev->core_rev <= 4)
2943                 ctl |= B43_MACCTL_PROMISC;
2944
2945         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2946
2947         cfp_pretbtt = 2;
2948         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2949                 if (dev->dev->chip_id == 0x4306 &&
2950                     dev->dev->chip_rev == 3)
2951                         cfp_pretbtt = 100;
2952                 else
2953                         cfp_pretbtt = 50;
2954         }
2955         b43_write16(dev, 0x612, cfp_pretbtt);
2956
2957         /* FIXME: We don't currently implement the PMQ mechanism,
2958          *        so always disable it. If we want to implement PMQ,
2959          *        we need to enable it here (clear DISCPMQ) in AP mode.
2960          */
2961         if (0  /* ctl & B43_MACCTL_AP */)
2962                 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
2963         else
2964                 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
2965 }
2966
2967 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2968 {
2969         u16 offset;
2970
2971         if (is_ofdm) {
2972                 offset = 0x480;
2973                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2974         } else {
2975                 offset = 0x4C0;
2976                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2977         }
2978         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2979                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2980 }
2981
2982 static void b43_rate_memory_init(struct b43_wldev *dev)
2983 {
2984         switch (dev->phy.type) {
2985         case B43_PHYTYPE_A:
2986         case B43_PHYTYPE_G:
2987         case B43_PHYTYPE_N:
2988         case B43_PHYTYPE_LP:
2989         case B43_PHYTYPE_HT:
2990         case B43_PHYTYPE_LCN:
2991                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2992                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2993                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2994                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2995                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2996                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2997                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2998                 if (dev->phy.type == B43_PHYTYPE_A)
2999                         break;
3000                 /* fallthrough */
3001         case B43_PHYTYPE_B:
3002                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
3003                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
3004                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
3005                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
3006                 break;
3007         default:
3008                 B43_WARN_ON(1);
3009         }
3010 }
3011
3012 /* Set the default values for the PHY TX Control Words. */
3013 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
3014 {
3015         u16 ctl = 0;
3016
3017         ctl |= B43_TXH_PHY_ENC_CCK;
3018         ctl |= B43_TXH_PHY_ANT01AUTO;
3019         ctl |= B43_TXH_PHY_TXPWR;
3020
3021         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
3022         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
3023         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
3024 }
3025
3026 /* Set the TX-Antenna for management frames sent by firmware. */
3027 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
3028 {
3029         u16 ant;
3030         u16 tmp;
3031
3032         ant = b43_antenna_to_phyctl(antenna);
3033
3034         /* For ACK/CTS */
3035         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
3036         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3037         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
3038         /* For Probe Resposes */
3039         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
3040         tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
3041         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
3042 }
3043
3044 /* This is the opposite of b43_chip_init() */
3045 static void b43_chip_exit(struct b43_wldev *dev)
3046 {
3047         b43_phy_exit(dev);
3048         b43_gpio_cleanup(dev);
3049         /* firmware is released later */
3050 }
3051
3052 /* Initialize the chip
3053  * http://bcm-specs.sipsolutions.net/ChipInit
3054  */
3055 static int b43_chip_init(struct b43_wldev *dev)
3056 {
3057         struct b43_phy *phy = &dev->phy;
3058         int err;
3059         u32 macctl;
3060         u16 value16;
3061
3062         /* Initialize the MAC control */
3063         macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
3064         if (dev->phy.gmode)
3065                 macctl |= B43_MACCTL_GMODE;
3066         macctl |= B43_MACCTL_INFRA;
3067         b43_write32(dev, B43_MMIO_MACCTL, macctl);
3068
3069         err = b43_upload_microcode(dev);
3070         if (err)
3071                 goto out;       /* firmware is released later */
3072
3073         err = b43_gpio_init(dev);
3074         if (err)
3075                 goto out;       /* firmware is released later */
3076
3077         err = b43_upload_initvals(dev);
3078         if (err)
3079                 goto err_gpio_clean;
3080
3081         /* Turn the Analog on and initialize the PHY. */
3082         phy->ops->switch_analog(dev, 1);
3083         err = b43_phy_init(dev);
3084         if (err)
3085                 goto err_gpio_clean;
3086
3087         /* Disable Interference Mitigation. */
3088         if (phy->ops->interf_mitigation)
3089                 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3090
3091         /* Select the antennae */
3092         if (phy->ops->set_rx_antenna)
3093                 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
3094         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
3095
3096         if (phy->type == B43_PHYTYPE_B) {
3097                 value16 = b43_read16(dev, 0x005E);
3098                 value16 |= 0x0004;
3099                 b43_write16(dev, 0x005E, value16);
3100         }
3101         b43_write32(dev, 0x0100, 0x01000000);
3102         if (dev->dev->core_rev < 5)
3103                 b43_write32(dev, 0x010C, 0x01000000);
3104
3105         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
3106         b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
3107
3108         /* Probe Response Timeout value */
3109         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3110         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
3111
3112         /* Initially set the wireless operation mode. */
3113         b43_adjust_opmode(dev);
3114
3115         if (dev->dev->core_rev < 3) {
3116                 b43_write16(dev, 0x060E, 0x0000);
3117                 b43_write16(dev, 0x0610, 0x8000);
3118                 b43_write16(dev, 0x0604, 0x0000);
3119                 b43_write16(dev, 0x0606, 0x0200);
3120         } else {
3121                 b43_write32(dev, 0x0188, 0x80000000);
3122                 b43_write32(dev, 0x018C, 0x02000000);
3123         }
3124         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
3125         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
3126         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
3127         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
3128         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
3129         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
3130         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
3131
3132         b43_mac_phy_clock_set(dev, true);
3133
3134         switch (dev->dev->bus_type) {
3135 #ifdef CONFIG_B43_BCMA
3136         case B43_BUS_BCMA:
3137                 /* FIXME: 0xE74 is quite common, but should be read from CC */
3138                 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3139                 break;
3140 #endif
3141 #ifdef CONFIG_B43_SSB
3142         case B43_BUS_SSB:
3143                 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3144                             dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3145                 break;
3146 #endif
3147         }
3148
3149         err = 0;
3150         b43dbg(dev->wl, "Chip initialized\n");
3151 out:
3152         return err;
3153
3154 err_gpio_clean:
3155         b43_gpio_cleanup(dev);
3156         return err;
3157 }
3158
3159 static void b43_periodic_every60sec(struct b43_wldev *dev)
3160 {
3161         const struct b43_phy_operations *ops = dev->phy.ops;
3162
3163         if (ops->pwork_60sec)
3164                 ops->pwork_60sec(dev);
3165
3166         /* Force check the TX power emission now. */
3167         b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
3168 }
3169
3170 static void b43_periodic_every30sec(struct b43_wldev *dev)
3171 {
3172         /* Update device statistics. */
3173         b43_calculate_link_quality(dev);
3174 }
3175
3176 static void b43_periodic_every15sec(struct b43_wldev *dev)
3177 {
3178         struct b43_phy *phy = &dev->phy;
3179         u16 wdr;
3180
3181         if (dev->fw.opensource) {
3182                 /* Check if the firmware is still alive.
3183                  * It will reset the watchdog counter to 0 in its idle loop. */
3184                 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
3185                 if (unlikely(wdr)) {
3186                         b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
3187                         b43_controller_restart(dev, "Firmware watchdog");
3188                         return;
3189                 } else {
3190                         b43_shm_write16(dev, B43_SHM_SCRATCH,
3191                                         B43_WATCHDOG_REG, 1);
3192                 }
3193         }
3194
3195         if (phy->ops->pwork_15sec)
3196                 phy->ops->pwork_15sec(dev);
3197
3198         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3199         wmb();
3200
3201 #if B43_DEBUG
3202         if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
3203                 unsigned int i;
3204
3205                 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
3206                        dev->irq_count / 15,
3207                        dev->tx_count / 15,
3208                        dev->rx_count / 15);
3209                 dev->irq_count = 0;
3210                 dev->tx_count = 0;
3211                 dev->rx_count = 0;
3212                 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
3213                         if (dev->irq_bit_count[i]) {
3214                                 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
3215                                        dev->irq_bit_count[i] / 15, i, (1 << i));
3216                                 dev->irq_bit_count[i] = 0;
3217                         }
3218                 }
3219         }
3220 #endif
3221 }
3222
3223 static void do_periodic_work(struct b43_wldev *dev)
3224 {
3225         unsigned int state;
3226
3227         state = dev->periodic_state;
3228         if (state % 4 == 0)
3229                 b43_periodic_every60sec(dev);
3230         if (state % 2 == 0)
3231                 b43_periodic_every30sec(dev);
3232         b43_periodic_every15sec(dev);
3233 }
3234
3235 /* Periodic work locking policy:
3236  *      The whole periodic work handler is protected by
3237  *      wl->mutex. If another lock is needed somewhere in the
3238  *      pwork callchain, it's acquired in-place, where it's needed.
3239  */
3240 static void b43_periodic_work_handler(struct work_struct *work)
3241 {
3242         struct b43_wldev *dev = container_of(work, struct b43_wldev,
3243                                              periodic_work.work);
3244         struct b43_wl *wl = dev->wl;
3245         unsigned long delay;
3246
3247         mutex_lock(&wl->mutex);
3248
3249         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
3250                 goto out;
3251         if (b43_debug(dev, B43_DBG_PWORK_STOP))
3252                 goto out_requeue;
3253
3254         do_periodic_work(dev);
3255
3256         dev->periodic_state++;
3257 out_requeue:
3258         if (b43_debug(dev, B43_DBG_PWORK_FAST))
3259                 delay = msecs_to_jiffies(50);
3260         else
3261                 delay = round_jiffies_relative(HZ * 15);
3262         ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
3263 out:
3264         mutex_unlock(&wl->mutex);
3265 }
3266
3267 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3268 {
3269         struct delayed_work *work = &dev->periodic_work;
3270
3271         dev->periodic_state = 0;
3272         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
3273         ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
3274 }
3275
3276 /* Check if communication with the device works correctly. */
3277 static int b43_validate_chipaccess(struct b43_wldev *dev)
3278 {
3279         u32 v, backup0, backup4;
3280
3281         backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3282         backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
3283
3284         /* Check for read/write and endianness problems. */
3285         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3286         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3287                 goto error;
3288         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3289         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
3290                 goto error;
3291
3292         /* Check if unaligned 32bit SHM_SHARED access works properly.
3293          * However, don't bail out on failure, because it's noncritical. */
3294         b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3295         b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3296         b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3297         b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3298         if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3299                 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3300         b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3301         if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3302             b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3303             b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3304             b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3305                 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3306
3307         b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3308         b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3309
3310         if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3311                 /* The 32bit register shadows the two 16bit registers
3312                  * with update sideeffects. Validate this. */
3313                 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3314                 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3315                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3316                         goto error;
3317                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3318                         goto error;
3319         }
3320         b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3321
3322         v = b43_read32(dev, B43_MMIO_MACCTL);
3323         v |= B43_MACCTL_GMODE;
3324         if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3325                 goto error;
3326
3327         return 0;
3328 error:
3329         b43err(dev->wl, "Failed to validate the chipaccess\n");
3330         return -ENODEV;
3331 }
3332
3333 static void b43_security_init(struct b43_wldev *dev)
3334 {
3335         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3336         /* KTP is a word address, but we address SHM bytewise.
3337          * So multiply by two.
3338          */
3339         dev->ktp *= 2;
3340         /* Number of RCMTA address slots */
3341         b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3342         /* Clear the key memory. */
3343         b43_clear_keys(dev);
3344 }
3345
3346 #ifdef CONFIG_B43_HWRNG
3347 static int b43_rng_read(struct hwrng *rng, u32 *data)
3348 {
3349         struct b43_wl *wl = (struct b43_wl *)rng->priv;
3350         struct b43_wldev *dev;
3351         int count = -ENODEV;
3352
3353         mutex_lock(&wl->mutex);
3354         dev = wl->current_dev;
3355         if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3356                 *data = b43_read16(dev, B43_MMIO_RNG);
3357                 count = sizeof(u16);
3358         }
3359         mutex_unlock(&wl->mutex);
3360
3361         return count;
3362 }
3363 #endif /* CONFIG_B43_HWRNG */
3364
3365 static void b43_rng_exit(struct b43_wl *wl)
3366 {
3367 #ifdef CONFIG_B43_HWRNG
3368         if (wl->rng_initialized)
3369                 hwrng_unregister(&wl->rng);
3370 #endif /* CONFIG_B43_HWRNG */
3371 }
3372
3373 static int b43_rng_init(struct b43_wl *wl)
3374 {
3375         int err = 0;
3376
3377 #ifdef CONFIG_B43_HWRNG
3378         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3379                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3380         wl->rng.name = wl->rng_name;
3381         wl->rng.data_read = b43_rng_read;
3382         wl->rng.priv = (unsigned long)wl;
3383         wl->rng_initialized = true;
3384         err = hwrng_register(&wl->rng);
3385         if (err) {
3386                 wl->rng_initialized = false;
3387                 b43err(wl, "Failed to register the random "
3388                        "number generator (%d)\n", err);
3389         }
3390 #endif /* CONFIG_B43_HWRNG */
3391
3392         return err;
3393 }
3394
3395 static void b43_tx_work(struct work_struct *work)
3396 {
3397         struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3398         struct b43_wldev *dev;
3399         struct sk_buff *skb;
3400         int queue_num;
3401         int err = 0;
3402
3403         mutex_lock(&wl->mutex);
3404         dev = wl->current_dev;
3405         if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3406                 mutex_unlock(&wl->mutex);
3407                 return;
3408         }
3409
3410         for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
3411                 while (skb_queue_len(&wl->tx_queue[queue_num])) {
3412                         skb = skb_dequeue(&wl->tx_queue[queue_num]);
3413                         if (b43_using_pio_transfers(dev))
3414                                 err = b43_pio_tx(dev, skb);
3415                         else
3416                                 err = b43_dma_tx(dev, skb);
3417                         if (err == -ENOSPC) {
3418                                 wl->tx_queue_stopped[queue_num] = 1;
3419                                 ieee80211_stop_queue(wl->hw, queue_num);
3420                                 skb_queue_head(&wl->tx_queue[queue_num], skb);
3421                                 break;
3422                         }
3423                         if (unlikely(err))
3424                                 ieee80211_free_txskb(wl->hw, skb);
3425                         err = 0;
3426                 }
3427
3428                 if (!err)
3429                         wl->tx_queue_stopped[queue_num] = 0;
3430         }
3431
3432 #if B43_DEBUG
3433         dev->tx_count++;
3434 #endif
3435         mutex_unlock(&wl->mutex);
3436 }
3437
3438 static void b43_op_tx(struct ieee80211_hw *hw,
3439                      struct sk_buff *skb)
3440 {
3441         struct b43_wl *wl = hw_to_b43_wl(hw);
3442
3443         if (unlikely(skb->len < 2 + 2 + 6)) {
3444                 /* Too short, this can't be a valid frame. */
3445                 ieee80211_free_txskb(hw, skb);
3446                 return;
3447         }
3448         B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3449
3450         skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
3451         if (!wl->tx_queue_stopped[skb->queue_mapping]) {
3452                 ieee80211_queue_work(wl->hw, &wl->tx_work);
3453         } else {
3454                 ieee80211_stop_queue(wl->hw, skb->queue_mapping);
3455         }
3456 }
3457
3458 static void b43_qos_params_upload(struct b43_wldev *dev,
3459                                   const struct ieee80211_tx_queue_params *p,
3460                                   u16 shm_offset)
3461 {
3462         u16 params[B43_NR_QOSPARAMS];
3463         int bslots, tmp;
3464         unsigned int i;
3465
3466         if (!dev->qos_enabled)
3467                 return;
3468
3469         bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3470
3471         memset(&params, 0, sizeof(params));
3472
3473         params[B43_QOSPARAM_TXOP] = p->txop * 32;
3474         params[B43_QOSPARAM_CWMIN] = p->cw_min;
3475         params[B43_QOSPARAM_CWMAX] = p->cw_max;
3476         params[B43_QOSPARAM_CWCUR] = p->cw_min;
3477         params[B43_QOSPARAM_AIFS] = p->aifs;
3478         params[B43_QOSPARAM_BSLOTS] = bslots;
3479         params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3480
3481         for (i = 0; i < ARRAY_SIZE(params); i++) {
3482                 if (i == B43_QOSPARAM_STATUS) {
3483                         tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3484                                              shm_offset + (i * 2));
3485                         /* Mark the parameters as updated. */
3486                         tmp |= 0x100;
3487                         b43_shm_write16(dev, B43_SHM_SHARED,
3488                                         shm_offset + (i * 2),
3489                                         tmp);
3490                 } else {
3491                         b43_shm_write16(dev, B43_SHM_SHARED,
3492                                         shm_offset + (i * 2),
3493                                         params[i]);
3494                 }
3495         }
3496 }
3497
3498 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3499 static const u16 b43_qos_shm_offsets[] = {
3500         /* [mac80211-queue-nr] = SHM_OFFSET, */
3501         [0] = B43_QOS_VOICE,
3502         [1] = B43_QOS_VIDEO,
3503         [2] = B43_QOS_BESTEFFORT,
3504         [3] = B43_QOS_BACKGROUND,
3505 };
3506
3507 /* Update all QOS parameters in hardware. */
3508 static void b43_qos_upload_all(struct b43_wldev *dev)
3509 {
3510         struct b43_wl *wl = dev->wl;
3511         struct b43_qos_params *params;
3512         unsigned int i;
3513
3514         if (!dev->qos_enabled)
3515                 return;
3516
3517         BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3518                      ARRAY_SIZE(wl->qos_params));
3519
3520         b43_mac_suspend(dev);
3521         for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3522                 params = &(wl->qos_params[i]);
3523                 b43_qos_params_upload(dev, &(params->p),
3524                                       b43_qos_shm_offsets[i]);
3525         }
3526         b43_mac_enable(dev);
3527 }
3528
3529 static void b43_qos_clear(struct b43_wl *wl)
3530 {
3531         struct b43_qos_params *params;
3532         unsigned int i;
3533
3534         /* Initialize QoS parameters to sane defaults. */
3535
3536         BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3537                      ARRAY_SIZE(wl->qos_params));
3538
3539         for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3540                 params = &(wl->qos_params[i]);
3541
3542                 switch (b43_qos_shm_offsets[i]) {
3543                 case B43_QOS_VOICE:
3544                         params->p.txop = 0;
3545                         params->p.aifs = 2;
3546                         params->p.cw_min = 0x0001;
3547                         params->p.cw_max = 0x0001;
3548                         break;
3549                 case B43_QOS_VIDEO:
3550                         params->p.txop = 0;
3551                         params->p.aifs = 2;
3552                         params->p.cw_min = 0x0001;
3553                         params->p.cw_max = 0x0001;
3554                         break;
3555                 case B43_QOS_BESTEFFORT:
3556                         params->p.txop = 0;
3557                         params->p.aifs = 3;
3558                         params->p.cw_min = 0x0001;
3559                         params->p.cw_max = 0x03FF;
3560                         break;
3561                 case B43_QOS_BACKGROUND:
3562                         params->p.txop = 0;
3563                         params->p.aifs = 7;
3564                         params->p.cw_min = 0x0001;
3565                         params->p.cw_max = 0x03FF;
3566                         break;
3567                 default:
3568                         B43_WARN_ON(1);
3569                 }
3570         }
3571 }
3572
3573 /* Initialize the core's QOS capabilities */
3574 static void b43_qos_init(struct b43_wldev *dev)
3575 {
3576         if (!dev->qos_enabled) {
3577                 /* Disable QOS support. */
3578                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3579                 b43_write16(dev, B43_MMIO_IFSCTL,
3580                             b43_read16(dev, B43_MMIO_IFSCTL)
3581                             & ~B43_MMIO_IFSCTL_USE_EDCF);
3582                 b43dbg(dev->wl, "QoS disabled\n");
3583                 return;
3584         }
3585
3586         /* Upload the current QOS parameters. */
3587         b43_qos_upload_all(dev);
3588
3589         /* Enable QOS support. */
3590         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3591         b43_write16(dev, B43_MMIO_IFSCTL,
3592                     b43_read16(dev, B43_MMIO_IFSCTL)
3593                     | B43_MMIO_IFSCTL_USE_EDCF);
3594         b43dbg(dev->wl, "QoS enabled\n");
3595 }
3596
3597 static int b43_op_conf_tx(struct ieee80211_hw *hw,
3598                           struct ieee80211_vif *vif, u16 _queue,
3599                           const struct ieee80211_tx_queue_params *params)
3600 {
3601         struct b43_wl *wl = hw_to_b43_wl(hw);
3602         struct b43_wldev *dev;
3603         unsigned int queue = (unsigned int)_queue;
3604         int err = -ENODEV;
3605
3606         if (queue >= ARRAY_SIZE(wl->qos_params)) {
3607                 /* Queue not available or don't support setting
3608                  * params on this queue. Return success to not
3609                  * confuse mac80211. */
3610                 return 0;
3611         }
3612         BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3613                      ARRAY_SIZE(wl->qos_params));
3614
3615         mutex_lock(&wl->mutex);
3616         dev = wl->current_dev;
3617         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3618                 goto out_unlock;
3619
3620         memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3621         b43_mac_suspend(dev);
3622         b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3623                               b43_qos_shm_offsets[queue]);
3624         b43_mac_enable(dev);
3625         err = 0;
3626
3627 out_unlock:
3628         mutex_unlock(&wl->mutex);
3629
3630         return err;
3631 }
3632
3633 static int b43_op_get_stats(struct ieee80211_hw *hw,
3634                             struct ieee80211_low_level_stats *stats)
3635 {
3636         struct b43_wl *wl = hw_to_b43_wl(hw);
3637
3638         mutex_lock(&wl->mutex);
3639         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3640         mutex_unlock(&wl->mutex);
3641
3642         return 0;
3643 }
3644
3645 static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3646 {
3647         struct b43_wl *wl = hw_to_b43_wl(hw);
3648         struct b43_wldev *dev;
3649         u64 tsf;
3650
3651         mutex_lock(&wl->mutex);
3652         dev = wl->current_dev;
3653
3654         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3655                 b43_tsf_read(dev, &tsf);
3656         else
3657                 tsf = 0;
3658
3659         mutex_unlock(&wl->mutex);
3660
3661         return tsf;
3662 }
3663
3664 static void b43_op_set_tsf(struct ieee80211_hw *hw,
3665                            struct ieee80211_vif *vif, u64 tsf)
3666 {
3667         struct b43_wl *wl = hw_to_b43_wl(hw);
3668         struct b43_wldev *dev;
3669
3670         mutex_lock(&wl->mutex);
3671         dev = wl->current_dev;
3672
3673         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3674                 b43_tsf_write(dev, tsf);
3675
3676         mutex_unlock(&wl->mutex);
3677 }
3678
3679 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3680 {
3681         u32 tmp;
3682
3683         switch (dev->dev->bus_type) {
3684 #ifdef CONFIG_B43_BCMA
3685         case B43_BUS_BCMA:
3686                 b43err(dev->wl,
3687                        "Putting PHY into reset not supported on BCMA\n");
3688                 break;
3689 #endif
3690 #ifdef CONFIG_B43_SSB
3691         case B43_BUS_SSB:
3692                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3693                 tmp &= ~B43_TMSLOW_GMODE;
3694                 tmp |= B43_TMSLOW_PHYRESET;
3695                 tmp |= SSB_TMSLOW_FGC;
3696                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3697                 msleep(1);
3698
3699                 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3700                 tmp &= ~SSB_TMSLOW_FGC;
3701                 tmp |= B43_TMSLOW_PHYRESET;
3702                 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3703                 msleep(1);
3704
3705                 break;
3706 #endif
3707         }
3708 }
3709
3710 static const char *band_to_string(enum ieee80211_band band)
3711 {
3712         switch (band) {
3713         case IEEE80211_BAND_5GHZ:
3714                 return "5";
3715         case IEEE80211_BAND_2GHZ:
3716                 return "2.4";
3717         default:
3718                 break;
3719         }
3720         B43_WARN_ON(1);
3721         return "";
3722 }
3723
3724 /* Expects wl->mutex locked */
3725 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3726 {
3727         struct b43_wldev *up_dev = NULL;
3728         struct b43_wldev *down_dev;
3729         struct b43_wldev *d;
3730         int err;
3731         bool uninitialized_var(gmode);
3732         int prev_status;
3733
3734         /* Find a device and PHY which supports the band. */
3735         list_for_each_entry(d, &wl->devlist, list) {
3736                 switch (chan->band) {
3737                 case IEEE80211_BAND_5GHZ:
3738                         if (d->phy.supports_5ghz) {
3739                                 up_dev = d;
3740                                 gmode = false;
3741                         }
3742                         break;
3743                 case IEEE80211_BAND_2GHZ:
3744                         if (d->phy.supports_2ghz) {
3745                                 up_dev = d;
3746                                 gmode = true;
3747                         }
3748                         break;
3749                 default:
3750                         B43_WARN_ON(1);
3751                         return -EINVAL;
3752                 }
3753                 if (up_dev)
3754                         break;
3755         }
3756         if (!up_dev) {
3757                 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3758                        band_to_string(chan->band));
3759                 return -ENODEV;
3760         }
3761         if ((up_dev == wl->current_dev) &&
3762             (!!wl->current_dev->phy.gmode == !!gmode)) {
3763                 /* This device is already running. */
3764                 return 0;
3765         }
3766         b43dbg(wl, "Switching to %s-GHz band\n",
3767                band_to_string(chan->band));
3768         down_dev = wl->current_dev;
3769
3770         prev_status = b43_status(down_dev);
3771         /* Shutdown the currently running core. */
3772         if (prev_status >= B43_STAT_STARTED)
3773                 down_dev = b43_wireless_core_stop(down_dev);
3774         if (prev_status >= B43_STAT_INITIALIZED)
3775                 b43_wireless_core_exit(down_dev);
3776
3777         if (down_dev != up_dev) {
3778                 /* We switch to a different core, so we put PHY into
3779                  * RESET on the old core. */
3780                 b43_put_phy_into_reset(down_dev);
3781         }
3782
3783         /* Now start the new core. */
3784         up_dev->phy.gmode = gmode;
3785         if (prev_status >= B43_STAT_INITIALIZED) {
3786                 err = b43_wireless_core_init(up_dev);
3787                 if (err) {
3788                         b43err(wl, "Fatal: Could not initialize device for "
3789                                "selected %s-GHz band\n",
3790                                band_to_string(chan->band));
3791                         goto init_failure;
3792                 }
3793         }
3794         if (prev_status >= B43_STAT_STARTED) {
3795                 err = b43_wireless_core_start(up_dev);
3796                 if (err) {
3797                         b43err(wl, "Fatal: Coult not start device for "
3798                                "selected %s-GHz band\n",
3799                                band_to_string(chan->band));
3800                         b43_wireless_core_exit(up_dev);
3801                         goto init_failure;
3802                 }
3803         }
3804         B43_WARN_ON(b43_status(up_dev) != prev_status);
3805
3806         wl->current_dev = up_dev;
3807
3808         return 0;
3809 init_failure:
3810         /* Whoops, failed to init the new core. No core is operating now. */
3811         wl->current_dev = NULL;
3812         return err;
3813 }
3814
3815 /* Write the short and long frame retry limit values. */
3816 static void b43_set_retry_limits(struct b43_wldev *dev,
3817                                  unsigned int short_retry,
3818                                  unsigned int long_retry)
3819 {
3820         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3821          * the chip-internal counter. */
3822         short_retry = min(short_retry, (unsigned int)0xF);
3823         long_retry = min(long_retry, (unsigned int)0xF);
3824
3825         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3826                         short_retry);
3827         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3828                         long_retry);
3829 }
3830
3831 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3832 {
3833         struct b43_wl *wl = hw_to_b43_wl(hw);
3834         struct b43_wldev *dev;
3835         struct b43_phy *phy;
3836         struct ieee80211_conf *conf = &hw->conf;
3837         int antenna;
3838         int err = 0;
3839         bool reload_bss = false;
3840
3841         mutex_lock(&wl->mutex);
3842
3843         dev = wl->current_dev;
3844
3845         /* Switch the band (if necessary). This might change the active core. */
3846         err = b43_switch_band(wl, conf->channel);
3847         if (err)
3848                 goto out_unlock_mutex;
3849
3850         /* Need to reload all settings if the core changed */
3851         if (dev != wl->current_dev) {
3852                 dev = wl->current_dev;
3853                 changed = ~0;
3854                 reload_bss = true;
3855         }
3856
3857         phy = &dev->phy;
3858
3859         if (conf_is_ht(conf))
3860                 phy->is_40mhz =
3861                         (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3862         else
3863                 phy->is_40mhz = false;
3864
3865         b43_mac_suspend(dev);
3866
3867         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3868                 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3869                                           conf->long_frame_max_tx_count);
3870         changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3871         if (!changed)
3872                 goto out_mac_enable;
3873
3874         /* Switch to the requested channel.
3875          * The firmware takes care of races with the TX handler. */
3876         if (conf->channel->hw_value != phy->channel)
3877                 b43_switch_channel(dev, conf->channel->hw_value);
3878
3879         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3880
3881         /* Adjust the desired TX power level. */
3882         if (conf->power_level != 0) {
3883                 if (conf->power_level != phy->desired_txpower) {
3884                         phy->desired_txpower = conf->power_level;
3885                         b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3886                                                    B43_TXPWR_IGNORE_TSSI);
3887                 }
3888         }
3889
3890         /* Antennas for RX and management frame TX. */
3891         antenna = B43_ANTENNA_DEFAULT;
3892         b43_mgmtframe_txantenna(dev, antenna);
3893         antenna = B43_ANTENNA_DEFAULT;
3894         if (phy->ops->set_rx_antenna)
3895                 phy->ops->set_rx_antenna(dev, antenna);
3896
3897         if (wl->radio_enabled != phy->radio_on) {
3898                 if (wl->radio_enabled) {
3899                         b43_software_rfkill(dev, false);
3900                         b43info(dev->wl, "Radio turned on by software\n");
3901                         if (!dev->radio_hw_enable) {
3902                                 b43info(dev->wl, "The hardware RF-kill button "
3903                                         "still turns the radio physically off. "
3904                                         "Press the button to turn it on.\n");
3905                         }
3906                 } else {
3907                         b43_software_rfkill(dev, true);
3908                         b43info(dev->wl, "Radio turned off by software\n");
3909                 }
3910         }
3911
3912 out_mac_enable:
3913         b43_mac_enable(dev);
3914 out_unlock_mutex:
3915         mutex_unlock(&wl->mutex);
3916
3917         if (wl->vif && reload_bss)
3918                 b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
3919
3920         return err;
3921 }
3922
3923 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3924 {
3925         struct ieee80211_supported_band *sband =
3926                 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3927         struct ieee80211_rate *rate;
3928         int i;
3929         u16 basic, direct, offset, basic_offset, rateptr;
3930
3931         for (i = 0; i < sband->n_bitrates; i++) {
3932                 rate = &sband->bitrates[i];
3933
3934                 if (b43_is_cck_rate(rate->hw_value)) {
3935                         direct = B43_SHM_SH_CCKDIRECT;
3936                         basic = B43_SHM_SH_CCKBASIC;
3937                         offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3938                         offset &= 0xF;
3939                 } else {
3940                         direct = B43_SHM_SH_OFDMDIRECT;
3941                         basic = B43_SHM_SH_OFDMBASIC;
3942                         offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3943                         offset &= 0xF;
3944                 }
3945
3946                 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3947
3948                 if (b43_is_cck_rate(rate->hw_value)) {
3949                         basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3950                         basic_offset &= 0xF;
3951                 } else {
3952                         basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3953                         basic_offset &= 0xF;
3954                 }
3955
3956                 /*
3957                  * Get the pointer that we need to point to
3958                  * from the direct map
3959                  */
3960                 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3961                                          direct + 2 * basic_offset);
3962                 /* and write it to the basic map */
3963                 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3964                                 rateptr);
3965         }
3966 }
3967
3968 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3969                                     struct ieee80211_vif *vif,
3970                                     struct ieee80211_bss_conf *conf,
3971                                     u32 changed)
3972 {
3973         struct b43_wl *wl = hw_to_b43_wl(hw);
3974         struct b43_wldev *dev;
3975
3976         mutex_lock(&wl->mutex);
3977
3978         dev = wl->current_dev;
3979         if (!dev || b43_status(dev) < B43_STAT_STARTED)
3980                 goto out_unlock_mutex;
3981
3982         B43_WARN_ON(wl->vif != vif);
3983
3984         if (changed & BSS_CHANGED_BSSID) {
3985                 if (conf->bssid)
3986                         memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3987                 else
3988                         memset(wl->bssid, 0, ETH_ALEN);
3989         }
3990
3991         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3992                 if (changed & BSS_CHANGED_BEACON &&
3993                     (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3994                      b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3995                      b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3996                         b43_update_templates(wl);
3997
3998                 if (changed & BSS_CHANGED_BSSID)
3999                         b43_write_mac_bssid_templates(dev);
4000         }
4001
4002         b43_mac_suspend(dev);
4003
4004         /* Update templates for AP/mesh mode. */
4005         if (changed & BSS_CHANGED_BEACON_INT &&
4006             (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
4007              b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
4008              b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
4009             conf->beacon_int)
4010                 b43_set_beacon_int(dev, conf->beacon_int);
4011
4012         if (changed & BSS_CHANGED_BASIC_RATES)
4013                 b43_update_basic_rates(dev, conf->basic_rates);
4014
4015         if (changed & BSS_CHANGED_ERP_SLOT) {
4016                 if (conf->use_short_slot)
4017                         b43_short_slot_timing_enable(dev);
4018                 else
4019                         b43_short_slot_timing_disable(dev);
4020         }
4021
4022         b43_mac_enable(dev);
4023 out_unlock_mutex:
4024         mutex_unlock(&wl->mutex);
4025 }
4026
4027 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
4028                           struct ieee80211_vif *vif, struct ieee80211_sta *sta,
4029                           struct ieee80211_key_conf *key)
4030 {
4031         struct b43_wl *wl = hw_to_b43_wl(hw);
4032         struct b43_wldev *dev;
4033         u8 algorithm;
4034         u8 index;
4035         int err;
4036         static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
4037
4038         if (modparam_nohwcrypt)
4039                 return -ENOSPC; /* User disabled HW-crypto */
4040
4041         mutex_lock(&wl->mutex);
4042
4043         dev = wl->current_dev;
4044         err = -ENODEV;
4045         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
4046                 goto out_unlock;
4047
4048         if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
4049                 /* We don't have firmware for the crypto engine.
4050                  * Must use software-crypto. */
4051                 err = -EOPNOTSUPP;
4052                 goto out_unlock;
4053         }
4054
4055         err = -EINVAL;
4056         switch (key->cipher) {
4057         case WLAN_CIPHER_SUITE_WEP40:
4058                 algorithm = B43_SEC_ALGO_WEP40;
4059                 break;
4060         case WLAN_CIPHER_SUITE_WEP104:
4061                 algorithm = B43_SEC_ALGO_WEP104;
4062                 break;
4063         case WLAN_CIPHER_SUITE_TKIP:
4064                 algorithm = B43_SEC_ALGO_TKIP;
4065                 break;
4066         case WLAN_CIPHER_SUITE_CCMP:
4067                 algorithm = B43_SEC_ALGO_AES;
4068                 break;
4069         default:
4070                 B43_WARN_ON(1);
4071                 goto out_unlock;
4072         }
4073         index = (u8) (key->keyidx);
4074         if (index > 3)
4075                 goto out_unlock;
4076
4077         switch (cmd) {
4078         case SET_KEY:
4079                 if (algorithm == B43_SEC_ALGO_TKIP &&
4080                     (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
4081                     !modparam_hwtkip)) {
4082                         /* We support only pairwise key */
4083                         err = -EOPNOTSUPP;
4084                         goto out_unlock;
4085                 }
4086
4087                 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
4088                         if (WARN_ON(!sta)) {
4089                                 err = -EOPNOTSUPP;
4090                                 goto out_unlock;
4091                         }
4092                         /* Pairwise key with an assigned MAC address. */
4093                         err = b43_key_write(dev, -1, algorithm,
4094                                             key->key, key->keylen,
4095                                             sta->addr, key);
4096                 } else {
4097                         /* Group key */
4098                         err = b43_key_write(dev, index, algorithm,
4099                                             key->key, key->keylen, NULL, key);
4100                 }
4101                 if (err)
4102                         goto out_unlock;
4103
4104                 if (algorithm == B43_SEC_ALGO_WEP40 ||
4105                     algorithm == B43_SEC_ALGO_WEP104) {
4106                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
4107                 } else {
4108                         b43_hf_write(dev,
4109                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
4110                 }
4111                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4112                 if (algorithm == B43_SEC_ALGO_TKIP)
4113                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
4114                 break;
4115         case DISABLE_KEY: {
4116                 err = b43_key_clear(dev, key->hw_key_idx);
4117                 if (err)
4118                         goto out_unlock;
4119                 break;
4120         }
4121         default:
4122                 B43_WARN_ON(1);
4123         }
4124
4125 out_unlock:
4126         if (!err) {
4127                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
4128                        "mac: %pM\n",
4129                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
4130                        sta ? sta->addr : bcast_addr);
4131                 b43_dump_keymemory(dev);
4132         }
4133         mutex_unlock(&wl->mutex);
4134
4135         return err;
4136 }
4137
4138 static void b43_op_configure_filter(struct ieee80211_hw *hw,
4139                                     unsigned int changed, unsigned int *fflags,
4140                                     u64 multicast)
4141 {
4142         struct b43_wl *wl = hw_to_b43_wl(hw);
4143         struct b43_wldev *dev;
4144
4145         mutex_lock(&wl->mutex);
4146         dev = wl->current_dev;
4147         if (!dev) {
4148                 *fflags = 0;
4149                 goto out_unlock;
4150         }
4151
4152         *fflags &= FIF_PROMISC_IN_BSS |
4153                   FIF_ALLMULTI |
4154                   FIF_FCSFAIL |
4155                   FIF_PLCPFAIL |
4156                   FIF_CONTROL |
4157                   FIF_OTHER_BSS |
4158                   FIF_BCN_PRBRESP_PROMISC;
4159
4160         changed &= FIF_PROMISC_IN_BSS |
4161                    FIF_ALLMULTI |
4162                    FIF_FCSFAIL |
4163                    FIF_PLCPFAIL |
4164                    FIF_CONTROL |
4165                    FIF_OTHER_BSS |
4166                    FIF_BCN_PRBRESP_PROMISC;
4167
4168         wl->filter_flags = *fflags;
4169
4170         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
4171                 b43_adjust_opmode(dev);
4172
4173 out_unlock:
4174         mutex_unlock(&wl->mutex);
4175 }
4176
4177 /* Locking: wl->mutex
4178  * Returns the current dev. This might be different from the passed in dev,
4179  * because the core might be gone away while we unlocked the mutex. */
4180 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
4181 {
4182         struct b43_wl *wl;
4183         struct b43_wldev *orig_dev;
4184         u32 mask;
4185         int queue_num;
4186
4187         if (!dev)
4188                 return NULL;
4189         wl = dev->wl;
4190 redo:
4191         if (!dev || b43_status(dev) < B43_STAT_STARTED)
4192                 return dev;
4193
4194         /* Cancel work. Unlock to avoid deadlocks. */
4195         mutex_unlock(&wl->mutex);
4196         cancel_delayed_work_sync(&dev->periodic_work);
4197         cancel_work_sync(&wl->tx_work);
4198         cancel_work_sync(&wl->firmware_load);
4199         mutex_lock(&wl->mutex);
4200         dev = wl->current_dev;
4201         if (!dev || b43_status(dev) < B43_STAT_STARTED) {
4202                 /* Whoops, aliens ate up the device while we were unlocked. */
4203                 return dev;
4204         }
4205
4206         /* Disable interrupts on the device. */
4207         b43_set_status(dev, B43_STAT_INITIALIZED);
4208         if (b43_bus_host_is_sdio(dev->dev)) {
4209                 /* wl->mutex is locked. That is enough. */
4210                 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4211                 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4212         } else {
4213                 spin_lock_irq(&wl->hardirq_lock);
4214                 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
4215                 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
4216                 spin_unlock_irq(&wl->hardirq_lock);
4217         }
4218         /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
4219         orig_dev = dev;
4220         mutex_unlock(&wl->mutex);
4221         if (b43_bus_host_is_sdio(dev->dev)) {
4222                 b43_sdio_free_irq(dev);
4223         } else {
4224                 synchronize_irq(dev->dev->irq);
4225                 free_irq(dev->dev->irq, dev);
4226         }
4227         mutex_lock(&wl->mutex);
4228         dev = wl->current_dev;
4229         if (!dev)
4230                 return dev;
4231         if (dev != orig_dev) {
4232                 if (b43_status(dev) >= B43_STAT_STARTED)
4233                         goto redo;
4234                 return dev;
4235         }
4236         mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
4237         B43_WARN_ON(mask != 0xFFFFFFFF && mask);
4238
4239         /* Drain all TX queues. */
4240         for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
4241                 while (skb_queue_len(&wl->tx_queue[queue_num])) {
4242                         struct sk_buff *skb;
4243
4244                         skb = skb_dequeue(&wl->tx_queue[queue_num]);
4245                         ieee80211_free_txskb(wl->hw, skb);
4246                 }
4247         }
4248
4249         b43_mac_suspend(dev);
4250         b43_leds_exit(dev);
4251         b43dbg(wl, "Wireless interface stopped\n");
4252
4253         return dev;
4254 }
4255
4256 /* Locking: wl->mutex */
4257 static int b43_wireless_core_start(struct b43_wldev *dev)
4258 {
4259         int err;
4260
4261         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4262
4263         drain_txstatus_queue(dev);
4264         if (b43_bus_host_is_sdio(dev->dev)) {
4265                 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4266                 if (err) {
4267                         b43err(dev->wl, "Cannot request SDIO IRQ\n");
4268                         goto out;
4269                 }
4270         } else {
4271                 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4272                                            b43_interrupt_thread_handler,
4273                                            IRQF_SHARED, KBUILD_MODNAME, dev);
4274                 if (err) {
4275                         b43err(dev->wl, "Cannot request IRQ-%d\n",
4276                                dev->dev->irq);
4277                         goto out;
4278                 }
4279         }
4280
4281         /* We are ready to run. */
4282         ieee80211_wake_queues(dev->wl->hw);
4283         b43_set_status(dev, B43_STAT_STARTED);
4284
4285         /* Start data flow (TX/RX). */
4286         b43_mac_enable(dev);
4287         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
4288
4289         /* Start maintenance work */
4290         b43_periodic_tasks_setup(dev);
4291
4292         b43_leds_init(dev);
4293
4294         b43dbg(dev->wl, "Wireless interface started\n");
4295 out:
4296         return err;
4297 }
4298
4299 /* Get PHY and RADIO versioning numbers */
4300 static int b43_phy_versioning(struct b43_wldev *dev)
4301 {
4302         struct b43_phy *phy = &dev->phy;
4303         u32 tmp;
4304         u8 analog_type;
4305         u8 phy_type;
4306         u8 phy_rev;
4307         u16 radio_manuf;
4308         u16 radio_ver;
4309         u16 radio_rev;
4310         int unsupported = 0;
4311
4312         /* Get PHY versioning */
4313         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4314         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4315         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4316         phy_rev = (tmp & B43_PHYVER_VERSION);
4317         switch (phy_type) {
4318         case B43_PHYTYPE_A:
4319                 if (phy_rev >= 4)
4320                         unsupported = 1;
4321                 break;
4322         case B43_PHYTYPE_B:
4323                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4324                     && phy_rev != 7)
4325                         unsupported = 1;
4326                 break;
4327         case B43_PHYTYPE_G:
4328                 if (phy_rev > 9)
4329                         unsupported = 1;
4330                 break;
4331 #ifdef CONFIG_B43_PHY_N
4332         case B43_PHYTYPE_N:
4333                 if (phy_rev > 9)
4334                         unsupported = 1;
4335                 break;
4336 #endif
4337 #ifdef CONFIG_B43_PHY_LP
4338         case B43_PHYTYPE_LP:
4339                 if (phy_rev > 2)
4340                         unsupported = 1;
4341                 break;
4342 #endif
4343 #ifdef CONFIG_B43_PHY_HT
4344         case B43_PHYTYPE_HT:
4345                 if (phy_rev > 1)
4346                         unsupported = 1;
4347                 break;
4348 #endif
4349 #ifdef CONFIG_B43_PHY_LCN
4350         case B43_PHYTYPE_LCN:
4351                 if (phy_rev > 1)
4352                         unsupported = 1;
4353                 break;
4354 #endif
4355         default:
4356                 unsupported = 1;
4357         }
4358         if (unsupported) {
4359                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4360                        "(Analog %u, Type %u, Revision %u)\n",
4361                        analog_type, phy_type, phy_rev);
4362                 return -EOPNOTSUPP;
4363         }
4364         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4365                analog_type, phy_type, phy_rev);
4366
4367         /* Get RADIO versioning */
4368         if (dev->dev->core_rev >= 24) {
4369                 u16 radio24[3];
4370
4371                 for (tmp = 0; tmp < 3; tmp++) {
4372                         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4373                         radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4374                 }
4375
4376                 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4377                 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4378
4379                 radio_manuf = 0x17F;
4380                 radio_ver = (radio24[2] << 8) | radio24[1];
4381                 radio_rev = (radio24[0] & 0xF);
4382         } else {
4383                 if (dev->dev->chip_id == 0x4317) {
4384                         if (dev->dev->chip_rev == 0)
4385                                 tmp = 0x3205017F;
4386                         else if (dev->dev->chip_rev == 1)
4387                                 tmp = 0x4205017F;
4388                         else
4389                                 tmp = 0x5205017F;
4390                 } else {
4391                         b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4392                                     B43_RADIOCTL_ID);
4393                         tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4394                         b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4395                                     B43_RADIOCTL_ID);
4396                         tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4397                                 << 16;
4398                 }
4399                 radio_manuf = (tmp & 0x00000FFF);
4400                 radio_ver = (tmp & 0x0FFFF000) >> 12;
4401                 radio_rev = (tmp & 0xF0000000) >> 28;
4402         }
4403
4404         if (radio_manuf != 0x17F /* Broadcom */)
4405                 unsupported = 1;
4406         switch (phy_type) {
4407         case B43_PHYTYPE_A:
4408                 if (radio_ver != 0x2060)
4409                         unsupported = 1;
4410                 if (radio_rev != 1)
4411                         unsupported = 1;
4412                 if (radio_manuf != 0x17F)
4413                         unsupported = 1;
4414                 break;
4415         case B43_PHYTYPE_B:
4416                 if ((radio_ver & 0xFFF0) != 0x2050)
4417                         unsupported = 1;
4418                 break;
4419         case B43_PHYTYPE_G:
4420                 if (radio_ver != 0x2050)
4421                         unsupported = 1;
4422                 break;
4423         case B43_PHYTYPE_N:
4424                 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4425                         unsupported = 1;
4426                 break;
4427         case B43_PHYTYPE_LP:
4428                 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4429                         unsupported = 1;
4430                 break;
4431         case B43_PHYTYPE_HT:
4432                 if (radio_ver != 0x2059)
4433                         unsupported = 1;
4434                 break;
4435         case B43_PHYTYPE_LCN:
4436                 if (radio_ver != 0x2064)
4437                         unsupported = 1;
4438                 break;
4439         default:
4440                 B43_WARN_ON(1);
4441         }
4442         if (unsupported) {
4443                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4444                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4445                        radio_manuf, radio_ver, radio_rev);
4446                 return -EOPNOTSUPP;
4447         }
4448         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4449                radio_manuf, radio_ver, radio_rev);
4450
4451         phy->radio_manuf = radio_manuf;
4452         phy->radio_ver = radio_ver;
4453         phy->radio_rev = radio_rev;
4454
4455         phy->analog = analog_type;
4456         phy->type = phy_type;
4457         phy->rev = phy_rev;
4458
4459         return 0;
4460 }
4461
4462 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4463                                       struct b43_phy *phy)
4464 {
4465         phy->hardware_power_control = !!modparam_hwpctl;
4466         phy->next_txpwr_check_time = jiffies;
4467         /* PHY TX errors counter. */
4468         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4469
4470 #if B43_DEBUG
4471         phy->phy_locked = false;
4472         phy->radio_locked = false;
4473 #endif
4474 }
4475
4476 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4477 {
4478         dev->dfq_valid = false;
4479
4480         /* Assume the radio is enabled. If it's not enabled, the state will
4481          * immediately get fixed on the first periodic work run. */
4482         dev->radio_hw_enable = true;
4483
4484         /* Stats */
4485         memset(&dev->stats, 0, sizeof(dev->stats));
4486
4487         setup_struct_phy_for_init(dev, &dev->phy);
4488
4489         /* IRQ related flags */
4490         dev->irq_reason = 0;
4491         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4492         dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4493         if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4494                 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4495
4496         dev->mac_suspended = 1;
4497
4498         /* Noise calculation context */
4499         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4500 }
4501
4502 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4503 {
4504         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4505         u64 hf;
4506
4507         if (!modparam_btcoex)
4508                 return;
4509         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4510                 return;
4511         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4512                 return;
4513
4514         hf = b43_hf_read(dev);
4515         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4516                 hf |= B43_HF_BTCOEXALT;
4517         else
4518                 hf |= B43_HF_BTCOEX;
4519         b43_hf_write(dev, hf);
4520 }
4521
4522 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4523 {
4524         if (!modparam_btcoex)
4525                 return;
4526         //TODO
4527 }
4528
4529 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4530 {
4531         struct ssb_bus *bus;
4532         u32 tmp;
4533
4534         if (dev->dev->bus_type != B43_BUS_SSB)
4535                 return;
4536
4537         bus = dev->dev->sdev->bus;
4538
4539         if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4540             (bus->chip_id == 0x4312)) {
4541                 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4542                 tmp &= ~SSB_IMCFGLO_REQTO;
4543                 tmp &= ~SSB_IMCFGLO_SERTO;
4544                 tmp |= 0x3;
4545                 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4546                 ssb_commit_settings(bus);
4547         }
4548 }
4549
4550 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4551 {
4552         u16 pu_delay;
4553
4554         /* The time value is in microseconds. */
4555         if (dev->phy.type == B43_PHYTYPE_A)
4556                 pu_delay = 3700;
4557         else
4558                 pu_delay = 1050;
4559         if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4560                 pu_delay = 500;
4561         if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4562                 pu_delay = max(pu_delay, (u16)2400);
4563
4564         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4565 }
4566
4567 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4568 static void b43_set_pretbtt(struct b43_wldev *dev)
4569 {
4570         u16 pretbtt;
4571
4572         /* The time value is in microseconds. */
4573         if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4574                 pretbtt = 2;
4575         } else {
4576                 if (dev->phy.type == B43_PHYTYPE_A)
4577                         pretbtt = 120;
4578                 else
4579                         pretbtt = 250;
4580         }
4581         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4582         b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4583 }
4584
4585 /* Shutdown a wireless core */
4586 /* Locking: wl->mutex */
4587 static void b43_wireless_core_exit(struct b43_wldev *dev)
4588 {
4589         B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4590         if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4591                 return;
4592
4593         /* Unregister HW RNG driver */
4594         b43_rng_exit(dev->wl);
4595
4596         b43_set_status(dev, B43_STAT_UNINIT);
4597
4598         /* Stop the microcode PSM. */
4599         b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
4600                       B43_MACCTL_PSM_JMP0);
4601
4602         b43_dma_free(dev);
4603         b43_pio_free(dev);
4604         b43_chip_exit(dev);
4605         dev->phy.ops->switch_analog(dev, 0);
4606         if (dev->wl->current_beacon) {
4607                 dev_kfree_skb_any(dev->wl->current_beacon);
4608                 dev->wl->current_beacon = NULL;
4609         }
4610
4611         b43_device_disable(dev, 0);
4612         b43_bus_may_powerdown(dev);
4613 }
4614
4615 /* Initialize a wireless core */
4616 static int b43_wireless_core_init(struct b43_wldev *dev)
4617 {
4618         struct ssb_sprom *sprom = dev->dev->bus_sprom;
4619         struct b43_phy *phy = &dev->phy;
4620         int err;
4621         u64 hf;
4622
4623         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4624
4625         err = b43_bus_powerup(dev, 0);
4626         if (err)
4627                 goto out;
4628         if (!b43_device_is_enabled(dev))
4629                 b43_wireless_core_reset(dev, phy->gmode);
4630
4631         /* Reset all data structures. */
4632         setup_struct_wldev_for_init(dev);
4633         phy->ops->prepare_structs(dev);
4634
4635         /* Enable IRQ routing to this device. */
4636         switch (dev->dev->bus_type) {
4637 #ifdef CONFIG_B43_BCMA
4638         case B43_BUS_BCMA:
4639                 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4640                                       dev->dev->bdev, true);
4641                 break;
4642 #endif
4643 #ifdef CONFIG_B43_SSB
4644         case B43_BUS_SSB:
4645                 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4646                                                dev->dev->sdev);
4647                 break;
4648 #endif
4649         }
4650
4651         b43_imcfglo_timeouts_workaround(dev);
4652         b43_bluetooth_coext_disable(dev);
4653         if (phy->ops->prepare_hardware) {
4654                 err = phy->ops->prepare_hardware(dev);
4655                 if (err)
4656                         goto err_busdown;
4657         }
4658         err = b43_chip_init(dev);
4659         if (err)
4660                 goto err_busdown;
4661         b43_shm_write16(dev, B43_SHM_SHARED,
4662                         B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4663         hf = b43_hf_read(dev);
4664         if (phy->type == B43_PHYTYPE_G) {
4665                 hf |= B43_HF_SYMW;
4666                 if (phy->rev == 1)
4667                         hf |= B43_HF_GDCW;
4668                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4669                         hf |= B43_HF_OFDMPABOOST;
4670         }
4671         if (phy->radio_ver == 0x2050) {
4672                 if (phy->radio_rev == 6)
4673                         hf |= B43_HF_4318TSSI;
4674                 if (phy->radio_rev < 6)
4675                         hf |= B43_HF_VCORECALC;
4676         }
4677         if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4678                 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4679 #ifdef CONFIG_SSB_DRIVER_PCICORE
4680         if (dev->dev->bus_type == B43_BUS_SSB &&
4681             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4682             dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4683                 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4684 #endif
4685         hf &= ~B43_HF_SKCFPUP;
4686         b43_hf_write(dev, hf);
4687
4688         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4689                              B43_DEFAULT_LONG_RETRY_LIMIT);
4690         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4691         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4692
4693         /* Disable sending probe responses from firmware.
4694          * Setting the MaxTime to one usec will always trigger
4695          * a timeout, so we never send any probe resp.
4696          * A timeout of zero is infinite. */
4697         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4698
4699         b43_rate_memory_init(dev);
4700         b43_set_phytxctl_defaults(dev);
4701
4702         /* Minimum Contention Window */
4703         if (phy->type == B43_PHYTYPE_B)
4704                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4705         else
4706                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4707         /* Maximum Contention Window */
4708         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4709
4710         if (b43_bus_host_is_pcmcia(dev->dev) ||
4711             b43_bus_host_is_sdio(dev->dev)) {
4712                 dev->__using_pio_transfers = true;
4713                 err = b43_pio_init(dev);
4714         } else if (dev->use_pio) {
4715                 b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
4716                         "This should not be needed and will result in lower "
4717                         "performance.\n");
4718                 dev->__using_pio_transfers = true;
4719                 err = b43_pio_init(dev);
4720         } else {
4721                 dev->__using_pio_transfers = false;
4722                 err = b43_dma_init(dev);
4723         }
4724         if (err)
4725                 goto err_chip_exit;
4726         b43_qos_init(dev);
4727         b43_set_synth_pu_delay(dev, 1);
4728         b43_bluetooth_coext_enable(dev);
4729
4730         b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4731         b43_upload_card_macaddress(dev);
4732         b43_security_init(dev);
4733
4734         ieee80211_wake_queues(dev->wl->hw);
4735
4736         b43_set_status(dev, B43_STAT_INITIALIZED);
4737
4738         /* Register HW RNG driver */
4739         b43_rng_init(dev->wl);
4740
4741 out:
4742         return err;
4743
4744 err_chip_exit:
4745         b43_chip_exit(dev);
4746 err_busdown:
4747         b43_bus_may_powerdown(dev);
4748         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4749         return err;
4750 }
4751
4752 static int b43_op_add_interface(struct ieee80211_hw *hw,
4753                                 struct ieee80211_vif *vif)
4754 {
4755         struct b43_wl *wl = hw_to_b43_wl(hw);
4756         struct b43_wldev *dev;
4757         int err = -EOPNOTSUPP;
4758
4759         /* TODO: allow WDS/AP devices to coexist */
4760
4761         if (vif->type != NL80211_IFTYPE_AP &&
4762             vif->type != NL80211_IFTYPE_MESH_POINT &&
4763             vif->type != NL80211_IFTYPE_STATION &&
4764             vif->type != NL80211_IFTYPE_WDS &&
4765             vif->type != NL80211_IFTYPE_ADHOC)
4766                 return -EOPNOTSUPP;
4767
4768         mutex_lock(&wl->mutex);
4769         if (wl->operating)
4770                 goto out_mutex_unlock;
4771
4772         b43dbg(wl, "Adding Interface type %d\n", vif->type);
4773
4774         dev = wl->current_dev;
4775         wl->operating = true;
4776         wl->vif = vif;
4777         wl->if_type = vif->type;
4778         memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4779
4780         b43_adjust_opmode(dev);
4781         b43_set_pretbtt(dev);
4782         b43_set_synth_pu_delay(dev, 0);
4783         b43_upload_card_macaddress(dev);
4784
4785         err = 0;
4786  out_mutex_unlock:
4787         mutex_unlock(&wl->mutex);
4788
4789         if (err == 0)
4790                 b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
4791
4792         return err;
4793 }
4794
4795 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4796                                     struct ieee80211_vif *vif)
4797 {
4798         struct b43_wl *wl = hw_to_b43_wl(hw);
4799         struct b43_wldev *dev = wl->current_dev;
4800
4801         b43dbg(wl, "Removing Interface type %d\n", vif->type);
4802
4803         mutex_lock(&wl->mutex);
4804
4805         B43_WARN_ON(!wl->operating);
4806         B43_WARN_ON(wl->vif != vif);
4807         wl->vif = NULL;
4808
4809         wl->operating = false;
4810
4811         b43_adjust_opmode(dev);
4812         memset(wl->mac_addr, 0, ETH_ALEN);
4813         b43_upload_card_macaddress(dev);
4814
4815         mutex_unlock(&wl->mutex);
4816 }
4817
4818 static int b43_op_start(struct ieee80211_hw *hw)
4819 {
4820         struct b43_wl *wl = hw_to_b43_wl(hw);
4821         struct b43_wldev *dev = wl->current_dev;
4822         int did_init = 0;
4823         int err = 0;
4824
4825         /* Kill all old instance specific information to make sure
4826          * the card won't use it in the short timeframe between start
4827          * and mac80211 reconfiguring it. */
4828         memset(wl->bssid, 0, ETH_ALEN);
4829         memset(wl->mac_addr, 0, ETH_ALEN);
4830         wl->filter_flags = 0;
4831         wl->radiotap_enabled = false;
4832         b43_qos_clear(wl);
4833         wl->beacon0_uploaded = false;
4834         wl->beacon1_uploaded = false;
4835         wl->beacon_templates_virgin = true;
4836         wl->radio_enabled = true;
4837
4838         mutex_lock(&wl->mutex);
4839
4840         if (b43_status(dev) < B43_STAT_INITIALIZED) {
4841                 err = b43_wireless_core_init(dev);
4842                 if (err)
4843                         goto out_mutex_unlock;
4844                 did_init = 1;
4845         }
4846
4847         if (b43_status(dev) < B43_STAT_STARTED) {
4848                 err = b43_wireless_core_start(dev);
4849                 if (err) {
4850                         if (did_init)
4851                                 b43_wireless_core_exit(dev);
4852                         goto out_mutex_unlock;
4853                 }
4854         }
4855
4856         /* XXX: only do if device doesn't support rfkill irq */
4857         wiphy_rfkill_start_polling(hw->wiphy);
4858
4859  out_mutex_unlock:
4860         mutex_unlock(&wl->mutex);
4861
4862         /*
4863          * Configuration may have been overwritten during initialization.
4864          * Reload the configuration, but only if initialization was
4865          * successful. Reloading the configuration after a failed init
4866          * may hang the system.
4867          */
4868         if (!err)
4869                 b43_op_config(hw, ~0);
4870
4871         return err;
4872 }
4873
4874 static void b43_op_stop(struct ieee80211_hw *hw)
4875 {
4876         struct b43_wl *wl = hw_to_b43_wl(hw);
4877         struct b43_wldev *dev = wl->current_dev;
4878
4879         cancel_work_sync(&(wl->beacon_update_trigger));
4880
4881         if (!dev)
4882                 goto out;
4883
4884         mutex_lock(&wl->mutex);
4885         if (b43_status(dev) >= B43_STAT_STARTED) {
4886                 dev = b43_wireless_core_stop(dev);
4887                 if (!dev)
4888                         goto out_unlock;
4889         }
4890         b43_wireless_core_exit(dev);
4891         wl->radio_enabled = false;
4892
4893 out_unlock:
4894         mutex_unlock(&wl->mutex);
4895 out:
4896         cancel_work_sync(&(wl->txpower_adjust_work));
4897 }
4898
4899 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4900                                  struct ieee80211_sta *sta, bool set)
4901 {
4902         struct b43_wl *wl = hw_to_b43_wl(hw);
4903
4904         /* FIXME: add locking */
4905         b43_update_templates(wl);
4906
4907         return 0;
4908 }
4909
4910 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4911                               struct ieee80211_vif *vif,
4912                               enum sta_notify_cmd notify_cmd,
4913                               struct ieee80211_sta *sta)
4914 {
4915         struct b43_wl *wl = hw_to_b43_wl(hw);
4916
4917         B43_WARN_ON(!vif || wl->vif != vif);
4918 }
4919
4920 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4921 {
4922         struct b43_wl *wl = hw_to_b43_wl(hw);
4923         struct b43_wldev *dev;
4924
4925         mutex_lock(&wl->mutex);
4926         dev = wl->current_dev;
4927         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4928                 /* Disable CFP update during scan on other channels. */
4929                 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4930         }
4931         mutex_unlock(&wl->mutex);
4932 }
4933
4934 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4935 {
4936         struct b43_wl *wl = hw_to_b43_wl(hw);
4937         struct b43_wldev *dev;
4938
4939         mutex_lock(&wl->mutex);
4940         dev = wl->current_dev;
4941         if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4942                 /* Re-enable CFP update. */
4943                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4944         }
4945         mutex_unlock(&wl->mutex);
4946 }
4947
4948 static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
4949                              struct survey_info *survey)
4950 {
4951         struct b43_wl *wl = hw_to_b43_wl(hw);
4952         struct b43_wldev *dev = wl->current_dev;
4953         struct ieee80211_conf *conf = &hw->conf;
4954
4955         if (idx != 0)
4956                 return -ENOENT;
4957
4958         survey->channel = conf->channel;
4959         survey->filled = SURVEY_INFO_NOISE_DBM;
4960         survey->noise = dev->stats.link_noise;
4961
4962         return 0;
4963 }
4964
4965 static const struct ieee80211_ops b43_hw_ops = {
4966         .tx                     = b43_op_tx,
4967         .conf_tx                = b43_op_conf_tx,
4968         .add_interface          = b43_op_add_interface,
4969         .remove_interface       = b43_op_remove_interface,
4970         .config                 = b43_op_config,
4971         .bss_info_changed       = b43_op_bss_info_changed,
4972         .configure_filter       = b43_op_configure_filter,
4973         .set_key                = b43_op_set_key,
4974         .update_tkip_key        = b43_op_update_tkip_key,
4975         .get_stats              = b43_op_get_stats,
4976         .get_tsf                = b43_op_get_tsf,
4977         .set_tsf                = b43_op_set_tsf,
4978         .start                  = b43_op_start,
4979         .stop                   = b43_op_stop,
4980         .set_tim                = b43_op_beacon_set_tim,
4981         .sta_notify             = b43_op_sta_notify,
4982         .sw_scan_start          = b43_op_sw_scan_start_notifier,
4983         .sw_scan_complete       = b43_op_sw_scan_complete_notifier,
4984         .get_survey             = b43_op_get_survey,
4985         .rfkill_poll            = b43_rfkill_poll,
4986 };
4987
4988 /* Hard-reset the chip. Do not call this directly.
4989  * Use b43_controller_restart()
4990  */
4991 static void b43_chip_reset(struct work_struct *work)
4992 {
4993         struct b43_wldev *dev =
4994             container_of(work, struct b43_wldev, restart_work);
4995         struct b43_wl *wl = dev->wl;
4996         int err = 0;
4997         int prev_status;
4998
4999         mutex_lock(&wl->mutex);
5000
5001         prev_status = b43_status(dev);
5002         /* Bring the device down... */
5003         if (prev_status >= B43_STAT_STARTED) {
5004                 dev = b43_wireless_core_stop(dev);
5005                 if (!dev) {
5006                         err = -ENODEV;
5007                         goto out;
5008                 }
5009         }
5010         if (prev_status >= B43_STAT_INITIALIZED)
5011                 b43_wireless_core_exit(dev);
5012
5013         /* ...and up again. */
5014         if (prev_status >= B43_STAT_INITIALIZED) {
5015                 err = b43_wireless_core_init(dev);
5016                 if (err)
5017                         goto out;
5018         }
5019         if (prev_status >= B43_STAT_STARTED) {
5020                 err = b43_wireless_core_start(dev);
5021                 if (err) {
5022                         b43_wireless_core_exit(dev);
5023                         goto out;
5024                 }
5025         }
5026 out:
5027         if (err)
5028                 wl->current_dev = NULL; /* Failed to init the dev. */
5029         mutex_unlock(&wl->mutex);
5030
5031         if (err) {
5032                 b43err(wl, "Controller restart FAILED\n");
5033                 return;
5034         }
5035
5036         /* reload configuration */
5037         b43_op_config(wl->hw, ~0);
5038         if (wl->vif)
5039                 b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
5040
5041         b43info(wl, "Controller restarted\n");
5042 }
5043
5044 static int b43_setup_bands(struct b43_wldev *dev,
5045                            bool have_2ghz_phy, bool have_5ghz_phy)
5046 {
5047         struct ieee80211_hw *hw = dev->wl->hw;
5048
5049         if (have_2ghz_phy)
5050                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
5051         if (dev->phy.type == B43_PHYTYPE_N) {
5052                 if (have_5ghz_phy)
5053                         hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
5054         } else {
5055                 if (have_5ghz_phy)
5056                         hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
5057         }
5058
5059         dev->phy.supports_2ghz = have_2ghz_phy;
5060         dev->phy.supports_5ghz = have_5ghz_phy;
5061
5062         return 0;
5063 }
5064
5065 static void b43_wireless_core_detach(struct b43_wldev *dev)
5066 {
5067         /* We release firmware that late to not be required to re-request
5068          * is all the time when we reinit the core. */
5069         b43_release_firmware(dev);
5070         b43_phy_free(dev);
5071 }
5072
5073 static int b43_wireless_core_attach(struct b43_wldev *dev)
5074 {
5075         struct b43_wl *wl = dev->wl;
5076         struct pci_dev *pdev = NULL;
5077         int err;
5078         u32 tmp;
5079         bool have_2ghz_phy = false, have_5ghz_phy = false;
5080
5081         /* Do NOT do any device initialization here.
5082          * Do it in wireless_core_init() instead.
5083          * This function is for gathering basic information about the HW, only.
5084          * Also some structs may be set up here. But most likely you want to have
5085          * that in core_init(), too.
5086          */
5087
5088 #ifdef CONFIG_B43_SSB
5089         if (dev->dev->bus_type == B43_BUS_SSB &&
5090             dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
5091                 pdev = dev->dev->sdev->bus->host_pci;
5092 #endif
5093
5094         err = b43_bus_powerup(dev, 0);
5095         if (err) {
5096                 b43err(wl, "Bus powerup failed\n");
5097                 goto out;
5098         }
5099
5100         /* Get the PHY type. */
5101         switch (dev->dev->bus_type) {
5102 #ifdef CONFIG_B43_BCMA
5103         case B43_BUS_BCMA:
5104                 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
5105                 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
5106                 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5107                 break;
5108 #endif
5109 #ifdef CONFIG_B43_SSB
5110         case B43_BUS_SSB:
5111                 if (dev->dev->core_rev >= 5) {
5112                         tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5113                         have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5114                         have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5115                 } else
5116                         B43_WARN_ON(1);
5117                 break;
5118 #endif
5119         }
5120
5121         dev->phy.gmode = have_2ghz_phy;
5122         dev->phy.radio_on = true;
5123         b43_wireless_core_reset(dev, dev->phy.gmode);
5124
5125         err = b43_phy_versioning(dev);
5126         if (err)
5127                 goto err_powerdown;
5128         /* Check if this device supports multiband. */
5129         if (!pdev ||
5130             (pdev->device != 0x4312 &&
5131              pdev->device != 0x4319 && pdev->device != 0x4324)) {
5132                 /* No multiband support. */
5133                 have_2ghz_phy = false;
5134                 have_5ghz_phy = false;
5135                 switch (dev->phy.type) {
5136                 case B43_PHYTYPE_A:
5137                         have_5ghz_phy = true;
5138                         break;
5139                 case B43_PHYTYPE_LP: //FIXME not always!
5140 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
5141                         have_5ghz_phy = 1;
5142 #endif
5143                 case B43_PHYTYPE_G:
5144                 case B43_PHYTYPE_N:
5145                 case B43_PHYTYPE_HT:
5146                 case B43_PHYTYPE_LCN:
5147                         have_2ghz_phy = true;
5148                         break;
5149                 default:
5150                         B43_WARN_ON(1);
5151                 }
5152         }
5153         if (dev->phy.type == B43_PHYTYPE_A) {
5154                 /* FIXME */
5155                 b43err(wl, "IEEE 802.11a devices are unsupported\n");
5156                 err = -EOPNOTSUPP;
5157                 goto err_powerdown;
5158         }
5159         if (1 /* disable A-PHY */) {
5160                 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
5161                 if (dev->phy.type != B43_PHYTYPE_N &&
5162                     dev->phy.type != B43_PHYTYPE_LP) {
5163                         have_2ghz_phy = true;
5164                         have_5ghz_phy = false;
5165                 }
5166         }
5167
5168         err = b43_phy_allocate(dev);
5169         if (err)
5170                 goto err_powerdown;
5171
5172         dev->phy.gmode = have_2ghz_phy;
5173         b43_wireless_core_reset(dev, dev->phy.gmode);
5174
5175         err = b43_validate_chipaccess(dev);
5176         if (err)
5177                 goto err_phy_free;
5178         err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
5179         if (err)
5180                 goto err_phy_free;
5181
5182         /* Now set some default "current_dev" */
5183         if (!wl->current_dev)
5184                 wl->current_dev = dev;
5185         INIT_WORK(&dev->restart_work, b43_chip_reset);
5186
5187         dev->phy.ops->switch_analog(dev, 0);
5188         b43_device_disable(dev, 0);
5189         b43_bus_may_powerdown(dev);
5190
5191 out:
5192         return err;
5193
5194 err_phy_free:
5195         b43_phy_free(dev);
5196 err_powerdown:
5197         b43_bus_may_powerdown(dev);
5198         return err;
5199 }
5200
5201 static void b43_one_core_detach(struct b43_bus_dev *dev)
5202 {
5203         struct b43_wldev *wldev;
5204         struct b43_wl *wl;
5205
5206         /* Do not cancel ieee80211-workqueue based work here.
5207          * See comment in b43_remove(). */
5208
5209         wldev = b43_bus_get_wldev(dev);
5210         wl = wldev->wl;
5211         b43_debugfs_remove_device(wldev);
5212         b43_wireless_core_detach(wldev);
5213         list_del(&wldev->list);
5214         wl->nr_devs--;
5215         b43_bus_set_wldev(dev, NULL);
5216         kfree(wldev);
5217 }
5218
5219 static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
5220 {
5221         struct b43_wldev *wldev;
5222         int err = -ENOMEM;
5223
5224         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
5225         if (!wldev)
5226                 goto out;
5227
5228         wldev->use_pio = b43_modparam_pio;
5229         wldev->dev = dev;
5230         wldev->wl = wl;
5231         b43_set_status(wldev, B43_STAT_UNINIT);
5232         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
5233         INIT_LIST_HEAD(&wldev->list);
5234
5235         err = b43_wireless_core_attach(wldev);
5236         if (err)
5237                 goto err_kfree_wldev;
5238
5239         list_add(&wldev->list, &wl->devlist);
5240         wl->nr_devs++;
5241         b43_bus_set_wldev(dev, wldev);
5242         b43_debugfs_add_device(wldev);
5243
5244       out:
5245         return err;
5246
5247       err_kfree_wldev:
5248         kfree(wldev);
5249         return err;
5250 }
5251
5252 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice)         ( \
5253         (pdev->vendor == PCI_VENDOR_ID_##_vendor) &&                    \
5254         (pdev->device == _device) &&                                    \
5255         (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) &&       \
5256         (pdev->subsystem_device == _subdevice)                          )
5257
5258 static void b43_sprom_fixup(struct ssb_bus *bus)
5259 {
5260         struct pci_dev *pdev;
5261
5262         /* boardflags workarounds */
5263         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
5264             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
5265                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
5266         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
5267             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
5268                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
5269         if (bus->bustype == SSB_BUSTYPE_PCI) {
5270                 pdev = bus->host_pci;
5271                 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
5272                     IS_PDEV(pdev, BROADCOM, 0x4320,    DELL, 0x0003) ||
5273                     IS_PDEV(pdev, BROADCOM, 0x4320,      HP, 0x12f8) ||
5274                     IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
5275                     IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
5276                     IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
5277                     IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
5278                         bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
5279         }
5280 }
5281
5282 static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
5283 {
5284         struct ieee80211_hw *hw = wl->hw;
5285
5286         ssb_set_devtypedata(dev->sdev, NULL);
5287         ieee80211_free_hw(hw);
5288 }
5289
5290 static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
5291 {
5292         struct ssb_sprom *sprom = dev->bus_sprom;
5293         struct ieee80211_hw *hw;
5294         struct b43_wl *wl;
5295         char chip_name[6];
5296         int queue_num;
5297
5298         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
5299         if (!hw) {
5300                 b43err(NULL, "Could not allocate ieee80211 device\n");
5301                 return ERR_PTR(-ENOMEM);
5302         }
5303         wl = hw_to_b43_wl(hw);
5304
5305         /* fill hw info */
5306         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
5307                     IEEE80211_HW_SIGNAL_DBM;
5308
5309         hw->wiphy->interface_modes =
5310                 BIT(NL80211_IFTYPE_AP) |
5311                 BIT(NL80211_IFTYPE_MESH_POINT) |
5312                 BIT(NL80211_IFTYPE_STATION) |
5313                 BIT(NL80211_IFTYPE_WDS) |
5314                 BIT(NL80211_IFTYPE_ADHOC);
5315
5316         hw->queues = modparam_qos ? B43_QOS_QUEUE_NUM : 1;
5317         wl->mac80211_initially_registered_queues = hw->queues;
5318         hw->max_rates = 2;
5319         SET_IEEE80211_DEV(hw, dev->dev);
5320         if (is_valid_ether_addr(sprom->et1mac))
5321                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
5322         else
5323                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
5324
5325         /* Initialize struct b43_wl */
5326         wl->hw = hw;
5327         mutex_init(&wl->mutex);
5328         spin_lock_init(&wl->hardirq_lock);
5329         INIT_LIST_HEAD(&wl->devlist);
5330         INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
5331         INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
5332         INIT_WORK(&wl->tx_work, b43_tx_work);
5333
5334         /* Initialize queues and flags. */
5335         for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
5336                 skb_queue_head_init(&wl->tx_queue[queue_num]);
5337                 wl->tx_queue_stopped[queue_num] = 0;
5338         }
5339
5340         snprintf(chip_name, ARRAY_SIZE(chip_name),
5341                  (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5342         b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5343                 dev->core_rev);
5344         return wl;
5345 }
5346
5347 #ifdef CONFIG_B43_BCMA
5348 static int b43_bcma_probe(struct bcma_device *core)
5349 {
5350         struct b43_bus_dev *dev;
5351         struct b43_wl *wl;
5352         int err;
5353
5354         dev = b43_bus_dev_bcma_init(core);
5355         if (!dev)
5356                 return -ENODEV;
5357
5358         wl = b43_wireless_init(dev);
5359         if (IS_ERR(wl)) {
5360                 err = PTR_ERR(wl);
5361                 goto bcma_out;
5362         }
5363
5364         err = b43_one_core_attach(dev, wl);
5365         if (err)
5366                 goto bcma_err_wireless_exit;
5367
5368         /* setup and start work to load firmware */
5369         INIT_WORK(&wl->firmware_load, b43_request_firmware);
5370         schedule_work(&wl->firmware_load);
5371
5372 bcma_out:
5373         return err;
5374
5375 bcma_err_wireless_exit:
5376         ieee80211_free_hw(wl->hw);
5377         return err;
5378 }
5379
5380 static void b43_bcma_remove(struct bcma_device *core)
5381 {
5382         struct b43_wldev *wldev = bcma_get_drvdata(core);
5383         struct b43_wl *wl = wldev->wl;
5384
5385         /* We must cancel any work here before unregistering from ieee80211,
5386          * as the ieee80211 unreg will destroy the workqueue. */
5387         cancel_work_sync(&wldev->restart_work);
5388
5389         /* Restore the queues count before unregistering, because firmware detect
5390          * might have modified it. Restoring is important, so the networking
5391          * stack can properly free resources. */
5392         wl->hw->queues = wl->mac80211_initially_registered_queues;
5393         b43_leds_stop(wldev);
5394         ieee80211_unregister_hw(wl->hw);
5395
5396         b43_one_core_detach(wldev->dev);
5397
5398         b43_leds_unregister(wl);
5399
5400         ieee80211_free_hw(wl->hw);
5401 }
5402
5403 static struct bcma_driver b43_bcma_driver = {
5404         .name           = KBUILD_MODNAME,
5405         .id_table       = b43_bcma_tbl,
5406         .probe          = b43_bcma_probe,
5407         .remove         = b43_bcma_remove,
5408 };
5409 #endif
5410
5411 #ifdef CONFIG_B43_SSB
5412 static
5413 int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5414 {
5415         struct b43_bus_dev *dev;
5416         struct b43_wl *wl;
5417         int err;
5418         int first = 0;
5419
5420         dev = b43_bus_dev_ssb_init(sdev);
5421         if (!dev)
5422                 return -ENOMEM;
5423
5424         wl = ssb_get_devtypedata(sdev);
5425         if (!wl) {
5426                 /* Probing the first core. Must setup common struct b43_wl */
5427                 first = 1;
5428                 b43_sprom_fixup(sdev->bus);
5429                 wl = b43_wireless_init(dev);
5430                 if (IS_ERR(wl)) {
5431                         err = PTR_ERR(wl);
5432                         goto out;
5433                 }
5434                 ssb_set_devtypedata(sdev, wl);
5435                 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5436         }
5437         err = b43_one_core_attach(dev, wl);
5438         if (err)
5439                 goto err_wireless_exit;
5440
5441         /* setup and start work to load firmware */
5442         INIT_WORK(&wl->firmware_load, b43_request_firmware);
5443         schedule_work(&wl->firmware_load);
5444
5445       out:
5446         return err;
5447
5448       err_wireless_exit:
5449         if (first)
5450                 b43_wireless_exit(dev, wl);
5451         return err;
5452 }
5453
5454 static void b43_ssb_remove(struct ssb_device *sdev)
5455 {
5456         struct b43_wl *wl = ssb_get_devtypedata(sdev);
5457         struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5458         struct b43_bus_dev *dev = wldev->dev;
5459
5460         /* We must cancel any work here before unregistering from ieee80211,
5461          * as the ieee80211 unreg will destroy the workqueue. */
5462         cancel_work_sync(&wldev->restart_work);
5463
5464         B43_WARN_ON(!wl);
5465         if (!wldev->fw.ucode.data)
5466                 return;                 /* NULL if firmware never loaded */
5467         if (wl->current_dev == wldev) {
5468                 /* Restore the queues count before unregistering, because firmware detect
5469                  * might have modified it. Restoring is important, so the networking
5470                  * stack can properly free resources. */
5471                 wl->hw->queues = wl->mac80211_initially_registered_queues;
5472                 b43_leds_stop(wldev);
5473                 ieee80211_unregister_hw(wl->hw);
5474         }
5475
5476         b43_one_core_detach(dev);
5477
5478         if (list_empty(&wl->devlist)) {
5479                 b43_leds_unregister(wl);
5480                 /* Last core on the chip unregistered.
5481                  * We can destroy common struct b43_wl.
5482                  */
5483                 b43_wireless_exit(dev, wl);
5484         }
5485 }
5486
5487 static struct ssb_driver b43_ssb_driver = {
5488         .name           = KBUILD_MODNAME,
5489         .id_table       = b43_ssb_tbl,
5490         .probe          = b43_ssb_probe,
5491         .remove         = b43_ssb_remove,
5492 };
5493 #endif /* CONFIG_B43_SSB */
5494
5495 /* Perform a hardware reset. This can be called from any context. */
5496 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5497 {
5498         /* Must avoid requeueing, if we are in shutdown. */
5499         if (b43_status(dev) < B43_STAT_INITIALIZED)
5500                 return;
5501         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
5502         ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5503 }
5504
5505 static void b43_print_driverinfo(void)
5506 {
5507         const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5508                    *feat_leds = "", *feat_sdio = "";
5509
5510 #ifdef CONFIG_B43_PCI_AUTOSELECT
5511         feat_pci = "P";
5512 #endif
5513 #ifdef CONFIG_B43_PCMCIA
5514         feat_pcmcia = "M";
5515 #endif
5516 #ifdef CONFIG_B43_PHY_N
5517         feat_nphy = "N";
5518 #endif
5519 #ifdef CONFIG_B43_LEDS
5520         feat_leds = "L";
5521 #endif
5522 #ifdef CONFIG_B43_SDIO
5523         feat_sdio = "S";
5524 #endif
5525         printk(KERN_INFO "Broadcom 43xx driver loaded "
5526                "[ Features: %s%s%s%s%s ]\n",
5527                feat_pci, feat_pcmcia, feat_nphy,
5528                feat_leds, feat_sdio);
5529 }
5530
5531 static int __init b43_init(void)
5532 {
5533         int err;
5534
5535         b43_debugfs_init();
5536         err = b43_pcmcia_init();
5537         if (err)
5538                 goto err_dfs_exit;
5539         err = b43_sdio_init();
5540         if (err)
5541                 goto err_pcmcia_exit;
5542 #ifdef CONFIG_B43_BCMA
5543         err = bcma_driver_register(&b43_bcma_driver);
5544         if (err)
5545                 goto err_sdio_exit;
5546 #endif
5547 #ifdef CONFIG_B43_SSB
5548         err = ssb_driver_register(&b43_ssb_driver);
5549         if (err)
5550                 goto err_bcma_driver_exit;
5551 #endif
5552         b43_print_driverinfo();
5553
5554         return err;
5555
5556 #ifdef CONFIG_B43_SSB
5557 err_bcma_driver_exit:
5558 #endif
5559 #ifdef CONFIG_B43_BCMA
5560         bcma_driver_unregister(&b43_bcma_driver);
5561 err_sdio_exit:
5562 #endif
5563         b43_sdio_exit();
5564 err_pcmcia_exit:
5565         b43_pcmcia_exit();
5566 err_dfs_exit:
5567         b43_debugfs_exit();
5568         return err;
5569 }
5570
5571 static void __exit b43_exit(void)
5572 {
5573 #ifdef CONFIG_B43_SSB
5574         ssb_driver_unregister(&b43_ssb_driver);
5575 #endif
5576 #ifdef CONFIG_B43_BCMA
5577         bcma_driver_unregister(&b43_bcma_driver);
5578 #endif
5579         b43_sdio_exit();
5580         b43_pcmcia_exit();
5581         b43_debugfs_exit();
5582 }
5583
5584 module_init(b43_init)
5585 module_exit(b43_exit)