net: convert print_mac to %pM
[linux-2.6.git] / drivers / net / wireless / ath9k / hw.c
1 /*
2  * Copyright (c) 2008 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "core.h"
21 #include "hw.h"
22 #include "reg.h"
23 #include "phy.h"
24 #include "initvals.h"
25
26 static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
27 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains);
28 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
29 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
30                                            u8 numChains);
31 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
32 static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
33                                          u8 numChains);
34
35 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
36 static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
37
38 static const struct hal_percal_data iq_cal_multi_sample = {
39         IQ_MISMATCH_CAL,
40         MAX_CAL_SAMPLES,
41         PER_MIN_LOG_COUNT,
42         ath9k_hw_iqcal_collect,
43         ath9k_hw_iqcalibrate
44 };
45 static const struct hal_percal_data iq_cal_single_sample = {
46         IQ_MISMATCH_CAL,
47         MIN_CAL_SAMPLES,
48         PER_MAX_LOG_COUNT,
49         ath9k_hw_iqcal_collect,
50         ath9k_hw_iqcalibrate
51 };
52 static const struct hal_percal_data adc_gain_cal_multi_sample = {
53         ADC_GAIN_CAL,
54         MAX_CAL_SAMPLES,
55         PER_MIN_LOG_COUNT,
56         ath9k_hw_adc_gaincal_collect,
57         ath9k_hw_adc_gaincal_calibrate
58 };
59 static const struct hal_percal_data adc_gain_cal_single_sample = {
60         ADC_GAIN_CAL,
61         MIN_CAL_SAMPLES,
62         PER_MAX_LOG_COUNT,
63         ath9k_hw_adc_gaincal_collect,
64         ath9k_hw_adc_gaincal_calibrate
65 };
66 static const struct hal_percal_data adc_dc_cal_multi_sample = {
67         ADC_DC_CAL,
68         MAX_CAL_SAMPLES,
69         PER_MIN_LOG_COUNT,
70         ath9k_hw_adc_dccal_collect,
71         ath9k_hw_adc_dccal_calibrate
72 };
73 static const struct hal_percal_data adc_dc_cal_single_sample = {
74         ADC_DC_CAL,
75         MIN_CAL_SAMPLES,
76         PER_MAX_LOG_COUNT,
77         ath9k_hw_adc_dccal_collect,
78         ath9k_hw_adc_dccal_calibrate
79 };
80 static const struct hal_percal_data adc_init_dc_cal = {
81         ADC_DC_INIT_CAL,
82         MIN_CAL_SAMPLES,
83         INIT_LOG_COUNT,
84         ath9k_hw_adc_dccal_collect,
85         ath9k_hw_adc_dccal_calibrate
86 };
87
88 static struct ath9k_rate_table ar5416_11a_table = {
89         8,
90         {0},
91         {
92                 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
93                 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
94                 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
95                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
96                 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
97                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
98                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
99                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
100         },
101 };
102
103 static struct ath9k_rate_table ar5416_11b_table = {
104         4,
105         {0},
106         {
107                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
108                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
109                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
110                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
111         },
112 };
113
114 static struct ath9k_rate_table ar5416_11g_table = {
115         12,
116         {0},
117         {
118                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
119                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
120                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
121                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
122
123                 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
124                 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
125                 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
126                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
127                 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
128                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
129                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
130                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
131         },
132 };
133
134 static struct ath9k_rate_table ar5416_11ng_table = {
135         28,
136         {0},
137         {
138                 {true, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
139                 {true, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
140                 {true, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
141                 {true, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
142
143                 {false, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
144                 {false, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
145                 {true, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
146                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
147                 {true, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
148                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
149                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
150                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
151                 {true, PHY_HT, 6500, 0x80, 0x00, 0, 4},
152                 {true, PHY_HT, 13000, 0x81, 0x00, 1, 6},
153                 {true, PHY_HT, 19500, 0x82, 0x00, 2, 6},
154                 {true, PHY_HT, 26000, 0x83, 0x00, 3, 8},
155                 {true, PHY_HT, 39000, 0x84, 0x00, 4, 8},
156                 {true, PHY_HT, 52000, 0x85, 0x00, 5, 8},
157                 {true, PHY_HT, 58500, 0x86, 0x00, 6, 8},
158                 {true, PHY_HT, 65000, 0x87, 0x00, 7, 8},
159                 {true, PHY_HT, 13000, 0x88, 0x00, 8, 4},
160                 {true, PHY_HT, 26000, 0x89, 0x00, 9, 6},
161                 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
162                 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
163                 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
164                 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
165                 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
166                 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
167         },
168 };
169
170 static struct ath9k_rate_table ar5416_11na_table = {
171         24,
172         {0},
173         {
174                 {true, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
175                 {true, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
176                 {true, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
177                 {true, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
178                 {true, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
179                 {true, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
180                 {true, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
181                 {true, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
182                 {true, PHY_HT, 6500, 0x80, 0x00, 0, 0},
183                 {true, PHY_HT, 13000, 0x81, 0x00, 1, 2},
184                 {true, PHY_HT, 19500, 0x82, 0x00, 2, 2},
185                 {true, PHY_HT, 26000, 0x83, 0x00, 3, 4},
186                 {true, PHY_HT, 39000, 0x84, 0x00, 4, 4},
187                 {true, PHY_HT, 52000, 0x85, 0x00, 5, 4},
188                 {true, PHY_HT, 58500, 0x86, 0x00, 6, 4},
189                 {true, PHY_HT, 65000, 0x87, 0x00, 7, 4},
190                 {true, PHY_HT, 13000, 0x88, 0x00, 8, 0},
191                 {true, PHY_HT, 26000, 0x89, 0x00, 9, 2},
192                 {true, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
193                 {true, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
194                 {true, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
195                 {true, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
196                 {true, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
197                 {true, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
198         },
199 };
200
201 static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
202                                        const struct ath9k_channel *chan)
203 {
204         if (IS_CHAN_CCK(chan))
205                 return ATH9K_MODE_11A;
206         if (IS_CHAN_G(chan))
207                 return ATH9K_MODE_11G;
208         return ATH9K_MODE_11A;
209 }
210
211 static bool ath9k_hw_wait(struct ath_hal *ah,
212                           u32 reg,
213                           u32 mask,
214                           u32 val)
215 {
216         int i;
217
218         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
219                 if ((REG_READ(ah, reg) & mask) == val)
220                         return true;
221
222                 udelay(AH_TIME_QUANTUM);
223         }
224         DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
225                  "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
226                  __func__, reg, REG_READ(ah, reg), mask, val);
227         return false;
228 }
229
230 static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off,
231                                  u16 *data)
232 {
233         (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
234
235         if (!ath9k_hw_wait(ah,
236                            AR_EEPROM_STATUS_DATA,
237                            AR_EEPROM_STATUS_DATA_BUSY |
238                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
239                 return false;
240         }
241
242         *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
243                    AR_EEPROM_STATUS_DATA_VAL);
244
245         return true;
246 }
247
248 static int ath9k_hw_flash_map(struct ath_hal *ah)
249 {
250         struct ath_hal_5416 *ahp = AH5416(ah);
251
252         ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
253
254         if (!ahp->ah_cal_mem) {
255                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
256                          "%s: cannot remap eeprom region \n", __func__);
257                 return -EIO;
258         }
259
260         return 0;
261 }
262
263 static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off,
264                                 u16 *data)
265 {
266         struct ath_hal_5416 *ahp = AH5416(ah);
267
268         *data = ioread16(ahp->ah_cal_mem + off);
269         return true;
270 }
271
272 static void ath9k_hw_read_revisions(struct ath_hal *ah)
273 {
274         u32 val;
275
276         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
277
278         if (val == 0xFF) {
279                 val = REG_READ(ah, AR_SREV);
280
281                 ah->ah_macVersion =
282                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
283
284                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
285                 ah->ah_isPciExpress =
286                         (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
287
288         } else {
289                 if (!AR_SREV_9100(ah))
290                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
291
292                 ah->ah_macRev = val & AR_SREV_REVISION;
293
294                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
295                         ah->ah_isPciExpress = true;
296         }
297 }
298
299 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
300 {
301         u32 retval;
302         int i;
303
304         for (i = 0, retval = 0; i < n; i++) {
305                 retval = (retval << 1) | (val & 1);
306                 val >>= 1;
307         }
308         return retval;
309 }
310
311 static void ath9k_hw_set_defaults(struct ath_hal *ah)
312 {
313         int i;
314
315         ah->ah_config.dma_beacon_response_time = 2;
316         ah->ah_config.sw_beacon_response_time = 10;
317         ah->ah_config.additional_swba_backoff = 0;
318         ah->ah_config.ack_6mb = 0x0;
319         ah->ah_config.cwm_ignore_extcca = 0;
320         ah->ah_config.pcie_powersave_enable = 0;
321         ah->ah_config.pcie_l1skp_enable = 0;
322         ah->ah_config.pcie_clock_req = 0;
323         ah->ah_config.pcie_power_reset = 0x100;
324         ah->ah_config.pcie_restore = 0;
325         ah->ah_config.pcie_waen = 0;
326         ah->ah_config.analog_shiftreg = 1;
327         ah->ah_config.ht_enable = 1;
328         ah->ah_config.ofdm_trig_low = 200;
329         ah->ah_config.ofdm_trig_high = 500;
330         ah->ah_config.cck_trig_high = 200;
331         ah->ah_config.cck_trig_low = 100;
332         ah->ah_config.enable_ani = 1;
333         ah->ah_config.noise_immunity_level = 4;
334         ah->ah_config.ofdm_weaksignal_det = 1;
335         ah->ah_config.cck_weaksignal_thr = 0;
336         ah->ah_config.spur_immunity_level = 2;
337         ah->ah_config.firstep_level = 0;
338         ah->ah_config.rssi_thr_high = 40;
339         ah->ah_config.rssi_thr_low = 7;
340         ah->ah_config.diversity_control = 0;
341         ah->ah_config.antenna_switch_swap = 0;
342
343         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
344                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
345                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
346         }
347
348         ah->ah_config.intr_mitigation = 0;
349 }
350
351 static void ath9k_hw_override_ini(struct ath_hal *ah,
352                                          struct ath9k_channel *chan)
353 {
354         if (!AR_SREV_5416_V20_OR_LATER(ah)
355             || AR_SREV_9280_10_OR_LATER(ah))
356                 return;
357
358         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
359 }
360
361 static void ath9k_hw_init_bb(struct ath_hal *ah,
362                              struct ath9k_channel *chan)
363 {
364         u32 synthDelay;
365
366         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
367         if (IS_CHAN_CCK(chan))
368                 synthDelay = (4 * synthDelay) / 22;
369         else
370                 synthDelay /= 10;
371
372         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
373
374         udelay(synthDelay + BASE_ACTIVATE_DELAY);
375 }
376
377 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
378                                           enum ath9k_opmode opmode)
379 {
380         struct ath_hal_5416 *ahp = AH5416(ah);
381
382         ahp->ah_maskReg = AR_IMR_TXERR |
383                 AR_IMR_TXURN |
384                 AR_IMR_RXERR |
385                 AR_IMR_RXORN |
386                 AR_IMR_BCNMISC;
387
388         if (ahp->ah_intrMitigation)
389                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
390         else
391                 ahp->ah_maskReg |= AR_IMR_RXOK;
392
393         ahp->ah_maskReg |= AR_IMR_TXOK;
394
395         if (opmode == ATH9K_M_HOSTAP)
396                 ahp->ah_maskReg |= AR_IMR_MIB;
397
398         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
399         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
400
401         if (!AR_SREV_9100(ah)) {
402                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
403                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
404                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
405         }
406 }
407
408 static void ath9k_hw_init_qos(struct ath_hal *ah)
409 {
410         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
411         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
412
413         REG_WRITE(ah, AR_QOS_NO_ACK,
414                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
415                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
416                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
417
418         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
419         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
420         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
421         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
422         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
423 }
424
425 static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
426                                       u32 reg,
427                                       u32 mask,
428                                       u32 shift,
429                                       u32 val)
430 {
431         u32 regVal;
432
433         regVal = REG_READ(ah, reg) & ~mask;
434         regVal |= (val << shift) & mask;
435
436         REG_WRITE(ah, reg, regVal);
437
438         if (ah->ah_config.analog_shiftreg)
439                 udelay(100);
440
441         return;
442 }
443
444 static u8 ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
445                                       enum ieee80211_band freq_band)
446 {
447         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
448         struct modal_eep_header *pModal =
449                 &(eep->modalHeader[IEEE80211_BAND_5GHZ == freq_band]);
450         struct base_eep_header *pBase = &eep->baseEepHeader;
451         u8 num_ant_config;
452
453         num_ant_config = 1;
454
455         if (pBase->version >= 0x0E0D)
456                 if (pModal->useAnt1)
457                         num_ant_config += 1;
458
459         return num_ant_config;
460 }
461
462 static int
463 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
464                                 struct ath9k_channel *chan,
465                                 u8 index,
466                                 u16 *config)
467 {
468         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
469         struct modal_eep_header *pModal =
470                 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
471         struct base_eep_header *pBase = &eep->baseEepHeader;
472
473         switch (index) {
474         case 0:
475                 *config = pModal->antCtrlCommon & 0xFFFF;
476                 return 0;
477         case 1:
478                 if (pBase->version >= 0x0E0D) {
479                         if (pModal->useAnt1) {
480                                 *config =
481                                 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
482                                 return 0;
483                         }
484                 }
485                 break;
486         default:
487                 break;
488         }
489
490         return -EINVAL;
491 }
492
493 static inline bool ath9k_hw_nvram_read(struct ath_hal *ah,
494                                        u32 off,
495                                        u16 *data)
496 {
497         if (ath9k_hw_use_flash(ah))
498                 return ath9k_hw_flash_read(ah, off, data);
499         else
500                 return ath9k_hw_eeprom_read(ah, off, data);
501 }
502
503 static bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
504 {
505         struct ath_hal_5416 *ahp = AH5416(ah);
506         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
507         u16 *eep_data;
508         int addr, ar5416_eep_start_loc = 0;
509
510         if (!ath9k_hw_use_flash(ah)) {
511                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
512                          "%s: Reading from EEPROM, not flash\n", __func__);
513                 ar5416_eep_start_loc = 256;
514         }
515         if (AR_SREV_9100(ah))
516                 ar5416_eep_start_loc = 256;
517
518         eep_data = (u16 *) eep;
519         for (addr = 0;
520              addr < sizeof(struct ar5416_eeprom) / sizeof(u16);
521              addr++) {
522                 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
523                                          eep_data)) {
524                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
525                                  "%s: Unable to read eeprom region \n",
526                                  __func__);
527                         return false;
528                 }
529                 eep_data++;
530         }
531         return true;
532 }
533
534 /* XXX: Clean me up, make me more legible */
535 static bool
536 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
537                                  struct ath9k_channel *chan)
538 {
539         struct modal_eep_header *pModal;
540         int i, regChainOffset;
541         struct ath_hal_5416 *ahp = AH5416(ah);
542         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
543         u8 txRxAttenLocal;
544         u16 ant_config;
545
546         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
547
548         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
549
550         ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 1, &ant_config);
551         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
552
553         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
554                 if (AR_SREV_9280(ah)) {
555                         if (i >= 2)
556                                 break;
557                 }
558
559                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
560                     (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
561                     && (i != 0))
562                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
563                 else
564                         regChainOffset = i * 0x1000;
565
566                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
567                           pModal->antCtrlChain[i]);
568
569                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
570                           (REG_READ(ah,
571                                     AR_PHY_TIMING_CTRL4(0) +
572                                     regChainOffset) &
573                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
574                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
575                           SM(pModal->iqCalICh[i],
576                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
577                           SM(pModal->iqCalQCh[i],
578                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
579
580                 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
581                         if ((eep->baseEepHeader.version &
582                              AR5416_EEP_VER_MINOR_MASK) >=
583                             AR5416_EEP_MINOR_VER_3) {
584                                 txRxAttenLocal = pModal->txRxAttenCh[i];
585                                 if (AR_SREV_9280_10_OR_LATER(ah)) {
586                                         REG_RMW_FIELD(ah,
587                                                 AR_PHY_GAIN_2GHZ +
588                                                 regChainOffset,
589                                                 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
590                                                 pModal->
591                                                 bswMargin[i]);
592                                         REG_RMW_FIELD(ah,
593                                                 AR_PHY_GAIN_2GHZ +
594                                                 regChainOffset,
595                                                 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
596                                                 pModal->
597                                                 bswAtten[i]);
598                                         REG_RMW_FIELD(ah,
599                                                 AR_PHY_GAIN_2GHZ +
600                                                 regChainOffset,
601                                                 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
602                                                 pModal->
603                                                 xatten2Margin[i]);
604                                         REG_RMW_FIELD(ah,
605                                                 AR_PHY_GAIN_2GHZ +
606                                                 regChainOffset,
607                                                 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
608                                                 pModal->
609                                                 xatten2Db[i]);
610                                 } else {
611                                         REG_WRITE(ah,
612                                                   AR_PHY_GAIN_2GHZ +
613                                                   regChainOffset,
614                                                   (REG_READ(ah,
615                                                             AR_PHY_GAIN_2GHZ +
616                                                             regChainOffset) &
617                                                    ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
618                                                   | SM(pModal->
619                                                   bswMargin[i],
620                                                   AR_PHY_GAIN_2GHZ_BSW_MARGIN));
621                                         REG_WRITE(ah,
622                                                   AR_PHY_GAIN_2GHZ +
623                                                   regChainOffset,
624                                                   (REG_READ(ah,
625                                                             AR_PHY_GAIN_2GHZ +
626                                                             regChainOffset) &
627                                                    ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
628                                                   | SM(pModal->bswAtten[i],
629                                                   AR_PHY_GAIN_2GHZ_BSW_ATTEN));
630                                 }
631                         }
632                         if (AR_SREV_9280_10_OR_LATER(ah)) {
633                                 REG_RMW_FIELD(ah,
634                                               AR_PHY_RXGAIN +
635                                               regChainOffset,
636                                               AR9280_PHY_RXGAIN_TXRX_ATTEN,
637                                               txRxAttenLocal);
638                                 REG_RMW_FIELD(ah,
639                                               AR_PHY_RXGAIN +
640                                               regChainOffset,
641                                               AR9280_PHY_RXGAIN_TXRX_MARGIN,
642                                               pModal->rxTxMarginCh[i]);
643                         } else {
644                                 REG_WRITE(ah,
645                                           AR_PHY_RXGAIN + regChainOffset,
646                                           (REG_READ(ah,
647                                                     AR_PHY_RXGAIN +
648                                                     regChainOffset) &
649                                            ~AR_PHY_RXGAIN_TXRX_ATTEN) |
650                                           SM(txRxAttenLocal,
651                                              AR_PHY_RXGAIN_TXRX_ATTEN));
652                                 REG_WRITE(ah,
653                                           AR_PHY_GAIN_2GHZ +
654                                           regChainOffset,
655                                           (REG_READ(ah,
656                                                     AR_PHY_GAIN_2GHZ +
657                                                     regChainOffset) &
658                                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
659                                           SM(pModal->rxTxMarginCh[i],
660                                              AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
661                         }
662                 }
663         }
664
665         if (AR_SREV_9280_10_OR_LATER(ah)) {
666                 if (IS_CHAN_2GHZ(chan)) {
667                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
668                                                   AR_AN_RF2G1_CH0_OB,
669                                                   AR_AN_RF2G1_CH0_OB_S,
670                                                   pModal->ob);
671                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
672                                                   AR_AN_RF2G1_CH0_DB,
673                                                   AR_AN_RF2G1_CH0_DB_S,
674                                                   pModal->db);
675                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
676                                                   AR_AN_RF2G1_CH1_OB,
677                                                   AR_AN_RF2G1_CH1_OB_S,
678                                                   pModal->ob_ch1);
679                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
680                                                   AR_AN_RF2G1_CH1_DB,
681                                                   AR_AN_RF2G1_CH1_DB_S,
682                                                   pModal->db_ch1);
683                 } else {
684                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
685                                                   AR_AN_RF5G1_CH0_OB5,
686                                                   AR_AN_RF5G1_CH0_OB5_S,
687                                                   pModal->ob);
688                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
689                                                   AR_AN_RF5G1_CH0_DB5,
690                                                   AR_AN_RF5G1_CH0_DB5_S,
691                                                   pModal->db);
692                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
693                                                   AR_AN_RF5G1_CH1_OB5,
694                                                   AR_AN_RF5G1_CH1_OB5_S,
695                                                   pModal->ob_ch1);
696                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
697                                                   AR_AN_RF5G1_CH1_DB5,
698                                                   AR_AN_RF5G1_CH1_DB5_S,
699                                                   pModal->db_ch1);
700                 }
701                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
702                                           AR_AN_TOP2_XPABIAS_LVL,
703                                           AR_AN_TOP2_XPABIAS_LVL_S,
704                                           pModal->xpaBiasLvl);
705                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
706                                           AR_AN_TOP2_LOCALBIAS,
707                                           AR_AN_TOP2_LOCALBIAS_S,
708                                           pModal->local_bias);
709                 DPRINTF(ah->ah_sc, ATH_DBG_ANY, "ForceXPAon: %d\n",
710                         pModal->force_xpaon);
711                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
712                               pModal->force_xpaon);
713         }
714
715         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
716                       pModal->switchSettling);
717         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
718                       pModal->adcDesiredSize);
719
720         if (!AR_SREV_9280_10_OR_LATER(ah))
721                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
722                               AR_PHY_DESIRED_SZ_PGA,
723                               pModal->pgaDesiredSize);
724
725         REG_WRITE(ah, AR_PHY_RF_CTL4,
726                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
727                   | SM(pModal->txEndToXpaOff,
728                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
729                   | SM(pModal->txFrameToXpaOn,
730                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
731                   | SM(pModal->txFrameToXpaOn,
732                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
733
734         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
735                       pModal->txEndToRxOn);
736         if (AR_SREV_9280_10_OR_LATER(ah)) {
737                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
738                               pModal->thresh62);
739                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
740                               AR_PHY_EXT_CCA0_THRESH62,
741                               pModal->thresh62);
742         } else {
743                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
744                               pModal->thresh62);
745                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
746                               AR_PHY_EXT_CCA_THRESH62,
747                               pModal->thresh62);
748         }
749
750         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
751             AR5416_EEP_MINOR_VER_2) {
752                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
753                               AR_PHY_TX_END_DATA_START,
754                               pModal->txFrameToDataStart);
755                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
756                               pModal->txFrameToPaOn);
757         }
758
759         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
760             AR5416_EEP_MINOR_VER_3) {
761                 if (IS_CHAN_HT40(chan))
762                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
763                                       AR_PHY_SETTLING_SWITCH,
764                                       pModal->swSettleHt40);
765         }
766
767         return true;
768 }
769
770 static int ath9k_hw_check_eeprom(struct ath_hal *ah)
771 {
772         u32 sum = 0, el;
773         u16 *eepdata;
774         int i;
775         struct ath_hal_5416 *ahp = AH5416(ah);
776         bool need_swap = false;
777         struct ar5416_eeprom *eep =
778                 (struct ar5416_eeprom *) &ahp->ah_eeprom;
779
780         if (!ath9k_hw_use_flash(ah)) {
781                 u16 magic, magic2;
782                 int addr;
783
784                 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
785                                         &magic)) {
786                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
787                                  "%s: Reading Magic # failed\n", __func__);
788                         return false;
789                 }
790                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
791                          __func__, magic);
792
793                 if (magic != AR5416_EEPROM_MAGIC) {
794                         magic2 = swab16(magic);
795
796                         if (magic2 == AR5416_EEPROM_MAGIC) {
797                                 need_swap = true;
798                                 eepdata = (u16 *) (&ahp->ah_eeprom);
799
800                                 for (addr = 0;
801                                      addr <
802                                              sizeof(struct ar5416_eeprom) /
803                                              sizeof(u16); addr++) {
804                                         u16 temp;
805
806                                         temp = swab16(*eepdata);
807                                         *eepdata = temp;
808                                         eepdata++;
809
810                                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
811                                                  "0x%04X  ", *eepdata);
812                                         if (((addr + 1) % 6) == 0)
813                                                 DPRINTF(ah->ah_sc,
814                                                          ATH_DBG_EEPROM,
815                                                          "\n");
816                                 }
817                         } else {
818                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
819                                          "Invalid EEPROM Magic. "
820                                         "endianness missmatch.\n");
821                                 return -EINVAL;
822                         }
823                 }
824         }
825         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
826                  need_swap ? "True" : "False");
827
828         if (need_swap)
829                 el = swab16(ahp->ah_eeprom.baseEepHeader.length);
830         else
831                 el = ahp->ah_eeprom.baseEepHeader.length;
832
833         if (el > sizeof(struct ar5416_eeprom))
834                 el = sizeof(struct ar5416_eeprom) / sizeof(u16);
835         else
836                 el = el / sizeof(u16);
837
838         eepdata = (u16 *) (&ahp->ah_eeprom);
839
840         for (i = 0; i < el; i++)
841                 sum ^= *eepdata++;
842
843         if (need_swap) {
844                 u32 integer, j;
845                 u16 word;
846
847                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
848                          "EEPROM Endianness is not native.. Changing \n");
849
850                 word = swab16(eep->baseEepHeader.length);
851                 eep->baseEepHeader.length = word;
852
853                 word = swab16(eep->baseEepHeader.checksum);
854                 eep->baseEepHeader.checksum = word;
855
856                 word = swab16(eep->baseEepHeader.version);
857                 eep->baseEepHeader.version = word;
858
859                 word = swab16(eep->baseEepHeader.regDmn[0]);
860                 eep->baseEepHeader.regDmn[0] = word;
861
862                 word = swab16(eep->baseEepHeader.regDmn[1]);
863                 eep->baseEepHeader.regDmn[1] = word;
864
865                 word = swab16(eep->baseEepHeader.rfSilent);
866                 eep->baseEepHeader.rfSilent = word;
867
868                 word = swab16(eep->baseEepHeader.blueToothOptions);
869                 eep->baseEepHeader.blueToothOptions = word;
870
871                 word = swab16(eep->baseEepHeader.deviceCap);
872                 eep->baseEepHeader.deviceCap = word;
873
874                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
875                         struct modal_eep_header *pModal =
876                                 &eep->modalHeader[j];
877                         integer = swab32(pModal->antCtrlCommon);
878                         pModal->antCtrlCommon = integer;
879
880                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
881                                 integer = swab32(pModal->antCtrlChain[i]);
882                                 pModal->antCtrlChain[i] = integer;
883                         }
884
885                         for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
886                                 word = swab16(pModal->spurChans[i].spurChan);
887                                 pModal->spurChans[i].spurChan = word;
888                         }
889                 }
890         }
891
892         if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
893             ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
894                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
895                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
896                          sum, ar5416_get_eep_ver(ahp));
897                 return -EINVAL;
898         }
899
900         return 0;
901 }
902
903 static bool ath9k_hw_chip_test(struct ath_hal *ah)
904 {
905         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
906         u32 regHold[2];
907         u32 patternData[4] = { 0x55555555,
908                                      0xaaaaaaaa,
909                                      0x66666666,
910                                      0x99999999 };
911         int i, j;
912
913         for (i = 0; i < 2; i++) {
914                 u32 addr = regAddr[i];
915                 u32 wrData, rdData;
916
917                 regHold[i] = REG_READ(ah, addr);
918                 for (j = 0; j < 0x100; j++) {
919                         wrData = (j << 16) | j;
920                         REG_WRITE(ah, addr, wrData);
921                         rdData = REG_READ(ah, addr);
922                         if (rdData != wrData) {
923                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
924                                  "%s: address test failed "
925                                 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
926                                  __func__, addr, wrData, rdData);
927                                 return false;
928                         }
929                 }
930                 for (j = 0; j < 4; j++) {
931                         wrData = patternData[j];
932                         REG_WRITE(ah, addr, wrData);
933                         rdData = REG_READ(ah, addr);
934                         if (wrData != rdData) {
935                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
936                                  "%s: address test failed "
937                                 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
938                                  __func__, addr, wrData, rdData);
939                                 return false;
940                         }
941                 }
942                 REG_WRITE(ah, regAddr[i], regHold[i]);
943         }
944         udelay(100);
945         return true;
946 }
947
948 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
949 {
950         u32 bits = REG_READ(ah, AR_RX_FILTER);
951         u32 phybits = REG_READ(ah, AR_PHY_ERR);
952
953         if (phybits & AR_PHY_ERR_RADAR)
954                 bits |= ATH9K_RX_FILTER_PHYRADAR;
955         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
956                 bits |= ATH9K_RX_FILTER_PHYERR;
957         return bits;
958 }
959
960 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
961 {
962         u32 phybits;
963
964         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
965         phybits = 0;
966         if (bits & ATH9K_RX_FILTER_PHYRADAR)
967                 phybits |= AR_PHY_ERR_RADAR;
968         if (bits & ATH9K_RX_FILTER_PHYERR)
969                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
970         REG_WRITE(ah, AR_PHY_ERR, phybits);
971
972         if (phybits)
973                 REG_WRITE(ah, AR_RXCFG,
974                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
975         else
976                 REG_WRITE(ah, AR_RXCFG,
977                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
978 }
979
980 bool ath9k_hw_setcapability(struct ath_hal *ah,
981                             enum ath9k_capability_type type,
982                             u32 capability,
983                             u32 setting,
984                             int *status)
985 {
986         struct ath_hal_5416 *ahp = AH5416(ah);
987         u32 v;
988
989         switch (type) {
990         case ATH9K_CAP_TKIP_MIC:
991                 if (setting)
992                         ahp->ah_staId1Defaults |=
993                                 AR_STA_ID1_CRPT_MIC_ENABLE;
994                 else
995                         ahp->ah_staId1Defaults &=
996                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
997                 return true;
998         case ATH9K_CAP_DIVERSITY:
999                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1000                 if (setting)
1001                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1002                 else
1003                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1004                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1005                 return true;
1006         case ATH9K_CAP_MCAST_KEYSRCH:
1007                 if (setting)
1008                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
1009                 else
1010                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1011                 return true;
1012         case ATH9K_CAP_TSF_ADJUST:
1013                 if (setting)
1014                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
1015                 else
1016                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
1017                 return true;
1018         default:
1019                 return false;
1020         }
1021 }
1022
1023 void ath9k_hw_dmaRegDump(struct ath_hal *ah)
1024 {
1025         u32 val[ATH9K_NUM_DMA_DEBUG_REGS];
1026         int qcuOffset = 0, dcuOffset = 0;
1027         u32 *qcuBase = &val[0], *dcuBase = &val[4];
1028         int i;
1029
1030         REG_WRITE(ah, AR_MACMISC,
1031                   ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1032                    (AR_MACMISC_MISC_OBS_BUS_1 <<
1033                     AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1034
1035         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "Raw DMA Debug values:\n");
1036         for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
1037                 if (i % 4 == 0)
1038                         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1039
1040                 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u32)));
1041                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "%d: %08x ", i, val[i]);
1042         }
1043
1044         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n\n");
1045         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1046                  "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1047
1048         for (i = 0; i < ATH9K_NUM_QUEUES;
1049              i++, qcuOffset += 4, dcuOffset += 5) {
1050                 if (i == 8) {
1051                         qcuOffset = 0;
1052                         qcuBase++;
1053                 }
1054
1055                 if (i == 6) {
1056                         dcuOffset = 0;
1057                         dcuBase++;
1058                 }
1059
1060                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1061                          "%2d          %2x      %1x     %2x           %2x\n",
1062                          i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
1063                          (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
1064                                                              3),
1065                          val[2] & (0x7 << (i * 3)) >> (i * 3),
1066                          (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
1067         }
1068
1069         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "\n");
1070         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1071                  "qcu_stitch state:   %2x    qcu_fetch state:        %2x\n",
1072                  (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1073         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1074                  "qcu_complete state: %2x    dcu_complete state:     %2x\n",
1075                  (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1076         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1077                  "dcu_arb state:      %2x    dcu_fp state:           %2x\n",
1078                  (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1079         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1080                  "chan_idle_dur:     %3d    chan_idle_dur_valid:     %1d\n",
1081                  (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1082         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1083                  "txfifo_valid_0:      %1d    txfifo_valid_1:          %1d\n",
1084                  (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1085         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1086                  "txfifo_dcu_num_0:   %2d    txfifo_dcu_num_1:       %2d\n",
1087                  (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1088
1089         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, "pcu observe 0x%x \n",
1090                 REG_READ(ah, AR_OBS_BUS_1));
1091         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1092                 "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
1093 }
1094
1095 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1096                                         u32 *rxc_pcnt,
1097                                         u32 *rxf_pcnt,
1098                                         u32 *txf_pcnt)
1099 {
1100         static u32 cycles, rx_clear, rx_frame, tx_frame;
1101         u32 good = 1;
1102
1103         u32 rc = REG_READ(ah, AR_RCCNT);
1104         u32 rf = REG_READ(ah, AR_RFCNT);
1105         u32 tf = REG_READ(ah, AR_TFCNT);
1106         u32 cc = REG_READ(ah, AR_CCCNT);
1107
1108         if (cycles == 0 || cycles > cc) {
1109                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1110                          "%s: cycle counter wrap. ExtBusy = 0\n",
1111                          __func__);
1112                 good = 0;
1113         } else {
1114                 u32 cc_d = cc - cycles;
1115                 u32 rc_d = rc - rx_clear;
1116                 u32 rf_d = rf - rx_frame;
1117                 u32 tf_d = tf - tx_frame;
1118
1119                 if (cc_d != 0) {
1120                         *rxc_pcnt = rc_d * 100 / cc_d;
1121                         *rxf_pcnt = rf_d * 100 / cc_d;
1122                         *txf_pcnt = tf_d * 100 / cc_d;
1123                 } else {
1124                         good = 0;
1125                 }
1126         }
1127
1128         cycles = cc;
1129         rx_frame = rf;
1130         rx_clear = rc;
1131         tx_frame = tf;
1132
1133         return good;
1134 }
1135
1136 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
1137 {
1138         u32 macmode;
1139
1140         if (mode == ATH9K_HT_MACMODE_2040 &&
1141             !ah->ah_config.cwm_ignore_extcca)
1142                 macmode = AR_2040_JOINED_RX_CLEAR;
1143         else
1144                 macmode = 0;
1145
1146         REG_WRITE(ah, AR_2040_MODE, macmode);
1147 }
1148
1149 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1150 {
1151         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1152 }
1153
1154
1155 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
1156                                               struct ath_softc *sc,
1157                                               void __iomem *mem,
1158                                               int *status)
1159 {
1160         static const u8 defbssidmask[ETH_ALEN] =
1161                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1162         struct ath_hal_5416 *ahp;
1163         struct ath_hal *ah;
1164
1165         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
1166         if (ahp == NULL) {
1167                 DPRINTF(sc, ATH_DBG_FATAL,
1168                          "%s: cannot allocate memory for state block\n",
1169                          __func__);
1170                 *status = -ENOMEM;
1171                 return NULL;
1172         }
1173
1174         ah = &ahp->ah;
1175
1176         ah->ah_sc = sc;
1177         ah->ah_sh = mem;
1178
1179         ah->ah_magic = AR5416_MAGIC;
1180         ah->ah_countryCode = CTRY_DEFAULT;
1181
1182         ah->ah_devid = devid;
1183         ah->ah_subvendorid = 0;
1184
1185         ah->ah_flags = 0;
1186         if ((devid == AR5416_AR9100_DEVID))
1187                 ah->ah_macVersion = AR_SREV_VERSION_9100;
1188         if (!AR_SREV_9100(ah))
1189                 ah->ah_flags = AH_USE_EEPROM;
1190
1191         ah->ah_powerLimit = MAX_RATE_POWER;
1192         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
1193
1194         ahp->ah_atimWindow = 0;
1195         ahp->ah_diversityControl = ah->ah_config.diversity_control;
1196         ahp->ah_antennaSwitchSwap =
1197                 ah->ah_config.antenna_switch_swap;
1198
1199         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
1200         ahp->ah_beaconInterval = 100;
1201         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
1202         ahp->ah_slottime = (u32) -1;
1203         ahp->ah_acktimeout = (u32) -1;
1204         ahp->ah_ctstimeout = (u32) -1;
1205         ahp->ah_globaltxtimeout = (u32) -1;
1206         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
1207
1208         ahp->ah_gBeaconRate = 0;
1209
1210         return ahp;
1211 }
1212
1213 static int ath9k_hw_eeprom_attach(struct ath_hal *ah)
1214 {
1215         int status;
1216
1217         if (ath9k_hw_use_flash(ah))
1218                 ath9k_hw_flash_map(ah);
1219
1220         if (!ath9k_hw_fill_eeprom(ah))
1221                 return -EIO;
1222
1223         status = ath9k_hw_check_eeprom(ah);
1224
1225         return status;
1226 }
1227
1228 u32 ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
1229                               enum eeprom_param param)
1230 {
1231         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1232         struct modal_eep_header *pModal = eep->modalHeader;
1233         struct base_eep_header *pBase = &eep->baseEepHeader;
1234
1235         switch (param) {
1236         case EEP_NFTHRESH_5:
1237                 return -pModal[0].noiseFloorThreshCh[0];
1238         case EEP_NFTHRESH_2:
1239                 return -pModal[1].noiseFloorThreshCh[0];
1240         case AR_EEPROM_MAC(0):
1241                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1242         case AR_EEPROM_MAC(1):
1243                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1244         case AR_EEPROM_MAC(2):
1245                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1246         case EEP_REG_0:
1247                 return pBase->regDmn[0];
1248         case EEP_REG_1:
1249                 return pBase->regDmn[1];
1250         case EEP_OP_CAP:
1251                 return pBase->deviceCap;
1252         case EEP_OP_MODE:
1253                 return pBase->opCapFlags;
1254         case EEP_RF_SILENT:
1255                 return pBase->rfSilent;
1256         case EEP_OB_5:
1257                 return pModal[0].ob;
1258         case EEP_DB_5:
1259                 return pModal[0].db;
1260         case EEP_OB_2:
1261                 return pModal[1].ob;
1262         case EEP_DB_2:
1263                 return pModal[1].db;
1264         case EEP_MINOR_REV:
1265                 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
1266         case EEP_TX_MASK:
1267                 return pBase->txMask;
1268         case EEP_RX_MASK:
1269                 return pBase->rxMask;
1270         default:
1271                 return 0;
1272         }
1273 }
1274
1275 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
1276 {
1277         u32 val;
1278         int i;
1279
1280         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
1281         for (i = 0; i < 8; i++)
1282                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
1283         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
1284         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
1285         return ath9k_hw_reverse_bits(val, 8);
1286 }
1287
1288 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
1289 {
1290         u32 sum;
1291         int i;
1292         u16 eeval;
1293         struct ath_hal_5416 *ahp = AH5416(ah);
1294
1295         sum = 0;
1296         for (i = 0; i < 3; i++) {
1297                 eeval = ath9k_hw_get_eeprom(ahp, AR_EEPROM_MAC(i));
1298                 sum += eeval;
1299                 ahp->ah_macaddr[2 * i] = eeval >> 8;
1300                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1301         }
1302         if (sum == 0 || sum == 0xffff * 3) {
1303                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1304                          "%s: mac address read failed: %pM\n", __func__,
1305                          ahp->ah_macaddr);
1306                 return -EADDRNOTAVAIL;
1307         }
1308
1309         return 0;
1310 }
1311
1312 static inline int16_t ath9k_hw_interpolate(u16 target,
1313                                            u16 srcLeft,
1314                                            u16 srcRight,
1315                                            int16_t targetLeft,
1316                                            int16_t targetRight)
1317 {
1318         int16_t rv;
1319
1320         if (srcRight == srcLeft) {
1321                 rv = targetLeft;
1322         } else {
1323                 rv = (int16_t) (((target - srcLeft) * targetRight +
1324                                  (srcRight - target) * targetLeft) /
1325                                 (srcRight - srcLeft));
1326         }
1327         return rv;
1328 }
1329
1330 static inline u16 ath9k_hw_fbin2freq(u8 fbin,
1331                                            bool is2GHz)
1332 {
1333
1334         if (fbin == AR5416_BCHAN_UNUSED)
1335                 return fbin;
1336
1337         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1338 }
1339
1340 static u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
1341                                                u16 i,
1342                                                bool is2GHz)
1343 {
1344         struct ath_hal_5416 *ahp = AH5416(ah);
1345         struct ar5416_eeprom *eep =
1346                 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1347         u16 spur_val = AR_NO_SPUR;
1348
1349         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1350                  "Getting spur idx %d is2Ghz. %d val %x\n",
1351                  i, is2GHz, ah->ah_config.spurchans[i][is2GHz]);
1352
1353         switch (ah->ah_config.spurmode) {
1354         case SPUR_DISABLE:
1355                 break;
1356         case SPUR_ENABLE_IOCTL:
1357                 spur_val = ah->ah_config.spurchans[i][is2GHz];
1358                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1359                          "Getting spur val from new loc. %d\n", spur_val);
1360                 break;
1361         case SPUR_ENABLE_EEPROM:
1362                 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan;
1363                 break;
1364
1365         }
1366         return spur_val;
1367 }
1368
1369 static int ath9k_hw_rfattach(struct ath_hal *ah)
1370 {
1371         bool rfStatus = false;
1372         int ecode = 0;
1373
1374         rfStatus = ath9k_hw_init_rf(ah, &ecode);
1375         if (!rfStatus) {
1376                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1377                          "%s: RF setup failed, status %u\n", __func__,
1378                          ecode);
1379                 return ecode;
1380         }
1381
1382         return 0;
1383 }
1384
1385 static int ath9k_hw_rf_claim(struct ath_hal *ah)
1386 {
1387         u32 val;
1388
1389         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1390
1391         val = ath9k_hw_get_radiorev(ah);
1392         switch (val & AR_RADIO_SREV_MAJOR) {
1393         case 0:
1394                 val = AR_RAD5133_SREV_MAJOR;
1395                 break;
1396         case AR_RAD5133_SREV_MAJOR:
1397         case AR_RAD5122_SREV_MAJOR:
1398         case AR_RAD2133_SREV_MAJOR:
1399         case AR_RAD2122_SREV_MAJOR:
1400                 break;
1401         default:
1402                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1403                          "%s: 5G Radio Chip Rev 0x%02X is not "
1404                         "supported by this driver\n",
1405                          __func__, ah->ah_analog5GhzRev);
1406                 return -EOPNOTSUPP;
1407         }
1408
1409         ah->ah_analog5GhzRev = val;
1410
1411         return 0;
1412 }
1413
1414 static void ath9k_hw_init_pll(struct ath_hal *ah,
1415                               struct ath9k_channel *chan)
1416 {
1417         u32 pll;
1418
1419         if (AR_SREV_9100(ah)) {
1420                 if (chan && IS_CHAN_5GHZ(chan))
1421                         pll = 0x1450;
1422                 else
1423                         pll = 0x1458;
1424         } else {
1425                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1426                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1427
1428                         if (chan && IS_CHAN_HALF_RATE(chan))
1429                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1430                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1431                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1432
1433                         if (chan && IS_CHAN_5GHZ(chan)) {
1434                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1435
1436
1437                                 if (AR_SREV_9280_20(ah)) {
1438                                         if (((chan->channel % 20) == 0)
1439                                             || ((chan->channel % 10) == 0))
1440                                                 pll = 0x2850;
1441                                         else
1442                                                 pll = 0x142c;
1443                                 }
1444                         } else {
1445                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1446                         }
1447
1448                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1449
1450                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1451
1452                         if (chan && IS_CHAN_HALF_RATE(chan))
1453                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1454                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1455                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1456
1457                         if (chan && IS_CHAN_5GHZ(chan))
1458                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1459                         else
1460                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1461                 } else {
1462                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1463
1464                         if (chan && IS_CHAN_HALF_RATE(chan))
1465                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1466                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1467                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1468
1469                         if (chan && IS_CHAN_5GHZ(chan))
1470                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1471                         else
1472                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1473                 }
1474         }
1475         REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1476
1477         udelay(RTC_PLL_SETTLE_DELAY);
1478
1479         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1480 }
1481
1482 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1483                               enum ath9k_ht_macmode macmode)
1484 {
1485         u32 phymode;
1486         struct ath_hal_5416 *ahp = AH5416(ah);
1487
1488         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1489                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1490
1491         if (IS_CHAN_HT40(chan)) {
1492                 phymode |= AR_PHY_FC_DYN2040_EN;
1493
1494                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1495                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1496                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1497
1498                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1499                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1500         }
1501         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1502
1503         ath9k_hw_set11nmac2040(ah, macmode);
1504
1505         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1506         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1507 }
1508
1509 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1510 {
1511         u32 val;
1512
1513         val = REG_READ(ah, AR_STA_ID1);
1514         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1515         switch (opmode) {
1516         case ATH9K_M_HOSTAP:
1517                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1518                           | AR_STA_ID1_KSRCH_MODE);
1519                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1520                 break;
1521         case ATH9K_M_IBSS:
1522                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1523                           | AR_STA_ID1_KSRCH_MODE);
1524                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1525                 break;
1526         case ATH9K_M_STA:
1527         case ATH9K_M_MONITOR:
1528                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1529                 break;
1530         }
1531 }
1532
1533 static void
1534 ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1535 {
1536         u32 rfMode = 0;
1537
1538         if (chan == NULL)
1539                 return;
1540
1541         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1542                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1543
1544         if (!AR_SREV_9280_10_OR_LATER(ah))
1545                 rfMode |= (IS_CHAN_5GHZ(chan)) ? AR_PHY_MODE_RF5GHZ :
1546                         AR_PHY_MODE_RF2GHZ;
1547
1548         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1549                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1550
1551         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1552 }
1553
1554 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1555 {
1556         u32 rst_flags;
1557         u32 tmpReg;
1558
1559         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1560                   AR_RTC_FORCE_WAKE_ON_INT);
1561
1562         if (AR_SREV_9100(ah)) {
1563                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1564                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1565         } else {
1566                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1567                 if (tmpReg &
1568                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1569                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1570                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1571                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1572                 } else {
1573                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1574                 }
1575
1576                 rst_flags = AR_RTC_RC_MAC_WARM;
1577                 if (type == ATH9K_RESET_COLD)
1578                         rst_flags |= AR_RTC_RC_MAC_COLD;
1579         }
1580
1581         REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1582         udelay(50);
1583
1584         REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1585         if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1586                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1587                         "%s: RTC stuck in MAC reset\n",
1588                         __func__);
1589                 return false;
1590         }
1591
1592         if (!AR_SREV_9100(ah))
1593                 REG_WRITE(ah, AR_RC, 0);
1594
1595         ath9k_hw_init_pll(ah, NULL);
1596
1597         if (AR_SREV_9100(ah))
1598                 udelay(50);
1599
1600         return true;
1601 }
1602
1603 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1604 {
1605         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1606                   AR_RTC_FORCE_WAKE_ON_INT);
1607
1608         REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1609         REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1610
1611         if (!ath9k_hw_wait(ah,
1612                            AR_RTC_STATUS,
1613                            AR_RTC_STATUS_M,
1614                            AR_RTC_STATUS_ON)) {
1615                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1616                          __func__);
1617                 return false;
1618         }
1619
1620         ath9k_hw_read_revisions(ah);
1621
1622         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1623 }
1624
1625 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
1626                                    u32 type)
1627 {
1628         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1629                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1630
1631         switch (type) {
1632         case ATH9K_RESET_POWER_ON:
1633                 return ath9k_hw_set_reset_power_on(ah);
1634                 break;
1635         case ATH9K_RESET_WARM:
1636         case ATH9K_RESET_COLD:
1637                 return ath9k_hw_set_reset(ah, type);
1638                 break;
1639         default:
1640                 return false;
1641         }
1642 }
1643
1644 static
1645 struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1646                                           struct ath9k_channel *chan)
1647 {
1648         if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1649                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1650                          "%s: invalid channel %u/0x%x; not marked as "
1651                          "2GHz or 5GHz\n", __func__, chan->channel,
1652                          chan->channelFlags);
1653                 return NULL;
1654         }
1655
1656         if (!IS_CHAN_OFDM(chan) &&
1657               !IS_CHAN_CCK(chan) &&
1658               !IS_CHAN_HT20(chan) &&
1659               !IS_CHAN_HT40(chan)) {
1660                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1661                         "%s: invalid channel %u/0x%x; not marked as "
1662                         "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1663                         __func__, chan->channel, chan->channelFlags);
1664                 return NULL;
1665         }
1666
1667         return ath9k_regd_check_channel(ah, chan);
1668 }
1669
1670 static inline bool
1671 ath9k_hw_get_lower_upper_index(u8 target,
1672                                u8 *pList,
1673                                u16 listSize,
1674                                u16 *indexL,
1675                                u16 *indexR)
1676 {
1677         u16 i;
1678
1679         if (target <= pList[0]) {
1680                 *indexL = *indexR = 0;
1681                 return true;
1682         }
1683         if (target >= pList[listSize - 1]) {
1684                 *indexL = *indexR = (u16) (listSize - 1);
1685                 return true;
1686         }
1687
1688         for (i = 0; i < listSize - 1; i++) {
1689                 if (pList[i] == target) {
1690                         *indexL = *indexR = i;
1691                         return true;
1692                 }
1693                 if (target < pList[i + 1]) {
1694                         *indexL = i;
1695                         *indexR = (u16) (i + 1);
1696                         return false;
1697                 }
1698         }
1699         return false;
1700 }
1701
1702 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
1703 {
1704         int16_t nfval;
1705         int16_t sort[ATH9K_NF_CAL_HIST_MAX];
1706         int i, j;
1707
1708         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
1709                 sort[i] = nfCalBuffer[i];
1710
1711         for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
1712                 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
1713                         if (sort[j] > sort[j - 1]) {
1714                                 nfval = sort[j];
1715                                 sort[j] = sort[j - 1];
1716                                 sort[j - 1] = nfval;
1717                         }
1718                 }
1719         }
1720         nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
1721
1722         return nfval;
1723 }
1724
1725 static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
1726                                               int16_t *nfarray)
1727 {
1728         int i;
1729
1730         for (i = 0; i < NUM_NF_READINGS; i++) {
1731                 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
1732
1733                 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
1734                         h[i].currIndex = 0;
1735
1736                 if (h[i].invalidNFcount > 0) {
1737                         if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
1738                             || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
1739                                 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
1740                         } else {
1741                                 h[i].invalidNFcount--;
1742                                 h[i].privNF = nfarray[i];
1743                         }
1744                 } else {
1745                         h[i].privNF =
1746                                 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
1747                 }
1748         }
1749         return;
1750 }
1751
1752 static void ar5416GetNoiseFloor(struct ath_hal *ah,
1753                                 int16_t nfarray[NUM_NF_READINGS])
1754 {
1755         int16_t nf;
1756
1757         if (AR_SREV_9280_10_OR_LATER(ah))
1758                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
1759         else
1760                 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1761
1762         if (nf & 0x100)
1763                 nf = 0 - ((nf ^ 0x1ff) + 1);
1764         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1765                  "NF calibrated [ctl] [chain 0] is %d\n", nf);
1766         nfarray[0] = nf;
1767
1768         if (AR_SREV_9280_10_OR_LATER(ah))
1769                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1770                         AR9280_PHY_CH1_MINCCA_PWR);
1771         else
1772                 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1773                         AR_PHY_CH1_MINCCA_PWR);
1774
1775         if (nf & 0x100)
1776                 nf = 0 - ((nf ^ 0x1ff) + 1);
1777         DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1778                  "NF calibrated [ctl] [chain 1] is %d\n", nf);
1779         nfarray[1] = nf;
1780
1781         if (!AR_SREV_9280(ah)) {
1782                 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
1783                         AR_PHY_CH2_MINCCA_PWR);
1784                 if (nf & 0x100)
1785                         nf = 0 - ((nf ^ 0x1ff) + 1);
1786                 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1787                          "NF calibrated [ctl] [chain 2] is %d\n", nf);
1788                 nfarray[2] = nf;
1789         }
1790
1791         if (AR_SREV_9280_10_OR_LATER(ah))
1792                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1793                         AR9280_PHY_EXT_MINCCA_PWR);
1794         else
1795                 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1796                         AR_PHY_EXT_MINCCA_PWR);
1797
1798         if (nf & 0x100)
1799                 nf = 0 - ((nf ^ 0x1ff) + 1);
1800         DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1801                  "NF calibrated [ext] [chain 0] is %d\n", nf);
1802         nfarray[3] = nf;
1803
1804         if (AR_SREV_9280_10_OR_LATER(ah))
1805                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1806                         AR9280_PHY_CH1_EXT_MINCCA_PWR);
1807         else
1808                 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1809                         AR_PHY_CH1_EXT_MINCCA_PWR);
1810
1811         if (nf & 0x100)
1812                 nf = 0 - ((nf ^ 0x1ff) + 1);
1813         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1814                  "NF calibrated [ext] [chain 1] is %d\n", nf);
1815         nfarray[4] = nf;
1816
1817         if (!AR_SREV_9280(ah)) {
1818                 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
1819                         AR_PHY_CH2_EXT_MINCCA_PWR);
1820                 if (nf & 0x100)
1821                         nf = 0 - ((nf ^ 0x1ff) + 1);
1822                 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL,
1823                          "NF calibrated [ext] [chain 2] is %d\n", nf);
1824                 nfarray[5] = nf;
1825         }
1826 }
1827
1828 static bool
1829 getNoiseFloorThresh(struct ath_hal *ah,
1830                     const struct ath9k_channel *chan,
1831                     int16_t *nft)
1832 {
1833         struct ath_hal_5416 *ahp = AH5416(ah);
1834
1835         switch (chan->chanmode) {
1836         case CHANNEL_A:
1837         case CHANNEL_A_HT20:
1838         case CHANNEL_A_HT40PLUS:
1839         case CHANNEL_A_HT40MINUS:
1840                 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_5);
1841                 break;
1842         case CHANNEL_B:
1843         case CHANNEL_G:
1844         case CHANNEL_G_HT20:
1845         case CHANNEL_G_HT40PLUS:
1846         case CHANNEL_G_HT40MINUS:
1847                 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
1848                 break;
1849         default:
1850                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1851                          "%s: invalid channel flags 0x%x\n", __func__,
1852                          chan->channelFlags);
1853                 return false;
1854         }
1855         return true;
1856 }
1857
1858 static void ath9k_hw_start_nfcal(struct ath_hal *ah)
1859 {
1860         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1861                     AR_PHY_AGC_CONTROL_ENABLE_NF);
1862         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1863                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1864         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1865 }
1866
1867 static void
1868 ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan)
1869 {
1870         struct ath9k_nfcal_hist *h;
1871         int i, j;
1872         int32_t val;
1873         const u32 ar5416_cca_regs[6] = {
1874                 AR_PHY_CCA,
1875                 AR_PHY_CH1_CCA,
1876                 AR_PHY_CH2_CCA,
1877                 AR_PHY_EXT_CCA,
1878                 AR_PHY_CH1_EXT_CCA,
1879                 AR_PHY_CH2_EXT_CCA
1880         };
1881         u8 chainmask;
1882
1883         if (AR_SREV_9280(ah))
1884                 chainmask = 0x1B;
1885         else
1886                 chainmask = 0x3F;
1887
1888 #ifdef ATH_NF_PER_CHAN
1889         h = chan->nfCalHist;
1890 #else
1891         h = ah->nfCalHist;
1892 #endif
1893
1894         for (i = 0; i < NUM_NF_READINGS; i++) {
1895                 if (chainmask & (1 << i)) {
1896                         val = REG_READ(ah, ar5416_cca_regs[i]);
1897                         val &= 0xFFFFFE00;
1898                         val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1899                         REG_WRITE(ah, ar5416_cca_regs[i], val);
1900                 }
1901         }
1902
1903         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1904                     AR_PHY_AGC_CONTROL_ENABLE_NF);
1905         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1906                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1907         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1908
1909         for (j = 0; j < 1000; j++) {
1910                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1911                      AR_PHY_AGC_CONTROL_NF) == 0)
1912                         break;
1913                 udelay(10);
1914         }
1915
1916         for (i = 0; i < NUM_NF_READINGS; i++) {
1917                 if (chainmask & (1 << i)) {
1918                         val = REG_READ(ah, ar5416_cca_regs[i]);
1919                         val &= 0xFFFFFE00;
1920                         val |= (((u32) (-50) << 1) & 0x1ff);
1921                         REG_WRITE(ah, ar5416_cca_regs[i], val);
1922                 }
1923         }
1924 }
1925
1926 static int16_t ath9k_hw_getnf(struct ath_hal *ah,
1927                               struct ath9k_channel *chan)
1928 {
1929         int16_t nf, nfThresh;
1930         int16_t nfarray[NUM_NF_READINGS] = { 0 };
1931         struct ath9k_nfcal_hist *h;
1932         u8 chainmask;
1933
1934         if (AR_SREV_9280(ah))
1935                 chainmask = 0x1B;
1936         else
1937                 chainmask = 0x3F;
1938
1939         chan->channelFlags &= (~CHANNEL_CW_INT);
1940         if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1941                 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1942                          "%s: NF did not complete in calibration window\n",
1943                          __func__);
1944                 nf = 0;
1945                 chan->rawNoiseFloor = nf;
1946                 return chan->rawNoiseFloor;
1947         } else {
1948                 ar5416GetNoiseFloor(ah, nfarray);
1949                 nf = nfarray[0];
1950                 if (getNoiseFloorThresh(ah, chan, &nfThresh)
1951                     && nf > nfThresh) {
1952                         DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
1953                                  "%s: noise floor failed detected; "
1954                                  "detected %d, threshold %d\n", __func__,
1955                                  nf, nfThresh);
1956                         chan->channelFlags |= CHANNEL_CW_INT;
1957                 }
1958         }
1959
1960 #ifdef ATH_NF_PER_CHAN
1961         h = chan->nfCalHist;
1962 #else
1963         h = ah->nfCalHist;
1964 #endif
1965
1966         ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
1967         chan->rawNoiseFloor = h[0].privNF;
1968
1969         return chan->rawNoiseFloor;
1970 }
1971
1972 static void ath9k_hw_update_mibstats(struct ath_hal *ah,
1973                               struct ath9k_mib_stats *stats)
1974 {
1975         stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
1976         stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
1977         stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
1978         stats->rts_good += REG_READ(ah, AR_RTS_OK);
1979         stats->beacons += REG_READ(ah, AR_BEACON_CNT);
1980 }
1981
1982 static void ath9k_enable_mib_counters(struct ath_hal *ah)
1983 {
1984         struct ath_hal_5416 *ahp = AH5416(ah);
1985
1986         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable mib counters\n");
1987
1988         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
1989
1990         REG_WRITE(ah, AR_FILT_OFDM, 0);
1991         REG_WRITE(ah, AR_FILT_CCK, 0);
1992         REG_WRITE(ah, AR_MIBC,
1993                   ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
1994                   & 0x0f);
1995         REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1996         REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1997 }
1998
1999 static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
2000 {
2001         struct ath_hal_5416 *ahp = AH5416(ah);
2002
2003         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling MIB counters\n");
2004
2005         REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
2006
2007         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2008
2009         REG_WRITE(ah, AR_FILT_OFDM, 0);
2010         REG_WRITE(ah, AR_FILT_CCK, 0);
2011 }
2012
2013 static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
2014                                         struct ath9k_channel *chan)
2015 {
2016         struct ath_hal_5416 *ahp = AH5416(ah);
2017         int i;
2018
2019         for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2020                 if (ahp->ah_ani[i].c.channel == chan->channel)
2021                         return i;
2022                 if (ahp->ah_ani[i].c.channel == 0) {
2023                         ahp->ah_ani[i].c.channel = chan->channel;
2024                         ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
2025                         return i;
2026                 }
2027         }
2028
2029         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2030                  "No more channel states left. Using channel 0\n");
2031         return 0;
2032 }
2033
2034 static void ath9k_hw_ani_attach(struct ath_hal *ah)
2035 {
2036         struct ath_hal_5416 *ahp = AH5416(ah);
2037         int i;
2038
2039         ahp->ah_hasHwPhyCounters = 1;
2040
2041         memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
2042         for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2043                 ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
2044                 ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
2045                 ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
2046                 ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
2047                 ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
2048                 ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
2049                 ahp->ah_ani[i].ofdmWeakSigDetectOff =
2050                         !ATH9K_ANI_USE_OFDM_WEAK_SIG;
2051                 ahp->ah_ani[i].cckWeakSigThreshold =
2052                         ATH9K_ANI_CCK_WEAK_SIG_THR;
2053                 ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
2054                 ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
2055                 if (ahp->ah_hasHwPhyCounters) {
2056                         ahp->ah_ani[i].ofdmPhyErrBase =
2057                                 AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
2058                         ahp->ah_ani[i].cckPhyErrBase =
2059                                 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
2060                 }
2061         }
2062         if (ahp->ah_hasHwPhyCounters) {
2063                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2064                         "Setting OfdmErrBase = 0x%08x\n",
2065                         ahp->ah_ani[0].ofdmPhyErrBase);
2066                 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
2067                         ahp->ah_ani[0].cckPhyErrBase);
2068
2069                 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
2070                 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
2071                 ath9k_enable_mib_counters(ah);
2072         }
2073         ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
2074         if (ah->ah_config.enable_ani)
2075                 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
2076 }
2077
2078 static void ath9k_hw_ani_setup(struct ath_hal *ah)
2079 {
2080         struct ath_hal_5416 *ahp = AH5416(ah);
2081         int i;
2082
2083         const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
2084         const int coarseHigh[] = { -14, -14, -14, -14, -12 };
2085         const int coarseLow[] = { -64, -64, -64, -64, -70 };
2086         const int firpwr[] = { -78, -78, -78, -78, -80 };
2087
2088         for (i = 0; i < 5; i++) {
2089                 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i];
2090                 ahp->ah_coarseHigh[i] = coarseHigh[i];
2091                 ahp->ah_coarseLow[i] = coarseLow[i];
2092                 ahp->ah_firpwr[i] = firpwr[i];
2093         }
2094 }
2095
2096 static void ath9k_hw_ani_detach(struct ath_hal *ah)
2097 {
2098         struct ath_hal_5416 *ahp = AH5416(ah);
2099
2100         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detaching Ani\n");
2101         if (ahp->ah_hasHwPhyCounters) {
2102                 ath9k_hw_disable_mib_counters(ah);
2103                 REG_WRITE(ah, AR_PHY_ERR_1, 0);
2104                 REG_WRITE(ah, AR_PHY_ERR_2, 0);
2105         }
2106 }
2107
2108
2109 static bool ath9k_hw_ani_control(struct ath_hal *ah,
2110                                  enum ath9k_ani_cmd cmd, int param)
2111 {
2112         struct ath_hal_5416 *ahp = AH5416(ah);
2113         struct ar5416AniState *aniState = ahp->ah_curani;
2114
2115         switch (cmd & ahp->ah_ani_function) {
2116         case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
2117                 u32 level = param;
2118
2119                 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
2120                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2121                                  "%s: level out of range (%u > %u)\n",
2122                                  __func__, level,
2123                                  (unsigned) ARRAY_SIZE(ahp->
2124                                                        ah_totalSizeDesired));
2125                         return false;
2126                 }
2127
2128                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2129                               AR_PHY_DESIRED_SZ_TOT_DES,
2130                               ahp->ah_totalSizeDesired[level]);
2131                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2132                               AR_PHY_AGC_CTL1_COARSE_LOW,
2133                               ahp->ah_coarseLow[level]);
2134                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2135                               AR_PHY_AGC_CTL1_COARSE_HIGH,
2136                               ahp->ah_coarseHigh[level]);
2137                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2138                               AR_PHY_FIND_SIG_FIRPWR,
2139                               ahp->ah_firpwr[level]);
2140
2141                 if (level > aniState->noiseImmunityLevel)
2142                         ahp->ah_stats.ast_ani_niup++;
2143                 else if (level < aniState->noiseImmunityLevel)
2144                         ahp->ah_stats.ast_ani_nidown++;
2145                 aniState->noiseImmunityLevel = level;
2146                 break;
2147         }
2148         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2149                 const int m1ThreshLow[] = { 127, 50 };
2150                 const int m2ThreshLow[] = { 127, 40 };
2151                 const int m1Thresh[] = { 127, 0x4d };
2152                 const int m2Thresh[] = { 127, 0x40 };
2153                 const int m2CountThr[] = { 31, 16 };
2154                 const int m2CountThrLow[] = { 63, 48 };
2155                 u32 on = param ? 1 : 0;
2156
2157                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2158                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2159                               m1ThreshLow[on]);
2160                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2161                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2162                               m2ThreshLow[on]);
2163                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2164                               AR_PHY_SFCORR_M1_THRESH,
2165                               m1Thresh[on]);
2166                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2167                               AR_PHY_SFCORR_M2_THRESH,
2168                               m2Thresh[on]);
2169                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2170                               AR_PHY_SFCORR_M2COUNT_THR,
2171                               m2CountThr[on]);
2172                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2173                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2174                               m2CountThrLow[on]);
2175
2176                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2177                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2178                               m1ThreshLow[on]);
2179                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2180                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2181                               m2ThreshLow[on]);
2182                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2183                               AR_PHY_SFCORR_EXT_M1_THRESH,
2184                               m1Thresh[on]);
2185                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2186                               AR_PHY_SFCORR_EXT_M2_THRESH,
2187                               m2Thresh[on]);
2188
2189                 if (on)
2190                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2191                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2192                 else
2193                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2194                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2195
2196                 if (!on != aniState->ofdmWeakSigDetectOff) {
2197                         if (on)
2198                                 ahp->ah_stats.ast_ani_ofdmon++;
2199                         else
2200                                 ahp->ah_stats.ast_ani_ofdmoff++;
2201                         aniState->ofdmWeakSigDetectOff = !on;
2202                 }
2203                 break;
2204         }
2205         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
2206                 const int weakSigThrCck[] = { 8, 6 };
2207                 u32 high = param ? 1 : 0;
2208
2209                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2210                               AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2211                               weakSigThrCck[high]);
2212                 if (high != aniState->cckWeakSigThreshold) {
2213                         if (high)
2214                                 ahp->ah_stats.ast_ani_cckhigh++;
2215                         else
2216                                 ahp->ah_stats.ast_ani_ccklow++;
2217                         aniState->cckWeakSigThreshold = high;
2218                 }
2219                 break;
2220         }
2221         case ATH9K_ANI_FIRSTEP_LEVEL:{
2222                 const int firstep[] = { 0, 4, 8 };
2223                 u32 level = param;
2224
2225                 if (level >= ARRAY_SIZE(firstep)) {
2226                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2227                                  "%s: level out of range (%u > %u)\n",
2228                                  __func__, level,
2229                                 (unsigned) ARRAY_SIZE(firstep));
2230                         return false;
2231                 }
2232                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2233                               AR_PHY_FIND_SIG_FIRSTEP,
2234                               firstep[level]);
2235                 if (level > aniState->firstepLevel)
2236                         ahp->ah_stats.ast_ani_stepup++;
2237                 else if (level < aniState->firstepLevel)
2238                         ahp->ah_stats.ast_ani_stepdown++;
2239                 aniState->firstepLevel = level;
2240                 break;
2241         }
2242         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
2243                 const int cycpwrThr1[] =
2244                         { 2, 4, 6, 8, 10, 12, 14, 16 };
2245                 u32 level = param;
2246
2247                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
2248                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2249                                  "%s: level out of range (%u > %u)\n",
2250                                  __func__, level,
2251                                  (unsigned)
2252                                 ARRAY_SIZE(cycpwrThr1));
2253                         return false;
2254                 }
2255                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2256                               AR_PHY_TIMING5_CYCPWR_THR1,
2257                               cycpwrThr1[level]);
2258                 if (level > aniState->spurImmunityLevel)
2259                         ahp->ah_stats.ast_ani_spurup++;
2260                 else if (level < aniState->spurImmunityLevel)
2261                         ahp->ah_stats.ast_ani_spurdown++;
2262                 aniState->spurImmunityLevel = level;
2263                 break;
2264         }
2265         case ATH9K_ANI_PRESENT:
2266                 break;
2267         default:
2268                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2269                         "%s: invalid cmd %u\n", __func__, cmd);
2270                 return false;
2271         }
2272
2273         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__);
2274         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2275                 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2276                 "ofdmWeakSigDetectOff=%d\n",
2277                  aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
2278                  !aniState->ofdmWeakSigDetectOff);
2279         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2280                 "cckWeakSigThreshold=%d, "
2281                 "firstepLevel=%d, listenTime=%d\n",
2282                  aniState->cckWeakSigThreshold, aniState->firstepLevel,
2283                  aniState->listenTime);
2284         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2285                  "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2286                  aniState->cycleCount, aniState->ofdmPhyErrCount,
2287                  aniState->cckPhyErrCount);
2288         return true;
2289 }
2290
2291 static void ath9k_ani_restart(struct ath_hal *ah)
2292 {
2293         struct ath_hal_5416 *ahp = AH5416(ah);
2294         struct ar5416AniState *aniState;
2295
2296         if (!DO_ANI(ah))
2297                 return;
2298
2299         aniState = ahp->ah_curani;
2300
2301         aniState->listenTime = 0;
2302         if (ahp->ah_hasHwPhyCounters) {
2303                 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
2304                         aniState->ofdmPhyErrBase = 0;
2305                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2306                                  "OFDM Trigger is too high for hw counters\n");
2307                 } else {
2308                         aniState->ofdmPhyErrBase =
2309                                 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
2310                 }
2311                 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
2312                         aniState->cckPhyErrBase = 0;
2313                         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2314                                  "CCK Trigger is too high for hw counters\n");
2315                 } else {
2316                         aniState->cckPhyErrBase =
2317                                 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
2318                 }
2319                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2320                          "%s: Writing ofdmbase=%u   cckbase=%u\n",
2321                          __func__, aniState->ofdmPhyErrBase,
2322                          aniState->cckPhyErrBase);
2323                 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
2324                 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
2325                 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2326                 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2327
2328                 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2329         }
2330         aniState->ofdmPhyErrCount = 0;
2331         aniState->cckPhyErrCount = 0;
2332 }
2333
2334 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
2335 {
2336         struct ath_hal_5416 *ahp = AH5416(ah);
2337         struct ath9k_channel *chan = ah->ah_curchan;
2338         struct ar5416AniState *aniState;
2339         enum wireless_mode mode;
2340         int32_t rssi;
2341
2342         if (!DO_ANI(ah))
2343                 return;
2344
2345         aniState = ahp->ah_curani;
2346
2347         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2348                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2349                                          aniState->noiseImmunityLevel + 1)) {
2350                         return;
2351                 }
2352         }
2353
2354         if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
2355                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2356                                          aniState->spurImmunityLevel + 1)) {
2357                         return;
2358                 }
2359         }
2360
2361         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2362                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2363                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2364                                              aniState->firstepLevel + 1);
2365                 }
2366                 return;
2367         }
2368         rssi = BEACON_RSSI(ahp);
2369         if (rssi > aniState->rssiThrHigh) {
2370                 if (!aniState->ofdmWeakSigDetectOff) {
2371                         if (ath9k_hw_ani_control(ah,
2372                                          ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2373                                          false)) {
2374                                 ath9k_hw_ani_control(ah,
2375                                         ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2376                                         0);
2377                                 return;
2378                         }
2379                 }
2380                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2381                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2382                                              aniState->firstepLevel + 1);
2383                         return;
2384                 }
2385         } else if (rssi > aniState->rssiThrLow) {
2386                 if (aniState->ofdmWeakSigDetectOff)
2387                         ath9k_hw_ani_control(ah,
2388                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2389                                      true);
2390                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2391                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2392                                              aniState->firstepLevel + 1);
2393                 return;
2394         } else {
2395                 mode = ath9k_hw_chan2wmode(ah, chan);
2396                 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2397                         if (!aniState->ofdmWeakSigDetectOff)
2398                                 ath9k_hw_ani_control(ah,
2399                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2400                                      false);
2401                         if (aniState->firstepLevel > 0)
2402                                 ath9k_hw_ani_control(ah,
2403                                                      ATH9K_ANI_FIRSTEP_LEVEL,
2404                                                      0);
2405                         return;
2406                 }
2407         }
2408 }
2409
2410 static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
2411 {
2412         struct ath_hal_5416 *ahp = AH5416(ah);
2413         struct ath9k_channel *chan = ah->ah_curchan;
2414         struct ar5416AniState *aniState;
2415         enum wireless_mode mode;
2416         int32_t rssi;
2417
2418         if (!DO_ANI(ah))
2419                 return;
2420
2421         aniState = ahp->ah_curani;
2422         if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2423                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2424                                          aniState->noiseImmunityLevel + 1)) {
2425                         return;
2426                 }
2427         }
2428         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2429                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2430                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2431                                              aniState->firstepLevel + 1);
2432                 }
2433                 return;
2434         }
2435         rssi = BEACON_RSSI(ahp);
2436         if (rssi > aniState->rssiThrLow) {
2437                 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2438                         ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2439                                              aniState->firstepLevel + 1);
2440         } else {
2441                 mode = ath9k_hw_chan2wmode(ah, chan);
2442                 if (mode == ATH9K_MODE_11G || mode == ATH9K_MODE_11B) {
2443                         if (aniState->firstepLevel > 0)
2444                                 ath9k_hw_ani_control(ah,
2445                                                      ATH9K_ANI_FIRSTEP_LEVEL,
2446                                                      0);
2447                 }
2448         }
2449 }
2450
2451 static void ath9k_ani_reset(struct ath_hal *ah)
2452 {
2453         struct ath_hal_5416 *ahp = AH5416(ah);
2454         struct ar5416AniState *aniState;
2455         struct ath9k_channel *chan = ah->ah_curchan;
2456         int index;
2457
2458         if (!DO_ANI(ah))
2459                 return;
2460
2461         index = ath9k_hw_get_ani_channel_idx(ah, chan);
2462         aniState = &ahp->ah_ani[index];
2463         ahp->ah_curani = aniState;
2464
2465         if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
2466             && ah->ah_opmode != ATH9K_M_IBSS) {
2467                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2468                          "%s: Reset ANI state opmode %u\n", __func__,
2469                          ah->ah_opmode);
2470                 ahp->ah_stats.ast_ani_reset++;
2471                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
2472                 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
2473                 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
2474                 ath9k_hw_ani_control(ah,
2475                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2476                                      !ATH9K_ANI_USE_OFDM_WEAK_SIG);
2477                 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2478                                      ATH9K_ANI_CCK_WEAK_SIG_THR);
2479                 ath9k_hw_setrxfilter(ah,
2480                                      ath9k_hw_getrxfilter(ah) |
2481                                      ATH9K_RX_FILTER_PHYERR);
2482                 if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2483                         ahp->ah_curani->ofdmTrigHigh =
2484                                 ah->ah_config.ofdm_trig_high;
2485                         ahp->ah_curani->ofdmTrigLow =
2486                                 ah->ah_config.ofdm_trig_low;
2487                         ahp->ah_curani->cckTrigHigh =
2488                                 ah->ah_config.cck_trig_high;
2489                         ahp->ah_curani->cckTrigLow =
2490                                 ah->ah_config.cck_trig_low;
2491                 }
2492                 ath9k_ani_restart(ah);
2493                 return;
2494         }
2495
2496         if (aniState->noiseImmunityLevel != 0)
2497                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2498                                      aniState->noiseImmunityLevel);
2499         if (aniState->spurImmunityLevel != 0)
2500                 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2501                                      aniState->spurImmunityLevel);
2502         if (aniState->ofdmWeakSigDetectOff)
2503                 ath9k_hw_ani_control(ah,
2504                                      ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2505                                      !aniState->ofdmWeakSigDetectOff);
2506         if (aniState->cckWeakSigThreshold)
2507                 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
2508                                      aniState->cckWeakSigThreshold);
2509         if (aniState->firstepLevel != 0)
2510                 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2511                                      aniState->firstepLevel);
2512         if (ahp->ah_hasHwPhyCounters) {
2513                 ath9k_hw_setrxfilter(ah,
2514                                      ath9k_hw_getrxfilter(ah) &
2515                                      ~ATH9K_RX_FILTER_PHYERR);
2516                 ath9k_ani_restart(ah);
2517                 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2518                 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2519
2520         } else {
2521                 ath9k_ani_restart(ah);
2522                 ath9k_hw_setrxfilter(ah,
2523                                      ath9k_hw_getrxfilter(ah) |
2524                                      ATH9K_RX_FILTER_PHYERR);
2525         }
2526 }
2527
2528 /*
2529  * Process a MIB interrupt.  We may potentially be invoked because
2530  * any of the MIB counters overflow/trigger so don't assume we're
2531  * here because a PHY error counter triggered.
2532  */
2533 void ath9k_hw_procmibevent(struct ath_hal *ah,
2534                            const struct ath9k_node_stats *stats)
2535 {
2536         struct ath_hal_5416 *ahp = AH5416(ah);
2537         u32 phyCnt1, phyCnt2;
2538
2539         DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Processing Mib Intr\n");
2540         /* Reset these counters regardless */
2541         REG_WRITE(ah, AR_FILT_OFDM, 0);
2542         REG_WRITE(ah, AR_FILT_CCK, 0);
2543         if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
2544                 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
2545
2546         /* Clear the mib counters and save them in the stats */
2547         ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2548         ahp->ah_stats.ast_nodestats = *stats;
2549
2550         if (!DO_ANI(ah))
2551                 return;
2552
2553         /* NB: these are not reset-on-read */
2554         phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2555         phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2556         if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
2557             ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
2558                 struct ar5416AniState *aniState = ahp->ah_curani;
2559                 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2560
2561                 /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
2562                 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2563                 ahp->ah_stats.ast_ani_ofdmerrs +=
2564                         ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2565                 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2566
2567                 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2568                 ahp->ah_stats.ast_ani_cckerrs +=
2569                         cckPhyErrCnt - aniState->cckPhyErrCount;
2570                 aniState->cckPhyErrCount = cckPhyErrCnt;
2571
2572                 /*
2573                  * NB: figure out which counter triggered.  If both
2574                  * trigger we'll only deal with one as the processing
2575                  * clobbers the error counter so the trigger threshold
2576                  * check will never be true.
2577                  */
2578                 if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
2579                         ath9k_hw_ani_ofdm_err_trigger(ah);
2580                 if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
2581                         ath9k_hw_ani_cck_err_trigger(ah);
2582                 /* NB: always restart to insure the h/w counters are reset */
2583                 ath9k_ani_restart(ah);
2584         }
2585 }
2586
2587 static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
2588 {
2589         struct ath_hal_5416 *ahp = AH5416(ah);
2590         struct ar5416AniState *aniState;
2591         int32_t rssi;
2592
2593         aniState = ahp->ah_curani;
2594
2595         if (ah->ah_opmode == ATH9K_M_HOSTAP) {
2596                 if (aniState->firstepLevel > 0) {
2597                         if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
2598                                                  aniState->firstepLevel - 1)) {
2599                                 return;
2600                         }
2601                 }
2602         } else {
2603                 rssi = BEACON_RSSI(ahp);
2604                 if (rssi > aniState->rssiThrHigh) {
2605                         /* XXX: Handle me */
2606                 } else if (rssi > aniState->rssiThrLow) {
2607                         if (aniState->ofdmWeakSigDetectOff) {
2608                                 if (ath9k_hw_ani_control(ah,
2609                                          ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2610                                          true) ==
2611                                     true) {
2612                                         return;
2613                                 }
2614                         }
2615                         if (aniState->firstepLevel > 0) {
2616                                 if (ath9k_hw_ani_control
2617                                     (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2618                                      aniState->firstepLevel - 1) ==
2619                                     true) {
2620                                         return;
2621                                 }
2622                         }
2623                 } else {
2624                         if (aniState->firstepLevel > 0) {
2625                                 if (ath9k_hw_ani_control
2626                                     (ah, ATH9K_ANI_FIRSTEP_LEVEL,
2627                                      aniState->firstepLevel - 1) ==
2628                                     true) {
2629                                         return;
2630                                 }
2631                         }
2632                 }
2633         }
2634
2635         if (aniState->spurImmunityLevel > 0) {
2636                 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
2637                                          aniState->spurImmunityLevel - 1)) {
2638                         return;
2639                 }
2640         }
2641
2642         if (aniState->noiseImmunityLevel > 0) {
2643                 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
2644                                      aniState->noiseImmunityLevel - 1);
2645                 return;
2646         }
2647 }
2648
2649 static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
2650 {
2651         struct ath_hal_5416 *ahp = AH5416(ah);
2652         struct ar5416AniState *aniState;
2653         u32 txFrameCount, rxFrameCount, cycleCount;
2654         int32_t listenTime;
2655
2656         txFrameCount = REG_READ(ah, AR_TFCNT);
2657         rxFrameCount = REG_READ(ah, AR_RFCNT);
2658         cycleCount = REG_READ(ah, AR_CCCNT);
2659
2660         aniState = ahp->ah_curani;
2661         if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
2662
2663                 listenTime = 0;
2664                 ahp->ah_stats.ast_ani_lzero++;
2665         } else {
2666                 int32_t ccdelta = cycleCount - aniState->cycleCount;
2667                 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
2668                 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
2669                 listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
2670         }
2671         aniState->cycleCount = cycleCount;
2672         aniState->txFrameCount = txFrameCount;
2673         aniState->rxFrameCount = rxFrameCount;
2674
2675         return listenTime;
2676 }
2677
2678 void ath9k_hw_ani_monitor(struct ath_hal *ah,
2679                           const struct ath9k_node_stats *stats,
2680                           struct ath9k_channel *chan)
2681 {
2682         struct ath_hal_5416 *ahp = AH5416(ah);
2683         struct ar5416AniState *aniState;
2684         int32_t listenTime;
2685
2686         aniState = ahp->ah_curani;
2687         ahp->ah_stats.ast_nodestats = *stats;
2688
2689         listenTime = ath9k_hw_ani_get_listen_time(ah);
2690         if (listenTime < 0) {
2691                 ahp->ah_stats.ast_ani_lneg++;
2692                 ath9k_ani_restart(ah);
2693                 return;
2694         }
2695
2696         aniState->listenTime += listenTime;
2697
2698         if (ahp->ah_hasHwPhyCounters) {
2699                 u32 phyCnt1, phyCnt2;
2700                 u32 ofdmPhyErrCnt, cckPhyErrCnt;
2701
2702                 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2703
2704                 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2705                 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2706
2707                 if (phyCnt1 < aniState->ofdmPhyErrBase ||
2708                     phyCnt2 < aniState->cckPhyErrBase) {
2709                         if (phyCnt1 < aniState->ofdmPhyErrBase) {
2710                                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2711                                          "%s: phyCnt1 0x%x, resetting "
2712                                          "counter value to 0x%x\n",
2713                                          __func__, phyCnt1,
2714                                          aniState->ofdmPhyErrBase);
2715                                 REG_WRITE(ah, AR_PHY_ERR_1,
2716                                           aniState->ofdmPhyErrBase);
2717                                 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
2718                                           AR_PHY_ERR_OFDM_TIMING);
2719                         }
2720                         if (phyCnt2 < aniState->cckPhyErrBase) {
2721                                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2722                                          "%s: phyCnt2 0x%x, resetting "
2723                                          "counter value to 0x%x\n",
2724                                          __func__, phyCnt2,
2725                                          aniState->cckPhyErrBase);
2726                                 REG_WRITE(ah, AR_PHY_ERR_2,
2727                                           aniState->cckPhyErrBase);
2728                                 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
2729                                           AR_PHY_ERR_CCK_TIMING);
2730                         }
2731                         return;
2732                 }
2733
2734                 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2735                 ahp->ah_stats.ast_ani_ofdmerrs +=
2736                         ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2737                 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2738
2739                 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2740                 ahp->ah_stats.ast_ani_cckerrs +=
2741                         cckPhyErrCnt - aniState->cckPhyErrCount;
2742                 aniState->cckPhyErrCount = cckPhyErrCnt;
2743         }
2744
2745         if (!DO_ANI(ah))
2746                 return;
2747
2748         if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
2749                 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
2750                     aniState->ofdmTrigLow / 1000 &&
2751                     aniState->cckPhyErrCount <= aniState->listenTime *
2752                     aniState->cckTrigLow / 1000)
2753                         ath9k_hw_ani_lower_immunity(ah);
2754                 ath9k_ani_restart(ah);
2755         } else if (aniState->listenTime > ahp->ah_aniPeriod) {
2756                 if (aniState->ofdmPhyErrCount > aniState->listenTime *
2757                     aniState->ofdmTrigHigh / 1000) {
2758                         ath9k_hw_ani_ofdm_err_trigger(ah);
2759                         ath9k_ani_restart(ah);
2760                 } else if (aniState->cckPhyErrCount >
2761                            aniState->listenTime * aniState->cckTrigHigh /
2762                            1000) {
2763                         ath9k_hw_ani_cck_err_trigger(ah);
2764                         ath9k_ani_restart(ah);
2765                 }
2766         }
2767 }
2768
2769 #ifndef ATH_NF_PER_CHAN
2770 static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
2771 {
2772         int i, j;
2773
2774         for (i = 0; i < NUM_NF_READINGS; i++) {
2775                 ah->nfCalHist[i].currIndex = 0;
2776                 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
2777                 ah->nfCalHist[i].invalidNFcount =
2778                         AR_PHY_CCA_FILTERWINDOW_LENGTH;
2779                 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
2780                         ah->nfCalHist[i].nfCalBuffer[j] =
2781                                 AR_PHY_CCA_MAX_GOOD_VALUE;
2782                 }
2783         }
2784         return;
2785 }
2786 #endif
2787
2788 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
2789                                          u32 gpio, u32 type)
2790 {
2791         int addr;
2792         u32 gpio_shift, tmp;
2793
2794         if (gpio > 11)
2795                 addr = AR_GPIO_OUTPUT_MUX3;
2796         else if (gpio > 5)
2797                 addr = AR_GPIO_OUTPUT_MUX2;
2798         else
2799                 addr = AR_GPIO_OUTPUT_MUX1;
2800
2801         gpio_shift = (gpio % 6) * 5;
2802
2803         if (AR_SREV_9280_20_OR_LATER(ah)
2804             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2805                 REG_RMW(ah, addr, (type << gpio_shift),
2806                         (0x1f << gpio_shift));
2807         } else {
2808                 tmp = REG_READ(ah, addr);
2809                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2810                 tmp &= ~(0x1f << gpio_shift);
2811                 tmp |= (type << gpio_shift);
2812                 REG_WRITE(ah, addr, tmp);
2813         }
2814 }
2815
2816 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
2817                          u32 ah_signal_type)
2818 {
2819         u32 gpio_shift;
2820
2821         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2822
2823         gpio_shift = 2 * gpio;
2824
2825         REG_RMW(ah,
2826                 AR_GPIO_OE_OUT,
2827                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2828                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2829 }
2830
2831 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
2832 {
2833         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2834                 AR_GPIO_BIT(gpio));
2835 }
2836
2837 /*
2838  * Configure GPIO Input lines
2839  */
2840 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
2841 {
2842         u32 gpio_shift;
2843
2844         ASSERT(gpio < ah->ah_caps.num_gpio_pins);
2845
2846         gpio_shift = gpio << 1;
2847
2848         REG_RMW(ah,
2849                 AR_GPIO_OE_OUT,
2850                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2851                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2852 }
2853
2854 #ifdef CONFIG_RFKILL
2855 static void ath9k_enable_rfkill(struct ath_hal *ah)
2856 {
2857         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2858                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2859
2860         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2861                     AR_GPIO_INPUT_MUX2_RFSILENT);
2862
2863         ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
2864         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2865 }
2866 #endif
2867
2868 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
2869 {
2870         if (gpio >= ah->ah_caps.num_gpio_pins)
2871                 return 0xffffffff;
2872
2873         if (AR_SREV_9280_10_OR_LATER(ah)) {
2874                 return (MS
2875                         (REG_READ(ah, AR_GPIO_IN_OUT),
2876                          AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
2877         } else {
2878                 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
2879                         AR_GPIO_BIT(gpio)) != 0;
2880         }
2881 }
2882
2883 static int ath9k_hw_post_attach(struct ath_hal *ah)
2884 {
2885         int ecode;
2886
2887         if (!ath9k_hw_chip_test(ah)) {
2888                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2889                          "%s: hardware self-test failed\n", __func__);
2890                 return -ENODEV;
2891         }
2892
2893         ecode = ath9k_hw_rf_claim(ah);
2894         if (ecode != 0)
2895                 return ecode;
2896
2897         ecode = ath9k_hw_eeprom_attach(ah);
2898         if (ecode != 0)
2899                 return ecode;
2900         ecode = ath9k_hw_rfattach(ah);
2901         if (ecode != 0)
2902                 return ecode;
2903
2904         if (!AR_SREV_9100(ah)) {
2905                 ath9k_hw_ani_setup(ah);
2906                 ath9k_hw_ani_attach(ah);
2907         }
2908         return 0;
2909 }
2910
2911 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
2912                                     struct ar5416_eeprom *pEepData,
2913                                     u32 reg, u32 value)
2914 {
2915         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
2916
2917         switch (ah->ah_devid) {
2918         case AR9280_DEVID_PCI:
2919                 if (reg == 0x7894) {
2920                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2921                                  "ini VAL: %x  EEPROM: %x\n", value,
2922                                  (pBase->version & 0xff));
2923
2924                         if ((pBase->version & 0xff) > 0x0a) {
2925                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2926                                          "PWDCLKIND: %d\n",
2927                                          pBase->pwdclkind);
2928                                 value &= ~AR_AN_TOP2_PWDCLKIND;
2929                                 value |= AR_AN_TOP2_PWDCLKIND & (pBase->
2930                                          pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
2931                         } else {
2932                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2933                                          "PWDCLKIND Earlier Rev\n");
2934                         }
2935
2936                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2937                                  "final ini VAL: %x\n", value);
2938                 }
2939                 break;
2940         }
2941         return value;
2942 }
2943
2944 static bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2945 {
2946         struct ath_hal_5416 *ahp = AH5416(ah);
2947         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2948         u16 capField = 0, eeval;
2949
2950         eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
2951
2952         ah->ah_currentRD = eeval;
2953
2954         eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_1);
2955         ah->ah_currentRDExt = eeval;
2956
2957         capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP);
2958
2959         if (ah->ah_opmode != ATH9K_M_HOSTAP &&
2960             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2961                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
2962                         ah->ah_currentRD += 5;
2963                 else if (ah->ah_currentRD == 0x41)
2964                         ah->ah_currentRD = 0x43;
2965                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
2966                          "%s: regdomain mapped to 0x%x\n", __func__,
2967                          ah->ah_currentRD);
2968         }
2969
2970         eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE);
2971         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2972
2973         if (eeval & AR5416_OPFLAGS_11A) {
2974                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2975                 if (ah->ah_config.ht_enable) {
2976                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2977                                 set_bit(ATH9K_MODE_11NA_HT20,
2978                                         pCap->wireless_modes);
2979                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2980                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2981                                         pCap->wireless_modes);
2982                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2983                                         pCap->wireless_modes);
2984                         }
2985                 }
2986         }
2987
2988         if (eeval & AR5416_OPFLAGS_11G) {
2989                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
2990                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2991                 if (ah->ah_config.ht_enable) {
2992                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2993                                 set_bit(ATH9K_MODE_11NG_HT20,
2994                                         pCap->wireless_modes);
2995                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2996                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2997                                         pCap->wireless_modes);
2998                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2999                                         pCap->wireless_modes);
3000                         }
3001                 }
3002         }
3003
3004         pCap->tx_chainmask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK);
3005         if ((ah->ah_isPciExpress)
3006             || (eeval & AR5416_OPFLAGS_11A)) {
3007                 pCap->rx_chainmask =
3008                         ath9k_hw_get_eeprom(ahp, EEP_RX_MASK);
3009         } else {
3010                 pCap->rx_chainmask =
3011                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3012         }
3013
3014         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3015                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3016
3017         pCap->low_2ghz_chan = 2312;
3018         pCap->high_2ghz_chan = 2732;
3019
3020         pCap->low_5ghz_chan = 4920;
3021         pCap->high_5ghz_chan = 6100;
3022
3023         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3024         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3025         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3026
3027         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3028         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3029         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3030
3031         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3032
3033         if (ah->ah_config.ht_enable)
3034                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3035         else
3036                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3037
3038         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3039         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3040         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3041         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3042
3043         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3044                 pCap->total_queues =
3045                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3046         else
3047                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3048
3049         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3050                 pCap->keycache_size =
3051                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3052         else
3053                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3054
3055         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3056         pCap->num_mr_retries = 4;
3057         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3058
3059         if (AR_SREV_9280_10_OR_LATER(ah))
3060                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3061         else
3062                 pCap->num_gpio_pins = AR_NUM_GPIO;
3063
3064         if (AR_SREV_9280_10_OR_LATER(ah)) {
3065                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3066                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3067         } else {
3068                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3069                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3070         }
3071
3072         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3073                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3074                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3075         } else {
3076                 pCap->rts_aggr_limit = (8 * 1024);
3077         }
3078
3079         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3080
3081 #ifdef CONFIG_RFKILL
3082         ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
3083         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3084                 ah->ah_rfkill_gpio =
3085                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3086                 ah->ah_rfkill_polarity =
3087                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3088
3089                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3090         }
3091 #endif
3092
3093         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3094             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3095             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3096             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3097             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3098                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3099         else
3100                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3101
3102         if (AR_SREV_9280(ah))
3103                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3104         else
3105                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3106
3107         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3108                 pCap->reg_cap =
3109                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3110                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3111                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3112                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3113         } else {
3114                 pCap->reg_cap =
3115                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3116                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3117         }
3118
3119         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3120
3121         pCap->num_antcfg_5ghz =
3122                 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_5GHZ);
3123         pCap->num_antcfg_2ghz =
3124                 ath9k_hw_get_num_ant_config(ahp, IEEE80211_BAND_2GHZ);
3125
3126         return true;
3127 }
3128
3129 static void ar5416DisablePciePhy(struct ath_hal *ah)
3130 {
3131         if (!AR_SREV_9100(ah))
3132                 return;
3133
3134         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3135         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3136         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
3137         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
3138         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
3139         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
3140         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3141         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3142         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
3143
3144         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3145 }
3146
3147 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
3148 {
3149         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3150         if (setChip) {
3151                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3152                             AR_RTC_FORCE_WAKE_EN);
3153                 if (!AR_SREV_9100(ah))
3154                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
3155
3156                 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
3157                             AR_RTC_RESET_EN);
3158         }
3159 }
3160
3161 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
3162 {
3163         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3164         if (setChip) {
3165                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3166
3167                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3168                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
3169                                   AR_RTC_FORCE_WAKE_ON_INT);
3170                 } else {
3171                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3172                                     AR_RTC_FORCE_WAKE_EN);
3173                 }
3174         }
3175 }
3176
3177 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
3178                                      int setChip)
3179 {
3180         u32 val;
3181         int i;
3182
3183         if (setChip) {
3184                 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
3185                     AR_RTC_STATUS_SHUTDOWN) {
3186                         if (ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)
3187                             != true) {
3188                                 return false;
3189                         }
3190                 }
3191                 if (AR_SREV_9100(ah))
3192                         REG_SET_BIT(ah, AR_RTC_RESET,
3193                                        AR_RTC_RESET_EN);
3194
3195                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3196                             AR_RTC_FORCE_WAKE_EN);
3197                 udelay(50);
3198
3199                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
3200                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
3201                         if (val == AR_RTC_STATUS_ON)
3202                                 break;
3203                         udelay(50);
3204                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3205                                        AR_RTC_FORCE_WAKE_EN);
3206                 }
3207                 if (i == 0) {
3208                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3209                                  "%s: Failed to wakeup in %uus\n",
3210                                  __func__, POWER_UP_TIME / 20);
3211                         return false;
3212                 }
3213         }
3214
3215         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3216         return true;
3217 }
3218
3219 bool ath9k_hw_setpower(struct ath_hal *ah,
3220                        enum ath9k_power_mode mode)
3221 {
3222         struct ath_hal_5416 *ahp = AH5416(ah);
3223         static const char *modes[] = {
3224                 "AWAKE",
3225                 "FULL-SLEEP",
3226                 "NETWORK SLEEP",
3227                 "UNDEFINED"
3228         };
3229         int status = true, setChip = true;
3230
3231         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
3232                  modes[ahp->ah_powerMode], modes[mode],
3233                  setChip ? "set chip " : "");
3234
3235         switch (mode) {
3236         case ATH9K_PM_AWAKE:
3237                 status = ath9k_hw_set_power_awake(ah, setChip);
3238                 break;
3239         case ATH9K_PM_FULL_SLEEP:
3240                 ath9k_set_power_sleep(ah, setChip);
3241                 ahp->ah_chipFullSleep = true;
3242                 break;
3243         case ATH9K_PM_NETWORK_SLEEP:
3244                 ath9k_set_power_network_sleep(ah, setChip);
3245                 break;
3246         default:
3247                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
3248                          "%s: unknown power mode %u\n", __func__, mode);
3249                 return false;
3250         }
3251         ahp->ah_powerMode = mode;
3252         return status;
3253 }
3254
3255 static struct ath_hal *ath9k_hw_do_attach(u16 devid,
3256                                           struct ath_softc *sc,
3257                                           void __iomem *mem,
3258                                           int *status)
3259 {
3260         struct ath_hal_5416 *ahp;
3261         struct ath_hal *ah;
3262         int ecode;
3263 #ifndef CONFIG_SLOW_ANT_DIV
3264         u32 i;
3265         u32 j;
3266 #endif
3267
3268         ahp = ath9k_hw_newstate(devid, sc, mem, status);
3269         if (ahp == NULL)
3270                 return NULL;
3271
3272         ah = &ahp->ah;
3273
3274         ath9k_hw_set_defaults(ah);
3275
3276         if (ah->ah_config.intr_mitigation != 0)
3277                 ahp->ah_intrMitigation = true;
3278
3279         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3280                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
3281                          __func__);
3282                 ecode = -EIO;
3283                 goto bad;
3284         }
3285
3286         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3287                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
3288                          __func__);
3289                 ecode = -EIO;
3290                 goto bad;
3291         }
3292
3293         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
3294                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
3295                         ah->ah_config.serialize_regmode =
3296                                 SER_REG_MODE_ON;
3297                 } else {
3298                         ah->ah_config.serialize_regmode =
3299                                 SER_REG_MODE_OFF;
3300                 }
3301         }
3302         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3303                 "%s: serialize_regmode is %d\n",
3304                 __func__, ah->ah_config.serialize_regmode);
3305
3306         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
3307             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
3308             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
3309             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
3310                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3311                          "%s: Mac Chip Rev 0x%02x.%x is not supported by "
3312                          "this driver\n", __func__,
3313                          ah->ah_macVersion, ah->ah_macRev);
3314                 ecode = -EOPNOTSUPP;
3315                 goto bad;
3316         }
3317
3318         if (AR_SREV_9100(ah)) {
3319                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3320                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
3321                 ah->ah_isPciExpress = false;
3322         }
3323         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
3324
3325         if (AR_SREV_9160_10_OR_LATER(ah)) {
3326                 if (AR_SREV_9280_10_OR_LATER(ah)) {
3327                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
3328                         ahp->ah_adcGainCalData.calData =
3329                                 &adc_gain_cal_single_sample;
3330                         ahp->ah_adcDcCalData.calData =
3331                                 &adc_dc_cal_single_sample;
3332                         ahp->ah_adcDcCalInitData.calData =
3333                                 &adc_init_dc_cal;
3334                 } else {
3335                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3336                         ahp->ah_adcGainCalData.calData =
3337                                 &adc_gain_cal_multi_sample;
3338                         ahp->ah_adcDcCalData.calData =
3339                                 &adc_dc_cal_multi_sample;
3340                         ahp->ah_adcDcCalInitData.calData =
3341                                 &adc_init_dc_cal;
3342                 }
3343                 ahp->ah_suppCals =
3344                         ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
3345         }
3346
3347         if (AR_SREV_9160(ah)) {
3348                 ah->ah_config.enable_ani = 1;
3349                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
3350                                         ATH9K_ANI_FIRSTEP_LEVEL);
3351         } else {
3352                 ahp->ah_ani_function = ATH9K_ANI_ALL;
3353                 if (AR_SREV_9280_10_OR_LATER(ah)) {
3354                         ahp->ah_ani_function &=
3355                                 ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
3356                 }
3357         }
3358
3359         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3360                  "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
3361                  ah->ah_macVersion, ah->ah_macRev);
3362
3363         if (AR_SREV_9280_20_OR_LATER(ah)) {
3364                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
3365                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
3366                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
3367                                ARRAY_SIZE(ar9280Common_9280_2), 2);
3368
3369                 if (ah->ah_config.pcie_clock_req) {
3370                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3371                                        ar9280PciePhy_clkreq_off_L1_9280,
3372                                        ARRAY_SIZE
3373                                        (ar9280PciePhy_clkreq_off_L1_9280),
3374                                        2);
3375                 } else {
3376                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3377                                        ar9280PciePhy_clkreq_always_on_L1_9280,
3378                                        ARRAY_SIZE
3379                                        (ar9280PciePhy_clkreq_always_on_L1_9280),
3380                                        2);
3381                 }
3382                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
3383                                ar9280Modes_fast_clock_9280_2,
3384                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2),
3385                                3);
3386         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
3387                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
3388                                ARRAY_SIZE(ar9280Modes_9280), 6);
3389                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
3390                                ARRAY_SIZE(ar9280Common_9280), 2);
3391         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
3392                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
3393                                ARRAY_SIZE(ar5416Modes_9160), 6);
3394                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
3395                                ARRAY_SIZE(ar5416Common_9160), 2);
3396                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
3397                                ARRAY_SIZE(ar5416Bank0_9160), 2);
3398                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
3399                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
3400                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
3401                                ARRAY_SIZE(ar5416Bank1_9160), 2);
3402                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
3403                                ARRAY_SIZE(ar5416Bank2_9160), 2);
3404                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
3405                                ARRAY_SIZE(ar5416Bank3_9160), 3);
3406                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
3407                                ARRAY_SIZE(ar5416Bank6_9160), 3);
3408                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
3409                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
3410                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
3411                                ARRAY_SIZE(ar5416Bank7_9160), 2);
3412                 if (AR_SREV_9160_11(ah)) {
3413                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
3414                                        ar5416Addac_91601_1,
3415                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
3416                 } else {
3417                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
3418                                        ARRAY_SIZE(ar5416Addac_9160), 2);
3419                 }
3420         } else if (AR_SREV_9100_OR_LATER(ah)) {
3421                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
3422                                ARRAY_SIZE(ar5416Modes_9100), 6);
3423                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
3424                                ARRAY_SIZE(ar5416Common_9100), 2);
3425                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
3426                                ARRAY_SIZE(ar5416Bank0_9100), 2);
3427                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
3428                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
3429                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
3430                                ARRAY_SIZE(ar5416Bank1_9100), 2);
3431                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
3432                                ARRAY_SIZE(ar5416Bank2_9100), 2);
3433                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
3434                                ARRAY_SIZE(ar5416Bank3_9100), 3);
3435                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
3436                                ARRAY_SIZE(ar5416Bank6_9100), 3);
3437                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
3438                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
3439                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
3440                                ARRAY_SIZE(ar5416Bank7_9100), 2);
3441                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
3442                                ARRAY_SIZE(ar5416Addac_9100), 2);
3443         } else {
3444                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
3445                                ARRAY_SIZE(ar5416Modes), 6);
3446                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
3447                                ARRAY_SIZE(ar5416Common), 2);
3448                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
3449                                ARRAY_SIZE(ar5416Bank0), 2);
3450                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
3451                                ARRAY_SIZE(ar5416BB_RfGain), 3);
3452                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
3453                                ARRAY_SIZE(ar5416Bank1), 2);
3454                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
3455                                ARRAY_SIZE(ar5416Bank2), 2);
3456                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
3457                                ARRAY_SIZE(ar5416Bank3), 3);
3458                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
3459                                ARRAY_SIZE(ar5416Bank6), 3);
3460                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
3461                                ARRAY_SIZE(ar5416Bank6TPC), 3);
3462                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
3463                                ARRAY_SIZE(ar5416Bank7), 2);
3464                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
3465                                ARRAY_SIZE(ar5416Addac), 2);
3466         }
3467
3468         if (ah->ah_isPciExpress)
3469                 ath9k_hw_configpcipowersave(ah, 0);
3470         else
3471                 ar5416DisablePciePhy(ah);
3472
3473         ecode = ath9k_hw_post_attach(ah);
3474         if (ecode != 0)
3475                 goto bad;
3476
3477 #ifndef CONFIG_SLOW_ANT_DIV
3478         if (ah->ah_devid == AR9280_DEVID_PCI) {
3479                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
3480                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
3481
3482                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
3483                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
3484
3485                                 INI_RA(&ahp->ah_iniModes, i, j) =
3486                                         ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
3487                                                            reg, val);
3488                         }
3489                 }
3490         }
3491 #endif
3492
3493         if (!ath9k_hw_fill_cap_info(ah)) {
3494                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3495                          "%s:failed ath9k_hw_fill_cap_info\n", __func__);
3496                 ecode = -EINVAL;
3497                 goto bad;
3498         }
3499
3500         ecode = ath9k_hw_init_macaddr(ah);
3501         if (ecode != 0) {
3502                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3503                          "%s: failed initializing mac address\n",
3504                          __func__);
3505                 goto bad;
3506         }
3507
3508         if (AR_SREV_9285(ah))
3509                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
3510         else
3511                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
3512
3513 #ifndef ATH_NF_PER_CHAN
3514
3515         ath9k_init_nfcal_hist_buffer(ah);
3516 #endif
3517
3518         return ah;
3519
3520 bad:
3521         if (ahp)
3522                 ath9k_hw_detach((struct ath_hal *) ahp);
3523         if (status)
3524                 *status = ecode;
3525         return NULL;
3526 }
3527
3528 void ath9k_hw_detach(struct ath_hal *ah)
3529 {
3530         if (!AR_SREV_9100(ah))
3531                 ath9k_hw_ani_detach(ah);
3532         ath9k_hw_rfdetach(ah);
3533
3534         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3535         kfree(ah);
3536 }
3537
3538 bool ath9k_get_channel_edges(struct ath_hal *ah,
3539                              u16 flags, u16 *low,
3540                              u16 *high)
3541 {
3542         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3543
3544         if (flags & CHANNEL_5GHZ) {
3545                 *low = pCap->low_5ghz_chan;
3546                 *high = pCap->high_5ghz_chan;
3547                 return true;
3548         }
3549         if ((flags & CHANNEL_2GHZ)) {
3550                 *low = pCap->low_2ghz_chan;
3551                 *high = pCap->high_2ghz_chan;
3552
3553                 return true;
3554         }
3555         return false;
3556 }
3557
3558 static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin,
3559                                            u8 pwrMax,
3560                                            u8 *pPwrList,
3561                                            u8 *pVpdList,
3562                                            u16
3563                                            numIntercepts,
3564                                            u8 *pRetVpdList)
3565 {
3566         u16 i, k;
3567         u8 currPwr = pwrMin;
3568         u16 idxL = 0, idxR = 0;
3569
3570         for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
3571                 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
3572                                                numIntercepts, &(idxL),
3573                                                &(idxR));
3574                 if (idxR < 1)
3575                         idxR = 1;
3576                 if (idxL == numIntercepts - 1)
3577                         idxL = (u16) (numIntercepts - 2);
3578                 if (pPwrList[idxL] == pPwrList[idxR])
3579                         k = pVpdList[idxL];
3580                 else
3581                         k = (u16) (((currPwr -
3582                                            pPwrList[idxL]) *
3583                                           pVpdList[idxR] +
3584                                           (pPwrList[idxR] -
3585                                            currPwr) * pVpdList[idxL]) /
3586                                          (pPwrList[idxR] -
3587                                           pPwrList[idxL]));
3588                 pRetVpdList[i] = (u8) k;
3589                 currPwr += 2;
3590         }
3591
3592         return true;
3593 }
3594
3595 static void
3596 ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
3597                                     struct ath9k_channel *chan,
3598                                     struct cal_data_per_freq *pRawDataSet,
3599                                     u8 *bChans,
3600                                     u16 availPiers,
3601                                     u16 tPdGainOverlap,
3602                                     int16_t *pMinCalPower,
3603                                     u16 *pPdGainBoundaries,
3604                                     u8 *pPDADCValues,
3605                                     u16 numXpdGains)
3606 {
3607         int i, j, k;
3608         int16_t ss;
3609         u16 idxL = 0, idxR = 0, numPiers;
3610         static u8 vpdTableL[AR5416_NUM_PD_GAINS]
3611                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3612         static u8 vpdTableR[AR5416_NUM_PD_GAINS]
3613                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3614         static u8 vpdTableI[AR5416_NUM_PD_GAINS]
3615                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3616
3617         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
3618         u8 minPwrT4[AR5416_NUM_PD_GAINS];
3619         u8 maxPwrT4[AR5416_NUM_PD_GAINS];
3620         int16_t vpdStep;
3621         int16_t tmpVal;
3622         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
3623         bool match;
3624         int16_t minDelta = 0;
3625         struct chan_centers centers;
3626
3627         ath9k_hw_get_channel_centers(ah, chan, &centers);
3628
3629         for (numPiers = 0; numPiers < availPiers; numPiers++) {
3630                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
3631                         break;
3632         }
3633
3634         match = ath9k_hw_get_lower_upper_index((u8)
3635                                                FREQ2FBIN(centers.
3636                                                          synth_center,
3637                                                          IS_CHAN_2GHZ
3638                                                          (chan)), bChans,
3639                                                numPiers, &idxL, &idxR);
3640
3641         if (match) {
3642                 for (i = 0; i < numXpdGains; i++) {
3643                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
3644                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
3645                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3646                                                 pRawDataSet[idxL].
3647                                                 pwrPdg[i],
3648                                                 pRawDataSet[idxL].
3649                                                 vpdPdg[i],
3650                                                 AR5416_PD_GAIN_ICEPTS,
3651                                                 vpdTableI[i]);
3652                 }
3653         } else {
3654                 for (i = 0; i < numXpdGains; i++) {
3655                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
3656                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
3657                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
3658                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
3659
3660                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
3661
3662                         maxPwrT4[i] =
3663                                 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
3664                                     pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
3665
3666
3667                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3668                                                 pPwrL, pVpdL,
3669                                                 AR5416_PD_GAIN_ICEPTS,
3670                                                 vpdTableL[i]);
3671                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3672                                                 pPwrR, pVpdR,
3673                                                 AR5416_PD_GAIN_ICEPTS,
3674                                                 vpdTableR[i]);
3675
3676                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
3677                                 vpdTableI[i][j] =
3678                                         (u8) (ath9k_hw_interpolate
3679                                                     ((u16)
3680                                                      FREQ2FBIN(centers.
3681                                                                synth_center,
3682                                                                IS_CHAN_2GHZ
3683                                                                (chan)),
3684                                                      bChans[idxL],
3685                                                      bChans[idxR], vpdTableL[i]
3686                                                      [j], vpdTableR[i]
3687                                                      [j]));
3688                         }
3689                 }
3690         }
3691
3692         *pMinCalPower = (int16_t) (minPwrT4[0] / 2);
3693
3694         k = 0;
3695         for (i = 0; i < numXpdGains; i++) {
3696                 if (i == (numXpdGains - 1))
3697                         pPdGainBoundaries[i] =
3698                                 (u16) (maxPwrT4[i] / 2);
3699                 else
3700                         pPdGainBoundaries[i] =
3701                                 (u16) ((maxPwrT4[i] +
3702                                               minPwrT4[i + 1]) / 4);
3703
3704                 pPdGainBoundaries[i] =
3705                         min((u16) AR5416_MAX_RATE_POWER,
3706                             pPdGainBoundaries[i]);
3707
3708                 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
3709                         minDelta = pPdGainBoundaries[0] - 23;
3710                         pPdGainBoundaries[0] = 23;
3711                 } else {
3712                         minDelta = 0;
3713                 }
3714
3715                 if (i == 0) {
3716                         if (AR_SREV_9280_10_OR_LATER(ah))
3717                                 ss = (int16_t) (0 - (minPwrT4[i] / 2));
3718                         else
3719                                 ss = 0;
3720                 } else {
3721                         ss = (int16_t) ((pPdGainBoundaries[i - 1] -
3722                                          (minPwrT4[i] / 2)) -
3723                                         tPdGainOverlap + 1 + minDelta);
3724                 }
3725                 vpdStep = (int16_t) (vpdTableI[i][1] - vpdTableI[i][0]);
3726                 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3727
3728                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3729                         tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep);
3730                         pPDADCValues[k++] =
3731                                 (u8) ((tmpVal < 0) ? 0 : tmpVal);
3732                         ss++;
3733                 }
3734
3735                 sizeCurrVpdTable =
3736                         (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
3737                 tgtIndex = (u8) (pPdGainBoundaries[i] + tPdGainOverlap -
3738                                        (minPwrT4[i] / 2));
3739                 maxIndex = (tgtIndex <
3740                             sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
3741
3742                 while ((ss < maxIndex)
3743                        && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3744                         pPDADCValues[k++] = vpdTableI[i][ss++];
3745                 }
3746
3747                 vpdStep = (int16_t) (vpdTableI[i][sizeCurrVpdTable - 1] -
3748                                      vpdTableI[i][sizeCurrVpdTable - 2]);
3749                 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3750
3751                 if (tgtIndex > maxIndex) {
3752                         while ((ss <= tgtIndex)
3753                                && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3754                                 tmpVal = (int16_t) ((vpdTableI[i]
3755                                                      [sizeCurrVpdTable -
3756                                                       1] + (ss - maxIndex +
3757                                                             1) * vpdStep));
3758                                 pPDADCValues[k++] = (u8) ((tmpVal >
3759                                                  255) ? 255 : tmpVal);
3760                                 ss++;
3761                         }
3762                 }
3763         }
3764
3765         while (i < AR5416_PD_GAINS_IN_MASK) {
3766                 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
3767                 i++;
3768         }
3769
3770         while (k < AR5416_NUM_PDADC_VALUES) {
3771                 pPDADCValues[k] = pPDADCValues[k - 1];
3772                 k++;
3773         }
3774         return;
3775 }
3776
3777 static bool
3778 ath9k_hw_set_power_cal_table(struct ath_hal *ah,
3779                              struct ar5416_eeprom *pEepData,
3780                              struct ath9k_channel *chan,
3781                              int16_t *pTxPowerIndexOffset)
3782 {
3783         struct cal_data_per_freq *pRawDataset;
3784         u8 *pCalBChans = NULL;
3785         u16 pdGainOverlap_t2;
3786         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
3787         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
3788         u16 numPiers, i, j;
3789         int16_t tMinCalPower;
3790         u16 numXpdGain, xpdMask;
3791         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
3792         u32 reg32, regOffset, regChainOffset;
3793         int16_t modalIdx;
3794         struct ath_hal_5416 *ahp = AH5416(ah);
3795
3796         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
3797         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
3798
3799         if ((pEepData->baseEepHeader.
3800              version & AR5416_EEP_VER_MINOR_MASK) >=
3801             AR5416_EEP_MINOR_VER_2) {
3802                 pdGainOverlap_t2 =
3803                         pEepData->modalHeader[modalIdx].pdGainOverlap;
3804         } else {
3805                 pdGainOverlap_t2 =
3806                         (u16) (MS
3807                                      (REG_READ(ah, AR_PHY_TPCRG5),
3808                                       AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
3809         }
3810
3811         if (IS_CHAN_2GHZ(chan)) {
3812                 pCalBChans = pEepData->calFreqPier2G;
3813                 numPiers = AR5416_NUM_2G_CAL_PIERS;
3814         } else {
3815                 pCalBChans = pEepData->calFreqPier5G;
3816                 numPiers = AR5416_NUM_5G_CAL_PIERS;
3817         }
3818
3819         numXpdGain = 0;
3820
3821         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
3822                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
3823                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
3824                                 break;
3825                         xpdGainValues[numXpdGain] =
3826                                 (u16) (AR5416_PD_GAINS_IN_MASK - i);
3827                         numXpdGain++;
3828                 }
3829         }
3830
3831         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
3832                       (numXpdGain - 1) & 0x3);
3833         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
3834                       xpdGainValues[0]);
3835         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
3836                       xpdGainValues[1]);
3837         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
3838                       xpdGainValues[2]);
3839
3840         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3841                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
3842                     (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
3843                     && (i != 0)) {
3844                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
3845                 } else
3846                         regChainOffset = i * 0x1000;
3847                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
3848                         if (IS_CHAN_2GHZ(chan))
3849                                 pRawDataset = pEepData->calPierData2G[i];
3850                         else
3851                                 pRawDataset = pEepData->calPierData5G[i];
3852
3853                         ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
3854                                                             pRawDataset,
3855                                                             pCalBChans,
3856                                                             numPiers,
3857                                                             pdGainOverlap_t2,
3858                                                             &tMinCalPower,
3859                                                             gainBoundaries,
3860                                                             pdadcValues,
3861                                                             numXpdGain);
3862
3863                         if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
3864
3865                                 REG_WRITE(ah,
3866                                           AR_PHY_TPCRG5 + regChainOffset,
3867                                           SM(pdGainOverlap_t2,
3868                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
3869                                           | SM(gainBoundaries[0],
3870                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
3871                                           | SM(gainBoundaries[1],
3872                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
3873                                           | SM(gainBoundaries[2],
3874                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
3875                                           | SM(gainBoundaries[3],
3876                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
3877                         }
3878
3879                         regOffset =
3880                                 AR_PHY_BASE + (672 << 2) + regChainOffset;
3881                         for (j = 0; j < 32; j++) {
3882                                 reg32 =
3883                                         ((pdadcValues[4 * j + 0] & 0xFF) << 0)
3884                                         | ((pdadcValues[4 * j + 1] & 0xFF) <<
3885                                            8) | ((pdadcValues[4 * j + 2] &
3886                                                   0xFF) << 16) |
3887                                         ((pdadcValues[4 * j + 3] & 0xFF) <<
3888                                          24);
3889                                 REG_WRITE(ah, regOffset, reg32);
3890
3891                                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3892                                          "PDADC (%d,%4x): %4.4x %8.8x\n",
3893                                          i, regChainOffset, regOffset,
3894                                          reg32);
3895                                 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
3896                                 "PDADC: Chain %d | PDADC %3d Value %3d | "
3897                                 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
3898                                 "PDADC %3d Value %3d |\n",
3899                                          i, 4 * j, pdadcValues[4 * j],
3900                                          4 * j + 1, pdadcValues[4 * j + 1],
3901                                          4 * j + 2, pdadcValues[4 * j + 2],
3902                                          4 * j + 3,
3903                                          pdadcValues[4 * j + 3]);
3904
3905                                 regOffset += 4;
3906                         }
3907                 }
3908         }
3909         *pTxPowerIndexOffset = 0;
3910
3911         return true;
3912 }
3913
3914 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
3915 {
3916         struct ath_hal_5416 *ahp = AH5416(ah);
3917         u8 i;
3918
3919         if (ah->ah_isPciExpress != true)
3920                 return;
3921
3922         if (ah->ah_config.pcie_powersave_enable == 2)
3923                 return;
3924
3925         if (restore)
3926                 return;
3927
3928         if (AR_SREV_9280_20_OR_LATER(ah)) {
3929                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
3930                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
3931                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
3932                 }
3933                 udelay(1000);
3934         } else if (AR_SREV_9280(ah)
3935                    && (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
3936                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3937                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3938
3939                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3940                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3941                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3942
3943                 if (ah->ah_config.pcie_clock_req)
3944                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3945                 else
3946                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3947
3948                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3949                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3950                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3951
3952                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3953
3954                 udelay(1000);
3955         } else {
3956                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3957                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3958                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3959                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3960                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3961                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3962                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3963                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3964                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3965                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3966         }
3967
3968         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3969
3970         if (ah->ah_config.pcie_waen) {
3971                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
3972         } else {
3973                 if (AR_SREV_9280(ah))
3974                         REG_WRITE(ah, AR_WA, 0x0040073f);
3975                 else
3976                         REG_WRITE(ah, AR_WA, 0x0000073f);
3977         }
3978 }
3979
3980 static void
3981 ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
3982                                   struct ath9k_channel *chan,
3983                                   struct cal_target_power_leg *powInfo,
3984                                   u16 numChannels,
3985                                   struct cal_target_power_leg *pNewPower,
3986                                   u16 numRates,
3987                                   bool isExtTarget)
3988 {
3989         u16 clo, chi;
3990         int i;
3991         int matchIndex = -1, lowIndex = -1;
3992         u16 freq;
3993         struct chan_centers centers;
3994
3995         ath9k_hw_get_channel_centers(ah, chan, &centers);
3996         freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
3997
3998         if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
3999                 IS_CHAN_2GHZ(chan))) {
4000                 matchIndex = 0;
4001         } else {
4002                 for (i = 0; (i < numChannels)
4003                      && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4004                         if (freq ==
4005                             ath9k_hw_fbin2freq(powInfo[i].bChannel,
4006                                                IS_CHAN_2GHZ(chan))) {
4007                                 matchIndex = i;
4008                                 break;
4009                         } else if ((freq <
4010                                     ath9k_hw_fbin2freq(powInfo[i].bChannel,
4011                                                        IS_CHAN_2GHZ(chan)))
4012                                    && (freq >
4013                                        ath9k_hw_fbin2freq(powInfo[i - 1].
4014                                                           bChannel,
4015                                                           IS_CHAN_2GHZ
4016                                                           (chan)))) {
4017                                 lowIndex = i - 1;
4018                                 break;
4019                         }
4020                 }
4021                 if ((matchIndex == -1) && (lowIndex == -1))
4022                         matchIndex = i - 1;
4023         }
4024
4025         if (matchIndex != -1) {
4026                 *pNewPower = powInfo[matchIndex];
4027         } else {
4028                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4029                                          IS_CHAN_2GHZ(chan));
4030                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4031                                          IS_CHAN_2GHZ(chan));
4032
4033                 for (i = 0; i < numRates; i++) {
4034                         pNewPower->tPow2x[i] =
4035                                 (u8) ath9k_hw_interpolate(freq, clo, chi,
4036                                                                 powInfo
4037                                                                 [lowIndex].
4038                                                                 tPow2x[i],
4039                                                                 powInfo
4040                                                                 [lowIndex +
4041                                                                  1].tPow2x[i]);
4042                 }
4043         }
4044 }
4045
4046 static void
4047 ath9k_hw_get_target_powers(struct ath_hal *ah,
4048                            struct ath9k_channel *chan,
4049                            struct cal_target_power_ht *powInfo,
4050                            u16 numChannels,
4051                            struct cal_target_power_ht *pNewPower,
4052                            u16 numRates,
4053                            bool isHt40Target)
4054 {
4055         u16 clo, chi;
4056         int i;
4057         int matchIndex = -1, lowIndex = -1;
4058         u16 freq;
4059         struct chan_centers centers;
4060
4061         ath9k_hw_get_channel_centers(ah, chan, &centers);
4062         freq = isHt40Target ? centers.synth_center : centers.ctl_center;
4063
4064         if (freq <=
4065                 ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
4066                 matchIndex = 0;
4067         } else {
4068                 for (i = 0; (i < numChannels)
4069                      && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4070                         if (freq ==
4071                             ath9k_hw_fbin2freq(powInfo[i].bChannel,
4072                                                IS_CHAN_2GHZ(chan))) {
4073                                 matchIndex = i;
4074                                 break;
4075                         } else
4076                                 if ((freq <
4077                                      ath9k_hw_fbin2freq(powInfo[i].bChannel,
4078                                                         IS_CHAN_2GHZ(chan)))
4079                                     && (freq >
4080                                         ath9k_hw_fbin2freq(powInfo[i - 1].
4081                                                            bChannel,
4082                                                            IS_CHAN_2GHZ
4083                                                            (chan)))) {
4084                                         lowIndex = i - 1;
4085                                         break;
4086                                 }
4087                 }
4088                 if ((matchIndex == -1) && (lowIndex == -1))
4089                         matchIndex = i - 1;
4090         }
4091
4092         if (matchIndex != -1) {
4093                 *pNewPower = powInfo[matchIndex];
4094         } else {
4095                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4096                                          IS_CHAN_2GHZ(chan));
4097                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4098                                          IS_CHAN_2GHZ(chan));
4099
4100                 for (i = 0; i < numRates; i++) {
4101                         pNewPower->tPow2x[i] =
4102                                 (u8) ath9k_hw_interpolate(freq, clo, chi,
4103                                                                 powInfo
4104                                                                 [lowIndex].
4105                                                                 tPow2x[i],
4106                                                                 powInfo
4107                                                                 [lowIndex +
4108                                                                  1].tPow2x[i]);
4109                 }
4110         }
4111 }
4112
4113 static u16
4114 ath9k_hw_get_max_edge_power(u16 freq,
4115                             struct cal_ctl_edges *pRdEdgesPower,
4116                             bool is2GHz)
4117 {
4118         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4119         int i;
4120
4121         for (i = 0; (i < AR5416_NUM_BAND_EDGES)
4122              && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4123                 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
4124                                                is2GHz)) {
4125                         twiceMaxEdgePower = pRdEdgesPower[i].tPower;
4126                         break;
4127                 } else if ((i > 0)
4128                            && (freq <
4129                                ath9k_hw_fbin2freq(pRdEdgesPower[i].
4130                                                   bChannel, is2GHz))) {
4131                         if (ath9k_hw_fbin2freq
4132                             (pRdEdgesPower[i - 1].bChannel, is2GHz) < freq
4133                             && pRdEdgesPower[i - 1].flag) {
4134                                 twiceMaxEdgePower =
4135                                         pRdEdgesPower[i - 1].tPower;
4136                         }
4137                         break;
4138                 }
4139         }
4140         return twiceMaxEdgePower;
4141 }
4142
4143 static bool
4144 ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
4145                                   struct ar5416_eeprom *pEepData,
4146                                   struct ath9k_channel *chan,
4147                                   int16_t *ratesArray,
4148                                   u16 cfgCtl,
4149                                   u8 AntennaReduction,
4150                                   u8 twiceMaxRegulatoryPower,
4151                                   u8 powerLimit)
4152 {
4153         u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4154         static const u16 tpScaleReductionTable[5] =
4155                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
4156
4157         int i;
4158         int8_t twiceLargestAntenna;
4159         struct cal_ctl_data *rep;
4160         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
4161                 0, { 0, 0, 0, 0}
4162         };
4163         struct cal_target_power_leg targetPowerOfdmExt = {
4164                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
4165                 0, { 0, 0, 0, 0 }
4166         };
4167         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
4168                 0, {0, 0, 0, 0}
4169         };
4170         u8 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4171         u16 ctlModesFor11a[] =
4172                 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
4173         u16 ctlModesFor11g[] =
4174                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
4175                   CTL_2GHT40
4176                 };
4177         u16 numCtlModes, *pCtlMode, ctlMode, freq;
4178         struct chan_centers centers;
4179         int tx_chainmask;
4180         u8 twiceMinEdgePower;
4181         struct ath_hal_5416 *ahp = AH5416(ah);
4182
4183         tx_chainmask = ahp->ah_txchainmask;
4184
4185         ath9k_hw_get_channel_centers(ah, chan, &centers);
4186
4187         twiceLargestAntenna = max(
4188                 pEepData->modalHeader
4189                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
4190                 pEepData->modalHeader
4191                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
4192
4193         twiceLargestAntenna = max((u8) twiceLargestAntenna,
4194                 pEepData->modalHeader
4195                         [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
4196
4197         twiceLargestAntenna =
4198                 (int8_t) min(AntennaReduction - twiceLargestAntenna, 0);
4199
4200         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4201
4202         if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) {
4203                 maxRegAllowedPower -=
4204                         (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
4205         }
4206
4207         scaledPower = min(powerLimit, maxRegAllowedPower);
4208
4209         switch (ar5416_get_ntxchains(tx_chainmask)) {
4210         case 1:
4211                 break;
4212         case 2:
4213                 scaledPower -=
4214                         pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4215                         pwrDecreaseFor2Chain;
4216                 break;
4217         case 3:
4218                 scaledPower -=
4219                         pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4220                         pwrDecreaseFor3Chain;
4221                 break;
4222         }
4223
4224         scaledPower = max(0, (int32_t) scaledPower);
4225
4226         if (IS_CHAN_2GHZ(chan)) {
4227                 numCtlModes =
4228                         ARRAY_SIZE(ctlModesFor11g) -
4229                         SUB_NUM_CTL_MODES_AT_2G_40;
4230                 pCtlMode = ctlModesFor11g;
4231
4232                 ath9k_hw_get_legacy_target_powers(ah, chan,
4233                         pEepData->
4234                         calTargetPowerCck,
4235                         AR5416_NUM_2G_CCK_TARGET_POWERS,
4236                         &targetPowerCck, 4,
4237                         false);
4238                 ath9k_hw_get_legacy_target_powers(ah, chan,
4239                         pEepData->
4240                         calTargetPower2G,
4241                         AR5416_NUM_2G_20_TARGET_POWERS,
4242                         &targetPowerOfdm, 4,
4243                         false);
4244                 ath9k_hw_get_target_powers(ah, chan,
4245                         pEepData->calTargetPower2GHT20,
4246                         AR5416_NUM_2G_20_TARGET_POWERS,
4247                         &targetPowerHt20, 8, false);
4248
4249                 if (IS_CHAN_HT40(chan)) {
4250                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4251                         ath9k_hw_get_target_powers(ah, chan,
4252                                 pEepData->
4253                                 calTargetPower2GHT40,
4254                                 AR5416_NUM_2G_40_TARGET_POWERS,
4255                                 &targetPowerHt40, 8,
4256                                 true);
4257                         ath9k_hw_get_legacy_target_powers(ah, chan,
4258                                 pEepData->
4259                                 calTargetPowerCck,
4260                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
4261                                 &targetPowerCckExt,
4262                                 4, true);
4263                         ath9k_hw_get_legacy_target_powers(ah, chan,
4264                                 pEepData->
4265                                 calTargetPower2G,
4266                                 AR5416_NUM_2G_20_TARGET_POWERS,
4267                                 &targetPowerOfdmExt,
4268                                 4, true);
4269                 }
4270         } else {
4271
4272                 numCtlModes =
4273                         ARRAY_SIZE(ctlModesFor11a) -
4274                         SUB_NUM_CTL_MODES_AT_5G_40;
4275                 pCtlMode = ctlModesFor11a;
4276
4277                 ath9k_hw_get_legacy_target_powers(ah, chan,
4278                         pEepData->
4279                         calTargetPower5G,
4280                         AR5416_NUM_5G_20_TARGET_POWERS,
4281                         &targetPowerOfdm, 4,
4282                         false);
4283                 ath9k_hw_get_target_powers(ah, chan,
4284                         pEepData->calTargetPower5GHT20,
4285                         AR5416_NUM_5G_20_TARGET_POWERS,
4286                         &targetPowerHt20, 8, false);
4287
4288                 if (IS_CHAN_HT40(chan)) {
4289                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4290                         ath9k_hw_get_target_powers(ah, chan,
4291                                 pEepData->
4292                                 calTargetPower5GHT40,
4293                                 AR5416_NUM_5G_40_TARGET_POWERS,
4294                                 &targetPowerHt40, 8,
4295                                 true);
4296                         ath9k_hw_get_legacy_target_powers(ah, chan,
4297                                 pEepData->
4298                                 calTargetPower5G,
4299                                 AR5416_NUM_5G_20_TARGET_POWERS,
4300                                 &targetPowerOfdmExt,
4301                                 4, true);
4302                 }
4303         }
4304
4305         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4306                 bool isHt40CtlMode =
4307                         (pCtlMode[ctlMode] == CTL_5GHT40)
4308                         || (pCtlMode[ctlMode] == CTL_2GHT40);
4309                 if (isHt40CtlMode)
4310                         freq = centers.synth_center;
4311                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4312                         freq = centers.ext_center;
4313                 else
4314                         freq = centers.ctl_center;
4315
4316                 if (ar5416_get_eep_ver(ahp) == 14
4317                     && ar5416_get_eep_rev(ahp) <= 2)
4318                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4319
4320                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4321                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4322                         "EXT_ADDITIVE %d\n",
4323                          ctlMode, numCtlModes, isHt40CtlMode,
4324                          (pCtlMode[ctlMode] & EXT_ADDITIVE));
4325
4326                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i];
4327                      i++) {
4328                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4329                                 "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4330                                 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4331                                 "chan %d\n",
4332                                 i, cfgCtl, pCtlMode[ctlMode],
4333                                 pEepData->ctlIndex[i], chan->channel);
4334
4335                         if ((((cfgCtl & ~CTL_MODE_M) |
4336                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4337                              pEepData->ctlIndex[i])
4338                             ||
4339                             (((cfgCtl & ~CTL_MODE_M) |
4340                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4341                              ((pEepData->
4342                                ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
4343                                 rep = &(pEepData->ctlData[i]);
4344
4345                                 twiceMinEdgePower =
4346                                         ath9k_hw_get_max_edge_power(freq,
4347                                                 rep->
4348                                                 ctlEdges
4349                                                 [ar5416_get_ntxchains
4350                                                 (tx_chainmask)
4351                                                 - 1],
4352                                                 IS_CHAN_2GHZ
4353                                                 (chan));
4354
4355                                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4356                                         "    MATCH-EE_IDX %d: ch %d is2 %d "
4357                                         "2xMinEdge %d chainmask %d chains %d\n",
4358                                          i, freq, IS_CHAN_2GHZ(chan),
4359                                          twiceMinEdgePower, tx_chainmask,
4360                                          ar5416_get_ntxchains
4361                                          (tx_chainmask));
4362                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
4363                                         twiceMaxEdgePower =
4364                                                 min(twiceMaxEdgePower,
4365                                                     twiceMinEdgePower);
4366                                 } else {
4367                                         twiceMaxEdgePower =
4368                                                 twiceMinEdgePower;
4369                                         break;
4370                                 }
4371                         }
4372                 }
4373
4374                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
4375
4376                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
4377                                 "    SEL-Min ctlMode %d pCtlMode %d "
4378                                 "2xMaxEdge %d sP %d minCtlPwr %d\n",
4379                          ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4380                          scaledPower, minCtlPower);
4381
4382                 switch (pCtlMode[ctlMode]) {
4383                 case CTL_11B:
4384                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
4385                              i++) {
4386                                 targetPowerCck.tPow2x[i] =
4387                                         min(targetPowerCck.tPow2x[i],
4388                                             minCtlPower);
4389                         }
4390                         break;
4391                 case CTL_11A:
4392                 case CTL_11G:
4393                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
4394                              i++) {
4395                                 targetPowerOfdm.tPow2x[i] =
4396                                         min(targetPowerOfdm.tPow2x[i],
4397                                             minCtlPower);
4398                         }
4399                         break;
4400                 case CTL_5GHT20:
4401                 case CTL_2GHT20:
4402                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
4403                              i++) {
4404                                 targetPowerHt20.tPow2x[i] =
4405                                         min(targetPowerHt20.tPow2x[i],
4406                                             minCtlPower);
4407                         }
4408                         break;
4409                 case CTL_11B_EXT:
4410                         targetPowerCckExt.tPow2x[0] =
4411                                 min(targetPowerCckExt.tPow2x[0], minCtlPower);
4412                         break;
4413                 case CTL_11A_EXT:
4414                 case CTL_11G_EXT:
4415                         targetPowerOfdmExt.tPow2x[0] =
4416                                 min(targetPowerOfdmExt.tPow2x[0], minCtlPower);
4417                         break;
4418                 case CTL_5GHT40:
4419                 case CTL_2GHT40:
4420                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
4421                              i++) {
4422                                 targetPowerHt40.tPow2x[i] =
4423                                         min(targetPowerHt40.tPow2x[i],
4424                                             minCtlPower);
4425                         }
4426                         break;
4427                 default:
4428                         break;
4429                 }
4430         }
4431
4432         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
4433                 ratesArray[rate18mb] = ratesArray[rate24mb] =
4434                 targetPowerOfdm.tPow2x[0];
4435         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
4436         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
4437         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
4438         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
4439
4440         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
4441                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
4442
4443         if (IS_CHAN_2GHZ(chan)) {
4444                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
4445                 ratesArray[rate2s] = ratesArray[rate2l] =
4446                         targetPowerCck.tPow2x[1];
4447                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
4448                         targetPowerCck.tPow2x[2];
4449                 ;
4450                 ratesArray[rate11s] = ratesArray[rate11l] =
4451                         targetPowerCck.tPow2x[3];
4452                 ;
4453         }
4454         if (IS_CHAN_HT40(chan)) {
4455                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
4456                         ratesArray[rateHt40_0 + i] =
4457                                 targetPowerHt40.tPow2x[i];
4458                 }
4459                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
4460                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
4461                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
4462                 if (IS_CHAN_2GHZ(chan)) {
4463                         ratesArray[rateExtCck] =
4464                                 targetPowerCckExt.tPow2x[0];
4465                 }
4466         }
4467         return true;
4468 }
4469
4470 static int
4471 ath9k_hw_set_txpower(struct ath_hal *ah,
4472                      struct ar5416_eeprom *pEepData,
4473                      struct ath9k_channel *chan,
4474                      u16 cfgCtl,
4475                      u8 twiceAntennaReduction,
4476                      u8 twiceMaxRegulatoryPower,
4477                      u8 powerLimit)
4478 {
4479         struct modal_eep_header *pModal =
4480                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
4481         int16_t ratesArray[Ar5416RateSize];
4482         int16_t txPowerIndexOffset = 0;
4483         u8 ht40PowerIncForPdadc = 2;
4484         int i;
4485
4486         memset(ratesArray, 0, sizeof(ratesArray));
4487
4488         if ((pEepData->baseEepHeader.
4489              version & AR5416_EEP_VER_MINOR_MASK) >=
4490             AR5416_EEP_MINOR_VER_2) {
4491                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
4492         }
4493
4494         if (!ath9k_hw_set_power_per_rate_table(ah, pEepData, chan,
4495                                                &ratesArray[0], cfgCtl,
4496                                                twiceAntennaReduction,
4497                                                twiceMaxRegulatoryPower,
4498                                                powerLimit)) {
4499                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4500                         "ath9k_hw_set_txpower: unable to set "
4501                         "tx power per rate table\n");
4502                 return -EIO;
4503         }
4504
4505         if (!ath9k_hw_set_power_cal_table
4506             (ah, pEepData, chan, &txPowerIndexOffset)) {
4507                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
4508                          "ath9k_hw_set_txpower: unable to set power table\n");
4509                 return -EIO;
4510         }
4511
4512         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
4513                 ratesArray[i] =
4514                         (int16_t) (txPowerIndexOffset + ratesArray[i]);
4515                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
4516                         ratesArray[i] = AR5416_MAX_RATE_POWER;
4517         }
4518
4519         if (AR_SREV_9280_10_OR_LATER(ah)) {
4520                 for (i = 0; i < Ar5416RateSize; i++)
4521                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
4522         }
4523
4524         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
4525                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
4526                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
4527                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
4528                   | ATH9K_POW_SM(ratesArray[rate6mb], 0)
4529                 );
4530         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
4531                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
4532                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
4533                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
4534                   | ATH9K_POW_SM(ratesArray[rate24mb], 0)
4535                 );
4536
4537         if (IS_CHAN_2GHZ(chan)) {
4538                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
4539                           ATH9K_POW_SM(ratesArray[rate2s], 24)
4540                           | ATH9K_POW_SM(ratesArray[rate2l], 16)
4541                           | ATH9K_POW_SM(ratesArray[rateXr], 8)
4542                           | ATH9K_POW_SM(ratesArray[rate1l], 0)
4543                         );
4544                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
4545                           ATH9K_POW_SM(ratesArray[rate11s], 24)
4546                           | ATH9K_POW_SM(ratesArray[rate11l], 16)
4547                           | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
4548                           | ATH9K_POW_SM(ratesArray[rate5_5l], 0)
4549                         );
4550         }
4551
4552         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
4553                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
4554                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
4555                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
4556                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)
4557                 );
4558         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
4559                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
4560                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
4561                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
4562                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)
4563                 );
4564
4565         if (IS_CHAN_HT40(chan)) {
4566                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
4567                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
4568                                        ht40PowerIncForPdadc, 24)
4569                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
4570                                          ht40PowerIncForPdadc, 16)
4571                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
4572                                          ht40PowerIncForPdadc, 8)
4573                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
4574                                          ht40PowerIncForPdadc, 0)
4575                         );
4576                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
4577                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
4578                                        ht40PowerIncForPdadc, 24)
4579                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
4580                                          ht40PowerIncForPdadc, 16)
4581                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
4582                                          ht40PowerIncForPdadc, 8)
4583                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
4584                                          ht40PowerIncForPdadc, 0)
4585                         );
4586
4587                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
4588                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
4589                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
4590                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
4591                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0)
4592                         );
4593         }
4594
4595         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
4596                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
4597                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)
4598                 );
4599
4600         i = rate6mb;
4601         if (IS_CHAN_HT40(chan))
4602                 i = rateHt40_0;
4603         else if (IS_CHAN_HT20(chan))
4604                 i = rateHt20_0;
4605
4606         if (AR_SREV_9280_10_OR_LATER(ah))
4607                 ah->ah_maxPowerLevel =
4608                         ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
4609         else
4610                 ah->ah_maxPowerLevel = ratesArray[i];
4611
4612         return 0;
4613 }
4614
4615 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
4616                                                  u32 coef_scaled,
4617                                                  u32 *coef_mantissa,
4618                                                  u32 *coef_exponent)
4619 {
4620         u32 coef_exp, coef_man;
4621
4622         for (coef_exp = 31; coef_exp > 0; coef_exp--)
4623                 if ((coef_scaled >> coef_exp) & 0x1)
4624                         break;
4625
4626         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
4627
4628         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
4629
4630         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
4631         *coef_exponent = coef_exp - 16;
4632 }
4633
4634 static void
4635 ath9k_hw_set_delta_slope(struct ath_hal *ah,
4636                          struct ath9k_channel *chan)
4637 {
4638         u32 coef_scaled, ds_coef_exp, ds_coef_man;
4639         u32 clockMhzScaled = 0x64000000;
4640         struct chan_centers centers;
4641
4642         if (IS_CHAN_HALF_RATE(chan))
4643                 clockMhzScaled = clockMhzScaled >> 1;
4644         else if (IS_CHAN_QUARTER_RATE(chan))
4645                 clockMhzScaled = clockMhzScaled >> 2;
4646
4647         ath9k_hw_get_channel_centers(ah, chan, &centers);
4648         coef_scaled = clockMhzScaled / centers.synth_center;
4649
4650         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4651                                       &ds_coef_exp);
4652
4653         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4654                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
4655         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4656                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
4657
4658         coef_scaled = (9 * coef_scaled) / 10;
4659
4660         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4661                                       &ds_coef_exp);
4662
4663         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4664                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
4665         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4666                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
4667 }
4668
4669 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
4670                                         struct ath9k_channel *chan)
4671 {
4672         int bb_spur = AR_NO_SPUR;
4673         int freq;
4674         int bin, cur_bin;
4675         int bb_spur_off, spur_subchannel_sd;
4676         int spur_freq_sd;
4677         int spur_delta_phase;
4678         int denominator;
4679         int upper, lower, cur_vit_mask;
4680         int tmp, newVal;
4681         int i;
4682         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4683                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4684         };
4685         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4686                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4687         };
4688         int inc[4] = { 0, 100, 0, 0 };
4689         struct chan_centers centers;
4690
4691         int8_t mask_m[123];
4692         int8_t mask_p[123];
4693         int8_t mask_amt;
4694         int tmp_mask;
4695         int cur_bb_spur;
4696         bool is2GHz = IS_CHAN_2GHZ(chan);
4697
4698         memset(&mask_m, 0, sizeof(int8_t) * 123);
4699         memset(&mask_p, 0, sizeof(int8_t) * 123);
4700
4701         ath9k_hw_get_channel_centers(ah, chan, &centers);
4702         freq = centers.synth_center;
4703
4704         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
4705         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4706                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4707
4708                 if (is2GHz)
4709                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
4710                 else
4711                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
4712
4713                 if (AR_NO_SPUR == cur_bb_spur)
4714                         break;
4715                 cur_bb_spur = cur_bb_spur - freq;
4716
4717                 if (IS_CHAN_HT40(chan)) {
4718                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
4719                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
4720                                 bb_spur = cur_bb_spur;
4721                                 break;
4722                         }
4723                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
4724                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
4725                         bb_spur = cur_bb_spur;
4726                         break;
4727                 }
4728         }
4729
4730         if (AR_NO_SPUR == bb_spur) {
4731                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4732                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4733                 return;
4734         } else {
4735                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4736                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4737         }
4738
4739         bin = bb_spur * 320;
4740
4741         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4742
4743         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4744                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4745                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4746                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4747         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
4748
4749         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4750                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4751                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4752                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4753                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4754         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
4755
4756         if (IS_CHAN_HT40(chan)) {
4757                 if (bb_spur < 0) {
4758                         spur_subchannel_sd = 1;
4759                         bb_spur_off = bb_spur + 10;
4760                 } else {
4761                         spur_subchannel_sd = 0;
4762                         bb_spur_off = bb_spur - 10;
4763                 }
4764         } else {
4765                 spur_subchannel_sd = 0;
4766                 bb_spur_off = bb_spur;
4767         }
4768
4769         if (IS_CHAN_HT40(chan))
4770                 spur_delta_phase =
4771                         ((bb_spur * 262144) /
4772                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4773         else
4774                 spur_delta_phase =
4775                         ((bb_spur * 524288) /
4776                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4777
4778         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
4779         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
4780
4781         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4782                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4783                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4784         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
4785
4786         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
4787         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
4788
4789         cur_bin = -6000;
4790         upper = bin + 100;
4791         lower = bin - 100;
4792
4793         for (i = 0; i < 4; i++) {
4794                 int pilot_mask = 0;
4795                 int chan_mask = 0;
4796                 int bp = 0;
4797                 for (bp = 0; bp < 30; bp++) {
4798                         if ((cur_bin > lower) && (cur_bin < upper)) {
4799                                 pilot_mask = pilot_mask | 0x1 << bp;
4800                                 chan_mask = chan_mask | 0x1 << bp;
4801                         }
4802                         cur_bin += 100;
4803                 }
4804                 cur_bin += inc[i];
4805                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4806                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4807         }
4808
4809         cur_vit_mask = 6100;
4810         upper = bin + 120;
4811         lower = bin - 120;
4812
4813         for (i = 0; i < 123; i++) {
4814                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
4815
4816                         /* workaround for gcc bug #37014 */
4817                         volatile int tmp = abs(cur_vit_mask - bin);
4818
4819                         if (tmp < 75)
4820                                 mask_amt = 1;
4821                         else
4822                                 mask_amt = 0;
4823                         if (cur_vit_mask < 0)
4824                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
4825                         else
4826                                 mask_p[cur_vit_mask / 100] = mask_amt;
4827                 }
4828                 cur_vit_mask -= 100;
4829         }
4830
4831         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
4832                 | (mask_m[48] << 26) | (mask_m[49] << 24)
4833                 | (mask_m[50] << 22) | (mask_m[51] << 20)
4834                 | (mask_m[52] << 18) | (mask_m[53] << 16)
4835                 | (mask_m[54] << 14) | (mask_m[55] << 12)
4836                 | (mask_m[56] << 10) | (mask_m[57] << 8)
4837                 | (mask_m[58] << 6) | (mask_m[59] << 4)
4838                 | (mask_m[60] << 2) | (mask_m[61] << 0);
4839         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
4840         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
4841
4842         tmp_mask = (mask_m[31] << 28)
4843                 | (mask_m[32] << 26) | (mask_m[33] << 24)
4844                 | (mask_m[34] << 22) | (mask_m[35] << 20)
4845                 | (mask_m[36] << 18) | (mask_m[37] << 16)
4846                 | (mask_m[48] << 14) | (mask_m[39] << 12)
4847                 | (mask_m[40] << 10) | (mask_m[41] << 8)
4848                 | (mask_m[42] << 6) | (mask_m[43] << 4)
4849                 | (mask_m[44] << 2) | (mask_m[45] << 0);
4850         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
4851         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
4852
4853         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
4854                 | (mask_m[18] << 26) | (mask_m[18] << 24)
4855                 | (mask_m[20] << 22) | (mask_m[20] << 20)
4856                 | (mask_m[22] << 18) | (mask_m[22] << 16)
4857                 | (mask_m[24] << 14) | (mask_m[24] << 12)
4858                 | (mask_m[25] << 10) | (mask_m[26] << 8)
4859                 | (mask_m[27] << 6) | (mask_m[28] << 4)
4860                 | (mask_m[29] << 2) | (mask_m[30] << 0);
4861         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
4862         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
4863
4864         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
4865                 | (mask_m[2] << 26) | (mask_m[3] << 24)
4866                 | (mask_m[4] << 22) | (mask_m[5] << 20)
4867                 | (mask_m[6] << 18) | (mask_m[7] << 16)
4868                 | (mask_m[8] << 14) | (mask_m[9] << 12)
4869                 | (mask_m[10] << 10) | (mask_m[11] << 8)
4870                 | (mask_m[12] << 6) | (mask_m[13] << 4)
4871                 | (mask_m[14] << 2) | (mask_m[15] << 0);
4872         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
4873         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
4874
4875         tmp_mask = (mask_p[15] << 28)
4876                 | (mask_p[14] << 26) | (mask_p[13] << 24)
4877                 | (mask_p[12] << 22) | (mask_p[11] << 20)
4878                 | (mask_p[10] << 18) | (mask_p[9] << 16)
4879                 | (mask_p[8] << 14) | (mask_p[7] << 12)
4880                 | (mask_p[6] << 10) | (mask_p[5] << 8)
4881                 | (mask_p[4] << 6) | (mask_p[3] << 4)
4882                 | (mask_p[2] << 2) | (mask_p[1] << 0);
4883         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
4884         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
4885
4886         tmp_mask = (mask_p[30] << 28)
4887                 | (mask_p[29] << 26) | (mask_p[28] << 24)
4888                 | (mask_p[27] << 22) | (mask_p[26] << 20)
4889                 | (mask_p[25] << 18) | (mask_p[24] << 16)
4890                 | (mask_p[23] << 14) | (mask_p[22] << 12)
4891                 | (mask_p[21] << 10) | (mask_p[20] << 8)
4892                 | (mask_p[19] << 6) | (mask_p[18] << 4)
4893                 | (mask_p[17] << 2) | (mask_p[16] << 0);
4894         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
4895         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
4896
4897         tmp_mask = (mask_p[45] << 28)
4898                 | (mask_p[44] << 26) | (mask_p[43] << 24)
4899                 | (mask_p[42] << 22) | (mask_p[41] << 20)
4900                 | (mask_p[40] << 18) | (mask_p[39] << 16)
4901                 | (mask_p[38] << 14) | (mask_p[37] << 12)
4902                 | (mask_p[36] << 10) | (mask_p[35] << 8)
4903                 | (mask_p[34] << 6) | (mask_p[33] << 4)
4904                 | (mask_p[32] << 2) | (mask_p[31] << 0);
4905         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
4906         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
4907
4908         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
4909                 | (mask_p[59] << 26) | (mask_p[58] << 24)
4910                 | (mask_p[57] << 22) | (mask_p[56] << 20)
4911                 | (mask_p[55] << 18) | (mask_p[54] << 16)
4912                 | (mask_p[53] << 14) | (mask_p[52] << 12)
4913                 | (mask_p[51] << 10) | (mask_p[50] << 8)
4914                 | (mask_p[49] << 6) | (mask_p[48] << 4)
4915                 | (mask_p[47] << 2) | (mask_p[46] << 0);
4916         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
4917         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
4918 }
4919
4920 static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
4921                                    struct ath9k_channel *chan)
4922 {
4923         int bb_spur = AR_NO_SPUR;
4924         int bin, cur_bin;
4925         int spur_freq_sd;
4926         int spur_delta_phase;
4927         int denominator;
4928         int upper, lower, cur_vit_mask;
4929         int tmp, new;
4930         int i;
4931         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4932                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4933         };
4934         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4935                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4936         };
4937         int inc[4] = { 0, 100, 0, 0 };
4938
4939         int8_t mask_m[123];
4940         int8_t mask_p[123];
4941         int8_t mask_amt;
4942         int tmp_mask;
4943         int cur_bb_spur;
4944         bool is2GHz = IS_CHAN_2GHZ(chan);
4945
4946         memset(&mask_m, 0, sizeof(int8_t) * 123);
4947         memset(&mask_p, 0, sizeof(int8_t) * 123);
4948
4949         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4950                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4951                 if (AR_NO_SPUR == cur_bb_spur)
4952                         break;
4953                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
4954                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
4955                         bb_spur = cur_bb_spur;
4956                         break;
4957                 }
4958         }
4959
4960         if (AR_NO_SPUR == bb_spur)
4961                 return;
4962
4963         bin = bb_spur * 32;
4964
4965         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4966         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4967                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4968                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4969                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4970
4971         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
4972
4973         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4974                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4975                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4976                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4977                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4978         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
4979
4980         spur_delta_phase = ((bb_spur * 524288) / 100) &
4981                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4982
4983         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
4984         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
4985
4986         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4987                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4988                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4989         REG_WRITE(ah, AR_PHY_TIMING11, new);
4990
4991         cur_bin = -6000;
4992         upper = bin + 100;
4993         lower = bin - 100;
4994
4995         for (i = 0; i < 4; i++) {
4996                 int pilot_mask = 0;
4997                 int chan_mask = 0;
4998                 int bp = 0;
4999                 for (bp = 0; bp < 30; bp++) {
5000                         if ((cur_bin > lower) && (cur_bin < upper)) {
5001                                 pilot_mask = pilot_mask | 0x1 << bp;
5002                                 chan_mask = chan_mask | 0x1 << bp;
5003                         }
5004                         cur_bin += 100;
5005                 }
5006                 cur_bin += inc[i];
5007                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
5008                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
5009         }
5010
5011         cur_vit_mask = 6100;
5012         upper = bin + 120;
5013         lower = bin - 120;
5014
5015         for (i = 0; i < 123; i++) {
5016                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
5017
5018                         /* workaround for gcc bug #37014 */
5019                         volatile int tmp = abs(cur_vit_mask - bin);
5020
5021                         if (tmp < 75)
5022                                 mask_amt = 1;
5023                         else
5024                                 mask_amt = 0;
5025                         if (cur_vit_mask < 0)
5026                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
5027                         else
5028                                 mask_p[cur_vit_mask / 100] = mask_amt;
5029                 }
5030                 cur_vit_mask -= 100;
5031         }
5032
5033         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
5034                 | (mask_m[48] << 26) | (mask_m[49] << 24)
5035                 | (mask_m[50] << 22) | (mask_m[51] << 20)
5036                 | (mask_m[52] << 18) | (mask_m[53] << 16)
5037                 | (mask_m[54] << 14) | (mask_m[55] << 12)
5038                 | (mask_m[56] << 10) | (mask_m[57] << 8)
5039                 | (mask_m[58] << 6) | (mask_m[59] << 4)
5040                 | (mask_m[60] << 2) | (mask_m[61] << 0);
5041         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
5042         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
5043
5044         tmp_mask = (mask_m[31] << 28)
5045                 | (mask_m[32] << 26) | (mask_m[33] << 24)
5046                 | (mask_m[34] << 22) | (mask_m[35] << 20)
5047                 | (mask_m[36] << 18) | (mask_m[37] << 16)
5048                 | (mask_m[48] << 14) | (mask_m[39] << 12)
5049                 | (mask_m[40] << 10) | (mask_m[41] << 8)
5050                 | (mask_m[42] << 6) | (mask_m[43] << 4)
5051                 | (mask_m[44] << 2) | (mask_m[45] << 0);
5052         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
5053         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
5054
5055         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
5056                 | (mask_m[18] << 26) | (mask_m[18] << 24)
5057                 | (mask_m[20] << 22) | (mask_m[20] << 20)
5058                 | (mask_m[22] << 18) | (mask_m[22] << 16)
5059                 | (mask_m[24] << 14) | (mask_m[24] << 12)
5060                 | (mask_m[25] << 10) | (mask_m[26] << 8)
5061                 | (mask_m[27] << 6) | (mask_m[28] << 4)
5062                 | (mask_m[29] << 2) | (mask_m[30] << 0);
5063         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
5064         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
5065
5066         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
5067                 | (mask_m[2] << 26) | (mask_m[3] << 24)
5068                 | (mask_m[4] << 22) | (mask_m[5] << 20)
5069                 | (mask_m[6] << 18) | (mask_m[7] << 16)
5070                 | (mask_m[8] << 14) | (mask_m[9] << 12)
5071                 | (mask_m[10] << 10) | (mask_m[11] << 8)
5072                 | (mask_m[12] << 6) | (mask_m[13] << 4)
5073                 | (mask_m[14] << 2) | (mask_m[15] << 0);
5074         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
5075         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
5076
5077         tmp_mask = (mask_p[15] << 28)
5078                 | (mask_p[14] << 26) | (mask_p[13] << 24)
5079                 | (mask_p[12] << 22) | (mask_p[11] << 20)
5080                 | (mask_p[10] << 18) | (mask_p[9] << 16)
5081                 | (mask_p[8] << 14) | (mask_p[7] << 12)
5082                 | (mask_p[6] << 10) | (mask_p[5] << 8)
5083                 | (mask_p[4] << 6) | (mask_p[3] << 4)
5084                 | (mask_p[2] << 2) | (mask_p[1] << 0);
5085         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
5086         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
5087
5088         tmp_mask = (mask_p[30] << 28)
5089                 | (mask_p[29] << 26) | (mask_p[28] << 24)
5090                 | (mask_p[27] << 22) | (mask_p[26] << 20)
5091                 | (mask_p[25] << 18) | (mask_p[24] << 16)
5092                 | (mask_p[23] << 14) | (mask_p[22] << 12)
5093                 | (mask_p[21] << 10) | (mask_p[20] << 8)
5094                 | (mask_p[19] << 6) | (mask_p[18] << 4)
5095                 | (mask_p[17] << 2) | (mask_p[16] << 0);
5096         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
5097         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
5098
5099         tmp_mask = (mask_p[45] << 28)
5100                 | (mask_p[44] << 26) | (mask_p[43] << 24)
5101                 | (mask_p[42] << 22) | (mask_p[41] << 20)
5102                 | (mask_p[40] << 18) | (mask_p[39] << 16)
5103                 | (mask_p[38] << 14) | (mask_p[37] << 12)
5104                 | (mask_p[36] << 10) | (mask_p[35] << 8)
5105                 | (mask_p[34] << 6) | (mask_p[33] << 4)
5106                 | (mask_p[32] << 2) | (mask_p[31] << 0);
5107         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
5108         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
5109
5110         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
5111                 | (mask_p[59] << 26) | (mask_p[58] << 24)
5112                 | (mask_p[57] << 22) | (mask_p[56] << 20)
5113                 | (mask_p[55] << 18) | (mask_p[54] << 16)
5114                 | (mask_p[53] << 14) | (mask_p[52] << 12)
5115                 | (mask_p[51] << 10) | (mask_p[50] << 8)
5116                 | (mask_p[49] << 6) | (mask_p[48] << 4)
5117                 | (mask_p[47] << 2) | (mask_p[46] << 0);
5118         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
5119         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
5120 }
5121
5122 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
5123 {
5124         struct ath_hal_5416 *ahp = AH5416(ah);
5125         int rx_chainmask, tx_chainmask;
5126
5127         rx_chainmask = ahp->ah_rxchainmask;
5128         tx_chainmask = ahp->ah_txchainmask;
5129
5130         switch (rx_chainmask) {
5131         case 0x5:
5132                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5133                             AR_PHY_SWAP_ALT_CHAIN);
5134         case 0x3:
5135                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
5136                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
5137                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
5138                         break;
5139                 }
5140         case 0x1:
5141         case 0x2:
5142                 if (!AR_SREV_9280(ah))
5143                         break;
5144         case 0x7:
5145                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5146                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5147                 break;
5148         default:
5149                 break;
5150         }
5151
5152         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
5153         if (tx_chainmask == 0x5) {
5154                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5155                             AR_PHY_SWAP_ALT_CHAIN);
5156         }
5157         if (AR_SREV_9100(ah))
5158                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
5159                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
5160 }
5161
5162 static void ath9k_hw_set_addac(struct ath_hal *ah,
5163                                struct ath9k_channel *chan)
5164 {
5165         struct modal_eep_header *pModal;
5166         struct ath_hal_5416 *ahp = AH5416(ah);
5167         struct ar5416_eeprom *eep = &ahp->ah_eeprom;
5168         u8 biaslevel;
5169
5170         if (ah->ah_macVersion != AR_SREV_VERSION_9160)
5171                 return;
5172
5173         if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
5174                 return;
5175
5176         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
5177
5178         if (pModal->xpaBiasLvl != 0xff) {
5179                 biaslevel = pModal->xpaBiasLvl;
5180         } else {
5181
5182                 u16 resetFreqBin, freqBin, freqCount = 0;
5183                 struct chan_centers centers;
5184
5185                 ath9k_hw_get_channel_centers(ah, chan, &centers);
5186
5187                 resetFreqBin =
5188                         FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
5189                 freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
5190                 biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14);
5191
5192                 freqCount++;
5193
5194                 while (freqCount < 3) {
5195            &nb