44401f6f578d01c7ce5a01b8f958d7cb93e37b13
[linux-2.6.git] / drivers / net / wireless / ath5k / base.c
1 /*-
2  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3  * Copyright (c) 2004-2005 Atheros Communications, Inc.
4  * Copyright (c) 2006 Devicescape Software, Inc.
5  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7  *
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer,
15  *    without modification.
16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18  *    redistribution must be conditioned upon including a substantially
19  *    similar Disclaimer requirement for further binary redistribution.
20  * 3. Neither the names of the above-listed copyright holders nor the names
21  *    of any contributors may be used to endorse or promote products derived
22  *    from this software without specific prior written permission.
23  *
24  * Alternatively, this software may be distributed under the terms of the
25  * GNU General Public License ("GPL") version 2 as published by the Free
26  * Software Foundation.
27  *
28  * NO WARRANTY
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39  * THE POSSIBILITY OF SUCH DAMAGES.
40  *
41  */
42
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53
54 #include <net/ieee80211_radiotap.h>
55
56 #include <asm/unaligned.h>
57
58 #include "base.h"
59 #include "reg.h"
60 #include "debug.h"
61
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63
64
65 /******************\
66 * Internal defines *
67 \******************/
68
69 /* Module info */
70 MODULE_AUTHOR("Jiri Slaby");
71 MODULE_AUTHOR("Nick Kossifidis");
72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74 MODULE_LICENSE("Dual BSD/GPL");
75 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
76
77
78 /* Known PCI ids */
79 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80         { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81         { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82         { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83         { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84         { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85         { PCI_VDEVICE(3COM_2,  0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86         { PCI_VDEVICE(3COM,    0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87         { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88         { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89         { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90         { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91         { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92         { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93         { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94         { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95         { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
96         { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
97         { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
98         { 0 }
99 };
100 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
101
102 /* Known SREVs */
103 static struct ath5k_srev_name srev_names[] = {
104         { "5210",       AR5K_VERSION_MAC,       AR5K_SREV_AR5210 },
105         { "5311",       AR5K_VERSION_MAC,       AR5K_SREV_AR5311 },
106         { "5311A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311A },
107         { "5311B",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311B },
108         { "5211",       AR5K_VERSION_MAC,       AR5K_SREV_AR5211 },
109         { "5212",       AR5K_VERSION_MAC,       AR5K_SREV_AR5212 },
110         { "5213",       AR5K_VERSION_MAC,       AR5K_SREV_AR5213 },
111         { "5213A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5213A },
112         { "2413",       AR5K_VERSION_MAC,       AR5K_SREV_AR2413 },
113         { "2414",       AR5K_VERSION_MAC,       AR5K_SREV_AR2414 },
114         { "5424",       AR5K_VERSION_MAC,       AR5K_SREV_AR5424 },
115         { "5413",       AR5K_VERSION_MAC,       AR5K_SREV_AR5413 },
116         { "5414",       AR5K_VERSION_MAC,       AR5K_SREV_AR5414 },
117         { "2415",       AR5K_VERSION_MAC,       AR5K_SREV_AR2415 },
118         { "5416",       AR5K_VERSION_MAC,       AR5K_SREV_AR5416 },
119         { "5418",       AR5K_VERSION_MAC,       AR5K_SREV_AR5418 },
120         { "2425",       AR5K_VERSION_MAC,       AR5K_SREV_AR2425 },
121         { "2417",       AR5K_VERSION_MAC,       AR5K_SREV_AR2417 },
122         { "xxxxx",      AR5K_VERSION_MAC,       AR5K_SREV_UNKNOWN },
123         { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
124         { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
125         { "5111A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111A },
126         { "2111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2111 },
127         { "5112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112 },
128         { "5112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112A },
129         { "5112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112B },
130         { "2112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112 },
131         { "2112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112A },
132         { "2112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112B },
133         { "2413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2413 },
134         { "5413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5413 },
135         { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
136         { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
137         { "5424",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5424 },
138         { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
139         { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
140 };
141
142 static struct ieee80211_rate ath5k_rates[] = {
143         { .bitrate = 10,
144           .hw_value = ATH5K_RATE_CODE_1M, },
145         { .bitrate = 20,
146           .hw_value = ATH5K_RATE_CODE_2M,
147           .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
148           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
149         { .bitrate = 55,
150           .hw_value = ATH5K_RATE_CODE_5_5M,
151           .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
152           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
153         { .bitrate = 110,
154           .hw_value = ATH5K_RATE_CODE_11M,
155           .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
156           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157         { .bitrate = 60,
158           .hw_value = ATH5K_RATE_CODE_6M,
159           .flags = 0 },
160         { .bitrate = 90,
161           .hw_value = ATH5K_RATE_CODE_9M,
162           .flags = 0 },
163         { .bitrate = 120,
164           .hw_value = ATH5K_RATE_CODE_12M,
165           .flags = 0 },
166         { .bitrate = 180,
167           .hw_value = ATH5K_RATE_CODE_18M,
168           .flags = 0 },
169         { .bitrate = 240,
170           .hw_value = ATH5K_RATE_CODE_24M,
171           .flags = 0 },
172         { .bitrate = 360,
173           .hw_value = ATH5K_RATE_CODE_36M,
174           .flags = 0 },
175         { .bitrate = 480,
176           .hw_value = ATH5K_RATE_CODE_48M,
177           .flags = 0 },
178         { .bitrate = 540,
179           .hw_value = ATH5K_RATE_CODE_54M,
180           .flags = 0 },
181         /* XR missing */
182 };
183
184 /*
185  * Prototypes - PCI stack related functions
186  */
187 static int __devinit    ath5k_pci_probe(struct pci_dev *pdev,
188                                 const struct pci_device_id *id);
189 static void __devexit   ath5k_pci_remove(struct pci_dev *pdev);
190 #ifdef CONFIG_PM
191 static int              ath5k_pci_suspend(struct pci_dev *pdev,
192                                         pm_message_t state);
193 static int              ath5k_pci_resume(struct pci_dev *pdev);
194 #else
195 #define ath5k_pci_suspend NULL
196 #define ath5k_pci_resume NULL
197 #endif /* CONFIG_PM */
198
199 static struct pci_driver ath5k_pci_driver = {
200         .name           = "ath5k_pci",
201         .id_table       = ath5k_pci_id_table,
202         .probe          = ath5k_pci_probe,
203         .remove         = __devexit_p(ath5k_pci_remove),
204         .suspend        = ath5k_pci_suspend,
205         .resume         = ath5k_pci_resume,
206 };
207
208
209
210 /*
211  * Prototypes - MAC 802.11 stack related functions
212  */
213 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
214 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
215 static int ath5k_reset_wake(struct ath5k_softc *sc);
216 static int ath5k_start(struct ieee80211_hw *hw);
217 static void ath5k_stop(struct ieee80211_hw *hw);
218 static int ath5k_add_interface(struct ieee80211_hw *hw,
219                 struct ieee80211_if_init_conf *conf);
220 static void ath5k_remove_interface(struct ieee80211_hw *hw,
221                 struct ieee80211_if_init_conf *conf);
222 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
223 static int ath5k_config_interface(struct ieee80211_hw *hw,
224                 struct ieee80211_vif *vif,
225                 struct ieee80211_if_conf *conf);
226 static void ath5k_configure_filter(struct ieee80211_hw *hw,
227                 unsigned int changed_flags,
228                 unsigned int *new_flags,
229                 int mc_count, struct dev_mc_list *mclist);
230 static int ath5k_set_key(struct ieee80211_hw *hw,
231                 enum set_key_cmd cmd,
232                 const u8 *local_addr, const u8 *addr,
233                 struct ieee80211_key_conf *key);
234 static int ath5k_get_stats(struct ieee80211_hw *hw,
235                 struct ieee80211_low_level_stats *stats);
236 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
237                 struct ieee80211_tx_queue_stats *stats);
238 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
239 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
240 static int ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb);
241
242 static struct ieee80211_ops ath5k_hw_ops = {
243         .tx             = ath5k_tx,
244         .start          = ath5k_start,
245         .stop           = ath5k_stop,
246         .add_interface  = ath5k_add_interface,
247         .remove_interface = ath5k_remove_interface,
248         .config         = ath5k_config,
249         .config_interface = ath5k_config_interface,
250         .configure_filter = ath5k_configure_filter,
251         .set_key        = ath5k_set_key,
252         .get_stats      = ath5k_get_stats,
253         .conf_tx        = NULL,
254         .get_tx_stats   = ath5k_get_tx_stats,
255         .get_tsf        = ath5k_get_tsf,
256         .reset_tsf      = ath5k_reset_tsf,
257 };
258
259 /*
260  * Prototypes - Internal functions
261  */
262 /* Attach detach */
263 static int      ath5k_attach(struct pci_dev *pdev,
264                         struct ieee80211_hw *hw);
265 static void     ath5k_detach(struct pci_dev *pdev,
266                         struct ieee80211_hw *hw);
267 /* Channel/mode setup */
268 static inline short ath5k_ieee2mhz(short chan);
269 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
270                                 struct ieee80211_channel *channels,
271                                 unsigned int mode,
272                                 unsigned int max);
273 static int      ath5k_setup_bands(struct ieee80211_hw *hw);
274 static int      ath5k_chan_set(struct ath5k_softc *sc,
275                                 struct ieee80211_channel *chan);
276 static void     ath5k_setcurmode(struct ath5k_softc *sc,
277                                 unsigned int mode);
278 static void     ath5k_mode_setup(struct ath5k_softc *sc);
279
280 /* Descriptor setup */
281 static int      ath5k_desc_alloc(struct ath5k_softc *sc,
282                                 struct pci_dev *pdev);
283 static void     ath5k_desc_free(struct ath5k_softc *sc,
284                                 struct pci_dev *pdev);
285 /* Buffers setup */
286 static int      ath5k_rxbuf_setup(struct ath5k_softc *sc,
287                                 struct ath5k_buf *bf);
288 static int      ath5k_txbuf_setup(struct ath5k_softc *sc,
289                                 struct ath5k_buf *bf);
290 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
291                                 struct ath5k_buf *bf)
292 {
293         BUG_ON(!bf);
294         if (!bf->skb)
295                 return;
296         pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
297                         PCI_DMA_TODEVICE);
298         dev_kfree_skb_any(bf->skb);
299         bf->skb = NULL;
300 }
301
302 /* Queues setup */
303 static struct   ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
304                                 int qtype, int subtype);
305 static int      ath5k_beaconq_setup(struct ath5k_hw *ah);
306 static int      ath5k_beaconq_config(struct ath5k_softc *sc);
307 static void     ath5k_txq_drainq(struct ath5k_softc *sc,
308                                 struct ath5k_txq *txq);
309 static void     ath5k_txq_cleanup(struct ath5k_softc *sc);
310 static void     ath5k_txq_release(struct ath5k_softc *sc);
311 /* Rx handling */
312 static int      ath5k_rx_start(struct ath5k_softc *sc);
313 static void     ath5k_rx_stop(struct ath5k_softc *sc);
314 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
315                                         struct ath5k_desc *ds,
316                                         struct sk_buff *skb,
317                                         struct ath5k_rx_status *rs);
318 static void     ath5k_tasklet_rx(unsigned long data);
319 /* Tx handling */
320 static void     ath5k_tx_processq(struct ath5k_softc *sc,
321                                 struct ath5k_txq *txq);
322 static void     ath5k_tasklet_tx(unsigned long data);
323 /* Beacon handling */
324 static int      ath5k_beacon_setup(struct ath5k_softc *sc,
325                                         struct ath5k_buf *bf);
326 static void     ath5k_beacon_send(struct ath5k_softc *sc);
327 static void     ath5k_beacon_config(struct ath5k_softc *sc);
328 static void     ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
329
330 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
331 {
332         u64 tsf = ath5k_hw_get_tsf64(ah);
333
334         if ((tsf & 0x7fff) < rstamp)
335                 tsf -= 0x8000;
336
337         return (tsf & ~0x7fff) | rstamp;
338 }
339
340 /* Interrupt handling */
341 static int      ath5k_init(struct ath5k_softc *sc, bool is_resume);
342 static int      ath5k_stop_locked(struct ath5k_softc *sc);
343 static int      ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend);
344 static irqreturn_t ath5k_intr(int irq, void *dev_id);
345 static void     ath5k_tasklet_reset(unsigned long data);
346
347 static void     ath5k_calibrate(unsigned long data);
348 /* LED functions */
349 static int      ath5k_init_leds(struct ath5k_softc *sc);
350 static void     ath5k_led_enable(struct ath5k_softc *sc);
351 static void     ath5k_led_off(struct ath5k_softc *sc);
352 static void     ath5k_unregister_leds(struct ath5k_softc *sc);
353
354 /*
355  * Module init/exit functions
356  */
357 static int __init
358 init_ath5k_pci(void)
359 {
360         int ret;
361
362         ath5k_debug_init();
363
364         ret = pci_register_driver(&ath5k_pci_driver);
365         if (ret) {
366                 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
367                 return ret;
368         }
369
370         return 0;
371 }
372
373 static void __exit
374 exit_ath5k_pci(void)
375 {
376         pci_unregister_driver(&ath5k_pci_driver);
377
378         ath5k_debug_finish();
379 }
380
381 module_init(init_ath5k_pci);
382 module_exit(exit_ath5k_pci);
383
384
385 /********************\
386 * PCI Initialization *
387 \********************/
388
389 static const char *
390 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
391 {
392         const char *name = "xxxxx";
393         unsigned int i;
394
395         for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
396                 if (srev_names[i].sr_type != type)
397                         continue;
398
399                 if ((val & 0xf0) == srev_names[i].sr_val)
400                         name = srev_names[i].sr_name;
401
402                 if ((val & 0xff) == srev_names[i].sr_val) {
403                         name = srev_names[i].sr_name;
404                         break;
405                 }
406         }
407
408         return name;
409 }
410
411 static int __devinit
412 ath5k_pci_probe(struct pci_dev *pdev,
413                 const struct pci_device_id *id)
414 {
415         void __iomem *mem;
416         struct ath5k_softc *sc;
417         struct ieee80211_hw *hw;
418         int ret;
419         u8 csz;
420
421         ret = pci_enable_device(pdev);
422         if (ret) {
423                 dev_err(&pdev->dev, "can't enable device\n");
424                 goto err;
425         }
426
427         /* XXX 32-bit addressing only */
428         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
429         if (ret) {
430                 dev_err(&pdev->dev, "32-bit DMA not available\n");
431                 goto err_dis;
432         }
433
434         /*
435          * Cache line size is used to size and align various
436          * structures used to communicate with the hardware.
437          */
438         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
439         if (csz == 0) {
440                 /*
441                  * Linux 2.4.18 (at least) writes the cache line size
442                  * register as a 16-bit wide register which is wrong.
443                  * We must have this setup properly for rx buffer
444                  * DMA to work so force a reasonable value here if it
445                  * comes up zero.
446                  */
447                 csz = L1_CACHE_BYTES / sizeof(u32);
448                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
449         }
450         /*
451          * The default setting of latency timer yields poor results,
452          * set it to the value used by other systems.  It may be worth
453          * tweaking this setting more.
454          */
455         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
456
457         /* Enable bus mastering */
458         pci_set_master(pdev);
459
460         /*
461          * Disable the RETRY_TIMEOUT register (0x41) to keep
462          * PCI Tx retries from interfering with C3 CPU state.
463          */
464         pci_write_config_byte(pdev, 0x41, 0);
465
466         ret = pci_request_region(pdev, 0, "ath5k");
467         if (ret) {
468                 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
469                 goto err_dis;
470         }
471
472         mem = pci_iomap(pdev, 0, 0);
473         if (!mem) {
474                 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
475                 ret = -EIO;
476                 goto err_reg;
477         }
478
479         /*
480          * Allocate hw (mac80211 main struct)
481          * and hw->priv (driver private data)
482          */
483         hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
484         if (hw == NULL) {
485                 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
486                 ret = -ENOMEM;
487                 goto err_map;
488         }
489
490         dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
491
492         /* Initialize driver private data */
493         SET_IEEE80211_DEV(hw, &pdev->dev);
494         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
495                     IEEE80211_HW_SIGNAL_DBM |
496                     IEEE80211_HW_NOISE_DBM;
497
498         hw->wiphy->interface_modes =
499                 BIT(NL80211_IFTYPE_STATION) |
500                 BIT(NL80211_IFTYPE_ADHOC) |
501                 BIT(NL80211_IFTYPE_MESH_POINT);
502
503         hw->extra_tx_headroom = 2;
504         hw->channel_change_time = 5000;
505         sc = hw->priv;
506         sc->hw = hw;
507         sc->pdev = pdev;
508
509         ath5k_debug_init_device(sc);
510
511         /*
512          * Mark the device as detached to avoid processing
513          * interrupts until setup is complete.
514          */
515         __set_bit(ATH_STAT_INVALID, sc->status);
516
517         sc->iobase = mem; /* So we can unmap it on detach */
518         sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
519         sc->opmode = NL80211_IFTYPE_STATION;
520         mutex_init(&sc->lock);
521         spin_lock_init(&sc->rxbuflock);
522         spin_lock_init(&sc->txbuflock);
523         spin_lock_init(&sc->block);
524
525         /* Set private data */
526         pci_set_drvdata(pdev, hw);
527
528         /* Setup interrupt handler */
529         ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
530         if (ret) {
531                 ATH5K_ERR(sc, "request_irq failed\n");
532                 goto err_free;
533         }
534
535         /* Initialize device */
536         sc->ah = ath5k_hw_attach(sc, id->driver_data);
537         if (IS_ERR(sc->ah)) {
538                 ret = PTR_ERR(sc->ah);
539                 goto err_irq;
540         }
541
542         /* set up multi-rate retry capabilities */
543         if (sc->ah->ah_version == AR5K_AR5212) {
544                 hw->max_altrates = 3;
545                 hw->max_altrate_tries = 11;
546         }
547
548         /* Finish private driver data initialization */
549         ret = ath5k_attach(pdev, hw);
550         if (ret)
551                 goto err_ah;
552
553         ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
554                         ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
555                                         sc->ah->ah_mac_srev,
556                                         sc->ah->ah_phy_revision);
557
558         if (!sc->ah->ah_single_chip) {
559                 /* Single chip radio (!RF5111) */
560                 if (sc->ah->ah_radio_5ghz_revision &&
561                         !sc->ah->ah_radio_2ghz_revision) {
562                         /* No 5GHz support -> report 2GHz radio */
563                         if (!test_bit(AR5K_MODE_11A,
564                                 sc->ah->ah_capabilities.cap_mode)) {
565                                 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
566                                         ath5k_chip_name(AR5K_VERSION_RAD,
567                                                 sc->ah->ah_radio_5ghz_revision),
568                                                 sc->ah->ah_radio_5ghz_revision);
569                         /* No 2GHz support (5110 and some
570                          * 5Ghz only cards) -> report 5Ghz radio */
571                         } else if (!test_bit(AR5K_MODE_11B,
572                                 sc->ah->ah_capabilities.cap_mode)) {
573                                 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
574                                         ath5k_chip_name(AR5K_VERSION_RAD,
575                                                 sc->ah->ah_radio_5ghz_revision),
576                                                 sc->ah->ah_radio_5ghz_revision);
577                         /* Multiband radio */
578                         } else {
579                                 ATH5K_INFO(sc, "RF%s multiband radio found"
580                                         " (0x%x)\n",
581                                         ath5k_chip_name(AR5K_VERSION_RAD,
582                                                 sc->ah->ah_radio_5ghz_revision),
583                                                 sc->ah->ah_radio_5ghz_revision);
584                         }
585                 }
586                 /* Multi chip radio (RF5111 - RF2111) ->
587                  * report both 2GHz/5GHz radios */
588                 else if (sc->ah->ah_radio_5ghz_revision &&
589                                 sc->ah->ah_radio_2ghz_revision){
590                         ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
591                                 ath5k_chip_name(AR5K_VERSION_RAD,
592                                         sc->ah->ah_radio_5ghz_revision),
593                                         sc->ah->ah_radio_5ghz_revision);
594                         ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
595                                 ath5k_chip_name(AR5K_VERSION_RAD,
596                                         sc->ah->ah_radio_2ghz_revision),
597                                         sc->ah->ah_radio_2ghz_revision);
598                 }
599         }
600
601
602         /* ready to process interrupts */
603         __clear_bit(ATH_STAT_INVALID, sc->status);
604
605         return 0;
606 err_ah:
607         ath5k_hw_detach(sc->ah);
608 err_irq:
609         free_irq(pdev->irq, sc);
610 err_free:
611         ieee80211_free_hw(hw);
612 err_map:
613         pci_iounmap(pdev, mem);
614 err_reg:
615         pci_release_region(pdev, 0);
616 err_dis:
617         pci_disable_device(pdev);
618 err:
619         return ret;
620 }
621
622 static void __devexit
623 ath5k_pci_remove(struct pci_dev *pdev)
624 {
625         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
626         struct ath5k_softc *sc = hw->priv;
627
628         ath5k_debug_finish_device(sc);
629         ath5k_detach(pdev, hw);
630         ath5k_hw_detach(sc->ah);
631         free_irq(pdev->irq, sc);
632         pci_iounmap(pdev, sc->iobase);
633         pci_release_region(pdev, 0);
634         pci_disable_device(pdev);
635         ieee80211_free_hw(hw);
636 }
637
638 #ifdef CONFIG_PM
639 static int
640 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
641 {
642         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
643         struct ath5k_softc *sc = hw->priv;
644
645         ath5k_led_off(sc);
646
647         ath5k_stop_hw(sc, true);
648
649         free_irq(pdev->irq, sc);
650         pci_save_state(pdev);
651         pci_disable_device(pdev);
652         pci_set_power_state(pdev, PCI_D3hot);
653
654         return 0;
655 }
656
657 static int
658 ath5k_pci_resume(struct pci_dev *pdev)
659 {
660         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
661         struct ath5k_softc *sc = hw->priv;
662         int err;
663
664         pci_restore_state(pdev);
665
666         err = pci_enable_device(pdev);
667         if (err)
668                 return err;
669
670         /*
671          * Suspend/Resume resets the PCI configuration space, so we have to
672          * re-disable the RETRY_TIMEOUT register (0x41) to keep
673          * PCI Tx retries from interfering with C3 CPU state
674          */
675         pci_write_config_byte(pdev, 0x41, 0);
676
677         err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
678         if (err) {
679                 ATH5K_ERR(sc, "request_irq failed\n");
680                 goto err_no_irq;
681         }
682
683         err = ath5k_init(sc, true);
684         if (err)
685                 goto err_irq;
686         ath5k_led_enable(sc);
687
688         return 0;
689 err_irq:
690         free_irq(pdev->irq, sc);
691 err_no_irq:
692         pci_disable_device(pdev);
693         return err;
694 }
695 #endif /* CONFIG_PM */
696
697
698 /***********************\
699 * Driver Initialization *
700 \***********************/
701
702 static int
703 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
704 {
705         struct ath5k_softc *sc = hw->priv;
706         struct ath5k_hw *ah = sc->ah;
707         u8 mac[ETH_ALEN];
708         int ret;
709
710         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
711
712         /*
713          * Check if the MAC has multi-rate retry support.
714          * We do this by trying to setup a fake extended
715          * descriptor.  MAC's that don't have support will
716          * return false w/o doing anything.  MAC's that do
717          * support it will return true w/o doing anything.
718          */
719         ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
720         if (ret < 0)
721                 goto err;
722         if (ret > 0)
723                 __set_bit(ATH_STAT_MRRETRY, sc->status);
724
725         /*
726          * Collect the channel list.  The 802.11 layer
727          * is resposible for filtering this list based
728          * on settings like the phy mode and regulatory
729          * domain restrictions.
730          */
731         ret = ath5k_setup_bands(hw);
732         if (ret) {
733                 ATH5K_ERR(sc, "can't get channels\n");
734                 goto err;
735         }
736
737         /* NB: setup here so ath5k_rate_update is happy */
738         if (test_bit(AR5K_MODE_11A, ah->ah_modes))
739                 ath5k_setcurmode(sc, AR5K_MODE_11A);
740         else
741                 ath5k_setcurmode(sc, AR5K_MODE_11B);
742
743         /*
744          * Allocate tx+rx descriptors and populate the lists.
745          */
746         ret = ath5k_desc_alloc(sc, pdev);
747         if (ret) {
748                 ATH5K_ERR(sc, "can't allocate descriptors\n");
749                 goto err;
750         }
751
752         /*
753          * Allocate hardware transmit queues: one queue for
754          * beacon frames and one data queue for each QoS
755          * priority.  Note that hw functions handle reseting
756          * these queues at the needed time.
757          */
758         ret = ath5k_beaconq_setup(ah);
759         if (ret < 0) {
760                 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
761                 goto err_desc;
762         }
763         sc->bhalq = ret;
764
765         sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
766         if (IS_ERR(sc->txq)) {
767                 ATH5K_ERR(sc, "can't setup xmit queue\n");
768                 ret = PTR_ERR(sc->txq);
769                 goto err_bhal;
770         }
771
772         tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
773         tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
774         tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
775         setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
776
777         ath5k_hw_get_lladdr(ah, mac);
778         SET_IEEE80211_PERM_ADDR(hw, mac);
779         /* All MAC address bits matter for ACKs */
780         memset(sc->bssidmask, 0xff, ETH_ALEN);
781         ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
782
783         ret = ieee80211_register_hw(hw);
784         if (ret) {
785                 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
786                 goto err_queues;
787         }
788
789         ath5k_init_leds(sc);
790
791         return 0;
792 err_queues:
793         ath5k_txq_release(sc);
794 err_bhal:
795         ath5k_hw_release_tx_queue(ah, sc->bhalq);
796 err_desc:
797         ath5k_desc_free(sc, pdev);
798 err:
799         return ret;
800 }
801
802 static void
803 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
804 {
805         struct ath5k_softc *sc = hw->priv;
806
807         /*
808          * NB: the order of these is important:
809          * o call the 802.11 layer before detaching ath5k_hw to
810          *   insure callbacks into the driver to delete global
811          *   key cache entries can be handled
812          * o reclaim the tx queue data structures after calling
813          *   the 802.11 layer as we'll get called back to reclaim
814          *   node state and potentially want to use them
815          * o to cleanup the tx queues the hal is called, so detach
816          *   it last
817          * XXX: ??? detach ath5k_hw ???
818          * Other than that, it's straightforward...
819          */
820         ieee80211_unregister_hw(hw);
821         ath5k_desc_free(sc, pdev);
822         ath5k_txq_release(sc);
823         ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
824         ath5k_unregister_leds(sc);
825
826         /*
827          * NB: can't reclaim these until after ieee80211_ifdetach
828          * returns because we'll get called back to reclaim node
829          * state and potentially want to use them.
830          */
831 }
832
833
834
835
836 /********************\
837 * Channel/mode setup *
838 \********************/
839
840 /*
841  * Convert IEEE channel number to MHz frequency.
842  */
843 static inline short
844 ath5k_ieee2mhz(short chan)
845 {
846         if (chan <= 14 || chan >= 27)
847                 return ieee80211chan2mhz(chan);
848         else
849                 return 2212 + chan * 20;
850 }
851
852 static unsigned int
853 ath5k_copy_channels(struct ath5k_hw *ah,
854                 struct ieee80211_channel *channels,
855                 unsigned int mode,
856                 unsigned int max)
857 {
858         unsigned int i, count, size, chfreq, freq, ch;
859
860         if (!test_bit(mode, ah->ah_modes))
861                 return 0;
862
863         switch (mode) {
864         case AR5K_MODE_11A:
865         case AR5K_MODE_11A_TURBO:
866                 /* 1..220, but 2GHz frequencies are filtered by check_channel */
867                 size = 220 ;
868                 chfreq = CHANNEL_5GHZ;
869                 break;
870         case AR5K_MODE_11B:
871         case AR5K_MODE_11G:
872         case AR5K_MODE_11G_TURBO:
873                 size = 26;
874                 chfreq = CHANNEL_2GHZ;
875                 break;
876         default:
877                 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
878                 return 0;
879         }
880
881         for (i = 0, count = 0; i < size && max > 0; i++) {
882                 ch = i + 1 ;
883                 freq = ath5k_ieee2mhz(ch);
884
885                 /* Check if channel is supported by the chipset */
886                 if (!ath5k_channel_ok(ah, freq, chfreq))
887                         continue;
888
889                 /* Write channel info and increment counter */
890                 channels[count].center_freq = freq;
891                 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
892                         IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
893                 switch (mode) {
894                 case AR5K_MODE_11A:
895                 case AR5K_MODE_11G:
896                         channels[count].hw_value = chfreq | CHANNEL_OFDM;
897                         break;
898                 case AR5K_MODE_11A_TURBO:
899                 case AR5K_MODE_11G_TURBO:
900                         channels[count].hw_value = chfreq |
901                                 CHANNEL_OFDM | CHANNEL_TURBO;
902                         break;
903                 case AR5K_MODE_11B:
904                         channels[count].hw_value = CHANNEL_B;
905                 }
906
907                 count++;
908                 max--;
909         }
910
911         return count;
912 }
913
914 static void
915 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
916 {
917         u8 i;
918
919         for (i = 0; i < AR5K_MAX_RATES; i++)
920                 sc->rate_idx[b->band][i] = -1;
921
922         for (i = 0; i < b->n_bitrates; i++) {
923                 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
924                 if (b->bitrates[i].hw_value_short)
925                         sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
926         }
927 }
928
929 static int
930 ath5k_setup_bands(struct ieee80211_hw *hw)
931 {
932         struct ath5k_softc *sc = hw->priv;
933         struct ath5k_hw *ah = sc->ah;
934         struct ieee80211_supported_band *sband;
935         int max_c, count_c = 0;
936         int i;
937
938         BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
939         max_c = ARRAY_SIZE(sc->channels);
940
941         /* 2GHz band */
942         sband = &sc->sbands[IEEE80211_BAND_2GHZ];
943         sband->band = IEEE80211_BAND_2GHZ;
944         sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
945
946         if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
947                 /* G mode */
948                 memcpy(sband->bitrates, &ath5k_rates[0],
949                        sizeof(struct ieee80211_rate) * 12);
950                 sband->n_bitrates = 12;
951
952                 sband->channels = sc->channels;
953                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
954                                         AR5K_MODE_11G, max_c);
955
956                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
957                 count_c = sband->n_channels;
958                 max_c -= count_c;
959         } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
960                 /* B mode */
961                 memcpy(sband->bitrates, &ath5k_rates[0],
962                        sizeof(struct ieee80211_rate) * 4);
963                 sband->n_bitrates = 4;
964
965                 /* 5211 only supports B rates and uses 4bit rate codes
966                  * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
967                  * fix them up here:
968                  */
969                 if (ah->ah_version == AR5K_AR5211) {
970                         for (i = 0; i < 4; i++) {
971                                 sband->bitrates[i].hw_value =
972                                         sband->bitrates[i].hw_value & 0xF;
973                                 sband->bitrates[i].hw_value_short =
974                                         sband->bitrates[i].hw_value_short & 0xF;
975                         }
976                 }
977
978                 sband->channels = sc->channels;
979                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
980                                         AR5K_MODE_11B, max_c);
981
982                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
983                 count_c = sband->n_channels;
984                 max_c -= count_c;
985         }
986         ath5k_setup_rate_idx(sc, sband);
987
988         /* 5GHz band, A mode */
989         if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
990                 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
991                 sband->band = IEEE80211_BAND_5GHZ;
992                 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
993
994                 memcpy(sband->bitrates, &ath5k_rates[4],
995                        sizeof(struct ieee80211_rate) * 8);
996                 sband->n_bitrates = 8;
997
998                 sband->channels = &sc->channels[count_c];
999                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1000                                         AR5K_MODE_11A, max_c);
1001
1002                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1003         }
1004         ath5k_setup_rate_idx(sc, sband);
1005
1006         ath5k_debug_dump_bands(sc);
1007
1008         return 0;
1009 }
1010
1011 /*
1012  * Set/change channels.  If the channel is really being changed,
1013  * it's done by reseting the chip.  To accomplish this we must
1014  * first cleanup any pending DMA, then restart stuff after a la
1015  * ath5k_init.
1016  */
1017 static int
1018 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1019 {
1020         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1021                 sc->curchan->center_freq, chan->center_freq);
1022
1023         if (chan->center_freq != sc->curchan->center_freq ||
1024                 chan->hw_value != sc->curchan->hw_value) {
1025
1026                 sc->curchan = chan;
1027                 sc->curband = &sc->sbands[chan->band];
1028
1029                 /*
1030                  * To switch channels clear any pending DMA operations;
1031                  * wait long enough for the RX fifo to drain, reset the
1032                  * hardware at the new frequency, and then re-enable
1033                  * the relevant bits of the h/w.
1034                  */
1035                 return ath5k_reset(sc, true, true);
1036         }
1037
1038         return 0;
1039 }
1040
1041 static void
1042 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1043 {
1044         sc->curmode = mode;
1045
1046         if (mode == AR5K_MODE_11A) {
1047                 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1048         } else {
1049                 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1050         }
1051 }
1052
1053 static void
1054 ath5k_mode_setup(struct ath5k_softc *sc)
1055 {
1056         struct ath5k_hw *ah = sc->ah;
1057         u32 rfilt;
1058
1059         /* configure rx filter */
1060         rfilt = sc->filter_flags;
1061         ath5k_hw_set_rx_filter(ah, rfilt);
1062
1063         if (ath5k_hw_hasbssidmask(ah))
1064                 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1065
1066         /* configure operational mode */
1067         ath5k_hw_set_opmode(ah);
1068
1069         ath5k_hw_set_mcast_filter(ah, 0, 0);
1070         ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1071 }
1072
1073 static inline int
1074 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1075 {
1076         WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1077         return sc->rate_idx[sc->curband->band][hw_rix];
1078 }
1079
1080 /***************\
1081 * Buffers setup *
1082 \***************/
1083
1084 static int
1085 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1086 {
1087         struct ath5k_hw *ah = sc->ah;
1088         struct sk_buff *skb = bf->skb;
1089         struct ath5k_desc *ds;
1090
1091         if (likely(skb == NULL)) {
1092                 unsigned int off;
1093
1094                 /*
1095                  * Allocate buffer with headroom_needed space for the
1096                  * fake physical layer header at the start.
1097                  */
1098                 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1099                 if (unlikely(skb == NULL)) {
1100                         ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1101                                         sc->rxbufsize + sc->cachelsz - 1);
1102                         return -ENOMEM;
1103                 }
1104                 /*
1105                  * Cache-line-align.  This is important (for the
1106                  * 5210 at least) as not doing so causes bogus data
1107                  * in rx'd frames.
1108                  */
1109                 off = ((unsigned long)skb->data) % sc->cachelsz;
1110                 if (off != 0)
1111                         skb_reserve(skb, sc->cachelsz - off);
1112
1113                 bf->skb = skb;
1114                 bf->skbaddr = pci_map_single(sc->pdev,
1115                         skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1116                 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1117                         ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1118                         dev_kfree_skb(skb);
1119                         bf->skb = NULL;
1120                         return -ENOMEM;
1121                 }
1122         }
1123
1124         /*
1125          * Setup descriptors.  For receive we always terminate
1126          * the descriptor list with a self-linked entry so we'll
1127          * not get overrun under high load (as can happen with a
1128          * 5212 when ANI processing enables PHY error frames).
1129          *
1130          * To insure the last descriptor is self-linked we create
1131          * each descriptor as self-linked and add it to the end.  As
1132          * each additional descriptor is added the previous self-linked
1133          * entry is ``fixed'' naturally.  This should be safe even
1134          * if DMA is happening.  When processing RX interrupts we
1135          * never remove/process the last, self-linked, entry on the
1136          * descriptor list.  This insures the hardware always has
1137          * someplace to write a new frame.
1138          */
1139         ds = bf->desc;
1140         ds->ds_link = bf->daddr;        /* link to self */
1141         ds->ds_data = bf->skbaddr;
1142         ah->ah_setup_rx_desc(ah, ds,
1143                 skb_tailroom(skb),      /* buffer size */
1144                 0);
1145
1146         if (sc->rxlink != NULL)
1147                 *sc->rxlink = bf->daddr;
1148         sc->rxlink = &ds->ds_link;
1149         return 0;
1150 }
1151
1152 static int
1153 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1154 {
1155         struct ath5k_hw *ah = sc->ah;
1156         struct ath5k_txq *txq = sc->txq;
1157         struct ath5k_desc *ds = bf->desc;
1158         struct sk_buff *skb = bf->skb;
1159         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1160         unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1161         struct ieee80211_rate *rate;
1162         unsigned int mrr_rate[3], mrr_tries[3];
1163         int i, ret;
1164
1165         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1166
1167         /* XXX endianness */
1168         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1169                         PCI_DMA_TODEVICE);
1170
1171         if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1172                 flags |= AR5K_TXDESC_NOACK;
1173
1174         pktlen = skb->len;
1175
1176         if (info->control.hw_key) {
1177                 keyidx = info->control.hw_key->hw_key_idx;
1178                 pktlen += info->control.hw_key->icv_len;
1179         }
1180         ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1181                 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1182                 (sc->power_level * 2),
1183                 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1184                 info->control.retry_limit, keyidx, 0, flags, 0, 0);
1185         if (ret)
1186                 goto err_unmap;
1187
1188         memset(mrr_rate, 0, sizeof(mrr_rate));
1189         memset(mrr_tries, 0, sizeof(mrr_tries));
1190         for (i = 0; i < 3; i++) {
1191                 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1192                 if (!rate)
1193                         break;
1194
1195                 mrr_rate[i] = rate->hw_value;
1196                 mrr_tries[i] = info->control.retries[i].limit;
1197         }
1198
1199         ah->ah_setup_mrr_tx_desc(ah, ds,
1200                 mrr_rate[0], mrr_tries[0],
1201                 mrr_rate[1], mrr_tries[1],
1202                 mrr_rate[2], mrr_tries[2]);
1203
1204         ds->ds_link = 0;
1205         ds->ds_data = bf->skbaddr;
1206
1207         spin_lock_bh(&txq->lock);
1208         list_add_tail(&bf->list, &txq->q);
1209         sc->tx_stats[txq->qnum].len++;
1210         if (txq->link == NULL) /* is this first packet? */
1211                 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1212         else /* no, so only link it */
1213                 *txq->link = bf->daddr;
1214
1215         txq->link = &ds->ds_link;
1216         ath5k_hw_start_tx_dma(ah, txq->qnum);
1217         mmiowb();
1218         spin_unlock_bh(&txq->lock);
1219
1220         return 0;
1221 err_unmap:
1222         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1223         return ret;
1224 }
1225
1226 /*******************\
1227 * Descriptors setup *
1228 \*******************/
1229
1230 static int
1231 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1232 {
1233         struct ath5k_desc *ds;
1234         struct ath5k_buf *bf;
1235         dma_addr_t da;
1236         unsigned int i;
1237         int ret;
1238
1239         /* allocate descriptors */
1240         sc->desc_len = sizeof(struct ath5k_desc) *
1241                         (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1242         sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1243         if (sc->desc == NULL) {
1244                 ATH5K_ERR(sc, "can't allocate descriptors\n");
1245                 ret = -ENOMEM;
1246                 goto err;
1247         }
1248         ds = sc->desc;
1249         da = sc->desc_daddr;
1250         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1251                 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1252
1253         bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1254                         sizeof(struct ath5k_buf), GFP_KERNEL);
1255         if (bf == NULL) {
1256                 ATH5K_ERR(sc, "can't allocate bufptr\n");
1257                 ret = -ENOMEM;
1258                 goto err_free;
1259         }
1260         sc->bufptr = bf;
1261
1262         INIT_LIST_HEAD(&sc->rxbuf);
1263         for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1264                 bf->desc = ds;
1265                 bf->daddr = da;
1266                 list_add_tail(&bf->list, &sc->rxbuf);
1267         }
1268
1269         INIT_LIST_HEAD(&sc->txbuf);
1270         sc->txbuf_len = ATH_TXBUF;
1271         for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1272                         da += sizeof(*ds)) {
1273                 bf->desc = ds;
1274                 bf->daddr = da;
1275                 list_add_tail(&bf->list, &sc->txbuf);
1276         }
1277
1278         /* beacon buffer */
1279         bf->desc = ds;
1280         bf->daddr = da;
1281         sc->bbuf = bf;
1282
1283         return 0;
1284 err_free:
1285         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1286 err:
1287         sc->desc = NULL;
1288         return ret;
1289 }
1290
1291 static void
1292 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1293 {
1294         struct ath5k_buf *bf;
1295
1296         ath5k_txbuf_free(sc, sc->bbuf);
1297         list_for_each_entry(bf, &sc->txbuf, list)
1298                 ath5k_txbuf_free(sc, bf);
1299         list_for_each_entry(bf, &sc->rxbuf, list)
1300                 ath5k_txbuf_free(sc, bf);
1301
1302         /* Free memory associated with all descriptors */
1303         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1304
1305         kfree(sc->bufptr);
1306         sc->bufptr = NULL;
1307 }
1308
1309
1310
1311
1312
1313 /**************\
1314 * Queues setup *
1315 \**************/
1316
1317 static struct ath5k_txq *
1318 ath5k_txq_setup(struct ath5k_softc *sc,
1319                 int qtype, int subtype)
1320 {
1321         struct ath5k_hw *ah = sc->ah;
1322         struct ath5k_txq *txq;
1323         struct ath5k_txq_info qi = {
1324                 .tqi_subtype = subtype,
1325                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1326                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1327                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1328         };
1329         int qnum;
1330
1331         /*
1332          * Enable interrupts only for EOL and DESC conditions.
1333          * We mark tx descriptors to receive a DESC interrupt
1334          * when a tx queue gets deep; otherwise waiting for the
1335          * EOL to reap descriptors.  Note that this is done to
1336          * reduce interrupt load and this only defers reaping
1337          * descriptors, never transmitting frames.  Aside from
1338          * reducing interrupts this also permits more concurrency.
1339          * The only potential downside is if the tx queue backs
1340          * up in which case the top half of the kernel may backup
1341          * due to a lack of tx descriptors.
1342          */
1343         qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1344                                 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1345         qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1346         if (qnum < 0) {
1347                 /*
1348                  * NB: don't print a message, this happens
1349                  * normally on parts with too few tx queues
1350                  */
1351                 return ERR_PTR(qnum);
1352         }
1353         if (qnum >= ARRAY_SIZE(sc->txqs)) {
1354                 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1355                         qnum, ARRAY_SIZE(sc->txqs));
1356                 ath5k_hw_release_tx_queue(ah, qnum);
1357                 return ERR_PTR(-EINVAL);
1358         }
1359         txq = &sc->txqs[qnum];
1360         if (!txq->setup) {
1361                 txq->qnum = qnum;
1362                 txq->link = NULL;
1363                 INIT_LIST_HEAD(&txq->q);
1364                 spin_lock_init(&txq->lock);
1365                 txq->setup = true;
1366         }
1367         return &sc->txqs[qnum];
1368 }
1369
1370 static int
1371 ath5k_beaconq_setup(struct ath5k_hw *ah)
1372 {
1373         struct ath5k_txq_info qi = {
1374                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1375                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1376                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1377                 /* NB: for dynamic turbo, don't enable any other interrupts */
1378                 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1379         };
1380
1381         return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1382 }
1383
1384 static int
1385 ath5k_beaconq_config(struct ath5k_softc *sc)
1386 {
1387         struct ath5k_hw *ah = sc->ah;
1388         struct ath5k_txq_info qi;
1389         int ret;
1390
1391         ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1392         if (ret)
1393                 return ret;
1394         if (sc->opmode == NL80211_IFTYPE_AP ||
1395                 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1396                 /*
1397                  * Always burst out beacon and CAB traffic
1398                  * (aifs = cwmin = cwmax = 0)
1399                  */
1400                 qi.tqi_aifs = 0;
1401                 qi.tqi_cw_min = 0;
1402                 qi.tqi_cw_max = 0;
1403         } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1404                 /*
1405                  * Adhoc mode; backoff between 0 and (2 * cw_min).
1406                  */
1407                 qi.tqi_aifs = 0;
1408                 qi.tqi_cw_min = 0;
1409                 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1410         }
1411
1412         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1413                 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1414                 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1415
1416         ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1417         if (ret) {
1418                 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1419                         "hardware queue!\n", __func__);
1420                 return ret;
1421         }
1422
1423         return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1424 }
1425
1426 static void
1427 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1428 {
1429         struct ath5k_buf *bf, *bf0;
1430
1431         /*
1432          * NB: this assumes output has been stopped and
1433          *     we do not need to block ath5k_tx_tasklet
1434          */
1435         spin_lock_bh(&txq->lock);
1436         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1437                 ath5k_debug_printtxbuf(sc, bf);
1438
1439                 ath5k_txbuf_free(sc, bf);
1440
1441                 spin_lock_bh(&sc->txbuflock);
1442                 sc->tx_stats[txq->qnum].len--;
1443                 list_move_tail(&bf->list, &sc->txbuf);
1444                 sc->txbuf_len++;
1445                 spin_unlock_bh(&sc->txbuflock);
1446         }
1447         txq->link = NULL;
1448         spin_unlock_bh(&txq->lock);
1449 }
1450
1451 /*
1452  * Drain the transmit queues and reclaim resources.
1453  */
1454 static void
1455 ath5k_txq_cleanup(struct ath5k_softc *sc)
1456 {
1457         struct ath5k_hw *ah = sc->ah;
1458         unsigned int i;
1459
1460         /* XXX return value */
1461         if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1462                 /* don't touch the hardware if marked invalid */
1463                 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1464                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1465                         ath5k_hw_get_txdp(ah, sc->bhalq));
1466                 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1467                         if (sc->txqs[i].setup) {
1468                                 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1469                                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1470                                         "link %p\n",
1471                                         sc->txqs[i].qnum,
1472                                         ath5k_hw_get_txdp(ah,
1473                                                         sc->txqs[i].qnum),
1474                                         sc->txqs[i].link);
1475                         }
1476         }
1477         ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1478
1479         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1480                 if (sc->txqs[i].setup)
1481                         ath5k_txq_drainq(sc, &sc->txqs[i]);
1482 }
1483
1484 static void
1485 ath5k_txq_release(struct ath5k_softc *sc)
1486 {
1487         struct ath5k_txq *txq = sc->txqs;
1488         unsigned int i;
1489
1490         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1491                 if (txq->setup) {
1492                         ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1493                         txq->setup = false;
1494                 }
1495 }
1496
1497
1498
1499
1500 /*************\
1501 * RX Handling *
1502 \*************/
1503
1504 /*
1505  * Enable the receive h/w following a reset.
1506  */
1507 static int
1508 ath5k_rx_start(struct ath5k_softc *sc)
1509 {
1510         struct ath5k_hw *ah = sc->ah;
1511         struct ath5k_buf *bf;
1512         int ret;
1513
1514         sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1515
1516         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1517                 sc->cachelsz, sc->rxbufsize);
1518
1519         sc->rxlink = NULL;
1520
1521         spin_lock_bh(&sc->rxbuflock);
1522         list_for_each_entry(bf, &sc->rxbuf, list) {
1523                 ret = ath5k_rxbuf_setup(sc, bf);
1524                 if (ret != 0) {
1525                         spin_unlock_bh(&sc->rxbuflock);
1526                         goto err;
1527                 }
1528         }
1529         bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1530         spin_unlock_bh(&sc->rxbuflock);
1531
1532         ath5k_hw_set_rxdp(ah, bf->daddr);
1533         ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
1534         ath5k_mode_setup(sc);           /* set filters, etc. */
1535         ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
1536
1537         return 0;
1538 err:
1539         return ret;
1540 }
1541
1542 /*
1543  * Disable the receive h/w in preparation for a reset.
1544  */
1545 static void
1546 ath5k_rx_stop(struct ath5k_softc *sc)
1547 {
1548         struct ath5k_hw *ah = sc->ah;
1549
1550         ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
1551         ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
1552         ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
1553
1554         ath5k_debug_printrxbuffs(sc, ah);
1555
1556         sc->rxlink = NULL;              /* just in case */
1557 }
1558
1559 static unsigned int
1560 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1561                 struct sk_buff *skb, struct ath5k_rx_status *rs)
1562 {
1563         struct ieee80211_hdr *hdr = (void *)skb->data;
1564         unsigned int keyix, hlen;
1565
1566         if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1567                         rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1568                 return RX_FLAG_DECRYPTED;
1569
1570         /* Apparently when a default key is used to decrypt the packet
1571            the hw does not set the index used to decrypt.  In such cases
1572            get the index from the packet. */
1573         hlen = ieee80211_hdrlen(hdr->frame_control);
1574         if (ieee80211_has_protected(hdr->frame_control) &&
1575             !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1576             skb->len >= hlen + 4) {
1577                 keyix = skb->data[hlen + 3] >> 6;
1578
1579                 if (test_bit(keyix, sc->keymap))
1580                         return RX_FLAG_DECRYPTED;
1581         }
1582
1583         return 0;
1584 }
1585
1586
1587 static void
1588 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1589                      struct ieee80211_rx_status *rxs)
1590 {
1591         u64 tsf, bc_tstamp;
1592         u32 hw_tu;
1593         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1594
1595         if (ieee80211_is_beacon(mgmt->frame_control) &&
1596             le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1597             memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1598                 /*
1599                  * Received an IBSS beacon with the same BSSID. Hardware *must*
1600                  * have updated the local TSF. We have to work around various
1601                  * hardware bugs, though...
1602                  */
1603                 tsf = ath5k_hw_get_tsf64(sc->ah);
1604                 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1605                 hw_tu = TSF_TO_TU(tsf);
1606
1607                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1608                         "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1609                         (unsigned long long)bc_tstamp,
1610                         (unsigned long long)rxs->mactime,
1611                         (unsigned long long)(rxs->mactime - bc_tstamp),
1612                         (unsigned long long)tsf);
1613
1614                 /*
1615                  * Sometimes the HW will give us a wrong tstamp in the rx
1616                  * status, causing the timestamp extension to go wrong.
1617                  * (This seems to happen especially with beacon frames bigger
1618                  * than 78 byte (incl. FCS))
1619                  * But we know that the receive timestamp must be later than the
1620                  * timestamp of the beacon since HW must have synced to that.
1621                  *
1622                  * NOTE: here we assume mactime to be after the frame was
1623                  * received, not like mac80211 which defines it at the start.
1624                  */
1625                 if (bc_tstamp > rxs->mactime) {
1626                         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1627                                 "fixing mactime from %llx to %llx\n",
1628                                 (unsigned long long)rxs->mactime,
1629                                 (unsigned long long)tsf);
1630                         rxs->mactime = tsf;
1631                 }
1632
1633                 /*
1634                  * Local TSF might have moved higher than our beacon timers,
1635                  * in that case we have to update them to continue sending
1636                  * beacons. This also takes care of synchronizing beacon sending
1637                  * times with other stations.
1638                  */
1639                 if (hw_tu >= sc->nexttbtt)
1640                         ath5k_beacon_update_timers(sc, bc_tstamp);
1641         }
1642 }
1643
1644
1645 static void
1646 ath5k_tasklet_rx(unsigned long data)
1647 {
1648         struct ieee80211_rx_status rxs = {};
1649         struct ath5k_rx_status rs = {};
1650         struct sk_buff *skb;
1651         struct ath5k_softc *sc = (void *)data;
1652         struct ath5k_buf *bf, *bf_last;
1653         struct ath5k_desc *ds;
1654         int ret;
1655         int hdrlen;
1656         int pad;
1657
1658         spin_lock(&sc->rxbuflock);
1659         if (list_empty(&sc->rxbuf)) {
1660                 ATH5K_WARN(sc, "empty rx buf pool\n");
1661                 goto unlock;
1662         }
1663         bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1664         do {
1665                 rxs.flag = 0;
1666
1667                 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1668                 BUG_ON(bf->skb == NULL);
1669                 skb = bf->skb;
1670                 ds = bf->desc;
1671
1672                 /*
1673                  * last buffer must not be freed to ensure proper hardware
1674                  * function. When the hardware finishes also a packet next to
1675                  * it, we are sure, it doesn't use it anymore and we can go on.
1676                  */
1677                 if (bf_last == bf)
1678                         bf->flags |= 1;
1679                 if (bf->flags) {
1680                         struct ath5k_buf *bf_next = list_entry(bf->list.next,
1681                                         struct ath5k_buf, list);
1682                         ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1683                                         &rs);
1684                         if (ret)
1685                                 break;
1686                         bf->flags &= ~1;
1687                         /* skip the overwritten one (even status is martian) */
1688                         goto next;
1689                 }
1690
1691                 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1692                 if (unlikely(ret == -EINPROGRESS))
1693                         break;
1694                 else if (unlikely(ret)) {
1695                         ATH5K_ERR(sc, "error in processing rx descriptor\n");
1696                         spin_unlock(&sc->rxbuflock);
1697                         return;
1698                 }
1699
1700                 if (unlikely(rs.rs_more)) {
1701                         ATH5K_WARN(sc, "unsupported jumbo\n");
1702                         goto next;
1703                 }
1704
1705                 if (unlikely(rs.rs_status)) {
1706                         if (rs.rs_status & AR5K_RXERR_PHY)
1707                                 goto next;
1708                         if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1709                                 /*
1710                                  * Decrypt error.  If the error occurred
1711                                  * because there was no hardware key, then
1712                                  * let the frame through so the upper layers
1713                                  * can process it.  This is necessary for 5210
1714                                  * parts which have no way to setup a ``clear''
1715                                  * key cache entry.
1716                                  *
1717                                  * XXX do key cache faulting
1718                                  */
1719                                 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1720                                     !(rs.rs_status & AR5K_RXERR_CRC))
1721                                         goto accept;
1722                         }
1723                         if (rs.rs_status & AR5K_RXERR_MIC) {
1724                                 rxs.flag |= RX_FLAG_MMIC_ERROR;
1725                                 goto accept;
1726                         }
1727
1728                         /* let crypto-error packets fall through in MNTR */
1729                         if ((rs.rs_status &
1730                                 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1731                                         sc->opmode != NL80211_IFTYPE_MONITOR)
1732                                 goto next;
1733                 }
1734 accept:
1735                 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1736                                 PCI_DMA_FROMDEVICE);
1737                 bf->skb = NULL;
1738
1739                 skb_put(skb, rs.rs_datalen);
1740
1741                 /*
1742                  * the hardware adds a padding to 4 byte boundaries between
1743                  * the header and the payload data if the header length is
1744                  * not multiples of 4 - remove it
1745                  */
1746                 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1747                 if (hdrlen & 3) {
1748                         pad = hdrlen % 4;
1749                         memmove(skb->data + pad, skb->data, hdrlen);
1750                         skb_pull(skb, pad);
1751                 }
1752
1753                 /*
1754                  * always extend the mac timestamp, since this information is
1755                  * also needed for proper IBSS merging.
1756                  *
1757                  * XXX: it might be too late to do it here, since rs_tstamp is
1758                  * 15bit only. that means TSF extension has to be done within
1759                  * 32768usec (about 32ms). it might be necessary to move this to
1760                  * the interrupt handler, like it is done in madwifi.
1761                  *
1762                  * Unfortunately we don't know when the hardware takes the rx
1763                  * timestamp (beginning of phy frame, data frame, end of rx?).
1764                  * The only thing we know is that it is hardware specific...
1765                  * On AR5213 it seems the rx timestamp is at the end of the
1766                  * frame, but i'm not sure.
1767                  *
1768                  * NOTE: mac80211 defines mactime at the beginning of the first
1769                  * data symbol. Since we don't have any time references it's
1770                  * impossible to comply to that. This affects IBSS merge only
1771                  * right now, so it's not too bad...
1772                  */
1773                 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1774                 rxs.flag |= RX_FLAG_TSFT;
1775
1776                 rxs.freq = sc->curchan->center_freq;
1777                 rxs.band = sc->curband->band;
1778
1779                 rxs.noise = sc->ah->ah_noise_floor;
1780                 rxs.signal = rxs.noise + rs.rs_rssi;
1781
1782                 /* An rssi of 35 indicates you should be able use
1783                  * 54 Mbps reliably. A more elaborate scheme can be used
1784                  * here but it requires a map of SNR/throughput for each
1785                  * possible mode used */
1786                 rxs.qual = rs.rs_rssi * 100 / 35;
1787
1788                 /* rssi can be more than 35 though, anything above that
1789                  * should be considered at 100% */
1790                 if (rxs.qual > 100)
1791                         rxs.qual = 100;
1792
1793                 rxs.antenna = rs.rs_antenna;
1794                 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1795                 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1796
1797                 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1798                     sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1799                         rxs.flag |= RX_FLAG_SHORTPRE;
1800
1801                 ath5k_debug_dump_skb(sc, skb, "RX  ", 0);
1802
1803                 /* check beacons in IBSS mode */
1804                 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1805                         ath5k_check_ibss_tsf(sc, skb, &rxs);
1806
1807                 __ieee80211_rx(sc->hw, skb, &rxs);
1808 next:
1809                 list_move_tail(&bf->list, &sc->rxbuf);
1810         } while (ath5k_rxbuf_setup(sc, bf) == 0);
1811 unlock:
1812         spin_unlock(&sc->rxbuflock);
1813 }
1814
1815
1816
1817
1818 /*************\
1819 * TX Handling *
1820 \*************/
1821
1822 static void
1823 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1824 {
1825         struct ath5k_tx_status ts = {};
1826         struct ath5k_buf *bf, *bf0;
1827         struct ath5k_desc *ds;
1828         struct sk_buff *skb;
1829         struct ieee80211_tx_info *info;
1830         int i, ret;
1831
1832         spin_lock(&txq->lock);
1833         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1834                 ds = bf->desc;
1835
1836                 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1837                 if (unlikely(ret == -EINPROGRESS))
1838                         break;
1839                 else if (unlikely(ret)) {
1840                         ATH5K_ERR(sc, "error %d while processing queue %u\n",
1841                                 ret, txq->qnum);
1842                         break;
1843                 }
1844
1845                 skb = bf->skb;
1846                 info = IEEE80211_SKB_CB(skb);
1847                 bf->skb = NULL;
1848
1849                 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1850                                 PCI_DMA_TODEVICE);
1851
1852                 memset(&info->status, 0, sizeof(info->status));
1853                 info->tx_rate_idx = ath5k_hw_to_driver_rix(sc,
1854                                 ts.ts_rate[ts.ts_final_idx]);
1855                 info->status.retry_count = ts.ts_longretry;
1856
1857                 for (i = 0; i < 4; i++) {
1858                         struct ieee80211_tx_altrate *r =
1859                                 &info->status.retries[i];
1860
1861                         if (ts.ts_rate[i]) {
1862                                 r->rate_idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1863                                 r->limit = ts.ts_retry[i];
1864                         } else {
1865                                 r->rate_idx = -1;
1866                                 r->limit = 0;
1867                         }
1868                 }
1869
1870                 info->status.excessive_retries = 0;
1871                 if (unlikely(ts.ts_status)) {
1872                         sc->ll_stats.dot11ACKFailureCount++;
1873                         if (ts.ts_status & AR5K_TXERR_XRETRY)
1874                                 info->status.excessive_retries = 1;
1875                         else if (ts.ts_status & AR5K_TXERR_FILT)
1876                                 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1877                 } else {
1878                         info->flags |= IEEE80211_TX_STAT_ACK;
1879                         info->status.ack_signal = ts.ts_rssi;
1880                 }
1881
1882                 ieee80211_tx_status(sc->hw, skb);
1883                 sc->tx_stats[txq->qnum].count++;
1884
1885                 spin_lock(&sc->txbuflock);
1886                 sc->tx_stats[txq->qnum].len--;
1887                 list_move_tail(&bf->list, &sc->txbuf);
1888                 sc->txbuf_len++;
1889                 spin_unlock(&sc->txbuflock);
1890         }
1891         if (likely(list_empty(&txq->q)))
1892                 txq->link = NULL;
1893         spin_unlock(&txq->lock);
1894         if (sc->txbuf_len > ATH_TXBUF / 5)
1895                 ieee80211_wake_queues(sc->hw);
1896 }
1897
1898 static void
1899 ath5k_tasklet_tx(unsigned long data)
1900 {
1901         struct ath5k_softc *sc = (void *)data;
1902
1903         ath5k_tx_processq(sc, sc->txq);
1904 }
1905
1906
1907 /*****************\
1908 * Beacon handling *
1909 \*****************/
1910
1911 /*
1912  * Setup the beacon frame for transmit.
1913  */
1914 static int
1915 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1916 {
1917         struct sk_buff *skb = bf->skb;
1918         struct  ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1919         struct ath5k_hw *ah = sc->ah;
1920         struct ath5k_desc *ds;
1921         int ret, antenna = 0;
1922         u32 flags;
1923
1924         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1925                         PCI_DMA_TODEVICE);
1926         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1927                         "skbaddr %llx\n", skb, skb->data, skb->len,
1928                         (unsigned long long)bf->skbaddr);
1929         if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1930                 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1931                 return -EIO;
1932         }
1933
1934         ds = bf->desc;
1935
1936         flags = AR5K_TXDESC_NOACK;
1937         if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1938                 ds->ds_link = bf->daddr;        /* self-linked */
1939                 flags |= AR5K_TXDESC_VEOL;
1940                 /*
1941                  * Let hardware handle antenna switching if txantenna is not set
1942                  */
1943         } else {
1944                 ds->ds_link = 0;
1945                 /*
1946                  * Switch antenna every 4 beacons if txantenna is not set
1947                  * XXX assumes two antennas
1948                  */
1949                 if (antenna == 0)
1950                         antenna = sc->bsent & 4 ? 2 : 1;
1951         }
1952
1953         ds->ds_data = bf->skbaddr;
1954         ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1955                         ieee80211_get_hdrlen_from_skb(skb),
1956                         AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1957                         ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1958                         1, AR5K_TXKEYIX_INVALID,
1959                         antenna, flags, 0, 0);
1960         if (ret)
1961                 goto err_unmap;
1962
1963         return 0;
1964 err_unmap:
1965         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1966         return ret;
1967 }
1968
1969 /*
1970  * Transmit a beacon frame at SWBA.  Dynamic updates to the
1971  * frame contents are done as needed and the slot time is
1972  * also adjusted based on current state.
1973  *
1974  * this is usually called from interrupt context (ath5k_intr())
1975  * but also from ath5k_beacon_config() in IBSS mode which in turn
1976  * can be called from a tasklet and user context
1977  */
1978 static void
1979 ath5k_beacon_send(struct ath5k_softc *sc)
1980 {
1981         struct ath5k_buf *bf = sc->bbuf;
1982         struct ath5k_hw *ah = sc->ah;
1983
1984         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1985
1986         if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1987                         sc->opmode == NL80211_IFTYPE_MONITOR)) {
1988                 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1989                 return;
1990         }
1991         /*
1992          * Check if the previous beacon has gone out.  If
1993          * not don't don't try to post another, skip this
1994          * period and wait for the next.  Missed beacons
1995          * indicate a problem and should not occur.  If we
1996          * miss too many consecutive beacons reset the device.
1997          */
1998         if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1999                 sc->bmisscount++;
2000                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2001                         "missed %u consecutive beacons\n", sc->bmisscount);
2002                 if (sc->bmisscount > 3) {               /* NB: 3 is a guess */
2003                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2004                                 "stuck beacon time (%u missed)\n",
2005                                 sc->bmisscount);
2006                         tasklet_schedule(&sc->restq);
2007                 }
2008                 return;
2009         }
2010         if (unlikely(sc->bmisscount != 0)) {
2011                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2012                         "resume beacon xmit after %u misses\n",
2013                         sc->bmisscount);
2014                 sc->bmisscount = 0;
2015         }
2016
2017         /*
2018          * Stop any current dma and put the new frame on the queue.
2019          * This should never fail since we check above that no frames
2020          * are still pending on the queue.
2021          */
2022         if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2023                 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2024                 /* NB: hw still stops DMA, so proceed */
2025         }
2026
2027         ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2028         ath5k_hw_start_tx_dma(ah, sc->bhalq);
2029         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2030                 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2031
2032         sc->bsent++;
2033 }
2034
2035
2036 /**
2037  * ath5k_beacon_update_timers - update beacon timers
2038  *
2039  * @sc: struct ath5k_softc pointer we are operating on
2040  * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2041  *          beacon timer update based on the current HW TSF.
2042  *
2043  * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2044  * of a received beacon or the current local hardware TSF and write it to the
2045  * beacon timer registers.
2046  *
2047  * This is called in a variety of situations, e.g. when a beacon is received,
2048  * when a TSF update has been detected, but also when an new IBSS is created or
2049  * when we otherwise know we have to update the timers, but we keep it in this
2050  * function to have it all together in one place.
2051  */
2052 static void
2053 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2054 {
2055         struct ath5k_hw *ah = sc->ah;
2056         u32 nexttbtt, intval, hw_tu, bc_tu;
2057         u64 hw_tsf;
2058
2059         intval = sc->bintval & AR5K_BEACON_PERIOD;
2060         if (WARN_ON(!intval))
2061                 return;
2062
2063         /* beacon TSF converted to TU */
2064         bc_tu = TSF_TO_TU(bc_tsf);
2065
2066         /* current TSF converted to TU */
2067         hw_tsf = ath5k_hw_get_tsf64(ah);
2068         hw_tu = TSF_TO_TU(hw_tsf);
2069
2070 #define FUDGE 3
2071         /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2072         if (bc_tsf == -1) {
2073                 /*
2074                  * no beacons received, called internally.
2075                  * just need to refresh timers based on HW TSF.
2076                  */
2077                 nexttbtt = roundup(hw_tu + FUDGE, intval);
2078         } else if (bc_tsf == 0) {
2079                 /*
2080                  * no beacon received, probably called by ath5k_reset_tsf().
2081                  * reset TSF to start with 0.
2082                  */
2083                 nexttbtt = intval;
2084                 intval |= AR5K_BEACON_RESET_TSF;
2085         } else if (bc_tsf > hw_tsf) {
2086                 /*
2087                  * beacon received, SW merge happend but HW TSF not yet updated.
2088                  * not possible to reconfigure timers yet, but next time we
2089                  * receive a beacon with the same BSSID, the hardware will
2090                  * automatically update the TSF and then we need to reconfigure
2091                  * the timers.
2092                  */
2093                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2094                         "need to wait for HW TSF sync\n");
2095                 return;
2096         } else {
2097                 /*
2098                  * most important case for beacon synchronization between STA.
2099                  *
2100                  * beacon received and HW TSF has been already updated by HW.
2101                  * update next TBTT based on the TSF of the beacon, but make
2102                  * sure it is ahead of our local TSF timer.
2103                  */
2104                 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2105         }
2106 #undef FUDGE
2107
2108         sc->nexttbtt = nexttbtt;
2109
2110         intval |= AR5K_BEACON_ENA;
2111         ath5k_hw_init_beacon(ah, nexttbtt, intval);
2112
2113         /*
2114          * debugging output last in order to preserve the time critical aspect
2115          * of this function
2116          */
2117         if (bc_tsf == -1)
2118                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2119                         "reconfigured timers based on HW TSF\n");
2120         else if (bc_tsf == 0)
2121                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2122                         "reset HW TSF and timers\n");
2123         else
2124                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2125                         "updated timers based on beacon TSF\n");
2126
2127         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2128                           "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2129                           (unsigned long long) bc_tsf,
2130                           (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2131         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2132                 intval & AR5K_BEACON_PERIOD,
2133                 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2134                 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2135 }
2136
2137
2138 /**
2139  * ath5k_beacon_config - Configure the beacon queues and interrupts
2140  *
2141  * @sc: struct ath5k_softc pointer we are operating on
2142  *
2143  * When operating in station mode we want to receive a BMISS interrupt when we
2144  * stop seeing beacons from the AP we've associated with so we can look for
2145  * another AP to associate with.
2146  *
2147  * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2148  * interrupts to detect TSF updates only.
2149  */
2150 static void
2151 ath5k_beacon_config(struct ath5k_softc *sc)
2152 {
2153         struct ath5k_hw *ah = sc->ah;
2154
2155         ath5k_hw_set_imr(ah, 0);
2156         sc->bmisscount = 0;
2157         sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2158
2159         if (sc->opmode == NL80211_IFTYPE_STATION) {
2160                 sc->imask |= AR5K_INT_BMISS;
2161         } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2162                         sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2163                         sc->opmode == NL80211_IFTYPE_AP) {
2164                 /*
2165                  * In IBSS mode we use a self-linked tx descriptor and let the
2166                  * hardware send the beacons automatically. We have to load it
2167                  * only once here.
2168                  * We use the SWBA interrupt only to keep track of the beacon
2169                  * timers in order to detect automatic TSF updates.
2170                  */
2171                 ath5k_beaconq_config(sc);
2172
2173                 sc->imask |= AR5K_INT_SWBA;
2174
2175                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2176                         if (ath5k_hw_hasveol(ah)) {
2177                                 spin_lock(&sc->block);
2178                                 ath5k_beacon_send(sc);
2179                                 spin_unlock(&sc->block);
2180                         }
2181                 } else
2182                         ath5k_beacon_update_timers(sc, -1);
2183         }
2184
2185         ath5k_hw_set_imr(ah, sc->imask);
2186 }
2187
2188
2189 /********************\
2190 * Interrupt handling *
2191 \********************/
2192
2193 static int
2194 ath5k_init(struct ath5k_softc *sc, bool is_resume)
2195 {
2196         struct ath5k_hw *ah = sc->ah;
2197         int ret, i;
2198
2199         mutex_lock(&sc->lock);
2200
2201         if (is_resume && !test_bit(ATH_STAT_STARTED, sc->status))
2202                 goto out_ok;
2203
2204         __clear_bit(ATH_STAT_STARTED, sc->status);
2205
2206         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2207
2208         /*
2209          * Stop anything previously setup.  This is safe
2210          * no matter this is the first time through or not.
2211          */
2212         ath5k_stop_locked(sc);
2213
2214         /*
2215          * The basic interface to setting the hardware in a good
2216          * state is ``reset''.  On return the hardware is known to
2217          * be powered up and with interrupts disabled.  This must
2218          * be followed by initialization of the appropriate bits
2219          * and then setup of the interrupt mask.
2220          */
2221         sc->curchan = sc->hw->conf.channel;
2222         sc->curband = &sc->sbands[sc->curchan->band];
2223         sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2224                 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2225                 AR5K_INT_MIB;
2226         ret = ath5k_reset(sc, false, false);
2227         if (ret)
2228                 goto done;
2229
2230         /*
2231          * Reset the key cache since some parts do not reset the
2232          * contents on initial power up or resume from suspend.
2233          */
2234         for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2235                 ath5k_hw_reset_key(ah, i);
2236
2237         __set_bit(ATH_STAT_STARTED, sc->status);
2238
2239         /* Set ack to be sent at low bit-rates */
2240         ath5k_hw_set_ack_bitrate_high(ah, false);
2241
2242         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2243                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2244
2245 out_ok:
2246         ret = 0;
2247 done:
2248         mmiowb();
2249         mutex_unlock(&sc->lock);
2250         return ret;
2251 }
2252
2253 static int
2254 ath5k_stop_locked(struct ath5k_softc *sc)
2255 {
2256         struct ath5k_hw *ah = sc->ah;
2257
2258         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2259                         test_bit(ATH_STAT_INVALID, sc->status));
2260
2261         /*
2262          * Shutdown the hardware and driver:
2263          *    stop output from above
2264          *    disable interrupts
2265          *    turn off timers
2266          *    turn off the radio
2267          *    clear transmit machinery
2268          *    clear receive machinery
2269          *    drain and release tx queues
2270          *    reclaim beacon resources
2271          *    power down hardware
2272          *
2273          * Note that some of this work is not possible if the
2274          * hardware is gone (invalid).
2275          */
2276         ieee80211_stop_queues(sc->hw);
2277
2278         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2279                 ath5k_led_off(sc);
2280                 ath5k_hw_set_imr(ah, 0);
2281                 synchronize_irq(sc->pdev->irq);
2282         }
2283         ath5k_txq_cleanup(sc);
2284         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2285                 ath5k_rx_stop(sc);
2286                 ath5k_hw_phy_disable(ah);
2287         } else
2288                 sc->rxlink = NULL;
2289
2290         return 0;
2291 }
2292
2293 /*
2294  * Stop the device, grabbing the top-level lock to protect
2295  * against concurrent entry through ath5k_init (which can happen
2296  * if another thread does a system call and the thread doing the
2297  * stop is preempted).
2298  */
2299 static int
2300 ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend)
2301 {
2302         int ret;
2303
2304         mutex_lock(&sc->lock);
2305         ret = ath5k_stop_locked(sc);
2306         if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2307                 /*
2308                  * Set the chip in full sleep mode.  Note that we are
2309                  * careful to do this only when bringing the interface
2310                  * completely to a stop.  When the chip is in this state
2311                  * it must be carefully woken up or references to
2312                  * registers in the PCI clock domain may freeze the bus
2313                  * (and system).  This varies by chip and is mostly an
2314                  * issue with newer parts that go to sleep more quickly.
2315                  */
2316                 if (sc->ah->ah_mac_srev >= 0x78) {
2317                         /*
2318                          * XXX
2319                          * don't put newer MAC revisions > 7.8 to sleep because
2320                          * of the above mentioned problems
2321                          */
2322                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2323                                 "not putting device to sleep\n");
2324                 } else {
2325                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2326                                 "putting device to full sleep\n");
2327                         ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2328                 }
2329         }
2330         ath5k_txbuf_free(sc, sc->bbuf);
2331         if (!is_suspend)
2332                 __clear_bit(ATH_STAT_STARTED, sc->status);
2333
2334         mmiowb();
2335         mutex_unlock(&sc->lock);
2336
2337         del_timer_sync(&sc->calib_tim);
2338         tasklet_kill(&sc->rxtq);
2339         tasklet_kill(&sc->txtq);
2340         tasklet_kill(&sc->restq);
2341
2342         return ret;
2343 }
2344
2345 static irqreturn_t
2346 ath5k_intr(int irq, void *dev_id)
2347 {
2348         struct ath5k_softc *sc = dev_id;
2349         struct ath5k_hw *ah = sc->ah;
2350         enum ath5k_int status;
2351         unsigned int counter = 1000;
2352
2353         if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2354                                 !ath5k_hw_is_intr_pending(ah)))
2355                 return IRQ_NONE;
2356
2357         do {
2358                 /*
2359                  * Figure out the reason(s) for the interrupt.  Note
2360                  * that get_isr returns a pseudo-ISR that may include
2361                  * bits we haven't explicitly enabled so we mask the
2362                  * value to insure we only process bits we requested.
2363                  */
2364                 ath5k_hw_get_isr(ah, &status);          /* NB: clears IRQ too */
2365                 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2366                                 status, sc->imask);
2367                 status &= sc->imask; /* discard unasked for bits */
2368                 if (unlikely(status & AR5K_INT_FATAL)) {
2369                         /*
2370                          * Fatal errors are unrecoverable.
2371                          * Typically these are caused by DMA errors.
2372                          */
2373                         tasklet_schedule(&sc->restq);
2374                 } else if (unlikely(status & AR5K_INT_RXORN)) {
2375                         tasklet_schedule(&sc->restq);
2376                 } else {
2377                         if (status & AR5K_INT_SWBA) {
2378                                 /*
2379                                 * Software beacon alert--time to send a beacon.
2380                                 * Handle beacon transmission directly; deferring
2381                                 * this is too slow to meet timing constraints
2382                                 * under load.
2383                                 *
2384                                 * In IBSS mode we use this interrupt just to
2385                                 * keep track of the next TBTT (target beacon
2386                                 * transmission time) in order to detect wether
2387                                 * automatic TSF updates happened.
2388                                 */
2389                                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2390                                          /* XXX: only if VEOL suppported */
2391                                         u64 tsf = ath5k_hw_get_tsf64(ah);
2392                                         sc->nexttbtt += sc->bintval;
2393                                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2394                                                   "SWBA nexttbtt: %x hw_tu: %x "
2395                                                   "TSF: %llx\n",
2396                                                   sc->nexttbtt,
2397                                                   TSF_TO_TU(tsf),
2398                                                   (unsigned long long) tsf);
2399                                 } else {
2400                                         spin_lock(&sc->block);
2401                                         ath5k_beacon_send(sc);
2402                                         spin_unlock(&sc->block);
2403                                 }
2404                         }
2405                         if (status & AR5K_INT_RXEOL) {
2406                                 /*
2407                                 * NB: the hardware should re-read the link when
2408                                 *     RXE bit is written, but it doesn't work at
2409                                 *     least on older hardware revs.
2410                                 */
2411                                 sc->rxlink = NULL;
2412                         }
2413                         if (status & AR5K_INT_TXURN) {
2414                                 /* bump tx trigger level */
2415                                 ath5k_hw_update_tx_triglevel(ah, true);
2416                         }
2417                         if (status & AR5K_INT_RX)
2418                                 tasklet_schedule(&sc->rxtq);
2419                         if (status & AR5K_INT_TX)
2420                                 tasklet_schedule(&sc->txtq);
2421                         if (status & AR5K_INT_BMISS) {
2422                         }
2423                         if (status & AR5K_INT_MIB) {
2424                                 /*
2425                                  * These stats are also used for ANI i think
2426                                  * so how about updating them more often ?
2427                                  */
2428                                 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2429                         }
2430                 }
2431         } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2432
2433         if (unlikely(!counter))
2434                 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2435
2436         return IRQ_HANDLED;
2437 }
2438
2439 static void
2440 ath5k_tasklet_reset(unsigned long data)
2441 {
2442         struct ath5k_softc *sc = (void *)data;
2443
2444         ath5k_reset_wake(sc);
2445 }
2446
2447 /*
2448  * Periodically recalibrate the PHY to account
2449  * for temperature/environment changes.
2450  */
2451 static void
2452 ath5k_calibrate(unsigned long data)
2453 {
2454         struct ath5k_softc *sc = (void *)data;
2455         struct ath5k_hw *ah = sc->ah;
2456
2457         ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2458                 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2459                 sc->curchan->hw_value);
2460
2461         if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2462                 /*
2463                  * Rfgain is out of bounds, reset the chip
2464                  * to load new gain values.
2465                  */
2466                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2467                 ath5k_reset_wake(sc);
2468         }
2469         if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2470                 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2471                         ieee80211_frequency_to_channel(
2472                                 sc->curchan->center_freq));
2473
2474         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2475                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2476 }
2477
2478
2479
2480 /***************\
2481 * LED functions *
2482 \***************/
2483
2484 static void
2485 ath5k_led_enable(struct ath5k_softc *sc)
2486 {
2487         if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2488                 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2489                 ath5k_led_off(sc);
2490         }
2491 }
2492
2493 static void
2494 ath5k_led_on(struct ath5k_softc *sc)
2495 {
2496         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2497                 return;
2498         ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2499 }
2500
2501 static void
2502 ath5k_led_off(struct ath5k_softc *sc)
2503 {
2504         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2505                 return;
2506         ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2507 }
2508
2509 static void
2510 ath5k_led_brightness_set(struct led_classdev *led_dev,
2511         enum led_brightness brightness)
2512 {
2513         struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2514                 led_dev);
2515
2516         if (brightness == LED_OFF)
2517                 ath5k_led_off(led->sc);
2518         else
2519                 ath5k_led_on(led->sc);
2520 }
2521
2522 static int
2523 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2524                    const char *name, char *trigger)
2525 {
2526         int err;
2527
2528         led->sc = sc;
2529         strncpy(led->name, name, sizeof(led->name));
2530         led->led_dev.name = led->name;
2531         led->led_dev.default_trigger = trigger;
2532         led->led_dev.brightness_set = ath5k_led_brightness_set;
2533
2534         err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2535         if (err)
2536         {
2537                 ATH5K_WARN(sc, "could not register LED %s\n", name);
2538                 led->sc = NULL;
2539         }
2540         return err;
2541 }
2542
2543 static void
2544 ath5k_unregister_led(struct ath5k_led *led)
2545 {
2546         if (!led->sc)
2547                 return;
2548         led_classdev_unregister(&led->led_dev);
2549         ath5k_led_off(led->sc);
2550         led->sc = NULL;
2551 }
2552
2553 static void
2554 ath5k_unregister_leds(struct ath5k_softc *sc)
2555 {
2556         ath5k_unregister_led(&sc->rx_led);
2557         ath5k_unregister_led(&sc->tx_led);
2558 }
2559
2560
2561 static int
2562 ath5k_init_leds(struct ath5k_softc *sc)
2563 {
2564         int ret = 0;
2565         struct ieee80211_hw *hw = sc->hw;
2566         struct pci_dev *pdev = sc->pdev;
2567         char name[ATH5K_LED_MAX_NAME_LEN + 1];
2568
2569         /*
2570          * Auto-enable soft led processing for IBM cards and for
2571          * 5211 minipci cards.
2572          */
2573         if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2574             pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2575                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2576                 sc->led_pin = 0;
2577                 sc->led_on = 0;  /* active low */
2578         }
2579         /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2580         if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2581                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2582                 sc->led_pin = 1;
2583                 sc->led_on = 1;  /* active high */
2584         }
2585         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2586                 goto out;
2587
2588         ath5k_led_enable(sc);
2589
2590         snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2591         ret = ath5k_register_led(sc, &sc->rx_led, name,
2592                 ieee80211_get_rx_led_name(hw));
2593         if (ret)
2594                 goto out;
2595
2596         snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2597         ret = ath5k_register_led(sc, &sc->tx_led, name,
2598                 ieee80211_get_tx_led_name(hw));
2599 out:
2600         return ret;
2601 }
2602
2603
2604 /********************\
2605 * Mac80211 functions *
2606 \********************/
2607
2608 static int
2609 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2610 {
2611         struct ath5k_softc *sc = hw->priv;
2612         struct ath5k_buf *bf;
2613         unsigned long flags;
2614         int hdrlen;
2615         int pad;
2616
2617         ath5k_debug_dump_skb(sc, skb, "TX  ", 1);
2618
2619         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2620                 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2621
2622         /*
2623          * the hardware expects the header padded to 4 byte boundaries
2624          * if this is not the case we add the padding after the header
2625          */
2626         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2627         if (hdrlen & 3) {
2628                 pad = hdrlen % 4;
2629                 if (skb_headroom(skb) < pad) {
2630                         ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2631                                 " headroom to pad %d\n", hdrlen, pad);
2632                         return -1;
2633                 }
2634                 skb_push(skb, pad);
2635                 memmove(skb->data, skb->data+pad, hdrlen);
2636         }
2637
2638         spin_lock_irqsave(&sc->txbuflock, flags);
2639         if (list_empty(&sc->txbuf)) {
2640                 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2641                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2642                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2643                 return -1;
2644         }
2645         bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2646         list_del(&bf->list);
2647         sc->txbuf_len--;
2648         if (list_empty(&sc->txbuf))
2649                 ieee80211_stop_queues(hw);
2650         spin_unlock_irqrestore(&sc->txbuflock, flags);
2651
2652         bf->skb = skb;
2653
2654         if (ath5k_txbuf_setup(sc, bf)) {
2655                 bf->skb = NULL;
2656                 spin_lock_irqsave(&sc->txbuflock, flags);
2657                 list_add_tail(&bf->list, &sc->txbuf);
2658                 sc->txbuf_len++;
2659                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2660                 dev_kfree_skb_any(skb);
2661                 return 0;
2662         }
2663
2664         return 0;
2665 }
2666
2667 static int
2668 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2669 {
2670         struct ath5k_hw *ah = sc->ah;
2671         int ret;
2672
2673         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2674
2675         if (stop) {
2676                 ath5k_hw_set_imr(ah, 0);
2677                 ath5k_txq_cleanup(sc);
2678                 ath5k_rx_stop(sc);
2679         }
2680         ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2681         if (ret) {
2682                 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2683                 goto err;
2684         }
2685
2686         /*
2687          * This is needed only to setup initial state
2688          * but it's best done after a reset.
2689          */
2690         ath5k_hw_set_txpower_limit(sc->ah, 0);
2691
2692         ret = ath5k_rx_start(sc);
2693         if (ret) {
2694                 ATH5K_ERR(sc, "can't start recv logic\n");
2695                 goto err;
2696         }
2697
2698         /*
2699          * Change channels and update the h/w rate map if we're switching;
2700          * e.g. 11a to 11b/g.
2701          *
2702          * We may be doing a reset in response to an ioctl that changes the
2703          * channel so update any state that might change as a result.
2704          *
2705          * XXX needed?
2706          */
2707 /*      ath5k_chan_change(sc, c); */
2708
2709         ath5k_beacon_config(sc);
2710         /* intrs are enabled by ath5k_beacon_config */
2711
2712         return 0;
2713 err:
2714         return ret;
2715 }
2716
2717 static int
2718 ath5k_reset_wake(struct ath5k_softc *sc)
2719 {
2720         int ret;
2721
2722         ret = ath5k_reset(sc, true, true);
2723         if (!ret)
2724                 ieee80211_wake_queues(sc->hw);
2725
2726         return ret;
2727 }
2728
2729 static int ath5k_start(struct ieee80211_hw *hw)
2730 {
2731         return ath5k_init(hw->priv, false);
2732 }
2733
2734 static void ath5k_stop(struct ieee80211_hw *hw)
2735 {
2736         ath5k_stop_hw(hw->priv, false);
2737 }
2738
2739 static int ath5k_add_interface(struct ieee80211_hw *hw,
2740                 struct ieee80211_if_init_conf *conf)
2741 {
2742         struct ath5k_softc *sc = hw->priv;
2743         int ret;
2744
2745         mutex_lock(&sc->lock);
2746         if (sc->vif) {
2747                 ret = 0;
2748                 goto end;
2749         }
2750
2751         sc->vif = conf->vif;
2752
2753         switch (conf->type) {
2754         case NL80211_IFTYPE_AP:
2755         case NL80211_IFTYPE_STATION:
2756         case NL80211_IFTYPE_ADHOC:
2757         case NL80211_IFTYPE_MESH_POINT:
2758         case NL80211_IFTYPE_MONITOR:
2759                 sc->opmode = conf->type;
2760                 break;
2761         default:
2762                 ret = -EOPNOTSUPP;
2763                 goto end;
2764         }
2765
2766         /* Set to a reasonable value. Note that this will
2767          * be set to mac80211's value at ath5k_config(). */
2768         sc->bintval = 1000;
2769
2770         ret = 0;
2771 end:
2772         mutex_unlock(&sc->lock);
2773         return ret;
2774 }
2775
2776 static void
2777 ath5k_remove_interface(struct ieee80211_hw *hw,
2778                         struct ieee80211_if_init_conf *conf)
2779 {
2780         struct ath5k_softc *sc = hw->priv;
2781
2782         mutex_lock(&sc->lock);
2783         if (sc->vif != conf->vif)
2784                 goto end;
2785
2786         sc->vif = NULL;
2787 end:
2788         mutex_unlock(&sc->lock);
2789 }
2790
2791 /*
2792  * TODO: Phy disable/diversity etc
2793  */
2794 static int
2795 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2796 {
2797         struct ath5k_softc *sc = hw->priv;
2798         struct ieee80211_conf *conf = &hw->conf;
2799
2800         sc->bintval = conf->beacon_int;
2801         sc->power_level = conf->power_level;
2802
2803         return ath5k_chan_set(sc, conf->channel);
2804 }
2805
2806 static int
2807 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2808                         struct ieee80211_if_conf *conf)
2809 {
2810         struct ath5k_softc *sc = hw->priv;
2811         struct ath5k_hw *ah = sc->ah;
2812         int ret;
2813
2814         mutex_lock(&sc->lock);
2815         if (sc->vif != vif) {
2816                 ret = -EIO;
2817                 goto unlock;
2818         }
2819         if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2820                 /* Cache for later use during resets */
2821                 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2822                 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2823                  * a clean way of letting us retrieve this yet. */
2824                 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2825                 mmiowb();
2826         }
2827         if (conf->changed & IEEE80211_IFCC_BEACON &&
2828                         (vif->type == NL80211_IFTYPE_ADHOC ||
2829                          vif->type == NL80211_IFTYPE_MESH_POINT ||
2830                          vif->type == NL80211_IFTYPE_AP)) {
2831                 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2832                 if (!beacon) {
2833                         ret = -ENOMEM;
2834                         goto unlock;
2835                 }
2836                 ath5k_beacon_update(sc, beacon);
2837         }
2838         mutex_unlock(&sc->lock);
2839
2840         return ath5k_reset_wake(sc);
2841 unlock:
2842         mutex_unlock(&sc->lock);
2843         return ret;
2844 }
2845
2846 #define SUPPORTED_FIF_FLAGS \
2847         FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
2848         FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2849         FIF_BCN_PRBRESP_PROMISC
2850 /*
2851  * o always accept unicast, broadcast, and multicast traffic
2852  * o multicast traffic for all BSSIDs will be enabled if mac80211
2853  *   says it should be
2854  * o maintain current state of phy ofdm or phy cck error reception.
2855  *   If the hardware detects any of these type of errors then
2856  *   ath5k_hw_get_rx_filter() will pass to us the respective
2857  *   hardware filters to be able to receive these type of frames.
2858  * o probe request frames are accepted only when operating in
2859  *   hostap, adhoc, or monitor modes
2860  * o enable promiscuous mode according to the interface state
2861  * o accept beacons:
2862  *   - when operating in adhoc mode so the 802.11 layer creates
2863  *     node table entries for peers,
2864  *   - when operating in station mode for collecting rssi data when
2865  *     the station is otherwise quiet, or
2866  *   - when scanning
2867  */
2868 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2869                 unsigned int changed_flags,
2870                 unsigned int *new_flags,
2871                 int mc_count, struct dev_mc_list *mclist)
2872 {
2873         struct ath5k_softc *sc = hw->priv;
2874         struct ath5k_hw *ah = sc->ah;
2875         u32 mfilt[2], val, rfilt;
2876         u8 pos;
2877         int i;
2878
2879         mfilt[0] = 0;
2880         mfilt[1] = 0;
2881
2882         /* Only deal with supported flags */
2883         changed_flags &= SUPPORTED_FIF_FLAGS;
2884         *new_flags &= SUPPORTED_FIF_FLAGS;
2885
2886         /* If HW detects any phy or radar errors, leave those filters on.
2887          * Also, always enable Unicast, Broadcasts and Multicast
2888          * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2889         rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2890                 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2891                 AR5K_RX_FILTER_MCAST);
2892
2893         if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2894                 if (*new_flags & FIF_PROMISC_IN_BSS) {
2895                         rfilt |= AR5K_RX_FILTER_PROM;
2896                         __set_bit(ATH_STAT_PROMISC, sc->status);
2897                 }
2898                 else
2899                         __clear_bit(ATH_STAT_PROMISC, sc->status);
2900         }
2901
2902         /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2903         if (*new_flags & FIF_ALLMULTI) {
2904                 mfilt[0] =  ~0;
2905                 mfilt[1] =  ~0;
2906         } else {
2907                 for (i = 0; i < mc_count; i++) {
2908                         if (!mclist)
2909                                 break;
2910                         /* calculate XOR of eight 6-bit values */
2911                         val = get_unaligned_le32(mclist->dmi_addr + 0);
2912                         pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2913                         val = get_unaligned_le32(mclist->dmi_addr + 3);
2914                         pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2915                         pos &= 0x3f;
2916                         mfilt[pos / 32] |= (1 << (pos % 32));
2917                         /* XXX: we might be able to just do this instead,
2918                         * but not sure, needs testing, if we do use this we'd
2919                         * neet to inform below to not reset the mcast */
2920                         /* ath5k_hw_set_mcast_filterindex(ah,
2921                          *      mclist->dmi_addr[5]); */
2922                         mclist = mclist->next;
2923                 }
2924         }
2925
2926         /* This is the best we can do */
2927         if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2928                 rfilt |= AR5K_RX_FILTER_PHYERR;
2929
2930         /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2931         * and probes for any BSSID, this needs testing */
2932         if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2933                 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2934
2935         /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2936          * set we should only pass on control frames for this
2937          * station. This needs testing. I believe right now this
2938          * enables *all* control frames, which is OK.. but
2939          * but we should see if we can improve on granularity */
2940         if (*new_flags & FIF_CONTROL)
2941                 rfilt |= AR5K_RX_FILTER_CONTROL;
2942
2943         /* Additional settings per mode -- this is per ath5k */
2944
2945         /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2946
2947         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2948                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2949                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2950         if (sc->opmode != NL80211_IFTYPE_STATION)
2951                 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2952         if (sc->opmode != NL80211_IFTYPE_AP &&
2953                 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2954                 test_bit(ATH_STAT_PROMISC, sc->status))
2955                 rfilt |= AR5K_RX_FILTER_PROM;
2956         if (sc->opmode == NL80211_IFTYPE_ADHOC)
2957                 rfilt |= AR5K_RX_FILTER_BEACON;
2958         if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2959                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2960                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2961
2962         /* Set filters */
2963         ath5k_hw_set_rx_filter(ah,rfilt);
2964
2965         /* Set multicast bits */
2966         ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2967         /* Set the cached hw filter flags, this will alter actually
2968          * be set in HW */
2969         sc->filter_flags = rfilt;
2970 }
2971
2972 static int
2973 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2974                 const u8 *local_addr, const u8 *addr,
2975                 struct ieee80211_key_conf *key)
2976 {
2977         struct ath5k_softc *sc = hw->priv;
2978         int ret = 0;
2979
2980         switch(key->alg) {
2981         case ALG_WEP:
2982         /* XXX: fix hardware encryption, its not working. For now
2983          * allow software encryption */
2984                 /* break; */
2985         case ALG_TKIP:
2986         case ALG_CCMP:
2987                 return -EOPNOTSUPP;
2988         default:
2989                 WARN_ON(1);
2990                 return -EINVAL;
2991         }
2992
2993         mutex_lock(&sc->lock);
2994
2995         switch (cmd) {
2996         case SET_KEY:
2997                 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2998                 if (ret) {
2999                         ATH5K_ERR(sc, "can't set the key\n");
3000                         goto unlock;
3001                 }
3002                 __set_bit(key->keyidx, sc->keymap);
3003                 key->hw_key_idx = key->keyidx;
3004                 break;
3005         case DISABLE_KEY:
3006                 ath5k_hw_reset_key(sc->ah, key->keyidx);
3007                 __clear_bit(key->keyidx, sc->keymap);
3008                 break;
3009         default:
3010                 ret = -EINVAL;
3011                 goto unlock;
3012         }
3013
3014 unlock:
3015         mmiowb();
3016         mutex_unlock(&sc->lock);
3017         return ret;
3018 }
3019
3020 static int
3021 ath5k_get_stats(struct ieee80211_hw *hw,
3022                 struct ieee80211_low_level_stats *stats)
3023 {
3024         struct ath5k_softc *sc = hw->priv;
3025         struct ath5k_hw *ah = sc->ah;
3026
3027         /* Force update */
3028         ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3029
3030         memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3031
3032         return 0;
3033 }
3034
3035 static int
3036 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3037                 struct ieee80211_tx_queue_stats *stats)
3038 {
3039         struct ath5k_softc *sc = hw->priv;
3040
3041         memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3042
3043         return 0;
3044 }
3045
3046 static u64
3047 ath5k_get_tsf(struct ieee80211_hw *hw)
3048 {
3049         struct ath5k_softc *sc = hw->priv;
3050
3051         return ath5k_hw_get_tsf64(sc->ah);
3052 }
3053
3054 static void
3055 ath5k_reset_tsf(struct ieee80211_hw *hw)
3056 {
3057         struct ath5k_softc *sc = hw->priv;
3058
3059         /*
3060          * in IBSS mode we need to update the beacon timers too.
3061          * this will also reset the TSF if we call it with 0
3062          */
3063         if (sc->opmode == NL80211_IFTYPE_ADHOC)
3064                 ath5k_beacon_update_timers(sc, 0);
3065         else
3066                 ath5k_hw_reset_tsf(sc->ah);
3067 }
3068
3069 static int
3070 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3071 {
3072         unsigned long flags;
3073         int ret;
3074
3075         ath5k_debug_dump_skb(sc, skb, "BC  ", 1);
3076
3077         spin_lock_irqsave(&sc->block, flags);
3078         ath5k_txbuf_free(sc, sc->bbuf);
3079         sc->bbuf->skb = skb;
3080         ret = ath5k_beacon_setup(sc, sc->bbuf);
3081         if (ret)
3082                 sc->bbuf->skb = NULL;
3083         spin_unlock_irqrestore(&sc->block, flags);
3084         if (!ret) {
3085                 ath5k_beacon_config(sc);
3086                 mmiowb();
3087         }
3088
3089         return ret;
3090 }
3091