e581b1f6c40c93d0e066da815e78bd345ec3e125
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / recv.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include "ath9k.h"
18 #include "ar9003_mac.h"
19
20 #define SKB_CB_ATHBUF(__skb)    (*((struct ath_buf **)__skb->cb))
21
22 static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
23                                                int mindelta, int main_rssi_avg,
24                                                int alt_rssi_avg, int pkt_count)
25 {
26         return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
27                 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
28                 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
29 }
30
31 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
32 {
33         return sc->ps_enabled &&
34                (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
35 }
36
37 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
38                                              struct ieee80211_hdr *hdr)
39 {
40         struct ieee80211_hw *hw = sc->pri_wiphy->hw;
41         int i;
42
43         spin_lock_bh(&sc->wiphy_lock);
44         for (i = 0; i < sc->num_sec_wiphy; i++) {
45                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
46                 if (aphy == NULL)
47                         continue;
48                 if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
49                     == 0) {
50                         hw = aphy->hw;
51                         break;
52                 }
53         }
54         spin_unlock_bh(&sc->wiphy_lock);
55         return hw;
56 }
57
58 /*
59  * Setup and link descriptors.
60  *
61  * 11N: we can no longer afford to self link the last descriptor.
62  * MAC acknowledges BA status as long as it copies frames to host
63  * buffer (or rx fifo). This can incorrectly acknowledge packets
64  * to a sender if last desc is self-linked.
65  */
66 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
67 {
68         struct ath_hw *ah = sc->sc_ah;
69         struct ath_common *common = ath9k_hw_common(ah);
70         struct ath_desc *ds;
71         struct sk_buff *skb;
72
73         ATH_RXBUF_RESET(bf);
74
75         ds = bf->bf_desc;
76         ds->ds_link = 0; /* link to null */
77         ds->ds_data = bf->bf_buf_addr;
78
79         /* virtual addr of the beginning of the buffer. */
80         skb = bf->bf_mpdu;
81         BUG_ON(skb == NULL);
82         ds->ds_vdata = skb->data;
83
84         /*
85          * setup rx descriptors. The rx_bufsize here tells the hardware
86          * how much data it can DMA to us and that we are prepared
87          * to process
88          */
89         ath9k_hw_setuprxdesc(ah, ds,
90                              common->rx_bufsize,
91                              0);
92
93         if (sc->rx.rxlink == NULL)
94                 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
95         else
96                 *sc->rx.rxlink = bf->bf_daddr;
97
98         sc->rx.rxlink = &ds->ds_link;
99         ath9k_hw_rxena(ah);
100 }
101
102 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
103 {
104         /* XXX block beacon interrupts */
105         ath9k_hw_setantenna(sc->sc_ah, antenna);
106         sc->rx.defant = antenna;
107         sc->rx.rxotherant = 0;
108 }
109
110 static void ath_opmode_init(struct ath_softc *sc)
111 {
112         struct ath_hw *ah = sc->sc_ah;
113         struct ath_common *common = ath9k_hw_common(ah);
114
115         u32 rfilt, mfilt[2];
116
117         /* configure rx filter */
118         rfilt = ath_calcrxfilter(sc);
119         ath9k_hw_setrxfilter(ah, rfilt);
120
121         /* configure bssid mask */
122         ath_hw_setbssidmask(common);
123
124         /* configure operational mode */
125         ath9k_hw_setopmode(ah);
126
127         /* calculate and install multicast filter */
128         mfilt[0] = mfilt[1] = ~0;
129         ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
130 }
131
132 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
133                                  enum ath9k_rx_qtype qtype)
134 {
135         struct ath_hw *ah = sc->sc_ah;
136         struct ath_rx_edma *rx_edma;
137         struct sk_buff *skb;
138         struct ath_buf *bf;
139
140         rx_edma = &sc->rx.rx_edma[qtype];
141         if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
142                 return false;
143
144         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
145         list_del_init(&bf->list);
146
147         skb = bf->bf_mpdu;
148
149         ATH_RXBUF_RESET(bf);
150         memset(skb->data, 0, ah->caps.rx_status_len);
151         dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
152                                 ah->caps.rx_status_len, DMA_TO_DEVICE);
153
154         SKB_CB_ATHBUF(skb) = bf;
155         ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
156         skb_queue_tail(&rx_edma->rx_fifo, skb);
157
158         return true;
159 }
160
161 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
162                                   enum ath9k_rx_qtype qtype, int size)
163 {
164         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
165         u32 nbuf = 0;
166
167         if (list_empty(&sc->rx.rxbuf)) {
168                 ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
169                 return;
170         }
171
172         while (!list_empty(&sc->rx.rxbuf)) {
173                 nbuf++;
174
175                 if (!ath_rx_edma_buf_link(sc, qtype))
176                         break;
177
178                 if (nbuf >= size)
179                         break;
180         }
181 }
182
183 static void ath_rx_remove_buffer(struct ath_softc *sc,
184                                  enum ath9k_rx_qtype qtype)
185 {
186         struct ath_buf *bf;
187         struct ath_rx_edma *rx_edma;
188         struct sk_buff *skb;
189
190         rx_edma = &sc->rx.rx_edma[qtype];
191
192         while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
193                 bf = SKB_CB_ATHBUF(skb);
194                 BUG_ON(!bf);
195                 list_add_tail(&bf->list, &sc->rx.rxbuf);
196         }
197 }
198
199 static void ath_rx_edma_cleanup(struct ath_softc *sc)
200 {
201         struct ath_buf *bf;
202
203         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
204         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
205
206         list_for_each_entry(bf, &sc->rx.rxbuf, list) {
207                 if (bf->bf_mpdu)
208                         dev_kfree_skb_any(bf->bf_mpdu);
209         }
210
211         INIT_LIST_HEAD(&sc->rx.rxbuf);
212
213         kfree(sc->rx.rx_bufptr);
214         sc->rx.rx_bufptr = NULL;
215 }
216
217 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
218 {
219         skb_queue_head_init(&rx_edma->rx_fifo);
220         skb_queue_head_init(&rx_edma->rx_buffers);
221         rx_edma->rx_fifo_hwsize = size;
222 }
223
224 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
225 {
226         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
227         struct ath_hw *ah = sc->sc_ah;
228         struct sk_buff *skb;
229         struct ath_buf *bf;
230         int error = 0, i;
231         u32 size;
232
233
234         common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
235                                      ah->caps.rx_status_len,
236                                      min(common->cachelsz, (u16)64));
237
238         ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
239                                     ah->caps.rx_status_len);
240
241         ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
242                                ah->caps.rx_lp_qdepth);
243         ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
244                                ah->caps.rx_hp_qdepth);
245
246         size = sizeof(struct ath_buf) * nbufs;
247         bf = kzalloc(size, GFP_KERNEL);
248         if (!bf)
249                 return -ENOMEM;
250
251         INIT_LIST_HEAD(&sc->rx.rxbuf);
252         sc->rx.rx_bufptr = bf;
253
254         for (i = 0; i < nbufs; i++, bf++) {
255                 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
256                 if (!skb) {
257                         error = -ENOMEM;
258                         goto rx_init_fail;
259                 }
260
261                 memset(skb->data, 0, common->rx_bufsize);
262                 bf->bf_mpdu = skb;
263
264                 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
265                                                  common->rx_bufsize,
266                                                  DMA_BIDIRECTIONAL);
267                 if (unlikely(dma_mapping_error(sc->dev,
268                                                 bf->bf_buf_addr))) {
269                                 dev_kfree_skb_any(skb);
270                                 bf->bf_mpdu = NULL;
271                                 bf->bf_buf_addr = 0;
272                                 ath_print(common, ATH_DBG_FATAL,
273                                         "dma_mapping_error() on RX init\n");
274                                 error = -ENOMEM;
275                                 goto rx_init_fail;
276                 }
277
278                 list_add_tail(&bf->list, &sc->rx.rxbuf);
279         }
280
281         return 0;
282
283 rx_init_fail:
284         ath_rx_edma_cleanup(sc);
285         return error;
286 }
287
288 static void ath_edma_start_recv(struct ath_softc *sc)
289 {
290         spin_lock_bh(&sc->rx.rxbuflock);
291
292         ath9k_hw_rxena(sc->sc_ah);
293
294         ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
295                               sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
296
297         ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
298                               sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
299
300         spin_unlock_bh(&sc->rx.rxbuflock);
301
302         ath_opmode_init(sc);
303
304         ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
305 }
306
307 static void ath_edma_stop_recv(struct ath_softc *sc)
308 {
309         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
310         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
311 }
312
313 int ath_rx_init(struct ath_softc *sc, int nbufs)
314 {
315         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
316         struct sk_buff *skb;
317         struct ath_buf *bf;
318         int error = 0;
319
320         spin_lock_init(&sc->rx.rxflushlock);
321         sc->sc_flags &= ~SC_OP_RXFLUSH;
322         spin_lock_init(&sc->rx.rxbuflock);
323
324         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
325                 return ath_rx_edma_init(sc, nbufs);
326         } else {
327                 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
328                                 min(common->cachelsz, (u16)64));
329
330                 ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
331                                 common->cachelsz, common->rx_bufsize);
332
333                 /* Initialize rx descriptors */
334
335                 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
336                                 "rx", nbufs, 1, 0);
337                 if (error != 0) {
338                         ath_print(common, ATH_DBG_FATAL,
339                                   "failed to allocate rx descriptors: %d\n",
340                                   error);
341                         goto err;
342                 }
343
344                 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
345                         skb = ath_rxbuf_alloc(common, common->rx_bufsize,
346                                               GFP_KERNEL);
347                         if (skb == NULL) {
348                                 error = -ENOMEM;
349                                 goto err;
350                         }
351
352                         bf->bf_mpdu = skb;
353                         bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
354                                         common->rx_bufsize,
355                                         DMA_FROM_DEVICE);
356                         if (unlikely(dma_mapping_error(sc->dev,
357                                                         bf->bf_buf_addr))) {
358                                 dev_kfree_skb_any(skb);
359                                 bf->bf_mpdu = NULL;
360                                 bf->bf_buf_addr = 0;
361                                 ath_print(common, ATH_DBG_FATAL,
362                                           "dma_mapping_error() on RX init\n");
363                                 error = -ENOMEM;
364                                 goto err;
365                         }
366                 }
367                 sc->rx.rxlink = NULL;
368         }
369
370 err:
371         if (error)
372                 ath_rx_cleanup(sc);
373
374         return error;
375 }
376
377 void ath_rx_cleanup(struct ath_softc *sc)
378 {
379         struct ath_hw *ah = sc->sc_ah;
380         struct ath_common *common = ath9k_hw_common(ah);
381         struct sk_buff *skb;
382         struct ath_buf *bf;
383
384         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
385                 ath_rx_edma_cleanup(sc);
386                 return;
387         } else {
388                 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
389                         skb = bf->bf_mpdu;
390                         if (skb) {
391                                 dma_unmap_single(sc->dev, bf->bf_buf_addr,
392                                                 common->rx_bufsize,
393                                                 DMA_FROM_DEVICE);
394                                 dev_kfree_skb(skb);
395                                 bf->bf_buf_addr = 0;
396                                 bf->bf_mpdu = NULL;
397                         }
398                 }
399
400                 if (sc->rx.rxdma.dd_desc_len != 0)
401                         ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
402         }
403 }
404
405 /*
406  * Calculate the receive filter according to the
407  * operating mode and state:
408  *
409  * o always accept unicast, broadcast, and multicast traffic
410  * o maintain current state of phy error reception (the hal
411  *   may enable phy error frames for noise immunity work)
412  * o probe request frames are accepted only when operating in
413  *   hostap, adhoc, or monitor modes
414  * o enable promiscuous mode according to the interface state
415  * o accept beacons:
416  *   - when operating in adhoc mode so the 802.11 layer creates
417  *     node table entries for peers,
418  *   - when operating in station mode for collecting rssi data when
419  *     the station is otherwise quiet, or
420  *   - when operating as a repeater so we see repeater-sta beacons
421  *   - when scanning
422  */
423
424 u32 ath_calcrxfilter(struct ath_softc *sc)
425 {
426 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
427
428         u32 rfilt;
429
430         rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
431                 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
432                 | ATH9K_RX_FILTER_MCAST;
433
434         if (sc->rx.rxfilter & FIF_PROBE_REQ)
435                 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
436
437         /*
438          * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
439          * mode interface or when in monitor mode. AP mode does not need this
440          * since it receives all in-BSS frames anyway.
441          */
442         if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
443              (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
444             (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR))
445                 rfilt |= ATH9K_RX_FILTER_PROM;
446
447         if (sc->rx.rxfilter & FIF_CONTROL)
448                 rfilt |= ATH9K_RX_FILTER_CONTROL;
449
450         if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
451             (sc->nvifs <= 1) &&
452             !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
453                 rfilt |= ATH9K_RX_FILTER_MYBEACON;
454         else
455                 rfilt |= ATH9K_RX_FILTER_BEACON;
456
457         if ((AR_SREV_9280_20_OR_LATER(sc->sc_ah) ||
458             AR_SREV_9285_12_OR_LATER(sc->sc_ah)) &&
459             (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
460             (sc->rx.rxfilter & FIF_PSPOLL))
461                 rfilt |= ATH9K_RX_FILTER_PSPOLL;
462
463         if (conf_is_ht(&sc->hw->conf))
464                 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
465
466         if (sc->sec_wiphy || (sc->nvifs > 1) ||
467             (sc->rx.rxfilter & FIF_OTHER_BSS)) {
468                 /* The following may also be needed for other older chips */
469                 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
470                         rfilt |= ATH9K_RX_FILTER_PROM;
471                 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
472         }
473
474         return rfilt;
475
476 #undef RX_FILTER_PRESERVE
477 }
478
479 int ath_startrecv(struct ath_softc *sc)
480 {
481         struct ath_hw *ah = sc->sc_ah;
482         struct ath_buf *bf, *tbf;
483
484         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
485                 ath_edma_start_recv(sc);
486                 return 0;
487         }
488
489         spin_lock_bh(&sc->rx.rxbuflock);
490         if (list_empty(&sc->rx.rxbuf))
491                 goto start_recv;
492
493         sc->rx.rxlink = NULL;
494         list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
495                 ath_rx_buf_link(sc, bf);
496         }
497
498         /* We could have deleted elements so the list may be empty now */
499         if (list_empty(&sc->rx.rxbuf))
500                 goto start_recv;
501
502         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
503         ath9k_hw_putrxbuf(ah, bf->bf_daddr);
504         ath9k_hw_rxena(ah);
505
506 start_recv:
507         spin_unlock_bh(&sc->rx.rxbuflock);
508         ath_opmode_init(sc);
509         ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
510
511         return 0;
512 }
513
514 bool ath_stoprecv(struct ath_softc *sc)
515 {
516         struct ath_hw *ah = sc->sc_ah;
517         bool stopped;
518
519         spin_lock_bh(&sc->rx.rxbuflock);
520         ath9k_hw_stoppcurecv(ah);
521         ath9k_hw_setrxfilter(ah, 0);
522         stopped = ath9k_hw_stopdmarecv(ah);
523
524         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
525                 ath_edma_stop_recv(sc);
526         else
527                 sc->rx.rxlink = NULL;
528         spin_unlock_bh(&sc->rx.rxbuflock);
529
530         return stopped;
531 }
532
533 void ath_flushrecv(struct ath_softc *sc)
534 {
535         spin_lock_bh(&sc->rx.rxflushlock);
536         sc->sc_flags |= SC_OP_RXFLUSH;
537         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
538                 ath_rx_tasklet(sc, 1, true);
539         ath_rx_tasklet(sc, 1, false);
540         sc->sc_flags &= ~SC_OP_RXFLUSH;
541         spin_unlock_bh(&sc->rx.rxflushlock);
542 }
543
544 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
545 {
546         /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
547         struct ieee80211_mgmt *mgmt;
548         u8 *pos, *end, id, elen;
549         struct ieee80211_tim_ie *tim;
550
551         mgmt = (struct ieee80211_mgmt *)skb->data;
552         pos = mgmt->u.beacon.variable;
553         end = skb->data + skb->len;
554
555         while (pos + 2 < end) {
556                 id = *pos++;
557                 elen = *pos++;
558                 if (pos + elen > end)
559                         break;
560
561                 if (id == WLAN_EID_TIM) {
562                         if (elen < sizeof(*tim))
563                                 break;
564                         tim = (struct ieee80211_tim_ie *) pos;
565                         if (tim->dtim_count != 0)
566                                 break;
567                         return tim->bitmap_ctrl & 0x01;
568                 }
569
570                 pos += elen;
571         }
572
573         return false;
574 }
575
576 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
577 {
578         struct ieee80211_mgmt *mgmt;
579         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
580
581         if (skb->len < 24 + 8 + 2 + 2)
582                 return;
583
584         mgmt = (struct ieee80211_mgmt *)skb->data;
585         if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
586                 return; /* not from our current AP */
587
588         sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
589
590         if (sc->ps_flags & PS_BEACON_SYNC) {
591                 sc->ps_flags &= ~PS_BEACON_SYNC;
592                 ath_print(common, ATH_DBG_PS,
593                           "Reconfigure Beacon timers based on "
594                           "timestamp from the AP\n");
595                 ath_beacon_config(sc, NULL);
596         }
597
598         if (ath_beacon_dtim_pending_cab(skb)) {
599                 /*
600                  * Remain awake waiting for buffered broadcast/multicast
601                  * frames. If the last broadcast/multicast frame is not
602                  * received properly, the next beacon frame will work as
603                  * a backup trigger for returning into NETWORK SLEEP state,
604                  * so we are waiting for it as well.
605                  */
606                 ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
607                           "buffered broadcast/multicast frame(s)\n");
608                 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
609                 return;
610         }
611
612         if (sc->ps_flags & PS_WAIT_FOR_CAB) {
613                 /*
614                  * This can happen if a broadcast frame is dropped or the AP
615                  * fails to send a frame indicating that all CAB frames have
616                  * been delivered.
617                  */
618                 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
619                 ath_print(common, ATH_DBG_PS,
620                           "PS wait for CAB frames timed out\n");
621         }
622 }
623
624 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
625 {
626         struct ieee80211_hdr *hdr;
627         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
628
629         hdr = (struct ieee80211_hdr *)skb->data;
630
631         /* Process Beacon and CAB receive in PS state */
632         if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
633             && ieee80211_is_beacon(hdr->frame_control))
634                 ath_rx_ps_beacon(sc, skb);
635         else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
636                  (ieee80211_is_data(hdr->frame_control) ||
637                   ieee80211_is_action(hdr->frame_control)) &&
638                  is_multicast_ether_addr(hdr->addr1) &&
639                  !ieee80211_has_moredata(hdr->frame_control)) {
640                 /*
641                  * No more broadcast/multicast frames to be received at this
642                  * point.
643                  */
644                 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
645                 ath_print(common, ATH_DBG_PS,
646                           "All PS CAB frames received, back to sleep\n");
647         } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
648                    !is_multicast_ether_addr(hdr->addr1) &&
649                    !ieee80211_has_morefrags(hdr->frame_control)) {
650                 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
651                 ath_print(common, ATH_DBG_PS,
652                           "Going back to sleep after having received "
653                           "PS-Poll data (0x%lx)\n",
654                         sc->ps_flags & (PS_WAIT_FOR_BEACON |
655                                         PS_WAIT_FOR_CAB |
656                                         PS_WAIT_FOR_PSPOLL_DATA |
657                                         PS_WAIT_FOR_TX_ACK));
658         }
659 }
660
661 static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
662                                     struct ath_softc *sc, struct sk_buff *skb,
663                                     struct ieee80211_rx_status *rxs)
664 {
665         struct ieee80211_hdr *hdr;
666
667         hdr = (struct ieee80211_hdr *)skb->data;
668
669         /* Send the frame to mac80211 */
670         if (is_multicast_ether_addr(hdr->addr1)) {
671                 int i;
672                 /*
673                  * Deliver broadcast/multicast frames to all suitable
674                  * virtual wiphys.
675                  */
676                 /* TODO: filter based on channel configuration */
677                 for (i = 0; i < sc->num_sec_wiphy; i++) {
678                         struct ath_wiphy *aphy = sc->sec_wiphy[i];
679                         struct sk_buff *nskb;
680                         if (aphy == NULL)
681                                 continue;
682                         nskb = skb_copy(skb, GFP_ATOMIC);
683                         if (!nskb)
684                                 continue;
685                         ieee80211_rx(aphy->hw, nskb);
686                 }
687                 ieee80211_rx(sc->hw, skb);
688         } else
689                 /* Deliver unicast frames based on receiver address */
690                 ieee80211_rx(hw, skb);
691 }
692
693 static bool ath_edma_get_buffers(struct ath_softc *sc,
694                                  enum ath9k_rx_qtype qtype)
695 {
696         struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
697         struct ath_hw *ah = sc->sc_ah;
698         struct ath_common *common = ath9k_hw_common(ah);
699         struct sk_buff *skb;
700         struct ath_buf *bf;
701         int ret;
702
703         skb = skb_peek(&rx_edma->rx_fifo);
704         if (!skb)
705                 return false;
706
707         bf = SKB_CB_ATHBUF(skb);
708         BUG_ON(!bf);
709
710         dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
711                                 common->rx_bufsize, DMA_FROM_DEVICE);
712
713         ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
714         if (ret == -EINPROGRESS) {
715                 /*let device gain the buffer again*/
716                 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
717                                 common->rx_bufsize, DMA_FROM_DEVICE);
718                 return false;
719         }
720
721         __skb_unlink(skb, &rx_edma->rx_fifo);
722         if (ret == -EINVAL) {
723                 /* corrupt descriptor, skip this one and the following one */
724                 list_add_tail(&bf->list, &sc->rx.rxbuf);
725                 ath_rx_edma_buf_link(sc, qtype);
726                 skb = skb_peek(&rx_edma->rx_fifo);
727                 if (!skb)
728                         return true;
729
730                 bf = SKB_CB_ATHBUF(skb);
731                 BUG_ON(!bf);
732
733                 __skb_unlink(skb, &rx_edma->rx_fifo);
734                 list_add_tail(&bf->list, &sc->rx.rxbuf);
735                 ath_rx_edma_buf_link(sc, qtype);
736                 return true;
737         }
738         skb_queue_tail(&rx_edma->rx_buffers, skb);
739
740         return true;
741 }
742
743 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
744                                                 struct ath_rx_status *rs,
745                                                 enum ath9k_rx_qtype qtype)
746 {
747         struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
748         struct sk_buff *skb;
749         struct ath_buf *bf;
750
751         while (ath_edma_get_buffers(sc, qtype));
752         skb = __skb_dequeue(&rx_edma->rx_buffers);
753         if (!skb)
754                 return NULL;
755
756         bf = SKB_CB_ATHBUF(skb);
757         ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
758         return bf;
759 }
760
761 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
762                                            struct ath_rx_status *rs)
763 {
764         struct ath_hw *ah = sc->sc_ah;
765         struct ath_common *common = ath9k_hw_common(ah);
766         struct ath_desc *ds;
767         struct ath_buf *bf;
768         int ret;
769
770         if (list_empty(&sc->rx.rxbuf)) {
771                 sc->rx.rxlink = NULL;
772                 return NULL;
773         }
774
775         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
776         ds = bf->bf_desc;
777
778         /*
779          * Must provide the virtual address of the current
780          * descriptor, the physical address, and the virtual
781          * address of the next descriptor in the h/w chain.
782          * This allows the HAL to look ahead to see if the
783          * hardware is done with a descriptor by checking the
784          * done bit in the following descriptor and the address
785          * of the current descriptor the DMA engine is working
786          * on.  All this is necessary because of our use of
787          * a self-linked list to avoid rx overruns.
788          */
789         ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
790         if (ret == -EINPROGRESS) {
791                 struct ath_rx_status trs;
792                 struct ath_buf *tbf;
793                 struct ath_desc *tds;
794
795                 memset(&trs, 0, sizeof(trs));
796                 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
797                         sc->rx.rxlink = NULL;
798                         return NULL;
799                 }
800
801                 tbf = list_entry(bf->list.next, struct ath_buf, list);
802
803                 /*
804                  * On some hardware the descriptor status words could
805                  * get corrupted, including the done bit. Because of
806                  * this, check if the next descriptor's done bit is
807                  * set or not.
808                  *
809                  * If the next descriptor's done bit is set, the current
810                  * descriptor has been corrupted. Force s/w to discard
811                  * this descriptor and continue...
812                  */
813
814                 tds = tbf->bf_desc;
815                 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
816                 if (ret == -EINPROGRESS)
817                         return NULL;
818         }
819
820         if (!bf->bf_mpdu)
821                 return bf;
822
823         /*
824          * Synchronize the DMA transfer with CPU before
825          * 1. accessing the frame
826          * 2. requeueing the same buffer to h/w
827          */
828         dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
829                         common->rx_bufsize,
830                         DMA_FROM_DEVICE);
831
832         return bf;
833 }
834
835 /* Assumes you've already done the endian to CPU conversion */
836 static bool ath9k_rx_accept(struct ath_common *common,
837                             struct ieee80211_hdr *hdr,
838                             struct ieee80211_rx_status *rxs,
839                             struct ath_rx_status *rx_stats,
840                             bool *decrypt_error)
841 {
842         struct ath_hw *ah = common->ah;
843         __le16 fc;
844         u8 rx_status_len = ah->caps.rx_status_len;
845
846         fc = hdr->frame_control;
847
848         if (!rx_stats->rs_datalen)
849                 return false;
850         /*
851          * rs_status follows rs_datalen so if rs_datalen is too large
852          * we can take a hint that hardware corrupted it, so ignore
853          * those frames.
854          */
855         if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
856                 return false;
857
858         /*
859          * rs_more indicates chained descriptors which can be used
860          * to link buffers together for a sort of scatter-gather
861          * operation.
862          * reject the frame, we don't support scatter-gather yet and
863          * the frame is probably corrupt anyway
864          */
865         if (rx_stats->rs_more)
866                 return false;
867
868         /*
869          * The rx_stats->rs_status will not be set until the end of the
870          * chained descriptors so it can be ignored if rs_more is set. The
871          * rs_more will be false at the last element of the chained
872          * descriptors.
873          */
874         if (rx_stats->rs_status != 0) {
875                 if (rx_stats->rs_status & ATH9K_RXERR_CRC)
876                         rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
877                 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
878                         return false;
879
880                 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
881                         *decrypt_error = true;
882                 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
883                         /*
884                          * The MIC error bit is only valid if the frame
885                          * is not a control frame or fragment, and it was
886                          * decrypted using a valid TKIP key.
887                          */
888                         if (!ieee80211_is_ctl(fc) &&
889                             !ieee80211_has_morefrags(fc) &&
890                             !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
891                             test_bit(rx_stats->rs_keyix, common->tkip_keymap))
892                                 rxs->flag |= RX_FLAG_MMIC_ERROR;
893                         else
894                                 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
895                 }
896                 /*
897                  * Reject error frames with the exception of
898                  * decryption and MIC failures. For monitor mode,
899                  * we also ignore the CRC error.
900                  */
901                 if (ah->opmode == NL80211_IFTYPE_MONITOR) {
902                         if (rx_stats->rs_status &
903                             ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
904                               ATH9K_RXERR_CRC))
905                                 return false;
906                 } else {
907                         if (rx_stats->rs_status &
908                             ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
909                                 return false;
910                         }
911                 }
912         }
913         return true;
914 }
915
916 static int ath9k_process_rate(struct ath_common *common,
917                               struct ieee80211_hw *hw,
918                               struct ath_rx_status *rx_stats,
919                               struct ieee80211_rx_status *rxs)
920 {
921         struct ieee80211_supported_band *sband;
922         enum ieee80211_band band;
923         unsigned int i = 0;
924
925         band = hw->conf.channel->band;
926         sband = hw->wiphy->bands[band];
927
928         if (rx_stats->rs_rate & 0x80) {
929                 /* HT rate */
930                 rxs->flag |= RX_FLAG_HT;
931                 if (rx_stats->rs_flags & ATH9K_RX_2040)
932                         rxs->flag |= RX_FLAG_40MHZ;
933                 if (rx_stats->rs_flags & ATH9K_RX_GI)
934                         rxs->flag |= RX_FLAG_SHORT_GI;
935                 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
936                 return 0;
937         }
938
939         for (i = 0; i < sband->n_bitrates; i++) {
940                 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
941                         rxs->rate_idx = i;
942                         return 0;
943                 }
944                 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
945                         rxs->flag |= RX_FLAG_SHORTPRE;
946                         rxs->rate_idx = i;
947                         return 0;
948                 }
949         }
950
951         /*
952          * No valid hardware bitrate found -- we should not get here
953          * because hardware has already validated this frame as OK.
954          */
955         ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected "
956                   "0x%02x using 1 Mbit\n", rx_stats->rs_rate);
957
958         return -EINVAL;
959 }
960
961 static void ath9k_process_rssi(struct ath_common *common,
962                                struct ieee80211_hw *hw,
963                                struct ieee80211_hdr *hdr,
964                                struct ath_rx_status *rx_stats)
965 {
966         struct ath_hw *ah = common->ah;
967         struct ieee80211_sta *sta;
968         struct ath_node *an;
969         int last_rssi = ATH_RSSI_DUMMY_MARKER;
970         __le16 fc;
971
972         fc = hdr->frame_control;
973
974         rcu_read_lock();
975         /*
976          * XXX: use ieee80211_find_sta! This requires quite a bit of work
977          * under the current ath9k virtual wiphy implementation as we have
978          * no way of tying a vif to wiphy. Typically vifs are attached to
979          * at least one sdata of a wiphy on mac80211 but with ath9k virtual
980          * wiphy you'd have to iterate over every wiphy and each sdata.
981          */
982         if (is_multicast_ether_addr(hdr->addr1))
983                 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr2, NULL);
984         else
985                 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr2, hdr->addr1);
986
987         if (sta) {
988                 an = (struct ath_node *) sta->drv_priv;
989                 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD &&
990                    !rx_stats->rs_moreaggr)
991                         ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi);
992                 last_rssi = an->last_rssi;
993         }
994         rcu_read_unlock();
995
996         if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
997                 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
998                                               ATH_RSSI_EP_MULTIPLIER);
999         if (rx_stats->rs_rssi < 0)
1000                 rx_stats->rs_rssi = 0;
1001
1002         /* Update Beacon RSSI, this is used by ANI. */
1003         if (ieee80211_is_beacon(fc))
1004                 ah->stats.avgbrssi = rx_stats->rs_rssi;
1005 }
1006
1007 /*
1008  * For Decrypt or Demic errors, we only mark packet status here and always push
1009  * up the frame up to let mac80211 handle the actual error case, be it no
1010  * decryption key or real decryption error. This let us keep statistics there.
1011  */
1012 static int ath9k_rx_skb_preprocess(struct ath_common *common,
1013                                    struct ieee80211_hw *hw,
1014                                    struct ieee80211_hdr *hdr,
1015                                    struct ath_rx_status *rx_stats,
1016                                    struct ieee80211_rx_status *rx_status,
1017                                    bool *decrypt_error)
1018 {
1019         memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
1020
1021         /*
1022          * everything but the rate is checked here, the rate check is done
1023          * separately to avoid doing two lookups for a rate for each frame.
1024          */
1025         if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
1026                 return -EINVAL;
1027
1028         ath9k_process_rssi(common, hw, hdr, rx_stats);
1029
1030         if (ath9k_process_rate(common, hw, rx_stats, rx_status))
1031                 return -EINVAL;
1032
1033         rx_status->band = hw->conf.channel->band;
1034         rx_status->freq = hw->conf.channel->center_freq;
1035         rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
1036         rx_status->antenna = rx_stats->rs_antenna;
1037         rx_status->flag |= RX_FLAG_TSFT;
1038
1039         return 0;
1040 }
1041
1042 static void ath9k_rx_skb_postprocess(struct ath_common *common,
1043                                      struct sk_buff *skb,
1044                                      struct ath_rx_status *rx_stats,
1045                                      struct ieee80211_rx_status *rxs,
1046                                      bool decrypt_error)
1047 {
1048         struct ath_hw *ah = common->ah;
1049         struct ieee80211_hdr *hdr;
1050         int hdrlen, padpos, padsize;
1051         u8 keyix;
1052         __le16 fc;
1053
1054         /* see if any padding is done by the hw and remove it */
1055         hdr = (struct ieee80211_hdr *) skb->data;
1056         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1057         fc = hdr->frame_control;
1058         padpos = ath9k_cmn_padpos(hdr->frame_control);
1059
1060         /* The MAC header is padded to have 32-bit boundary if the
1061          * packet payload is non-zero. The general calculation for
1062          * padsize would take into account odd header lengths:
1063          * padsize = (4 - padpos % 4) % 4; However, since only
1064          * even-length headers are used, padding can only be 0 or 2
1065          * bytes and we can optimize this a bit. In addition, we must
1066          * not try to remove padding from short control frames that do
1067          * not have payload. */
1068         padsize = padpos & 3;
1069         if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1070                 memmove(skb->data + padsize, skb->data, padpos);
1071                 skb_pull(skb, padsize);
1072         }
1073
1074         keyix = rx_stats->rs_keyix;
1075
1076         if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1077             ieee80211_has_protected(fc)) {
1078                 rxs->flag |= RX_FLAG_DECRYPTED;
1079         } else if (ieee80211_has_protected(fc)
1080                    && !decrypt_error && skb->len >= hdrlen + 4) {
1081                 keyix = skb->data[hdrlen + 3] >> 6;
1082
1083                 if (test_bit(keyix, common->keymap))
1084                         rxs->flag |= RX_FLAG_DECRYPTED;
1085         }
1086         if (ah->sw_mgmt_crypto &&
1087             (rxs->flag & RX_FLAG_DECRYPTED) &&
1088             ieee80211_is_mgmt(fc))
1089                 /* Use software decrypt for management frames. */
1090                 rxs->flag &= ~RX_FLAG_DECRYPTED;
1091 }
1092
1093 static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1094                                       struct ath_hw_antcomb_conf ant_conf,
1095                                       int main_rssi_avg)
1096 {
1097         antcomb->quick_scan_cnt = 0;
1098
1099         if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1100                 antcomb->rssi_lna2 = main_rssi_avg;
1101         else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1102                 antcomb->rssi_lna1 = main_rssi_avg;
1103
1104         switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1105         case (0x10): /* LNA2 A-B */
1106                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1107                 antcomb->first_quick_scan_conf =
1108                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1109                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1110                 break;
1111         case (0x20): /* LNA1 A-B */
1112                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1113                 antcomb->first_quick_scan_conf =
1114                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1115                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1116                 break;
1117         case (0x21): /* LNA1 LNA2 */
1118                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1119                 antcomb->first_quick_scan_conf =
1120                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1121                 antcomb->second_quick_scan_conf =
1122                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1123                 break;
1124         case (0x12): /* LNA2 LNA1 */
1125                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1126                 antcomb->first_quick_scan_conf =
1127                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1128                 antcomb->second_quick_scan_conf =
1129                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1130                 break;
1131         case (0x13): /* LNA2 A+B */
1132                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1133                 antcomb->first_quick_scan_conf =
1134                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1135                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1136                 break;
1137         case (0x23): /* LNA1 A+B */
1138                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1139                 antcomb->first_quick_scan_conf =
1140                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1141                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1142                 break;
1143         default:
1144                 break;
1145         }
1146 }
1147
1148 static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1149                                 struct ath_hw_antcomb_conf *div_ant_conf,
1150                                 int main_rssi_avg, int alt_rssi_avg,
1151                                 int alt_ratio)
1152 {
1153         /* alt_good */
1154         switch (antcomb->quick_scan_cnt) {
1155         case 0:
1156                 /* set alt to main, and alt to first conf */
1157                 div_ant_conf->main_lna_conf = antcomb->main_conf;
1158                 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1159                 break;
1160         case 1:
1161                 /* set alt to main, and alt to first conf */
1162                 div_ant_conf->main_lna_conf = antcomb->main_conf;
1163                 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1164                 antcomb->rssi_first = main_rssi_avg;
1165                 antcomb->rssi_second = alt_rssi_avg;
1166
1167                 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1168                         /* main is LNA1 */
1169                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1170                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1171                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1172                                                 main_rssi_avg, alt_rssi_avg,
1173                                                 antcomb->total_pkt_count))
1174                                 antcomb->first_ratio = true;
1175                         else
1176                                 antcomb->first_ratio = false;
1177                 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1178                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1179                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1180                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1181                                                 main_rssi_avg, alt_rssi_avg,
1182                                                 antcomb->total_pkt_count))
1183                                 antcomb->first_ratio = true;
1184                         else
1185                                 antcomb->first_ratio = false;
1186                 } else {
1187                         if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1188                             (alt_rssi_avg > main_rssi_avg +
1189                             ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1190                             (alt_rssi_avg > main_rssi_avg)) &&
1191                             (antcomb->total_pkt_count > 50))
1192                                 antcomb->first_ratio = true;
1193                         else
1194                                 antcomb->first_ratio = false;
1195                 }
1196                 break;
1197         case 2:
1198                 antcomb->alt_good = false;
1199                 antcomb->scan_not_start = false;
1200                 antcomb->scan = false;
1201                 antcomb->rssi_first = main_rssi_avg;
1202                 antcomb->rssi_third = alt_rssi_avg;
1203
1204                 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1205                         antcomb->rssi_lna1 = alt_rssi_avg;
1206                 else if (antcomb->second_quick_scan_conf ==
1207                          ATH_ANT_DIV_COMB_LNA2)
1208                         antcomb->rssi_lna2 = alt_rssi_avg;
1209                 else if (antcomb->second_quick_scan_conf ==
1210                          ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1211                         if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1212                                 antcomb->rssi_lna2 = main_rssi_avg;
1213                         else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1214                                 antcomb->rssi_lna1 = main_rssi_avg;
1215                 }
1216
1217                 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1218                     ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1219                         div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1220                 else
1221                         div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1222
1223                 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1224                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1225                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1226                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1227                                                 main_rssi_avg, alt_rssi_avg,
1228                                                 antcomb->total_pkt_count))
1229                                 antcomb->second_ratio = true;
1230                         else
1231                                 antcomb->second_ratio = false;
1232                 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1233                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1234                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1235                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1236                                                 main_rssi_avg, alt_rssi_avg,
1237                                                 antcomb->total_pkt_count))
1238                                 antcomb->second_ratio = true;
1239                         else
1240                                 antcomb->second_ratio = false;
1241                 } else {
1242                         if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1243                             (alt_rssi_avg > main_rssi_avg +
1244                             ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1245                             (alt_rssi_avg > main_rssi_avg)) &&
1246                             (antcomb->total_pkt_count > 50))
1247                                 antcomb->second_ratio = true;
1248                         else
1249                                 antcomb->second_ratio = false;
1250                 }
1251
1252                 /* set alt to the conf with maximun ratio */
1253                 if (antcomb->first_ratio && antcomb->second_ratio) {
1254                         if (antcomb->rssi_second > antcomb->rssi_third) {
1255                                 /* first alt*/
1256                                 if ((antcomb->first_quick_scan_conf ==
1257                                     ATH_ANT_DIV_COMB_LNA1) ||
1258                                     (antcomb->first_quick_scan_conf ==
1259                                     ATH_ANT_DIV_COMB_LNA2))
1260                                         /* Set alt LNA1 or LNA2*/
1261                                         if (div_ant_conf->main_lna_conf ==
1262                                             ATH_ANT_DIV_COMB_LNA2)
1263                                                 div_ant_conf->alt_lna_conf =
1264                                                         ATH_ANT_DIV_COMB_LNA1;
1265                                         else
1266                                                 div_ant_conf->alt_lna_conf =
1267                                                         ATH_ANT_DIV_COMB_LNA2;
1268                                 else
1269                                         /* Set alt to A+B or A-B */
1270                                         div_ant_conf->alt_lna_conf =
1271                                                 antcomb->first_quick_scan_conf;
1272                         } else if ((antcomb->second_quick_scan_conf ==
1273                                    ATH_ANT_DIV_COMB_LNA1) ||
1274                                    (antcomb->second_quick_scan_conf ==
1275                                    ATH_ANT_DIV_COMB_LNA2)) {
1276                                 /* Set alt LNA1 or LNA2 */
1277                                 if (div_ant_conf->main_lna_conf ==
1278                                     ATH_ANT_DIV_COMB_LNA2)
1279                                         div_ant_conf->alt_lna_conf =
1280                                                 ATH_ANT_DIV_COMB_LNA1;
1281                                 else
1282                                         div_ant_conf->alt_lna_conf =
1283                                                 ATH_ANT_DIV_COMB_LNA2;
1284                         } else {
1285                                 /* Set alt to A+B or A-B */
1286                                 div_ant_conf->alt_lna_conf =
1287                                         antcomb->second_quick_scan_conf;
1288                         }
1289                 } else if (antcomb->first_ratio) {
1290                         /* first alt */
1291                         if ((antcomb->first_quick_scan_conf ==
1292                             ATH_ANT_DIV_COMB_LNA1) ||
1293                             (antcomb->first_quick_scan_conf ==
1294                             ATH_ANT_DIV_COMB_LNA2))
1295                                         /* Set alt LNA1 or LNA2 */
1296                                 if (div_ant_conf->main_lna_conf ==
1297                                     ATH_ANT_DIV_COMB_LNA2)
1298                                         div_ant_conf->alt_lna_conf =
1299                                                         ATH_ANT_DIV_COMB_LNA1;
1300                                 else
1301                                         div_ant_conf->alt_lna_conf =
1302                                                         ATH_ANT_DIV_COMB_LNA2;
1303                         else
1304                                 /* Set alt to A+B or A-B */
1305                                 div_ant_conf->alt_lna_conf =
1306                                                 antcomb->first_quick_scan_conf;
1307                 } else if (antcomb->second_ratio) {
1308                                 /* second alt */
1309                         if ((antcomb->second_quick_scan_conf ==
1310                             ATH_ANT_DIV_COMB_LNA1) ||
1311                             (antcomb->second_quick_scan_conf ==
1312                             ATH_ANT_DIV_COMB_LNA2))
1313                                 /* Set alt LNA1 or LNA2 */
1314                                 if (div_ant_conf->main_lna_conf ==
1315                                     ATH_ANT_DIV_COMB_LNA2)
1316                                         div_ant_conf->alt_lna_conf =
1317                                                 ATH_ANT_DIV_COMB_LNA1;
1318                                 else
1319                                         div_ant_conf->alt_lna_conf =
1320                                                 ATH_ANT_DIV_COMB_LNA2;
1321                         else
1322                                 /* Set alt to A+B or A-B */
1323                                 div_ant_conf->alt_lna_conf =
1324                                                 antcomb->second_quick_scan_conf;
1325                 } else {
1326                         /* main is largest */
1327                         if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1328                             (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1329                                 /* Set alt LNA1 or LNA2 */
1330                                 if (div_ant_conf->main_lna_conf ==
1331                                     ATH_ANT_DIV_COMB_LNA2)
1332                                         div_ant_conf->alt_lna_conf =
1333                                                         ATH_ANT_DIV_COMB_LNA1;
1334                                 else
1335                                         div_ant_conf->alt_lna_conf =
1336                                                         ATH_ANT_DIV_COMB_LNA2;
1337                         else
1338                                 /* Set alt to A+B or A-B */
1339                                 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1340                 }
1341                 break;
1342         default:
1343                 break;
1344         }
1345 }
1346
1347 static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf)
1348 {
1349         /* Adjust the fast_div_bias based on main and alt lna conf */
1350         switch ((ant_conf->main_lna_conf << 4) | ant_conf->alt_lna_conf) {
1351         case (0x01): /* A-B LNA2 */
1352                 ant_conf->fast_div_bias = 0x3b;
1353                 break;
1354         case (0x02): /* A-B LNA1 */
1355                 ant_conf->fast_div_bias = 0x3d;
1356                 break;
1357         case (0x03): /* A-B A+B */
1358                 ant_conf->fast_div_bias = 0x1;
1359                 break;
1360         case (0x10): /* LNA2 A-B */
1361                 ant_conf->fast_div_bias = 0x7;
1362                 break;
1363         case (0x12): /* LNA2 LNA1 */
1364                 ant_conf->fast_div_bias = 0x2;
1365                 break;
1366         case (0x13): /* LNA2 A+B */
1367                 ant_conf->fast_div_bias = 0x7;
1368                 break;
1369         case (0x20): /* LNA1 A-B */
1370                 ant_conf->fast_div_bias = 0x6;
1371                 break;
1372         case (0x21): /* LNA1 LNA2 */
1373                 ant_conf->fast_div_bias = 0x0;
1374                 break;
1375         case (0x23): /* LNA1 A+B */
1376                 ant_conf->fast_div_bias = 0x6;
1377                 break;
1378         case (0x30): /* A+B A-B */
1379                 ant_conf->fast_div_bias = 0x1;
1380                 break;
1381         case (0x31): /* A+B LNA2 */
1382                 ant_conf->fast_div_bias = 0x3b;
1383                 break;
1384         case (0x32): /* A+B LNA1 */
1385                 ant_conf->fast_div_bias = 0x3d;
1386                 break;
1387         default:
1388                 break;
1389         }
1390 }
1391
1392 /* Antenna diversity and combining */
1393 static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1394 {
1395         struct ath_hw_antcomb_conf div_ant_conf;
1396         struct ath_ant_comb *antcomb = &sc->ant_comb;
1397         int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1398         int curr_main_set, curr_bias;
1399         int main_rssi = rs->rs_rssi_ctl0;
1400         int alt_rssi = rs->rs_rssi_ctl1;
1401         int rx_ant_conf,  main_ant_conf;
1402         bool short_scan = false;
1403
1404         rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1405                        ATH_ANT_RX_MASK;
1406         main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1407                          ATH_ANT_RX_MASK;
1408
1409         /* Record packet only when alt_rssi is positive */
1410         if (alt_rssi > 0) {
1411                 antcomb->total_pkt_count++;
1412                 antcomb->main_total_rssi += main_rssi;
1413                 antcomb->alt_total_rssi  += alt_rssi;
1414                 if (main_ant_conf == rx_ant_conf)
1415                         antcomb->main_recv_cnt++;
1416                 else
1417                         antcomb->alt_recv_cnt++;
1418         }
1419
1420         /* Short scan check */
1421         if (antcomb->scan && antcomb->alt_good) {
1422                 if (time_after(jiffies, antcomb->scan_start_time +
1423                     msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1424                         short_scan = true;
1425                 else
1426                         if (antcomb->total_pkt_count ==
1427                             ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1428                                 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1429                                             antcomb->total_pkt_count);
1430                                 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1431                                         short_scan = true;
1432                         }
1433         }
1434
1435         if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1436             rs->rs_moreaggr) && !short_scan)
1437                 return;
1438
1439         if (antcomb->total_pkt_count) {
1440                 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1441                              antcomb->total_pkt_count);
1442                 main_rssi_avg = (antcomb->main_total_rssi /
1443                                  antcomb->total_pkt_count);
1444                 alt_rssi_avg = (antcomb->alt_total_rssi /
1445                                  antcomb->total_pkt_count);
1446         }
1447
1448
1449         ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1450         curr_alt_set = div_ant_conf.alt_lna_conf;
1451         curr_main_set = div_ant_conf.main_lna_conf;
1452         curr_bias = div_ant_conf.fast_div_bias;
1453
1454         antcomb->count++;
1455
1456         if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1457                 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1458                         ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1459                                                   main_rssi_avg);
1460                         antcomb->alt_good = true;
1461                 } else {
1462                         antcomb->alt_good = false;
1463                 }
1464
1465                 antcomb->count = 0;
1466                 antcomb->scan = true;
1467                 antcomb->scan_not_start = true;
1468         }
1469
1470         if (!antcomb->scan) {
1471                 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1472                         if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1473                                 /* Switch main and alt LNA */
1474                                 div_ant_conf.main_lna_conf =
1475                                                 ATH_ANT_DIV_COMB_LNA2;
1476                                 div_ant_conf.alt_lna_conf  =
1477                                                 ATH_ANT_DIV_COMB_LNA1;
1478                         } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1479                                 div_ant_conf.main_lna_conf =
1480                                                 ATH_ANT_DIV_COMB_LNA1;
1481                                 div_ant_conf.alt_lna_conf  =
1482                                                 ATH_ANT_DIV_COMB_LNA2;
1483                         }
1484
1485                         goto div_comb_done;
1486                 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1487                            (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1488                         /* Set alt to another LNA */
1489                         if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1490                                 div_ant_conf.alt_lna_conf =
1491                                                 ATH_ANT_DIV_COMB_LNA1;
1492                         else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1493                                 div_ant_conf.alt_lna_conf =
1494                                                 ATH_ANT_DIV_COMB_LNA2;
1495
1496                         goto div_comb_done;
1497                 }
1498
1499                 if ((alt_rssi_avg < (main_rssi_avg +
1500                     ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA)))
1501                         goto div_comb_done;
1502         }
1503
1504         if (!antcomb->scan_not_start) {
1505                 switch (curr_alt_set) {
1506                 case ATH_ANT_DIV_COMB_LNA2:
1507                         antcomb->rssi_lna2 = alt_rssi_avg;
1508                         antcomb->rssi_lna1 = main_rssi_avg;
1509                         antcomb->scan = true;
1510                         /* set to A+B */
1511                         div_ant_conf.main_lna_conf =
1512                                 ATH_ANT_DIV_COMB_LNA1;
1513                         div_ant_conf.alt_lna_conf  =
1514                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1515                         break;
1516                 case ATH_ANT_DIV_COMB_LNA1:
1517                         antcomb->rssi_lna1 = alt_rssi_avg;
1518                         antcomb->rssi_lna2 = main_rssi_avg;
1519                         antcomb->scan = true;
1520                         /* set to A+B */
1521                         div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1522                         div_ant_conf.alt_lna_conf  =
1523                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1524                         break;
1525                 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1526                         antcomb->rssi_add = alt_rssi_avg;
1527                         antcomb->scan = true;
1528                         /* set to A-B */
1529                         div_ant_conf.alt_lna_conf =
1530                                 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1531                         break;
1532                 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1533                         antcomb->rssi_sub = alt_rssi_avg;
1534                         antcomb->scan = false;
1535                         if (antcomb->rssi_lna2 >
1536                             (antcomb->rssi_lna1 +
1537                             ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1538                                 /* use LNA2 as main LNA */
1539                                 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1540                                     (antcomb->rssi_add > antcomb->rssi_sub)) {
1541                                         /* set to A+B */
1542                                         div_ant_conf.main_lna_conf =
1543                                                 ATH_ANT_DIV_COMB_LNA2;
1544                                         div_ant_conf.alt_lna_conf  =
1545                                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1546                                 } else if (antcomb->rssi_sub >
1547                                            antcomb->rssi_lna1) {
1548                                         /* set to A-B */
1549                                         div_ant_conf.main_lna_conf =
1550                                                 ATH_ANT_DIV_COMB_LNA2;
1551                                         div_ant_conf.alt_lna_conf =
1552                                                 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1553                                 } else {
1554                                         /* set to LNA1 */
1555                                         div_ant_conf.main_lna_conf =
1556                                                 ATH_ANT_DIV_COMB_LNA2;
1557                                         div_ant_conf.alt_lna_conf =
1558                                                 ATH_ANT_DIV_COMB_LNA1;
1559                                 }
1560                         } else {
1561                                 /* use LNA1 as main LNA */
1562                                 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1563                                     (antcomb->rssi_add > antcomb->rssi_sub)) {
1564                                         /* set to A+B */
1565                                         div_ant_conf.main_lna_conf =
1566                                                 ATH_ANT_DIV_COMB_LNA1;
1567                                         div_ant_conf.alt_lna_conf  =
1568                                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1569                                 } else if (antcomb->rssi_sub >
1570                                            antcomb->rssi_lna1) {
1571                                         /* set to A-B */
1572                                         div_ant_conf.main_lna_conf =
1573                                                 ATH_ANT_DIV_COMB_LNA1;
1574                                         div_ant_conf.alt_lna_conf =
1575                                                 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1576                                 } else {
1577                                         /* set to LNA2 */
1578                                         div_ant_conf.main_lna_conf =
1579                                                 ATH_ANT_DIV_COMB_LNA1;
1580                                         div_ant_conf.alt_lna_conf =
1581                                                 ATH_ANT_DIV_COMB_LNA2;
1582                                 }
1583                         }
1584                         break;
1585                 default:
1586                         break;
1587                 }
1588         } else {
1589                 if (!antcomb->alt_good) {
1590                         antcomb->scan_not_start = false;
1591                         /* Set alt to another LNA */
1592                         if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1593                                 div_ant_conf.main_lna_conf =
1594                                                 ATH_ANT_DIV_COMB_LNA2;
1595                                 div_ant_conf.alt_lna_conf =
1596                                                 ATH_ANT_DIV_COMB_LNA1;
1597                         } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1598                                 div_ant_conf.main_lna_conf =
1599                                                 ATH_ANT_DIV_COMB_LNA1;
1600                                 div_ant_conf.alt_lna_conf =
1601                                                 ATH_ANT_DIV_COMB_LNA2;
1602                         }
1603                         goto div_comb_done;
1604                 }
1605         }
1606
1607         ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1608                                            main_rssi_avg, alt_rssi_avg,
1609                                            alt_ratio);
1610
1611         antcomb->quick_scan_cnt++;
1612
1613 div_comb_done:
1614         ath_ant_div_conf_fast_divbias(&div_ant_conf);
1615
1616         ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1617
1618         antcomb->scan_start_time = jiffies;
1619         antcomb->total_pkt_count = 0;
1620         antcomb->main_total_rssi = 0;
1621         antcomb->alt_total_rssi = 0;
1622         antcomb->main_recv_cnt = 0;
1623         antcomb->alt_recv_cnt = 0;
1624 }
1625
1626 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1627 {
1628         struct ath_buf *bf;
1629         struct sk_buff *skb = NULL, *requeue_skb;
1630         struct ieee80211_rx_status *rxs;
1631         struct ath_hw *ah = sc->sc_ah;
1632         struct ath_common *common = ath9k_hw_common(ah);
1633         /*
1634          * The hw can techncically differ from common->hw when using ath9k
1635          * virtual wiphy so to account for that we iterate over the active
1636          * wiphys and find the appropriate wiphy and therefore hw.
1637          */
1638         struct ieee80211_hw *hw = NULL;
1639         struct ieee80211_hdr *hdr;
1640         int retval;
1641         bool decrypt_error = false;
1642         struct ath_rx_status rs;
1643         enum ath9k_rx_qtype qtype;
1644         bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1645         int dma_type;
1646         u8 rx_status_len = ah->caps.rx_status_len;
1647         u64 tsf = 0;
1648         u32 tsf_lower = 0;
1649         unsigned long flags;
1650
1651         if (edma)
1652                 dma_type = DMA_BIDIRECTIONAL;
1653         else
1654                 dma_type = DMA_FROM_DEVICE;
1655
1656         qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1657         spin_lock_bh(&sc->rx.rxbuflock);
1658
1659         tsf = ath9k_hw_gettsf64(ah);
1660         tsf_lower = tsf & 0xffffffff;
1661
1662         do {
1663                 /* If handling rx interrupt and flush is in progress => exit */
1664                 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1665                         break;
1666
1667                 memset(&rs, 0, sizeof(rs));
1668                 if (edma)
1669                         bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1670                 else
1671                         bf = ath_get_next_rx_buf(sc, &rs);
1672
1673                 if (!bf)
1674                         break;
1675
1676                 skb = bf->bf_mpdu;
1677                 if (!skb)
1678                         continue;
1679
1680                 hdr = (struct ieee80211_hdr *) (skb->data + rx_status_len);
1681                 rxs =  IEEE80211_SKB_RXCB(skb);
1682
1683                 hw = ath_get_virt_hw(sc, hdr);
1684
1685                 ath_debug_stat_rx(sc, &rs);
1686
1687                 /*
1688                  * If we're asked to flush receive queue, directly
1689                  * chain it back at the queue without processing it.
1690                  */
1691                 if (flush)
1692                         goto requeue;
1693
1694                 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1695                                                  rxs, &decrypt_error);
1696                 if (retval)
1697                         goto requeue;
1698
1699                 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1700                 if (rs.rs_tstamp > tsf_lower &&
1701                     unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1702                         rxs->mactime -= 0x100000000ULL;
1703
1704                 if (rs.rs_tstamp < tsf_lower &&
1705                     unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1706                         rxs->mactime += 0x100000000ULL;
1707
1708                 /* Ensure we always have an skb to requeue once we are done
1709                  * processing the current buffer's skb */
1710                 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1711
1712                 /* If there is no memory we ignore the current RX'd frame,
1713                  * tell hardware it can give us a new frame using the old
1714                  * skb and put it at the tail of the sc->rx.rxbuf list for
1715                  * processing. */
1716                 if (!requeue_skb)
1717                         goto requeue;
1718
1719                 /* Unmap the frame */
1720                 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1721                                  common->rx_bufsize,
1722                                  dma_type);
1723
1724                 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1725                 if (ah->caps.rx_status_len)
1726                         skb_pull(skb, ah->caps.rx_status_len);
1727
1728                 ath9k_rx_skb_postprocess(common, skb, &rs,
1729                                          rxs, decrypt_error);
1730
1731                 /* We will now give hardware our shiny new allocated skb */
1732                 bf->bf_mpdu = requeue_skb;
1733                 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1734                                                  common->rx_bufsize,
1735                                                  dma_type);
1736                 if (unlikely(dma_mapping_error(sc->dev,
1737                           bf->bf_buf_addr))) {
1738                         dev_kfree_skb_any(requeue_skb);
1739                         bf->bf_mpdu = NULL;
1740                         bf->bf_buf_addr = 0;
1741                         ath_print(common, ATH_DBG_FATAL,
1742                                   "dma_mapping_error() on RX\n");
1743                         ath_rx_send_to_mac80211(hw, sc, skb, rxs);
1744                         break;
1745                 }
1746
1747                 /*
1748                  * change the default rx antenna if rx diversity chooses the
1749                  * other antenna 3 times in a row.
1750                  */
1751                 if (sc->rx.defant != rs.rs_antenna) {
1752                         if (++sc->rx.rxotherant >= 3)
1753                                 ath_setdefantenna(sc, rs.rs_antenna);
1754                 } else {
1755                         sc->rx.rxotherant = 0;
1756                 }
1757
1758                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1759                 if (unlikely(ath9k_check_auto_sleep(sc) ||
1760                              (sc->ps_flags & (PS_WAIT_FOR_BEACON |
1761                                               PS_WAIT_FOR_CAB |
1762                                               PS_WAIT_FOR_PSPOLL_DATA))))
1763                         ath_rx_ps(sc, skb);
1764                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1765
1766                 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
1767                         ath_ant_comb_scan(sc, &rs);
1768
1769                 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
1770
1771 requeue:
1772                 if (edma) {
1773                         list_add_tail(&bf->list, &sc->rx.rxbuf);
1774                         ath_rx_edma_buf_link(sc, qtype);
1775                 } else {
1776                         list_move_tail(&bf->list, &sc->rx.rxbuf);
1777                         ath_rx_buf_link(sc, bf);
1778                 }
1779         } while (1);
1780
1781         spin_unlock_bh(&sc->rx.rxbuflock);
1782
1783         return 0;
1784 }