8bf2bf36fd6d37833e16f9d047afb062925f06f4
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19
20 #define ATH_PCI_VERSION "0.1"
21
22 static char *dev_info = "ath9k";
23
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
28
29 static int modparam_nohwcrypt;
30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
33 /* We use the hw_value as an index into our private channel structure */
34
35 #define CHAN2G(_freq, _idx)  { \
36         .center_freq = (_freq), \
37         .hw_value = (_idx), \
38         .max_power = 30, \
39 }
40
41 #define CHAN5G(_freq, _idx) { \
42         .band = IEEE80211_BAND_5GHZ, \
43         .center_freq = (_freq), \
44         .hw_value = (_idx), \
45         .max_power = 30, \
46 }
47
48 /* Some 2 GHz radios are actually tunable on 2312-2732
49  * on 5 MHz steps, we support the channels which we know
50  * we have calibration data for all cards though to make
51  * this static */
52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53         CHAN2G(2412, 0), /* Channel 1 */
54         CHAN2G(2417, 1), /* Channel 2 */
55         CHAN2G(2422, 2), /* Channel 3 */
56         CHAN2G(2427, 3), /* Channel 4 */
57         CHAN2G(2432, 4), /* Channel 5 */
58         CHAN2G(2437, 5), /* Channel 6 */
59         CHAN2G(2442, 6), /* Channel 7 */
60         CHAN2G(2447, 7), /* Channel 8 */
61         CHAN2G(2452, 8), /* Channel 9 */
62         CHAN2G(2457, 9), /* Channel 10 */
63         CHAN2G(2462, 10), /* Channel 11 */
64         CHAN2G(2467, 11), /* Channel 12 */
65         CHAN2G(2472, 12), /* Channel 13 */
66         CHAN2G(2484, 13), /* Channel 14 */
67 };
68
69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
70  * on 5 MHz steps, we support the channels which we know
71  * we have calibration data for all cards though to make
72  * this static */
73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74         /* _We_ call this UNII 1 */
75         CHAN5G(5180, 14), /* Channel 36 */
76         CHAN5G(5200, 15), /* Channel 40 */
77         CHAN5G(5220, 16), /* Channel 44 */
78         CHAN5G(5240, 17), /* Channel 48 */
79         /* _We_ call this UNII 2 */
80         CHAN5G(5260, 18), /* Channel 52 */
81         CHAN5G(5280, 19), /* Channel 56 */
82         CHAN5G(5300, 20), /* Channel 60 */
83         CHAN5G(5320, 21), /* Channel 64 */
84         /* _We_ call this "Middle band" */
85         CHAN5G(5500, 22), /* Channel 100 */
86         CHAN5G(5520, 23), /* Channel 104 */
87         CHAN5G(5540, 24), /* Channel 108 */
88         CHAN5G(5560, 25), /* Channel 112 */
89         CHAN5G(5580, 26), /* Channel 116 */
90         CHAN5G(5600, 27), /* Channel 120 */
91         CHAN5G(5620, 28), /* Channel 124 */
92         CHAN5G(5640, 29), /* Channel 128 */
93         CHAN5G(5660, 30), /* Channel 132 */
94         CHAN5G(5680, 31), /* Channel 136 */
95         CHAN5G(5700, 32), /* Channel 140 */
96         /* _We_ call this UNII 3 */
97         CHAN5G(5745, 33), /* Channel 149 */
98         CHAN5G(5765, 34), /* Channel 153 */
99         CHAN5G(5785, 35), /* Channel 157 */
100         CHAN5G(5805, 36), /* Channel 161 */
101         CHAN5G(5825, 37), /* Channel 165 */
102 };
103
104 static void ath_cache_conf_rate(struct ath_softc *sc,
105                                 struct ieee80211_conf *conf)
106 {
107         switch (conf->channel->band) {
108         case IEEE80211_BAND_2GHZ:
109                 if (conf_is_ht20(conf))
110                         sc->cur_rate_table =
111                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112                 else if (conf_is_ht40_minus(conf))
113                         sc->cur_rate_table =
114                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115                 else if (conf_is_ht40_plus(conf))
116                         sc->cur_rate_table =
117                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
118                 else
119                         sc->cur_rate_table =
120                           sc->hw_rate_table[ATH9K_MODE_11G];
121                 break;
122         case IEEE80211_BAND_5GHZ:
123                 if (conf_is_ht20(conf))
124                         sc->cur_rate_table =
125                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126                 else if (conf_is_ht40_minus(conf))
127                         sc->cur_rate_table =
128                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129                 else if (conf_is_ht40_plus(conf))
130                         sc->cur_rate_table =
131                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132                 else
133                         sc->cur_rate_table =
134                           sc->hw_rate_table[ATH9K_MODE_11A];
135                 break;
136         default:
137                 BUG_ON(1);
138                 break;
139         }
140 }
141
142 static void ath_update_txpow(struct ath_softc *sc)
143 {
144         struct ath_hw *ah = sc->sc_ah;
145         u32 txpow;
146
147         if (sc->curtxpow != sc->config.txpowlimit) {
148                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
149                 /* read back in case value is clamped */
150                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
151                 sc->curtxpow = txpow;
152         }
153 }
154
155 static u8 parse_mpdudensity(u8 mpdudensity)
156 {
157         /*
158          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159          *   0 for no restriction
160          *   1 for 1/4 us
161          *   2 for 1/2 us
162          *   3 for 1 us
163          *   4 for 2 us
164          *   5 for 4 us
165          *   6 for 8 us
166          *   7 for 16 us
167          */
168         switch (mpdudensity) {
169         case 0:
170                 return 0;
171         case 1:
172         case 2:
173         case 3:
174                 /* Our lower layer calculations limit our precision to
175                    1 microsecond */
176                 return 1;
177         case 4:
178                 return 2;
179         case 5:
180                 return 4;
181         case 6:
182                 return 8;
183         case 7:
184                 return 16;
185         default:
186                 return 0;
187         }
188 }
189
190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191 {
192         struct ath_rate_table *rate_table = NULL;
193         struct ieee80211_supported_band *sband;
194         struct ieee80211_rate *rate;
195         int i, maxrates;
196
197         switch (band) {
198         case IEEE80211_BAND_2GHZ:
199                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200                 break;
201         case IEEE80211_BAND_5GHZ:
202                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203                 break;
204         default:
205                 break;
206         }
207
208         if (rate_table == NULL)
209                 return;
210
211         sband = &sc->sbands[band];
212         rate = sc->rates[band];
213
214         if (rate_table->rate_cnt > ATH_RATE_MAX)
215                 maxrates = ATH_RATE_MAX;
216         else
217                 maxrates = rate_table->rate_cnt;
218
219         for (i = 0; i < maxrates; i++) {
220                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221                 rate[i].hw_value = rate_table->info[i].ratecode;
222                 if (rate_table->info[i].short_preamble) {
223                         rate[i].hw_value_short = rate_table->info[i].ratecode |
224                                 rate_table->info[i].short_preamble;
225                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226                 }
227                 sband->n_bitrates++;
228
229                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230                         rate[i].bitrate / 10, rate[i].hw_value);
231         }
232 }
233
234 /*
235  * Set/change channels.  If the channel is really being changed, it's done
236  * by reseting the chip.  To accomplish this we must first cleanup any pending
237  * DMA, then restart stuff.
238 */
239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240                     struct ath9k_channel *hchan)
241 {
242         struct ath_hw *ah = sc->sc_ah;
243         bool fastcc = true, stopped;
244         struct ieee80211_channel *channel = hw->conf.channel;
245         int r;
246
247         if (sc->sc_flags & SC_OP_INVALID)
248                 return -EIO;
249
250         ath9k_ps_wakeup(sc);
251
252         /*
253          * This is only performed if the channel settings have
254          * actually changed.
255          *
256          * To switch channels clear any pending DMA operations;
257          * wait long enough for the RX fifo to drain, reset the
258          * hardware at the new frequency, and then re-enable
259          * the relevant bits of the h/w.
260          */
261         ath9k_hw_set_interrupts(ah, 0);
262         ath_drain_all_txq(sc, false);
263         stopped = ath_stoprecv(sc);
264
265         /* XXX: do not flush receive queue here. We don't want
266          * to flush data frames already in queue because of
267          * changing channel. */
268
269         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270                 fastcc = false;
271
272         DPRINTF(sc, ATH_DBG_CONFIG,
273                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
274                 sc->sc_ah->curchan->channel,
275                 channel->center_freq, sc->tx_chan_width);
276
277         spin_lock_bh(&sc->sc_resetlock);
278
279         r = ath9k_hw_reset(ah, hchan, fastcc);
280         if (r) {
281                 DPRINTF(sc, ATH_DBG_FATAL,
282                         "Unable to reset channel (%u Mhz) "
283                         "reset status %u\n",
284                         channel->center_freq, r);
285                 spin_unlock_bh(&sc->sc_resetlock);
286                 return r;
287         }
288         spin_unlock_bh(&sc->sc_resetlock);
289
290         sc->sc_flags &= ~SC_OP_FULL_RESET;
291
292         if (ath_startrecv(sc) != 0) {
293                 DPRINTF(sc, ATH_DBG_FATAL,
294                         "Unable to restart recv logic\n");
295                 return -EIO;
296         }
297
298         ath_cache_conf_rate(sc, &hw->conf);
299         ath_update_txpow(sc);
300         ath9k_hw_set_interrupts(ah, sc->imask);
301         ath9k_ps_restore(sc);
302         return 0;
303 }
304
305 /*
306  *  This routine performs the periodic noise floor calibration function
307  *  that is used to adjust and optimize the chip performance.  This
308  *  takes environmental changes (location, temperature) into account.
309  *  When the task is complete, it reschedules itself depending on the
310  *  appropriate interval that was calculated.
311  */
312 static void ath_ani_calibrate(unsigned long data)
313 {
314         struct ath_softc *sc = (struct ath_softc *)data;
315         struct ath_hw *ah = sc->sc_ah;
316         bool longcal = false;
317         bool shortcal = false;
318         bool aniflag = false;
319         unsigned int timestamp = jiffies_to_msecs(jiffies);
320         u32 cal_interval, short_cal_interval;
321
322         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
323                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
324
325         /*
326         * don't calibrate when we're scanning.
327         * we are most likely not on our home channel.
328         */
329         if (sc->sc_flags & SC_OP_SCANNING)
330                 goto set_timer;
331
332         /* Long calibration runs independently of short calibration. */
333         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
334                 longcal = true;
335                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
336                 sc->ani.longcal_timer = timestamp;
337         }
338
339         /* Short calibration applies only while caldone is false */
340         if (!sc->ani.caldone) {
341                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
342                         shortcal = true;
343                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
344                         sc->ani.shortcal_timer = timestamp;
345                         sc->ani.resetcal_timer = timestamp;
346                 }
347         } else {
348                 if ((timestamp - sc->ani.resetcal_timer) >=
349                     ATH_RESTART_CALINTERVAL) {
350                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
351                         if (sc->ani.caldone)
352                                 sc->ani.resetcal_timer = timestamp;
353                 }
354         }
355
356         /* Verify whether we must check ANI */
357         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
358                 aniflag = true;
359                 sc->ani.checkani_timer = timestamp;
360         }
361
362         /* Skip all processing if there's nothing to do. */
363         if (longcal || shortcal || aniflag) {
364                 /* Call ANI routine if necessary */
365                 if (aniflag)
366                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
367
368                 /* Perform calibration if necessary */
369                 if (longcal || shortcal) {
370                         sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
371                                                      sc->rx_chainmask, longcal);
372
373                         if (longcal)
374                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
375                                                                      ah->curchan);
376
377                         DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
378                                 ah->curchan->channel, ah->curchan->channelFlags,
379                                 sc->ani.noise_floor);
380                 }
381         }
382
383 set_timer:
384         /*
385         * Set timer interval based on previous results.
386         * The interval must be the shortest necessary to satisfy ANI,
387         * short calibration and long calibration.
388         */
389         cal_interval = ATH_LONG_CALINTERVAL;
390         if (sc->sc_ah->config.enable_ani)
391                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
392         if (!sc->ani.caldone)
393                 cal_interval = min(cal_interval, (u32)short_cal_interval);
394
395         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
396 }
397
398 static void ath_start_ani(struct ath_softc *sc)
399 {
400         unsigned long timestamp = jiffies_to_msecs(jiffies);
401
402         sc->ani.longcal_timer = timestamp;
403         sc->ani.shortcal_timer = timestamp;
404         sc->ani.checkani_timer = timestamp;
405
406         mod_timer(&sc->ani.timer,
407                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
408 }
409
410 /*
411  * Update tx/rx chainmask. For legacy association,
412  * hard code chainmask to 1x1, for 11n association, use
413  * the chainmask configuration, for bt coexistence, use
414  * the chainmask configuration even in legacy mode.
415  */
416 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
417 {
418         if (is_ht ||
419             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
422         } else {
423                 sc->tx_chainmask = 1;
424                 sc->rx_chainmask = 1;
425         }
426
427         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
428                 sc->tx_chainmask, sc->rx_chainmask);
429 }
430
431 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
432 {
433         struct ath_node *an;
434
435         an = (struct ath_node *)sta->drv_priv;
436
437         if (sc->sc_flags & SC_OP_TXAGGR) {
438                 ath_tx_node_init(sc, an);
439                 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
440                                      sta->ht_cap.ampdu_factor);
441                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
442         }
443 }
444
445 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
446 {
447         struct ath_node *an = (struct ath_node *)sta->drv_priv;
448
449         if (sc->sc_flags & SC_OP_TXAGGR)
450                 ath_tx_node_cleanup(sc, an);
451 }
452
453 static void ath9k_tasklet(unsigned long data)
454 {
455         struct ath_softc *sc = (struct ath_softc *)data;
456         u32 status = sc->intrstatus;
457
458         if (status & ATH9K_INT_FATAL) {
459                 ath_reset(sc, false);
460                 return;
461         }
462
463         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
464                 spin_lock_bh(&sc->rx.rxflushlock);
465                 ath_rx_tasklet(sc, 0);
466                 spin_unlock_bh(&sc->rx.rxflushlock);
467         }
468
469         if (status & ATH9K_INT_TX)
470                 ath_tx_tasklet(sc);
471
472         /* re-enable hardware interrupt */
473         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
474 }
475
476 irqreturn_t ath_isr(int irq, void *dev)
477 {
478 #define SCHED_INTR (                            \
479                 ATH9K_INT_FATAL |               \
480                 ATH9K_INT_RXORN |               \
481                 ATH9K_INT_RXEOL |               \
482                 ATH9K_INT_RX |                  \
483                 ATH9K_INT_TX |                  \
484                 ATH9K_INT_BMISS |               \
485                 ATH9K_INT_CST |                 \
486                 ATH9K_INT_TSFOOR)
487
488         struct ath_softc *sc = dev;
489         struct ath_hw *ah = sc->sc_ah;
490         enum ath9k_int status;
491         bool sched = false;
492
493         /*
494          * The hardware is not ready/present, don't
495          * touch anything. Note this can happen early
496          * on if the IRQ is shared.
497          */
498         if (sc->sc_flags & SC_OP_INVALID)
499                 return IRQ_NONE;
500
501         ath9k_ps_wakeup(sc);
502
503         /* shared irq, not for us */
504
505         if (!ath9k_hw_intrpend(ah)) {
506                 ath9k_ps_restore(sc);
507                 return IRQ_NONE;
508         }
509
510         /*
511          * Figure out the reason(s) for the interrupt.  Note
512          * that the hal returns a pseudo-ISR that may include
513          * bits we haven't explicitly enabled so we mask the
514          * value to insure we only process bits we requested.
515          */
516         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
517         status &= sc->imask;    /* discard unasked-for bits */
518
519         /*
520          * If there are no status bits set, then this interrupt was not
521          * for me (should have been caught above).
522          */
523         if (!status) {
524                 ath9k_ps_restore(sc);
525                 return IRQ_NONE;
526         }
527
528         /* Cache the status */
529         sc->intrstatus = status;
530
531         if (status & SCHED_INTR)
532                 sched = true;
533
534         /*
535          * If a FATAL or RXORN interrupt is received, we have to reset the
536          * chip immediately.
537          */
538         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
539                 goto chip_reset;
540
541         if (status & ATH9K_INT_SWBA)
542                 tasklet_schedule(&sc->bcon_tasklet);
543
544         if (status & ATH9K_INT_TXURN)
545                 ath9k_hw_updatetxtriglevel(ah, true);
546
547         if (status & ATH9K_INT_MIB) {
548                 /*
549                  * Disable interrupts until we service the MIB
550                  * interrupt; otherwise it will continue to
551                  * fire.
552                  */
553                 ath9k_hw_set_interrupts(ah, 0);
554                 /*
555                  * Let the hal handle the event. We assume
556                  * it will clear whatever condition caused
557                  * the interrupt.
558                  */
559                 ath9k_hw_procmibevent(ah, &sc->nodestats);
560                 ath9k_hw_set_interrupts(ah, sc->imask);
561         }
562
563         if (status & ATH9K_INT_TIM_TIMER) {
564                 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
565                         /* Clear RxAbort bit so that we can
566                          * receive frames */
567                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
568                         ath9k_hw_setrxabort(ah, 0);
569                         sched = true;
570                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
571                 }
572         }
573
574 chip_reset:
575
576         ath9k_ps_restore(sc);
577         ath_debug_stat_interrupt(sc, status);
578
579         if (sched) {
580                 /* turn off every interrupt except SWBA */
581                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
582                 tasklet_schedule(&sc->intr_tq);
583         }
584
585         return IRQ_HANDLED;
586
587 #undef SCHED_INTR
588 }
589
590 static u32 ath_get_extchanmode(struct ath_softc *sc,
591                                struct ieee80211_channel *chan,
592                                enum nl80211_channel_type channel_type)
593 {
594         u32 chanmode = 0;
595
596         switch (chan->band) {
597         case IEEE80211_BAND_2GHZ:
598                 switch(channel_type) {
599                 case NL80211_CHAN_NO_HT:
600                 case NL80211_CHAN_HT20:
601                         chanmode = CHANNEL_G_HT20;
602                         break;
603                 case NL80211_CHAN_HT40PLUS:
604                         chanmode = CHANNEL_G_HT40PLUS;
605                         break;
606                 case NL80211_CHAN_HT40MINUS:
607                         chanmode = CHANNEL_G_HT40MINUS;
608                         break;
609                 }
610                 break;
611         case IEEE80211_BAND_5GHZ:
612                 switch(channel_type) {
613                 case NL80211_CHAN_NO_HT:
614                 case NL80211_CHAN_HT20:
615                         chanmode = CHANNEL_A_HT20;
616                         break;
617                 case NL80211_CHAN_HT40PLUS:
618                         chanmode = CHANNEL_A_HT40PLUS;
619                         break;
620                 case NL80211_CHAN_HT40MINUS:
621                         chanmode = CHANNEL_A_HT40MINUS;
622                         break;
623                 }
624                 break;
625         default:
626                 break;
627         }
628
629         return chanmode;
630 }
631
632 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
633                            struct ath9k_keyval *hk, const u8 *addr,
634                            bool authenticator)
635 {
636         const u8 *key_rxmic;
637         const u8 *key_txmic;
638
639         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
640         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
641
642         if (addr == NULL) {
643                 /*
644                  * Group key installation - only two key cache entries are used
645                  * regardless of splitmic capability since group key is only
646                  * used either for TX or RX.
647                  */
648                 if (authenticator) {
649                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
650                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
651                 } else {
652                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
653                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
654                 }
655                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
656         }
657         if (!sc->splitmic) {
658                 /* TX and RX keys share the same key cache entry. */
659                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
660                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
661                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
662         }
663
664         /* Separate key cache entries for TX and RX */
665
666         /* TX key goes at first index, RX key at +32. */
667         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
668         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
669                 /* TX MIC entry failed. No need to proceed further */
670                 DPRINTF(sc, ATH_DBG_FATAL,
671                         "Setting TX MIC Key Failed\n");
672                 return 0;
673         }
674
675         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
676         /* XXX delete tx key on failure? */
677         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
678 }
679
680 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
681 {
682         int i;
683
684         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
685                 if (test_bit(i, sc->keymap) ||
686                     test_bit(i + 64, sc->keymap))
687                         continue; /* At least one part of TKIP key allocated */
688                 if (sc->splitmic &&
689                     (test_bit(i + 32, sc->keymap) ||
690                      test_bit(i + 64 + 32, sc->keymap)))
691                         continue; /* At least one part of TKIP key allocated */
692
693                 /* Found a free slot for a TKIP key */
694                 return i;
695         }
696         return -1;
697 }
698
699 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
700 {
701         int i;
702
703         /* First, try to find slots that would not be available for TKIP. */
704         if (sc->splitmic) {
705                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
706                         if (!test_bit(i, sc->keymap) &&
707                             (test_bit(i + 32, sc->keymap) ||
708                              test_bit(i + 64, sc->keymap) ||
709                              test_bit(i + 64 + 32, sc->keymap)))
710                                 return i;
711                         if (!test_bit(i + 32, sc->keymap) &&
712                             (test_bit(i, sc->keymap) ||
713                              test_bit(i + 64, sc->keymap) ||
714                              test_bit(i + 64 + 32, sc->keymap)))
715                                 return i + 32;
716                         if (!test_bit(i + 64, sc->keymap) &&
717                             (test_bit(i , sc->keymap) ||
718                              test_bit(i + 32, sc->keymap) ||
719                              test_bit(i + 64 + 32, sc->keymap)))
720                                 return i + 64;
721                         if (!test_bit(i + 64 + 32, sc->keymap) &&
722                             (test_bit(i, sc->keymap) ||
723                              test_bit(i + 32, sc->keymap) ||
724                              test_bit(i + 64, sc->keymap)))
725                                 return i + 64 + 32;
726                 }
727         } else {
728                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
729                         if (!test_bit(i, sc->keymap) &&
730                             test_bit(i + 64, sc->keymap))
731                                 return i;
732                         if (test_bit(i, sc->keymap) &&
733                             !test_bit(i + 64, sc->keymap))
734                                 return i + 64;
735                 }
736         }
737
738         /* No partially used TKIP slots, pick any available slot */
739         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
740                 /* Do not allow slots that could be needed for TKIP group keys
741                  * to be used. This limitation could be removed if we know that
742                  * TKIP will not be used. */
743                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
744                         continue;
745                 if (sc->splitmic) {
746                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
747                                 continue;
748                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
749                                 continue;
750                 }
751
752                 if (!test_bit(i, sc->keymap))
753                         return i; /* Found a free slot for a key */
754         }
755
756         /* No free slot found */
757         return -1;
758 }
759
760 static int ath_key_config(struct ath_softc *sc,
761                           struct ieee80211_vif *vif,
762                           struct ieee80211_sta *sta,
763                           struct ieee80211_key_conf *key)
764 {
765         struct ath9k_keyval hk;
766         const u8 *mac = NULL;
767         int ret = 0;
768         int idx;
769
770         memset(&hk, 0, sizeof(hk));
771
772         switch (key->alg) {
773         case ALG_WEP:
774                 hk.kv_type = ATH9K_CIPHER_WEP;
775                 break;
776         case ALG_TKIP:
777                 hk.kv_type = ATH9K_CIPHER_TKIP;
778                 break;
779         case ALG_CCMP:
780                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
781                 break;
782         default:
783                 return -EOPNOTSUPP;
784         }
785
786         hk.kv_len = key->keylen;
787         memcpy(hk.kv_val, key->key, key->keylen);
788
789         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
790                 /* For now, use the default keys for broadcast keys. This may
791                  * need to change with virtual interfaces. */
792                 idx = key->keyidx;
793         } else if (key->keyidx) {
794                 if (WARN_ON(!sta))
795                         return -EOPNOTSUPP;
796                 mac = sta->addr;
797
798                 if (vif->type != NL80211_IFTYPE_AP) {
799                         /* Only keyidx 0 should be used with unicast key, but
800                          * allow this for client mode for now. */
801                         idx = key->keyidx;
802                 } else
803                         return -EIO;
804         } else {
805                 if (WARN_ON(!sta))
806                         return -EOPNOTSUPP;
807                 mac = sta->addr;
808
809                 if (key->alg == ALG_TKIP)
810                         idx = ath_reserve_key_cache_slot_tkip(sc);
811                 else
812                         idx = ath_reserve_key_cache_slot(sc);
813                 if (idx < 0)
814                         return -ENOSPC; /* no free key cache entries */
815         }
816
817         if (key->alg == ALG_TKIP)
818                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
819                                       vif->type == NL80211_IFTYPE_AP);
820         else
821                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
822
823         if (!ret)
824                 return -EIO;
825
826         set_bit(idx, sc->keymap);
827         if (key->alg == ALG_TKIP) {
828                 set_bit(idx + 64, sc->keymap);
829                 if (sc->splitmic) {
830                         set_bit(idx + 32, sc->keymap);
831                         set_bit(idx + 64 + 32, sc->keymap);
832                 }
833         }
834
835         return idx;
836 }
837
838 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
839 {
840         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
841         if (key->hw_key_idx < IEEE80211_WEP_NKID)
842                 return;
843
844         clear_bit(key->hw_key_idx, sc->keymap);
845         if (key->alg != ALG_TKIP)
846                 return;
847
848         clear_bit(key->hw_key_idx + 64, sc->keymap);
849         if (sc->splitmic) {
850                 clear_bit(key->hw_key_idx + 32, sc->keymap);
851                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
852         }
853 }
854
855 static void setup_ht_cap(struct ath_softc *sc,
856                          struct ieee80211_sta_ht_cap *ht_info)
857 {
858 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
859 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
860
861         ht_info->ht_supported = true;
862         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
863                        IEEE80211_HT_CAP_SM_PS |
864                        IEEE80211_HT_CAP_SGI_40 |
865                        IEEE80211_HT_CAP_DSSSCCK40;
866
867         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
868         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
869
870         /* set up supported mcs set */
871         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
872
873         switch(sc->rx_chainmask) {
874         case 1:
875                 ht_info->mcs.rx_mask[0] = 0xff;
876                 break;
877         case 3:
878         case 5:
879         case 7:
880         default:
881                 ht_info->mcs.rx_mask[0] = 0xff;
882                 ht_info->mcs.rx_mask[1] = 0xff;
883                 break;
884         }
885
886         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
887 }
888
889 static void ath9k_bss_assoc_info(struct ath_softc *sc,
890                                  struct ieee80211_vif *vif,
891                                  struct ieee80211_bss_conf *bss_conf)
892 {
893         struct ath_vif *avp = (void *)vif->drv_priv;
894
895         if (bss_conf->assoc) {
896                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
897                         bss_conf->aid, sc->curbssid);
898
899                 /* New association, store aid */
900                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
901                         sc->curaid = bss_conf->aid;
902                         ath9k_hw_write_associd(sc);
903                 }
904
905                 /* Configure the beacon */
906                 ath_beacon_config(sc, vif);
907
908                 /* Reset rssi stats */
909                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
910                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
911                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
912                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
913
914                 ath_start_ani(sc);
915         } else {
916                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
917                 sc->curaid = 0;
918         }
919 }
920
921 /********************************/
922 /*       LED functions          */
923 /********************************/
924
925 static void ath_led_blink_work(struct work_struct *work)
926 {
927         struct ath_softc *sc = container_of(work, struct ath_softc,
928                                             ath_led_blink_work.work);
929
930         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
931                 return;
932
933         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
934             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
935                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
936         else
937                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
938                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
939
940         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
941                            (sc->sc_flags & SC_OP_LED_ON) ?
942                            msecs_to_jiffies(sc->led_off_duration) :
943                            msecs_to_jiffies(sc->led_on_duration));
944
945         sc->led_on_duration = sc->led_on_cnt ?
946                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
947                         ATH_LED_ON_DURATION_IDLE;
948         sc->led_off_duration = sc->led_off_cnt ?
949                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
950                         ATH_LED_OFF_DURATION_IDLE;
951         sc->led_on_cnt = sc->led_off_cnt = 0;
952         if (sc->sc_flags & SC_OP_LED_ON)
953                 sc->sc_flags &= ~SC_OP_LED_ON;
954         else
955                 sc->sc_flags |= SC_OP_LED_ON;
956 }
957
958 static void ath_led_brightness(struct led_classdev *led_cdev,
959                                enum led_brightness brightness)
960 {
961         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
962         struct ath_softc *sc = led->sc;
963
964         switch (brightness) {
965         case LED_OFF:
966                 if (led->led_type == ATH_LED_ASSOC ||
967                     led->led_type == ATH_LED_RADIO) {
968                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
969                                 (led->led_type == ATH_LED_RADIO));
970                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
971                         if (led->led_type == ATH_LED_RADIO)
972                                 sc->sc_flags &= ~SC_OP_LED_ON;
973                 } else {
974                         sc->led_off_cnt++;
975                 }
976                 break;
977         case LED_FULL:
978                 if (led->led_type == ATH_LED_ASSOC) {
979                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
980                         queue_delayed_work(sc->hw->workqueue,
981                                            &sc->ath_led_blink_work, 0);
982                 } else if (led->led_type == ATH_LED_RADIO) {
983                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
984                         sc->sc_flags |= SC_OP_LED_ON;
985                 } else {
986                         sc->led_on_cnt++;
987                 }
988                 break;
989         default:
990                 break;
991         }
992 }
993
994 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
995                             char *trigger)
996 {
997         int ret;
998
999         led->sc = sc;
1000         led->led_cdev.name = led->name;
1001         led->led_cdev.default_trigger = trigger;
1002         led->led_cdev.brightness_set = ath_led_brightness;
1003
1004         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1005         if (ret)
1006                 DPRINTF(sc, ATH_DBG_FATAL,
1007                         "Failed to register led:%s", led->name);
1008         else
1009                 led->registered = 1;
1010         return ret;
1011 }
1012
1013 static void ath_unregister_led(struct ath_led *led)
1014 {
1015         if (led->registered) {
1016                 led_classdev_unregister(&led->led_cdev);
1017                 led->registered = 0;
1018         }
1019 }
1020
1021 static void ath_deinit_leds(struct ath_softc *sc)
1022 {
1023         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1024         ath_unregister_led(&sc->assoc_led);
1025         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1026         ath_unregister_led(&sc->tx_led);
1027         ath_unregister_led(&sc->rx_led);
1028         ath_unregister_led(&sc->radio_led);
1029         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1030 }
1031
1032 static void ath_init_leds(struct ath_softc *sc)
1033 {
1034         char *trigger;
1035         int ret;
1036
1037         /* Configure gpio 1 for output */
1038         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1039                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1040         /* LED off, active low */
1041         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1042
1043         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1044
1045         trigger = ieee80211_get_radio_led_name(sc->hw);
1046         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1047                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1048         ret = ath_register_led(sc, &sc->radio_led, trigger);
1049         sc->radio_led.led_type = ATH_LED_RADIO;
1050         if (ret)
1051                 goto fail;
1052
1053         trigger = ieee80211_get_assoc_led_name(sc->hw);
1054         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1055                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1056         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1057         sc->assoc_led.led_type = ATH_LED_ASSOC;
1058         if (ret)
1059                 goto fail;
1060
1061         trigger = ieee80211_get_tx_led_name(sc->hw);
1062         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1063                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1064         ret = ath_register_led(sc, &sc->tx_led, trigger);
1065         sc->tx_led.led_type = ATH_LED_TX;
1066         if (ret)
1067                 goto fail;
1068
1069         trigger = ieee80211_get_rx_led_name(sc->hw);
1070         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1071                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1072         ret = ath_register_led(sc, &sc->rx_led, trigger);
1073         sc->rx_led.led_type = ATH_LED_RX;
1074         if (ret)
1075                 goto fail;
1076
1077         return;
1078
1079 fail:
1080         ath_deinit_leds(sc);
1081 }
1082
1083 void ath_radio_enable(struct ath_softc *sc)
1084 {
1085         struct ath_hw *ah = sc->sc_ah;
1086         struct ieee80211_channel *channel = sc->hw->conf.channel;
1087         int r;
1088
1089         ath9k_ps_wakeup(sc);
1090         ath9k_hw_configpcipowersave(ah, 0);
1091
1092         spin_lock_bh(&sc->sc_resetlock);
1093         r = ath9k_hw_reset(ah, ah->curchan, false);
1094         if (r) {
1095                 DPRINTF(sc, ATH_DBG_FATAL,
1096                         "Unable to reset channel %u (%uMhz) ",
1097                         "reset status %u\n",
1098                         channel->center_freq, r);
1099         }
1100         spin_unlock_bh(&sc->sc_resetlock);
1101
1102         ath_update_txpow(sc);
1103         if (ath_startrecv(sc) != 0) {
1104                 DPRINTF(sc, ATH_DBG_FATAL,
1105                         "Unable to restart recv logic\n");
1106                 return;
1107         }
1108
1109         if (sc->sc_flags & SC_OP_BEACONS)
1110                 ath_beacon_config(sc, NULL);    /* restart beacons */
1111
1112         /* Re-Enable  interrupts */
1113         ath9k_hw_set_interrupts(ah, sc->imask);
1114
1115         /* Enable LED */
1116         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1117                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1118         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1119
1120         ieee80211_wake_queues(sc->hw);
1121         ath9k_ps_restore(sc);
1122 }
1123
1124 void ath_radio_disable(struct ath_softc *sc)
1125 {
1126         struct ath_hw *ah = sc->sc_ah;
1127         struct ieee80211_channel *channel = sc->hw->conf.channel;
1128         int r;
1129
1130         ath9k_ps_wakeup(sc);
1131         ieee80211_stop_queues(sc->hw);
1132
1133         /* Disable LED */
1134         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1135         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1136
1137         /* Disable interrupts */
1138         ath9k_hw_set_interrupts(ah, 0);
1139
1140         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1141         ath_stoprecv(sc);               /* turn off frame recv */
1142         ath_flushrecv(sc);              /* flush recv queue */
1143
1144         spin_lock_bh(&sc->sc_resetlock);
1145         r = ath9k_hw_reset(ah, ah->curchan, false);
1146         if (r) {
1147                 DPRINTF(sc, ATH_DBG_FATAL,
1148                         "Unable to reset channel %u (%uMhz) "
1149                         "reset status %u\n",
1150                         channel->center_freq, r);
1151         }
1152         spin_unlock_bh(&sc->sc_resetlock);
1153
1154         ath9k_hw_phy_disable(ah);
1155         ath9k_hw_configpcipowersave(ah, 1);
1156         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1157         ath9k_ps_restore(sc);
1158 }
1159
1160 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1161
1162 /*******************/
1163 /*      Rfkill     */
1164 /*******************/
1165
1166 static bool ath_is_rfkill_set(struct ath_softc *sc)
1167 {
1168         struct ath_hw *ah = sc->sc_ah;
1169
1170         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1171                                   ah->rfkill_polarity;
1172 }
1173
1174 /* h/w rfkill poll function */
1175 static void ath_rfkill_poll(struct work_struct *work)
1176 {
1177         struct ath_softc *sc = container_of(work, struct ath_softc,
1178                                             rf_kill.rfkill_poll.work);
1179         bool radio_on;
1180
1181         if (sc->sc_flags & SC_OP_INVALID)
1182                 return;
1183
1184         radio_on = !ath_is_rfkill_set(sc);
1185
1186         /*
1187          * enable/disable radio only when there is a
1188          * state change in RF switch
1189          */
1190         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1191                 enum rfkill_state state;
1192
1193                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1194                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1195                                 : RFKILL_STATE_HARD_BLOCKED;
1196                 } else if (radio_on) {
1197                         ath_radio_enable(sc);
1198                         state = RFKILL_STATE_UNBLOCKED;
1199                 } else {
1200                         ath_radio_disable(sc);
1201                         state = RFKILL_STATE_HARD_BLOCKED;
1202                 }
1203
1204                 if (state == RFKILL_STATE_HARD_BLOCKED)
1205                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1206                 else
1207                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1208
1209                 rfkill_force_state(sc->rf_kill.rfkill, state);
1210         }
1211
1212         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1213                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1214 }
1215
1216 /* s/w rfkill handler */
1217 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1218 {
1219         struct ath_softc *sc = data;
1220
1221         switch (state) {
1222         case RFKILL_STATE_SOFT_BLOCKED:
1223                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1224                     SC_OP_RFKILL_SW_BLOCKED)))
1225                         ath_radio_disable(sc);
1226                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1227                 return 0;
1228         case RFKILL_STATE_UNBLOCKED:
1229                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1230                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1231                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1232                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1233                                         "radio as it is disabled by h/w\n");
1234                                 return -EPERM;
1235                         }
1236                         ath_radio_enable(sc);
1237                 }
1238                 return 0;
1239         default:
1240                 return -EINVAL;
1241         }
1242 }
1243
1244 /* Init s/w rfkill */
1245 static int ath_init_sw_rfkill(struct ath_softc *sc)
1246 {
1247         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1248                                              RFKILL_TYPE_WLAN);
1249         if (!sc->rf_kill.rfkill) {
1250                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1251                 return -ENOMEM;
1252         }
1253
1254         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1255                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1256         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1257         sc->rf_kill.rfkill->data = sc;
1258         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1259         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1260
1261         return 0;
1262 }
1263
1264 /* Deinitialize rfkill */
1265 static void ath_deinit_rfkill(struct ath_softc *sc)
1266 {
1267         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1268                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1269
1270         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1271                 rfkill_unregister(sc->rf_kill.rfkill);
1272                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1273                 sc->rf_kill.rfkill = NULL;
1274         }
1275 }
1276
1277 static int ath_start_rfkill_poll(struct ath_softc *sc)
1278 {
1279         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1280                 queue_delayed_work(sc->hw->workqueue,
1281                                    &sc->rf_kill.rfkill_poll, 0);
1282
1283         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1284                 if (rfkill_register(sc->rf_kill.rfkill)) {
1285                         DPRINTF(sc, ATH_DBG_FATAL,
1286                                 "Unable to register rfkill\n");
1287                         rfkill_free(sc->rf_kill.rfkill);
1288
1289                         /* Deinitialize the device */
1290                         ath_cleanup(sc);
1291                         return -EIO;
1292                 } else {
1293                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1294                 }
1295         }
1296
1297         return 0;
1298 }
1299 #endif /* CONFIG_RFKILL */
1300
1301 void ath_cleanup(struct ath_softc *sc)
1302 {
1303         ath_detach(sc);
1304         free_irq(sc->irq, sc);
1305         ath_bus_cleanup(sc);
1306         kfree(sc->sec_wiphy);
1307         ieee80211_free_hw(sc->hw);
1308 }
1309
1310 void ath_detach(struct ath_softc *sc)
1311 {
1312         struct ieee80211_hw *hw = sc->hw;
1313         int i = 0;
1314
1315         ath9k_ps_wakeup(sc);
1316
1317         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1318
1319 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1320         ath_deinit_rfkill(sc);
1321 #endif
1322         ath_deinit_leds(sc);
1323         cancel_work_sync(&sc->chan_work);
1324         cancel_delayed_work_sync(&sc->wiphy_work);
1325
1326         for (i = 0; i < sc->num_sec_wiphy; i++) {
1327                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1328                 if (aphy == NULL)
1329                         continue;
1330                 sc->sec_wiphy[i] = NULL;
1331                 ieee80211_unregister_hw(aphy->hw);
1332                 ieee80211_free_hw(aphy->hw);
1333         }
1334         ieee80211_unregister_hw(hw);
1335         ath_rx_cleanup(sc);
1336         ath_tx_cleanup(sc);
1337
1338         tasklet_kill(&sc->intr_tq);
1339         tasklet_kill(&sc->bcon_tasklet);
1340
1341         if (!(sc->sc_flags & SC_OP_INVALID))
1342                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1343
1344         /* cleanup tx queues */
1345         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1346                 if (ATH_TXQ_SETUP(sc, i))
1347                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1348
1349         ath9k_hw_detach(sc->sc_ah);
1350         ath9k_exit_debug(sc);
1351         ath9k_ps_restore(sc);
1352 }
1353
1354 static int ath9k_reg_notifier(struct wiphy *wiphy,
1355                               struct regulatory_request *request)
1356 {
1357         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1358         struct ath_wiphy *aphy = hw->priv;
1359         struct ath_softc *sc = aphy->sc;
1360         struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1361
1362         return ath_reg_notifier_apply(wiphy, request, reg);
1363 }
1364
1365 static int ath_init(u16 devid, struct ath_softc *sc)
1366 {
1367         struct ath_hw *ah = NULL;
1368         int status;
1369         int error = 0, i;
1370         int csz = 0;
1371
1372         /* XXX: hardware will not be ready until ath_open() being called */
1373         sc->sc_flags |= SC_OP_INVALID;
1374
1375         if (ath9k_init_debug(sc) < 0)
1376                 printk(KERN_ERR "Unable to create debugfs files\n");
1377
1378         spin_lock_init(&sc->wiphy_lock);
1379         spin_lock_init(&sc->sc_resetlock);
1380         spin_lock_init(&sc->sc_serial_rw);
1381         mutex_init(&sc->mutex);
1382         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1383         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1384                      (unsigned long)sc);
1385
1386         /*
1387          * Cache line size is used to size and align various
1388          * structures used to communicate with the hardware.
1389          */
1390         ath_read_cachesize(sc, &csz);
1391         /* XXX assert csz is non-zero */
1392         sc->cachelsz = csz << 2;        /* convert to bytes */
1393
1394         ah = ath9k_hw_attach(devid, sc, &status);
1395         if (ah == NULL) {
1396                 DPRINTF(sc, ATH_DBG_FATAL,
1397                         "Unable to attach hardware; HAL status %d\n", status);
1398                 error = -ENXIO;
1399                 goto bad;
1400         }
1401         sc->sc_ah = ah;
1402
1403         /* Get the hardware key cache size. */
1404         sc->keymax = ah->caps.keycache_size;
1405         if (sc->keymax > ATH_KEYMAX) {
1406                 DPRINTF(sc, ATH_DBG_ANY,
1407                         "Warning, using only %u entries in %u key cache\n",
1408                         ATH_KEYMAX, sc->keymax);
1409                 sc->keymax = ATH_KEYMAX;
1410         }
1411
1412         /*
1413          * Reset the key cache since some parts do not
1414          * reset the contents on initial power up.
1415          */
1416         for (i = 0; i < sc->keymax; i++)
1417                 ath9k_hw_keyreset(ah, (u16) i);
1418
1419         if (ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1420                           ath9k_reg_notifier))
1421                 goto bad;
1422
1423         /* default to MONITOR mode */
1424         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1425
1426         /* Setup rate tables */
1427
1428         ath_rate_attach(sc);
1429         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1430         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1431
1432         /*
1433          * Allocate hardware transmit queues: one queue for
1434          * beacon frames and one data queue for each QoS
1435          * priority.  Note that the hal handles reseting
1436          * these queues at the needed time.
1437          */
1438         sc->beacon.beaconq = ath_beaconq_setup(ah);
1439         if (sc->beacon.beaconq == -1) {
1440                 DPRINTF(sc, ATH_DBG_FATAL,
1441                         "Unable to setup a beacon xmit queue\n");
1442                 error = -EIO;
1443                 goto bad2;
1444         }
1445         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1446         if (sc->beacon.cabq == NULL) {
1447                 DPRINTF(sc, ATH_DBG_FATAL,
1448                         "Unable to setup CAB xmit queue\n");
1449                 error = -EIO;
1450                 goto bad2;
1451         }
1452
1453         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1454         ath_cabq_update(sc);
1455
1456         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1457                 sc->tx.hwq_map[i] = -1;
1458
1459         /* Setup data queues */
1460         /* NB: ensure BK queue is the lowest priority h/w queue */
1461         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1462                 DPRINTF(sc, ATH_DBG_FATAL,
1463                         "Unable to setup xmit queue for BK traffic\n");
1464                 error = -EIO;
1465                 goto bad2;
1466         }
1467
1468         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1469                 DPRINTF(sc, ATH_DBG_FATAL,
1470                         "Unable to setup xmit queue for BE traffic\n");
1471                 error = -EIO;
1472                 goto bad2;
1473         }
1474         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1475                 DPRINTF(sc, ATH_DBG_FATAL,
1476                         "Unable to setup xmit queue for VI traffic\n");
1477                 error = -EIO;
1478                 goto bad2;
1479         }
1480         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1481                 DPRINTF(sc, ATH_DBG_FATAL,
1482                         "Unable to setup xmit queue for VO traffic\n");
1483                 error = -EIO;
1484                 goto bad2;
1485         }
1486
1487         /* Initializes the noise floor to a reasonable default value.
1488          * Later on this will be updated during ANI processing. */
1489
1490         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1491         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1492
1493         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1494                                    ATH9K_CIPHER_TKIP, NULL)) {
1495                 /*
1496                  * Whether we should enable h/w TKIP MIC.
1497                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1498                  * report WMM capable, so it's always safe to turn on
1499                  * TKIP MIC in this case.
1500                  */
1501                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1502                                        0, 1, NULL);
1503         }
1504
1505         /*
1506          * Check whether the separate key cache entries
1507          * are required to handle both tx+rx MIC keys.
1508          * With split mic keys the number of stations is limited
1509          * to 27 otherwise 59.
1510          */
1511         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1512                                    ATH9K_CIPHER_TKIP, NULL)
1513             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1514                                       ATH9K_CIPHER_MIC, NULL)
1515             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1516                                       0, NULL))
1517                 sc->splitmic = 1;
1518
1519         /* turn on mcast key search if possible */
1520         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1521                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1522                                              1, NULL);
1523
1524         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1525
1526         /* 11n Capabilities */
1527         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1528                 sc->sc_flags |= SC_OP_TXAGGR;
1529                 sc->sc_flags |= SC_OP_RXAGGR;
1530         }
1531
1532         sc->tx_chainmask = ah->caps.tx_chainmask;
1533         sc->rx_chainmask = ah->caps.rx_chainmask;
1534
1535         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1536         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1537
1538         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1539                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1540
1541         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1542
1543         /* initialize beacon slots */
1544         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1545                 sc->beacon.bslot[i] = NULL;
1546                 sc->beacon.bslot_aphy[i] = NULL;
1547         }
1548
1549         /* setup channels and rates */
1550
1551         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1552         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1553                 sc->rates[IEEE80211_BAND_2GHZ];
1554         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1555         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1556                 ARRAY_SIZE(ath9k_2ghz_chantable);
1557
1558         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1559                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1560                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1561                         sc->rates[IEEE80211_BAND_5GHZ];
1562                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1563                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1564                         ARRAY_SIZE(ath9k_5ghz_chantable);
1565         }
1566
1567         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1568                 ath9k_hw_btcoex_enable(sc->sc_ah);
1569
1570         return 0;
1571 bad2:
1572         /* cleanup tx queues */
1573         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1574                 if (ATH_TXQ_SETUP(sc, i))
1575                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1576 bad:
1577         if (ah)
1578                 ath9k_hw_detach(ah);
1579         ath9k_exit_debug(sc);
1580
1581         return error;
1582 }
1583
1584 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1585 {
1586         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1587                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1588                 IEEE80211_HW_SIGNAL_DBM |
1589                 IEEE80211_HW_AMPDU_AGGREGATION |
1590                 IEEE80211_HW_SUPPORTS_PS |
1591                 IEEE80211_HW_PS_NULLFUNC_STACK |
1592                 IEEE80211_HW_SPECTRUM_MGMT;
1593
1594         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1595                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1596
1597         hw->wiphy->interface_modes =
1598                 BIT(NL80211_IFTYPE_AP) |
1599                 BIT(NL80211_IFTYPE_STATION) |
1600                 BIT(NL80211_IFTYPE_ADHOC) |
1601                 BIT(NL80211_IFTYPE_MESH_POINT);
1602
1603         hw->queues = 4;
1604         hw->max_rates = 4;
1605         hw->channel_change_time = 5000;
1606         hw->max_listen_interval = 10;
1607         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1608         hw->sta_data_size = sizeof(struct ath_node);
1609         hw->vif_data_size = sizeof(struct ath_vif);
1610
1611         hw->rate_control_algorithm = "ath9k_rate_control";
1612
1613         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1614                 &sc->sbands[IEEE80211_BAND_2GHZ];
1615         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1616                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1617                         &sc->sbands[IEEE80211_BAND_5GHZ];
1618 }
1619
1620 int ath_attach(u16 devid, struct ath_softc *sc)
1621 {
1622         struct ieee80211_hw *hw = sc->hw;
1623         int error = 0, i;
1624         struct ath_regulatory *reg;
1625
1626         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1627
1628         error = ath_init(devid, sc);
1629         if (error != 0)
1630                 return error;
1631
1632         reg = &sc->sc_ah->regulatory;
1633
1634         /* get mac address from hardware and set in mac80211 */
1635
1636         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1637
1638         ath_set_hw_capab(sc, hw);
1639
1640         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1641                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1642                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1643                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1644         }
1645
1646         /* initialize tx/rx engine */
1647         error = ath_tx_init(sc, ATH_TXBUF);
1648         if (error != 0)
1649                 goto error_attach;
1650
1651         error = ath_rx_init(sc, ATH_RXBUF);
1652         if (error != 0)
1653                 goto error_attach;
1654
1655 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1656         /* Initialze h/w Rfkill */
1657         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1658                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1659
1660         /* Initialize s/w rfkill */
1661         error = ath_init_sw_rfkill(sc);
1662         if (error)
1663                 goto error_attach;
1664 #endif
1665
1666         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1667         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1668         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1669
1670         error = ieee80211_register_hw(hw);
1671
1672         if (!ath_is_world_regd(reg)) {
1673                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1674                 if (error)
1675                         goto error_attach;
1676         }
1677
1678         /* Initialize LED control */
1679         ath_init_leds(sc);
1680
1681
1682         return 0;
1683
1684 error_attach:
1685         /* cleanup tx queues */
1686         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1687                 if (ATH_TXQ_SETUP(sc, i))
1688                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1689
1690         ath9k_hw_detach(sc->sc_ah);
1691         ath9k_exit_debug(sc);
1692
1693         return error;
1694 }
1695
1696 int ath_reset(struct ath_softc *sc, bool retry_tx)
1697 {
1698         struct ath_hw *ah = sc->sc_ah;
1699         struct ieee80211_hw *hw = sc->hw;
1700         int r;
1701
1702         ath9k_hw_set_interrupts(ah, 0);
1703         ath_drain_all_txq(sc, retry_tx);
1704         ath_stoprecv(sc);
1705         ath_flushrecv(sc);
1706
1707         spin_lock_bh(&sc->sc_resetlock);
1708         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1709         if (r)
1710                 DPRINTF(sc, ATH_DBG_FATAL,
1711                         "Unable to reset hardware; reset status %u\n", r);
1712         spin_unlock_bh(&sc->sc_resetlock);
1713
1714         if (ath_startrecv(sc) != 0)
1715                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1716
1717         /*
1718          * We may be doing a reset in response to a request
1719          * that changes the channel so update any state that
1720          * might change as a result.
1721          */
1722         ath_cache_conf_rate(sc, &hw->conf);
1723
1724         ath_update_txpow(sc);
1725
1726         if (sc->sc_flags & SC_OP_BEACONS)
1727                 ath_beacon_config(sc, NULL);    /* restart beacons */
1728
1729         ath9k_hw_set_interrupts(ah, sc->imask);
1730
1731         if (retry_tx) {
1732                 int i;
1733                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1734                         if (ATH_TXQ_SETUP(sc, i)) {
1735                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1736                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1737                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1738                         }
1739                 }
1740         }
1741
1742         return r;
1743 }
1744
1745 /*
1746  *  This function will allocate both the DMA descriptor structure, and the
1747  *  buffers it contains.  These are used to contain the descriptors used
1748  *  by the system.
1749 */
1750 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1751                       struct list_head *head, const char *name,
1752                       int nbuf, int ndesc)
1753 {
1754 #define DS2PHYS(_dd, _ds)                                               \
1755         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1756 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1757 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1758
1759         struct ath_desc *ds;
1760         struct ath_buf *bf;
1761         int i, bsize, error;
1762
1763         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1764                 name, nbuf, ndesc);
1765
1766         INIT_LIST_HEAD(head);
1767         /* ath_desc must be a multiple of DWORDs */
1768         if ((sizeof(struct ath_desc) % 4) != 0) {
1769                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1770                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1771                 error = -ENOMEM;
1772                 goto fail;
1773         }
1774
1775         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1776
1777         /*
1778          * Need additional DMA memory because we can't use
1779          * descriptors that cross the 4K page boundary. Assume
1780          * one skipped descriptor per 4K page.
1781          */
1782         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1783                 u32 ndesc_skipped =
1784                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1785                 u32 dma_len;
1786
1787                 while (ndesc_skipped) {
1788                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1789                         dd->dd_desc_len += dma_len;
1790
1791                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1792                 };
1793         }
1794
1795         /* allocate descriptors */
1796         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1797                                          &dd->dd_desc_paddr, GFP_KERNEL);
1798         if (dd->dd_desc == NULL) {
1799                 error = -ENOMEM;
1800                 goto fail;
1801         }
1802         ds = dd->dd_desc;
1803         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1804                 name, ds, (u32) dd->dd_desc_len,
1805                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1806
1807         /* allocate buffers */
1808         bsize = sizeof(struct ath_buf) * nbuf;
1809         bf = kzalloc(bsize, GFP_KERNEL);
1810         if (bf == NULL) {
1811                 error = -ENOMEM;
1812                 goto fail2;
1813         }
1814         dd->dd_bufptr = bf;
1815
1816         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1817                 bf->bf_desc = ds;
1818                 bf->bf_daddr = DS2PHYS(dd, ds);
1819
1820                 if (!(sc->sc_ah->caps.hw_caps &
1821                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1822                         /*
1823                          * Skip descriptor addresses which can cause 4KB
1824                          * boundary crossing (addr + length) with a 32 dword
1825                          * descriptor fetch.
1826                          */
1827                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1828                                 ASSERT((caddr_t) bf->bf_desc <
1829                                        ((caddr_t) dd->dd_desc +
1830                                         dd->dd_desc_len));
1831
1832                                 ds += ndesc;
1833                                 bf->bf_desc = ds;
1834                                 bf->bf_daddr = DS2PHYS(dd, ds);
1835                         }
1836                 }
1837                 list_add_tail(&bf->list, head);
1838         }
1839         return 0;
1840 fail2:
1841         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1842                           dd->dd_desc_paddr);
1843 fail:
1844         memset(dd, 0, sizeof(*dd));
1845         return error;
1846 #undef ATH_DESC_4KB_BOUND_CHECK
1847 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1848 #undef DS2PHYS
1849 }
1850
1851 void ath_descdma_cleanup(struct ath_softc *sc,
1852                          struct ath_descdma *dd,
1853                          struct list_head *head)
1854 {
1855         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1856                           dd->dd_desc_paddr);
1857
1858         INIT_LIST_HEAD(head);
1859         kfree(dd->dd_bufptr);
1860         memset(dd, 0, sizeof(*dd));
1861 }
1862
1863 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1864 {
1865         int qnum;
1866
1867         switch (queue) {
1868         case 0:
1869                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1870                 break;
1871         case 1:
1872                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1873                 break;
1874         case 2:
1875                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1876                 break;
1877         case 3:
1878                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1879                 break;
1880         default:
1881                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1882                 break;
1883         }
1884
1885         return qnum;
1886 }
1887
1888 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1889 {
1890         int qnum;
1891
1892         switch (queue) {
1893         case ATH9K_WME_AC_VO:
1894                 qnum = 0;
1895                 break;
1896         case ATH9K_WME_AC_VI:
1897                 qnum = 1;
1898                 break;
1899         case ATH9K_WME_AC_BE:
1900                 qnum = 2;
1901                 break;
1902         case ATH9K_WME_AC_BK:
1903                 qnum = 3;
1904                 break;
1905         default:
1906                 qnum = -1;
1907                 break;
1908         }
1909
1910         return qnum;
1911 }
1912
1913 /* XXX: Remove me once we don't depend on ath9k_channel for all
1914  * this redundant data */
1915 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1916                            struct ath9k_channel *ichan)
1917 {
1918         struct ieee80211_channel *chan = hw->conf.channel;
1919         struct ieee80211_conf *conf = &hw->conf;
1920
1921         ichan->channel = chan->center_freq;
1922         ichan->chan = chan;
1923
1924         if (chan->band == IEEE80211_BAND_2GHZ) {
1925                 ichan->chanmode = CHANNEL_G;
1926                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1927         } else {
1928                 ichan->chanmode = CHANNEL_A;
1929                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1930         }
1931
1932         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1933
1934         if (conf_is_ht(conf)) {
1935                 if (conf_is_ht40(conf))
1936                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1937
1938                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1939                                             conf->channel_type);
1940         }
1941 }
1942
1943 /**********************/
1944 /* mac80211 callbacks */
1945 /**********************/
1946
1947 static int ath9k_start(struct ieee80211_hw *hw)
1948 {
1949         struct ath_wiphy *aphy = hw->priv;
1950         struct ath_softc *sc = aphy->sc;
1951         struct ieee80211_channel *curchan = hw->conf.channel;
1952         struct ath9k_channel *init_channel;
1953         int r, pos;
1954
1955         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1956                 "initial channel: %d MHz\n", curchan->center_freq);
1957
1958         mutex_lock(&sc->mutex);
1959
1960         if (ath9k_wiphy_started(sc)) {
1961                 if (sc->chan_idx == curchan->hw_value) {
1962                         /*
1963                          * Already on the operational channel, the new wiphy
1964                          * can be marked active.
1965                          */
1966                         aphy->state = ATH_WIPHY_ACTIVE;
1967                         ieee80211_wake_queues(hw);
1968                 } else {
1969                         /*
1970                          * Another wiphy is on another channel, start the new
1971                          * wiphy in paused state.
1972                          */
1973                         aphy->state = ATH_WIPHY_PAUSED;
1974                         ieee80211_stop_queues(hw);
1975                 }
1976                 mutex_unlock(&sc->mutex);
1977                 return 0;
1978         }
1979         aphy->state = ATH_WIPHY_ACTIVE;
1980
1981         /* setup initial channel */
1982
1983         pos = curchan->hw_value;
1984
1985         sc->chan_idx = pos;
1986         init_channel = &sc->sc_ah->channels[pos];
1987         ath9k_update_ichannel(sc, hw, init_channel);
1988
1989         /* Reset SERDES registers */
1990         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1991
1992         /*
1993          * The basic interface to setting the hardware in a good
1994          * state is ``reset''.  On return the hardware is known to
1995          * be powered up and with interrupts disabled.  This must
1996          * be followed by initialization of the appropriate bits
1997          * and then setup of the interrupt mask.
1998          */
1999         spin_lock_bh(&sc->sc_resetlock);
2000         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2001         if (r) {
2002                 DPRINTF(sc, ATH_DBG_FATAL,
2003                         "Unable to reset hardware; reset status %u "
2004                         "(freq %u MHz)\n", r,
2005                         curchan->center_freq);
2006                 spin_unlock_bh(&sc->sc_resetlock);
2007                 goto mutex_unlock;
2008         }
2009         spin_unlock_bh(&sc->sc_resetlock);
2010
2011         /*
2012          * This is needed only to setup initial state
2013          * but it's best done after a reset.
2014          */
2015         ath_update_txpow(sc);
2016
2017         /*
2018          * Setup the hardware after reset:
2019          * The receive engine is set going.
2020          * Frame transmit is handled entirely
2021          * in the frame output path; there's nothing to do
2022          * here except setup the interrupt mask.
2023          */
2024         if (ath_startrecv(sc) != 0) {
2025                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
2026                 r = -EIO;
2027                 goto mutex_unlock;
2028         }
2029
2030         /* Setup our intr mask. */
2031         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2032                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2033                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2034
2035         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2036                 sc->imask |= ATH9K_INT_GTT;
2037
2038         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2039                 sc->imask |= ATH9K_INT_CST;
2040
2041         ath_cache_conf_rate(sc, &hw->conf);
2042
2043         sc->sc_flags &= ~SC_OP_INVALID;
2044
2045         /* Disable BMISS interrupt when we're not associated */
2046         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2047         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2048
2049         ieee80211_wake_queues(hw);
2050
2051 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2052         r = ath_start_rfkill_poll(sc);
2053 #endif
2054
2055 mutex_unlock:
2056         mutex_unlock(&sc->mutex);
2057
2058         return r;
2059 }
2060
2061 static int ath9k_tx(struct ieee80211_hw *hw,
2062                     struct sk_buff *skb)
2063 {
2064         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2065         struct ath_wiphy *aphy = hw->priv;
2066         struct ath_softc *sc = aphy->sc;
2067         struct ath_tx_control txctl;
2068         int hdrlen, padsize;
2069
2070         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2071                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2072                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2073                 goto exit;
2074         }
2075
2076         memset(&txctl, 0, sizeof(struct ath_tx_control));
2077
2078         /*
2079          * As a temporary workaround, assign seq# here; this will likely need
2080          * to be cleaned up to work better with Beacon transmission and virtual
2081          * BSSes.
2082          */
2083         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2084                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2085                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2086                         sc->tx.seq_no += 0x10;
2087                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2088                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2089         }
2090
2091         /* Add the padding after the header if this is not already done */
2092         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2093         if (hdrlen & 3) {
2094                 padsize = hdrlen % 4;
2095                 if (skb_headroom(skb) < padsize)
2096                         return -1;
2097                 skb_push(skb, padsize);
2098                 memmove(skb->data, skb->data + padsize, hdrlen);
2099         }
2100
2101         /* Check if a tx queue is available */
2102
2103         txctl.txq = ath_test_get_txq(sc, skb);
2104         if (!txctl.txq)
2105                 goto exit;
2106
2107         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2108
2109         if (ath_tx_start(hw, skb, &txctl) != 0) {
2110                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2111                 goto exit;
2112         }
2113
2114         return 0;
2115 exit:
2116         dev_kfree_skb_any(skb);
2117         return 0;
2118 }
2119
2120 static void ath9k_stop(struct ieee80211_hw *hw)
2121 {
2122         struct ath_wiphy *aphy = hw->priv;
2123         struct ath_softc *sc = aphy->sc;
2124
2125         aphy->state = ATH_WIPHY_INACTIVE;
2126
2127         if (sc->sc_flags & SC_OP_INVALID) {
2128                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2129                 return;
2130         }
2131
2132         mutex_lock(&sc->mutex);
2133
2134         ieee80211_stop_queues(hw);
2135
2136         if (ath9k_wiphy_started(sc)) {
2137                 mutex_unlock(&sc->mutex);
2138                 return; /* another wiphy still in use */
2139         }
2140
2141         /* make sure h/w will not generate any interrupt
2142          * before setting the invalid flag. */
2143         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2144
2145         if (!(sc->sc_flags & SC_OP_INVALID)) {
2146                 ath_drain_all_txq(sc, false);
2147                 ath_stoprecv(sc);
2148                 ath9k_hw_phy_disable(sc->sc_ah);
2149         } else
2150                 sc->rx.rxlink = NULL;
2151
2152 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2153         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2154                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2155 #endif
2156         /* disable HAL and put h/w to sleep */
2157         ath9k_hw_disable(sc->sc_ah);
2158         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2159
2160         sc->sc_flags |= SC_OP_INVALID;
2161
2162         mutex_unlock(&sc->mutex);
2163
2164         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2165 }
2166
2167 static int ath9k_add_interface(struct ieee80211_hw *hw,
2168                                struct ieee80211_if_init_conf *conf)
2169 {
2170         struct ath_wiphy *aphy = hw->priv;
2171         struct ath_softc *sc = aphy->sc;
2172         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2173         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2174         int ret = 0;
2175
2176         mutex_lock(&sc->mutex);
2177
2178         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2179             sc->nvifs > 0) {
2180                 ret = -ENOBUFS;
2181                 goto out;
2182         }
2183
2184         switch (conf->type) {
2185         case NL80211_IFTYPE_STATION:
2186                 ic_opmode = NL80211_IFTYPE_STATION;
2187                 break;
2188         case NL80211_IFTYPE_ADHOC:
2189         case NL80211_IFTYPE_AP:
2190         case NL80211_IFTYPE_MESH_POINT:
2191                 if (sc->nbcnvifs >= ATH_BCBUF) {
2192                         ret = -ENOBUFS;
2193                         goto out;
2194                 }
2195                 ic_opmode = conf->type;
2196                 break;
2197         default:
2198                 DPRINTF(sc, ATH_DBG_FATAL,
2199                         "Interface type %d not yet supported\n", conf->type);
2200                 ret = -EOPNOTSUPP;
2201                 goto out;
2202         }
2203
2204         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2205
2206         /* Set the VIF opmode */
2207         avp->av_opmode = ic_opmode;
2208         avp->av_bslot = -1;
2209
2210         sc->nvifs++;
2211
2212         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2213                 ath9k_set_bssid_mask(hw);
2214
2215         if (sc->nvifs > 1)
2216                 goto out; /* skip global settings for secondary vif */
2217
2218         if (ic_opmode == NL80211_IFTYPE_AP) {
2219                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2220                 sc->sc_flags |= SC_OP_TSF_RESET;
2221         }
2222
2223         /* Set the device opmode */
2224         sc->sc_ah->opmode = ic_opmode;
2225
2226         /*
2227          * Enable MIB interrupts when there are hardware phy counters.
2228          * Note we only do this (at the moment) for station mode.
2229          */
2230         if ((conf->type == NL80211_IFTYPE_STATION) ||
2231             (conf->type == NL80211_IFTYPE_ADHOC) ||
2232             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2233                 if (ath9k_hw_phycounters(sc->sc_ah))
2234                         sc->imask |= ATH9K_INT_MIB;
2235                 sc->imask |= ATH9K_INT_TSFOOR;
2236         }
2237
2238         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2239
2240         if (conf->type == NL80211_IFTYPE_AP)
2241                 ath_start_ani(sc);
2242
2243 out:
2244         mutex_unlock(&sc->mutex);
2245         return ret;
2246 }
2247
2248 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2249                                    struct ieee80211_if_init_conf *conf)
2250 {
2251         struct ath_wiphy *aphy = hw->priv;
2252         struct ath_softc *sc = aphy->sc;
2253         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2254         int i;
2255
2256         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2257
2258         mutex_lock(&sc->mutex);
2259
2260         /* Stop ANI */
2261         del_timer_sync(&sc->ani.timer);
2262
2263         /* Reclaim beacon resources */
2264         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2265             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2266             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2267                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2268                 ath_beacon_return(sc, avp);
2269         }
2270
2271         sc->sc_flags &= ~SC_OP_BEACONS;
2272
2273         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2274                 if (sc->beacon.bslot[i] == conf->vif) {
2275                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2276                                "slot\n", __func__);
2277                         sc->beacon.bslot[i] = NULL;
2278                         sc->beacon.bslot_aphy[i] = NULL;
2279                 }
2280         }
2281
2282         sc->nvifs--;
2283
2284         mutex_unlock(&sc->mutex);
2285 }
2286
2287 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2288 {
2289         struct ath_wiphy *aphy = hw->priv;
2290         struct ath_softc *sc = aphy->sc;
2291         struct ieee80211_conf *conf = &hw->conf;
2292         struct ath_hw *ah = sc->sc_ah;
2293
2294         mutex_lock(&sc->mutex);
2295
2296         if (changed & IEEE80211_CONF_CHANGE_PS) {
2297                 if (conf->flags & IEEE80211_CONF_PS) {
2298                         if (!(ah->caps.hw_caps &
2299                               ATH9K_HW_CAP_AUTOSLEEP)) {
2300                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2301                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2302                                         ath9k_hw_set_interrupts(sc->sc_ah,
2303                                                         sc->imask);
2304                                 }
2305                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2306                         }
2307                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2308                 } else {
2309                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2310                         if (!(ah->caps.hw_caps &
2311                               ATH9K_HW_CAP_AUTOSLEEP)) {
2312                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2313                                 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2314                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2315                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2316                                         ath9k_hw_set_interrupts(sc->sc_ah,
2317                                                         sc->imask);
2318                                 }
2319                         }
2320                 }
2321         }
2322
2323         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2324                 struct ieee80211_channel *curchan = hw->conf.channel;
2325                 int pos = curchan->hw_value;
2326
2327                 aphy->chan_idx = pos;
2328                 aphy->chan_is_ht = conf_is_ht(conf);
2329
2330                 if (aphy->state == ATH_WIPHY_SCAN ||
2331                     aphy->state == ATH_WIPHY_ACTIVE)
2332                         ath9k_wiphy_pause_all_forced(sc, aphy);
2333                 else {
2334                         /*
2335                          * Do not change operational channel based on a paused
2336                          * wiphy changes.
2337                          */
2338                         goto skip_chan_change;
2339                 }
2340
2341                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2342                         curchan->center_freq);
2343
2344                 /* XXX: remove me eventualy */
2345                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2346
2347                 ath_update_chainmask(sc, conf_is_ht(conf));
2348
2349                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2350                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2351                         mutex_unlock(&sc->mutex);
2352                         return -EINVAL;
2353                 }
2354         }
2355
2356 skip_chan_change:
2357         if (changed & IEEE80211_CONF_CHANGE_POWER)
2358                 sc->config.txpowlimit = 2 * conf->power_level;
2359
2360         /*
2361          * The HW TSF has to be reset when the beacon interval changes.
2362          * We set the flag here, and ath_beacon_config_ap() would take this
2363          * into account when it gets called through the subsequent
2364          * config_interface() call - with IFCC_BEACON in the changed field.
2365          */
2366
2367         if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2368                 sc->sc_flags |= SC_OP_TSF_RESET;
2369
2370         mutex_unlock(&sc->mutex);
2371
2372         return 0;
2373 }
2374
2375 static int ath9k_config_interface(struct ieee80211_hw *hw,
2376                                   struct ieee80211_vif *vif,
2377                                   struct ieee80211_if_conf *conf)
2378 {
2379         struct ath_wiphy *aphy = hw->priv;
2380         struct ath_softc *sc = aphy->sc;
2381         struct ath_hw *ah = sc->sc_ah;
2382         struct ath_vif *avp = (void *)vif->drv_priv;
2383         u32 rfilt = 0;
2384         int error, i;
2385
2386         mutex_lock(&sc->mutex);
2387
2388         /* TODO: Need to decide which hw opmode to use for multi-interface
2389          * cases */
2390         if (vif->type == NL80211_IFTYPE_AP &&
2391             ah->opmode != NL80211_IFTYPE_AP) {
2392                 ah->opmode = NL80211_IFTYPE_STATION;
2393                 ath9k_hw_setopmode(ah);
2394                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2395                 sc->curaid = 0;
2396                 ath9k_hw_write_associd(sc);
2397                 /* Request full reset to get hw opmode changed properly */
2398                 sc->sc_flags |= SC_OP_FULL_RESET;
2399         }
2400
2401         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2402             !is_zero_ether_addr(conf->bssid)) {
2403                 switch (vif->type) {
2404                 case NL80211_IFTYPE_STATION:
2405                 case NL80211_IFTYPE_ADHOC:
2406                 case NL80211_IFTYPE_MESH_POINT:
2407                         /* Set BSSID */
2408                         memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2409                         memcpy(avp->bssid, conf->bssid, ETH_ALEN);
2410                         sc->curaid = 0;
2411                         ath9k_hw_write_associd(sc);
2412
2413                         /* Set aggregation protection mode parameters */
2414                         sc->config.ath_aggr_prot = 0;
2415
2416                         DPRINTF(sc, ATH_DBG_CONFIG,
2417                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2418                                 rfilt, sc->curbssid, sc->curaid);
2419
2420                         /* need to reconfigure the beacon */
2421                         sc->sc_flags &= ~SC_OP_BEACONS ;
2422
2423                         break;
2424                 default:
2425                         break;
2426                 }
2427         }
2428
2429         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2430             (vif->type == NL80211_IFTYPE_AP) ||
2431             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2432                 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2433                     (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2434                      conf->enable_beacon)) {
2435                         /*
2436                          * Allocate and setup the beacon frame.
2437                          *
2438                          * Stop any previous beacon DMA.  This may be
2439                          * necessary, for example, when an ibss merge
2440                          * causes reconfiguration; we may be called
2441                          * with beacon transmission active.
2442                          */
2443                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2444
2445                         error = ath_beacon_alloc(aphy, vif);
2446                         if (error != 0) {
2447                                 mutex_unlock(&sc->mutex);
2448                                 return error;
2449                         }
2450
2451                         ath_beacon_config(sc, vif);
2452                 }
2453         }
2454
2455         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2456         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2457                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2458                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2459                                 ath9k_hw_keysetmac(sc->sc_ah,
2460                                                    (u16)i,
2461                                                    sc->curbssid);
2462         }
2463
2464         /* Only legacy IBSS for now */
2465         if (vif->type == NL80211_IFTYPE_ADHOC)
2466                 ath_update_chainmask(sc, 0);
2467
2468         mutex_unlock(&sc->mutex);
2469
2470         return 0;
2471 }
2472
2473 #define SUPPORTED_FILTERS                       \
2474         (FIF_PROMISC_IN_BSS |                   \
2475         FIF_ALLMULTI |                          \
2476         FIF_CONTROL |                           \
2477         FIF_OTHER_BSS |                         \
2478         FIF_BCN_PRBRESP_PROMISC |               \
2479         FIF_FCSFAIL)
2480
2481 /* FIXME: sc->sc_full_reset ? */
2482 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2483                                    unsigned int changed_flags,
2484                                    unsigned int *total_flags,
2485                                    int mc_count,
2486                                    struct dev_mc_list *mclist)
2487 {
2488         struct ath_wiphy *aphy = hw->priv;
2489         struct ath_softc *sc = aphy->sc;
2490         u32 rfilt;
2491
2492         changed_flags &= SUPPORTED_FILTERS;
2493         *total_flags &= SUPPORTED_FILTERS;
2494
2495         sc->rx.rxfilter = *total_flags;
2496         rfilt = ath_calcrxfilter(sc);
2497         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2498
2499         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2500 }
2501
2502 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2503                              struct ieee80211_vif *vif,
2504                              enum sta_notify_cmd cmd,
2505                              struct ieee80211_sta *sta)
2506 {
2507         struct ath_wiphy *aphy = hw->priv;
2508         struct ath_softc *sc = aphy->sc;
2509
2510         switch (cmd) {
2511         case STA_NOTIFY_ADD:
2512                 ath_node_attach(sc, sta);
2513                 break;
2514         case STA_NOTIFY_REMOVE:
2515                 ath_node_detach(sc, sta);
2516                 break;
2517         default:
2518                 break;
2519         }
2520 }
2521
2522 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2523                          const struct ieee80211_tx_queue_params *params)
2524 {
2525         struct ath_wiphy *aphy = hw->priv;
2526         struct ath_softc *sc = aphy->sc;
2527         struct ath9k_tx_queue_info qi;
2528         int ret = 0, qnum;
2529
2530         if (queue >= WME_NUM_AC)
2531                 return 0;
2532
2533         mutex_lock(&sc->mutex);
2534
2535         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2536
2537         qi.tqi_aifs = params->aifs;
2538         qi.tqi_cwmin = params->cw_min;
2539         qi.tqi_cwmax = params->cw_max;
2540         qi.tqi_burstTime = params->txop;
2541         qnum = ath_get_hal_qnum(queue, sc);
2542
2543         DPRINTF(sc, ATH_DBG_CONFIG,
2544                 "Configure tx [queue/halq] [%d/%d],  "
2545                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2546                 queue, qnum, params->aifs, params->cw_min,
2547                 params->cw_max, params->txop);
2548
2549         ret = ath_txq_update(sc, qnum, &qi);
2550         if (ret)
2551                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2552
2553         mutex_unlock(&sc->mutex);
2554
2555         return ret;
2556 }
2557
2558 static int ath9k_set_key(struct ieee80211_hw *hw,
2559                          enum set_key_cmd cmd,
2560                          struct ieee80211_vif *vif,
2561                          struct ieee80211_sta *sta,
2562                          struct ieee80211_key_conf *key)
2563 {
2564         struct ath_wiphy *aphy = hw->priv;
2565         struct ath_softc *sc = aphy->sc;
2566         int ret = 0;
2567
2568         if (modparam_nohwcrypt)
2569                 return -ENOSPC;
2570
2571         mutex_lock(&sc->mutex);
2572         ath9k_ps_wakeup(sc);
2573         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2574
2575         switch (cmd) {
2576         case SET_KEY:
2577                 ret = ath_key_config(sc, vif, sta, key);
2578                 if (ret >= 0) {
2579                         key->hw_key_idx = ret;
2580                         /* push IV and Michael MIC generation to stack */
2581                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2582                         if (key->alg == ALG_TKIP)
2583                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2584                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2585                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2586                         ret = 0;
2587                 }
2588                 break;
2589         case DISABLE_KEY:
2590                 ath_key_delete(sc, key);
2591                 break;
2592         default:
2593                 ret = -EINVAL;
2594         }
2595
2596         ath9k_ps_restore(sc);
2597         mutex_unlock(&sc->mutex);
2598
2599         return ret;
2600 }
2601
2602 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2603                                    struct ieee80211_vif *vif,
2604                                    struct ieee80211_bss_conf *bss_conf,
2605                                    u32 changed)
2606 {
2607         struct ath_wiphy *aphy = hw->priv;
2608         struct ath_softc *sc = aphy->sc;
2609
2610         mutex_lock(&sc->mutex);
2611
2612         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2613                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2614                         bss_conf->use_short_preamble);
2615                 if (bss_conf->use_short_preamble)
2616                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2617                 else
2618                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2619         }
2620
2621         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2622                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2623                         bss_conf->use_cts_prot);
2624                 if (bss_conf->use_cts_prot &&
2625                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2626                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2627                 else
2628                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2629         }
2630
2631         if (changed & BSS_CHANGED_ASSOC) {
2632                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2633                         bss_conf->assoc);
2634                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2635         }
2636
2637         mutex_unlock(&sc->mutex);
2638 }
2639
2640 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2641 {
2642         u64 tsf;
2643         struct ath_wiphy *aphy = hw->priv;
2644         struct ath_softc *sc = aphy->sc;
2645
2646         mutex_lock(&sc->mutex);
2647         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2648         mutex_unlock(&sc->mutex);
2649
2650         return tsf;
2651 }
2652
2653 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2654 {
2655         struct ath_wiphy *aphy = hw->priv;
2656         struct ath_softc *sc = aphy->sc;
2657
2658         mutex_lock(&sc->mutex);
2659         ath9k_hw_settsf64(sc->sc_ah, tsf);
2660         mutex_unlock(&sc->mutex);
2661 }
2662
2663 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2664 {
2665         struct ath_wiphy *aphy = hw->priv;
2666         struct ath_softc *sc = aphy->sc;
2667
2668         mutex_lock(&sc->mutex);
2669         ath9k_hw_reset_tsf(sc->sc_ah);
2670         mutex_unlock(&sc->mutex);
2671 }
2672
2673 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2674                               enum ieee80211_ampdu_mlme_action action,
2675                               struct ieee80211_sta *sta,
2676                               u16 tid, u16 *ssn)
2677 {
2678         struct ath_wiphy *aphy = hw->priv;
2679         struct ath_softc *sc = aphy->sc;
2680         int ret = 0;
2681
2682         switch (action) {
2683         case IEEE80211_AMPDU_RX_START:
2684                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2685                         ret = -ENOTSUPP;
2686                 break;
2687         case IEEE80211_AMPDU_RX_STOP:
2688                 break;
2689         case IEEE80211_AMPDU_TX_START:
2690                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2691                 if (ret < 0)
2692                         DPRINTF(sc, ATH_DBG_FATAL,
2693                                 "Unable to start TX aggregation\n");
2694                 else
2695                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2696                 break;
2697         case IEEE80211_AMPDU_TX_STOP:
2698                 ret = ath_tx_aggr_stop(sc, sta, tid);
2699                 if (ret < 0)
2700                         DPRINTF(sc, ATH_DBG_FATAL,
2701                                 "Unable to stop TX aggregation\n");
2702
2703                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2704                 break;
2705         case IEEE80211_AMPDU_TX_OPERATIONAL:
2706                 ath_tx_aggr_resume(sc, sta, tid);
2707                 break;
2708         default:
2709                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2710         }
2711
2712         return ret;
2713 }
2714
2715 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2716 {
2717         struct ath_wiphy *aphy = hw->priv;
2718         struct ath_softc *sc = aphy->sc;
2719
2720         if (ath9k_wiphy_scanning(sc)) {
2721                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2722                        "same time\n");
2723                 /*
2724                  * Do not allow the concurrent scanning state for now. This
2725                  * could be improved with scanning control moved into ath9k.
2726                  */
2727                 return;
2728         }
2729
2730         aphy->state = ATH_WIPHY_SCAN;
2731         ath9k_wiphy_pause_all_forced(sc, aphy);
2732
2733         mutex_lock(&sc->mutex);
2734         sc->sc_flags |= SC_OP_SCANNING;
2735         mutex_unlock(&sc->mutex);
2736 }
2737
2738 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2739 {
2740         struct ath_wiphy *aphy = hw->priv;
2741         struct ath_softc *sc = aphy->sc;
2742
2743         mutex_lock(&sc->mutex);
2744         aphy->state = ATH_WIPHY_ACTIVE;
2745         sc->sc_flags &= ~SC_OP_SCANNING;
2746         sc->sc_flags |= SC_OP_FULL_RESET;
2747         mutex_unlock(&sc->mutex);
2748 }
2749
2750 struct ieee80211_ops ath9k_ops = {
2751         .tx                 = ath9k_tx,
2752         .start              = ath9k_start,
2753         .stop               = ath9k_stop,
2754         .add_interface      = ath9k_add_interface,
2755         .remove_interface   = ath9k_remove_interface,
2756         .config             = ath9k_config,
2757         .config_interface   = ath9k_config_interface,
2758         .configure_filter   = ath9k_configure_filter,
2759         .sta_notify         = ath9k_sta_notify,
2760         .conf_tx            = ath9k_conf_tx,
2761         .bss_info_changed   = ath9k_bss_info_changed,
2762         .set_key            = ath9k_set_key,
2763         .get_tsf            = ath9k_get_tsf,
2764         .set_tsf            = ath9k_set_tsf,
2765         .reset_tsf          = ath9k_reset_tsf,
2766         .ampdu_action       = ath9k_ampdu_action,
2767         .sw_scan_start      = ath9k_sw_scan_start,
2768         .sw_scan_complete   = ath9k_sw_scan_complete,
2769 };
2770
2771 static struct {
2772         u32 version;
2773         const char * name;
2774 } ath_mac_bb_names[] = {
2775         { AR_SREV_VERSION_5416_PCI,     "5416" },
2776         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2777         { AR_SREV_VERSION_9100,         "9100" },
2778         { AR_SREV_VERSION_9160,         "9160" },
2779         { AR_SREV_VERSION_9280,         "9280" },
2780         { AR_SREV_VERSION_9285,         "9285" }
2781 };
2782
2783 static struct {
2784         u16 version;
2785         const char * name;
2786 } ath_rf_names[] = {
2787         { 0,                            "5133" },
2788         { AR_RAD5133_SREV_MAJOR,        "5133" },
2789         { AR_RAD5122_SREV_MAJOR,        "5122" },
2790         { AR_RAD2133_SREV_MAJOR,        "2133" },
2791         { AR_RAD2122_SREV_MAJOR,        "2122" }
2792 };
2793
2794 /*
2795  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2796  */
2797 const char *
2798 ath_mac_bb_name(u32 mac_bb_version)
2799 {
2800         int i;
2801
2802         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2803                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2804                         return ath_mac_bb_names[i].name;
2805                 }
2806         }
2807
2808         return "????";
2809 }
2810
2811 /*
2812  * Return the RF name. "????" is returned if the RF is unknown.
2813  */
2814 const char *
2815 ath_rf_name(u16 rf_version)
2816 {
2817         int i;
2818
2819         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2820                 if (ath_rf_names[i].version == rf_version) {
2821                         return ath_rf_names[i].name;
2822                 }
2823         }
2824
2825         return "????";
2826 }
2827
2828 static int __init ath9k_init(void)
2829 {
2830         int error;
2831
2832         /* Register rate control algorithm */
2833         error = ath_rate_control_register();
2834         if (error != 0) {
2835                 printk(KERN_ERR
2836                         "ath9k: Unable to register rate control "
2837                         "algorithm: %d\n",
2838                         error);
2839                 goto err_out;
2840         }
2841
2842         error = ath9k_debug_create_root();
2843         if (error) {
2844                 printk(KERN_ERR
2845                         "ath9k: Unable to create debugfs root: %d\n",
2846                         error);
2847                 goto err_rate_unregister;
2848         }
2849
2850         error = ath_pci_init();
2851         if (error < 0) {
2852                 printk(KERN_ERR
2853                         "ath9k: No PCI devices found, driver not installed.\n");
2854                 error = -ENODEV;
2855                 goto err_remove_root;
2856         }
2857
2858         error = ath_ahb_init();
2859         if (error < 0) {
2860                 error = -ENODEV;
2861                 goto err_pci_exit;
2862         }
2863
2864         return 0;
2865
2866  err_pci_exit:
2867         ath_pci_exit();
2868
2869  err_remove_root:
2870         ath9k_debug_remove_root();
2871  err_rate_unregister:
2872         ath_rate_control_unregister();
2873  err_out:
2874         return error;
2875 }
2876 module_init(ath9k_init);
2877
2878 static void __exit ath9k_exit(void)
2879 {
2880         ath_ahb_exit();
2881         ath_pci_exit();
2882         ath9k_debug_remove_root();
2883         ath_rate_control_unregister();
2884         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2885 }
2886 module_exit(ath9k_exit);