42772d25491a47e87ff82be8a72ef88322ae4b60
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19 #include "btcoex.h"
20
21 static char *dev_info = "ath9k";
22
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
27
28 static int modparam_nohwcrypt;
29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
32 /* We use the hw_value as an index into our private channel structure */
33
34 #define CHAN2G(_freq, _idx)  { \
35         .center_freq = (_freq), \
36         .hw_value = (_idx), \
37         .max_power = 20, \
38 }
39
40 #define CHAN5G(_freq, _idx) { \
41         .band = IEEE80211_BAND_5GHZ, \
42         .center_freq = (_freq), \
43         .hw_value = (_idx), \
44         .max_power = 20, \
45 }
46
47 /* Some 2 GHz radios are actually tunable on 2312-2732
48  * on 5 MHz steps, we support the channels which we know
49  * we have calibration data for all cards though to make
50  * this static */
51 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
52         CHAN2G(2412, 0), /* Channel 1 */
53         CHAN2G(2417, 1), /* Channel 2 */
54         CHAN2G(2422, 2), /* Channel 3 */
55         CHAN2G(2427, 3), /* Channel 4 */
56         CHAN2G(2432, 4), /* Channel 5 */
57         CHAN2G(2437, 5), /* Channel 6 */
58         CHAN2G(2442, 6), /* Channel 7 */
59         CHAN2G(2447, 7), /* Channel 8 */
60         CHAN2G(2452, 8), /* Channel 9 */
61         CHAN2G(2457, 9), /* Channel 10 */
62         CHAN2G(2462, 10), /* Channel 11 */
63         CHAN2G(2467, 11), /* Channel 12 */
64         CHAN2G(2472, 12), /* Channel 13 */
65         CHAN2G(2484, 13), /* Channel 14 */
66 };
67
68 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
69  * on 5 MHz steps, we support the channels which we know
70  * we have calibration data for all cards though to make
71  * this static */
72 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
73         /* _We_ call this UNII 1 */
74         CHAN5G(5180, 14), /* Channel 36 */
75         CHAN5G(5200, 15), /* Channel 40 */
76         CHAN5G(5220, 16), /* Channel 44 */
77         CHAN5G(5240, 17), /* Channel 48 */
78         /* _We_ call this UNII 2 */
79         CHAN5G(5260, 18), /* Channel 52 */
80         CHAN5G(5280, 19), /* Channel 56 */
81         CHAN5G(5300, 20), /* Channel 60 */
82         CHAN5G(5320, 21), /* Channel 64 */
83         /* _We_ call this "Middle band" */
84         CHAN5G(5500, 22), /* Channel 100 */
85         CHAN5G(5520, 23), /* Channel 104 */
86         CHAN5G(5540, 24), /* Channel 108 */
87         CHAN5G(5560, 25), /* Channel 112 */
88         CHAN5G(5580, 26), /* Channel 116 */
89         CHAN5G(5600, 27), /* Channel 120 */
90         CHAN5G(5620, 28), /* Channel 124 */
91         CHAN5G(5640, 29), /* Channel 128 */
92         CHAN5G(5660, 30), /* Channel 132 */
93         CHAN5G(5680, 31), /* Channel 136 */
94         CHAN5G(5700, 32), /* Channel 140 */
95         /* _We_ call this UNII 3 */
96         CHAN5G(5745, 33), /* Channel 149 */
97         CHAN5G(5765, 34), /* Channel 153 */
98         CHAN5G(5785, 35), /* Channel 157 */
99         CHAN5G(5805, 36), /* Channel 161 */
100         CHAN5G(5825, 37), /* Channel 165 */
101 };
102
103 static void ath_cache_conf_rate(struct ath_softc *sc,
104                                 struct ieee80211_conf *conf)
105 {
106         switch (conf->channel->band) {
107         case IEEE80211_BAND_2GHZ:
108                 if (conf_is_ht20(conf))
109                         sc->cur_rate_table =
110                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
111                 else if (conf_is_ht40_minus(conf))
112                         sc->cur_rate_table =
113                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
114                 else if (conf_is_ht40_plus(conf))
115                         sc->cur_rate_table =
116                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
117                 else
118                         sc->cur_rate_table =
119                           sc->hw_rate_table[ATH9K_MODE_11G];
120                 break;
121         case IEEE80211_BAND_5GHZ:
122                 if (conf_is_ht20(conf))
123                         sc->cur_rate_table =
124                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
125                 else if (conf_is_ht40_minus(conf))
126                         sc->cur_rate_table =
127                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
128                 else if (conf_is_ht40_plus(conf))
129                         sc->cur_rate_table =
130                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
131                 else
132                         sc->cur_rate_table =
133                           sc->hw_rate_table[ATH9K_MODE_11A];
134                 break;
135         default:
136                 BUG_ON(1);
137                 break;
138         }
139 }
140
141 static void ath_update_txpow(struct ath_softc *sc)
142 {
143         struct ath_hw *ah = sc->sc_ah;
144         u32 txpow;
145
146         if (sc->curtxpow != sc->config.txpowlimit) {
147                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
148                 /* read back in case value is clamped */
149                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
150                 sc->curtxpow = txpow;
151         }
152 }
153
154 static u8 parse_mpdudensity(u8 mpdudensity)
155 {
156         /*
157          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
158          *   0 for no restriction
159          *   1 for 1/4 us
160          *   2 for 1/2 us
161          *   3 for 1 us
162          *   4 for 2 us
163          *   5 for 4 us
164          *   6 for 8 us
165          *   7 for 16 us
166          */
167         switch (mpdudensity) {
168         case 0:
169                 return 0;
170         case 1:
171         case 2:
172         case 3:
173                 /* Our lower layer calculations limit our precision to
174                    1 microsecond */
175                 return 1;
176         case 4:
177                 return 2;
178         case 5:
179                 return 4;
180         case 6:
181                 return 8;
182         case 7:
183                 return 16;
184         default:
185                 return 0;
186         }
187 }
188
189 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
190 {
191         const struct ath_rate_table *rate_table = NULL;
192         struct ieee80211_supported_band *sband;
193         struct ieee80211_rate *rate;
194         int i, maxrates;
195
196         switch (band) {
197         case IEEE80211_BAND_2GHZ:
198                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
199                 break;
200         case IEEE80211_BAND_5GHZ:
201                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
202                 break;
203         default:
204                 break;
205         }
206
207         if (rate_table == NULL)
208                 return;
209
210         sband = &sc->sbands[band];
211         rate = sc->rates[band];
212
213         if (rate_table->rate_cnt > ATH_RATE_MAX)
214                 maxrates = ATH_RATE_MAX;
215         else
216                 maxrates = rate_table->rate_cnt;
217
218         for (i = 0; i < maxrates; i++) {
219                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
220                 rate[i].hw_value = rate_table->info[i].ratecode;
221                 if (rate_table->info[i].short_preamble) {
222                         rate[i].hw_value_short = rate_table->info[i].ratecode |
223                                 rate_table->info[i].short_preamble;
224                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
225                 }
226                 sband->n_bitrates++;
227
228                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
229                         rate[i].bitrate / 10, rate[i].hw_value);
230         }
231 }
232
233 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
234                                                 struct ieee80211_hw *hw)
235 {
236         struct ieee80211_channel *curchan = hw->conf.channel;
237         struct ath9k_channel *channel;
238         u8 chan_idx;
239
240         chan_idx = curchan->hw_value;
241         channel = &sc->sc_ah->channels[chan_idx];
242         ath9k_update_ichannel(sc, hw, channel);
243         return channel;
244 }
245
246 /*
247  * Set/change channels.  If the channel is really being changed, it's done
248  * by reseting the chip.  To accomplish this we must first cleanup any pending
249  * DMA, then restart stuff.
250 */
251 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
252                     struct ath9k_channel *hchan)
253 {
254         struct ath_hw *ah = sc->sc_ah;
255         bool fastcc = true, stopped;
256         struct ieee80211_channel *channel = hw->conf.channel;
257         int r;
258
259         if (sc->sc_flags & SC_OP_INVALID)
260                 return -EIO;
261
262         ath9k_ps_wakeup(sc);
263
264         /*
265          * This is only performed if the channel settings have
266          * actually changed.
267          *
268          * To switch channels clear any pending DMA operations;
269          * wait long enough for the RX fifo to drain, reset the
270          * hardware at the new frequency, and then re-enable
271          * the relevant bits of the h/w.
272          */
273         ath9k_hw_set_interrupts(ah, 0);
274         ath_drain_all_txq(sc, false);
275         stopped = ath_stoprecv(sc);
276
277         /* XXX: do not flush receive queue here. We don't want
278          * to flush data frames already in queue because of
279          * changing channel. */
280
281         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
282                 fastcc = false;
283
284         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
285                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
286                 sc->sc_ah->curchan->channel,
287                 channel->center_freq, sc->tx_chan_width);
288
289         spin_lock_bh(&sc->sc_resetlock);
290
291         r = ath9k_hw_reset(ah, hchan, fastcc);
292         if (r) {
293                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
294                         "Unable to reset channel (%u Mhz) "
295                         "reset status %d\n",
296                         channel->center_freq, r);
297                 spin_unlock_bh(&sc->sc_resetlock);
298                 goto ps_restore;
299         }
300         spin_unlock_bh(&sc->sc_resetlock);
301
302         sc->sc_flags &= ~SC_OP_FULL_RESET;
303
304         if (ath_startrecv(sc) != 0) {
305                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
306                         "Unable to restart recv logic\n");
307                 r = -EIO;
308                 goto ps_restore;
309         }
310
311         ath_cache_conf_rate(sc, &hw->conf);
312         ath_update_txpow(sc);
313         ath9k_hw_set_interrupts(ah, sc->imask);
314
315  ps_restore:
316         ath9k_ps_restore(sc);
317         return r;
318 }
319
320 /*
321  *  This routine performs the periodic noise floor calibration function
322  *  that is used to adjust and optimize the chip performance.  This
323  *  takes environmental changes (location, temperature) into account.
324  *  When the task is complete, it reschedules itself depending on the
325  *  appropriate interval that was calculated.
326  */
327 static void ath_ani_calibrate(unsigned long data)
328 {
329         struct ath_softc *sc = (struct ath_softc *)data;
330         struct ath_hw *ah = sc->sc_ah;
331         bool longcal = false;
332         bool shortcal = false;
333         bool aniflag = false;
334         unsigned int timestamp = jiffies_to_msecs(jiffies);
335         u32 cal_interval, short_cal_interval;
336
337         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
338                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
339
340         /*
341         * don't calibrate when we're scanning.
342         * we are most likely not on our home channel.
343         */
344         spin_lock(&sc->ani_lock);
345         if (sc->sc_flags & SC_OP_SCANNING)
346                 goto set_timer;
347
348         /* Only calibrate if awake */
349         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
350                 goto set_timer;
351
352         ath9k_ps_wakeup(sc);
353
354         /* Long calibration runs independently of short calibration. */
355         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
356                 longcal = true;
357                 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
358                 sc->ani.longcal_timer = timestamp;
359         }
360
361         /* Short calibration applies only while caldone is false */
362         if (!sc->ani.caldone) {
363                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
364                         shortcal = true;
365                         DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
366                         sc->ani.shortcal_timer = timestamp;
367                         sc->ani.resetcal_timer = timestamp;
368                 }
369         } else {
370                 if ((timestamp - sc->ani.resetcal_timer) >=
371                     ATH_RESTART_CALINTERVAL) {
372                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
373                         if (sc->ani.caldone)
374                                 sc->ani.resetcal_timer = timestamp;
375                 }
376         }
377
378         /* Verify whether we must check ANI */
379         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
380                 aniflag = true;
381                 sc->ani.checkani_timer = timestamp;
382         }
383
384         /* Skip all processing if there's nothing to do. */
385         if (longcal || shortcal || aniflag) {
386                 /* Call ANI routine if necessary */
387                 if (aniflag)
388                         ath9k_hw_ani_monitor(ah, ah->curchan);
389
390                 /* Perform calibration if necessary */
391                 if (longcal || shortcal) {
392                         sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
393                                                      sc->rx_chainmask, longcal);
394
395                         if (longcal)
396                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
397                                                                      ah->curchan);
398
399                         DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
400                                 ah->curchan->channel, ah->curchan->channelFlags,
401                                 sc->ani.noise_floor);
402                 }
403         }
404
405         ath9k_ps_restore(sc);
406
407 set_timer:
408         spin_unlock(&sc->ani_lock);
409         /*
410         * Set timer interval based on previous results.
411         * The interval must be the shortest necessary to satisfy ANI,
412         * short calibration and long calibration.
413         */
414         cal_interval = ATH_LONG_CALINTERVAL;
415         if (sc->sc_ah->config.enable_ani)
416                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
417         if (!sc->ani.caldone)
418                 cal_interval = min(cal_interval, (u32)short_cal_interval);
419
420         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
421 }
422
423 static void ath_start_ani(struct ath_softc *sc)
424 {
425         unsigned long timestamp = jiffies_to_msecs(jiffies);
426
427         sc->ani.longcal_timer = timestamp;
428         sc->ani.shortcal_timer = timestamp;
429         sc->ani.checkani_timer = timestamp;
430
431         mod_timer(&sc->ani.timer,
432                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
433 }
434
435 /*
436  * Update tx/rx chainmask. For legacy association,
437  * hard code chainmask to 1x1, for 11n association, use
438  * the chainmask configuration, for bt coexistence, use
439  * the chainmask configuration even in legacy mode.
440  */
441 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
442 {
443         struct ath_hw *ah = sc->sc_ah;
444
445         if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
446             (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
447                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
448                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
449         } else {
450                 sc->tx_chainmask = 1;
451                 sc->rx_chainmask = 1;
452         }
453
454         DPRINTF(ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
455                 sc->tx_chainmask, sc->rx_chainmask);
456 }
457
458 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
459 {
460         struct ath_node *an;
461
462         an = (struct ath_node *)sta->drv_priv;
463
464         if (sc->sc_flags & SC_OP_TXAGGR) {
465                 ath_tx_node_init(sc, an);
466                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
467                                      sta->ht_cap.ampdu_factor);
468                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
469                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
470         }
471 }
472
473 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
474 {
475         struct ath_node *an = (struct ath_node *)sta->drv_priv;
476
477         if (sc->sc_flags & SC_OP_TXAGGR)
478                 ath_tx_node_cleanup(sc, an);
479 }
480
481 static void ath9k_tasklet(unsigned long data)
482 {
483         struct ath_softc *sc = (struct ath_softc *)data;
484         struct ath_hw *ah = sc->sc_ah;
485
486         u32 status = sc->intrstatus;
487
488         ath9k_ps_wakeup(sc);
489
490         if (status & ATH9K_INT_FATAL) {
491                 ath_reset(sc, false);
492                 ath9k_ps_restore(sc);
493                 return;
494         }
495
496         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
497                 spin_lock_bh(&sc->rx.rxflushlock);
498                 ath_rx_tasklet(sc, 0);
499                 spin_unlock_bh(&sc->rx.rxflushlock);
500         }
501
502         if (status & ATH9K_INT_TX)
503                 ath_tx_tasklet(sc);
504
505         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
506                 /*
507                  * TSF sync does not look correct; remain awake to sync with
508                  * the next Beacon.
509                  */
510                 DPRINTF(ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
511                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
512         }
513
514         if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
515                 if (status & ATH9K_INT_GENTIMER)
516                         ath_gen_timer_isr(sc->sc_ah);
517
518         /* re-enable hardware interrupt */
519         ath9k_hw_set_interrupts(ah, sc->imask);
520         ath9k_ps_restore(sc);
521 }
522
523 irqreturn_t ath_isr(int irq, void *dev)
524 {
525 #define SCHED_INTR (                            \
526                 ATH9K_INT_FATAL |               \
527                 ATH9K_INT_RXORN |               \
528                 ATH9K_INT_RXEOL |               \
529                 ATH9K_INT_RX |                  \
530                 ATH9K_INT_TX |                  \
531                 ATH9K_INT_BMISS |               \
532                 ATH9K_INT_CST |                 \
533                 ATH9K_INT_TSFOOR |              \
534                 ATH9K_INT_GENTIMER)
535
536         struct ath_softc *sc = dev;
537         struct ath_hw *ah = sc->sc_ah;
538         enum ath9k_int status;
539         bool sched = false;
540
541         /*
542          * The hardware is not ready/present, don't
543          * touch anything. Note this can happen early
544          * on if the IRQ is shared.
545          */
546         if (sc->sc_flags & SC_OP_INVALID)
547                 return IRQ_NONE;
548
549
550         /* shared irq, not for us */
551
552         if (!ath9k_hw_intrpend(ah))
553                 return IRQ_NONE;
554
555         /*
556          * Figure out the reason(s) for the interrupt.  Note
557          * that the hal returns a pseudo-ISR that may include
558          * bits we haven't explicitly enabled so we mask the
559          * value to insure we only process bits we requested.
560          */
561         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
562         status &= sc->imask;    /* discard unasked-for bits */
563
564         /*
565          * If there are no status bits set, then this interrupt was not
566          * for me (should have been caught above).
567          */
568         if (!status)
569                 return IRQ_NONE;
570
571         /* Cache the status */
572         sc->intrstatus = status;
573
574         if (status & SCHED_INTR)
575                 sched = true;
576
577         /*
578          * If a FATAL or RXORN interrupt is received, we have to reset the
579          * chip immediately.
580          */
581         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
582                 goto chip_reset;
583
584         if (status & ATH9K_INT_SWBA)
585                 tasklet_schedule(&sc->bcon_tasklet);
586
587         if (status & ATH9K_INT_TXURN)
588                 ath9k_hw_updatetxtriglevel(ah, true);
589
590         if (status & ATH9K_INT_MIB) {
591                 /*
592                  * Disable interrupts until we service the MIB
593                  * interrupt; otherwise it will continue to
594                  * fire.
595                  */
596                 ath9k_hw_set_interrupts(ah, 0);
597                 /*
598                  * Let the hal handle the event. We assume
599                  * it will clear whatever condition caused
600                  * the interrupt.
601                  */
602                 ath9k_hw_procmibevent(ah);
603                 ath9k_hw_set_interrupts(ah, sc->imask);
604         }
605
606         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
607                 if (status & ATH9K_INT_TIM_TIMER) {
608                         /* Clear RxAbort bit so that we can
609                          * receive frames */
610                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
611                         ath9k_hw_setrxabort(sc->sc_ah, 0);
612                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
613                 }
614
615 chip_reset:
616
617         ath_debug_stat_interrupt(sc, status);
618
619         if (sched) {
620                 /* turn off every interrupt except SWBA */
621                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
622                 tasklet_schedule(&sc->intr_tq);
623         }
624
625         return IRQ_HANDLED;
626
627 #undef SCHED_INTR
628 }
629
630 static u32 ath_get_extchanmode(struct ath_softc *sc,
631                                struct ieee80211_channel *chan,
632                                enum nl80211_channel_type channel_type)
633 {
634         u32 chanmode = 0;
635
636         switch (chan->band) {
637         case IEEE80211_BAND_2GHZ:
638                 switch(channel_type) {
639                 case NL80211_CHAN_NO_HT:
640                 case NL80211_CHAN_HT20:
641                         chanmode = CHANNEL_G_HT20;
642                         break;
643                 case NL80211_CHAN_HT40PLUS:
644                         chanmode = CHANNEL_G_HT40PLUS;
645                         break;
646                 case NL80211_CHAN_HT40MINUS:
647                         chanmode = CHANNEL_G_HT40MINUS;
648                         break;
649                 }
650                 break;
651         case IEEE80211_BAND_5GHZ:
652                 switch(channel_type) {
653                 case NL80211_CHAN_NO_HT:
654                 case NL80211_CHAN_HT20:
655                         chanmode = CHANNEL_A_HT20;
656                         break;
657                 case NL80211_CHAN_HT40PLUS:
658                         chanmode = CHANNEL_A_HT40PLUS;
659                         break;
660                 case NL80211_CHAN_HT40MINUS:
661                         chanmode = CHANNEL_A_HT40MINUS;
662                         break;
663                 }
664                 break;
665         default:
666                 break;
667         }
668
669         return chanmode;
670 }
671
672 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
673                            struct ath9k_keyval *hk, const u8 *addr,
674                            bool authenticator)
675 {
676         const u8 *key_rxmic;
677         const u8 *key_txmic;
678
679         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
680         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
681
682         if (addr == NULL) {
683                 /*
684                  * Group key installation - only two key cache entries are used
685                  * regardless of splitmic capability since group key is only
686                  * used either for TX or RX.
687                  */
688                 if (authenticator) {
689                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
690                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
691                 } else {
692                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
693                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
694                 }
695                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
696         }
697         if (!sc->splitmic) {
698                 /* TX and RX keys share the same key cache entry. */
699                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
700                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
701                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
702         }
703
704         /* Separate key cache entries for TX and RX */
705
706         /* TX key goes at first index, RX key at +32. */
707         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
708         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
709                 /* TX MIC entry failed. No need to proceed further */
710                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
711                         "Setting TX MIC Key Failed\n");
712                 return 0;
713         }
714
715         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
716         /* XXX delete tx key on failure? */
717         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
718 }
719
720 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
721 {
722         int i;
723
724         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
725                 if (test_bit(i, sc->keymap) ||
726                     test_bit(i + 64, sc->keymap))
727                         continue; /* At least one part of TKIP key allocated */
728                 if (sc->splitmic &&
729                     (test_bit(i + 32, sc->keymap) ||
730                      test_bit(i + 64 + 32, sc->keymap)))
731                         continue; /* At least one part of TKIP key allocated */
732
733                 /* Found a free slot for a TKIP key */
734                 return i;
735         }
736         return -1;
737 }
738
739 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
740 {
741         int i;
742
743         /* First, try to find slots that would not be available for TKIP. */
744         if (sc->splitmic) {
745                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
746                         if (!test_bit(i, sc->keymap) &&
747                             (test_bit(i + 32, sc->keymap) ||
748                              test_bit(i + 64, sc->keymap) ||
749                              test_bit(i + 64 + 32, sc->keymap)))
750                                 return i;
751                         if (!test_bit(i + 32, sc->keymap) &&
752                             (test_bit(i, sc->keymap) ||
753                              test_bit(i + 64, sc->keymap) ||
754                              test_bit(i + 64 + 32, sc->keymap)))
755                                 return i + 32;
756                         if (!test_bit(i + 64, sc->keymap) &&
757                             (test_bit(i , sc->keymap) ||
758                              test_bit(i + 32, sc->keymap) ||
759                              test_bit(i + 64 + 32, sc->keymap)))
760                                 return i + 64;
761                         if (!test_bit(i + 64 + 32, sc->keymap) &&
762                             (test_bit(i, sc->keymap) ||
763                              test_bit(i + 32, sc->keymap) ||
764                              test_bit(i + 64, sc->keymap)))
765                                 return i + 64 + 32;
766                 }
767         } else {
768                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
769                         if (!test_bit(i, sc->keymap) &&
770                             test_bit(i + 64, sc->keymap))
771                                 return i;
772                         if (test_bit(i, sc->keymap) &&
773                             !test_bit(i + 64, sc->keymap))
774                                 return i + 64;
775                 }
776         }
777
778         /* No partially used TKIP slots, pick any available slot */
779         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
780                 /* Do not allow slots that could be needed for TKIP group keys
781                  * to be used. This limitation could be removed if we know that
782                  * TKIP will not be used. */
783                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
784                         continue;
785                 if (sc->splitmic) {
786                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
787                                 continue;
788                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
789                                 continue;
790                 }
791
792                 if (!test_bit(i, sc->keymap))
793                         return i; /* Found a free slot for a key */
794         }
795
796         /* No free slot found */
797         return -1;
798 }
799
800 static int ath_key_config(struct ath_softc *sc,
801                           struct ieee80211_vif *vif,
802                           struct ieee80211_sta *sta,
803                           struct ieee80211_key_conf *key)
804 {
805         struct ath9k_keyval hk;
806         const u8 *mac = NULL;
807         int ret = 0;
808         int idx;
809
810         memset(&hk, 0, sizeof(hk));
811
812         switch (key->alg) {
813         case ALG_WEP:
814                 hk.kv_type = ATH9K_CIPHER_WEP;
815                 break;
816         case ALG_TKIP:
817                 hk.kv_type = ATH9K_CIPHER_TKIP;
818                 break;
819         case ALG_CCMP:
820                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
821                 break;
822         default:
823                 return -EOPNOTSUPP;
824         }
825
826         hk.kv_len = key->keylen;
827         memcpy(hk.kv_val, key->key, key->keylen);
828
829         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
830                 /* For now, use the default keys for broadcast keys. This may
831                  * need to change with virtual interfaces. */
832                 idx = key->keyidx;
833         } else if (key->keyidx) {
834                 if (WARN_ON(!sta))
835                         return -EOPNOTSUPP;
836                 mac = sta->addr;
837
838                 if (vif->type != NL80211_IFTYPE_AP) {
839                         /* Only keyidx 0 should be used with unicast key, but
840                          * allow this for client mode for now. */
841                         idx = key->keyidx;
842                 } else
843                         return -EIO;
844         } else {
845                 if (WARN_ON(!sta))
846                         return -EOPNOTSUPP;
847                 mac = sta->addr;
848
849                 if (key->alg == ALG_TKIP)
850                         idx = ath_reserve_key_cache_slot_tkip(sc);
851                 else
852                         idx = ath_reserve_key_cache_slot(sc);
853                 if (idx < 0)
854                         return -ENOSPC; /* no free key cache entries */
855         }
856
857         if (key->alg == ALG_TKIP)
858                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
859                                       vif->type == NL80211_IFTYPE_AP);
860         else
861                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
862
863         if (!ret)
864                 return -EIO;
865
866         set_bit(idx, sc->keymap);
867         if (key->alg == ALG_TKIP) {
868                 set_bit(idx + 64, sc->keymap);
869                 if (sc->splitmic) {
870                         set_bit(idx + 32, sc->keymap);
871                         set_bit(idx + 64 + 32, sc->keymap);
872                 }
873         }
874
875         return idx;
876 }
877
878 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
879 {
880         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
881         if (key->hw_key_idx < IEEE80211_WEP_NKID)
882                 return;
883
884         clear_bit(key->hw_key_idx, sc->keymap);
885         if (key->alg != ALG_TKIP)
886                 return;
887
888         clear_bit(key->hw_key_idx + 64, sc->keymap);
889         if (sc->splitmic) {
890                 clear_bit(key->hw_key_idx + 32, sc->keymap);
891                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
892         }
893 }
894
895 static void setup_ht_cap(struct ath_softc *sc,
896                          struct ieee80211_sta_ht_cap *ht_info)
897 {
898         u8 tx_streams, rx_streams;
899
900         ht_info->ht_supported = true;
901         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
902                        IEEE80211_HT_CAP_SM_PS |
903                        IEEE80211_HT_CAP_SGI_40 |
904                        IEEE80211_HT_CAP_DSSSCCK40;
905
906         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
907         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
908
909         /* set up supported mcs set */
910         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
911         tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
912         rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
913
914         if (tx_streams != rx_streams) {
915                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
916                         tx_streams, rx_streams);
917                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
918                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
919                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
920         }
921
922         ht_info->mcs.rx_mask[0] = 0xff;
923         if (rx_streams >= 2)
924                 ht_info->mcs.rx_mask[1] = 0xff;
925
926         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
927 }
928
929 static void ath9k_bss_assoc_info(struct ath_softc *sc,
930                                  struct ieee80211_vif *vif,
931                                  struct ieee80211_bss_conf *bss_conf)
932 {
933
934         if (bss_conf->assoc) {
935                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
936                         bss_conf->aid, sc->curbssid);
937
938                 /* New association, store aid */
939                 sc->curaid = bss_conf->aid;
940                 ath9k_hw_write_associd(sc);
941
942                 /*
943                  * Request a re-configuration of Beacon related timers
944                  * on the receipt of the first Beacon frame (i.e.,
945                  * after time sync with the AP).
946                  */
947                 sc->sc_flags |= SC_OP_BEACON_SYNC;
948
949                 /* Configure the beacon */
950                 ath_beacon_config(sc, vif);
951
952                 /* Reset rssi stats */
953                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
954
955                 ath_start_ani(sc);
956         } else {
957                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
958                 sc->curaid = 0;
959                 /* Stop ANI */
960                 del_timer_sync(&sc->ani.timer);
961         }
962 }
963
964 /********************************/
965 /*       LED functions          */
966 /********************************/
967
968 static void ath_led_blink_work(struct work_struct *work)
969 {
970         struct ath_softc *sc = container_of(work, struct ath_softc,
971                                             ath_led_blink_work.work);
972
973         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
974                 return;
975
976         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
977             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
978                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
979         else
980                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
981                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
982
983         ieee80211_queue_delayed_work(sc->hw,
984                                      &sc->ath_led_blink_work,
985                                      (sc->sc_flags & SC_OP_LED_ON) ?
986                                         msecs_to_jiffies(sc->led_off_duration) :
987                                         msecs_to_jiffies(sc->led_on_duration));
988
989         sc->led_on_duration = sc->led_on_cnt ?
990                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
991                         ATH_LED_ON_DURATION_IDLE;
992         sc->led_off_duration = sc->led_off_cnt ?
993                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
994                         ATH_LED_OFF_DURATION_IDLE;
995         sc->led_on_cnt = sc->led_off_cnt = 0;
996         if (sc->sc_flags & SC_OP_LED_ON)
997                 sc->sc_flags &= ~SC_OP_LED_ON;
998         else
999                 sc->sc_flags |= SC_OP_LED_ON;
1000 }
1001
1002 static void ath_led_brightness(struct led_classdev *led_cdev,
1003                                enum led_brightness brightness)
1004 {
1005         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1006         struct ath_softc *sc = led->sc;
1007
1008         switch (brightness) {
1009         case LED_OFF:
1010                 if (led->led_type == ATH_LED_ASSOC ||
1011                     led->led_type == ATH_LED_RADIO) {
1012                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1013                                 (led->led_type == ATH_LED_RADIO));
1014                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1015                         if (led->led_type == ATH_LED_RADIO)
1016                                 sc->sc_flags &= ~SC_OP_LED_ON;
1017                 } else {
1018                         sc->led_off_cnt++;
1019                 }
1020                 break;
1021         case LED_FULL:
1022                 if (led->led_type == ATH_LED_ASSOC) {
1023                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1024                         ieee80211_queue_delayed_work(sc->hw,
1025                                                      &sc->ath_led_blink_work, 0);
1026                 } else if (led->led_type == ATH_LED_RADIO) {
1027                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1028                         sc->sc_flags |= SC_OP_LED_ON;
1029                 } else {
1030                         sc->led_on_cnt++;
1031                 }
1032                 break;
1033         default:
1034                 break;
1035         }
1036 }
1037
1038 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1039                             char *trigger)
1040 {
1041         int ret;
1042
1043         led->sc = sc;
1044         led->led_cdev.name = led->name;
1045         led->led_cdev.default_trigger = trigger;
1046         led->led_cdev.brightness_set = ath_led_brightness;
1047
1048         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1049         if (ret)
1050                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1051                         "Failed to register led:%s", led->name);
1052         else
1053                 led->registered = 1;
1054         return ret;
1055 }
1056
1057 static void ath_unregister_led(struct ath_led *led)
1058 {
1059         if (led->registered) {
1060                 led_classdev_unregister(&led->led_cdev);
1061                 led->registered = 0;
1062         }
1063 }
1064
1065 static void ath_deinit_leds(struct ath_softc *sc)
1066 {
1067         ath_unregister_led(&sc->assoc_led);
1068         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1069         ath_unregister_led(&sc->tx_led);
1070         ath_unregister_led(&sc->rx_led);
1071         ath_unregister_led(&sc->radio_led);
1072         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1073 }
1074
1075 static void ath_init_leds(struct ath_softc *sc)
1076 {
1077         char *trigger;
1078         int ret;
1079
1080         if (AR_SREV_9287(sc->sc_ah))
1081                 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1082         else
1083                 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1084
1085         /* Configure gpio 1 for output */
1086         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1087                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1088         /* LED off, active low */
1089         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1090
1091         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1092
1093         trigger = ieee80211_get_radio_led_name(sc->hw);
1094         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1095                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1096         ret = ath_register_led(sc, &sc->radio_led, trigger);
1097         sc->radio_led.led_type = ATH_LED_RADIO;
1098         if (ret)
1099                 goto fail;
1100
1101         trigger = ieee80211_get_assoc_led_name(sc->hw);
1102         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1103                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1104         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1105         sc->assoc_led.led_type = ATH_LED_ASSOC;
1106         if (ret)
1107                 goto fail;
1108
1109         trigger = ieee80211_get_tx_led_name(sc->hw);
1110         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1111                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1112         ret = ath_register_led(sc, &sc->tx_led, trigger);
1113         sc->tx_led.led_type = ATH_LED_TX;
1114         if (ret)
1115                 goto fail;
1116
1117         trigger = ieee80211_get_rx_led_name(sc->hw);
1118         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1119                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1120         ret = ath_register_led(sc, &sc->rx_led, trigger);
1121         sc->rx_led.led_type = ATH_LED_RX;
1122         if (ret)
1123                 goto fail;
1124
1125         return;
1126
1127 fail:
1128         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1129         ath_deinit_leds(sc);
1130 }
1131
1132 void ath_radio_enable(struct ath_softc *sc)
1133 {
1134         struct ath_hw *ah = sc->sc_ah;
1135         struct ieee80211_channel *channel = sc->hw->conf.channel;
1136         int r;
1137
1138         ath9k_ps_wakeup(sc);
1139         ath9k_hw_configpcipowersave(ah, 0, 0);
1140
1141         if (!ah->curchan)
1142                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1143
1144         spin_lock_bh(&sc->sc_resetlock);
1145         r = ath9k_hw_reset(ah, ah->curchan, false);
1146         if (r) {
1147                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1148                         "Unable to reset channel %u (%uMhz) ",
1149                         "reset status %d\n",
1150                         channel->center_freq, r);
1151         }
1152         spin_unlock_bh(&sc->sc_resetlock);
1153
1154         ath_update_txpow(sc);
1155         if (ath_startrecv(sc) != 0) {
1156                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1157                         "Unable to restart recv logic\n");
1158                 return;
1159         }
1160
1161         if (sc->sc_flags & SC_OP_BEACONS)
1162                 ath_beacon_config(sc, NULL);    /* restart beacons */
1163
1164         /* Re-Enable  interrupts */
1165         ath9k_hw_set_interrupts(ah, sc->imask);
1166
1167         /* Enable LED */
1168         ath9k_hw_cfg_output(ah, ah->led_pin,
1169                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1170         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1171
1172         ieee80211_wake_queues(sc->hw);
1173         ath9k_ps_restore(sc);
1174 }
1175
1176 void ath_radio_disable(struct ath_softc *sc)
1177 {
1178         struct ath_hw *ah = sc->sc_ah;
1179         struct ieee80211_channel *channel = sc->hw->conf.channel;
1180         int r;
1181
1182         ath9k_ps_wakeup(sc);
1183         ieee80211_stop_queues(sc->hw);
1184
1185         /* Disable LED */
1186         ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1187         ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1188
1189         /* Disable interrupts */
1190         ath9k_hw_set_interrupts(ah, 0);
1191
1192         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1193         ath_stoprecv(sc);               /* turn off frame recv */
1194         ath_flushrecv(sc);              /* flush recv queue */
1195
1196         if (!ah->curchan)
1197                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1198
1199         spin_lock_bh(&sc->sc_resetlock);
1200         r = ath9k_hw_reset(ah, ah->curchan, false);
1201         if (r) {
1202                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1203                         "Unable to reset channel %u (%uMhz) "
1204                         "reset status %d\n",
1205                         channel->center_freq, r);
1206         }
1207         spin_unlock_bh(&sc->sc_resetlock);
1208
1209         ath9k_hw_phy_disable(ah);
1210         ath9k_hw_configpcipowersave(ah, 1, 1);
1211         ath9k_ps_restore(sc);
1212         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1213 }
1214
1215 /*******************/
1216 /*      Rfkill     */
1217 /*******************/
1218
1219 static bool ath_is_rfkill_set(struct ath_softc *sc)
1220 {
1221         struct ath_hw *ah = sc->sc_ah;
1222
1223         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1224                                   ah->rfkill_polarity;
1225 }
1226
1227 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1228 {
1229         struct ath_wiphy *aphy = hw->priv;
1230         struct ath_softc *sc = aphy->sc;
1231         bool blocked = !!ath_is_rfkill_set(sc);
1232
1233         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1234 }
1235
1236 static void ath_start_rfkill_poll(struct ath_softc *sc)
1237 {
1238         struct ath_hw *ah = sc->sc_ah;
1239
1240         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1241                 wiphy_rfkill_start_polling(sc->hw->wiphy);
1242 }
1243
1244 void ath_cleanup(struct ath_softc *sc)
1245 {
1246         ath_detach(sc);
1247         free_irq(sc->irq, sc);
1248         ath_bus_cleanup(sc);
1249         kfree(sc->sec_wiphy);
1250         ieee80211_free_hw(sc->hw);
1251 }
1252
1253 void ath_detach(struct ath_softc *sc)
1254 {
1255         struct ieee80211_hw *hw = sc->hw;
1256         struct ath_hw *ah = sc->sc_ah;
1257         int i = 0;
1258
1259         ath9k_ps_wakeup(sc);
1260
1261         dev_dbg(sc->dev, "Detach ATH hw\n");
1262
1263         ath_deinit_leds(sc);
1264         wiphy_rfkill_stop_polling(sc->hw->wiphy);
1265
1266         for (i = 0; i < sc->num_sec_wiphy; i++) {
1267                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1268                 if (aphy == NULL)
1269                         continue;
1270                 sc->sec_wiphy[i] = NULL;
1271                 ieee80211_unregister_hw(aphy->hw);
1272                 ieee80211_free_hw(aphy->hw);
1273         }
1274         ieee80211_unregister_hw(hw);
1275         ath_rx_cleanup(sc);
1276         ath_tx_cleanup(sc);
1277
1278         tasklet_kill(&sc->intr_tq);
1279         tasklet_kill(&sc->bcon_tasklet);
1280
1281         if (!(sc->sc_flags & SC_OP_INVALID))
1282                 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1283
1284         /* cleanup tx queues */
1285         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1286                 if (ATH_TXQ_SETUP(sc, i))
1287                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1288
1289         if ((sc->btcoex.no_stomp_timer) &&
1290             ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1291                 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1292
1293         ath9k_hw_detach(ah);
1294         ath9k_exit_debug(ah);
1295         sc->sc_ah = NULL;
1296 }
1297
1298 static int ath9k_reg_notifier(struct wiphy *wiphy,
1299                               struct regulatory_request *request)
1300 {
1301         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1302         struct ath_wiphy *aphy = hw->priv;
1303         struct ath_softc *sc = aphy->sc;
1304         struct ath_regulatory *reg = &sc->common.regulatory;
1305
1306         return ath_reg_notifier_apply(wiphy, request, reg);
1307 }
1308
1309 /*
1310  * Detects if there is any priority bt traffic
1311  */
1312 static void ath_detect_bt_priority(struct ath_softc *sc)
1313 {
1314         struct ath_btcoex *btcoex = &sc->btcoex;
1315         struct ath_hw *ah = sc->sc_ah;
1316
1317         if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1318                 btcoex->bt_priority_cnt++;
1319
1320         if (time_after(jiffies, btcoex->bt_priority_time +
1321                         msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1322                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1323                         DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX,
1324                                 "BT priority traffic detected");
1325                         sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1326                 } else {
1327                         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1328                 }
1329
1330                 btcoex->bt_priority_cnt = 0;
1331                 btcoex->bt_priority_time = jiffies;
1332         }
1333 }
1334
1335 /*
1336  * Configures appropriate weight based on stomp type.
1337  */
1338 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1339                                   enum ath_stomp_type stomp_type)
1340 {
1341         struct ath_hw *ah = sc->sc_ah;
1342
1343         switch (stomp_type) {
1344         case ATH_BTCOEX_STOMP_ALL:
1345                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1346                                            AR_STOMP_ALL_WLAN_WGHT);
1347                 break;
1348         case ATH_BTCOEX_STOMP_LOW:
1349                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1350                                            AR_STOMP_LOW_WLAN_WGHT);
1351                 break;
1352         case ATH_BTCOEX_STOMP_NONE:
1353                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1354                                            AR_STOMP_NONE_WLAN_WGHT);
1355                 break;
1356         default:
1357                 DPRINTF(ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
1358                 break;
1359         }
1360
1361         ath9k_hw_btcoex_enable(ah);
1362 }
1363
1364 /*
1365  * This is the master bt coex timer which runs for every
1366  * 45ms, bt traffic will be given priority during 55% of this
1367  * period while wlan gets remaining 45%
1368  */
1369 static void ath_btcoex_period_timer(unsigned long data)
1370 {
1371         struct ath_softc *sc = (struct ath_softc *) data;
1372         struct ath_hw *ah = sc->sc_ah;
1373         struct ath_btcoex *btcoex = &sc->btcoex;
1374
1375         ath_detect_bt_priority(sc);
1376
1377         spin_lock_bh(&btcoex->btcoex_lock);
1378
1379         ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1380
1381         spin_unlock_bh(&btcoex->btcoex_lock);
1382
1383         if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1384                 if (btcoex->hw_timer_enabled)
1385                         ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
1386
1387                 ath_gen_timer_start(ah,
1388                         btcoex->no_stomp_timer,
1389                         (ath9k_hw_gettsf32(ah) +
1390                                 btcoex->btcoex_no_stomp),
1391                                 btcoex->btcoex_no_stomp * 10);
1392                 btcoex->hw_timer_enabled = true;
1393         }
1394
1395         mod_timer(&btcoex->period_timer, jiffies +
1396                                   msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1397 }
1398
1399 /*
1400  * Generic tsf based hw timer which configures weight
1401  * registers to time slice between wlan and bt traffic
1402  */
1403 static void ath_btcoex_no_stomp_timer(void *arg)
1404 {
1405         struct ath_softc *sc = (struct ath_softc *)arg;
1406         struct ath_hw *ah = sc->sc_ah;
1407         struct ath_btcoex *btcoex = &sc->btcoex;
1408
1409         DPRINTF(ah, ATH_DBG_BTCOEX, "no stomp timer running \n");
1410
1411         spin_lock_bh(&btcoex->btcoex_lock);
1412
1413         if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1414                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1415          else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1416                 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1417
1418         spin_unlock_bh(&btcoex->btcoex_lock);
1419 }
1420
1421 static int ath_init_btcoex_timer(struct ath_softc *sc)
1422 {
1423         struct ath_btcoex *btcoex = &sc->btcoex;
1424
1425         btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1426         btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1427                 btcoex->btcoex_period / 100;
1428
1429         setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1430                         (unsigned long) sc);
1431
1432         spin_lock_init(&btcoex->btcoex_lock);
1433
1434         btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1435                         ath_btcoex_no_stomp_timer,
1436                         ath_btcoex_no_stomp_timer,
1437                         (void *) sc, AR_FIRST_NDP_TIMER);
1438
1439         if (!btcoex->no_stomp_timer)
1440                 return -ENOMEM;
1441
1442         return 0;
1443 }
1444
1445 /*
1446  * Initialize and fill ath_softc, ath_sofct is the
1447  * "Software Carrier" struct. Historically it has existed
1448  * to allow the separation between hardware specific
1449  * variables (now in ath_hw) and driver specific variables.
1450  */
1451 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1452 {
1453         struct ath_hw *ah = NULL;
1454         int r = 0, i;
1455         int csz = 0;
1456         int qnum;
1457
1458         /* XXX: hardware will not be ready until ath_open() being called */
1459         sc->sc_flags |= SC_OP_INVALID;
1460
1461         spin_lock_init(&sc->wiphy_lock);
1462         spin_lock_init(&sc->sc_resetlock);
1463         spin_lock_init(&sc->sc_serial_rw);
1464         spin_lock_init(&sc->ani_lock);
1465         spin_lock_init(&sc->sc_pm_lock);
1466         mutex_init(&sc->mutex);
1467         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1468         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1469                      (unsigned long)sc);
1470
1471         /*
1472          * Cache line size is used to size and align various
1473          * structures used to communicate with the hardware.
1474          */
1475         ath_read_cachesize(sc, &csz);
1476         /* XXX assert csz is non-zero */
1477         sc->common.cachelsz = csz << 2; /* convert to bytes */
1478
1479         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1480         if (!ah) {
1481                 r = -ENOMEM;
1482                 goto bad_no_ah;
1483         }
1484
1485         ah->ah_sc = sc;
1486         ah->hw_version.devid = devid;
1487         ah->hw_version.subsysid = subsysid;
1488         sc->sc_ah = ah;
1489
1490         if (ath9k_init_debug(ah) < 0)
1491                 dev_err(sc->dev, "Unable to create debugfs files\n");
1492
1493         r = ath9k_hw_init(ah);
1494         if (r) {
1495                 DPRINTF(ah, ATH_DBG_FATAL,
1496                         "Unable to initialize hardware; "
1497                         "initialization status: %d\n", r);
1498                 goto bad;
1499         }
1500
1501         /* Get the hardware key cache size. */
1502         sc->keymax = ah->caps.keycache_size;
1503         if (sc->keymax > ATH_KEYMAX) {
1504                 DPRINTF(ah, ATH_DBG_ANY,
1505                         "Warning, using only %u entries in %u key cache\n",
1506                         ATH_KEYMAX, sc->keymax);
1507                 sc->keymax = ATH_KEYMAX;
1508         }
1509
1510         /*
1511          * Reset the key cache since some parts do not
1512          * reset the contents on initial power up.
1513          */
1514         for (i = 0; i < sc->keymax; i++)
1515                 ath9k_hw_keyreset(ah, (u16) i);
1516
1517         /* default to MONITOR mode */
1518         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1519
1520         /* Setup rate tables */
1521
1522         ath_rate_attach(sc);
1523         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1524         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1525
1526         /*
1527          * Allocate hardware transmit queues: one queue for
1528          * beacon frames and one data queue for each QoS
1529          * priority.  Note that the hal handles reseting
1530          * these queues at the needed time.
1531          */
1532         sc->beacon.beaconq = ath_beaconq_setup(ah);
1533         if (sc->beacon.beaconq == -1) {
1534                 DPRINTF(ah, ATH_DBG_FATAL,
1535                         "Unable to setup a beacon xmit queue\n");
1536                 r = -EIO;
1537                 goto bad2;
1538         }
1539         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1540         if (sc->beacon.cabq == NULL) {
1541                 DPRINTF(ah, ATH_DBG_FATAL,
1542                         "Unable to setup CAB xmit queue\n");
1543                 r = -EIO;
1544                 goto bad2;
1545         }
1546
1547         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1548         ath_cabq_update(sc);
1549
1550         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1551                 sc->tx.hwq_map[i] = -1;
1552
1553         /* Setup data queues */
1554         /* NB: ensure BK queue is the lowest priority h/w queue */
1555         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1556                 DPRINTF(ah, ATH_DBG_FATAL,
1557                         "Unable to setup xmit queue for BK traffic\n");
1558                 r = -EIO;
1559                 goto bad2;
1560         }
1561
1562         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1563                 DPRINTF(ah, ATH_DBG_FATAL,
1564                         "Unable to setup xmit queue for BE traffic\n");
1565                 r = -EIO;
1566                 goto bad2;
1567         }
1568         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1569                 DPRINTF(ah, ATH_DBG_FATAL,
1570                         "Unable to setup xmit queue for VI traffic\n");
1571                 r = -EIO;
1572                 goto bad2;
1573         }
1574         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1575                 DPRINTF(ah, ATH_DBG_FATAL,
1576                         "Unable to setup xmit queue for VO traffic\n");
1577                 r = -EIO;
1578                 goto bad2;
1579         }
1580
1581         /* Initializes the noise floor to a reasonable default value.
1582          * Later on this will be updated during ANI processing. */
1583
1584         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1585         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1586
1587         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1588                                    ATH9K_CIPHER_TKIP, NULL)) {
1589                 /*
1590                  * Whether we should enable h/w TKIP MIC.
1591                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1592                  * report WMM capable, so it's always safe to turn on
1593                  * TKIP MIC in this case.
1594                  */
1595                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1596                                        0, 1, NULL);
1597         }
1598
1599         /*
1600          * Check whether the separate key cache entries
1601          * are required to handle both tx+rx MIC keys.
1602          * With split mic keys the number of stations is limited
1603          * to 27 otherwise 59.
1604          */
1605         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1606                                    ATH9K_CIPHER_TKIP, NULL)
1607             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1608                                       ATH9K_CIPHER_MIC, NULL)
1609             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1610                                       0, NULL))
1611                 sc->splitmic = 1;
1612
1613         /* turn on mcast key search if possible */
1614         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1615                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1616                                              1, NULL);
1617
1618         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1619
1620         /* 11n Capabilities */
1621         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1622                 sc->sc_flags |= SC_OP_TXAGGR;
1623                 sc->sc_flags |= SC_OP_RXAGGR;
1624         }
1625
1626         sc->tx_chainmask = ah->caps.tx_chainmask;
1627         sc->rx_chainmask = ah->caps.rx_chainmask;
1628
1629         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1630         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1631
1632         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1633                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1634
1635         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1636
1637         /* initialize beacon slots */
1638         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1639                 sc->beacon.bslot[i] = NULL;
1640                 sc->beacon.bslot_aphy[i] = NULL;
1641         }
1642
1643         /* setup channels and rates */
1644
1645         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1646         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1647                 sc->rates[IEEE80211_BAND_2GHZ];
1648         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1649         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1650                 ARRAY_SIZE(ath9k_2ghz_chantable);
1651
1652         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1653                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1654                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1655                         sc->rates[IEEE80211_BAND_5GHZ];
1656                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1657                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1658                         ARRAY_SIZE(ath9k_5ghz_chantable);
1659         }
1660
1661         switch (ah->btcoex_hw.scheme) {
1662         case ATH_BTCOEX_CFG_NONE:
1663                 break;
1664         case ATH_BTCOEX_CFG_2WIRE:
1665                 ath9k_hw_btcoex_init_2wire(ah);
1666                 break;
1667         case ATH_BTCOEX_CFG_3WIRE:
1668                 ath9k_hw_btcoex_init_3wire(ah);
1669                 r = ath_init_btcoex_timer(sc);
1670                 if (r)
1671                         goto bad2;
1672                 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1673                 ath9k_hw_init_btcoex_hw(ah, qnum);
1674                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1675                 break;
1676         default:
1677                 WARN_ON(1);
1678                 break;
1679         }
1680
1681         return 0;
1682 bad2:
1683         /* cleanup tx queues */
1684         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1685                 if (ATH_TXQ_SETUP(sc, i))
1686                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1687 bad:
1688         ath9k_hw_detach(ah);
1689 bad_no_ah:
1690         ath9k_exit_debug(sc->sc_ah);
1691         sc->sc_ah = NULL;
1692
1693         return r;
1694 }
1695
1696 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1697 {
1698         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1699                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1700                 IEEE80211_HW_SIGNAL_DBM |
1701                 IEEE80211_HW_AMPDU_AGGREGATION |
1702                 IEEE80211_HW_SUPPORTS_PS |
1703                 IEEE80211_HW_PS_NULLFUNC_STACK |
1704                 IEEE80211_HW_SPECTRUM_MGMT;
1705
1706         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1707                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1708
1709         hw->wiphy->interface_modes =
1710                 BIT(NL80211_IFTYPE_AP) |
1711                 BIT(NL80211_IFTYPE_STATION) |
1712                 BIT(NL80211_IFTYPE_ADHOC) |
1713                 BIT(NL80211_IFTYPE_MESH_POINT);
1714
1715         hw->queues = 4;
1716         hw->max_rates = 4;
1717         hw->channel_change_time = 5000;
1718         hw->max_listen_interval = 10;
1719         /* Hardware supports 10 but we use 4 */
1720         hw->max_rate_tries = 4;
1721         hw->sta_data_size = sizeof(struct ath_node);
1722         hw->vif_data_size = sizeof(struct ath_vif);
1723
1724         hw->rate_control_algorithm = "ath9k_rate_control";
1725
1726         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1727                 &sc->sbands[IEEE80211_BAND_2GHZ];
1728         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1729                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1730                         &sc->sbands[IEEE80211_BAND_5GHZ];
1731 }
1732
1733 /* Device driver core initialization */
1734 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
1735 {
1736         struct ieee80211_hw *hw = sc->hw;
1737         struct ath_hw *ah;
1738         int error = 0, i;
1739         struct ath_regulatory *reg;
1740
1741         dev_dbg(sc->dev, "Attach ATH hw\n");
1742
1743         error = ath_init_softc(devid, sc, subsysid);
1744         if (error != 0)
1745                 return error;
1746
1747         ah = sc->sc_ah;
1748
1749         /* get mac address from hardware and set in mac80211 */
1750
1751         SET_IEEE80211_PERM_ADDR(hw, ah->macaddr);
1752
1753         ath_set_hw_capab(sc, hw);
1754
1755         error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
1756                               ath9k_reg_notifier);
1757         if (error)
1758                 return error;
1759
1760         reg = &sc->common.regulatory;
1761
1762         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1763                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1764                 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1765                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1766         }
1767
1768         /* initialize tx/rx engine */
1769         error = ath_tx_init(sc, ATH_TXBUF);
1770         if (error != 0)
1771                 goto error_attach;
1772
1773         error = ath_rx_init(sc, ATH_RXBUF);
1774         if (error != 0)
1775                 goto error_attach;
1776
1777         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1778         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1779         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1780
1781         error = ieee80211_register_hw(hw);
1782
1783         if (!ath_is_world_regd(reg)) {
1784                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1785                 if (error)
1786                         goto error_attach;
1787         }
1788
1789         /* Initialize LED control */
1790         ath_init_leds(sc);
1791
1792         ath_start_rfkill_poll(sc);
1793
1794         return 0;
1795
1796 error_attach:
1797         /* cleanup tx queues */
1798         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1799                 if (ATH_TXQ_SETUP(sc, i))
1800                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1801
1802         ath9k_hw_detach(ah);
1803         ath9k_exit_debug(ah);
1804         sc->sc_ah = NULL;
1805
1806         return error;
1807 }
1808
1809 int ath_reset(struct ath_softc *sc, bool retry_tx)
1810 {
1811         struct ath_hw *ah = sc->sc_ah;
1812         struct ieee80211_hw *hw = sc->hw;
1813         int r;
1814
1815         ath9k_hw_set_interrupts(ah, 0);
1816         ath_drain_all_txq(sc, retry_tx);
1817         ath_stoprecv(sc);
1818         ath_flushrecv(sc);
1819
1820         spin_lock_bh(&sc->sc_resetlock);
1821         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1822         if (r)
1823                 DPRINTF(ah, ATH_DBG_FATAL,
1824                         "Unable to reset hardware; reset status %d\n", r);
1825         spin_unlock_bh(&sc->sc_resetlock);
1826
1827         if (ath_startrecv(sc) != 0)
1828                 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
1829
1830         /*
1831          * We may be doing a reset in response to a request
1832          * that changes the channel so update any state that
1833          * might change as a result.
1834          */
1835         ath_cache_conf_rate(sc, &hw->conf);
1836
1837         ath_update_txpow(sc);
1838
1839         if (sc->sc_flags & SC_OP_BEACONS)
1840                 ath_beacon_config(sc, NULL);    /* restart beacons */
1841
1842         ath9k_hw_set_interrupts(ah, sc->imask);
1843
1844         if (retry_tx) {
1845                 int i;
1846                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1847                         if (ATH_TXQ_SETUP(sc, i)) {
1848                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1849                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1850                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1851                         }
1852                 }
1853         }
1854
1855         return r;
1856 }
1857
1858 /*
1859  *  This function will allocate both the DMA descriptor structure, and the
1860  *  buffers it contains.  These are used to contain the descriptors used
1861  *  by the system.
1862 */
1863 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1864                       struct list_head *head, const char *name,
1865                       int nbuf, int ndesc)
1866 {
1867 #define DS2PHYS(_dd, _ds)                                               \
1868         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1869 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1870 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1871
1872         struct ath_desc *ds;
1873         struct ath_buf *bf;
1874         int i, bsize, error;
1875
1876         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1877                 name, nbuf, ndesc);
1878
1879         INIT_LIST_HEAD(head);
1880         /* ath_desc must be a multiple of DWORDs */
1881         if ((sizeof(struct ath_desc) % 4) != 0) {
1882                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1883                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1884                 error = -ENOMEM;
1885                 goto fail;
1886         }
1887
1888         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1889
1890         /*
1891          * Need additional DMA memory because we can't use
1892          * descriptors that cross the 4K page boundary. Assume
1893          * one skipped descriptor per 4K page.
1894          */
1895         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1896                 u32 ndesc_skipped =
1897                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1898                 u32 dma_len;
1899
1900                 while (ndesc_skipped) {
1901                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1902                         dd->dd_desc_len += dma_len;
1903
1904                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1905                 };
1906         }
1907
1908         /* allocate descriptors */
1909         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1910                                          &dd->dd_desc_paddr, GFP_KERNEL);
1911         if (dd->dd_desc == NULL) {
1912                 error = -ENOMEM;
1913                 goto fail;
1914         }
1915         ds = dd->dd_desc;
1916         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1917                 name, ds, (u32) dd->dd_desc_len,
1918                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1919
1920         /* allocate buffers */
1921         bsize = sizeof(struct ath_buf) * nbuf;
1922         bf = kzalloc(bsize, GFP_KERNEL);
1923         if (bf == NULL) {
1924                 error = -ENOMEM;
1925                 goto fail2;
1926         }
1927         dd->dd_bufptr = bf;
1928
1929         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1930                 bf->bf_desc = ds;
1931                 bf->bf_daddr = DS2PHYS(dd, ds);
1932
1933                 if (!(sc->sc_ah->caps.hw_caps &
1934                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1935                         /*
1936                          * Skip descriptor addresses which can cause 4KB
1937                          * boundary crossing (addr + length) with a 32 dword
1938                          * descriptor fetch.
1939                          */
1940                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1941                                 ASSERT((caddr_t) bf->bf_desc <
1942                                        ((caddr_t) dd->dd_desc +
1943                                         dd->dd_desc_len));
1944
1945                                 ds += ndesc;
1946                                 bf->bf_desc = ds;
1947                                 bf->bf_daddr = DS2PHYS(dd, ds);
1948                         }
1949                 }
1950                 list_add_tail(&bf->list, head);
1951         }
1952         return 0;
1953 fail2:
1954         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1955                           dd->dd_desc_paddr);
1956 fail:
1957         memset(dd, 0, sizeof(*dd));
1958         return error;
1959 #undef ATH_DESC_4KB_BOUND_CHECK
1960 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1961 #undef DS2PHYS
1962 }
1963
1964 void ath_descdma_cleanup(struct ath_softc *sc,
1965                          struct ath_descdma *dd,
1966                          struct list_head *head)
1967 {
1968         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1969                           dd->dd_desc_paddr);
1970
1971         INIT_LIST_HEAD(head);
1972         kfree(dd->dd_bufptr);
1973         memset(dd, 0, sizeof(*dd));
1974 }
1975
1976 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1977 {
1978         int qnum;
1979
1980         switch (queue) {
1981         case 0:
1982                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1983                 break;
1984         case 1:
1985                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1986                 break;
1987         case 2:
1988                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1989                 break;
1990         case 3:
1991                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1992                 break;
1993         default:
1994                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1995                 break;
1996         }
1997
1998         return qnum;
1999 }
2000
2001 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2002 {
2003         int qnum;
2004
2005         switch (queue) {
2006         case ATH9K_WME_AC_VO:
2007                 qnum = 0;
2008                 break;
2009         case ATH9K_WME_AC_VI:
2010                 qnum = 1;
2011                 break;
2012         case ATH9K_WME_AC_BE:
2013                 qnum = 2;
2014                 break;
2015         case ATH9K_WME_AC_BK:
2016                 qnum = 3;
2017                 break;
2018         default:
2019                 qnum = -1;
2020                 break;
2021         }
2022
2023         return qnum;
2024 }
2025
2026 /* XXX: Remove me once we don't depend on ath9k_channel for all
2027  * this redundant data */
2028 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2029                            struct ath9k_channel *ichan)
2030 {
2031         struct ieee80211_channel *chan = hw->conf.channel;
2032         struct ieee80211_conf *conf = &hw->conf;
2033
2034         ichan->channel = chan->center_freq;
2035         ichan->chan = chan;
2036
2037         if (chan->band == IEEE80211_BAND_2GHZ) {
2038                 ichan->chanmode = CHANNEL_G;
2039                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2040         } else {
2041                 ichan->chanmode = CHANNEL_A;
2042                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2043         }
2044
2045         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2046
2047         if (conf_is_ht(conf)) {
2048                 if (conf_is_ht40(conf))
2049                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2050
2051                 ichan->chanmode = ath_get_extchanmode(sc, chan,
2052                                             conf->channel_type);
2053         }
2054 }
2055
2056 /**********************/
2057 /* mac80211 callbacks */
2058 /**********************/
2059
2060 /*
2061  * (Re)start btcoex timers
2062  */
2063 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2064 {
2065         struct ath_btcoex *btcoex = &sc->btcoex;
2066         struct ath_hw *ah = sc->sc_ah;
2067
2068         DPRINTF(ah, ATH_DBG_BTCOEX, "Starting btcoex timers");
2069
2070         /* make sure duty cycle timer is also stopped when resuming */
2071         if (btcoex->hw_timer_enabled)
2072                 ath_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2073
2074         btcoex->bt_priority_cnt = 0;
2075         btcoex->bt_priority_time = jiffies;
2076         sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2077
2078         mod_timer(&btcoex->period_timer, jiffies);
2079 }
2080
2081 static int ath9k_start(struct ieee80211_hw *hw)
2082 {
2083         struct ath_wiphy *aphy = hw->priv;
2084         struct ath_softc *sc = aphy->sc;
2085         struct ath_hw *ah = sc->sc_ah;
2086         struct ieee80211_channel *curchan = hw->conf.channel;
2087         struct ath9k_channel *init_channel;
2088         int r;
2089
2090         DPRINTF(ah, ATH_DBG_CONFIG, "Starting driver with "
2091                 "initial channel: %d MHz\n", curchan->center_freq);
2092
2093         mutex_lock(&sc->mutex);
2094
2095         if (ath9k_wiphy_started(sc)) {
2096                 if (sc->chan_idx == curchan->hw_value) {
2097                         /*
2098                          * Already on the operational channel, the new wiphy
2099                          * can be marked active.
2100                          */
2101                         aphy->state = ATH_WIPHY_ACTIVE;
2102                         ieee80211_wake_queues(hw);
2103                 } else {
2104                         /*
2105                          * Another wiphy is on another channel, start the new
2106                          * wiphy in paused state.
2107                          */
2108                         aphy->state = ATH_WIPHY_PAUSED;
2109                         ieee80211_stop_queues(hw);
2110                 }
2111                 mutex_unlock(&sc->mutex);
2112                 return 0;
2113         }
2114         aphy->state = ATH_WIPHY_ACTIVE;
2115
2116         /* setup initial channel */
2117
2118         sc->chan_idx = curchan->hw_value;
2119
2120         init_channel = ath_get_curchannel(sc, hw);
2121
2122         /* Reset SERDES registers */
2123         ath9k_hw_configpcipowersave(ah, 0, 0);
2124
2125         /*
2126          * The basic interface to setting the hardware in a good
2127          * state is ``reset''.  On return the hardware is known to
2128          * be powered up and with interrupts disabled.  This must
2129          * be followed by initialization of the appropriate bits
2130          * and then setup of the interrupt mask.
2131          */
2132         spin_lock_bh(&sc->sc_resetlock);
2133         r = ath9k_hw_reset(ah, init_channel, false);
2134         if (r) {
2135                 DPRINTF(ah, ATH_DBG_FATAL,
2136                         "Unable to reset hardware; reset status %d "
2137                         "(freq %u MHz)\n", r,
2138                         curchan->center_freq);
2139                 spin_unlock_bh(&sc->sc_resetlock);
2140                 goto mutex_unlock;
2141         }
2142         spin_unlock_bh(&sc->sc_resetlock);
2143
2144         /*
2145          * This is needed only to setup initial state
2146          * but it's best done after a reset.
2147          */
2148         ath_update_txpow(sc);
2149
2150         /*
2151          * Setup the hardware after reset:
2152          * The receive engine is set going.
2153          * Frame transmit is handled entirely
2154          * in the frame output path; there's nothing to do
2155          * here except setup the interrupt mask.
2156          */
2157         if (ath_startrecv(sc) != 0) {
2158                 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
2159                 r = -EIO;
2160                 goto mutex_unlock;
2161         }
2162
2163         /* Setup our intr mask. */
2164         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2165                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2166                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2167
2168         if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2169                 sc->imask |= ATH9K_INT_GTT;
2170
2171         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2172                 sc->imask |= ATH9K_INT_CST;
2173
2174         ath_cache_conf_rate(sc, &hw->conf);
2175
2176         sc->sc_flags &= ~SC_OP_INVALID;
2177
2178         /* Disable BMISS interrupt when we're not associated */
2179         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2180         ath9k_hw_set_interrupts(ah, sc->imask);
2181
2182         ieee80211_wake_queues(hw);
2183
2184         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2185
2186         if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2187             !ah->btcoex_hw.enabled) {
2188                 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2189                                            AR_STOMP_LOW_WLAN_WGHT);
2190                 ath9k_hw_btcoex_enable(ah);
2191
2192                 ath_pcie_aspm_disable(sc);
2193                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2194                         ath9k_btcoex_timer_resume(sc);
2195         }
2196
2197 mutex_unlock:
2198         mutex_unlock(&sc->mutex);
2199
2200         return r;
2201 }
2202
2203 static int ath9k_tx(struct ieee80211_hw *hw,
2204                     struct sk_buff *skb)
2205 {
2206         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2207         struct ath_wiphy *aphy = hw->priv;
2208         struct ath_softc *sc = aphy->sc;
2209         struct ath_tx_control txctl;
2210         int hdrlen, padsize;
2211
2212         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2213                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2214                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2215                 goto exit;
2216         }
2217
2218         if (sc->ps_enabled) {
2219                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2220                 /*
2221                  * mac80211 does not set PM field for normal data frames, so we
2222                  * need to update that based on the current PS mode.
2223                  */
2224                 if (ieee80211_is_data(hdr->frame_control) &&
2225                     !ieee80211_is_nullfunc(hdr->frame_control) &&
2226                     !ieee80211_has_pm(hdr->frame_control)) {
2227                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame "
2228                                 "while in PS mode\n");
2229                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2230                 }
2231         }
2232
2233         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2234                 /*
2235                  * We are using PS-Poll and mac80211 can request TX while in
2236                  * power save mode. Need to wake up hardware for the TX to be
2237                  * completed and if needed, also for RX of buffered frames.
2238                  */
2239                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2240                 ath9k_ps_wakeup(sc);
2241                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2242                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2243                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a "
2244                                 "buffered frame\n");
2245                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2246                 } else {
2247                         DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n");
2248                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2249                 }
2250                 /*
2251                  * The actual restore operation will happen only after
2252                  * the sc_flags bit is cleared. We are just dropping
2253                  * the ps_usecount here.
2254                  */
2255                 ath9k_ps_restore(sc);
2256         }
2257
2258         memset(&txctl, 0, sizeof(struct ath_tx_control));
2259
2260         /*
2261          * As a temporary workaround, assign seq# here; this will likely need
2262          * to be cleaned up to work better with Beacon transmission and virtual
2263          * BSSes.
2264          */
2265         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2266                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2267                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2268                         sc->tx.seq_no += 0x10;
2269                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2270                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2271         }
2272
2273         /* Add the padding after the header if this is not already done */
2274         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2275         if (hdrlen & 3) {
2276                 padsize = hdrlen % 4;
2277                 if (skb_headroom(skb) < padsize)
2278                         return -1;
2279                 skb_push(skb, padsize);
2280                 memmove(skb->data, skb->data + padsize, hdrlen);
2281         }
2282
2283         /* Check if a tx queue is available */
2284
2285         txctl.txq = ath_test_get_txq(sc, skb);
2286         if (!txctl.txq)
2287                 goto exit;
2288
2289         DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2290
2291         if (ath_tx_start(hw, skb, &txctl) != 0) {
2292                 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n");
2293                 goto exit;
2294         }
2295
2296         return 0;
2297 exit:
2298         dev_kfree_skb_any(skb);
2299         return 0;
2300 }
2301
2302 /*
2303  * Pause btcoex timer and bt duty cycle timer
2304  */
2305 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2306 {
2307         struct ath_btcoex *btcoex = &sc->btcoex;
2308         struct ath_hw *ah = sc->sc_ah;
2309
2310         del_timer_sync(&btcoex->period_timer);
2311
2312         if (btcoex->hw_timer_enabled)
2313                 ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
2314
2315         btcoex->hw_timer_enabled = false;
2316 }
2317
2318 static void ath9k_stop(struct ieee80211_hw *hw)
2319 {
2320         struct ath_wiphy *aphy = hw->priv;
2321         struct ath_softc *sc = aphy->sc;
2322         struct ath_hw *ah = sc->sc_ah;
2323
2324         mutex_lock(&sc->mutex);
2325
2326         aphy->state = ATH_WIPHY_INACTIVE;
2327
2328         cancel_delayed_work_sync(&sc->ath_led_blink_work);
2329         cancel_delayed_work_sync(&sc->tx_complete_work);
2330
2331         if (!sc->num_sec_wiphy) {
2332                 cancel_delayed_work_sync(&sc->wiphy_work);
2333                 cancel_work_sync(&sc->chan_work);
2334         }
2335
2336         if (sc->sc_flags & SC_OP_INVALID) {
2337                 DPRINTF(ah, ATH_DBG_ANY, "Device not present\n");
2338                 mutex_unlock(&sc->mutex);
2339                 return;
2340         }
2341
2342         if (ath9k_wiphy_started(sc)) {
2343                 mutex_unlock(&sc->mutex);
2344                 return; /* another wiphy still in use */
2345         }
2346
2347         if (ah->btcoex_hw.enabled) {
2348                 ath9k_hw_btcoex_disable(ah);
2349                 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2350                         ath9k_btcoex_timer_pause(sc);
2351         }
2352
2353         /* make sure h/w will not generate any interrupt
2354          * before setting the invalid flag. */
2355         ath9k_hw_set_interrupts(ah, 0);
2356
2357         if (!(sc->sc_flags & SC_OP_INVALID)) {
2358                 ath_drain_all_txq(sc, false);
2359                 ath_stoprecv(sc);
2360                 ath9k_hw_phy_disable(ah);
2361         } else
2362                 sc->rx.rxlink = NULL;
2363
2364         /* disable HAL and put h/w to sleep */
2365         ath9k_hw_disable(ah);
2366         ath9k_hw_configpcipowersave(ah, 1, 1);
2367         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
2368
2369         sc->sc_flags |= SC_OP_INVALID;
2370
2371         mutex_unlock(&sc->mutex);
2372
2373         DPRINTF(ah, ATH_DBG_CONFIG, "Driver halt\n");
2374 }
2375
2376 static int ath9k_add_interface(struct ieee80211_hw *hw,
2377                                struct ieee80211_if_init_conf *conf)
2378 {
2379         struct ath_wiphy *aphy = hw->priv;
2380         struct ath_softc *sc = aphy->sc;
2381         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2382         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2383         int ret = 0;
2384
2385         mutex_lock(&sc->mutex);
2386
2387         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2388             sc->nvifs > 0) {
2389                 ret = -ENOBUFS;
2390                 goto out;
2391         }
2392
2393         switch (conf->type) {
2394         case NL80211_IFTYPE_STATION:
2395                 ic_opmode = NL80211_IFTYPE_STATION;
2396                 break;
2397         case NL80211_IFTYPE_ADHOC:
2398         case NL80211_IFTYPE_AP:
2399         case NL80211_IFTYPE_MESH_POINT:
2400                 if (sc->nbcnvifs >= ATH_BCBUF) {
2401                         ret = -ENOBUFS;
2402                         goto out;
2403                 }
2404                 ic_opmode = conf->type;
2405                 break;
2406         default:
2407                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
2408                         "Interface type %d not yet supported\n", conf->type);
2409                 ret = -EOPNOTSUPP;
2410                 goto out;
2411         }
2412
2413         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2414
2415         /* Set the VIF opmode */
2416         avp->av_opmode = ic_opmode;
2417         avp->av_bslot = -1;
2418
2419         sc->nvifs++;
2420
2421         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2422                 ath9k_set_bssid_mask(hw);
2423
2424         if (sc->nvifs > 1)
2425                 goto out; /* skip global settings for secondary vif */
2426
2427         if (ic_opmode == NL80211_IFTYPE_AP) {
2428                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2429                 sc->sc_flags |= SC_OP_TSF_RESET;
2430         }
2431
2432         /* Set the device opmode */
2433         sc->sc_ah->opmode = ic_opmode;
2434
2435         /*
2436          * Enable MIB interrupts when there are hardware phy counters.
2437          * Note we only do this (at the moment) for station mode.
2438          */
2439         if ((conf->type == NL80211_IFTYPE_STATION) ||
2440             (conf->type == NL80211_IFTYPE_ADHOC) ||
2441             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2442                 sc->imask |= ATH9K_INT_MIB;
2443                 sc->imask |= ATH9K_INT_TSFOOR;
2444         }
2445
2446         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2447
2448         if (conf->type == NL80211_IFTYPE_AP    ||
2449             conf->type == NL80211_IFTYPE_ADHOC ||
2450             conf->type == NL80211_IFTYPE_MONITOR)
2451                 ath_start_ani(sc);
2452
2453 out:
2454         mutex_unlock(&sc->mutex);
2455         return ret;
2456 }
2457
2458 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2459                                    struct ieee80211_if_init_conf *conf)
2460 {
2461         struct ath_wiphy *aphy = hw->priv;
2462         struct ath_softc *sc = aphy->sc;
2463         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2464         int i;
2465
2466         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n");
2467
2468         mutex_lock(&sc->mutex);
2469
2470         /* Stop ANI */
2471         del_timer_sync(&sc->ani.timer);
2472
2473         /* Reclaim beacon resources */
2474         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2475             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2476             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2477                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2478                 ath_beacon_return(sc, avp);
2479         }
2480
2481         sc->sc_flags &= ~SC_OP_BEACONS;
2482
2483         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2484                 if (sc->beacon.bslot[i] == conf->vif) {
2485                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2486                                "slot\n", __func__);
2487                         sc->beacon.bslot[i] = NULL;
2488                         sc->beacon.bslot_aphy[i] = NULL;
2489                 }
2490         }
2491
2492         sc->nvifs--;
2493
2494         mutex_unlock(&sc->mutex);
2495 }
2496
2497 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2498 {
2499         struct ath_wiphy *aphy = hw->priv;
2500         struct ath_softc *sc = aphy->sc;
2501         struct ieee80211_conf *conf = &hw->conf;
2502         struct ath_hw *ah = sc->sc_ah;
2503         bool all_wiphys_idle = false, disable_radio = false;
2504
2505         mutex_lock(&sc->mutex);
2506
2507         /* Leave this as the first check */
2508         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2509
2510                 spin_lock_bh(&sc->wiphy_lock);
2511                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
2512                 spin_unlock_bh(&sc->wiphy_lock);
2513
2514                 if (conf->flags & IEEE80211_CONF_IDLE){
2515                         if (all_wiphys_idle)
2516                                 disable_radio = true;
2517                 }
2518                 else if (all_wiphys_idle) {
2519                         ath_radio_enable(sc);
2520                         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2521                                 "not-idle: enabling radio\n");
2522                 }
2523         }
2524
2525         if (changed & IEEE80211_CONF_CHANGE_PS) {
2526                 if (conf->flags & IEEE80211_CONF_PS) {
2527                         if (!(ah->caps.hw_caps &
2528                               ATH9K_HW_CAP_AUTOSLEEP)) {
2529                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2530                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2531                                         ath9k_hw_set_interrupts(sc->sc_ah,
2532                                                         sc->imask);
2533                                 }
2534                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2535                         }
2536                         sc->ps_enabled = true;
2537                 } else {
2538                         sc->ps_enabled = false;
2539                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2540                         if (!(ah->caps.hw_caps &
2541                               ATH9K_HW_CAP_AUTOSLEEP)) {
2542                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2543                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2544                                                   SC_OP_WAIT_FOR_CAB |
2545                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2546                                                   SC_OP_WAIT_FOR_TX_ACK);
2547                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2548                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2549                                         ath9k_hw_set_interrupts(sc->sc_ah,
2550                                                         sc->imask);
2551                                 }
2552                         }
2553                 }
2554         }
2555
2556         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2557                 struct ieee80211_channel *curchan = hw->conf.channel;
2558                 int pos = curchan->hw_value;
2559
2560                 aphy->chan_idx = pos;
2561                 aphy->chan_is_ht = conf_is_ht(conf);
2562
2563                 if (aphy->state == ATH_WIPHY_SCAN ||
2564                     aphy->state == ATH_WIPHY_ACTIVE)
2565                         ath9k_wiphy_pause_all_forced(sc, aphy);
2566                 else {
2567                         /*
2568                          * Do not change operational channel based on a paused
2569                          * wiphy changes.
2570                          */
2571                         goto skip_chan_change;
2572                 }
2573
2574                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2575                         curchan->center_freq);
2576
2577                 /* XXX: remove me eventualy */
2578                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2579
2580                 ath_update_chainmask(sc, conf_is_ht(conf));
2581
2582                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2583                         DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n");
2584                         mutex_unlock(&sc->mutex);
2585                         return -EINVAL;
2586                 }
2587         }
2588
2589 skip_chan_change:
2590         if (changed & IEEE80211_CONF_CHANGE_POWER)
2591                 sc->config.txpowlimit = 2 * conf->power_level;
2592
2593         if (disable_radio) {
2594                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n");
2595                 ath_radio_disable(sc);
2596         }
2597
2598         mutex_unlock(&sc->mutex);
2599
2600         return 0;
2601 }
2602
2603 #define SUPPORTED_FILTERS                       \
2604         (FIF_PROMISC_IN_BSS |                   \
2605         FIF_ALLMULTI |                          \
2606         FIF_CONTROL |                           \
2607         FIF_PSPOLL |                            \
2608         FIF_OTHER_BSS |                         \
2609         FIF_BCN_PRBRESP_PROMISC |               \
2610         FIF_FCSFAIL)
2611
2612 /* FIXME: sc->sc_full_reset ? */
2613 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2614                                    unsigned int changed_flags,
2615                                    unsigned int *total_flags,
2616                                    u64 multicast)
2617 {
2618         struct ath_wiphy *aphy = hw->priv;
2619         struct ath_softc *sc = aphy->sc;
2620         u32 rfilt;
2621
2622         changed_flags &= SUPPORTED_FILTERS;
2623         *total_flags &= SUPPORTED_FILTERS;
2624
2625         sc->rx.rxfilter = *total_flags;
2626         ath9k_ps_wakeup(sc);
2627         rfilt = ath_calcrxfilter(sc);
2628         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2629         ath9k_ps_restore(sc);
2630
2631         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
2632 }
2633
2634 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2635                              struct ieee80211_vif *vif,
2636                              enum sta_notify_cmd cmd,
2637                              struct ieee80211_sta *sta)
2638 {
2639         struct ath_wiphy *aphy = hw->priv;
2640         struct ath_softc *sc = aphy->sc;
2641
2642         switch (cmd) {
2643         case STA_NOTIFY_ADD:
2644                 ath_node_attach(sc, sta);
2645                 break;
2646         case STA_NOTIFY_REMOVE:
2647                 ath_node_detach(sc, sta);
2648                 break;
2649         default:
2650                 break;
2651         }
2652 }
2653
2654 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2655                          const struct ieee80211_tx_queue_params *params)
2656 {
2657         struct ath_wiphy *aphy = hw->priv;
2658         struct ath_softc *sc = aphy->sc;
2659         struct ath9k_tx_queue_info qi;
2660         int ret = 0, qnum;
2661
2662         if (queue >= WME_NUM_AC)
2663                 return 0;
2664
2665         mutex_lock(&sc->mutex);
2666
2667         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2668
2669         qi.tqi_aifs = params->aifs;
2670         qi.tqi_cwmin = params->cw_min;
2671         qi.tqi_cwmax = params->cw_max;
2672         qi.tqi_burstTime = params->txop;
2673         qnum = ath_get_hal_qnum(queue, sc);
2674
2675         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2676                 "Configure tx [queue/halq] [%d/%d],  "
2677                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2678                 queue, qnum, params->aifs, params->cw_min,
2679                 params->cw_max, params->txop);
2680
2681         ret = ath_txq_update(sc, qnum, &qi);
2682         if (ret)
2683                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n");
2684
2685         mutex_unlock(&sc->mutex);
2686
2687         return ret;
2688 }
2689
2690 static int ath9k_set_key(struct ieee80211_hw *hw,
2691                          enum set_key_cmd cmd,
2692                          struct ieee80211_vif *vif,
2693                          struct ieee80211_sta *sta,
2694                          struct ieee80211_key_conf *key)
2695 {
2696         struct ath_wiphy *aphy = hw->priv;
2697         struct ath_softc *sc = aphy->sc;
2698         int ret = 0;
2699
2700         if (modparam_nohwcrypt)
2701                 return -ENOSPC;
2702
2703         mutex_lock(&sc->mutex);
2704         ath9k_ps_wakeup(sc);
2705         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n");
2706
2707         switch (cmd) {
2708         case SET_KEY:
2709                 ret = ath_key_config(sc, vif, sta, key);
2710                 if (ret >= 0) {
2711                         key->hw_key_idx = ret;
2712                         /* push IV and Michael MIC generation to stack */
2713                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2714                         if (key->alg == ALG_TKIP)
2715                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2716                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2717                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2718                         ret = 0;
2719                 }
2720                 break;
2721         case DISABLE_KEY:
2722                 ath_key_delete(sc, key);
2723                 break;
2724         default:
2725                 ret = -EINVAL;
2726         }
2727
2728         ath9k_ps_restore(sc);
2729         mutex_unlock(&sc->mutex);
2730
2731         return ret;
2732 }
2733
2734 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2735                                    struct ieee80211_vif *vif,
2736                                    struct ieee80211_bss_conf *bss_conf,
2737                                    u32 changed)
2738 {
2739         struct ath_wiphy *aphy = hw->priv;
2740         struct ath_softc *sc = aphy->sc;
2741         struct ath_hw *ah = sc->sc_ah;
2742         struct ath_vif *avp = (void *)vif->drv_priv;
2743         u32 rfilt = 0;
2744         int error, i;
2745
2746         mutex_lock(&sc->mutex);
2747
2748         /*
2749          * TODO: Need to decide which hw opmode to use for
2750          *       multi-interface cases
2751          * XXX: This belongs into add_interface!
2752          */
2753         if (vif->type == NL80211_IFTYPE_AP &&
2754             ah->opmode != NL80211_IFTYPE_AP) {
2755                 ah->opmode = NL80211_IFTYPE_STATION;
2756                 ath9k_hw_setopmode(ah);
2757                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2758                 sc->curaid = 0;
2759                 ath9k_hw_write_associd(sc);
2760                 /* Request full reset to get hw opmode changed properly */
2761                 sc->sc_flags |= SC_OP_FULL_RESET;
2762         }
2763
2764         if ((changed & BSS_CHANGED_BSSID) &&
2765             !is_zero_ether_addr(bss_conf->bssid)) {
2766                 switch (vif->type) {
2767                 case NL80211_IFTYPE_STATION:
2768                 case NL80211_IFTYPE_ADHOC:
2769                 case NL80211_IFTYPE_MESH_POINT:
2770                         /* Set BSSID */
2771                         memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2772                         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2773                         sc->curaid = 0;
2774                         ath9k_hw_write_associd(sc);
2775
2776                         /* Set aggregation protection mode parameters */
2777                         sc->config.ath_aggr_prot = 0;
2778
2779                         DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2780                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2781                                 rfilt, sc->curbssid, sc->curaid);
2782
2783                         /* need to reconfigure the beacon */
2784                         sc->sc_flags &= ~SC_OP_BEACONS ;
2785
2786                         break;
2787                 default:
2788                         break;
2789                 }
2790         }
2791
2792         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2793             (vif->type == NL80211_IFTYPE_AP) ||
2794             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2795                 if ((changed & BSS_CHANGED_BEACON) ||
2796                     (changed & BSS_CHANGED_BEACON_ENABLED &&
2797                      bss_conf->enable_beacon)) {
2798                         /*
2799                          * Allocate and setup the beacon frame.
2800                          *
2801                          * Stop any previous beacon DMA.  This may be
2802                          * necessary, for example, when an ibss merge
2803                          * causes reconfiguration; we may be called
2804                          * with beacon transmission active.
2805                          */
2806                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2807
2808                         error = ath_beacon_alloc(aphy, vif);
2809                         if (!error)
2810                                 ath_beacon_config(sc, vif);
2811                 }
2812         }
2813
2814         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2815         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2816                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2817                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2818                                 ath9k_hw_keysetmac(sc->sc_ah,
2819                                                    (u16)i,
2820                                                    sc->curbssid);
2821         }
2822
2823         /* Only legacy IBSS for now */
2824         if (vif->type == NL80211_IFTYPE_ADHOC)
2825                 ath_update_chainmask(sc, 0);
2826
2827         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2828                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2829                         bss_conf->use_short_preamble);
2830                 if (bss_conf->use_short_preamble)
2831                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2832                 else
2833                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2834         }
2835
2836         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2837                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2838                         bss_conf->use_cts_prot);
2839                 if (bss_conf->use_cts_prot &&
2840                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2841                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2842                 else
2843                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2844         }
2845
2846         if (changed & BSS_CHANGED_ASSOC) {
2847                 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2848                         bss_conf->assoc);
2849                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2850         }
2851
2852         /*
2853          * The HW TSF has to be reset when the beacon interval changes.
2854          * We set the flag here, and ath_beacon_config_ap() would take this
2855          * into account when it gets called through the subsequent
2856          * config_interface() call - with IFCC_BEACON in the changed field.
2857          */
2858
2859         if (changed & BSS_CHANGED_BEACON_INT) {
2860                 sc->sc_flags |= SC_OP_TSF_RESET;
2861                 sc->beacon_interval = bss_conf->beacon_int;
2862         }
2863
2864         mutex_unlock(&sc->mutex);
2865 }
2866
2867 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2868 {
2869         u64 tsf;
2870         struct ath_wiphy *aphy = hw->priv;
2871         struct ath_softc *sc = aphy->sc;
2872
2873         mutex_lock(&sc->mutex);
2874         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2875         mutex_unlock(&sc->mutex);
2876
2877         return tsf;
2878 }
2879
2880 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2881 {
2882         struct ath_wiphy *aphy = hw->priv;
2883         struct ath_softc *sc = aphy->sc;
2884
2885         mutex_lock(&sc->mutex);
2886         ath9k_hw_settsf64(sc->sc_ah, tsf);
2887         mutex_unlock(&sc->mutex);
2888 }
2889
2890 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2891 {
2892         struct ath_wiphy *aphy = hw->priv;
2893         struct ath_softc *sc = aphy->sc;
2894
2895         mutex_lock(&sc->mutex);
2896         ath9k_hw_reset_tsf(sc->sc_ah);
2897         mutex_unlock(&sc->mutex);
2898 }
2899
2900 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2901                               enum ieee80211_ampdu_mlme_action action,
2902                               struct ieee80211_sta *sta,
2903                               u16 tid, u16 *ssn)
2904 {
2905         struct ath_wiphy *aphy = hw->priv;
2906         struct ath_softc *sc = aphy->sc;
2907         int ret = 0;
2908
2909         switch (action) {
2910         case IEEE80211_AMPDU_RX_START:
2911                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2912                         ret = -ENOTSUPP;
2913                 break;
2914         case IEEE80211_AMPDU_RX_STOP:
2915                 break;
2916         case IEEE80211_AMPDU_TX_START:
2917                 ath_tx_aggr_start(sc, sta, tid, ssn);
2918                 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2919                 break;
2920         case IEEE80211_AMPDU_TX_STOP:
2921                 ath_tx_aggr_stop(sc, sta, tid);
2922                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2923                 break;
2924         case IEEE80211_AMPDU_TX_OPERATIONAL:
2925                 ath_tx_aggr_resume(sc, sta, tid);
2926                 break;
2927         default:
2928                 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2929         }
2930
2931         return ret;
2932 }
2933
2934 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2935 {
2936         struct ath_wiphy *aphy = hw->priv;
2937         struct ath_softc *sc = aphy->sc;
2938
2939         mutex_lock(&sc->mutex);
2940         if (ath9k_wiphy_scanning(sc)) {
2941                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2942                        "same time\n");
2943                 /*
2944                  * Do not allow the concurrent scanning state for now. This
2945                  * could be improved with scanning control moved into ath9k.
2946                  */
2947                 mutex_unlock(&sc->mutex);
2948                 return;
2949         }
2950
2951         aphy->state = ATH_WIPHY_SCAN;
2952         ath9k_wiphy_pause_all_forced(sc, aphy);
2953
2954         spin_lock_bh(&sc->ani_lock);
2955         sc->sc_flags |= SC_OP_SCANNING;
2956         spin_unlock_bh(&sc->ani_lock);
2957         mutex_unlock(&sc->mutex);
2958 }
2959
2960 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2961 {
2962         struct ath_wiphy *aphy = hw->priv;
2963         struct ath_softc *sc = aphy->sc;
2964
2965         mutex_lock(&sc->mutex);
2966         spin_lock_bh(&sc->ani_lock);
2967         aphy->state = ATH_WIPHY_ACTIVE;
2968         sc->sc_flags &= ~SC_OP_SCANNING;
2969         sc->sc_flags |= SC_OP_FULL_RESET;
2970         spin_unlock_bh(&sc->ani_lock);
2971         ath_beacon_config(sc, NULL);
2972         mutex_unlock(&sc->mutex);
2973 }
2974
2975 struct ieee80211_ops ath9k_ops = {
2976         .tx                 = ath9k_tx,
2977         .start              = ath9k_start,
2978         .stop               = ath9k_stop,
2979         .add_interface      = ath9k_add_interface,
2980         .remove_interface   = ath9k_remove_interface,
2981         .config             = ath9k_config,
2982         .configure_filter   = ath9k_configure_filter,
2983         .sta_notify         = ath9k_sta_notify,
2984         .conf_tx            = ath9k_conf_tx,
2985         .bss_info_changed   = ath9k_bss_info_changed,
2986         .set_key            = ath9k_set_key,
2987         .get_tsf            = ath9k_get_tsf,
2988         .set_tsf            = ath9k_set_tsf,
2989         .reset_tsf          = ath9k_reset_tsf,
2990         .ampdu_action       = ath9k_ampdu_action,
2991         .sw_scan_start      = ath9k_sw_scan_start,
2992         .sw_scan_complete   = ath9k_sw_scan_complete,
2993         .rfkill_poll        = ath9k_rfkill_poll_state,
2994 };
2995
2996 static struct {
2997         u32 version;
2998         const char * name;
2999 } ath_mac_bb_names[] = {
3000         { AR_SREV_VERSION_5416_PCI,     "5416" },
3001         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3002         { AR_SREV_VERSION_9100,         "9100" },
3003         { AR_SREV_VERSION_9160,         "9160" },
3004         { AR_SREV_VERSION_9280,         "9280" },
3005         { AR_SREV_VERSION_9285,         "9285" },
3006         { AR_SREV_VERSION_9287,         "9287" }
3007 };
3008
3009 static struct {
3010         u16 version;
3011         const char * name;
3012 } ath_rf_names[] = {
3013         { 0,                            "5133" },
3014         { AR_RAD5133_SREV_MAJOR,        "5133" },
3015         { AR_RAD5122_SREV_MAJOR,        "5122" },
3016         { AR_RAD2133_SREV_MAJOR,        "2133" },
3017         { AR_RAD2122_SREV_MAJOR,        "2122" }
3018 };
3019
3020 /*
3021  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3022  */
3023 const char *
3024 ath_mac_bb_name(u32 mac_bb_version)
3025 {
3026         int i;
3027
3028         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3029                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3030                         return ath_mac_bb_names[i].name;
3031                 }
3032         }
3033
3034         return "????";
3035 }
3036
3037 /*
3038  * Return the RF name. "????" is returned if the RF is unknown.
3039  */
3040 const char *
3041 ath_rf_name(u16 rf_version)
3042 {
3043         int i;
3044
3045         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3046                 if (ath_rf_names[i].version == rf_version) {
3047                         return ath_rf_names[i].name;
3048                 }
3049         }
3050
3051         return "????";
3052 }
3053
3054 static int __init ath9k_init(void)
3055 {
3056         int error;
3057
3058         /* Register rate control algorithm */
3059         error = ath_rate_control_register();
3060         if (error != 0) {
3061                 printk(KERN_ERR
3062                         "ath9k: Unable to register rate control "
3063                         "algorithm: %d\n",
3064                         error);
3065                 goto err_out;
3066         }
3067
3068         error = ath9k_debug_create_root();
3069         if (error) {
3070                 printk(KERN_ERR
3071                         "ath9k: Unable to create debugfs root: %d\n",
3072                         error);
3073                 goto err_rate_unregister;
3074         }
3075
3076         error = ath_pci_init();
3077         if (error < 0) {
3078                 printk(KERN_ERR
3079                         "ath9k: No PCI devices found, driver not installed.\n");
3080                 error = -ENODEV;
3081                 goto err_remove_root;
3082         }
3083
3084         error = ath_ahb_init();
3085         if (error < 0) {
3086                 error = -ENODEV;
3087                 goto err_pci_exit;
3088         }
3089
3090         return 0;
3091
3092  err_pci_exit:
3093         ath_pci_exit();
3094
3095  err_remove_root:
3096         ath9k_debug_remove_root();
3097  err_rate_unregister:
3098         ath_rate_control_unregister();
3099  err_out:
3100         return error;
3101 }
3102 module_init(ath9k_init);
3103
3104 static void __exit ath9k_exit(void)
3105 {
3106         ath_ahb_exit();
3107         ath_pci_exit();
3108         ath9k_debug_remove_root();
3109         ath_rate_control_unregister();
3110         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
3111 }
3112 module_exit(ath9k_exit);