ath9k: break up hw initialization into a few more helpers
[linux-2.6.git] / drivers / net / wireless / ath / ath9k / hw.c
1 /*
2  * Copyright (c) 2008-2009 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK            22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33                               enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35                               struct ar5416_eeprom_def *pEepData,
36                               u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45 {
46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48         if (!ah->curchan) /* should really check for CCK instead */
49                 return clks / ATH9K_CLOCK_RATE_CCK;
50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54 }
55
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57 {
58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60         if (conf_is_ht40(conf))
61                 return ath9k_hw_mac_usec(ah, clks) / 2;
62         else
63                 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67 {
68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70         if (!ah->curchan) /* should really check for CCK instead */
71                 return usecs *ATH9K_CLOCK_RATE_CCK;
72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75 }
76
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78 {
79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81         if (conf_is_ht40(conf))
82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
83         else
84                 return ath9k_hw_mac_clks(ah, usecs);
85 }
86
87 /*
88  * Read and write, they both share the same lock. We do this to serialize
89  * reads and writes on Atheros 802.11n PCI devices only. This is required
90  * as the FIFO on these devices can only accept sanely 2 requests. After
91  * that the device goes bananas. Serializing the reads/writes prevents this
92  * from happening.
93  */
94
95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
96 {
97         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
98                 unsigned long flags;
99                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
100                 iowrite32(val, ah->ah_sc->mem + reg_offset);
101                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
102         } else
103                 iowrite32(val, ah->ah_sc->mem + reg_offset);
104 }
105
106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
107 {
108         u32 val;
109         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
110                 unsigned long flags;
111                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
112                 val = ioread32(ah->ah_sc->mem + reg_offset);
113                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
114         } else
115                 val = ioread32(ah->ah_sc->mem + reg_offset);
116         return val;
117 }
118
119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
120 {
121         int i;
122
123         BUG_ON(timeout < AH_TIME_QUANTUM);
124
125         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126                 if ((REG_READ(ah, reg) & mask) == val)
127                         return true;
128
129                 udelay(AH_TIME_QUANTUM);
130         }
131
132         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
133                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134                 timeout, reg, REG_READ(ah, reg), mask, val);
135
136         return false;
137 }
138
139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
140 {
141         u32 retval;
142         int i;
143
144         for (i = 0, retval = 0; i < n; i++) {
145                 retval = (retval << 1) | (val & 1);
146                 val >>= 1;
147         }
148         return retval;
149 }
150
151 bool ath9k_get_channel_edges(struct ath_hw *ah,
152                              u16 flags, u16 *low,
153                              u16 *high)
154 {
155         struct ath9k_hw_capabilities *pCap = &ah->caps;
156
157         if (flags & CHANNEL_5GHZ) {
158                 *low = pCap->low_5ghz_chan;
159                 *high = pCap->high_5ghz_chan;
160                 return true;
161         }
162         if ((flags & CHANNEL_2GHZ)) {
163                 *low = pCap->low_2ghz_chan;
164                 *high = pCap->high_2ghz_chan;
165                 return true;
166         }
167         return false;
168 }
169
170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171                            const struct ath_rate_table *rates,
172                            u32 frameLen, u16 rateix,
173                            bool shortPreamble)
174 {
175         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
176         u32 kbps;
177
178         kbps = rates->info[rateix].ratekbps;
179
180         if (kbps == 0)
181                 return 0;
182
183         switch (rates->info[rateix].phy) {
184         case WLAN_RC_PHY_CCK:
185                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
186                 if (shortPreamble && rates->info[rateix].short_preamble)
187                         phyTime >>= 1;
188                 numBits = frameLen << 3;
189                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
190                 break;
191         case WLAN_RC_PHY_OFDM:
192                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196                         txTime = OFDM_SIFS_TIME_QUARTER
197                                 + OFDM_PREAMBLE_TIME_QUARTER
198                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
199                 } else if (ah->curchan &&
200                            IS_CHAN_HALF_RATE(ah->curchan)) {
201                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
202                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
203                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
204                         txTime = OFDM_SIFS_TIME_HALF +
205                                 OFDM_PREAMBLE_TIME_HALF
206                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
207                 } else {
208                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
209                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
210                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
212                                 + (numSymbols * OFDM_SYMBOL_TIME);
213                 }
214                 break;
215         default:
216                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
217                         "Unknown phy %u (rate ix %u)\n",
218                         rates->info[rateix].phy, rateix);
219                 txTime = 0;
220                 break;
221         }
222
223         return txTime;
224 }
225
226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
227                                   struct ath9k_channel *chan,
228                                   struct chan_centers *centers)
229 {
230         int8_t extoff;
231
232         if (!IS_CHAN_HT40(chan)) {
233                 centers->ctl_center = centers->ext_center =
234                         centers->synth_center = chan->channel;
235                 return;
236         }
237
238         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
239             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
240                 centers->synth_center =
241                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
242                 extoff = 1;
243         } else {
244                 centers->synth_center =
245                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
246                 extoff = -1;
247         }
248
249         centers->ctl_center =
250                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
251         centers->ext_center =
252                 centers->synth_center + (extoff *
253                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
254                           HT40_CHANNEL_CENTER_SHIFT : 15));
255 }
256
257 /******************/
258 /* Chip Revisions */
259 /******************/
260
261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
262 {
263         u32 val;
264
265         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
266
267         if (val == 0xFF) {
268                 val = REG_READ(ah, AR_SREV);
269                 ah->hw_version.macVersion =
270                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
271                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
273         } else {
274                 if (!AR_SREV_9100(ah))
275                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
276
277                 ah->hw_version.macRev = val & AR_SREV_REVISION;
278
279                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
280                         ah->is_pciexpress = true;
281         }
282 }
283
284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
285 {
286         u32 val;
287         int i;
288
289         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
290
291         for (i = 0; i < 8; i++)
292                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
293         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
294         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
295
296         return ath9k_hw_reverse_bits(val, 8);
297 }
298
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
302
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
304 {
305         if (AR_SREV_9100(ah))
306                 return;
307
308         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
317
318         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
319 }
320
321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
322 {
323         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
324         u32 regHold[2];
325         u32 patternData[4] = { 0x55555555,
326                                0xaaaaaaaa,
327                                0x66666666,
328                                0x99999999 };
329         int i, j;
330
331         for (i = 0; i < 2; i++) {
332                 u32 addr = regAddr[i];
333                 u32 wrData, rdData;
334
335                 regHold[i] = REG_READ(ah, addr);
336                 for (j = 0; j < 0x100; j++) {
337                         wrData = (j << 16) | j;
338                         REG_WRITE(ah, addr, wrData);
339                         rdData = REG_READ(ah, addr);
340                         if (rdData != wrData) {
341                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
342                                         "address test failed "
343                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
344                                         addr, wrData, rdData);
345                                 return false;
346                         }
347                 }
348                 for (j = 0; j < 4; j++) {
349                         wrData = patternData[j];
350                         REG_WRITE(ah, addr, wrData);
351                         rdData = REG_READ(ah, addr);
352                         if (wrData != rdData) {
353                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
354                                         "address test failed "
355                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
356                                         addr, wrData, rdData);
357                                 return false;
358                         }
359                 }
360                 REG_WRITE(ah, regAddr[i], regHold[i]);
361         }
362         udelay(100);
363
364         return true;
365 }
366
367 static const char *ath9k_hw_devname(u16 devid)
368 {
369         switch (devid) {
370         case AR5416_DEVID_PCI:
371                 return "Atheros 5416";
372         case AR5416_DEVID_PCIE:
373                 return "Atheros 5418";
374         case AR9160_DEVID_PCI:
375                 return "Atheros 9160";
376         case AR5416_AR9100_DEVID:
377                 return "Atheros 9100";
378         case AR9280_DEVID_PCI:
379         case AR9280_DEVID_PCIE:
380                 return "Atheros 9280";
381         case AR9285_DEVID_PCIE:
382                 return "Atheros 9285";
383         case AR5416_DEVID_AR9287_PCI:
384         case AR5416_DEVID_AR9287_PCIE:
385                 return "Atheros 9287";
386         }
387
388         return NULL;
389 }
390
391 static void ath9k_hw_init_config(struct ath_hw *ah)
392 {
393         int i;
394
395         ah->config.dma_beacon_response_time = 2;
396         ah->config.sw_beacon_response_time = 10;
397         ah->config.additional_swba_backoff = 0;
398         ah->config.ack_6mb = 0x0;
399         ah->config.cwm_ignore_extcca = 0;
400         ah->config.pcie_powersave_enable = 0;
401         ah->config.pcie_clock_req = 0;
402         ah->config.pcie_waen = 0;
403         ah->config.analog_shiftreg = 1;
404         ah->config.ht_enable = 1;
405         ah->config.ofdm_trig_low = 200;
406         ah->config.ofdm_trig_high = 500;
407         ah->config.cck_trig_high = 200;
408         ah->config.cck_trig_low = 100;
409         ah->config.enable_ani = 1;
410         ah->config.diversity_control = 0;
411         ah->config.antenna_switch_swap = 0;
412
413         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
414                 ah->config.spurchans[i][0] = AR_NO_SPUR;
415                 ah->config.spurchans[i][1] = AR_NO_SPUR;
416         }
417
418         ah->config.intr_mitigation = true;
419
420         /*
421          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
422          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
423          * This means we use it for all AR5416 devices, and the few
424          * minor PCI AR9280 devices out there.
425          *
426          * Serialization is required because these devices do not handle
427          * well the case of two concurrent reads/writes due to the latency
428          * involved. During one read/write another read/write can be issued
429          * on another CPU while the previous read/write may still be working
430          * on our hardware, if we hit this case the hardware poops in a loop.
431          * We prevent this by serializing reads and writes.
432          *
433          * This issue is not present on PCI-Express devices or pre-AR5416
434          * devices (legacy, 802.11abg).
435          */
436         if (num_possible_cpus() > 1)
437                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
438 }
439
440 static void ath9k_hw_init_defaults(struct ath_hw *ah)
441 {
442         ah->hw_version.magic = AR5416_MAGIC;
443         ah->regulatory.country_code = CTRY_DEFAULT;
444         ah->hw_version.subvendorid = 0;
445
446         ah->ah_flags = 0;
447         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
448                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
449         if (!AR_SREV_9100(ah))
450                 ah->ah_flags = AH_USE_EEPROM;
451
452         ah->regulatory.power_limit = MAX_RATE_POWER;
453         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
454         ah->atim_window = 0;
455         ah->diversity_control = ah->config.diversity_control;
456         ah->antenna_switch_swap =
457                 ah->config.antenna_switch_swap;
458         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
459         ah->beacon_interval = 100;
460         ah->enable_32kHz_clock = DONT_USE_32KHZ;
461         ah->slottime = (u32) -1;
462         ah->acktimeout = (u32) -1;
463         ah->ctstimeout = (u32) -1;
464         ah->globaltxtimeout = (u32) -1;
465
466         ah->gbeacon_rate = 0;
467
468         ah->power_mode = ATH9K_PM_UNDEFINED;
469 }
470
471 static int ath9k_hw_rfattach(struct ath_hw *ah)
472 {
473         bool rfStatus = false;
474         int ecode = 0;
475
476         rfStatus = ath9k_hw_init_rf(ah, &ecode);
477         if (!rfStatus) {
478                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
479                         "RF setup failed, status: %u\n", ecode);
480                 return ecode;
481         }
482
483         return 0;
484 }
485
486 static int ath9k_hw_rf_claim(struct ath_hw *ah)
487 {
488         u32 val;
489
490         REG_WRITE(ah, AR_PHY(0), 0x00000007);
491
492         val = ath9k_hw_get_radiorev(ah);
493         switch (val & AR_RADIO_SREV_MAJOR) {
494         case 0:
495                 val = AR_RAD5133_SREV_MAJOR;
496                 break;
497         case AR_RAD5133_SREV_MAJOR:
498         case AR_RAD5122_SREV_MAJOR:
499         case AR_RAD2133_SREV_MAJOR:
500         case AR_RAD2122_SREV_MAJOR:
501                 break;
502         default:
503                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
504                         "Radio Chip Rev 0x%02X not supported\n",
505                         val & AR_RADIO_SREV_MAJOR);
506                 return -EOPNOTSUPP;
507         }
508
509         ah->hw_version.analog5GhzRev = val;
510
511         return 0;
512 }
513
514 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
515 {
516         u32 sum;
517         int i;
518         u16 eeval;
519
520         sum = 0;
521         for (i = 0; i < 3; i++) {
522                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
523                 sum += eeval;
524                 ah->macaddr[2 * i] = eeval >> 8;
525                 ah->macaddr[2 * i + 1] = eeval & 0xff;
526         }
527         if (sum == 0 || sum == 0xffff * 3)
528                 return -EADDRNOTAVAIL;
529
530         return 0;
531 }
532
533 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
534 {
535         u32 rxgain_type;
536
537         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
538                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
539
540                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
541                         INIT_INI_ARRAY(&ah->iniModesRxGain,
542                         ar9280Modes_backoff_13db_rxgain_9280_2,
543                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
544                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
545                         INIT_INI_ARRAY(&ah->iniModesRxGain,
546                         ar9280Modes_backoff_23db_rxgain_9280_2,
547                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
548                 else
549                         INIT_INI_ARRAY(&ah->iniModesRxGain,
550                         ar9280Modes_original_rxgain_9280_2,
551                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
552         } else {
553                 INIT_INI_ARRAY(&ah->iniModesRxGain,
554                         ar9280Modes_original_rxgain_9280_2,
555                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
556         }
557 }
558
559 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
560 {
561         u32 txgain_type;
562
563         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
564                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
565
566                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
567                         INIT_INI_ARRAY(&ah->iniModesTxGain,
568                         ar9280Modes_high_power_tx_gain_9280_2,
569                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
570                 else
571                         INIT_INI_ARRAY(&ah->iniModesTxGain,
572                         ar9280Modes_original_tx_gain_9280_2,
573                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
574         } else {
575                 INIT_INI_ARRAY(&ah->iniModesTxGain,
576                 ar9280Modes_original_tx_gain_9280_2,
577                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
578         }
579 }
580
581 static int ath9k_hw_post_attach(struct ath_hw *ah)
582 {
583         int ecode;
584
585         if (!ath9k_hw_chip_test(ah))
586                 return -ENODEV;
587
588         ecode = ath9k_hw_rf_claim(ah);
589         if (ecode != 0)
590                 return ecode;
591
592         ecode = ath9k_hw_eeprom_attach(ah);
593         if (ecode != 0)
594                 return ecode;
595
596         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
597                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
598
599         ecode = ath9k_hw_rfattach(ah);
600         if (ecode != 0)
601                 return ecode;
602
603         if (!AR_SREV_9100(ah)) {
604                 ath9k_hw_ani_setup(ah);
605                 ath9k_hw_ani_attach(ah);
606         }
607
608         return 0;
609 }
610
611 static bool ath9k_hw_devid_supported(u16 devid)
612 {
613         switch (devid) {
614         case AR5416_DEVID_PCI:
615         case AR5416_DEVID_PCIE:
616         case AR5416_AR9100_DEVID:
617         case AR9160_DEVID_PCI:
618         case AR9280_DEVID_PCI:
619         case AR9280_DEVID_PCIE:
620         case AR9285_DEVID_PCIE:
621         case AR5416_DEVID_AR9287_PCI:
622         case AR5416_DEVID_AR9287_PCIE:
623                 return true;
624         default:
625                 break;
626         }
627         return false;
628 }
629
630 static bool ath9k_hw_macversion_supported(u32 macversion)
631 {
632         switch (macversion) {
633         case AR_SREV_VERSION_5416_PCI:
634         case AR_SREV_VERSION_5416_PCIE:
635         case AR_SREV_VERSION_9160:
636         case AR_SREV_VERSION_9100:
637         case AR_SREV_VERSION_9280:
638         case AR_SREV_VERSION_9285:
639         case AR_SREV_VERSION_9287:
640                 return true;
641         default:
642                 break;
643         }
644         return false;
645 }
646
647 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
648 {
649         if (AR_SREV_9160_10_OR_LATER(ah)) {
650                 if (AR_SREV_9280_10_OR_LATER(ah)) {
651                         ah->iq_caldata.calData = &iq_cal_single_sample;
652                         ah->adcgain_caldata.calData =
653                                 &adc_gain_cal_single_sample;
654                         ah->adcdc_caldata.calData =
655                                 &adc_dc_cal_single_sample;
656                         ah->adcdc_calinitdata.calData =
657                                 &adc_init_dc_cal;
658                 } else {
659                         ah->iq_caldata.calData = &iq_cal_multi_sample;
660                         ah->adcgain_caldata.calData =
661                                 &adc_gain_cal_multi_sample;
662                         ah->adcdc_caldata.calData =
663                                 &adc_dc_cal_multi_sample;
664                         ah->adcdc_calinitdata.calData =
665                                 &adc_init_dc_cal;
666                 }
667                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
668         }
669 }
670
671 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
672 {
673         if (AR_SREV_9287_11_OR_LATER(ah)) {
674                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
675                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
676                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
677                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
678                 if (ah->config.pcie_clock_req)
679                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
680                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
681                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
682                 else
683                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
684                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
685                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
686                                         2);
687         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
688                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
689                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
690                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
691                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
692
693                 if (ah->config.pcie_clock_req)
694                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
695                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
696                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
697                 else
698                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
699                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
700                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
701                                   2);
702         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
703
704
705                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
706                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
707                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
708                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
709
710                 if (ah->config.pcie_clock_req) {
711                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
712                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
713                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
714                 } else {
715                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
716                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
717                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
718                                   2);
719                 }
720         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
721                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
722                                ARRAY_SIZE(ar9285Modes_9285), 6);
723                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
724                                ARRAY_SIZE(ar9285Common_9285), 2);
725
726                 if (ah->config.pcie_clock_req) {
727                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
728                         ar9285PciePhy_clkreq_off_L1_9285,
729                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
730                 } else {
731                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
732                         ar9285PciePhy_clkreq_always_on_L1_9285,
733                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
734                 }
735         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
736                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
737                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
738                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
739                                ARRAY_SIZE(ar9280Common_9280_2), 2);
740
741                 if (ah->config.pcie_clock_req) {
742                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
743                                ar9280PciePhy_clkreq_off_L1_9280,
744                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
745                 } else {
746                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
747                                ar9280PciePhy_clkreq_always_on_L1_9280,
748                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
749                 }
750                 INIT_INI_ARRAY(&ah->iniModesAdditional,
751                                ar9280Modes_fast_clock_9280_2,
752                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
753         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
754                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
755                                ARRAY_SIZE(ar9280Modes_9280), 6);
756                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
757                                ARRAY_SIZE(ar9280Common_9280), 2);
758         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
759                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
760                                ARRAY_SIZE(ar5416Modes_9160), 6);
761                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
762                                ARRAY_SIZE(ar5416Common_9160), 2);
763                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
764                                ARRAY_SIZE(ar5416Bank0_9160), 2);
765                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
766                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
767                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
768                                ARRAY_SIZE(ar5416Bank1_9160), 2);
769                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
770                                ARRAY_SIZE(ar5416Bank2_9160), 2);
771                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
772                                ARRAY_SIZE(ar5416Bank3_9160), 3);
773                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
774                                ARRAY_SIZE(ar5416Bank6_9160), 3);
775                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
776                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
777                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
778                                ARRAY_SIZE(ar5416Bank7_9160), 2);
779                 if (AR_SREV_9160_11(ah)) {
780                         INIT_INI_ARRAY(&ah->iniAddac,
781                                        ar5416Addac_91601_1,
782                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
783                 } else {
784                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
785                                        ARRAY_SIZE(ar5416Addac_9160), 2);
786                 }
787         } else if (AR_SREV_9100_OR_LATER(ah)) {
788                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
789                                ARRAY_SIZE(ar5416Modes_9100), 6);
790                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
791                                ARRAY_SIZE(ar5416Common_9100), 2);
792                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
793                                ARRAY_SIZE(ar5416Bank0_9100), 2);
794                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
795                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
796                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
797                                ARRAY_SIZE(ar5416Bank1_9100), 2);
798                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
799                                ARRAY_SIZE(ar5416Bank2_9100), 2);
800                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
801                                ARRAY_SIZE(ar5416Bank3_9100), 3);
802                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
803                                ARRAY_SIZE(ar5416Bank6_9100), 3);
804                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
805                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
806                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
807                                ARRAY_SIZE(ar5416Bank7_9100), 2);
808                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
809                                ARRAY_SIZE(ar5416Addac_9100), 2);
810         } else {
811                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
812                                ARRAY_SIZE(ar5416Modes), 6);
813                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
814                                ARRAY_SIZE(ar5416Common), 2);
815                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
816                                ARRAY_SIZE(ar5416Bank0), 2);
817                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
818                                ARRAY_SIZE(ar5416BB_RfGain), 3);
819                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
820                                ARRAY_SIZE(ar5416Bank1), 2);
821                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
822                                ARRAY_SIZE(ar5416Bank2), 2);
823                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
824                                ARRAY_SIZE(ar5416Bank3), 3);
825                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
826                                ARRAY_SIZE(ar5416Bank6), 3);
827                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
828                                ARRAY_SIZE(ar5416Bank6TPC), 3);
829                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
830                                ARRAY_SIZE(ar5416Bank7), 2);
831                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
832                                ARRAY_SIZE(ar5416Addac), 2);
833         }
834 }
835
836 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
837 {
838         if (AR_SREV_9287_11(ah))
839                 INIT_INI_ARRAY(&ah->iniModesRxGain,
840                 ar9287Modes_rx_gain_9287_1_1,
841                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
842         else if (AR_SREV_9287_10(ah))
843                 INIT_INI_ARRAY(&ah->iniModesRxGain,
844                 ar9287Modes_rx_gain_9287_1_0,
845                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
846         else if (AR_SREV_9280_20(ah))
847                 ath9k_hw_init_rxgain_ini(ah);
848
849         if (AR_SREV_9287_11(ah)) {
850                 INIT_INI_ARRAY(&ah->iniModesTxGain,
851                 ar9287Modes_tx_gain_9287_1_1,
852                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
853         } else if (AR_SREV_9287_10(ah)) {
854                 INIT_INI_ARRAY(&ah->iniModesTxGain,
855                 ar9287Modes_tx_gain_9287_1_0,
856                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
857         } else if (AR_SREV_9280_20(ah)) {
858                 ath9k_hw_init_txgain_ini(ah);
859         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
860                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
861
862                 /* txgain table */
863                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
864                         INIT_INI_ARRAY(&ah->iniModesTxGain,
865                         ar9285Modes_high_power_tx_gain_9285_1_2,
866                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
867                 } else {
868                         INIT_INI_ARRAY(&ah->iniModesTxGain,
869                         ar9285Modes_original_tx_gain_9285_1_2,
870                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
871                 }
872
873         }
874 }
875
876 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
877 {
878         u32 i, j;
879
880         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
881             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
882
883                 /* EEPROM Fixup */
884                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
885                         u32 reg = INI_RA(&ah->iniModes, i, 0);
886
887                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
888                                 u32 val = INI_RA(&ah->iniModes, i, j);
889
890                                 INI_RA(&ah->iniModes, i, j) =
891                                         ath9k_hw_ini_fixup(ah,
892                                                            &ah->eeprom.def,
893                                                            reg, val);
894                         }
895                 }
896         }
897 }
898
899 int ath9k_hw_attach(struct ath_hw *ah)
900 {
901         int r;
902
903         if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
904                 r = -EOPNOTSUPP;
905                 goto bad;
906         }
907
908         ath9k_hw_init_defaults(ah);
909         ath9k_hw_init_config(ah);
910
911         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
912                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
913                 r = -EIO;
914                 goto bad;
915         }
916
917         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
918                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
919                 r = -EIO;
920                 goto bad;
921         }
922
923         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
924                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
925                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
926                         ah->config.serialize_regmode =
927                                 SER_REG_MODE_ON;
928                 } else {
929                         ah->config.serialize_regmode =
930                                 SER_REG_MODE_OFF;
931                 }
932         }
933
934         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
935                 ah->config.serialize_regmode);
936
937         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
938                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
939                         "Mac Chip Rev 0x%02x.%x is not supported by "
940                         "this driver\n", ah->hw_version.macVersion,
941                         ah->hw_version.macRev);
942                 r = -EOPNOTSUPP;
943                 goto bad;
944         }
945
946         if (AR_SREV_9100(ah)) {
947                 ah->iq_caldata.calData = &iq_cal_multi_sample;
948                 ah->supp_cals = IQ_MISMATCH_CAL;
949                 ah->is_pciexpress = false;
950         }
951         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
952
953         ath9k_hw_init_cal_settings(ah);
954
955         ah->ani_function = ATH9K_ANI_ALL;
956         if (AR_SREV_9280_10_OR_LATER(ah))
957                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
958
959         ath9k_hw_init_mode_regs(ah);
960
961         if (ah->is_pciexpress)
962                 ath9k_hw_configpcipowersave(ah, 0);
963         else
964                 ath9k_hw_disablepcie(ah);
965
966         r = ath9k_hw_post_attach(ah);
967         if (r)
968                 goto bad;
969
970         ath9k_hw_init_mode_gain_regs(ah);
971         ath9k_hw_fill_cap_info(ah);
972         ath9k_hw_init_11a_eeprom_fix(ah);
973
974         r = ath9k_hw_init_macaddr(ah);
975         if (r) {
976                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
977                         "Failed to initialize MAC address\n");
978                 goto bad;
979         }
980
981         if (AR_SREV_9285(ah))
982                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
983         else
984                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
985
986         ath9k_init_nfcal_hist_buffer(ah);
987
988         return 0;
989 bad:
990         ath9k_hw_detach(ah);
991         return r;
992 }
993
994 static void ath9k_hw_init_bb(struct ath_hw *ah,
995                              struct ath9k_channel *chan)
996 {
997         u32 synthDelay;
998
999         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1000         if (IS_CHAN_B(chan))
1001                 synthDelay = (4 * synthDelay) / 22;
1002         else
1003                 synthDelay /= 10;
1004
1005         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1006
1007         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1008 }
1009
1010 static void ath9k_hw_init_qos(struct ath_hw *ah)
1011 {
1012         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1013         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1014
1015         REG_WRITE(ah, AR_QOS_NO_ACK,
1016                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1017                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1018                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1019
1020         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1021         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1022         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1023         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1024         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1025 }
1026
1027 static void ath9k_hw_init_pll(struct ath_hw *ah,
1028                               struct ath9k_channel *chan)
1029 {
1030         u32 pll;
1031
1032         if (AR_SREV_9100(ah)) {
1033                 if (chan && IS_CHAN_5GHZ(chan))
1034                         pll = 0x1450;
1035                 else
1036                         pll = 0x1458;
1037         } else {
1038                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1039                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1040
1041                         if (chan && IS_CHAN_HALF_RATE(chan))
1042                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1043                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1044                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1045
1046                         if (chan && IS_CHAN_5GHZ(chan)) {
1047                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1048
1049
1050                                 if (AR_SREV_9280_20(ah)) {
1051                                         if (((chan->channel % 20) == 0)
1052                                             || ((chan->channel % 10) == 0))
1053                                                 pll = 0x2850;
1054                                         else
1055                                                 pll = 0x142c;
1056                                 }
1057                         } else {
1058                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1059                         }
1060
1061                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1062
1063                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1064
1065                         if (chan && IS_CHAN_HALF_RATE(chan))
1066                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1067                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1068                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1069
1070                         if (chan && IS_CHAN_5GHZ(chan))
1071                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1072                         else
1073                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1074                 } else {
1075                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1076
1077                         if (chan && IS_CHAN_HALF_RATE(chan))
1078                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1079                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1080                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1081
1082                         if (chan && IS_CHAN_5GHZ(chan))
1083                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1084                         else
1085                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1086                 }
1087         }
1088         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1089
1090         udelay(RTC_PLL_SETTLE_DELAY);
1091
1092         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1093 }
1094
1095 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1096 {
1097         int rx_chainmask, tx_chainmask;
1098
1099         rx_chainmask = ah->rxchainmask;
1100         tx_chainmask = ah->txchainmask;
1101
1102         switch (rx_chainmask) {
1103         case 0x5:
1104                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1105                             AR_PHY_SWAP_ALT_CHAIN);
1106         case 0x3:
1107                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1108                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1109                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1110                         break;
1111                 }
1112         case 0x1:
1113         case 0x2:
1114         case 0x7:
1115                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1116                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1117                 break;
1118         default:
1119                 break;
1120         }
1121
1122         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1123         if (tx_chainmask == 0x5) {
1124                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1125                             AR_PHY_SWAP_ALT_CHAIN);
1126         }
1127         if (AR_SREV_9100(ah))
1128                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1129                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1130 }
1131
1132 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1133                                           enum nl80211_iftype opmode)
1134 {
1135         ah->mask_reg = AR_IMR_TXERR |
1136                 AR_IMR_TXURN |
1137                 AR_IMR_RXERR |
1138                 AR_IMR_RXORN |
1139                 AR_IMR_BCNMISC;
1140
1141         if (ah->config.intr_mitigation)
1142                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1143         else
1144                 ah->mask_reg |= AR_IMR_RXOK;
1145
1146         ah->mask_reg |= AR_IMR_TXOK;
1147
1148         if (opmode == NL80211_IFTYPE_AP)
1149                 ah->mask_reg |= AR_IMR_MIB;
1150
1151         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1152         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1153
1154         if (!AR_SREV_9100(ah)) {
1155                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1156                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1157                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1158         }
1159 }
1160
1161 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1162 {
1163         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1164                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1165                 ah->acktimeout = (u32) -1;
1166                 return false;
1167         } else {
1168                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1169                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1170                 ah->acktimeout = us;
1171                 return true;
1172         }
1173 }
1174
1175 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1176 {
1177         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1178                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1179                 ah->ctstimeout = (u32) -1;
1180                 return false;
1181         } else {
1182                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1183                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1184                 ah->ctstimeout = us;
1185                 return true;
1186         }
1187 }
1188
1189 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1190 {
1191         if (tu > 0xFFFF) {
1192                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1193                         "bad global tx timeout %u\n", tu);
1194                 ah->globaltxtimeout = (u32) -1;
1195                 return false;
1196         } else {
1197                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1198                 ah->globaltxtimeout = tu;
1199                 return true;
1200         }
1201 }
1202
1203 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1204 {
1205         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1206                 ah->misc_mode);
1207
1208         if (ah->misc_mode != 0)
1209                 REG_WRITE(ah, AR_PCU_MISC,
1210                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1211         if (ah->slottime != (u32) -1)
1212                 ath9k_hw_setslottime(ah, ah->slottime);
1213         if (ah->acktimeout != (u32) -1)
1214                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1215         if (ah->ctstimeout != (u32) -1)
1216                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1217         if (ah->globaltxtimeout != (u32) -1)
1218                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1219 }
1220
1221 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1222 {
1223         return vendorid == ATHEROS_VENDOR_ID ?
1224                 ath9k_hw_devname(devid) : NULL;
1225 }
1226
1227 void ath9k_hw_detach(struct ath_hw *ah)
1228 {
1229         if (!AR_SREV_9100(ah))
1230                 ath9k_hw_ani_detach(ah);
1231
1232         ath9k_hw_rfdetach(ah);
1233         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1234         kfree(ah);
1235 }
1236
1237 /*******/
1238 /* INI */
1239 /*******/
1240
1241 static void ath9k_hw_override_ini(struct ath_hw *ah,
1242                                   struct ath9k_channel *chan)
1243 {
1244         /*
1245          * Set the RX_ABORT and RX_DIS and clear if off only after
1246          * RXE is set for MAC. This prevents frames with corrupted
1247          * descriptor status.
1248          */
1249         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1250
1251
1252         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1253             AR_SREV_9280_10_OR_LATER(ah))
1254                 return;
1255
1256         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1257 }
1258
1259 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1260                               struct ar5416_eeprom_def *pEepData,
1261                               u32 reg, u32 value)
1262 {
1263         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1264
1265         switch (ah->hw_version.devid) {
1266         case AR9280_DEVID_PCI:
1267                 if (reg == 0x7894) {
1268                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1269                                 "ini VAL: %x  EEPROM: %x\n", value,
1270                                 (pBase->version & 0xff));
1271
1272                         if ((pBase->version & 0xff) > 0x0a) {
1273                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1274                                         "PWDCLKIND: %d\n",
1275                                         pBase->pwdclkind);
1276                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1277                                 value |= AR_AN_TOP2_PWDCLKIND &
1278                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1279                         } else {
1280                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1281                                         "PWDCLKIND Earlier Rev\n");
1282                         }
1283
1284                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1285                                 "final ini VAL: %x\n", value);
1286                 }
1287                 break;
1288         }
1289
1290         return value;
1291 }
1292
1293 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1294                               struct ar5416_eeprom_def *pEepData,
1295                               u32 reg, u32 value)
1296 {
1297         if (ah->eep_map == EEP_MAP_4KBITS)
1298                 return value;
1299         else
1300                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1301 }
1302
1303 static void ath9k_olc_init(struct ath_hw *ah)
1304 {
1305         u32 i;
1306
1307         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1308                 ah->originalGain[i] =
1309                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1310                                         AR_PHY_TX_GAIN);
1311         ah->PDADCdelta = 0;
1312 }
1313
1314 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1315                               struct ath9k_channel *chan)
1316 {
1317         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1318
1319         if (IS_CHAN_B(chan))
1320                 ctl |= CTL_11B;
1321         else if (IS_CHAN_G(chan))
1322                 ctl |= CTL_11G;
1323         else
1324                 ctl |= CTL_11A;
1325
1326         return ctl;
1327 }
1328
1329 static int ath9k_hw_process_ini(struct ath_hw *ah,
1330                                 struct ath9k_channel *chan,
1331                                 enum ath9k_ht_macmode macmode)
1332 {
1333         int i, regWrites = 0;
1334         struct ieee80211_channel *channel = chan->chan;
1335         u32 modesIndex, freqIndex;
1336
1337         switch (chan->chanmode) {
1338         case CHANNEL_A:
1339         case CHANNEL_A_HT20:
1340                 modesIndex = 1;
1341                 freqIndex = 1;
1342                 break;
1343         case CHANNEL_A_HT40PLUS:
1344         case CHANNEL_A_HT40MINUS:
1345                 modesIndex = 2;
1346                 freqIndex = 1;
1347                 break;
1348         case CHANNEL_G:
1349         case CHANNEL_G_HT20:
1350         case CHANNEL_B:
1351                 modesIndex = 4;
1352                 freqIndex = 2;
1353                 break;
1354         case CHANNEL_G_HT40PLUS:
1355         case CHANNEL_G_HT40MINUS:
1356                 modesIndex = 3;
1357                 freqIndex = 2;
1358                 break;
1359
1360         default:
1361                 return -EINVAL;
1362         }
1363
1364         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1365         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1366         ah->eep_ops->set_addac(ah, chan);
1367
1368         if (AR_SREV_5416_22_OR_LATER(ah)) {
1369                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1370         } else {
1371                 struct ar5416IniArray temp;
1372                 u32 addacSize =
1373                         sizeof(u32) * ah->iniAddac.ia_rows *
1374                         ah->iniAddac.ia_columns;
1375
1376                 memcpy(ah->addac5416_21,
1377                        ah->iniAddac.ia_array, addacSize);
1378
1379                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1380
1381                 temp.ia_array = ah->addac5416_21;
1382                 temp.ia_columns = ah->iniAddac.ia_columns;
1383                 temp.ia_rows = ah->iniAddac.ia_rows;
1384                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1385         }
1386
1387         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1388
1389         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1390                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1391                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1392
1393                 REG_WRITE(ah, reg, val);
1394
1395                 if (reg >= 0x7800 && reg < 0x78a0
1396                     && ah->config.analog_shiftreg) {
1397                         udelay(100);
1398                 }
1399
1400                 DO_DELAY(regWrites);
1401         }
1402
1403         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1404                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1405
1406         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1407             AR_SREV_9287_10_OR_LATER(ah))
1408                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1409
1410         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1411                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1412                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1413
1414                 REG_WRITE(ah, reg, val);
1415
1416                 if (reg >= 0x7800 && reg < 0x78a0
1417                     && ah->config.analog_shiftreg) {
1418                         udelay(100);
1419                 }
1420
1421                 DO_DELAY(regWrites);
1422         }
1423
1424         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1425
1426         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1427                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1428                                 regWrites);
1429         }
1430
1431         ath9k_hw_override_ini(ah, chan);
1432         ath9k_hw_set_regs(ah, chan, macmode);
1433         ath9k_hw_init_chain_masks(ah);
1434
1435         if (OLC_FOR_AR9280_20_LATER)
1436                 ath9k_olc_init(ah);
1437
1438         ah->eep_ops->set_txpower(ah, chan,
1439                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
1440                                  channel->max_antenna_gain * 2,
1441                                  channel->max_power * 2,
1442                                  min((u32) MAX_RATE_POWER,
1443                                  (u32) ah->regulatory.power_limit));
1444
1445         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1446                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1447                         "ar5416SetRfRegs failed\n");
1448                 return -EIO;
1449         }
1450
1451         return 0;
1452 }
1453
1454 /****************************************/
1455 /* Reset and Channel Switching Routines */
1456 /****************************************/
1457
1458 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1459 {
1460         u32 rfMode = 0;
1461
1462         if (chan == NULL)
1463                 return;
1464
1465         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1466                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1467
1468         if (!AR_SREV_9280_10_OR_LATER(ah))
1469                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1470                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1471
1472         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1473                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1474
1475         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1476 }
1477
1478 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1479 {
1480         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1481 }
1482
1483 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1484 {
1485         u32 regval;
1486
1487         regval = REG_READ(ah, AR_AHB_MODE);
1488         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1489
1490         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1491         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1492
1493         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1494
1495         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1496         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1497
1498         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1499
1500         if (AR_SREV_9285(ah)) {
1501                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1502                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1503         } else {
1504                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1505                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1506         }
1507 }
1508
1509 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1510 {
1511         u32 val;
1512
1513         val = REG_READ(ah, AR_STA_ID1);
1514         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1515         switch (opmode) {
1516         case NL80211_IFTYPE_AP:
1517                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1518                           | AR_STA_ID1_KSRCH_MODE);
1519                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1520                 break;
1521         case NL80211_IFTYPE_ADHOC:
1522         case NL80211_IFTYPE_MESH_POINT:
1523                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1524                           | AR_STA_ID1_KSRCH_MODE);
1525                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1526                 break;
1527         case NL80211_IFTYPE_STATION:
1528         case NL80211_IFTYPE_MONITOR:
1529                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1530                 break;
1531         }
1532 }
1533
1534 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1535                                                  u32 coef_scaled,
1536                                                  u32 *coef_mantissa,
1537                                                  u32 *coef_exponent)
1538 {
1539         u32 coef_exp, coef_man;
1540
1541         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1542                 if ((coef_scaled >> coef_exp) & 0x1)
1543                         break;
1544
1545         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1546
1547         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1548
1549         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1550         *coef_exponent = coef_exp - 16;
1551 }
1552
1553 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1554                                      struct ath9k_channel *chan)
1555 {
1556         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1557         u32 clockMhzScaled = 0x64000000;
1558         struct chan_centers centers;
1559
1560         if (IS_CHAN_HALF_RATE(chan))
1561                 clockMhzScaled = clockMhzScaled >> 1;
1562         else if (IS_CHAN_QUARTER_RATE(chan))
1563                 clockMhzScaled = clockMhzScaled >> 2;
1564
1565         ath9k_hw_get_channel_centers(ah, chan, &centers);
1566         coef_scaled = clockMhzScaled / centers.synth_center;
1567
1568         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1569                                       &ds_coef_exp);
1570
1571         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1572                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1573         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1574                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1575
1576         coef_scaled = (9 * coef_scaled) / 10;
1577
1578         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1579                                       &ds_coef_exp);
1580
1581         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1582                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1583         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1584                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1585 }
1586
1587 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1588 {
1589         u32 rst_flags;
1590         u32 tmpReg;
1591
1592         if (AR_SREV_9100(ah)) {
1593                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1594                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1595                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1596                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1597                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1598         }
1599
1600         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1601                   AR_RTC_FORCE_WAKE_ON_INT);
1602
1603         if (AR_SREV_9100(ah)) {
1604                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1605                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1606         } else {
1607                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1608                 if (tmpReg &
1609                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1610                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1611                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1612                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1613                 } else {
1614                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1615                 }
1616
1617                 rst_flags = AR_RTC_RC_MAC_WARM;
1618                 if (type == ATH9K_RESET_COLD)
1619                         rst_flags |= AR_RTC_RC_MAC_COLD;
1620         }
1621
1622         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1623         udelay(50);
1624
1625         REG_WRITE(ah, AR_RTC_RC, 0);
1626         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1627                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1628                         "RTC stuck in MAC reset\n");
1629                 return false;
1630         }
1631
1632         if (!AR_SREV_9100(ah))
1633                 REG_WRITE(ah, AR_RC, 0);
1634
1635         ath9k_hw_init_pll(ah, NULL);
1636
1637         if (AR_SREV_9100(ah))
1638                 udelay(50);
1639
1640         return true;
1641 }
1642
1643 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1644 {
1645         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1646                   AR_RTC_FORCE_WAKE_ON_INT);
1647
1648         REG_WRITE(ah, AR_RTC_RESET, 0);
1649         udelay(2);
1650         REG_WRITE(ah, AR_RTC_RESET, 1);
1651
1652         if (!ath9k_hw_wait(ah,
1653                            AR_RTC_STATUS,
1654                            AR_RTC_STATUS_M,
1655                            AR_RTC_STATUS_ON,
1656                            AH_WAIT_TIMEOUT)) {
1657                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1658                 return false;
1659         }
1660
1661         ath9k_hw_read_revisions(ah);
1662
1663         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1664 }
1665
1666 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1667 {
1668         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1669                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1670
1671         switch (type) {
1672         case ATH9K_RESET_POWER_ON:
1673                 return ath9k_hw_set_reset_power_on(ah);
1674         case ATH9K_RESET_WARM:
1675         case ATH9K_RESET_COLD:
1676                 return ath9k_hw_set_reset(ah, type);
1677         default:
1678                 return false;
1679         }
1680 }
1681
1682 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1683                               enum ath9k_ht_macmode macmode)
1684 {
1685         u32 phymode;
1686         u32 enableDacFifo = 0;
1687
1688         if (AR_SREV_9285_10_OR_LATER(ah))
1689                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1690                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1691
1692         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1693                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1694
1695         if (IS_CHAN_HT40(chan)) {
1696                 phymode |= AR_PHY_FC_DYN2040_EN;
1697
1698                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1699                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1700                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1701
1702                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1703                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1704         }
1705         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1706
1707         ath9k_hw_set11nmac2040(ah, macmode);
1708
1709         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1710         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1711 }
1712
1713 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1714                                 struct ath9k_channel *chan)
1715 {
1716         if (OLC_FOR_AR9280_20_LATER) {
1717                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1718                         return false;
1719         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1720                 return false;
1721
1722         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1723                 return false;
1724
1725         ah->chip_fullsleep = false;
1726         ath9k_hw_init_pll(ah, chan);
1727         ath9k_hw_set_rfmode(ah, chan);
1728
1729         return true;
1730 }
1731
1732 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1733                                     struct ath9k_channel *chan,
1734                                     enum ath9k_ht_macmode macmode)
1735 {
1736         struct ieee80211_channel *channel = chan->chan;
1737         u32 synthDelay, qnum;
1738
1739         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1740                 if (ath9k_hw_numtxpending(ah, qnum)) {
1741                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1742                                 "Transmit frames pending on queue %d\n", qnum);
1743                         return false;
1744                 }
1745         }
1746
1747         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1748         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1749                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1750                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1751                         "Could not kill baseband RX\n");
1752                 return false;
1753         }
1754
1755         ath9k_hw_set_regs(ah, chan, macmode);
1756
1757         if (AR_SREV_9280_10_OR_LATER(ah)) {
1758                 ath9k_hw_ar9280_set_channel(ah, chan);
1759         } else {
1760                 if (!(ath9k_hw_set_channel(ah, chan))) {
1761                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1762                                 "Failed to set channel\n");
1763                         return false;
1764                 }
1765         }
1766
1767         ah->eep_ops->set_txpower(ah, chan,
1768                              ath9k_regd_get_ctl(&ah->regulatory, chan),
1769                              channel->max_antenna_gain * 2,
1770                              channel->max_power * 2,
1771                              min((u32) MAX_RATE_POWER,
1772                              (u32) ah->regulatory.power_limit));
1773
1774         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1775         if (IS_CHAN_B(chan))
1776                 synthDelay = (4 * synthDelay) / 22;
1777         else
1778                 synthDelay /= 10;
1779
1780         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1781
1782         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1783
1784         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1785                 ath9k_hw_set_delta_slope(ah, chan);
1786
1787         if (AR_SREV_9280_10_OR_LATER(ah))
1788                 ath9k_hw_9280_spur_mitigate(ah, chan);
1789         else
1790                 ath9k_hw_spur_mitigate(ah, chan);
1791
1792         if (!chan->oneTimeCalsDone)
1793                 chan->oneTimeCalsDone = true;
1794
1795         return true;
1796 }
1797
1798 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1799 {
1800         int bb_spur = AR_NO_SPUR;
1801         int freq;
1802         int bin, cur_bin;
1803         int bb_spur_off, spur_subchannel_sd;
1804         int spur_freq_sd;
1805         int spur_delta_phase;
1806         int denominator;
1807         int upper, lower, cur_vit_mask;
1808         int tmp, newVal;
1809         int i;
1810         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1811                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1812         };
1813         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1814                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1815         };
1816         int inc[4] = { 0, 100, 0, 0 };
1817         struct chan_centers centers;
1818
1819         int8_t mask_m[123];
1820         int8_t mask_p[123];
1821         int8_t mask_amt;
1822         int tmp_mask;
1823         int cur_bb_spur;
1824         bool is2GHz = IS_CHAN_2GHZ(chan);
1825
1826         memset(&mask_m, 0, sizeof(int8_t) * 123);
1827         memset(&mask_p, 0, sizeof(int8_t) * 123);
1828
1829         ath9k_hw_get_channel_centers(ah, chan, &centers);
1830         freq = centers.synth_center;
1831
1832         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1833         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1834                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1835
1836                 if (is2GHz)
1837                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1838                 else
1839                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1840
1841                 if (AR_NO_SPUR == cur_bb_spur)
1842                         break;
1843                 cur_bb_spur = cur_bb_spur - freq;
1844
1845                 if (IS_CHAN_HT40(chan)) {
1846                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1847                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1848                                 bb_spur = cur_bb_spur;
1849                                 break;
1850                         }
1851                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1852                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1853                         bb_spur = cur_bb_spur;
1854                         break;
1855                 }
1856         }
1857
1858         if (AR_NO_SPUR == bb_spur) {
1859                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1860                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1861                 return;
1862         } else {
1863                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1864                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1865         }
1866
1867         bin = bb_spur * 320;
1868
1869         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1870
1871         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1872                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1873                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1874                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1875         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1876
1877         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1878                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1879                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1880                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1881                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1882         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1883
1884         if (IS_CHAN_HT40(chan)) {
1885                 if (bb_spur < 0) {
1886                         spur_subchannel_sd = 1;
1887                         bb_spur_off = bb_spur + 10;
1888                 } else {
1889                         spur_subchannel_sd = 0;
1890                         bb_spur_off = bb_spur - 10;
1891                 }
1892         } else {
1893                 spur_subchannel_sd = 0;
1894                 bb_spur_off = bb_spur;
1895         }
1896
1897         if (IS_CHAN_HT40(chan))
1898                 spur_delta_phase =
1899                         ((bb_spur * 262144) /
1900                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1901         else
1902                 spur_delta_phase =
1903                         ((bb_spur * 524288) /
1904                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1905
1906         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1907         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1908
1909         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1910                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1911                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1912         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1913
1914         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1915         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1916
1917         cur_bin = -6000;
1918         upper = bin + 100;
1919         lower = bin - 100;
1920
1921         for (i = 0; i < 4; i++) {
1922                 int pilot_mask = 0;
1923                 int chan_mask = 0;
1924                 int bp = 0;
1925                 for (bp = 0; bp < 30; bp++) {
1926                         if ((cur_bin > lower) && (cur_bin < upper)) {
1927                                 pilot_mask = pilot_mask | 0x1 << bp;
1928                                 chan_mask = chan_mask | 0x1 << bp;
1929                         }
1930                         cur_bin += 100;
1931                 }
1932                 cur_bin += inc[i];
1933                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1934                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1935         }
1936
1937         cur_vit_mask = 6100;
1938         upper = bin + 120;
1939         lower = bin - 120;
1940
1941         for (i = 0; i < 123; i++) {
1942                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1943
1944                         /* workaround for gcc bug #37014 */
1945                         volatile int tmp_v = abs(cur_vit_mask - bin);
1946
1947                         if (tmp_v < 75)
1948                                 mask_amt = 1;
1949                         else
1950                                 mask_amt = 0;
1951                         if (cur_vit_mask < 0)
1952                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1953                         else
1954                                 mask_p[cur_vit_mask / 100] = mask_amt;
1955                 }
1956                 cur_vit_mask -= 100;
1957         }
1958
1959         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1960                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1961                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1962                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1963                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1964                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1965                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1966                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1967         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1968         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1969
1970         tmp_mask = (mask_m[31] << 28)
1971                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1972                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1973                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1974                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1975                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1976                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1977                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1978         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1979         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1980
1981         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1982                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1983                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1984                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1985                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1986                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1987                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1988                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1989         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1990         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1991
1992         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1993                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1994                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1995                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1996                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1997                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1998                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1999                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2000         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2001         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2002
2003         tmp_mask = (mask_p[15] << 28)
2004                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2005                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2006                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2007                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2008                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2009                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2010                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2011         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2012         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2013
2014         tmp_mask = (mask_p[30] << 28)
2015                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2016                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2017                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2018                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2019                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2020                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2021                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2022         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2023         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2024
2025         tmp_mask = (mask_p[45] << 28)
2026                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2027                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2028                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2029                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2030                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2031                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2032                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2033         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2034         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2035
2036         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2037                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2038                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2039                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2040                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2041                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2042                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2043                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2044         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2045         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2046 }
2047
2048 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2049 {
2050         int bb_spur = AR_NO_SPUR;
2051         int bin, cur_bin;
2052         int spur_freq_sd;
2053         int spur_delta_phase;
2054         int denominator;
2055         int upper, lower, cur_vit_mask;
2056         int tmp, new;
2057         int i;
2058         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2059                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2060         };
2061         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2062                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2063         };
2064         int inc[4] = { 0, 100, 0, 0 };
2065
2066         int8_t mask_m[123];
2067         int8_t mask_p[123];
2068         int8_t mask_amt;
2069         int tmp_mask;
2070         int cur_bb_spur;
2071         bool is2GHz = IS_CHAN_2GHZ(chan);
2072
2073         memset(&mask_m, 0, sizeof(int8_t) * 123);
2074         memset(&mask_p, 0, sizeof(int8_t) * 123);
2075
2076         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2077                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2078                 if (AR_NO_SPUR == cur_bb_spur)
2079                         break;
2080                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2081                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2082                         bb_spur = cur_bb_spur;
2083                         break;
2084                 }
2085         }
2086
2087         if (AR_NO_SPUR == bb_spur)
2088                 return;
2089
2090         bin = bb_spur * 32;
2091
2092         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2093         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2094                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2095                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2096                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2097
2098         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2099
2100         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2101                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2102                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2103                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2104                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2105         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2106
2107         spur_delta_phase = ((bb_spur * 524288) / 100) &
2108                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2109
2110         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2111         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2112
2113         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2114                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2115                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2116         REG_WRITE(ah, AR_PHY_TIMING11, new);
2117
2118         cur_bin = -6000;
2119         upper = bin + 100;
2120         lower = bin - 100;
2121
2122         for (i = 0; i < 4; i++) {
2123                 int pilot_mask = 0;
2124                 int chan_mask = 0;
2125                 int bp = 0;
2126                 for (bp = 0; bp < 30; bp++) {
2127                         if ((cur_bin > lower) && (cur_bin < upper)) {
2128                                 pilot_mask = pilot_mask | 0x1 << bp;
2129                                 chan_mask = chan_mask | 0x1 << bp;
2130                         }
2131                         cur_bin += 100;
2132                 }
2133                 cur_bin += inc[i];
2134                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2135                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2136         }
2137
2138         cur_vit_mask = 6100;
2139         upper = bin + 120;
2140         lower = bin - 120;
2141
2142         for (i = 0; i < 123; i++) {
2143                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2144
2145                         /* workaround for gcc bug #37014 */
2146                         volatile int tmp_v = abs(cur_vit_mask - bin);
2147
2148                         if (tmp_v < 75)
2149                                 mask_amt = 1;
2150                         else
2151                                 mask_amt = 0;
2152                         if (cur_vit_mask < 0)
2153                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2154                         else
2155                                 mask_p[cur_vit_mask / 100] = mask_amt;
2156                 }
2157                 cur_vit_mask -= 100;
2158         }
2159
2160         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2161                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2162                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2163                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2164                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2165                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2166                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2167                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2168         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2169         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2170
2171         tmp_mask = (mask_m[31] << 28)
2172                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2173                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2174                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2175                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2176                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2177                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2178                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2179         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2180         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2181
2182         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2183                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2184                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2185                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2186                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2187                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2188                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2189                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2190         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2191         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2192
2193         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2194                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2195                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2196                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2197                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2198                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2199                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2200                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2201         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2202         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2203
2204         tmp_mask = (mask_p[15] << 28)
2205                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2206                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2207                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2208                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2209                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2210                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2211                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2212         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2213         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2214
2215         tmp_mask = (mask_p[30] << 28)
2216                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2217                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2218                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2219                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2220                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2221                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2222                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2223         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2224         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2225
2226         tmp_mask = (mask_p[45] << 28)
2227                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2228                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2229                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2230                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2231                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2232                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2233                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2234         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2235         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2236
2237         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2238                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2239                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2240                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2241                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2242                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2243                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2244                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2245         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2246         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2247 }
2248
2249 static void ath9k_enable_rfkill(struct ath_hw *ah)
2250 {
2251         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2252                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2253
2254         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2255                     AR_GPIO_INPUT_MUX2_RFSILENT);
2256
2257         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2258         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2259 }
2260
2261 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2262                     bool bChannelChange)
2263 {
2264         u32 saveLedState;
2265         struct ath_softc *sc = ah->ah_sc;
2266         struct ath9k_channel *curchan = ah->curchan;
2267         u32 saveDefAntenna;
2268         u32 macStaId1;
2269         int i, rx_chainmask, r;
2270
2271         ah->extprotspacing = sc->ht_extprotspacing;
2272         ah->txchainmask = sc->tx_chainmask;
2273         ah->rxchainmask = sc->rx_chainmask;
2274
2275         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2276                 return -EIO;
2277
2278         if (curchan)
2279                 ath9k_hw_getnf(ah, curchan);
2280
2281         if (bChannelChange &&
2282             (ah->chip_fullsleep != true) &&
2283             (ah->curchan != NULL) &&
2284             (chan->channel != ah->curchan->channel) &&
2285             ((chan->channelFlags & CHANNEL_ALL) ==
2286              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2287             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2288                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2289
2290                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2291                         ath9k_hw_loadnf(ah, ah->curchan);
2292                         ath9k_hw_start_nfcal(ah);
2293                         return 0;
2294                 }
2295         }
2296
2297         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2298         if (saveDefAntenna == 0)
2299                 saveDefAntenna = 1;
2300
2301         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2302
2303         saveLedState = REG_READ(ah, AR_CFG_LED) &
2304                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2305                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2306
2307         ath9k_hw_mark_phy_inactive(ah);
2308
2309         if (!ath9k_hw_chip_reset(ah, chan)) {
2310                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2311                 return -EINVAL;
2312         }
2313
2314         if (AR_SREV_9280_10_OR_LATER(ah))
2315                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2316
2317         if (AR_SREV_9287_10_OR_LATER(ah)) {
2318                 /* Enable ASYNC FIFO */
2319                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2320                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2321                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2322                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2323                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2324                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2325                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2326         }
2327         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2328         if (r)
2329                 return r;
2330
2331         /* Setup MFP options for CCMP */
2332         if (AR_SREV_9280_20_OR_LATER(ah)) {
2333                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2334                  * frames when constructing CCMP AAD. */
2335                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2336                               0xc7ff);
2337                 ah->sw_mgmt_crypto = false;
2338         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2339                 /* Disable hardware crypto for management frames */
2340                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2341                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2342                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2343                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2344                 ah->sw_mgmt_crypto = true;
2345         } else
2346                 ah->sw_mgmt_crypto = true;
2347
2348         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2349                 ath9k_hw_set_delta_slope(ah, chan);
2350
2351         if (AR_SREV_9280_10_OR_LATER(ah))
2352                 ath9k_hw_9280_spur_mitigate(ah, chan);
2353         else
2354                 ath9k_hw_spur_mitigate(ah, chan);
2355
2356         ah->eep_ops->set_board_values(ah, chan);
2357
2358         ath9k_hw_decrease_chain_power(ah, chan);
2359
2360         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2361         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2362                   | macStaId1
2363                   | AR_STA_ID1_RTS_USE_DEF
2364                   | (ah->config.
2365                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2366                   | ah->sta_id1_defaults);
2367         ath9k_hw_set_operating_mode(ah, ah->opmode);
2368
2369         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2370         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2371
2372         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2373
2374         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2375         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2376                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2377
2378         REG_WRITE(ah, AR_ISR, ~0);
2379
2380         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2381
2382         if (AR_SREV_9280_10_OR_LATER(ah))
2383                 ath9k_hw_ar9280_set_channel(ah, chan);
2384         else
2385                 if (!(ath9k_hw_set_channel(ah, chan)))
2386                         return -EIO;
2387
2388         for (i = 0; i < AR_NUM_DCU; i++)
2389                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2390
2391         ah->intr_txqs = 0;
2392         for (i = 0; i < ah->caps.total_queues; i++)
2393                 ath9k_hw_resettxqueue(ah, i);
2394
2395         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2396         ath9k_hw_init_qos(ah);
2397
2398         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2399                 ath9k_enable_rfkill(ah);
2400
2401         ath9k_hw_init_user_settings(ah);
2402
2403         if (AR_SREV_9287_10_OR_LATER(ah)) {
2404                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2405                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2406                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2407                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2408                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2409                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2410
2411                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2412                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2413
2414                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2415                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2416                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2417                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2418         }
2419         if (AR_SREV_9287_10_OR_LATER(ah)) {
2420                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2421                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2422         }
2423
2424         REG_WRITE(ah, AR_STA_ID1,
2425                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2426
2427         ath9k_hw_set_dma(ah);
2428
2429         REG_WRITE(ah, AR_OBS, 8);
2430
2431         if (ah->config.intr_mitigation) {
2432                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2433                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2434         }
2435
2436         ath9k_hw_init_bb(ah, chan);
2437
2438         if (!ath9k_hw_init_cal(ah, chan))
2439                 return -EIO;
2440
2441         rx_chainmask = ah->rxchainmask;
2442         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2443                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2444                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2445         }
2446
2447         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2448
2449         if (AR_SREV_9100(ah)) {
2450                 u32 mask;
2451                 mask = REG_READ(ah, AR_CFG);
2452                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2453                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2454                                 "CFG Byte Swap Set 0x%x\n", mask);
2455                 } else {
2456                         mask =
2457                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2458                         REG_WRITE(ah, AR_CFG, mask);
2459                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2460                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2461                 }
2462         } else {
2463 #ifdef __BIG_ENDIAN
2464                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2465 #endif
2466         }
2467
2468         return 0;
2469 }
2470
2471 /************************/
2472 /* Key Cache Management */
2473 /************************/
2474
2475 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2476 {
2477         u32 keyType;
2478
2479         if (entry >= ah->caps.keycache_size) {
2480                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2481                         "keychache entry %u out of range\n", entry);
2482                 return false;
2483         }
2484
2485         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2486
2487         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2488         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2489         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2490         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2491         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2492         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2493         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2494         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2495
2496         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2497                 u16 micentry = entry + 64;
2498
2499                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2500                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2501                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2502                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2503
2504         }
2505
2506         if (ah->curchan == NULL)
2507                 return true;
2508
2509         return true;
2510 }
2511
2512 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2513 {
2514         u32 macHi, macLo;
2515
2516         if (entry >= ah->caps.keycache_size) {
2517                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2518                         "keychache entry %u out of range\n", entry);
2519                 return false;
2520         }
2521
2522         if (mac != NULL) {
2523                 macHi = (mac[5] << 8) | mac[4];
2524                 macLo = (mac[3] << 24) |
2525                         (mac[2] << 16) |
2526                         (mac[1] << 8) |
2527                         mac[0];
2528                 macLo >>= 1;
2529                 macLo |= (macHi & 1) << 31;
2530                 macHi >>= 1;
2531         } else {
2532                 macLo = macHi = 0;
2533         }
2534         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2535         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2536
2537         return true;
2538 }
2539
2540 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2541                                  const struct ath9k_keyval *k,
2542                                  const u8 *mac)
2543 {
2544         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2545         u32 key0, key1, key2, key3, key4;
2546         u32 keyType;
2547
2548         if (entry >= pCap->keycache_size) {
2549                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2550                         "keycache entry %u out of range\n", entry);
2551                 return false;
2552         }
2553
2554         switch (k->kv_type) {
2555         case ATH9K_CIPHER_AES_OCB:
2556                 keyType = AR_KEYTABLE_TYPE_AES;
2557                 break;
2558         case ATH9K_CIPHER_AES_CCM:
2559                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2560                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2561                                 "AES-CCM not supported by mac rev 0x%x\n",
2562                                 ah->hw_version.macRev);
2563                         return false;
2564                 }
2565                 keyType = AR_KEYTABLE_TYPE_CCM;
2566                 break;
2567         case ATH9K_CIPHER_TKIP:
2568                 keyType = AR_KEYTABLE_TYPE_TKIP;
2569                 if (ATH9K_IS_MIC_ENABLED(ah)
2570                     && entry + 64 >= pCap->keycache_size) {
2571                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2572                                 "entry %u inappropriate for TKIP\n", entry);
2573                         return false;
2574                 }
2575                 break;
2576         case ATH9K_CIPHER_WEP:
2577                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2578                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2579                                 "WEP key length %u too small\n", k->kv_len);
2580                         return false;
2581                 }
2582                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2583                         keyType = AR_KEYTABLE_TYPE_40;
2584                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2585                         keyType = AR_KEYTABLE_TYPE_104;
2586                 else
2587                         keyType = AR_KEYTABLE_TYPE_128;
2588                 break;
2589         case ATH9K_CIPHER_CLR:
2590                 keyType = AR_KEYTABLE_TYPE_CLR;
2591                 break;
2592         default:
2593                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2594                         "cipher %u not supported\n", k->kv_type);
2595                 return false;
2596         }
2597
2598         key0 = get_unaligned_le32(k->kv_val + 0);
2599         key1 = get_unaligned_le16(k->kv_val + 4);
2600         key2 = get_unaligned_le32(k->kv_val + 6);
2601         key3 = get_unaligned_le16(k->kv_val + 10);
2602         key4 = get_unaligned_le32(k->kv_val + 12);
2603         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2604                 key4 &= 0xff;
2605
2606         /*
2607          * Note: Key cache registers access special memory area that requires
2608          * two 32-bit writes to actually update the values in the internal
2609          * memory. Consequently, the exact order and pairs used here must be
2610          * maintained.
2611          */
2612
2613         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2614                 u16 micentry = entry + 64;
2615
2616                 /*
2617                  * Write inverted key[47:0] first to avoid Michael MIC errors
2618                  * on frames that could be sent or received at the same time.
2619                  * The correct key will be written in the end once everything
2620                  * else is ready.
2621                  */
2622                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2623                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2624
2625                 /* Write key[95:48] */
2626                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2627                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2628
2629                 /* Write key[127:96] and key type */
2630                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2631                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2632
2633                 /* Write MAC address for the entry */
2634                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2635
2636                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2637                         /*
2638                          * TKIP uses two key cache entries:
2639                          * Michael MIC TX/RX keys in the same key cache entry
2640                          * (idx = main index + 64):
2641                          * key0 [31:0] = RX key [31:0]
2642                          * key1 [15:0] = TX key [31:16]
2643                          * key1 [31:16] = reserved
2644                          * key2 [31:0] = RX key [63:32]
2645                          * key3 [15:0] = TX key [15:0]
2646                          * key3 [31:16] = reserved
2647                          * key4 [31:0] = TX key [63:32]
2648                          */
2649                         u32 mic0, mic1, mic2, mic3, mic4;
2650
2651                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2652                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2653                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2654                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2655                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2656
2657                         /* Write RX[31:0] and TX[31:16] */
2658                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2659                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2660
2661                         /* Write RX[63:32] and TX[15:0] */
2662                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2663                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2664
2665                         /* Write TX[63:32] and keyType(reserved) */
2666                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2667                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2668                                   AR_KEYTABLE_TYPE_CLR);
2669
2670                 } else {
2671                         /*
2672                          * TKIP uses four key cache entries (two for group
2673                          * keys):
2674                          * Michael MIC TX/RX keys are in different key cache
2675                          * entries (idx = main index + 64 for TX and
2676                          * main index + 32 + 96 for RX):
2677                          * key0 [31:0] = TX/RX MIC key [31:0]
2678                          * key1 [31:0] = reserved
2679                          * key2 [31:0] = TX/RX MIC key [63:32]
2680                          * key3 [31:0] = reserved
2681                          * key4 [31:0] = reserved
2682                          *
2683                          * Upper layer code will call this function separately
2684                          * for TX and RX keys when these registers offsets are
2685                          * used.
2686                          */
2687                         u32 mic0, mic2;
2688
2689                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2690                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2691
2692                         /* Write MIC key[31:0] */
2693                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2694                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2695
2696                         /* Write MIC key[63:32] */
2697                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2698                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2699
2700                         /* Write TX[63:32] and keyType(reserved) */
2701                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2702                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2703                                   AR_KEYTABLE_TYPE_CLR);
2704                 }
2705
2706                 /* MAC address registers are reserved for the MIC entry */
2707                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2708                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2709
2710                 /*
2711                  * Write the correct (un-inverted) key[47:0] last to enable
2712                  * TKIP now that all other registers are set with correct
2713                  * values.
2714                  */
2715                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2716                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2717         } else {
2718                 /* Write key[47:0] */
2719                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2720                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2721
2722                 /* Write key[95:48] */
2723                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2724                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2725
2726                 /* Write key[127:96] and key type */
2727                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2728                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2729
2730                 /* Write MAC address for the entry */
2731                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2732         }
2733
2734         return true;
2735 }
2736
2737 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2738 {
2739         if (entry < ah->caps.keycache_size) {
2740                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2741                 if (val & AR_KEYTABLE_VALID)
2742                         return true;
2743         }
2744         return false;
2745 }
2746
2747 /******************************/
2748 /* Power Management (Chipset) */
2749 /******************************/
2750
2751 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2752 {
2753         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2754         if (setChip) {
2755                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2756                             AR_RTC_FORCE_WAKE_EN);
2757                 if (!AR_SREV_9100(ah))
2758                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2759
2760                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2761                             AR_RTC_RESET_EN);
2762         }
2763 }
2764
2765 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2766 {
2767         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2768         if (setChip) {
2769                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2770
2771                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2772                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2773                                   AR_RTC_FORCE_WAKE_ON_INT);
2774                 } else {
2775                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2776                                     AR_RTC_FORCE_WAKE_EN);
2777                 }
2778         }
2779 }
2780
2781 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2782 {
2783         u32 val;
2784         int i;
2785
2786         if (setChip) {
2787                 if ((REG_READ(ah, AR_RTC_STATUS) &
2788                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2789                         if (ath9k_hw_set_reset_reg(ah,
2790                                            ATH9K_RESET_POWER_ON) != true) {
2791                                 return false;
2792                         }
2793                 }
2794                 if (AR_SREV_9100(ah))
2795                         REG_SET_BIT(ah, AR_RTC_RESET,
2796                                     AR_RTC_RESET_EN);
2797
2798                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2799                             AR_RTC_FORCE_WAKE_EN);
2800                 udelay(50);
2801
2802                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2803                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2804                         if (val == AR_RTC_STATUS_ON)
2805                                 break;
2806                         udelay(50);
2807                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2808                                     AR_RTC_FORCE_WAKE_EN);
2809                 }
2810                 if (i == 0) {
2811                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2812                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2813                         return false;
2814                 }
2815         }
2816
2817         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2818
2819         return true;
2820 }
2821
2822 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2823                                      enum ath9k_power_mode mode)
2824 {
2825         int status = true, setChip = true;
2826         static const char *modes[] = {
2827                 "AWAKE",
2828                 "FULL-SLEEP",
2829                 "NETWORK SLEEP",
2830                 "UNDEFINED"
2831         };
2832
2833         if (ah->power_mode == mode)
2834                 return status;
2835
2836         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2837                 modes[ah->power_mode], modes[mode]);
2838
2839         switch (mode) {
2840         case ATH9K_PM_AWAKE:
2841                 status = ath9k_hw_set_power_awake(ah, setChip);
2842                 break;
2843         case ATH9K_PM_FULL_SLEEP:
2844                 ath9k_set_power_sleep(ah, setChip);
2845                 ah->chip_fullsleep = true;
2846                 break;
2847         case ATH9K_PM_NETWORK_SLEEP:
2848                 ath9k_set_power_network_sleep(ah, setChip);
2849                 break;
2850         default:
2851                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2852                         "Unknown power mode %u\n", mode);
2853                 return false;
2854         }
2855         ah->power_mode = mode;
2856
2857         return status;
2858 }
2859
2860 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2861 {
2862         unsigned long flags;
2863         bool ret;
2864
2865         spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2866         ret = ath9k_hw_setpower_nolock(ah, mode);
2867         spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2868
2869         return ret;
2870 }
2871
2872 void ath9k_ps_wakeup(struct ath_softc *sc)
2873 {
2874         unsigned long flags;
2875
2876         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2877         if (++sc->ps_usecount != 1)
2878                 goto unlock;
2879
2880         ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2881
2882  unlock:
2883         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2884 }
2885
2886 void ath9k_ps_restore(struct ath_softc *sc)
2887 {
2888         unsigned long flags;
2889
2890         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2891         if (--sc->ps_usecount != 0)
2892                 goto unlock;
2893
2894         if (sc->ps_enabled &&
2895             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2896                               SC_OP_WAIT_FOR_CAB |
2897                               SC_OP_WAIT_FOR_PSPOLL_DATA |
2898                               SC_OP_WAIT_FOR_TX_ACK)))
2899                 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2900
2901  unlock:
2902         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2903 }
2904
2905 /*
2906  * Helper for ASPM support.
2907  *
2908  * Disable PLL when in L0s as well as receiver clock when in L1.
2909  * This power saving option must be enabled through the SerDes.
2910  *
2911  * Programming the SerDes must go through the same 288 bit serial shift
2912  * register as the other analog registers.  Hence the 9 writes.
2913  */
2914 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2915 {
2916         u8 i;
2917
2918         if (ah->is_pciexpress != true)
2919                 return;
2920
2921         /* Do not touch SerDes registers */
2922         if (ah->config.pcie_powersave_enable == 2)
2923                 return;
2924
2925         /* Nothing to do on restore for 11N */
2926         if (restore)
2927                 return;
2928
2929         if (AR_SREV_9280_20_OR_LATER(ah)) {
2930                 /*
2931                  * AR9280 2.0 or later chips use SerDes values from the
2932                  * initvals.h initialized depending on chipset during
2933                  * ath9k_hw_attach()
2934                  */
2935                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2936                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2937                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2938                 }
2939         } else if (AR_SREV_9280(ah) &&
2940                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2941                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2942                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2943
2944                 /* RX shut off when elecidle is asserted */
2945                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2946                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2947                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2948
2949                 /* Shut off CLKREQ active in L1 */
2950                 if (ah->config.pcie_clock_req)
2951                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2952                 else
2953                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2954
2955                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2956                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2957                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2958
2959                 /* Load the new settings */
2960                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2961
2962         } else {
2963                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2964                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2965
2966                 /* RX shut off when elecidle is asserted */
2967                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2968                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2969                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2970
2971                 /*
2972                  * Ignore ah->ah_config.pcie_clock_req setting for
2973                  * pre-AR9280 11n
2974                  */
2975                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2976
2977                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2978                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2979                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2980
2981                 /* Load the new settings */
2982                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2983         }
2984
2985         udelay(1000);
2986
2987         /* set bit 19 to allow forcing of pcie core into L1 state */
2988         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2989
2990         /* Several PCIe massages to ensure proper behaviour */
2991         if (ah->config.pcie_waen) {
2992                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2993         } else {
2994                 if (AR_SREV_9285(ah))
2995                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2996                 /*
2997                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2998                  * otherwise card may disappear.
2999                  */
3000                 else if (AR_SREV_9280(ah))
3001                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
3002                 else
3003                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
3004         }
3005 }
3006
3007 /**********************/
3008 /* Interrupt Handling */
3009 /**********************/
3010
3011 bool ath9k_hw_intrpend(struct ath_hw *ah)
3012 {
3013         u32 host_isr;
3014
3015         if (AR_SREV_9100(ah))
3016                 return true;
3017
3018         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3019         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3020                 return true;
3021
3022         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3023         if ((host_isr & AR_INTR_SYNC_DEFAULT)
3024             && (host_isr != AR_INTR_SPURIOUS))
3025                 return true;
3026
3027         return false;
3028 }
3029
3030 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3031 {
3032         u32 isr = 0;
3033         u32 mask2 = 0;
3034         struct ath9k_hw_capabilities *pCap = &ah->caps;
3035         u32 sync_cause = 0;
3036         bool fatal_int = false;
3037
3038         if (!AR_SREV_9100(ah)) {
3039                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3040                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3041                             == AR_RTC_STATUS_ON) {
3042                                 isr = REG_READ(ah, AR_ISR);
3043                         }
3044                 }
3045
3046                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3047                         AR_INTR_SYNC_DEFAULT;
3048
3049                 *masked = 0;
3050
3051                 if (!isr && !sync_cause)
3052                         return false;
3053         } else {
3054                 *masked = 0;
3055                 isr = REG_READ(ah, AR_ISR);
3056         }
3057
3058         if (isr) {
3059                 if (isr & AR_ISR_BCNMISC) {
3060                         u32 isr2;
3061                         isr2 = REG_READ(ah, AR_ISR_S2);
3062                         if (isr2 & AR_ISR_S2_TIM)
3063                                 mask2 |= ATH9K_INT_TIM;
3064                         if (isr2 & AR_ISR_S2_DTIM)
3065                                 mask2 |= ATH9K_INT_DTIM;
3066                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3067                                 mask2 |= ATH9K_INT_DTIMSYNC;
3068                         if (isr2 & (AR_ISR_S2_CABEND))
3069                                 mask2 |= ATH9K_INT_CABEND;
3070                         if (isr2 & AR_ISR_S2_GTT)
3071                                 mask2 |= ATH9K_INT_GTT;
3072                         if (isr2 & AR_ISR_S2_CST)
3073                                 mask2 |= ATH9K_INT_CST;
3074                         if (isr2 & AR_ISR_S2_TSFOOR)
3075                                 mask2 |= ATH9K_INT_TSFOOR;
3076                 }
3077
3078                 isr = REG_READ(ah, AR_ISR_RAC);
3079                 if (isr == 0xffffffff) {
3080                         *masked = 0;
3081                         return false;
3082                 }
3083
3084                 *masked = isr & ATH9K_INT_COMMON;
3085
3086                 if (ah->config.intr_mitigation) {
3087                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3088                                 *masked |= ATH9K_INT_RX;
3089                 }
3090
3091                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3092                         *masked |= ATH9K_INT_RX;
3093                 if (isr &
3094                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3095                      AR_ISR_TXEOL)) {
3096                         u32 s0_s, s1_s;
3097
3098                         *masked |= ATH9K_INT_TX;
3099
3100                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3101                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3102                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3103
3104                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3105                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3106                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3107                 }
3108
3109                 if (isr & AR_ISR_RXORN) {
3110                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3111                                 "receive FIFO overrun interrupt\n");
3112                 }
3113
3114                 if (!AR_SREV_9100(ah)) {
3115                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3116                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3117                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3118                                         *masked |= ATH9K_INT_TIM_TIMER;
3119                         }
3120                 }
3121
3122                 *masked |= mask2;
3123         }
3124
3125         if (AR_SREV_9100(ah))
3126                 return true;
3127
3128         if (sync_cause) {
3129                 fatal_int =
3130                         (sync_cause &
3131                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3132                         ? true : false;
3133
3134                 if (fatal_int) {
3135                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3136                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3137                                         "received PCI FATAL interrupt\n");
3138                         }
3139                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3140                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3141                                         "received PCI PERR interrupt\n");
3142                         }
3143                         *masked |= ATH9K_INT_FATAL;
3144                 }
3145                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3146                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3147                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3148                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3149                         REG_WRITE(ah, AR_RC, 0);
3150                         *masked |= ATH9K_INT_FATAL;
3151                 }
3152                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3153                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3154                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3155                 }
3156
3157                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3158                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3159         }
3160
3161         return true;
3162 }
3163
3164 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3165 {
3166         u32 omask = ah->mask_reg;
3167         u32 mask, mask2;
3168         struct ath9k_hw_capabilities *pCap = &ah->caps;
3169
3170         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3171
3172         if (omask & ATH9K_INT_GLOBAL) {
3173                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3174                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3175                 (void) REG_READ(ah, AR_IER);
3176                 if (!AR_SREV_9100(ah)) {
3177                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3178                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3179
3180                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3181                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3182                 }
3183         }
3184
3185         mask = ints & ATH9K_INT_COMMON;
3186         mask2 = 0;
3187
3188         if (ints & ATH9K_INT_TX) {
3189                 if (ah->txok_interrupt_mask)
3190                         mask |= AR_IMR_TXOK;
3191                 if (ah->txdesc_interrupt_mask)
3192                         mask |= AR_IMR_TXDESC;
3193                 if (ah->txerr_interrupt_mask)
3194                         mask |= AR_IMR_TXERR;
3195                 if (ah->txeol_interrupt_mask)
3196                         mask |= AR_IMR_TXEOL;
3197         }
3198         if (ints & ATH9K_INT_RX) {
3199                 mask |= AR_IMR_RXERR;
3200                 if (ah->config.intr_mitigation)
3201                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3202                 else
3203                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3204                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3205                         mask |= AR_IMR_GENTMR;
3206         }
3207
3208         if (ints & (ATH9K_INT_BMISC)) {
3209                 mask |= AR_IMR_BCNMISC;
3210                 if (ints & ATH9K_INT_TIM)
3211                         mask2 |= AR_IMR_S2_TIM;
3212                 if (ints & ATH9K_INT_DTIM)
3213                         mask2 |= AR_IMR_S2_DTIM;
3214                 if (ints & ATH9K_INT_DTIMSYNC)
3215                         mask2 |= AR_IMR_S2_DTIMSYNC;
3216                 if (ints & ATH9K_INT_CABEND)
3217                         mask2 |= AR_IMR_S2_CABEND;
3218                 if (ints & ATH9K_INT_TSFOOR)
3219                         mask2 |= AR_IMR_S2_TSFOOR;
3220         }
3221
3222         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3223                 mask |= AR_IMR_BCNMISC;
3224                 if (ints & ATH9K_INT_GTT)
3225                         mask2 |= AR_IMR_S2_GTT;
3226                 if (ints & ATH9K_INT_CST)
3227                         mask2 |= AR_IMR_S2_CST;
3228         }
3229
3230         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3231         REG_WRITE(ah, AR_IMR, mask);
3232         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3233                                            AR_IMR_S2_DTIM |
3234                                            AR_IMR_S2_DTIMSYNC |
3235                                            AR_IMR_S2_CABEND |
3236                                            AR_IMR_S2_CABTO |
3237                                            AR_IMR_S2_TSFOOR |
3238                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3239         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3240         ah->mask_reg = ints;
3241
3242         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3243                 if (ints & ATH9K_INT_TIM_TIMER)
3244                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3245                 else
3246                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3247         }
3248
3249         if (ints & ATH9K_INT_GLOBAL) {
3250                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3251                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3252                 if (!AR_SREV_9100(ah)) {
3253                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3254                                   AR_INTR_MAC_IRQ);
3255                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3256
3257
3258                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3259                                   AR_INTR_SYNC_DEFAULT);
3260                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3261                                   AR_INTR_SYNC_DEFAULT);
3262                 }
3263                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3264                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3265         }
3266
3267         return omask;
3268 }
3269
3270 /*******************/
3271 /* Beacon Handling */
3272 /*******************/
3273
3274 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3275 {
3276         int flags = 0;
3277
3278         ah->beacon_interval = beacon_period;
3279
3280         switch (ah->opmode) {
3281         case NL80211_IFTYPE_STATION:
3282         case NL80211_IFTYPE_MONITOR:
3283                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3284                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3285                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3286                 flags |= AR_TBTT_TIMER_EN;
3287                 break;
3288         case NL80211_IFTYPE_ADHOC:
3289         case NL80211_IFTYPE_MESH_POINT:
3290                 REG_SET_BIT(ah, AR_TXCFG,
3291                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3292                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3293                           TU_TO_USEC(next_beacon +
3294                                      (ah->atim_window ? ah->
3295                                       atim_window : 1)));
3296                 flags |= AR_NDP_TIMER_EN;
3297         case NL80211_IFTYPE_AP:
3298                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3299                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3300                           TU_TO_USEC(next_beacon -
3301                                      ah->config.
3302                                      dma_beacon_response_time));
3303                 REG_WRITE(ah, AR_NEXT_SWBA,
3304                           TU_TO_USEC(next_beacon -
3305                                      ah->config.
3306                                      sw_beacon_response_time));
3307                 flags |=
3308                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3309                 break;
3310         default:
3311                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3312                         "%s: unsupported opmode: %d\n",
3313                         __func__, ah->opmode);
3314                 return;
3315                 break;
3316         }
3317
3318         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3319         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3320         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3321         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3322
3323         beacon_period &= ~ATH9K_BEACON_ENA;
3324         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3325                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3326                 ath9k_hw_reset_tsf(ah);
3327         }
3328
3329         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3330 }
3331
3332 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3333                                     const struct ath9k_beacon_state *bs)
3334 {
3335         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3336         struct ath9k_hw_capabilities *pCap = &ah->caps;
3337
3338         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3339
3340         REG_WRITE(ah, AR_BEACON_PERIOD,
3341                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3342         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3343                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3344
3345         REG_RMW_FIELD(ah, AR_RSSI_THR,
3346                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3347
3348         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3349
3350         if (bs->bs_sleepduration > beaconintval)
3351                 beaconintval = bs->bs_sleepduration;
3352
3353         dtimperiod = bs->bs_dtimperiod;
3354         if (bs->bs_sleepduration > dtimperiod)
3355                 dtimperiod = bs->bs_sleepduration;
3356
3357         if (beaconintval == dtimperiod)
3358                 nextTbtt = bs->bs_nextdtim;
3359         else
3360                 nextTbtt = bs->bs_nexttbtt;
3361
3362         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3363         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3364         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3365         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3366
3367         REG_WRITE(ah, AR_NEXT_DTIM,
3368                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3369         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3370
3371         REG_WRITE(ah, AR_SLEEP1,
3372                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3373                   | AR_SLEEP1_ASSUME_DTIM);
3374
3375         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3376                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3377         else
3378                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3379
3380         REG_WRITE(ah, AR_SLEEP2,
3381                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3382
3383         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3384         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3385
3386         REG_SET_BIT(ah, AR_TIMER_MODE,
3387                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3388                     AR_DTIM_TIMER_EN);
3389
3390         /* TSF Out of Range Threshold */
3391         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3392 }
3393
3394 /*******************/
3395 /* HW Capabilities */
3396 /*******************/
3397
3398 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3399 {
3400         struct ath9k_hw_capabilities *pCap = &ah->caps;
3401         u16 capField = 0, eeval;
3402
3403         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3404         ah->regulatory.current_rd = eeval;
3405
3406         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3407         if (AR_SREV_9285_10_OR_LATER(ah))
3408                 eeval |= AR9285_RDEXT_DEFAULT;
3409         ah->regulatory.current_rd_ext = eeval;
3410
3411         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3412
3413         if (ah->opmode != NL80211_IFTYPE_AP &&
3414             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3415                 if (ah->regulatory.current_rd == 0x64 ||
3416                     ah->regulatory.current_rd == 0x65)
3417                         ah->regulatory.current_rd += 5;
3418                 else if (ah->regulatory.current_rd == 0x41)
3419                         ah->regulatory.current_rd = 0x43;
3420                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3421                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3422         }
3423
3424         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3425         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3426
3427         if (eeval & AR5416_OPFLAGS_11A) {
3428                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3429                 if (ah->config.ht_enable) {
3430                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3431                                 set_bit(ATH9K_MODE_11NA_HT20,
3432                                         pCap->wireless_modes);
3433                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3434                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3435                                         pCap->wireless_modes);
3436                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3437                                         pCap->wireless_modes);
3438                         }
3439                 }
3440         }
3441
3442         if (eeval & AR5416_OPFLAGS_11G) {
3443                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3444                 if (ah->config.ht_enable) {
3445                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3446                                 set_bit(ATH9K_MODE_11NG_HT20,
3447                                         pCap->wireless_modes);
3448                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3449                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3450                                         pCap->wireless_modes);
3451                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3452                                         pCap->wireless_modes);
3453                         }
3454                 }
3455         }
3456
3457         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3458         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3459             !(eeval & AR5416_OPFLAGS_11A))
3460                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3461         else
3462                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3463
3464         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3465                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3466
3467         pCap->low_2ghz_chan = 2312;
3468         pCap->high_2ghz_chan = 2732;
3469
3470         pCap->low_5ghz_chan = 4920;
3471         pCap->high_5ghz_chan = 6100;
3472
3473         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3474         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3475         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3476
3477         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3478         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3479         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3480
3481         if (ah->config.ht_enable)
3482                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3483         else
3484                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3485
3486         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3487         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3488         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3489         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3490
3491         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3492                 pCap->total_queues =
3493                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3494         else
3495                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3496
3497         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3498                 pCap->keycache_size =
3499                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3500         else
3501                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3502
3503         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3504         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3505
3506         if (AR_SREV_9285_10_OR_LATER(ah))
3507                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3508         else if (AR_SREV_9280_10_OR_LATER(ah))
3509                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3510         else
3511                 pCap->num_gpio_pins = AR_NUM_GPIO;
3512
3513         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3514                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3515                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3516         } else {
3517                 pCap->rts_aggr_limit = (8 * 1024);
3518         }
3519
3520         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3521
3522 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3523         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3524         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3525                 ah->rfkill_gpio =
3526                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3527                 ah->rfkill_polarity =
3528                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3529
3530                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3531         }
3532 #endif
3533
3534         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3535             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3536             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3537             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3538             (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3539             (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3540                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3541         else
3542                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3543
3544         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3545                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3546         else
3547                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3548
3549         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3550                 pCap->reg_cap =
3551                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3552                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3553                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3554                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3555         } else {
3556                 pCap->reg_cap =
3557                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3558                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3559         }
3560
3561         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3562
3563         pCap->num_antcfg_5ghz =
3564                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3565         pCap->num_antcfg_2ghz =
3566                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3567
3568         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3569                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3570                 ah->btactive_gpio = 6;
3571                 ah->wlanactive_gpio = 5;
3572         }
3573 }
3574
3575 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3576                             u32 capability, u32 *result)
3577 {
3578         switch (type) {
3579         case ATH9K_CAP_CIPHER:
3580                 switch (capability) {
3581                 case ATH9K_CIPHER_AES_CCM:
3582                 case ATH9K_CIPHER_AES_OCB:
3583                 case ATH9K_CIPHER_TKIP:
3584                 case ATH9K_CIPHER_WEP:
3585                 case ATH9K_CIPHER_MIC:
3586                 case ATH9K_CIPHER_CLR:
3587                         return true;
3588                 default:
3589                         return false;
3590                 }
3591         case ATH9K_CAP_TKIP_MIC:
3592                 switch (capability) {
3593                 case 0:
3594                         return true;
3595                 case 1:
3596                         return (ah->sta_id1_defaults &
3597                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3598                         false;
3599                 }
3600         case ATH9K_CAP_TKIP_SPLIT:
3601                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3602                         false : true;
3603         case ATH9K_CAP_DIVERSITY:
3604                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3605                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3606                         true : false;
3607         case ATH9K_CAP_MCAST_KEYSRCH:
3608                 switch (capability) {
3609                 case 0:
3610                         return true;
3611                 case 1:
3612                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3613                                 return false;
3614                         } else {
3615                                 return (ah->sta_id1_defaults &
3616                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3617                                         false;
3618                         }
3619                 }
3620                 return false;
3621         case ATH9K_CAP_TXPOW:
3622                 switch (capability) {
3623                 case 0:
3624                         return 0;
3625                 case 1:
3626                         *result = ah->regulatory.power_limit;
3627                         return 0;
3628                 case 2:
3629                         *result = ah->regulatory.max_power_level;
3630                         return 0;
3631                 case 3:
3632                         *result = ah->regulatory.tp_scale;
3633                         return 0;
3634                 }
3635                 return false;
3636         case ATH9K_CAP_DS:
3637                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3638                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3639                         ? false : true;
3640         default:
3641                 return false;
3642         }
3643 }
3644
3645 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3646                             u32 capability, u32 setting, int *status)
3647 {
3648         u32 v;
3649
3650         switch (type) {
3651         case ATH9K_CAP_TKIP_MIC:
3652                 if (setting)
3653                         ah->sta_id1_defaults |=
3654                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3655                 else
3656                         ah->sta_id1_defaults &=
3657                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3658                 return true;
3659         case ATH9K_CAP_DIVERSITY:
3660                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3661                 if (setting)
3662                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3663                 else
3664                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3665                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3666                 return true;
3667         case ATH9K_CAP_MCAST_KEYSRCH:
3668                 if (setting)
3669                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3670                 else
3671                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3672                 return true;
3673         default:
3674                 return false;
3675         }
3676 }
3677
3678 /****************************/
3679 /* GPIO / RFKILL / Antennae */
3680 /****************************/
3681
3682 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3683                                          u32 gpio, u32 type)
3684 {
3685         int addr;
3686         u32 gpio_shift, tmp;
3687
3688         if (gpio > 11)
3689                 addr = AR_GPIO_OUTPUT_MUX3;
3690         else if (gpio > 5)
3691                 addr = AR_GPIO_OUTPUT_MUX2;
3692         else
3693                 addr = AR_GPIO_OUTPUT_MUX1;
3694
3695         gpio_shift = (gpio % 6) * 5;
3696
3697         if (AR_SREV_9280_20_OR_LATER(ah)
3698             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3699                 REG_RMW(ah, addr, (type << gpio_shift),
3700                         (0x1f << gpio_shift));
3701         } else {
3702                 tmp = REG_READ(ah, addr);
3703                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3704                 tmp &= ~(0x1f << gpio_shift);
3705                 tmp |= (type << gpio_shift);
3706                 REG_WRITE(ah, addr, tmp);
3707         }
3708 }
3709
3710 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3711 {
3712         u32 gpio_shift;
3713
3714         ASSERT(gpio < ah->caps.num_gpio_pins);
3715
3716         gpio_shift = gpio << 1;
3717
3718         REG_RMW(ah,
3719                 AR_GPIO_OE_OUT,
3720                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3721                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3722 }
3723
3724 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3725 {
3726 #define MS_REG_READ(x, y) \
3727         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3728
3729         if (gpio >= ah->caps.num_gpio_pins)
3730                 return 0xffffffff;
3731
3732         if (AR_SREV_9287_10_OR_LATER(ah))
3733                 return MS_REG_READ(AR9287, gpio) != 0;
3734         else if (AR_SREV_9285_10_OR_LATER(ah))
3735                 return MS_REG_READ(AR9285, gpio) != 0;
3736         else if (AR_SREV_9280_10_OR_LATER(ah))
3737                 return MS_REG_READ(AR928X, gpio) != 0;
3738         else
3739                 return MS_REG_READ(AR, gpio) != 0;
3740 }
3741
3742 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3743                          u32 ah_signal_type)
3744 {
3745         u32 gpio_shift;
3746
3747         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3748
3749         gpio_shift = 2 * gpio;
3750
3751         REG_RMW(ah,
3752                 AR_GPIO_OE_OUT,
3753                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3754                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3755 }
3756
3757 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3758 {
3759         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3760                 AR_GPIO_BIT(gpio));
3761 }
3762
3763 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3764 {
3765         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3766 }
3767
3768 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3769 {
3770         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3771 }
3772
3773 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3774                                enum ath9k_ant_setting settings,
3775                                struct ath9k_channel *chan,
3776                                u8 *tx_chainmask,
3777                                u8 *rx_chainmask,
3778                                u8 *antenna_cfgd)
3779 {
3780         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3781
3782         if (AR_SREV_9280(ah)) {
3783                 if (!tx_chainmask_cfg) {
3784
3785                         tx_chainmask_cfg = *tx_chainmask;
3786                         rx_chainmask_cfg = *rx_chainmask;
3787                 }
3788
3789                 switch (settings) {
3790                 case ATH9K_ANT_FIXED_A:
3791                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3792                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3793                         *antenna_cfgd = true;
3794                         break;
3795                 case ATH9K_ANT_FIXED_B:
3796                         if (ah->caps.tx_chainmask >
3797                             ATH9K_ANTENNA1_CHAINMASK) {
3798                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3799                         }
3800                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3801                         *antenna_cfgd = true;
3802                         break;
3803                 case ATH9K_ANT_VARIABLE:
3804                         *tx_chainmask = tx_chainmask_cfg;
3805                         *rx_chainmask = rx_chainmask_cfg;
3806                         *antenna_cfgd = true;
3807                         break;
3808                 default:
3809                         break;
3810                 }
3811         } else {
3812                 ah->diversity_control = settings;
3813         }
3814
3815         return true;
3816 }
3817
3818 /*********************/
3819 /* General Operation */
3820 /*********************/
3821
3822 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3823 {
3824         u32 bits = REG_READ(ah, AR_RX_FILTER);
3825         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3826
3827         if (phybits & AR_PHY_ERR_RADAR)
3828                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3829         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3830                 bits |= ATH9K_RX_FILTER_PHYERR;
3831
3832         return bits;
3833 }
3834
3835 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3836 {
3837         u32 phybits;
3838
3839         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3840         phybits = 0;
3841         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3842                 phybits |= AR_PHY_ERR_RADAR;
3843         if (bits & ATH9K_RX_FILTER_PHYERR)
3844                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3845         REG_WRITE(ah, AR_PHY_ERR, phybits);
3846
3847         if (phybits)
3848                 REG_WRITE(ah, AR_RXCFG,
3849                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3850         else
3851                 REG_WRITE(ah, AR_RXCFG,
3852                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3853 }
3854
3855 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3856 {
3857         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3858 }
3859
3860 bool ath9k_hw_disable(struct ath_hw *ah)
3861 {
3862         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3863                 return false;
3864
3865         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3866 }
3867
3868 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3869 {
3870         struct ath9k_channel *chan = ah->curchan;
3871         struct ieee80211_channel *channel = chan->chan;
3872
3873         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3874
3875         ah->eep_ops->set_txpower(ah, chan,
3876                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
3877                                  channel->max_antenna_gain * 2,
3878                                  channel->max_power * 2,
3879                                  min((u32) MAX_RATE_POWER,
3880                                  (u32) ah->regulatory.power_limit));
3881 }
3882
3883 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3884 {
3885         memcpy(ah->macaddr, mac, ETH_ALEN);
3886 }
3887
3888 void ath9k_hw_setopmode(struct ath_hw *ah)
3889 {
3890         ath9k_hw_set_operating_mode(ah, ah->opmode);
3891 }
3892
3893 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3894 {
3895         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3896         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3897 }
3898
3899 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3900 {
3901         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3902         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3903 }
3904
3905 void ath9k_hw_write_associd(struct ath_softc *sc)
3906 {
3907         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3908         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3909                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3910 }
3911
3912 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3913 {
3914         u64 tsf;
3915
3916         tsf = REG_READ(ah, AR_TSF_U32);
3917         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3918
3919         return tsf;
3920 }
3921
3922 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3923 {
3924         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3925         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3926 }
3927
3928 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3929 {
3930         ath9k_ps_wakeup(ah->ah_sc);
3931         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3932                            AH_TSF_WRITE_TIMEOUT))
3933                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3934                         "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3935
3936         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3937         ath9k_ps_restore(ah->ah_sc);
3938 }
3939
3940 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3941 {
3942         if (setting)
3943                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3944         else
3945                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3946
3947         return true;
3948 }
3949
3950 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3951 {
3952         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3953                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3954                 ah->slottime = (u32) -1;
3955                 return false;
3956         } else {
3957                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3958                 ah->slottime = us;
3959                 return true;
3960         }
3961 }
3962
3963 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3964 {
3965         u32 macmode;
3966
3967         if (mode == ATH9K_HT_MACMODE_2040 &&
3968             !ah->config.cwm_ignore_extcca)
3969                 macmode = AR_2040_JOINED_RX_CLEAR;
3970         else
3971                 macmode = 0;
3972
3973         REG_WRITE(ah, AR_2040_MODE, macmode);
3974 }
3975
3976 /***************************/
3977 /*  Bluetooth Coexistence  */
3978 /***************************/
3979
3980 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3981 {
3982         /* connect bt_active to baseband */
3983         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3984                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3985                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3986
3987         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3988                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3989
3990         /* Set input mux for bt_active to gpio pin */
3991         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3992                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3993                         ah->btactive_gpio);
3994
3995         /* Configure the desired gpio port for input */
3996         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3997
3998         /* Configure the desired GPIO port for TX_FRAME output */
3999         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
4000                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
4001 }